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net: phy: dp83822: Fix RGMII TX delay configuration

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[ Upstream commit c8a5c731fd1223090af57da33838c671a7fc6a78 ]

The logic for enabling the TX clock shift is inverse of enabling the RX
clock shift. The TX clock shift is disabled when DP83822_TX_CLK_SHIFT is
set. Correct the current behavior and always write the delay configuration
to ensure consistent delay settings regardless of bootloader configuration.

Reference: https://www.ti.com/lit/ds/symlink/dp83822i.pdf p. 69

Fixes: 8095295292 ("net: phy: DP83822: Add setting the fixed internal delay")
Signed-off-by: Tim Pambor <tp@osasysteme.de>
Link: https://lore.kernel.org/r/20240305110608.104072-1-tp@osasysteme.de
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Tim Pambor
2024-03-05 12:06:08 +01:00
committed by Sasha Levin
parent 262a77d85e
commit 877cce250a
1 changed files with 20 additions and 17 deletions
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37
drivers/net/phy/dp83822.c
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@@ -380,7 +380,7 @@ static int dp83822_config_init(struct phy_device *phydev)
{ {
struct dp83822_private *dp83822 = phydev->priv; struct dp83822_private *dp83822 = phydev->priv;
struct device *dev = &phydev->mdio.dev; struct device *dev = &phydev->mdio.dev;
int rgmii_delay; int rgmii_delay = 0;
s32 rx_int_delay; s32 rx_int_delay;
s32 tx_int_delay; s32 tx_int_delay;
int err = 0; int err = 0;
@@ -390,30 +390,33 @@ static int dp83822_config_init(struct phy_device *phydev)
rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,
true); true);
if (rx_int_delay <= 0) /* Set DP83822_RX_CLK_SHIFT to enable rx clk internal delay */
rgmii_delay = 0; if (rx_int_delay > 0)
else rgmii_delay |= DP83822_RX_CLK_SHIFT;
rgmii_delay = DP83822_RX_CLK_SHIFT;
tx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, tx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,
false); false);
/* Set DP83822_TX_CLK_SHIFT to disable tx clk internal delay */
if (tx_int_delay <= 0) if (tx_int_delay <= 0)
rgmii_delay &= ~DP83822_TX_CLK_SHIFT;
else
rgmii_delay |= DP83822_TX_CLK_SHIFT; rgmii_delay |= DP83822_TX_CLK_SHIFT;
if (rgmii_delay) { err = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR,
err = phy_set_bits_mmd(phydev, DP83822_DEVADDR, DP83822_RX_CLK_SHIFT | DP83822_TX_CLK_SHIFT, rgmii_delay);
MII_DP83822_RCSR, rgmii_delay); if (err)
if (err) return err;
return err;
}
phy_set_bits_mmd(phydev, DP83822_DEVADDR, err = phy_set_bits_mmd(phydev, DP83822_DEVADDR,
MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
if (err)
return err;
} else { } else {
phy_clear_bits_mmd(phydev, DP83822_DEVADDR, err = phy_clear_bits_mmd(phydev, DP83822_DEVADDR,
MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
if (err)
return err;
} }
if (dp83822->fx_enabled) { if (dp83822->fx_enabled) {