From 87aa02fb28dae1388c0e3f320436eb560504f419 Mon Sep 17 00:00:00 2001 From: "hong.guo" Date: Sun, 4 Feb 2018 13:46:10 +0800 Subject: [PATCH] CPUFREQ: add dvfs cpufreq and latency. PD#156734: cpufreq: add dvfs cpufreq cpufreq and latency. Change-Id: I0d7c74e54b2e6dcbd949c1c59cce41deec5047f7 Signed-off-by: hong.guo --- arch/arm64/boot/dts/amlogic/mesong12a.dtsi | 26 ++++++++++------------ drivers/amlogic/clk/g12a/g12a.h | 1 + 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/mesong12a.dtsi b/arch/arm64/boot/dts/amlogic/mesong12a.dtsi index d6ad119f8666..c80fc9134fb6 100644 --- a/arch/arm64/boot/dts/amlogic/mesong12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/mesong12a.dtsi @@ -66,6 +66,7 @@ operating-points-v2 = <&cpu_opp_table0>; cpu-supply = <&vddcpu0>; voltage-tolerance = <0>; + clock-latency = <50000>; }; CPU1:cpu@1 { @@ -83,6 +84,7 @@ operating-points-v2 = <&cpu_opp_table0>; cpu-supply = <&vddcpu0>; voltage-tolerance = <0>; + clock-latency = <50000>; }; CPU2:cpu@2 { @@ -100,6 +102,7 @@ operating-points-v2 = <&cpu_opp_table0>; cpu-supply = <&vddcpu0>; voltage-tolerance = <0>; + clock-latency = <50000>; }; CPU3:cpu@3 { @@ -117,6 +120,7 @@ operating-points-v2 = <&cpu_opp_table0>; cpu-supply = <&vddcpu0>; voltage-tolerance = <0>; + clock-latency = <50000>; }; idle-states { @@ -139,53 +143,47 @@ opp00 { opp-hz = /bits/ 64 <100000000>; opp-microvolt = <761000>; - clock-latency-ns = <2000000>; }; opp01 { opp-hz = /bits/ 64 <250000000>; opp-microvolt = <781000>; - clock-latency-ns = <2000000>; }; opp02 { opp-hz = /bits/ 64 <500000000>; opp-microvolt = <801000>; - clock-latency-ns = <2000000>; }; opp03 { opp-hz = /bits/ 64 <667000000>; opp-microvolt = <851000>; - clock-latency-ns = <2000000>; }; opp04 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <881000>; - clock-latency-ns = <2000000>; }; opp05 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <891000>; - clock-latency-ns = <2000000>; }; opp06 { opp-hz = /bits/ 64 <1398000000>; - opp-microvolt = <981000>; - clock-latency-ns = <2000000>; + opp-microvolt = <921000>; }; opp07 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <991000>; - clock-latency-ns = <2000000>; + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <951000>; }; opp08 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <991000>; + }; + opp09 { opp-hz = /bits/ 64 <1800000000>; opp-microvolt = <1001000>; - clock-latency-ns = <2000000>; }; - opp09 { + opp10 { opp-hz = /bits/ 64 <2016000000>; opp-microvolt = <1011000>; - clock-latency-ns = <2000000>; }; }; diff --git a/drivers/amlogic/clk/g12a/g12a.h b/drivers/amlogic/clk/g12a/g12a.h index 173819109272..506ad8546c6e 100644 --- a/drivers/amlogic/clk/g12a/g12a.h +++ b/drivers/amlogic/clk/g12a/g12a.h @@ -130,6 +130,7 @@ static const struct pll_rate_table g12a_pll_rate_table[] = { PLL_RATE(1296000000, 216, 1, 2), /*DCO=5184M*/ PLL_RATE(1398000000, 233, 1, 2), /*DCO=5592M*/ PLL_RATE(1494000000, 249, 1, 2), /*DCO=5976M*/ + PLL_RATE(1512000000, 126, 1, 1), /*DCO=3024M*/ PLL_RATE(1608000000, 134, 1, 1), /*DCO=3216M*/ PLL_RATE(1704000000, 142, 1, 1), /*DCO=3408M*/ PLL_RATE(1800000000, 150, 1, 1), /*DCO=3600M*/