diff --git a/Documentation/ABI/stable/sysfs-driver-firmware-zynqmp b/Documentation/ABI/stable/sysfs-driver-firmware-zynqmp new file mode 100644 index 000000000000..00fa04c76ff3 --- /dev/null +++ b/Documentation/ABI/stable/sysfs-driver-firmware-zynqmp @@ -0,0 +1,103 @@ +What: /sys/devices/platform/firmware\:zynqmp-firmware/ggs* +Date: March 2020 +KernelVersion: 5.6 +Contact: "Jolly Shah" +Description: + Read/Write PMU global general storage register value, + GLOBAL_GEN_STORAGE{0:3}. + Global general storage register that can be used + by system to pass information between masters. + + The register is reset during system or power-on + resets. Three registers are used by the FSBL and + other Xilinx software products: GLOBAL_GEN_STORAGE{4:6}. + + Usage: + # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0 + # echo > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0 + + Example: + # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0 + # echo 0x1234ABCD > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0 + +Users: Xilinx + +What: /sys/devices/platform/firmware\:zynqmp-firmware/pggs* +Date: March 2020 +KernelVersion: 5.6 +Contact: "Jolly Shah" +Description: + Read/Write PMU persistent global general storage register + value, PERS_GLOB_GEN_STORAGE{0:3}. + Persistent global general storage register that + can be used by system to pass information between + masters. + + This register is only reset by the power-on reset + and maintains its value through a system reset. + Four registers are used by the FSBL and other Xilinx + software products: PERS_GLOB_GEN_STORAGE{4:7}. + Register is reset only by a POR reset. + + Usage: + # cat /sys/devices/platform/firmware\:zynqmp-firmware/pggs0 + # echo > /sys/devices/platform/firmware\:zynqmp-firmware/pggs0 + + Example: + # cat /sys/devices/platform/firmware\:zynqmp-firmware/pggs0 + # echo 0x1234ABCD > /sys/devices/platform/firmware\:zynqmp-firmware/pggs0 + +Users: Xilinx + +What: /sys/devices/platform/firmware\:zynqmp-firmware/shutdown_scope +Date: March 2020 +KernelVersion: 5.6 +Contact: "Jolly Shah" +Description: + This sysfs interface allows to set the shutdown scope for the + next shutdown request. When the next shutdown is performed, the + platform specific portion of PSCI-system_off can use the chosen + shutdown scope. + + Following are available shutdown scopes(subtypes): + + subsystem: Only the APU along with all of its peripherals + not used by other processing units will be + shut down. This may result in the FPD power + domain being shut down provided that no other + processing unit uses FPD peripherals or DRAM. + ps_only: The complete PS will be shut down, including the + RPU, PMU, etc. Only the PL domain (FPGA) + remains untouched. + system: The complete system/device is shut down. + + Usage: + # cat /sys/devices/platform/firmware\:zynqmp-firmware/shutdown_scope + # echo > /sys/devices/platform/firmware\:zynqmp-firmware/shutdown_scope + + Example: + # cat /sys/devices/platform/firmware\:zynqmp-firmware/shutdown_scope + # echo "subsystem" > /sys/devices/platform/firmware\:zynqmp-firmware/shutdown_scope + +Users: Xilinx + +What: /sys/devices/platform/firmware\:zynqmp-firmware/health_status +Date: March 2020 +KernelVersion: 5.6 +Contact: "Jolly Shah" +Description: + This sysfs interface allows to set the health status. If PMUFW + is compiled with CHECK_HEALTHY_BOOT, it will check the healthy + bit on FPD WDT expiration. If healthy bit is set by a user + application running in Linux, PMUFW will do APU only restart. If + healthy bit is not set during FPD WDT expiration, PMUFW will do + system restart. + + Usage: + Set healthy bit + # echo 1 > /sys/devices/platform/firmware\:zynqmp-firmware/health_status + + Unset healthy bit + # echo 0 > /sys/devices/platform/firmware\:zynqmp-firmware/health_status + +Users: Xilinx diff --git a/Documentation/ABI/testing/debugfs-driver-habanalabs b/Documentation/ABI/testing/debugfs-driver-habanalabs index a73601c5121e..f6d9c2a8d528 100644 --- a/Documentation/ABI/testing/debugfs-driver-habanalabs +++ b/Documentation/ABI/testing/debugfs-driver-habanalabs @@ -8,6 +8,16 @@ Description: Sets the device address to be used for read or write through only when the IOMMU is disabled. The acceptable value is a string that starts with "0x" +What: /sys/kernel/debug/habanalabs/hl/clk_gate +Date: May 2020 +KernelVersion: 5.8 +Contact: oded.gabbay@gmail.com +Description: Allow the root user to disable/enable in runtime the clock + gating mechanism in Gaudi. Due to how Gaudi is built, the + clock gating needs to be disabled in order to access the + registers of the TPC and MME engines. This is sometimes needed + during debug by the user and hence the user needs this option + What: /sys/kernel/debug/habanalabs/hl/command_buffers Date: Jan 2019 KernelVersion: 5.1 @@ -150,3 +160,10 @@ KernelVersion: 5.1 Contact: oded.gabbay@gmail.com Description: Displays a list with information about all the active virtual address mappings per ASID + +What: /sys/kernel/debug/habanalabs/hl/stop_on_err +Date: Mar 2020 +KernelVersion: 5.6 +Contact: oded.gabbay@gmail.com +Description: Sets the stop-on_error option for the device engines. Value of + "0" is for disable, otherwise enable. diff --git a/Documentation/ABI/testing/sysfs-bus-event_source-devices-dfl_fme b/Documentation/ABI/testing/sysfs-bus-event_source-devices-dfl_fme new file mode 100644 index 000000000000..c9278a3b3df1 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-event_source-devices-dfl_fme @@ -0,0 +1,104 @@ +What: /sys/bus/event_source/devices/dfl_fmeX/format +Date: April 2020 +KernelVersion: 5.8 +Contact: Wu Hao +Description: Read-only. Attribute group to describe the magic bits + that go into perf_event_attr.config for a particular pmu. + (See ABI/testing/sysfs-bus-event_source-devices-format). + + Each attribute under this group defines a bit range of the + perf_event_attr.config. All supported attributes are listed + below. + + event = "config:0-11" - event ID + evtype = "config:12-15" - event type + portid = "config:16-23" - event source + + For example, + + fab_mmio_read = "event=0x06,evtype=0x02,portid=0xff" + + It shows this fab_mmio_read is a fabric type (0x02) event with + 0x06 local event id for overall monitoring (portid=0xff). + +What: /sys/bus/event_source/devices/dfl_fmeX/cpumask +Date: April 2020 +KernelVersion: 5.8 +Contact: Wu Hao +Description: Read-only. This file always returns cpu which the PMU is bound + for access to all fme pmu performance monitoring events. + +What: /sys/bus/event_source/devices/dfl_fmeX/events +Date: April 2020 +KernelVersion: 5.8 +Contact: Wu Hao +Description: Read-only. Attribute group to describe performance monitoring + events specific to fme. Each attribute in this group describes + a single performance monitoring event supported by this fme pmu. + The name of the file is the name of the event. + (See ABI/testing/sysfs-bus-event_source-devices-events). + + All supported performance monitoring events are listed below. + + Basic events (evtype=0x00) + + clock = "event=0x00,evtype=0x00,portid=0xff" + + Cache events (evtype=0x01) + + cache_read_hit = "event=0x00,evtype=0x01,portid=0xff" + cache_read_miss = "event=0x01,evtype=0x01,portid=0xff" + cache_write_hit = "event=0x02,evtype=0x01,portid=0xff" + cache_write_miss = "event=0x03,evtype=0x01,portid=0xff" + cache_hold_request = "event=0x05,evtype=0x01,portid=0xff" + cache_data_write_port_contention = + "event=0x06,evtype=0x01,portid=0xff" + cache_tag_write_port_contention = + "event=0x07,evtype=0x01,portid=0xff" + cache_tx_req_stall = "event=0x08,evtype=0x01,portid=0xff" + cache_rx_req_stall = "event=0x09,evtype=0x01,portid=0xff" + cache_eviction = "event=0x0a,evtype=0x01,portid=0xff" + + Fabric events (evtype=0x02) + + fab_pcie0_read = "event=0x00,evtype=0x02,portid=0xff" + fab_pcie0_write = "event=0x01,evtype=0x02,portid=0xff" + fab_pcie1_read = "event=0x02,evtype=0x02,portid=0xff" + fab_pcie1_write = "event=0x03,evtype=0x02,portid=0xff" + fab_upi_read = "event=0x04,evtype=0x02,portid=0xff" + fab_upi_write = "event=0x05,evtype=0x02,portid=0xff" + fab_mmio_read = "event=0x06,evtype=0x02,portid=0xff" + fab_mmio_write = "event=0x07,evtype=0x02,portid=0xff" + fab_port_pcie0_read = "event=0x00,evtype=0x02,portid=?" + fab_port_pcie0_write = "event=0x01,evtype=0x02,portid=?" + fab_port_pcie1_read = "event=0x02,evtype=0x02,portid=?" + fab_port_pcie1_write = "event=0x03,evtype=0x02,portid=?" + fab_port_upi_read = "event=0x04,evtype=0x02,portid=?" + fab_port_upi_write = "event=0x05,evtype=0x02,portid=?" + fab_port_mmio_read = "event=0x06,evtype=0x02,portid=?" + fab_port_mmio_write = "event=0x07,evtype=0x02,portid=?" + + VTD events (evtype=0x03) + + vtd_port_read_transaction = "event=0x00,evtype=0x03,portid=?" + vtd_port_write_transaction = "event=0x01,evtype=0x03,portid=?" + vtd_port_devtlb_read_hit = "event=0x02,evtype=0x03,portid=?" + vtd_port_devtlb_write_hit = "event=0x03,evtype=0x03,portid=?" + vtd_port_devtlb_4k_fill = "event=0x04,evtype=0x03,portid=?" + vtd_port_devtlb_2m_fill = "event=0x05,evtype=0x03,portid=?" + vtd_port_devtlb_1g_fill = "event=0x06,evtype=0x03,portid=?" + + VTD SIP events (evtype=0x04) + + vtd_sip_iotlb_4k_hit = "event=0x00,evtype=0x04,portid=0xff" + vtd_sip_iotlb_2m_hit = "event=0x01,evtype=0x04,portid=0xff" + vtd_sip_iotlb_1g_hit = "event=0x02,evtype=0x04,portid=0xff" + vtd_sip_slpwc_l3_hit = "event=0x03,evtype=0x04,portid=0xff" + vtd_sip_slpwc_l4_hit = "event=0x04,evtype=0x04,portid=0xff" + vtd_sip_rcc_hit = "event=0x05,evtype=0x04,portid=0xff" + vtd_sip_iotlb_4k_miss = "event=0x06,evtype=0x04,portid=0xff" + vtd_sip_iotlb_2m_miss = "event=0x07,evtype=0x04,portid=0xff" + vtd_sip_iotlb_1g_miss = "event=0x08,evtype=0x04,portid=0xff" + vtd_sip_slpwc_l3_miss = "event=0x09,evtype=0x04,portid=0xff" + vtd_sip_slpwc_l4_miss = "event=0x0a,evtype=0x04,portid=0xff" + vtd_sip_rcc_miss = "event=0x0b,evtype=0x04,portid=0xff" diff --git a/Documentation/ABI/testing/sysfs-bus-iio-proximity b/Documentation/ABI/testing/sysfs-bus-iio-proximity new file mode 100644 index 000000000000..2172f3bb9c64 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-iio-proximity @@ -0,0 +1,10 @@ +What: /sys/bus/iio/devices/iio:deviceX/in_proximity_nearlevel +Date: March 2020 +KernelVersion: 5.7 +Contact: linux-iio@vger.kernel.org +Description: + Near level for proximity sensors. This is a single integer + value that tells user space when an object should be + considered close to the device. If the value read from the + sensor is above or equal to the value in this file an object + should typically be considered near. diff --git a/Documentation/ABI/testing/sysfs-bus-iio-sx9310 b/Documentation/ABI/testing/sysfs-bus-iio-sx9310 new file mode 100644 index 000000000000..3ac7759013e5 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-iio-sx9310 @@ -0,0 +1,10 @@ +What: /sys/bus/iio/devices/iio:deviceX/in_proximity3_comb_raw +Date: February 2019 +KernelVersion: 5.6 +Contact: Daniel Campello +Description: + Proximity measurement indicating that some object is + near the combined sensor. The combined sensor presents + proximity measurements constructed by hardware by + combining measurements taken from a given set of + physical sensors. diff --git a/Documentation/ABI/testing/sysfs-bus-most b/Documentation/ABI/testing/sysfs-bus-most index 6b1d06e3285e..ec0a603d804b 100644 --- a/Documentation/ABI/testing/sysfs-bus-most +++ b/Documentation/ABI/testing/sysfs-bus-most @@ -1,14 +1,14 @@ -What: /sys/bus/most/devices/.../description +What: /sys/bus/most/devices//description Date: March 2017 KernelVersion: 4.15 Contact: Christian Gromm Description: - Provides information about the interface type and the physical - location of the device. Hardware attached via USB, for instance, + Provides information about the physical location of the + device. Hardware attached via USB, for instance, might return <1-1.1:1.0> Users: -What: /sys/bus/most/devices/.../interface +What: /sys/bus/most/devices//interface Date: March 2017 KernelVersion: 4.15 Contact: Christian Gromm @@ -16,7 +16,7 @@ Description: Indicates the type of peripheral interface the device uses. Users: -What: /sys/bus/most/devices/.../dci +What: /sys/bus/most/devices//dci Date: June 2016 KernelVersion: 4.15 Contact: Christian Gromm @@ -26,7 +26,7 @@ Description: write the controller's DCI registers. Users: -What: /sys/bus/most/devices/.../dci/arb_address +What: /sys/bus/most/devices//dci/arb_address Date: June 2016 KernelVersion: 4.15 Contact: Christian Gromm @@ -35,7 +35,7 @@ Description: application wants to read from or write to. Users: -What: /sys/bus/most/devices/.../dci/arb_value +What: /sys/bus/most/devices//dci/arb_value Date: June 2016 KernelVersion: 4.15 Contact: Christian Gromm @@ -44,7 +44,7 @@ Description: is stored in arb_address. Users: -What: /sys/bus/most/devices/.../dci/mep_eui48_hi +What: /sys/bus/most/devices//dci/mep_eui48_hi Date: June 2016 KernelVersion: 4.15 Contact: Christian Gromm @@ -52,7 +52,7 @@ Description: This is used to check and configure the MAC address. Users: -What: /sys/bus/most/devices/.../dci/mep_eui48_lo +What: /sys/bus/most/devices//dci/mep_eui48_lo Date: June 2016 KernelVersion: 4.15 Contact: Christian Gromm @@ -60,7 +60,7 @@ Description: This is used to check and configure the MAC address. Users: -What: /sys/bus/most/devices/.../dci/mep_eui48_mi +What: /sys/bus/most/devices//dci/mep_eui48_mi Date: June 2016 KernelVersion: 4.15 Contact: Christian Gromm @@ -68,7 +68,7 @@ Description: This is used to check and configure the MAC address. Users: -What: /sys/bus/most/devices/.../dci/mep_filter +What: /sys/bus/most/devices//dci/mep_filter Date: June 2016 KernelVersion: 4.15 Contact: Christian Gromm @@ -76,7 +76,7 @@ Description: This is used to check and configure the MEP filter address. Users: -What: /sys/bus/most/devices/.../dci/mep_hash0 +What: /sys/bus/most/devices//dci/mep_hash0 Date: June 2016 KernelVersion: 4.15 Contact: Christian Gromm @@ -84,7 +84,7 @@ Description: This is used to check and configure the MEP hash table. Users: -What: /sys/bus/most/devices/.../dci/mep_hash1 +What: /sys/bus/most/devices//dci/mep_hash1 Date: June 2016 KernelVersion: 4.15 Contact: Christian Gromm @@ -92,7 +92,7 @@ Description: This is used to check and configure the MEP hash table. Users: -What: /sys/bus/most/devices/.../dci/mep_hash2 +What: /sys/bus/most/devices//dci/mep_hash2 Date: June 2016 KernelVersion: 4.15 Contact: Christian Gromm @@ -100,7 +100,7 @@ Description: This is used to check and configure the MEP hash table. Users: -What: /sys/bus/most/devices/.../dci/mep_hash3 +What: /sys/bus/most/devices//dci/mep_hash3 Date: June 2016 KernelVersion: 4.15 Contact: Christian Gromm @@ -108,7 +108,7 @@ Description: This is used to check and configure the MEP hash table. Users: -What: /sys/bus/most/devices/.../dci/ni_state +What: /sys/bus/most/devices//dci/ni_state Date: June 2016 KernelVersion: 4.15 Contact: Christian Gromm @@ -116,7 +116,7 @@ Description: Indicates the current network interface state. Users: -What: /sys/bus/most/devices/.../dci/node_address +What: /sys/bus/most/devices//dci/node_address Date: June 2016 KernelVersion: 4.15 Contact: Christian Gromm @@ -124,7 +124,7 @@ Description: Indicates the current node address. Users: -What: /sys/bus/most/devices/.../dci/node_position +What: /sys/bus/most/devices//dci/node_position Date: June 2016 KernelVersion: 4.15 Contact: Christian Gromm @@ -132,7 +132,7 @@ Description: Indicates the current node position. Users: -What: /sys/bus/most/devices/.../dci/packet_bandwidth +What: /sys/bus/most/devices//dci/packet_bandwidth Date: June 2016 KernelVersion: 4.15 Contact: Christian Gromm @@ -140,7 +140,7 @@ Description: Indicates the configured packet bandwidth. Users: -What: /sys/bus/most/devices/.../dci/sync_ep +What: /sys/bus/most/devices//dci/sync_ep Date: June 2016 KernelVersion: 4.15 Contact: Christian Gromm @@ -149,7 +149,7 @@ Description: endpoint. Users: -What: /sys/bus/most/devices/...// +What: /sys/bus/most/devices/// Date: March 2017 KernelVersion: 4.15 Contact: Christian Gromm @@ -160,91 +160,92 @@ Description: configure it. Users: -What: /sys/bus/most/devices/...//available_datatypes +What: /sys/bus/most/devices///available_datatypes Date: March 2017 KernelVersion: 4.15 Contact: Christian Gromm Description: - Indicates the data types the current channel can transport. + Indicates the data types the channel can transport. Users: -What: /sys/bus/most/devices/...//available_directions +What: /sys/bus/most/devices///available_directions Date: March 2017 KernelVersion: 4.15 Contact: Christian Gromm Description: - Indicates the directions the current channel is capable of. + Indicates the directions the channel is capable of. Users: -What: /sys/bus/most/devices/...//number_of_packet_buffers +What: /sys/bus/most/devices///number_of_packet_buffers Date: March 2017 KernelVersion: 4.15 Contact: Christian Gromm Description: - Indicates the number of packet buffers the current channel can + Indicates the number of packet buffers the channel can handle. Users: -What: /sys/bus/most/devices/...//number_of_stream_buffers +What: /sys/bus/most/devices///number_of_stream_buffers Date: March 2017 KernelVersion: 4.15 Contact: Christian Gromm Description: - Indicates the number of streaming buffers the current channel can + Indicates the number of streaming buffers the channel can handle. Users: -What: /sys/bus/most/devices/...//size_of_packet_buffer +What: /sys/bus/most/devices///size_of_packet_buffer Date: March 2017 KernelVersion: 4.15 Contact: Christian Gromm Description: - Indicates the size of a packet buffer the current channel can + Indicates the size of a packet buffer the channel can handle. Users: -What: /sys/bus/most/devices/...//size_of_stream_buffer +What: /sys/bus/most/devices///size_of_stream_buffer Date: March 2017 KernelVersion: 4.15 Contact: Christian Gromm Description: - Indicates the size of a streaming buffer the current channel can + Indicates the size of a streaming buffer the channel can handle. Users: -What: /sys/bus/most/devices/...//set_number_of_buffers +What: /sys/bus/most/devices///set_number_of_buffers Date: March 2017 KernelVersion: 4.15 Contact: Christian Gromm Description: - This is to configure the number of buffers of the current channel. + This is to read back the configured number of buffers of + the channel. Users: -What: /sys/bus/most/devices/...//set_buffer_size +What: /sys/bus/most/devices///set_buffer_size Date: March 2017 KernelVersion: 4.15 Contact: Christian Gromm Description: - This is to configure the size of a buffer of the current channel. + This is to read back the configured buffer size of the channel. Users: -What: /sys/bus/most/devices/...//set_direction +What: /sys/bus/most/devices///set_direction Date: March 2017 KernelVersion: 4.15 Contact: Christian Gromm Description: - This is to configure the direction of the current channel. + This is to read back the configured direction of the channel. The following strings will be accepted: - 'dir_tx', - 'dir_rx' + 'tx', + 'rx' Users: -What: /sys/bus/most/devices/...//set_datatype +What: /sys/bus/most/devices///set_datatype Date: March 2017 KernelVersion: 4.15 Contact: Christian Gromm Description: - This is to configure the data type of the current channel. + This is to read back the configured data type of the channel. The following strings will be accepted: 'control', 'async', @@ -252,30 +253,31 @@ Description: 'isoc_avp' Users: -What: /sys/bus/most/devices/...//set_subbuffer_size +What: /sys/bus/most/devices///set_subbuffer_size Date: March 2017 KernelVersion: 4.15 Contact: Christian Gromm Description: - This is to configure the subbuffer size of the current channel. + This is to read back the configured subbuffer size of + the channel. Users: -What: /sys/bus/most/devices/...//set_packets_per_xact +What: /sys/bus/most/devices///set_packets_per_xact Date: March 2017 KernelVersion: 4.15 Contact: Christian Gromm Description: - This is to configure the number of packets per transaction of - the current channel. This is only needed network interface - controller is attached via USB. + This is to read back the configured number of packets per + transaction of the channel. This is only applicable when + connected via USB. Users: -What: /sys/bus/most/devices/...//channel_starving +What: /sys/bus/most/devices///channel_starving Date: March 2017 KernelVersion: 4.15 Contact: Christian Gromm Description: - Indicates whether current channel ran out of buffers. + Indicates whether channel ran out of buffers. Users: What: /sys/bus/most/drivers/most_core/components diff --git a/Documentation/ABI/testing/sysfs-bus-soundwire-master b/Documentation/ABI/testing/sysfs-bus-soundwire-master new file mode 100644 index 000000000000..46ef038d8722 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-soundwire-master @@ -0,0 +1,23 @@ +What: /sys/bus/soundwire/devices/sdw-master-N/revision + /sys/bus/soundwire/devices/sdw-master-N/clk_stop_modes + /sys/bus/soundwire/devices/sdw-master-N/clk_freq + /sys/bus/soundwire/devices/sdw-master-N/clk_gears + /sys/bus/soundwire/devices/sdw-master-N/default_col + /sys/bus/soundwire/devices/sdw-master-N/default_frame_rate + /sys/bus/soundwire/devices/sdw-master-N/default_row + /sys/bus/soundwire/devices/sdw-master-N/dynamic_shape + /sys/bus/soundwire/devices/sdw-master-N/err_threshold + /sys/bus/soundwire/devices/sdw-master-N/max_clk_freq + +Date: April 2020 + +Contact: Pierre-Louis Bossart + Bard Liao + Vinod Koul + +Description: SoundWire Master-N DisCo properties. + These properties are defined by MIPI DisCo Specification + for SoundWire. They define various properties of the Master + and are used by the bus to configure the Master. clk_stop_modes + is a bitmask for simplifications and combines the + clock-stop-mode0 and clock-stop-mode1 properties. diff --git a/Documentation/ABI/testing/sysfs-bus-soundwire-slave b/Documentation/ABI/testing/sysfs-bus-soundwire-slave new file mode 100644 index 000000000000..db4c9511d1aa --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-soundwire-slave @@ -0,0 +1,91 @@ +What: /sys/bus/soundwire/devices/sdw:.../dev-properties/mipi_revision + /sys/bus/soundwire/devices/sdw:.../dev-properties/wake_capable + /sys/bus/soundwire/devices/sdw:.../dev-properties/test_mode_capable + /sys/bus/soundwire/devices/sdw:.../dev-properties/clk_stop_mode1 + /sys/bus/soundwire/devices/sdw:.../dev-properties/simple_clk_stop_capable + /sys/bus/soundwire/devices/sdw:.../dev-properties/clk_stop_timeout + /sys/bus/soundwire/devices/sdw:.../dev-properties/ch_prep_timeout + /sys/bus/soundwire/devices/sdw:.../dev-properties/reset_behave + /sys/bus/soundwire/devices/sdw:.../dev-properties/high_PHY_capable + /sys/bus/soundwire/devices/sdw:.../dev-properties/paging_support + /sys/bus/soundwire/devices/sdw:.../dev-properties/bank_delay_support + /sys/bus/soundwire/devices/sdw:.../dev-properties/p15_behave + /sys/bus/soundwire/devices/sdw:.../dev-properties/master_count + /sys/bus/soundwire/devices/sdw:.../dev-properties/source_ports + /sys/bus/soundwire/devices/sdw:.../dev-properties/sink_ports + +Date: May 2020 + +Contact: Pierre-Louis Bossart + Bard Liao + Vinod Koul + +Description: SoundWire Slave DisCo properties. + These properties are defined by MIPI DisCo Specification + for SoundWire. They define various properties of the + SoundWire Slave and are used by the bus to configure + the Slave + + +What: /sys/bus/soundwire/devices/sdw:.../dp0/max_word + /sys/bus/soundwire/devices/sdw:.../dp0/min_word + /sys/bus/soundwire/devices/sdw:.../dp0/words + /sys/bus/soundwire/devices/sdw:.../dp0/BRA_flow_controlled + /sys/bus/soundwire/devices/sdw:.../dp0/simple_ch_prep_sm + /sys/bus/soundwire/devices/sdw:.../dp0/imp_def_interrupts + +Date: May 2020 + +Contact: Pierre-Louis Bossart + Bard Liao + Vinod Koul + +Description: SoundWire Slave Data Port-0 DisCo properties. + These properties are defined by MIPI DisCo Specification + for the SoundWire. They define various properties of the + Data port 0 are used by the bus to configure the Data Port 0. + + +What: /sys/bus/soundwire/devices/sdw:.../dpN_src/max_word + /sys/bus/soundwire/devices/sdw:.../dpN_src/min_word + /sys/bus/soundwire/devices/sdw:.../dpN_src/words + /sys/bus/soundwire/devices/sdw:.../dpN_src/type + /sys/bus/soundwire/devices/sdw:.../dpN_src/max_grouping + /sys/bus/soundwire/devices/sdw:.../dpN_src/simple_ch_prep_sm + /sys/bus/soundwire/devices/sdw:.../dpN_src/ch_prep_timeout + /sys/bus/soundwire/devices/sdw:.../dpN_src/imp_def_interrupts + /sys/bus/soundwire/devices/sdw:.../dpN_src/min_ch + /sys/bus/soundwire/devices/sdw:.../dpN_src/max_ch + /sys/bus/soundwire/devices/sdw:.../dpN_src/channels + /sys/bus/soundwire/devices/sdw:.../dpN_src/ch_combinations + /sys/bus/soundwire/devices/sdw:.../dpN_src/max_async_buffer + /sys/bus/soundwire/devices/sdw:.../dpN_src/block_pack_mode + /sys/bus/soundwire/devices/sdw:.../dpN_src/port_encoding + + /sys/bus/soundwire/devices/sdw:.../dpN_sink/max_word + /sys/bus/soundwire/devices/sdw:.../dpN_sink/min_word + /sys/bus/soundwire/devices/sdw:.../dpN_sink/words + /sys/bus/soundwire/devices/sdw:.../dpN_sink/type + /sys/bus/soundwire/devices/sdw:.../dpN_sink/max_grouping + /sys/bus/soundwire/devices/sdw:.../dpN_sink/simple_ch_prep_sm + /sys/bus/soundwire/devices/sdw:.../dpN_sink/ch_prep_timeout + /sys/bus/soundwire/devices/sdw:.../dpN_sink/imp_def_interrupts + /sys/bus/soundwire/devices/sdw:.../dpN_sink/min_ch + /sys/bus/soundwire/devices/sdw:.../dpN_sink/max_ch + /sys/bus/soundwire/devices/sdw:.../dpN_sink/channels + /sys/bus/soundwire/devices/sdw:.../dpN_sink/ch_combinations + /sys/bus/soundwire/devices/sdw:.../dpN_sink/max_async_buffer + /sys/bus/soundwire/devices/sdw:.../dpN_sink/block_pack_mode + /sys/bus/soundwire/devices/sdw:.../dpN_sink/port_encoding + +Date: May 2020 + +Contact: Pierre-Louis Bossart + Bard Liao + Vinod Koul + +Description: SoundWire Slave Data Source/Sink Port-N DisCo properties. + These properties are defined by MIPI DisCo Specification + for SoundWire. They define various properties of the + Source/Sink Data port N and are used by the bus to configure + the Data Port N. diff --git a/Documentation/ABI/testing/sysfs-driver-habanalabs b/Documentation/ABI/testing/sysfs-driver-habanalabs index 782df74042ed..1a14bf9b22ba 100644 --- a/Documentation/ABI/testing/sysfs-driver-habanalabs +++ b/Documentation/ABI/testing/sysfs-driver-habanalabs @@ -10,6 +10,23 @@ KernelVersion: 5.1 Contact: oded.gabbay@gmail.com Description: Version of the application running on the device's CPU +What: /sys/class/habanalabs/hl/clk_max_freq_mhz +Date: Jun 2019 +KernelVersion: not yet upstreamed +Contact: oded.gabbay@gmail.com +Description: Allows the user to set the maximum clock frequency, in MHz. + The device clock might be set to lower value than the maximum. + The user should read the clk_cur_freq_mhz to see the actual + frequency value of the device clock. This property is valid + only for the Gaudi ASIC family + +What: /sys/class/habanalabs/hl/clk_cur_freq_mhz +Date: Jun 2019 +KernelVersion: not yet upstreamed +Contact: oded.gabbay@gmail.com +Description: Displays the current frequency, in MHz, of the device clock. + This property is valid only for the Gaudi ASIC family + What: /sys/class/habanalabs/hl/cpld_ver Date: Jan 2019 KernelVersion: 5.1 diff --git a/Documentation/ABI/testing/sysfs-driver-w1_therm b/Documentation/ABI/testing/sysfs-driver-w1_therm new file mode 100644 index 000000000000..076659d506f2 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-driver-w1_therm @@ -0,0 +1,116 @@ +What: /sys/bus/w1/devices/.../alarms +Date: May 2020 +Contact: Akira Shimahara +Description: + (RW) read or write TH and TL (Temperature High an Low) alarms. + Values shall be space separated and in the device range + (typical -55 degC to 125 degC), if not values will be trimmed + to device min/max capabilities. Values are integer as they are + stored in a 8bit register in the device. Lowest value is + automatically put to TL. Once set, alarms could be search at + master level, refer to Documentation/w1/w1_generic.rst for + detailed information +Users: any user space application which wants to communicate with + w1_term device + + +What: /sys/bus/w1/devices/.../eeprom +Date: May 2020 +Contact: Akira Shimahara +Description: + (WO) writing that file will either trigger a save of the + device data to its embedded EEPROM, either restore data + embedded in device EEPROM. Be aware that devices support + limited EEPROM writing cycles (typical 50k) + * 'save': save device RAM to EEPROM + * 'restore': restore EEPROM data in device RAM +Users: any user space application which wants to communicate with + w1_term device + + +What: /sys/bus/w1/devices/.../ext_power +Date: May 2020 +Contact: Akira Shimahara +Description: + (RO) return the power status by asking the device + * '0': device parasite powered + * '1': device externally powered + * '-xx': xx is kernel error when reading power status +Users: any user space application which wants to communicate with + w1_term device + + +What: /sys/bus/w1/devices/.../resolution +Date: May 2020 +Contact: Akira Shimahara +Description: + (RW) get or set the device resolution (on supported devices, + if not, this entry is not present). Note that the resolution + will be changed only in device RAM, so it will be cleared when + power is lost. Trigger a 'save' to EEPROM command to keep + values after power-on. Read or write are : + * '9..12': device resolution in bit + or resolution to set in bit + * '-xx': xx is kernel error when reading the resolution + * Anything else: do nothing +Users: any user space application which wants to communicate with + w1_term device + + +What: /sys/bus/w1/devices/.../temperature +Date: May 2020 +Contact: Akira Shimahara +Description: + (RO) return the temperature in 1/1000 degC. + * If a bulk read has been triggered, it will directly + return the temperature computed when the bulk read + occurred, if available. If not yet available, nothing + is returned (a debug kernel message is sent), you + should retry later on. + * If no bulk read has been triggered, it will trigger + a conversion and send the result. Note that the + conversion duration depend on the resolution (if + device support this feature). It takes 94ms in 9bits + resolution, 750ms for 12bits. +Users: any user space application which wants to communicate with + w1_term device + + +What: /sys/bus/w1/devices/.../w1_slave +Date: May 2020 +Contact: Akira Shimahara +Description: + (RW) return the temperature in 1/1000 degC. + *read*: return 2 lines with the hexa output data sent on the + bus, return the CRC check and temperature in 1/1000 degC + *write* : + * '0' : save the 2 or 3 bytes to the device EEPROM + (i.e. TH, TL and config register) + * '9..12' : set the device resolution in RAM + (if supported) + * Anything else: do nothing + refer to Documentation/w1/slaves/w1_therm.rst for detailed + information. +Users: any user space application which wants to communicate with + w1_term device + + +What: /sys/bus/w1/devices/w1_bus_masterXX/therm_bulk_read +Date: May 2020 +Contact: Akira Shimahara +Description: + (RW) trigger a bulk read conversion. read the status + *read*: + * '-1': conversion in progress on at least 1 sensor + * '1' : conversion complete but at least one sensor + value has not been read yet + * '0' : no bulk operation. Reading temperature will + trigger a conversion on each device + *write*: 'trigger': trigger a bulk read on all supporting + devices on the bus + Note that if a bulk read is sent but one sensor is not read + immediately, the next access to temperature on this device + will return the temperature measured at the time of issue + of the bulk read command (not the current temperature). +Users: any user space application which wants to communicate with + w1_term device diff --git a/Documentation/admin-guide/sysrq.rst b/Documentation/admin-guide/sysrq.rst index a46209f4636c..e6424d8c5846 100644 --- a/Documentation/admin-guide/sysrq.rst +++ b/Documentation/admin-guide/sysrq.rst @@ -231,13 +231,13 @@ prints help, and C) an action_msg string, that will print right before your handler is called. Your handler must conform to the prototype in 'sysrq.h'. After the ``sysrq_key_op`` is created, you can call the kernel function -``register_sysrq_key(int key, struct sysrq_key_op *op_p);`` this will +``register_sysrq_key(int key, const struct sysrq_key_op *op_p);`` this will register the operation pointed to by ``op_p`` at table key 'key', if that slot in the table is blank. At module unload time, you must call -the function ``unregister_sysrq_key(int key, struct sysrq_key_op *op_p)``, which -will remove the key op pointed to by 'op_p' from the key 'key', if and only if -it is currently registered in that slot. This is in case the slot has been -overwritten since you registered it. +the function ``unregister_sysrq_key(int key, const struct sysrq_key_op *op_p)``, +which will remove the key op pointed to by 'op_p' from the key 'key', if and +only if it is currently registered in that slot. This is in case the slot has +been overwritten since you registered it. The Magic SysRQ system works by registering key operations against a key op lookup table, which is defined in 'drivers/tty/sysrq.c'. This key table has diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt index 623fedf12180..715047444391 100644 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt @@ -108,7 +108,8 @@ This binding uses the i.MX common pinctrl binding[3]. Required properties: - compatible: Should be one of: "fsl,imx8qm-iomuxc", - "fsl,imx8qxp-iomuxc". + "fsl,imx8qxp-iomuxc", + "fsl,imx8dxl-iomuxc". Required properties for Pinctrl sub nodes: - fsl,pins: Each entry consists of 3 integers which represents @@ -116,7 +117,8 @@ Required properties for Pinctrl sub nodes: integers are specified using a PIN_FUNC_ID macro, which can be found in , - . + , + . The last integer CONFIG is the pad setting value like pull-up on this pin. diff --git a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt index 1fa66065acc6..6eff1afd8daf 100644 --- a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt +++ b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt @@ -23,7 +23,7 @@ Required properties: The svc node has the following mandatory properties, must be located under the firmware node. -- compatible: "intel,stratix10-svc" +- compatible: "intel,stratix10-svc" or "intel,agilex-svc" - method: smc or hvc smc - Secure Monitor Call hvc - Hypervisor Call diff --git a/Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt index 6e03f79287fb..0f874137ca46 100644 --- a/Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt +++ b/Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt @@ -4,7 +4,8 @@ Required properties: The fpga_mgr node has the following mandatory property, must be located under firmware/svc node. -- compatible : should contain "intel,stratix10-soc-fpga-mgr" +- compatible : should contain "intel,stratix10-soc-fpga-mgr" or + "intel,agilex-soc-fpga-mgr" Example: diff --git a/Documentation/devicetree/bindings/iio/accel/bma180.txt b/Documentation/devicetree/bindings/iio/accel/bma180.txt index f53237270b32..33da4a6fdb39 100644 --- a/Documentation/devicetree/bindings/iio/accel/bma180.txt +++ b/Documentation/devicetree/bindings/iio/accel/bma180.txt @@ -1,15 +1,21 @@ -* Bosch BMA180 / BMA25x triaxial acceleration sensor +* Bosch BMA023 / BMA150/ BMA180 / BMA25x / SMB380 triaxial acceleration sensor +https://media.digikey.com/pdf/Data%20Sheets/Bosch/BMA150.pdf http://omapworld.com/BMA180_111_1002839.pdf http://ae-bst.resource.bosch.com/media/products/dokumente/bma250/bst-bma250-ds002-05.pdf Required properties: - compatible : should be one of: + "bosch,bma023" + "bosch,bma150" "bosch,bma180" "bosch,bma250" "bosch,bma254" + "bosch,smb380" - reg : the I2C address of the sensor + - vdd-supply : regulator phandle connected to the VDD pin + - vddio-supply : regulator phandle connected to the VDDIO pin Optional properties: diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad9467.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad9467.yaml new file mode 100644 index 000000000000..c4f57fa6aad1 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad9467.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad9467.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD9467 High-Speed ADC + +maintainers: + - Michael Hennerich + - Alexandru Ardelean + +description: | + The AD9467 is a 16-bit, monolithic, IF sampling analog-to-digital + converter (ADC). + + https://www.analog.com/media/en/technical-documentation/data-sheets/AD9467.pdf + +properties: + compatible: + enum: + - adi,ad9467 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: adc-clk + + powerdown-gpios: + description: + Pin that controls the powerdown mode of the device. + maxItems: 1 + + reset-gpios: + description: + Reset pin for the device. + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "adi,ad9467"; + reg = <0>; + clocks = <&adc_clk>; + clock-names = "adc-clk"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml b/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml new file mode 100644 index 000000000000..0924b2b4972b --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,axi-adc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AXI ADC IP core + +maintainers: + - Michael Hennerich + - Alexandru Ardelean + +description: | + Analog Devices Generic AXI ADC IP core for interfacing an ADC device + with a high speed serial (JESD204B/C) or source synchronous parallel + interface (LVDS/CMOS). + Usually, some other interface type (i.e SPI) is used as a control + interface for the actual ADC, while this IP core will interface + to the data-lines of the ADC and handle the streaming of data into + memory via DMA. + + https://wiki.analog.com/resources/fpga/docs/axi_adc_ip + +properties: + compatible: + enum: + - adi,axi-adc-10.0.a + + reg: + maxItems: 1 + + dmas: + maxItems: 1 + + dma-names: + items: + - const: rx + + adi,adc-dev: + $ref: /schemas/types.yaml#/definitions/phandle + description: + A reference to a the actual ADC to which this FPGA ADC interfaces to. + +required: + - compatible + - dmas + - reg + - adi,adc-dev + +additionalProperties: false + +examples: + - | + axi-adc@44a00000 { + compatible = "adi,axi-adc-10.0.a"; + reg = <0x44a00000 0x10000>; + dmas = <&rx_dma 0>; + dma-names = "rx"; + + adi,adc-dev = <&spi_adc>; + }; +... diff --git a/Documentation/devicetree/bindings/iio/adc/maxim,max1241.yaml b/Documentation/devicetree/bindings/iio/adc/maxim,max1241.yaml new file mode 100644 index 000000000000..f562505f5ecd --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/maxim,max1241.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2020 Alexandru Lazar +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/maxim,max1241.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim MAX1241 12-bit, single-channel analog to digital converter + +maintainers: + - Alexandru Lazar + +description: | + Bindings for the max1241 12-bit, single-channel ADC device. Datasheet + can be found at: + https://datasheets.maximintegrated.com/en/ds/MAX1240-MAX1241.pdf + +properties: + compatible: + enum: + - maxim,max1241 + + reg: + maxItems: 1 + + vdd-supply: + description: + Device tree identifier of the regulator that powers the ADC. + + vref-supply: + description: + Device tree identifier of the regulator that provides the external + reference voltage. + + shutdown-gpios: + description: + GPIO spec for the GPIO pin connected to the ADC's /SHDN pin. If + specified, the /SHDN pin will be asserted between conversions, + thus enabling power-down mode. + maxItems: 1 + +required: + - compatible + - reg + - vdd-supply + - vref-supply + +examples: + - | + #include + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "maxim,max1241"; + reg = <0>; + vdd-supply = <&adc_vdd>; + vref-supply = <&adc_vref>; + spi-max-frequency = <1000000>; + shutdown-gpios = <&gpio 26 1>; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt deleted file mode 100644 index c2c50b59873d..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt +++ /dev/null @@ -1,37 +0,0 @@ -Rockchip Successive Approximation Register (SAR) A/D Converter bindings - -Required properties: -- compatible: should be "rockchip,-saradc" or "rockchip,rk3066-tsadc" - - "rockchip,saradc": for rk3188, rk3288 - - "rockchip,rk3066-tsadc": for rk3036 - - "rockchip,rk3328-saradc", "rockchip,rk3399-saradc": for rk3328 - - "rockchip,rk3399-saradc": for rk3399 - - "rockchip,rv1108-saradc", "rockchip,rk3399-saradc": for rv1108 - -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: The interrupt number to the cpu. The interrupt specifier format - depends on the interrupt controller. -- clocks: Must contain an entry for each entry in clock-names. -- clock-names: Shall be "saradc" for the converter-clock, and "apb_pclk" for - the peripheral clock. -- vref-supply: The regulator supply ADC reference voltage. -- #io-channel-cells: Should be 1, see ../iio-bindings.txt - -Optional properties: -- resets: Must contain an entry for each entry in reset-names if need support - this option. See ../reset/reset.txt for details. -- reset-names: Must include the name "saradc-apb". - -Example: - saradc: saradc@2006c000 { - compatible = "rockchip,saradc"; - reg = <0x2006c000 0x100>; - interrupts = ; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_SARADC>; - reset-names = "saradc-apb"; - #io-channel-cells = <1>; - vref-supply = <&vcc18>; - }; diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml new file mode 100644 index 000000000000..bcff82a423bc --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/rockchip-saradc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip Successive Approximation Register (SAR) A/D Converter + +maintainers: + - Heiko Stuebner + +properties: + compatible: + oneOf: + - const: rockchip,saradc + - const: rockchip,rk3066-tsadc + - const: rockchip,rk3399-saradc + - items: + - enum: + - rockchip,px30-saradc + - rockchip,rk3308-saradc + - rockchip,rk3328-saradc + - rockchip,rv1108-saradc + - const: rockchip,rk3399-saradc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: converter clock + - description: peripheral clock + + clock-names: + items: + - const: saradc + - const: apb_pclk + + resets: + maxItems: 1 + + reset-names: + const: saradc-apb + + vref-supply: + description: + The regulator supply for the ADC reference voltage. + + "#io-channel-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - vref-supply + - "#io-channel-cells" + +additionalProperties: false + +examples: + - | + #include + #include + saradc: saradc@2006c000 { + compatible = "rockchip,saradc"; + reg = <0x2006c000 0x100>; + interrupts = ; + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC>; + reset-names = "saradc-apb"; + vref-supply = <&vcc18>; + #io-channel-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/iio/chemical/ams,ccs811.yaml b/Documentation/devicetree/bindings/iio/chemical/ams,ccs811.yaml new file mode 100644 index 000000000000..52341c8bacd9 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/chemical/ams,ccs811.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/chemical/ams,ccs811.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMS CCS811 VOC Sensor + +maintainers: + - Narcisa Vasile + +description: | + Ultra-Low Power Digital Gas Sensor for Monitoring Indoor Air Quality. + +properties: + compatible: + enum: + - ams,ccs811 + reg: + maxItems: 1 + + reset-gpios: + description: GPIO connected to the nRESET line. This is an active low + input to CCS811. + maxItems: 1 + + wakeup-gpios: + description: GPIO connected to the nWAKE line. This is an active low + input to CCS811. + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + voc@5b { + compatible = "ams,ccs811"; + reg = <0x5b>; + reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>; + wakeup-gpios = <&gpioa 12 GPIO_ACTIVE_LOW>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/iio/chemical/atlas,sensor.yaml b/Documentation/devicetree/bindings/iio/chemical/atlas,sensor.yaml index edcd2904d50e..69e8931e0ae8 100644 --- a/Documentation/devicetree/bindings/iio/chemical/atlas,sensor.yaml +++ b/Documentation/devicetree/bindings/iio/chemical/atlas,sensor.yaml @@ -4,19 +4,21 @@ $id: http://devicetree.org/schemas/iio/chemical/atlas,sensor.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Atlas Scientific OEM sensors +title: Atlas Scientific OEM + EZO sensors maintainers: - Matt Ranostay description: | - Atlas Scientific OEM sensors connected via I2C + Atlas Scientific OEM + EZO sensors connected via I2C Datasheets: http://www.atlas-scientific.com/_files/_datasheets/_oem/DO_oem_datasheet.pdf http://www.atlas-scientific.com/_files/_datasheets/_oem/EC_oem_datasheet.pdf http://www.atlas-scientific.com/_files/_datasheets/_oem/ORP_oem_datasheet.pdf http://www.atlas-scientific.com/_files/_datasheets/_oem/pH_oem_datasheet.pdf + http://www.atlas-scientific.com/_files/_datasheets/_oem/RTD_oem_datasheet.pdf + http://www.atlas-scientific.com/_files/_datasheets/_probe/EZO_CO2_Datasheet.pdf properties: compatible: @@ -25,6 +27,8 @@ properties: - atlas,ec-sm - atlas,orp-sm - atlas,ph-sm + - atlas,rtd-sm + - atlas,co2-ezo reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/iio/common.yaml b/Documentation/devicetree/bindings/iio/common.yaml new file mode 100644 index 000000000000..97ffcb77043d --- /dev/null +++ b/Documentation/devicetree/bindings/iio/common.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common properties for iio sensors + +maintainers: + - Jonathan Cameron + - Guido Günther + +description: | + This document defines device tree properties common to several iio + sensors. It doesn't constitue a device tree binding specification by itself but + is meant to be referenced by device tree bindings. + + When referenced from sensor tree bindings the properties defined in this + document are defined as follows. The sensor tree bindings are responsible for + defining whether each property is required or optional. + +properties: + proximity-near-level: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + For proximity sensors whether an object can be considered near to the + device depends on parameters like sensor position, covering glass and + aperture. This value gives an indication to userspace for which + sensor readings this is the case. + + Raw proximity values equal or above this level should be + considered 'near' to the device (an object is near to the + sensor). + +... diff --git a/Documentation/devicetree/bindings/iio/dac/ltc2632.txt b/Documentation/devicetree/bindings/iio/dac/ltc2632.txt index 338c3220f01a..1ab9570cf219 100644 --- a/Documentation/devicetree/bindings/iio/dac/ltc2632.txt +++ b/Documentation/devicetree/bindings/iio/dac/ltc2632.txt @@ -1,4 +1,4 @@ -Linear Technology LTC2632/2636 DAC +Linear Technology LTC2632/2634/2636 DAC Required properties: - compatible: Has to contain one of the following: @@ -8,6 +8,12 @@ Required properties: lltc,ltc2632-h12 lltc,ltc2632-h10 lltc,ltc2632-h8 + lltc,ltc2634-l12 + lltc,ltc2634-l10 + lltc,ltc2634-l8 + lltc,ltc2634-h12 + lltc,ltc2634-h10 + lltc,ltc2634-h8 lltc,ltc2636-l12 lltc,ltc2636-l10 lltc,ltc2636-l8 diff --git a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.txt b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.txt deleted file mode 100644 index bf2925c671c6..000000000000 --- a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.txt +++ /dev/null @@ -1,63 +0,0 @@ -STMicroelectronics STM32 DAC - -The STM32 DAC is a 12-bit voltage output digital-to-analog converter. The DAC -may be configured in 8 or 12-bit mode. It has two output channels, each with -its own converter. -It has built-in noise and triangle waveform generator and supports external -triggers for conversions. The DAC's output buffer allows a high drive output -current. - -Contents of a stm32 dac root node: ------------------------------------ -Required properties: -- compatible: Should be one of: - "st,stm32f4-dac-core" - "st,stm32h7-dac-core" -- reg: Offset and length of the device's register set. -- clocks: Must contain an entry for pclk (which feeds the peripheral bus - interface) -- clock-names: Must be "pclk". -- vref-supply: Phandle to the vref+ input analog reference supply. -- #address-cells = <1>; -- #size-cells = <0>; - -Optional properties: -- resets: Must contain the phandle to the reset controller. -- A pinctrl state named "default" for each DAC channel may be defined to set - DAC_OUTx pin in mode of operation for analog output on external pin. - -Contents of a stm32 dac child node: ------------------------------------ -DAC core node should contain at least one subnode, representing a -DAC instance/channel available on the machine. - -Required properties: -- compatible: Must be "st,stm32-dac". -- reg: Must be either 1 or 2, to define (single) channel in use -- #io-channel-cells = <1>: See the IIO bindings section "IIO consumers" in - Documentation/devicetree/bindings/iio/iio-bindings.txt - -Example: - dac: dac@40007400 { - compatible = "st,stm32h7-dac-core"; - reg = <0x40007400 0x400>; - clocks = <&clk>; - clock-names = "pclk"; - vref-supply = <®_vref>; - pinctrl-names = "default"; - pinctrl-0 = <&dac_out1 &dac_out2>; - #address-cells = <1>; - #size-cells = <0>; - - dac1: dac@1 { - compatible = "st,stm32-dac"; - #io-channels-cells = <1>; - reg = <1>; - }; - - dac2: dac@2 { - compatible = "st,stm32-dac"; - #io-channels-cells = <1>; - reg = <2>; - }; - }; diff --git a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml new file mode 100644 index 000000000000..393f7005941a --- /dev/null +++ b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/iio/dac/st,stm32-dac.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: STMicroelectronics STM32 DAC bindings + +description: | + The STM32 DAC is a 12-bit voltage output digital-to-analog converter. The DAC + may be configured in 8 or 12-bit mode. It has two output channels, each with + its own converter. + It has built-in noise and triangle waveform generator and supports external + triggers for conversions. The DAC's output buffer allows a high drive output + current. + +maintainers: + - Fabrice Gasnier + +properties: + compatible: + enum: + - st,stm32f4-dac-core + - st,stm32h7-dac-core + + reg: + maxItems: 1 + + resets: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: pclk + + vref-supply: + description: Phandle to the vref input analog reference voltage. + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - vref-supply + - '#address-cells' + - '#size-cells' + +patternProperties: + "^dac@[1-2]+$": + type: object + description: + A DAC block node should contain at least one subnode, representing an + DAC instance/channel available on the machine. + + properties: + compatible: + const: st,stm32-dac + + reg: + description: Must be either 1 or 2, to define (single) channel in use + enum: [1, 2] + + '#io-channel-cells': + const: 1 + + additionalProperties: false + + required: + - compatible + - reg + - '#io-channel-cells' + +examples: + - | + // Example on stm32mp157c + #include + dac: dac@40017000 { + compatible = "st,stm32h7-dac-core"; + reg = <0x40017000 0x400>; + clocks = <&rcc DAC12>; + clock-names = "pclk"; + vref-supply = <&vref>; + #address-cells = <1>; + #size-cells = <0>; + + dac@1 { + compatible = "st,stm32-dac"; + #io-channel-cells = <1>; + reg = <1>; + }; + + dac@2 { + compatible = "st,stm32-dac"; + #io-channel-cells = <1>; + reg = <2>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/iio/gyroscope/bmg160.txt b/Documentation/devicetree/bindings/iio/gyroscope/bmg160.txt index 78e18a1e9c1d..bb43d1ad9c9f 100644 --- a/Documentation/devicetree/bindings/iio/gyroscope/bmg160.txt +++ b/Documentation/devicetree/bindings/iio/gyroscope/bmg160.txt @@ -2,7 +2,7 @@ Required properties: - - compatible : should be "bosch,bmg160" or "bosch,bmi055_gyro" + - compatible : should be "bosch,bmg160", "bosch,bmi055_gyro" or "bosch,bmi088_gyro" - reg : the I2C address of the sensor (0x69) Optional properties: diff --git a/Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml b/Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml new file mode 100644 index 000000000000..98baecb4b98a --- /dev/null +++ b/Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml @@ -0,0 +1,137 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/imu/adi,adis16475.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices ADIS16475 and similar IMUs + +maintainers: + - Nuno Sá + +description: | + Analog Devices ADIS16475 and similar IMUs + https://www.analog.com/media/en/technical-documentation/data-sheets/ADIS16475.pdf + +properties: + compatible: + enum: + - adi,adis16475-1 + - adi,adis16475-2 + - adi,adis16475-3 + - adi,adis16477-1 + - adi,adis16477-2 + - adi,adis16477-3 + - adi,adis16470 + - adi,adis16465-1 + - adi,adis16465-2 + - adi,adis16465-3 + - adi,adis16467-1 + - adi,adis16467-2 + - adi,adis16467-3 + - adi,adis16500 + - adi,adis16505-1 + - adi,adis16505-2 + - adi,adis16505-3 + - adi,adis16507-1 + - adi,adis16507-2 + - adi,adis16507-3 + + reg: + maxItems: 1 + + spi-cpha: true + + spi-cpol: true + + spi-max-frequency: + maximum: 2000000 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + reset-gpios: + description: + Must be the device tree identifier of the RESET pin. If specified, + it will be asserted during driver probe. As the line is active low, + it should be marked GPIO_ACTIVE_LOW. + maxItems: 1 + + adi,sync-mode: + description: + Configures the device SYNC pin. The following modes are supported + 0 - output_sync + 1 - direct_sync + 2 - scaled_sync + 3 - pulse_sync + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + + adi,scaled-output-hz: + description: + This property must be present if the clock mode is scaled-sync through + clock-names property. In this mode, the input clock can have a range + of 1Hz to 128HZ which must be scaled to originate an allowable sample + rate. This property specifies that rate. + minimum: 1900 + maximum: 2100 + +required: + - compatible + - reg + - interrupts + - spi-cpha + - spi-cpol + +allOf: + - if: + properties: + compatible: + contains: + enum: + - adi,adis16500 + - adi,adis16505-1 + - adi,adis16505-2 + - adi,adis16505-3 + - adi,adis16507-1 + - adi,adis16507-2 + - adi,adis16507-3 + + then: + properties: + adi,sync-mode: + minimum: 0 + maximum: 2 + + - if: + properties: + adi,sync-mode: + enum: [1, 2, 3] + + then: + dependencies: + adi,sync-mode: [ clocks ] + +examples: + - | + #include + spi { + #address-cells = <1>; + #size-cells = <0>; + + adis16475: adis16475-3@0 { + compatible = "adi,adis16475-3"; + reg = <0>; + spi-cpha; + spi-cpol; + spi-max-frequency = <2000000>; + interrupts = <4 IRQ_TYPE_EDGE_RISING>; + interrupt-parent = <&gpio>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/light/amstaos,tsl2563.yaml b/Documentation/devicetree/bindings/iio/light/amstaos,tsl2563.yaml new file mode 100644 index 000000000000..efd2eba5f23c --- /dev/null +++ b/Documentation/devicetree/bindings/iio/light/amstaos,tsl2563.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/light/amstaos,tsl2563.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMS TAOS TSL2563 ambient light sensor + +maintainers: + - Sebastian Reichel + +description: | + Ambient light sensor with an i2c interface. + +properties: + compatible: + enum: + - amstaos,tsl2560 + - amstaos,tsl2561 + - amstaos,tsl2562 + - amstaos,tsl2563 + + reg: + maxItems: 1 + + amstaos,cover-comp-gain: + description: Multiplier for gain compensation + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [1, 16] + +required: + - compatible + - reg + +examples: + - | + i2c { + + #address-cells = <1>; + #size-cells = <0>; + + light-sensor@29 { + compatible = "amstaos,tsl2563"; + reg = <0x29>; + amstaos,cover-comp-gain = <16>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/light/tsl2563.txt b/Documentation/devicetree/bindings/iio/light/tsl2563.txt deleted file mode 100644 index f91e809e736e..000000000000 --- a/Documentation/devicetree/bindings/iio/light/tsl2563.txt +++ /dev/null @@ -1,19 +0,0 @@ -* AMS TAOS TSL2563 ambient light sensor - -Required properties: - - - compatible : should be "amstaos,tsl2563" - - reg : the I2C address of the sensor - -Optional properties: - - - amstaos,cover-comp-gain : integer used as multiplier for gain - compensation (default = 1) - -Example: - -tsl2563@29 { - compatible = "amstaos,tsl2563"; - reg = <0x29>; - amstaos,cover-comp-gain = <16>; -}; diff --git a/Documentation/devicetree/bindings/iio/light/vcnl4000.txt b/Documentation/devicetree/bindings/iio/light/vcnl4000.txt deleted file mode 100644 index 955af4555c90..000000000000 --- a/Documentation/devicetree/bindings/iio/light/vcnl4000.txt +++ /dev/null @@ -1,24 +0,0 @@ -VISHAY VCNL4000 - Ambient Light and proximity sensor - -This driver supports the VCNL4000/10/20/40 and VCNL4200 chips - -Required properties: - - -compatible: must be one of : - vishay,vcnl4000 - vishay,vcnl4010 - vishay,vcnl4020 - vishay,vcnl4040 - vishay,vcnl4200 - - -reg: I2C address of the sensor, should be one from below based on the model: - 0x13 - 0x51 - 0x60 - -Example: - -light-sensor@51 { - compatible = "vishay,vcnl4200"; - reg = <0x51>; -}; diff --git a/Documentation/devicetree/bindings/iio/light/vishay,vcnl4000.yaml b/Documentation/devicetree/bindings/iio/light/vishay,vcnl4000.yaml new file mode 100644 index 000000000000..da8f2e872535 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/light/vishay,vcnl4000.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/light/vishay,vcnl4000.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: VISHAY VCNL4000 ambient light and proximity sensor + +maintainers: + - Peter Meerwald + +description: | + Ambient light sensing with proximity detection over an i2c + interface. + +allOf: + - $ref: ../common.yaml# + +properties: + compatible: + enum: + - vishay,vcnl4000 + - vishay,vcnl4010 + - vishay,vcnl4020 + - vishay,vcnl4040 + - vishay,vcnl4200 + reg: + maxItems: 1 + + proximity-near-level: true + +required: + - compatible + - reg + +additionalProperties: false + +examples: +- | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + light-sensor@51 { + compatible = "vishay,vcnl4200"; + reg = <0x51>; + proximity-near-level = <220>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/magnetometer/ak8974.txt b/Documentation/devicetree/bindings/iio/magnetometer/ak8974.txt index baecc4a85197..7f06eff3b504 100644 --- a/Documentation/devicetree/bindings/iio/magnetometer/ak8974.txt +++ b/Documentation/devicetree/bindings/iio/magnetometer/ak8974.txt @@ -2,7 +2,9 @@ Required properties: -- compatible : should be "asahi-kasei,ak8974" +- compatible: + * "asahi-kasei,ak8974" + * "alps,hscdtd008a" - reg : the I2C address of the magnetometer Optional properties: diff --git a/Documentation/devicetree/bindings/iio/proximity/vishay,vcnl3020.yaml b/Documentation/devicetree/bindings/iio/proximity/vishay,vcnl3020.yaml new file mode 100644 index 000000000000..4190253336ec --- /dev/null +++ b/Documentation/devicetree/bindings/iio/proximity/vishay,vcnl3020.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/proximity/vishay,vcnl3020.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Integrated Proximity Sensor With Infrared Emitter + +maintainers: + - Ivan Mikhaylov + +description: | + The VCNL3020 is a fully integrated proximity sensor. Fully integrated means + that the infrared emitter is included in the package. It has 16-bit + resolution. It includes a signal processing IC and features standard I2C + communication interface. It features an interrupt function. + + Specifications about the devices can be found at: + https://www.vishay.com/docs/84150/vcnl3020.pdf + +properties: + compatible: + enum: + - vishay,vcnl3020 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + vdd-supply: + description: Regulator that provides power to the sensor + + vddio-supply: + description: Regulator that provides power to the bus + + vishay,led-current-microamp: + description: + The driver current for the LED used in proximity sensing. + enum: [0, 10000, 20000, 30000, 40000, 50000, 60000, 70000, 80000, 90000, + 100000, 110000, 120000, 130000, 140000, 150000, 160000, 170000, + 180000, 190000, 200000] + default: 20000 + +required: + - compatible + - reg + +examples: + - | + i2c { + + #address-cells = <1>; + #size-cells = <0>; + + proximity@13 { + compatible = "vishay,vcnl3020"; + reg = <0x13>; + vishay,led-current-microamp = <200000>; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/st-sensors.txt b/Documentation/devicetree/bindings/iio/st-sensors.txt index 0ef64a444479..3213599c5071 100644 --- a/Documentation/devicetree/bindings/iio/st-sensors.txt +++ b/Documentation/devicetree/bindings/iio/st-sensors.txt @@ -50,6 +50,7 @@ Accelerometers: - st,lis3dhh - st,lis3de - st,lis2de12 +- st,lis2hh12 Gyroscopes: - st,l3g4200d-gyro diff --git a/Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml b/Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml new file mode 100644 index 000000000000..ff09550ad959 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/fsl,imx8m-noc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic i.MX bus frequency device + +maintainers: + - Leonard Crestez + +description: | + The i.MX SoC family has multiple buses for which clock frequency (and + sometimes voltage) can be adjusted. + + Some of those buses expose register areas mentioned in the memory maps as GPV + ("Global Programmers View") but not all. Access to this area might be denied + for normal (non-secure) world. + + The buses are based on externally licensed IPs such as ARM NIC-301 and + Arteris FlexNOC but DT bindings are specific to the integration of these bus + interconnect IPs into imx SOCs. + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,imx8mn-nic + - fsl,imx8mm-nic + - fsl,imx8mq-nic + - const: fsl,imx8m-nic + - items: + - enum: + - fsl,imx8mn-noc + - fsl,imx8mm-noc + - fsl,imx8mq-noc + - const: fsl,imx8m-noc + - const: fsl,imx8m-nic + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + operating-points-v2: true + opp-table: true + + fsl,ddrc: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: + Phandle to DDR Controller. + + '#interconnect-cells': + description: + If specified then also act as an interconnect provider. Should only be + set once per soc on the main noc. + const: 1 + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + #include + + noc: interconnect@32700000 { + compatible = "fsl,imx8mm-noc", "fsl,imx8m-noc"; + reg = <0x32700000 0x100000>; + clocks = <&clk IMX8MM_CLK_NOC>; + #interconnect-cells = <1>; + fsl,ddrc = <&ddrc>; + + operating-points-v2 = <&noc_opp_table>; + noc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-133M { + opp-hz = /bits/ 64 <133333333>; + }; + opp-800M { + opp-hz = /bits/ 64 <800000000>; + }; + }; + }; + + ddrc: memory-controller@3d400000 { + compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; + reg = <0x3d400000 0x400000>; + clock-names = "core", "pll", "alt", "apb"; + clocks = <&clk IMX8MM_CLK_DRAM_CORE>, + <&clk IMX8MM_DRAM_PLL>, + <&clk IMX8MM_CLK_DRAM_ALT>, + <&clk IMX8MM_CLK_DRAM_APB>; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt index 3cab7336a326..5682b2010e50 100644 --- a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt @@ -9,13 +9,16 @@ Required properties: "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl + "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl - reg: Should contain the physical address of the GPIO module's registers. - gpio-controller: Marks the device node as a GPIO controller. - #gpio-cells : Should be two. The first cell is the pin number and the second cell is used to specify optional parameters: - bit 0 specifies polarity (0 for normal, 1 for inverted) - interrupts : The interrupt outputs from the controller. One interrupt per - individual bank followed by the "all banks" interrupt. + individual bank followed by the "all banks" interrupt. For BCM7211, an + additional set of per-bank interrupt line and an "all banks" wake-up + interrupt may be specified. - interrupt-controller: Marks the device node as an interrupt controller. - #interrupt-cells : Should be 2. The first cell is the GPIO number. diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt index 32a8a8fa7805..00912449237b 100644 --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt @@ -2,8 +2,8 @@ Microsemi Ocelot pin controller Device Tree Bindings ---------------------------------------------------- Required properties: - - compatible : Should be "mscc,ocelot-pinctrl" or - "mscc,jaguar2-pinctrl" + - compatible : Should be "mscc,ocelot-pinctrl", + "mscc,jaguar2-pinctrl" or "microchip,sparx5-pinctrl" - reg : Address and length of the register set for the device - gpio-controller : Indicates this device is a GPIO controller - #gpio-cells : Must be 2. diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml new file mode 100644 index 000000000000..6dc3b52f47cd --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml @@ -0,0 +1,147 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SM8250 TLMM block + +maintainers: + - Bjorn Andersson + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + SM8250 platform. + +properties: + compatible: + const: qcom,sm8250-pinctrl + + reg: + minItems: 3 + maxItems: 3 + + reg-names: + items: + - const: "west" + - const: "south" + - const: "north" + + interrupts: + description: Specifies the TLMM summary IRQ + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + description: + Specifies the PIN numbers and Flags, as defined in defined in + include/dt-bindings/interrupt-controller/irq.h + const: 2 + + gpio-controller: true + + '#gpio-cells': + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + + wakeup-parent: + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '^.*$': + if: + type: object + then: + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$" + - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ aoss_cti, atest, audio_ref, cam_mclk, cci_async, cci_i2c, + cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng, + cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, + ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gpio, + ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0, + mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1, + mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws, + mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, pci_e0, pci_e1, + pci_e2, phase_flag, pll_bist, pll_bypassnl, pll_clk, pll_reset, + pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qspi0, qspi1, qspi2, qspi3, + qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13, qup14, + qup15, qup16, qup17, qup18, qup19, qup2, qup3, qup4, qup5, qup6, + qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40, sdc41, + sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, tgu_ch0, tgu_ch1, + tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, tsif0_clk, tsif0_data, + tsif0_en, tsif0_error, tsif0_sync, tsif1_clk, tsif1_data, tsif1_en, + tsif1_error, tsif1_sync, usb2phy_ac, usb_phy, vsense_trigger ] + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + required: + - pins + - function + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + pinctrl@1f00000 { + compatible = "qcom,sm8250-pinctrl"; + reg = <0x0f100000 0x300000>, + <0x0f500000 0x300000>, + <0x0f900000 0x300000>; + reg-names = "west", "south", "north"; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 180>; + wakeup-parent = <&pdc>; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt index 6eada23eaa31..b68613188c19 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt @@ -13,6 +13,7 @@ Required Properties: - "renesas,pfc-emev2": for EMEV2 (EMMA Mobile EV2) compatible pin-controller. - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller. - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller. + - "renesas,pfc-r8a7742": for R8A7742 (RZ/G1H) compatible pin-controller. - "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller. - "renesas,pfc-r8a7744": for R8A7744 (RZ/G1N) compatible pin-controller. - "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller. diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt index 2113cfaa26e6..d3eae61a340d 100644 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt @@ -110,8 +110,8 @@ pinctrl@20008000 { uart2 { uart2_xfer: uart2-xfer { - rockchip,pins = , - ; + rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>, + <1 RK_PB1 1 &pcfg_pull_default>; }; }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml index 1f6e51891ddc..0857cbeeb43c 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml @@ -36,6 +36,9 @@ properties: pins-are-numbered: true hwlocks: true + interrupts: + maxItems: 1 + st,syscfg: description: Should be phandle/offset/mask - Phandle to the syscon node which includes IRQ mux selection. diff --git a/Documentation/devicetree/bindings/serial/nxp,sc16is7xx.txt b/Documentation/devicetree/bindings/serial/nxp,sc16is7xx.txt index c1091a923a89..0fa8e3e43bf8 100644 --- a/Documentation/devicetree/bindings/serial/nxp,sc16is7xx.txt +++ b/Documentation/devicetree/bindings/serial/nxp,sc16is7xx.txt @@ -21,6 +21,8 @@ Optional properties: the second cell is used to specify the GPIO polarity: 0 = active high, 1 = active low. +- irda-mode-ports: An array that lists the indices of the port that + should operate in IrDA mode. Example: sc16is750: sc16is750@51 { @@ -55,6 +57,8 @@ Optional properties: the second cell is used to specify the GPIO polarity: 0 = active high, 1 = active low. +- irda-mode-ports: An array that lists the indices of the port that + should operate in IrDA mode. Example: sc16is750: sc16is750@0 { diff --git a/Documentation/devicetree/bindings/serial/rs485.yaml b/Documentation/devicetree/bindings/serial/rs485.yaml index 8141e4aad530..fe90569475e1 100644 --- a/Documentation/devicetree/bindings/serial/rs485.yaml +++ b/Documentation/devicetree/bindings/serial/rs485.yaml @@ -41,4 +41,8 @@ properties: rs485-rx-during-tx: description: enables the receiving of data even while sending data. $ref: /schemas/types.yaml#/definitions/flag + + rs485-term-gpios: + description: GPIO pin to enable RS485 bus termination. + maxItems: 1 ... diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml index ff2f49fe322c..32a5e1e30833 100644 --- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml +++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml @@ -29,6 +29,14 @@ properties: reg: maxItems: 1 + reg-io-width: + description: | + The size (in bytes) of the IO accesses that should be performed + on the device. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [ 1, 4 ] + clocks: minItems: 2 maxItems: 5 diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml index 238c44192d31..75b8521eb7cb 100644 --- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml +++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml @@ -48,6 +48,12 @@ properties: minItems: 1 maxItems: 2 + cts-gpios: + maxItems: 1 + + rts-gpios: + maxItems: 1 + wakeup-source: true rs485-rts-delay: true @@ -55,6 +61,14 @@ properties: linux,rs485-enabled-at-boot-time: true rs485-rx-during-tx: true +if: + required: + - st,hw-flow-ctrl +then: + properties: + cts-gpios: false + rts-gpios: false + required: - compatible - reg diff --git a/Documentation/driver-api/driver-model/devres.rst b/Documentation/driver-api/driver-model/devres.rst index fc242ed4bde5..644078332354 100644 --- a/Documentation/driver-api/driver-model/devres.rst +++ b/Documentation/driver-api/driver-model/devres.rst @@ -284,21 +284,13 @@ I2C IIO devm_iio_device_alloc() - devm_iio_device_free() devm_iio_device_register() - devm_iio_device_unregister() devm_iio_kfifo_allocate() - devm_iio_kfifo_free() devm_iio_triggered_buffer_setup() - devm_iio_triggered_buffer_cleanup() devm_iio_trigger_alloc() - devm_iio_trigger_free() devm_iio_trigger_register() - devm_iio_trigger_unregister() devm_iio_channel_get() - devm_iio_channel_release() devm_iio_channel_get_all() - devm_iio_channel_release_all() INPUT devm_input_allocate_device() diff --git a/Documentation/driver-api/driver-model/driver.rst b/Documentation/driver-api/driver-model/driver.rst index 63887b813005..7d5040f6a3d8 100644 --- a/Documentation/driver-api/driver-model/driver.rst +++ b/Documentation/driver-api/driver-model/driver.rst @@ -4,7 +4,6 @@ Device Drivers See the kerneldoc for the struct device_driver. - Allocation ~~~~~~~~~~ @@ -167,9 +166,26 @@ the driver to that device. A driver's probe() may return a negative errno value to indicate that the driver did not bind to this device, in which case it should have -released all resources it allocated:: +released all resources it allocated. - void (*sync_state)(struct device *dev); +Optionally, probe() may return -EPROBE_DEFER if the driver depends on +resources that are not yet available (e.g., supplied by a driver that +hasn't initialized yet). The driver core will put the device onto the +deferred probe list and will try to call it again later. If a driver +must defer, it should return -EPROBE_DEFER as early as possible to +reduce the amount of time spent on setup work that will need to be +unwound and reexecuted at a later time. + +.. warning:: + -EPROBE_DEFER must not be returned if probe() has already created + child devices, even if those child devices are removed again + in a cleanup path. If -EPROBE_DEFER is returned after a child + device has been registered, it may result in an infinite loop of + .probe() calls to the same driver. + +:: + + void (*sync_state) (struct device *dev); sync_state is called only once for a device. It's called when all the consumer devices of the device have successfully probed. The list of consumers of the @@ -212,6 +228,8 @@ over management of devices from the bootloader, the usage of sync_state() is not restricted to that. Use it whenever it makes sense to take an action after all the consumers of a device have probed:: +:: + int (*remove) (struct device *dev); remove is called to unbind a driver from a device. This may be @@ -224,11 +242,15 @@ not. It should free any resources allocated specifically for the device; i.e. anything in the device's driver_data field. If the device is still present, it should quiesce the device and place -it into a supported low-power state:: +it into a supported low-power state. + +:: int (*suspend) (struct device *dev, pm_message_t state); -suspend is called to put the device in a low power state:: +suspend is called to put the device in a low power state. + +:: int (*resume) (struct device *dev); diff --git a/Documentation/driver-api/iio/triggers.rst b/Documentation/driver-api/iio/triggers.rst index 5c2156de6284..dfd7ba3eabde 100644 --- a/Documentation/driver-api/iio/triggers.rst +++ b/Documentation/driver-api/iio/triggers.rst @@ -4,9 +4,7 @@ Triggers * struct :c:type:`iio_trigger` — industrial I/O trigger device * :c:func:`devm_iio_trigger_alloc` — Resource-managed iio_trigger_alloc -* :c:func:`devm_iio_trigger_free` — Resource-managed iio_trigger_free * :c:func:`devm_iio_trigger_register` — Resource-managed iio_trigger_register -* :c:func:`devm_iio_trigger_unregister` — Resource-managed iio_trigger_unregister * :c:func:`iio_trigger_validate_own_device` — Check if a trigger and IIO device belong to the same device diff --git a/Documentation/driver-api/soundwire/stream.rst b/Documentation/driver-api/soundwire/stream.rst index 8bceece51554..1b386076402c 100644 --- a/Documentation/driver-api/soundwire/stream.rst +++ b/Documentation/driver-api/soundwire/stream.rst @@ -75,8 +75,33 @@ Slaves are using single port. :: | (Data) | +---------------+ +Example 4: Stereo Stream with L and R channels is rendered by +Master. Both of the L and R channels are received by two different +Slaves. Master and both Slaves are using single port handling +L+R. Each Slave device processes the L + R data locally, typically +based on static configuration or dynamic orientation, and may drive +one or more speakers. :: -Example 4: Stereo Stream with L and R channel is rendered by two different + +---------------+ Clock Signal +---------------+ + | Master +---------+------------------------+ Slave | + | Interface | | | Interface | + | | | | 1 | + | | | Data Signal | | + | L + R +---+------------------------------+ L + R | + | (Data) | | | Data Direction | (Data) | + +---------------+ | | +-------------> +---------------+ + | | + | | + | | +---------------+ + | +----------------------> | Slave | + | | Interface | + | | 2 | + | | | + +----------------------------> | L + R | + | (Data) | + +---------------+ + +Example 5: Stereo Stream with L and R channel is rendered by two different Ports of the Master and is received by only single Port of the Slave interface. :: @@ -101,7 +126,7 @@ interface. :: +--------------------+ | | +----------------+ -Example 5: Stereo Stream with L and R channel is rendered by 2 Masters, each +Example 6: Stereo Stream with L and R channel is rendered by 2 Masters, each rendering one channel, and is received by two different Slaves, each receiving one channel. Both Masters and both Slaves are using single port. :: @@ -123,12 +148,70 @@ receiving one channel. Both Masters and both Slaves are using single port. :: | (Data) | Data Direction | (Data) | +---------------+ +-----------------------> +---------------+ -Note: In multi-link cases like above, to lock, one would acquire a global +Example 7: Stereo Stream with L and R channel is rendered by 2 +Masters, each rendering both channels. Each Slave receives L + R. This +is the same application as Example 4 but with Slaves placed on +separate links. :: + + +---------------+ Clock Signal +---------------+ + | Master +----------------------------------+ Slave | + | Interface | | Interface | + | 1 | | 1 | + | | Data Signal | | + | L + R +----------------------------------+ L + R | + | (Data) | Data Direction | (Data) | + +---------------+ +-----------------------> +---------------+ + + +---------------+ Clock Signal +---------------+ + | Master +----------------------------------+ Slave | + | Interface | | Interface | + | 2 | | 2 | + | | Data Signal | | + | L + R +----------------------------------+ L + R | + | (Data) | Data Direction | (Data) | + +---------------+ +-----------------------> +---------------+ + +Example 8: 4-channel Stream is rendered by 2 Masters, each rendering a +2 channels. Each Slave receives 2 channels. :: + + +---------------+ Clock Signal +---------------+ + | Master +----------------------------------+ Slave | + | Interface | | Interface | + | 1 | | 1 | + | | Data Signal | | + | L1 + R1 +----------------------------------+ L1 + R1 | + | (Data) | Data Direction | (Data) | + +---------------+ +-----------------------> +---------------+ + + +---------------+ Clock Signal +---------------+ + | Master +----------------------------------+ Slave | + | Interface | | Interface | + | 2 | | 2 | + | | Data Signal | | + | L2 + R2 +----------------------------------+ L2 + R2 | + | (Data) | Data Direction | (Data) | + +---------------+ +-----------------------> +---------------+ + +Note1: In multi-link cases like above, to lock, one would acquire a global lock and then go on locking bus instances. But, in this case the caller framework(ASoC DPCM) guarantees that stream operations on a card are always serialized. So, there is no race condition and hence no need for global lock. +Note2: A Slave device may be configured to receive all channels +transmitted on a link for a given Stream (Example 4) or just a subset +of the data (Example 3). The configuration of the Slave device is not +handled by a SoundWire subsystem API, but instead by the +snd_soc_dai_set_tdm_slot() API. The platform or machine driver will +typically configure which of the slots are used. For Example 4, the +same slots would be used by all Devices, while for Example 3 the Slave +Device1 would use e.g. Slot 0 and Slave device2 slot 1. + +Note3: Multiple Sink ports can extract the same information for the +same bitSlots in the SoundWire frame, however multiple Source ports +shall be configured with different bitSlot configurations. This is the +same limitation as with I2S/PCM TDM usages. + SoundWire Stream Management flow ================================ diff --git a/Documentation/driver-api/soundwire/summary.rst b/Documentation/driver-api/soundwire/summary.rst index 8193125a2bfb..01dcb954f6d7 100644 --- a/Documentation/driver-api/soundwire/summary.rst +++ b/Documentation/driver-api/soundwire/summary.rst @@ -101,10 +101,11 @@ Following is the Bus API to register the SoundWire Bus: .. code-block:: c - int sdw_add_bus_master(struct sdw_bus *bus) + int sdw_bus_master_add(struct sdw_bus *bus, + struct device *parent, + struct fwnode_handle) { - if (!bus->dev) - return -ENODEV; + sdw_master_device_add(bus, parent, fwnode); mutex_init(&bus->lock); INIT_LIST_HEAD(&bus->slaves); diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst index 094fc8aacd8e..978c4af416a4 100644 --- a/Documentation/fpga/dfl.rst +++ b/Documentation/fpga/dfl.rst @@ -118,6 +118,11 @@ More functions are exposed through sysfs management information (current temperature, thresholds, threshold status, etc.). + Performance reporting + performance counters are exposed through perf PMU APIs. Standard perf tool + can be used to monitor all available perf events. Please see performance + counter section below for more detailed information. + FIU - PORT ========== @@ -378,6 +383,85 @@ The device nodes used for ioctl() or mmap() can be referenced through:: /sys/class/fpga_region///dev +Performance Counters +==================== +Performance reporting is one private feature implemented in FME. It could +supports several independent, system-wide, device counter sets in hardware to +monitor and count for performance events, including "basic", "cache", "fabric", +"vtd" and "vtd_sip" counters. Users could use standard perf tool to monitor +FPGA cache hit/miss rate, transaction number, interface clock counter of AFU +and other FPGA performance events. + +Different FPGA devices may have different counter sets, depending on hardware +implementation. E.g., some discrete FPGA cards don't have any cache. User could +use "perf list" to check which perf events are supported by target hardware. + +In order to allow user to use standard perf API to access these performance +counters, driver creates a perf PMU, and related sysfs interfaces in +/sys/bus/event_source/devices/dfl_fme* to describe available perf events and +configuration options. + +The "format" directory describes the format of the config field of struct +perf_event_attr. There are 3 bitfields for config: "evtype" defines which type +the perf event belongs to; "event" is the identity of the event within its +category; "portid" is introduced to decide counters set to monitor on FPGA +overall data or a specific port. + +The "events" directory describes the configuration templates for all available +events which can be used with perf tool directly. For example, fab_mmio_read +has the configuration "event=0x06,evtype=0x02,portid=0xff", which shows this +event belongs to fabric type (0x02), the local event id is 0x06 and it is for +overall monitoring (portid=0xff). + +Example usage of perf:: + + $# perf list |grep dfl_fme + + dfl_fme0/fab_mmio_read/ [Kernel PMU event] + <...> + dfl_fme0/fab_port_mmio_read,portid=?/ [Kernel PMU event] + <...> + + $# perf stat -a -e dfl_fme0/fab_mmio_read/ + or + $# perf stat -a -e dfl_fme0/event=0x06,evtype=0x02,portid=0xff/ + or + $# perf stat -a -e dfl_fme0/config=0xff2006/ + +Another example, fab_port_mmio_read monitors mmio read of a specific port. So +its configuration template is "event=0x06,evtype=0x01,portid=?". The portid +should be explicitly set. + +Its usage of perf:: + + $# perf stat -a -e dfl_fme0/fab_port_mmio_read,portid=0x0/ + or + $# perf stat -a -e dfl_fme0/event=0x06,evtype=0x02,portid=0x0/ + or + $# perf stat -a -e dfl_fme0/config=0x2006/ + +Please note for fabric counters, overall perf events (fab_*) and port perf +events (fab_port_*) actually share one set of counters in hardware, so it can't +monitor both at the same time. If this set of counters is configured to monitor +overall data, then per port perf data is not supported. See below example:: + + $# perf stat -e dfl_fme0/fab_mmio_read/,dfl_fme0/fab_port_mmio_write,\ + portid=0/ sleep 1 + + Performance counter stats for 'system wide': + + 3 dfl_fme0/fab_mmio_read/ + dfl_fme0/fab_port_mmio_write,portid=0x0/ + + 1.001750904 seconds time elapsed + +The driver also provides a "cpumask" sysfs attribute, which contains only one +CPU id used to access these perf events. Counting on multiple CPU is not allowed +since they are system-wide counters on FPGA device. + +The current driver does not support sampling. So "perf record" is unsupported. + + Add new FIUs support ==================== It's possible that developers made some new function blocks (FIUs) under this diff --git a/Documentation/trace/coresight/coresight-ect.rst b/Documentation/trace/coresight/coresight-ect.rst index a93e52abcf46..a68732c5c6d6 100644 --- a/Documentation/trace/coresight/coresight-ect.rst +++ b/Documentation/trace/coresight/coresight-ect.rst @@ -73,7 +73,7 @@ capable of generating or using trigger signals.:: >$ ls /sys/bus/coresight/devices/etm0/cti_cpu0 channels ctmid enable nr_trigger_cons mgmt power powered regs - subsystem triggers0 triggers1 uevent + connections subsystem triggers0 triggers1 uevent *Key file items are:-* * ``enable``: enables/disables the CTI. Read to determine current state. @@ -89,6 +89,9 @@ capable of generating or using trigger signals.:: * ``channels``: Contains the channel API - CTI main programming interface. * ``regs``: Gives access to the raw programmable CTI regs. * ``mgmt``: the standard CoreSight management registers. + * ``connections``: Links to connected *CoreSight* devices. The number of + links can be 0 to ``nr_trigger_cons``. Actual number given by ``nr_links`` + in this directory. triggers directories diff --git a/Documentation/trace/coresight/coresight.rst b/Documentation/trace/coresight/coresight.rst index 108600ee1e12..0b73acb44efa 100644 --- a/Documentation/trace/coresight/coresight.rst +++ b/Documentation/trace/coresight/coresight.rst @@ -241,6 +241,91 @@ to the newer scheme, to give a confirmation that what you see on your system is not unexpected. One must use the "names" as they appear on the system under specified locations. +Topology Representation +----------------------- + +Each CoreSight component has a ``connections`` directory which will contain +links to other CoreSight components. This allows the user to explore the trace +topology and for larger systems, determine the most appropriate sink for a +given source. The connection information can also be used to establish +which CTI devices are connected to a given component. This directory contains a +``nr_links`` attribute detailing the number of links in the directory. + +For an ETM source, in this case ``etm0`` on a Juno platform, a typical +arrangement will be:: + + linaro-developer:~# ls - l /sys/bus/coresight/devices/etm0/connections + cti_cpu0 -> ../../../23020000.cti/cti_cpu0 + nr_links + out:0 -> ../../../230c0000.funnel/funnel2 + +Following the out port to ``funnel2``:: + + linaro-developer:~# ls -l /sys/bus/coresight/devices/funnel2/connections + in:0 -> ../../../23040000.etm/etm0 + in:1 -> ../../../23140000.etm/etm3 + in:2 -> ../../../23240000.etm/etm4 + in:3 -> ../../../23340000.etm/etm5 + nr_links + out:0 -> ../../../20040000.funnel/funnel0 + +And again to ``funnel0``:: + + linaro-developer:~# ls -l /sys/bus/coresight/devices/funnel0/connections + in:0 -> ../../../220c0000.funnel/funnel1 + in:1 -> ../../../230c0000.funnel/funnel2 + nr_links + out:0 -> ../../../20010000.etf/tmc_etf0 + +Finding the first sink ``tmc_etf0``. This can be used to collect data +as a sink, or as a link to propagate further along the chain:: + + linaro-developer:~# ls -l /sys/bus/coresight/devices/tmc_etf0/connections + cti_sys0 -> ../../../20020000.cti/cti_sys0 + in:0 -> ../../../20040000.funnel/funnel0 + nr_links + out:0 -> ../../../20150000.funnel/funnel4 + +via ``funnel4``:: + + linaro-developer:~# ls -l /sys/bus/coresight/devices/funnel4/connections + in:0 -> ../../../20010000.etf/tmc_etf0 + in:1 -> ../../../20140000.etf/tmc_etf1 + nr_links + out:0 -> ../../../20120000.replicator/replicator0 + +and a ``replicator0``:: + + linaro-developer:~# ls -l /sys/bus/coresight/devices/replicator0/connections + in:0 -> ../../../20150000.funnel/funnel4 + nr_links + out:0 -> ../../../20030000.tpiu/tpiu0 + out:1 -> ../../../20070000.etr/tmc_etr0 + +Arriving at the final sink in the chain, ``tmc_etr0``:: + + linaro-developer:~# ls -l /sys/bus/coresight/devices/tmc_etr0/connections + cti_sys0 -> ../../../20020000.cti/cti_sys0 + in:0 -> ../../../20120000.replicator/replicator0 + nr_links + +As described below, when using sysfs it is sufficient to enable a sink and +a source for successful trace. The framework will correctly enable all +intermediate links as required. + +Note: ``cti_sys0`` appears in two of the connections lists above. +CTIs can connect to multiple devices and are arranged in a star topology +via the CTM. See (:doc:`coresight-ect`) [#fourth]_ for further details. +Looking at this device we see 4 connections:: + + linaro-developer:~# ls -l /sys/bus/coresight/devices/cti_sys0/connections + nr_links + stm0 -> ../../../20100000.stm/stm0 + tmc_etf0 -> ../../../20010000.etf/tmc_etf0 + tmc_etr0 -> ../../../20070000.etr/tmc_etr0 + tpiu0 -> ../../../20030000.tpiu/tpiu0 + + How to use the tracer modules ----------------------------- diff --git a/Documentation/w1/slaves/w1_therm.rst b/Documentation/w1/slaves/w1_therm.rst index 90531c340a07..cc4edae17751 100644 --- a/Documentation/w1/slaves/w1_therm.rst +++ b/Documentation/w1/slaves/w1_therm.rst @@ -26,20 +26,31 @@ W1_THERM_DS1825 0x3B W1_THERM_DS28EA00 0x42 ==================== ==== -Support is provided through the sysfs w1_slave file. Each open and +Support is provided through the sysfs w1_slave file. Each open and read sequence will initiate a temperature conversion then provide two -lines of ASCII output. The first line contains the nine hex bytes +lines of ASCII output. The first line contains the nine hex bytes read along with a calculated crc value and YES or NO if it matched. -If the crc matched the returned values are retained. The second line +If the crc matched the returned values are retained. The second line displays the retained values along with a temperature in millidegrees Centigrade after t=. -Parasite powered devices are limited to one slave performing a -temperature conversion at a time. If none of the devices are parasite -powered it would be possible to convert all the devices at the same -time and then go back to read individual sensors. That isn't -currently supported. The driver also doesn't support reduced -precision (which would also reduce the conversion time) when reading values. +Alternatively, temperature can be read using temperature sysfs, it +return only temperature in millidegrees Centigrade. + +A bulk read of all devices on the bus could be done writing 'trigger' +in the therm_bulk_read sysfs entry at w1_bus_master level. This will +sent the convert command on all devices on the bus, and if parasite +powered devices are detected on the bus (and strong pullup is enable +in the module), it will drive the line high during the longer conversion +time required by parasited powered device on the line. Reading +therm_bulk_read will return 0 if no bulk conversion pending, +-1 if at least one sensor still in conversion, 1 if conversion is complete +but at least one sensor value has not been read yet. Result temperature is +then accessed by reading the temperature sysfs entry of each device, which +may return empty if conversion is still in progress. Note that if a bulk +read is sent but one sensor is not read immediately, the next access to +temperature on this device will return the temperature measured at the +time of issue of the bulk read command (not the current temperature). Writing a value between 9 and 12 to the sysfs w1_slave file will change the precision of the sensor for the next readings. This value is in (volatile) @@ -49,6 +60,27 @@ To store the current precision configuration into EEPROM, the value 0 has to be written to the sysfs w1_slave file. Since the EEPROM has a limited amount of writes (>50k), this command should be used wisely. +Alternatively, resolution can be set or read (value from 9 to 12) using the +dedicated resolution sysfs entry on each device. This sysfs entry is not +present for devices not supporting this feature. Driver will adjust the +correct conversion time for each device regarding to its resolution setting. +In particular, strong pullup will be applied if required during the conversion +duration. + +The write-only sysfs entry eeprom is an alternative for EEPROM operations: + * 'save': will save device RAM to EEPROM + * 'restore': will restore EEPROM data in device RAM. + +ext_power syfs entry allow tho check the power status of each device. + * '0': device parasite powered + * '1': device externally powered + +sysfs alarms allow read or write TH and TL (Temperature High an Low) alarms. +Values shall be space separated and in the device range (typical -55 degC +to 125 degC). Values are integer as they are store in a 8bit register in +the device. Lowest value is automatically put to TL.Once set, alarms could +be search at master level. + The module parameter strong_pullup can be set to 0 to disable the strong pullup, 1 to enable autodetection or 2 to force strong pullup. In case of autodetection, the driver will use the "READ POWER SUPPLY" diff --git a/MAINTAINERS b/MAINTAINERS index 93769328576d..5e7c42fecb2a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -294,6 +294,7 @@ F: drivers/gpio/gpio-104-idio-16.c ACCES 104-QUAD-8 DRIVER M: William Breathitt Gray +M: Syed Nayyar Waris L: linux-iio@vger.kernel.org S: Maintained F: Documentation/ABI/testing/sysfs-bus-counter-104-quad-8 @@ -1042,6 +1043,14 @@ W: http://ez.analog.com/community/linux-device-drivers F: Documentation/devicetree/bindings/iio/imu/adi,adis16460.yaml F: drivers/iio/imu/adis16460.c +ANALOG DEVICES INC ADIS16475 DRIVER +M: Nuno Sa +L: linux-iio@vger.kernel.org +W: http://ez.analog.com/community/linux-device-drivers +S: Supported +F: drivers/iio/imu/adis16475.c +F: Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml + ANALOG DEVICES INC ADM1177 DRIVER M: Beniamin Bia M: Michael Hennerich @@ -7094,6 +7103,7 @@ GASKET DRIVER FRAMEWORK M: Rob Springer M: Todd Poynor M: Ben Chan +M: Richard Yeh S: Maintained F: drivers/staging/gasket/ @@ -13492,8 +13502,9 @@ F: drivers/pinctrl/qcom/ PIN CONTROLLER - RENESAS M: Geert Uytterhoeven L: linux-renesas-soc@vger.kernel.org -S: Maintained +S: Supported T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git sh-pfc +F: Documentation/devicetree/bindings/pinctrl/renesas,* F: drivers/pinctrl/pinctrl-rz* F: drivers/pinctrl/sh-pfc/ diff --git a/arch/alpha/kernel/setup.c b/arch/alpha/kernel/setup.c index f19aa577354b..6fa802c495b4 100644 --- a/arch/alpha/kernel/setup.c +++ b/arch/alpha/kernel/setup.c @@ -430,6 +430,15 @@ register_cpus(void) arch_initcall(register_cpus); +#ifdef CONFIG_MAGIC_SYSRQ +static const struct sysrq_key_op srm_sysrq_reboot_op = { + .handler = machine_halt, + .help_msg = "reboot(b)", + .action_msg = "Resetting", + .enable_mask = SYSRQ_ENABLE_BOOT, +}; +#endif + void __init setup_arch(char **cmdline_p) { @@ -550,8 +559,8 @@ setup_arch(char **cmdline_p) /* If we're using SRM, make sysrq-b halt back to the prom, not auto-reboot. */ if (alpha_using_srm) { - struct sysrq_key_op *op = __sysrq_get_key_op('b'); - op->handler = (void *) machine_halt; + unregister_sysrq_key('b', __sysrq_reboot_op); + register_sysrq_key('b', &srm_sysrq_reboot_op); } #endif diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index d8c44d3ca15a..f52de8f7806a 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -539,12 +539,12 @@ firmware { svc { - compatible = "intel,stratix10-svc"; + compatible = "intel,agilex-svc"; method = "smc"; memory-region = <&service_reserved>; fpga_mgr: fpga-mgr { - compatible = "intel,stratix10-soc-fpga-mgr"; + compatible = "intel,agilex-soc-fpga-mgr"; }; }; }; diff --git a/arch/mips/kernel/sysrq.c b/arch/mips/kernel/sysrq.c index e5a2a6ab71ac..9c1a2019113b 100644 --- a/arch/mips/kernel/sysrq.c +++ b/arch/mips/kernel/sysrq.c @@ -52,7 +52,7 @@ static void sysrq_handle_tlbdump(int key) #endif } -static struct sysrq_key_op sysrq_tlbdump_op = { +static const struct sysrq_key_op sysrq_tlbdump_op = { .handler = sysrq_handle_tlbdump, .help_msg = "show-tlbs(x)", .action_msg = "Show TLB entries", diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c index a001711863e5..bfd152933376 100644 --- a/arch/powerpc/xmon/xmon.c +++ b/arch/powerpc/xmon/xmon.c @@ -3919,7 +3919,7 @@ static void sysrq_handle_xmon(int key) xmon_init(0); } -static struct sysrq_key_op sysrq_xmon_op = { +static const struct sysrq_key_op sysrq_xmon_op = { .handler = sysrq_handle_xmon, .help_msg = "xmon(x)", .action_msg = "Entering xmon", diff --git a/arch/sparc/kernel/process_64.c b/arch/sparc/kernel/process_64.c index 4282116e28e7..423011e60982 100644 --- a/arch/sparc/kernel/process_64.c +++ b/arch/sparc/kernel/process_64.c @@ -313,7 +313,7 @@ static void sysrq_handle_globreg(int key) trigger_all_cpu_backtrace(); } -static struct sysrq_key_op sparc_globalreg_op = { +static const struct sysrq_key_op sparc_globalreg_op = { .handler = sysrq_handle_globreg, .help_msg = "global-regs(y)", .action_msg = "Show Global CPU Regs", @@ -388,7 +388,7 @@ static void sysrq_handle_globpmu(int key) pmu_snapshot_all_cpus(); } -static struct sysrq_key_op sparc_globalpmu_op = { +static const struct sysrq_key_op sparc_globalpmu_op = { .handler = sysrq_handle_globpmu, .help_msg = "global-pmu(x)", .action_msg = "Show Global PMU Regs", diff --git a/drivers/android/binderfs.c b/drivers/android/binderfs.c index 9ecad74183a3..7cf566aafe1f 100644 --- a/drivers/android/binderfs.c +++ b/drivers/android/binderfs.c @@ -650,7 +650,7 @@ static int binderfs_fill_super(struct super_block *sb, struct fs_context *fc) struct binderfs_info *info; struct binderfs_mount_opts *ctx = fc->fs_private; struct inode *inode = NULL; - struct binderfs_device device_info = { 0 }; + struct binderfs_device device_info = {}; const char *name; size_t len; @@ -747,7 +747,7 @@ static const struct fs_context_operations binderfs_fs_context_ops = { static int binderfs_init_fs_context(struct fs_context *fc) { - struct binderfs_mount_opts *ctx = fc->fs_private; + struct binderfs_mount_opts *ctx; ctx = kzalloc(sizeof(struct binderfs_mount_opts), GFP_KERNEL); if (!ctx) diff --git a/drivers/base/base.h b/drivers/base/base.h index 40fb069a8a7e..95c22c0f9036 100644 --- a/drivers/base/base.h +++ b/drivers/base/base.h @@ -153,6 +153,7 @@ extern char *make_class_name(const char *name, struct kobject *kobj); extern int devres_release_all(struct device *dev); extern void device_block_probing(void); extern void device_unblock_probing(void); +extern void driver_deferred_probe_force_trigger(void); /* /sys/devices directory */ extern struct kset *devices_kset; diff --git a/drivers/base/core.c b/drivers/base/core.c index 6be64c4f7307..1ce27c7e1b99 100644 --- a/drivers/base/core.c +++ b/drivers/base/core.c @@ -49,6 +49,9 @@ static LIST_HEAD(wait_for_suppliers); static DEFINE_MUTEX(wfs_lock); static LIST_HEAD(deferred_sync); static unsigned int defer_sync_state_count = 1; +static unsigned int defer_fw_devlink_count; +static DEFINE_MUTEX(defer_fw_devlink_lock); +static bool fw_devlink_is_permissive(void); #ifdef CONFIG_SRCU static DEFINE_MUTEX(device_links_lock); @@ -529,7 +532,7 @@ static void device_link_add_missing_supplier_links(void) int ret = fwnode_call_int_op(dev->fwnode, add_links, dev); if (!ret) list_del_init(&dev->links.needs_suppliers); - else if (ret != -ENODEV) + else if (ret != -ENODEV || fw_devlink_is_permissive()) dev->links.need_for_probe = false; } mutex_unlock(&wfs_lock); @@ -643,9 +646,17 @@ static void device_links_missing_supplier(struct device *dev) { struct device_link *link; - list_for_each_entry(link, &dev->links.suppliers, c_node) - if (link->status == DL_STATE_CONSUMER_PROBE) + list_for_each_entry(link, &dev->links.suppliers, c_node) { + if (link->status != DL_STATE_CONSUMER_PROBE) + continue; + + if (link->supplier->links.status == DL_DEV_DRIVER_BOUND) { WRITE_ONCE(link->status, DL_STATE_AVAILABLE); + } else { + WARN_ON(!(link->flags & DL_FLAG_SYNC_STATE_ONLY)); + WRITE_ONCE(link->status, DL_STATE_DORMANT); + } + } } /** @@ -684,11 +695,11 @@ int device_links_check_suppliers(struct device *dev) device_links_write_lock(); list_for_each_entry(link, &dev->links.suppliers, c_node) { - if (!(link->flags & DL_FLAG_MANAGED) || - link->flags & DL_FLAG_SYNC_STATE_ONLY) + if (!(link->flags & DL_FLAG_MANAGED)) continue; - if (link->status != DL_STATE_AVAILABLE) { + if (link->status != DL_STATE_AVAILABLE && + !(link->flags & DL_FLAG_SYNC_STATE_ONLY)) { device_links_missing_supplier(dev); ret = -EPROBE_DEFER; break; @@ -949,11 +960,21 @@ static void __device_links_no_driver(struct device *dev) if (!(link->flags & DL_FLAG_MANAGED)) continue; - if (link->flags & DL_FLAG_AUTOREMOVE_CONSUMER) + if (link->flags & DL_FLAG_AUTOREMOVE_CONSUMER) { device_link_drop_managed(link); - else if (link->status == DL_STATE_CONSUMER_PROBE || - link->status == DL_STATE_ACTIVE) + continue; + } + + if (link->status != DL_STATE_CONSUMER_PROBE && + link->status != DL_STATE_ACTIVE) + continue; + + if (link->supplier->links.status == DL_DEV_DRIVER_BOUND) { WRITE_ONCE(link->status, DL_STATE_AVAILABLE); + } else { + WARN_ON(!(link->flags & DL_FLAG_SYNC_STATE_ONLY)); + WRITE_ONCE(link->status, DL_STATE_DORMANT); + } } dev->links.status = DL_DEV_NO_DRIVER; @@ -1162,6 +1183,150 @@ static void device_links_purge(struct device *dev) device_links_write_unlock(); } +static u32 fw_devlink_flags = DL_FLAG_AUTOPROBE_CONSUMER; +static int __init fw_devlink_setup(char *arg) +{ + if (!arg) + return -EINVAL; + + if (strcmp(arg, "off") == 0) { + fw_devlink_flags = 0; + } else if (strcmp(arg, "permissive") == 0) { + fw_devlink_flags = DL_FLAG_SYNC_STATE_ONLY; + } else if (strcmp(arg, "on") == 0) { + fw_devlink_flags = DL_FLAG_AUTOPROBE_CONSUMER; + } else if (strcmp(arg, "rpm") == 0) { + fw_devlink_flags = DL_FLAG_AUTOPROBE_CONSUMER | + DL_FLAG_PM_RUNTIME; + } + return 0; +} +early_param("fw_devlink", fw_devlink_setup); + +u32 fw_devlink_get_flags(void) +{ + return fw_devlink_flags; +} + +static bool fw_devlink_is_permissive(void) +{ + return fw_devlink_flags == DL_FLAG_SYNC_STATE_ONLY; +} + +static void fw_devlink_link_device(struct device *dev) +{ + int fw_ret; + + if (!fw_devlink_flags) + return; + + mutex_lock(&defer_fw_devlink_lock); + if (!defer_fw_devlink_count) + device_link_add_missing_supplier_links(); + + /* + * The device's fwnode not having add_links() doesn't affect if other + * consumers can find this device as a supplier. So, this check is + * intentionally placed after device_link_add_missing_supplier_links(). + */ + if (!fwnode_has_op(dev->fwnode, add_links)) + goto out; + + /* + * If fw_devlink is being deferred, assume all devices have mandatory + * suppliers they need to link to later. Then, when the fw_devlink is + * resumed, all these devices will get a chance to try and link to any + * suppliers they have. + */ + if (!defer_fw_devlink_count) { + fw_ret = fwnode_call_int_op(dev->fwnode, add_links, dev); + if (fw_ret == -ENODEV && fw_devlink_is_permissive()) + fw_ret = -EAGAIN; + } else { + fw_ret = -ENODEV; + } + + if (fw_ret == -ENODEV) + device_link_wait_for_mandatory_supplier(dev); + else if (fw_ret) + device_link_wait_for_optional_supplier(dev); + +out: + mutex_unlock(&defer_fw_devlink_lock); +} + +/** + * fw_devlink_pause - Pause parsing of fwnode to create device links + * + * Calling this function defers any fwnode parsing to create device links until + * fw_devlink_resume() is called. Both these functions are ref counted and the + * caller needs to match the calls. + * + * While fw_devlink is paused: + * - Any device that is added won't have its fwnode parsed to create device + * links. + * - The probe of the device will also be deferred during this period. + * - Any devices that were already added, but waiting for suppliers won't be + * able to link to newly added devices. + * + * Once fw_devlink_resume(): + * - All the fwnodes that was not parsed will be parsed. + * - All the devices that were deferred probing will be reattempted if they + * aren't waiting for any more suppliers. + * + * This pair of functions, is mainly meant to optimize the parsing of fwnodes + * when a lot of devices that need to link to each other are added in a short + * interval of time. For example, adding all the top level devices in a system. + * + * For example, if N devices are added and: + * - All the consumers are added before their suppliers + * - All the suppliers of the N devices are part of the N devices + * + * Then: + * + * - With the use of fw_devlink_pause() and fw_devlink_resume(), each device + * will only need one parsing of its fwnode because it is guaranteed to find + * all the supplier devices already registered and ready to link to. It won't + * have to do another pass later to find one or more suppliers it couldn't + * find in the first parse of the fwnode. So, we'll only need O(N) fwnode + * parses. + * + * - Without the use of fw_devlink_pause() and fw_devlink_resume(), we would + * end up doing O(N^2) parses of fwnodes because every device that's added is + * guaranteed to trigger a parse of the fwnode of every device added before + * it. This O(N^2) parse is made worse by the fact that when a fwnode of a + * device is parsed, all it descendant devices might need to have their + * fwnodes parsed too (even if the devices themselves aren't added). + */ +void fw_devlink_pause(void) +{ + mutex_lock(&defer_fw_devlink_lock); + defer_fw_devlink_count++; + mutex_unlock(&defer_fw_devlink_lock); +} + +/** fw_devlink_resume - Resume parsing of fwnode to create device links + * + * This function is used in conjunction with fw_devlink_pause() and is ref + * counted. See documentation for fw_devlink_pause() for more details. + */ +void fw_devlink_resume(void) +{ + mutex_lock(&defer_fw_devlink_lock); + if (!defer_fw_devlink_count) { + WARN(true, "Unmatched fw_devlink pause/resume!"); + goto out; + } + + defer_fw_devlink_count--; + if (defer_fw_devlink_count) + goto out; + + device_link_add_missing_supplier_links(); + driver_deferred_probe_force_trigger(); +out: + mutex_unlock(&defer_fw_devlink_lock); +} /* Device links support end. */ int (*platform_notify)(struct device *dev) = NULL; @@ -2364,36 +2529,6 @@ static int device_private_init(struct device *dev) return 0; } -static u32 fw_devlink_flags = DL_FLAG_AUTOPROBE_CONSUMER; -static int __init fw_devlink_setup(char *arg) -{ - if (!arg) - return -EINVAL; - - if (strcmp(arg, "off") == 0) { - fw_devlink_flags = 0; - } else if (strcmp(arg, "permissive") == 0) { - fw_devlink_flags = DL_FLAG_SYNC_STATE_ONLY; - } else if (strcmp(arg, "on") == 0) { - fw_devlink_flags = DL_FLAG_AUTOPROBE_CONSUMER; - } else if (strcmp(arg, "rpm") == 0) { - fw_devlink_flags = DL_FLAG_AUTOPROBE_CONSUMER | - DL_FLAG_PM_RUNTIME; - } - return 0; -} -early_param("fw_devlink", fw_devlink_setup); - -u32 fw_devlink_get_flags(void) -{ - return fw_devlink_flags; -} - -static bool fw_devlink_is_permissive(void) -{ - return fw_devlink_flags == DL_FLAG_SYNC_STATE_ONLY; -} - /** * device_add - add device to device hierarchy. * @dev: device. @@ -2426,9 +2561,8 @@ int device_add(struct device *dev) struct device *parent; struct kobject *kobj; struct class_interface *class_intf; - int error = -EINVAL, fw_ret; + int error = -EINVAL; struct kobject *glue_dir = NULL; - bool is_fwnode_dev = false; dev = get_device(dev); if (!dev) @@ -2526,11 +2660,6 @@ int device_add(struct device *dev) kobject_uevent(&dev->kobj, KOBJ_ADD); - if (dev->fwnode && !dev->fwnode->dev) { - dev->fwnode->dev = dev; - is_fwnode_dev = true; - } - /* * Check if any of the other devices (consumers) have been waiting for * this device (supplier) to be added so that they can create a device @@ -2539,19 +2668,13 @@ int device_add(struct device *dev) * This needs to happen after device_pm_add() because device_link_add() * requires the supplier be registered before it's called. * - * But this also needs to happe before bus_probe_device() to make sure + * But this also needs to happen before bus_probe_device() to make sure * waiting consumers can link to it before the driver is bound to the * device and the driver sync_state callback is called for this device. */ - device_link_add_missing_supplier_links(); - - if (fw_devlink_flags && is_fwnode_dev && - fwnode_has_op(dev->fwnode, add_links)) { - fw_ret = fwnode_call_int_op(dev->fwnode, add_links, dev); - if (fw_ret == -ENODEV && !fw_devlink_is_permissive()) - device_link_wait_for_mandatory_supplier(dev); - else if (fw_ret) - device_link_wait_for_optional_supplier(dev); + if (dev->fwnode && !dev->fwnode->dev) { + dev->fwnode->dev = dev; + fw_devlink_link_device(dev); } bus_probe_device(dev); diff --git a/drivers/base/dd.c b/drivers/base/dd.c index 94037be7f5d7..9a1d940342ac 100644 --- a/drivers/base/dd.c +++ b/drivers/base/dd.c @@ -164,6 +164,11 @@ static void driver_deferred_probe_trigger(void) if (!driver_deferred_probe_enable) return; + driver_deferred_probe_force_trigger(); +} + +void driver_deferred_probe_force_trigger(void) +{ /* * A successful probe means that all the devices in the pending list * should be triggered to be reprobed. Move all the deferred devices @@ -254,12 +259,12 @@ __setup("deferred_probe_timeout=", deferred_probe_timeout_setup); int driver_deferred_probe_check_state(struct device *dev) { if (!IS_ENABLED(CONFIG_MODULES) && initcalls_done) { - dev_warn(dev, "ignoring dependency for device, assuming no driver"); + dev_warn(dev, "ignoring dependency for device, assuming no driver\n"); return -ENODEV; } if (!driver_deferred_probe_timeout && initcalls_done) { - dev_warn(dev, "deferred probe timeout, ignoring dependency"); + dev_warn(dev, "deferred probe timeout, ignoring dependency\n"); return -ETIMEDOUT; } @@ -275,7 +280,7 @@ static void deferred_probe_timeout_work_func(struct work_struct *work) flush_work(&deferred_probe_work); list_for_each_entry_safe(private, p, &deferred_probe_pending_list, deferred_probe) - dev_info(private->device, "deferred probe pending"); + dev_info(private->device, "deferred probe pending\n"); wake_up(&probe_timeout_waitqueue); } static DECLARE_DELAYED_WORK(deferred_probe_timeout_work, deferred_probe_timeout_work_func); @@ -336,7 +341,7 @@ bool device_is_bound(struct device *dev) static void driver_bound(struct device *dev) { if (device_is_bound(dev)) { - printk(KERN_WARNING "%s: device %s already bound\n", + pr_warn("%s: device %s already bound\n", __func__, kobject_name(&dev->kobj)); return; } @@ -505,8 +510,8 @@ re_probe: } if (driver_sysfs_add(dev)) { - printk(KERN_ERR "%s: driver_sysfs_add(%s) failed\n", - __func__, dev_name(dev)); + pr_err("%s: driver_sysfs_add(%s) failed\n", + __func__, dev_name(dev)); goto probe_failed; } @@ -597,9 +602,8 @@ pinctrl_bind_failed: break; default: /* driver matched but the probe failed */ - printk(KERN_WARNING - "%s: probe of %s failed with error %d\n", - drv->name, dev_name(dev), ret); + pr_warn("%s: probe of %s failed with error %d\n", + drv->name, dev_name(dev), ret); } /* * Ignore errors returned by ->probe so that the next driver can try @@ -624,8 +628,8 @@ static int really_probe_debug(struct device *dev, struct device_driver *drv) ret = really_probe(dev, drv); rettime = ktime_get(); delta = ktime_sub(rettime, calltime); - printk(KERN_DEBUG "probe of %s returned %d after %lld usecs\n", - dev_name(dev), ret, (s64) ktime_to_us(delta)); + pr_debug("probe of %s returned %d after %lld usecs\n", + dev_name(dev), ret, (s64) ktime_to_us(delta)); return ret; } @@ -713,8 +717,7 @@ static inline bool cmdline_requested_async_probing(const char *drv_name) static int __init save_async_options(char *buf) { if (strlen(buf) >= ASYNC_DRV_NAMES_MAX_LEN) - printk(KERN_WARNING - "Too long list of driver names for 'driver_async_probe'!\n"); + pr_warn("Too long list of driver names for 'driver_async_probe'!\n"); strlcpy(async_probe_drv_names, buf, ASYNC_DRV_NAMES_MAX_LEN); return 0; @@ -789,7 +792,7 @@ static int __device_attach_driver(struct device_driver *drv, void *_data) dev_dbg(dev, "Device match requests probe deferral\n"); driver_deferred_probe_add(dev); } else if (ret < 0) { - dev_dbg(dev, "Bus failed to match device: %d", ret); + dev_dbg(dev, "Bus failed to match device: %d\n", ret); return ret; } /* ret > 0 means positive match */ @@ -1022,7 +1025,7 @@ static int __driver_attach(struct device *dev, void *data) dev_dbg(dev, "Device match requests probe deferral\n"); driver_deferred_probe_add(dev); } else if (ret < 0) { - dev_dbg(dev, "Bus failed to match device: %d", ret); + dev_dbg(dev, "Bus failed to match device: %d\n", ret); return ret; } /* ret > 0 means positive match */ diff --git a/drivers/base/firmware_loader/fallback.c b/drivers/base/firmware_loader/fallback.c index 1e9c96e3ed63..5327bfc6ba71 100644 --- a/drivers/base/firmware_loader/fallback.c +++ b/drivers/base/firmware_loader/fallback.c @@ -9,6 +9,7 @@ #include #include #include +#include #include "fallback.h" #include "firmware.h" @@ -17,6 +18,8 @@ * firmware fallback mechanism */ +MODULE_IMPORT_NS(FIRMWARE_LOADER_PRIVATE); + extern struct firmware_fallback_config fw_fallback_config; /* These getters are vetted to use int properly */ @@ -460,7 +463,7 @@ static const struct attribute_group *fw_dev_attr_groups[] = { static struct fw_sysfs * fw_create_instance(struct firmware *firmware, const char *fw_name, - struct device *device, enum fw_opt opt_flags) + struct device *device, u32 opt_flags) { struct fw_sysfs *fw_sysfs; struct device *f_dev; @@ -493,7 +496,7 @@ exit: * In charge of constructing a sysfs fallback interface for firmware loading. **/ static int fw_load_sysfs_fallback(struct fw_sysfs *fw_sysfs, - enum fw_opt opt_flags, long timeout) + u32 opt_flags, long timeout) { int retval = 0; struct device *f_dev = &fw_sysfs->dev; @@ -547,7 +550,7 @@ err_put_dev: static int fw_load_from_user_helper(struct firmware *firmware, const char *name, struct device *device, - enum fw_opt opt_flags) + u32 opt_flags) { struct fw_sysfs *fw_sysfs; long timeout; @@ -588,7 +591,7 @@ out_unlock: return ret; } -static bool fw_force_sysfs_fallback(enum fw_opt opt_flags) +static bool fw_force_sysfs_fallback(u32 opt_flags) { if (fw_fallback_config.force_sysfs_fallback) return true; @@ -597,7 +600,7 @@ static bool fw_force_sysfs_fallback(enum fw_opt opt_flags) return true; } -static bool fw_run_sysfs_fallback(enum fw_opt opt_flags) +static bool fw_run_sysfs_fallback(u32 opt_flags) { int ret; @@ -640,7 +643,7 @@ static bool fw_run_sysfs_fallback(enum fw_opt opt_flags) **/ int firmware_fallback_sysfs(struct firmware *fw, const char *name, struct device *device, - enum fw_opt opt_flags, + u32 opt_flags, int ret) { if (!fw_run_sysfs_fallback(opt_flags)) diff --git a/drivers/base/firmware_loader/fallback.h b/drivers/base/firmware_loader/fallback.h index 06f4577733a8..2afdb6adb23f 100644 --- a/drivers/base/firmware_loader/fallback.h +++ b/drivers/base/firmware_loader/fallback.h @@ -33,7 +33,7 @@ struct firmware_fallback_config { #ifdef CONFIG_FW_LOADER_USER_HELPER int firmware_fallback_sysfs(struct firmware *fw, const char *name, struct device *device, - enum fw_opt opt_flags, + u32 opt_flags, int ret); void kill_pending_fw_fallback_reqs(bool only_kill_custom); @@ -45,7 +45,7 @@ void unregister_sysfs_loader(void); #else /* CONFIG_FW_LOADER_USER_HELPER */ static inline int firmware_fallback_sysfs(struct firmware *fw, const char *name, struct device *device, - enum fw_opt opt_flags, + u32 opt_flags, int ret) { /* Keep carrying over the same error */ @@ -67,10 +67,10 @@ static inline void unregister_sysfs_loader(void) #endif /* CONFIG_FW_LOADER_USER_HELPER */ #ifdef CONFIG_EFI_EMBEDDED_FIRMWARE -int firmware_fallback_platform(struct fw_priv *fw_priv, enum fw_opt opt_flags); +int firmware_fallback_platform(struct fw_priv *fw_priv, u32 opt_flags); #else static inline int firmware_fallback_platform(struct fw_priv *fw_priv, - enum fw_opt opt_flags) + u32 opt_flags) { return -ENOENT; } diff --git a/drivers/base/firmware_loader/fallback_platform.c b/drivers/base/firmware_loader/fallback_platform.c index c88c745590fe..cdd2c9a9f38a 100644 --- a/drivers/base/firmware_loader/fallback_platform.c +++ b/drivers/base/firmware_loader/fallback_platform.c @@ -8,7 +8,7 @@ #include "fallback.h" #include "firmware.h" -int firmware_fallback_platform(struct fw_priv *fw_priv, enum fw_opt opt_flags) +int firmware_fallback_platform(struct fw_priv *fw_priv, u32 opt_flags) { const u8 *data; size_t size; diff --git a/drivers/base/firmware_loader/fallback_table.c b/drivers/base/firmware_loader/fallback_table.c index a182e318bd09..46a731dede6f 100644 --- a/drivers/base/firmware_loader/fallback_table.c +++ b/drivers/base/firmware_loader/fallback_table.c @@ -21,7 +21,7 @@ struct firmware_fallback_config fw_fallback_config = { .loading_timeout = 60, .old_timeout = 60, }; -EXPORT_SYMBOL_GPL(fw_fallback_config); +EXPORT_SYMBOL_NS_GPL(fw_fallback_config, FIRMWARE_LOADER_PRIVATE); #ifdef CONFIG_SYSCTL struct ctl_table firmware_config_table[] = { diff --git a/drivers/base/firmware_loader/firmware.h b/drivers/base/firmware_loader/firmware.h index 25836a6afc9f..933e2192fbe8 100644 --- a/drivers/base/firmware_loader/firmware.h +++ b/drivers/base/firmware_loader/firmware.h @@ -136,8 +136,7 @@ static inline void fw_state_done(struct fw_priv *fw_priv) __fw_state_set(fw_priv, FW_STATUS_DONE); } -int assign_fw(struct firmware *fw, struct device *device, - enum fw_opt opt_flags); +int assign_fw(struct firmware *fw, struct device *device, u32 opt_flags); #ifdef CONFIG_FW_LOADER_PAGED_BUF void fw_free_paged_buf(struct fw_priv *fw_priv); diff --git a/drivers/base/firmware_loader/main.c b/drivers/base/firmware_loader/main.c index 76f79913916d..ca871b13524e 100644 --- a/drivers/base/firmware_loader/main.c +++ b/drivers/base/firmware_loader/main.c @@ -210,7 +210,7 @@ static struct fw_priv *__lookup_fw_priv(const char *fw_name) static int alloc_lookup_fw_priv(const char *fw_name, struct firmware_cache *fwc, struct fw_priv **fw_priv, void *dbuf, - size_t size, enum fw_opt opt_flags) + size_t size, u32 opt_flags) { struct fw_priv *tmp; @@ -548,9 +548,6 @@ static void firmware_free_data(const struct firmware *fw) static void fw_set_page_data(struct fw_priv *fw_priv, struct firmware *fw) { fw->priv = fw_priv; -#ifdef CONFIG_FW_LOADER_USER_HELPER - fw->pages = fw_priv->pages; -#endif fw->size = fw_priv->size; fw->data = fw_priv->data; @@ -635,8 +632,7 @@ static int fw_add_devm_name(struct device *dev, const char *name) } #endif -int assign_fw(struct firmware *fw, struct device *device, - enum fw_opt opt_flags) +int assign_fw(struct firmware *fw, struct device *device, u32 opt_flags) { struct fw_priv *fw_priv = fw->priv; int ret; @@ -687,7 +683,7 @@ int assign_fw(struct firmware *fw, struct device *device, static int _request_firmware_prepare(struct firmware **firmware_p, const char *name, struct device *device, void *dbuf, size_t size, - enum fw_opt opt_flags) + u32 opt_flags) { struct firmware *firmware; struct fw_priv *fw_priv; @@ -753,7 +749,7 @@ static void fw_abort_batch_reqs(struct firmware *fw) static int _request_firmware(const struct firmware **firmware_p, const char *name, struct device *device, void *buf, size_t size, - enum fw_opt opt_flags) + u32 opt_flags) { struct firmware *fw = NULL; int ret; @@ -990,7 +986,7 @@ struct firmware_work { struct device *device; void *context; void (*cont)(const struct firmware *fw, void *context); - enum fw_opt opt_flags; + u32 opt_flags; }; static void request_firmware_work_func(struct work_struct *work) diff --git a/drivers/base/platform.c b/drivers/base/platform.c index 4b49641effa1..c0d0a5490ac6 100644 --- a/drivers/base/platform.c +++ b/drivers/base/platform.c @@ -682,7 +682,7 @@ EXPORT_SYMBOL_GPL(platform_device_unregister); struct platform_device *platform_device_register_full( const struct platform_device_info *pdevinfo) { - int ret = -ENOMEM; + int ret; struct platform_device *pdev; pdev = platform_device_alloc(pdevinfo->name, pdevinfo->id); @@ -863,6 +863,8 @@ int __init_or_module __platform_driver_probe(struct platform_driver *drv, /* temporary section violation during probe() */ drv->probe = probe; retval = code = __platform_driver_register(drv, module); + if (retval) + return retval; /* * Fixup that section violation, being paranoid about code scanning @@ -987,7 +989,7 @@ EXPORT_SYMBOL_GPL(__platform_register_drivers); * @drivers: an array of drivers to unregister * @count: the number of drivers to unregister * - * Unegisters platform drivers specified by an array. This is typically used + * Unregisters platform drivers specified by an array. This is typically used * to complement an earlier call to platform_register_drivers(). Drivers are * unregistered in the reverse order in which they were registered. */ diff --git a/drivers/base/property.c b/drivers/base/property.c index 5f35c0ccf5e0..1e6d75e65938 100644 --- a/drivers/base/property.c +++ b/drivers/base/property.c @@ -708,14 +708,23 @@ struct fwnode_handle *device_get_next_child_node(struct device *dev, struct fwnode_handle *child) { struct acpi_device *adev = ACPI_COMPANION(dev); - struct fwnode_handle *fwnode = NULL; + struct fwnode_handle *fwnode = NULL, *next; if (dev->of_node) fwnode = &dev->of_node->fwnode; else if (adev) fwnode = acpi_fwnode_handle(adev); - return fwnode_get_next_child_node(fwnode, child); + /* Try to find a child in primary fwnode */ + next = fwnode_get_next_child_node(fwnode, child); + if (next) + return next; + + /* When no more children in primary, continue with secondary */ + if (!IS_ERR_OR_NULL(fwnode->secondary)) + next = fwnode_get_next_child_node(fwnode->secondary, child); + + return next; } EXPORT_SYMBOL_GPL(device_get_next_child_node); diff --git a/drivers/base/soc.c b/drivers/base/soc.c index 4af11a423475..a5bae551167d 100644 --- a/drivers/base/soc.c +++ b/drivers/base/soc.c @@ -46,7 +46,7 @@ static umode_t soc_attribute_mode(struct kobject *kobj, struct attribute *attr, int index) { - struct device *dev = container_of(kobj, struct device, kobj); + struct device *dev = kobj_to_dev(kobj); struct soc_device *soc_dev = container_of(dev, struct soc_device, dev); if ((attr == &dev_attr_machine.attr) diff --git a/drivers/base/swnode.c b/drivers/base/swnode.c index 2079937ddb51..e5eb27375416 100644 --- a/drivers/base/swnode.c +++ b/drivers/base/swnode.c @@ -712,17 +712,18 @@ EXPORT_SYMBOL_GPL(software_node_register_nodes); * @nodes: Zero terminated array of software nodes to be unregistered * * Unregister multiple software nodes at once. + * + * NOTE: Be careful using this call if the nodes had parent pointers set up in + * them before registering. If so, it is wiser to remove the nodes + * individually, in the correct order (child before parent) instead of relying + * on the sequential order of the list of nodes in the array. */ void software_node_unregister_nodes(const struct software_node *nodes) { - struct swnode *swnode; int i; - for (i = 0; nodes[i].name; i++) { - swnode = software_node_to_swnode(&nodes[i]); - if (swnode) - fwnode_remove_software_node(&swnode->fwnode); - } + for (i = 0; nodes[i].name; i++) + software_node_unregister(&nodes[i]); } EXPORT_SYMBOL_GPL(software_node_unregister_nodes); @@ -789,6 +790,20 @@ int software_node_register(const struct software_node *node) } EXPORT_SYMBOL_GPL(software_node_register); +/** + * software_node_unregister - Unregister static software node + * @node: The software node to be unregistered + */ +void software_node_unregister(const struct software_node *node) +{ + struct swnode *swnode; + + swnode = software_node_to_swnode(node); + if (swnode) + fwnode_remove_software_node(&swnode->fwnode); +} +EXPORT_SYMBOL_GPL(software_node_unregister); + struct fwnode_handle * fwnode_create_software_node(const struct property_entry *properties, const struct fwnode_handle *parent) diff --git a/drivers/bus/mhi/core/boot.c b/drivers/bus/mhi/core/boot.c index ebad5eb48e5a..0b38014d040e 100644 --- a/drivers/bus/mhi/core/boot.c +++ b/drivers/bus/mhi/core/boot.c @@ -43,10 +43,7 @@ void mhi_rddm_prepare(struct mhi_controller *mhi_cntrl, lower_32_bits(mhi_buf->dma_addr)); mhi_write_reg(mhi_cntrl, base, BHIE_RXVECSIZE_OFFS, mhi_buf->len); - sequence_id = prandom_u32() & BHIE_RXVECSTATUS_SEQNUM_BMSK; - - if (unlikely(!sequence_id)) - sequence_id = 1; + sequence_id = MHI_RANDOM_U32_NONZERO(BHIE_RXVECSTATUS_SEQNUM_BMSK); mhi_write_reg_field(mhi_cntrl, base, BHIE_RXVECDB_OFFS, BHIE_RXVECDB_SEQNUM_BMSK, BHIE_RXVECDB_SEQNUM_SHFT, @@ -121,7 +118,8 @@ static int __mhi_download_rddm_in_panic(struct mhi_controller *mhi_cntrl) ee = mhi_get_exec_env(mhi_cntrl); } - dev_dbg(dev, "Waiting for image download completion, current EE: %s\n", + dev_dbg(dev, + "Waiting for RDDM image download via BHIe, current EE:%s\n", TO_MHI_EXEC_STR(ee)); while (retry--) { @@ -152,11 +150,14 @@ static int __mhi_download_rddm_in_panic(struct mhi_controller *mhi_cntrl) int mhi_download_rddm_img(struct mhi_controller *mhi_cntrl, bool in_panic) { void __iomem *base = mhi_cntrl->bhie; + struct device *dev = &mhi_cntrl->mhi_dev->dev; u32 rx_status; if (in_panic) return __mhi_download_rddm_in_panic(mhi_cntrl); + dev_dbg(dev, "Waiting for RDDM image download via BHIe\n"); + /* Wait for the image download to complete */ wait_event_timeout(mhi_cntrl->state_event, mhi_read_reg_field(mhi_cntrl, base, @@ -174,8 +175,10 @@ static int mhi_fw_load_amss(struct mhi_controller *mhi_cntrl, const struct mhi_buf *mhi_buf) { void __iomem *base = mhi_cntrl->bhie; + struct device *dev = &mhi_cntrl->mhi_dev->dev; rwlock_t *pm_lock = &mhi_cntrl->pm_lock; u32 tx_status, sequence_id; + int ret; read_lock_bh(pm_lock); if (!MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) { @@ -183,6 +186,9 @@ static int mhi_fw_load_amss(struct mhi_controller *mhi_cntrl, return -EIO; } + sequence_id = MHI_RANDOM_U32_NONZERO(BHIE_TXVECSTATUS_SEQNUM_BMSK); + dev_dbg(dev, "Starting AMSS download via BHIe. Sequence ID:%u\n", + sequence_id); mhi_write_reg(mhi_cntrl, base, BHIE_TXVECADDR_HIGH_OFFS, upper_32_bits(mhi_buf->dma_addr)); @@ -191,26 +197,25 @@ static int mhi_fw_load_amss(struct mhi_controller *mhi_cntrl, mhi_write_reg(mhi_cntrl, base, BHIE_TXVECSIZE_OFFS, mhi_buf->len); - sequence_id = prandom_u32() & BHIE_TXVECSTATUS_SEQNUM_BMSK; mhi_write_reg_field(mhi_cntrl, base, BHIE_TXVECDB_OFFS, BHIE_TXVECDB_SEQNUM_BMSK, BHIE_TXVECDB_SEQNUM_SHFT, sequence_id); read_unlock_bh(pm_lock); /* Wait for the image download to complete */ - wait_event_timeout(mhi_cntrl->state_event, - MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state) || - mhi_read_reg_field(mhi_cntrl, base, - BHIE_TXVECSTATUS_OFFS, - BHIE_TXVECSTATUS_STATUS_BMSK, - BHIE_TXVECSTATUS_STATUS_SHFT, - &tx_status) || tx_status, - msecs_to_jiffies(mhi_cntrl->timeout_ms)); - - if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) + ret = wait_event_timeout(mhi_cntrl->state_event, + MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state) || + mhi_read_reg_field(mhi_cntrl, base, + BHIE_TXVECSTATUS_OFFS, + BHIE_TXVECSTATUS_STATUS_BMSK, + BHIE_TXVECSTATUS_STATUS_SHFT, + &tx_status) || tx_status, + msecs_to_jiffies(mhi_cntrl->timeout_ms)); + if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state) || + tx_status != BHIE_TXVECSTATUS_STATUS_XFER_COMPL) return -EIO; - return (tx_status == BHIE_TXVECSTATUS_STATUS_XFER_COMPL) ? 0 : -EIO; + return (!ret) ? -ETIMEDOUT : 0; } static int mhi_fw_load_sbl(struct mhi_controller *mhi_cntrl, @@ -239,14 +244,15 @@ static int mhi_fw_load_sbl(struct mhi_controller *mhi_cntrl, goto invalid_pm_state; } - dev_dbg(dev, "Starting SBL download via BHI\n"); + session_id = MHI_RANDOM_U32_NONZERO(BHI_TXDB_SEQNUM_BMSK); + dev_dbg(dev, "Starting SBL download via BHI. Session ID:%u\n", + session_id); mhi_write_reg(mhi_cntrl, base, BHI_STATUS, 0); mhi_write_reg(mhi_cntrl, base, BHI_IMGADDR_HIGH, upper_32_bits(dma_addr)); mhi_write_reg(mhi_cntrl, base, BHI_IMGADDR_LOW, lower_32_bits(dma_addr)); mhi_write_reg(mhi_cntrl, base, BHI_IMGSIZE, size); - session_id = prandom_u32() & BHI_TXDB_SEQNUM_BMSK; mhi_write_reg(mhi_cntrl, base, BHI_IMGTXDB, session_id); read_unlock_bh(pm_lock); @@ -377,30 +383,18 @@ static void mhi_firmware_copy(struct mhi_controller *mhi_cntrl, } } -void mhi_fw_load_worker(struct work_struct *work) +void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl) { - struct mhi_controller *mhi_cntrl; const struct firmware *firmware = NULL; struct image_info *image_info; - struct device *dev; + struct device *dev = &mhi_cntrl->mhi_dev->dev; const char *fw_name; void *buf; dma_addr_t dma_addr; size_t size; int ret; - mhi_cntrl = container_of(work, struct mhi_controller, fw_worker); - dev = &mhi_cntrl->mhi_dev->dev; - - dev_dbg(dev, "Waiting for device to enter PBL from: %s\n", - TO_MHI_EXEC_STR(mhi_cntrl->ee)); - - ret = wait_event_timeout(mhi_cntrl->state_event, - MHI_IN_PBL(mhi_cntrl->ee) || - MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state), - msecs_to_jiffies(mhi_cntrl->timeout_ms)); - - if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) { + if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) { dev_err(dev, "Device MHI is not in valid state\n"); return; } @@ -446,7 +440,12 @@ void mhi_fw_load_worker(struct work_struct *work) release_firmware(firmware); /* Error or in EDL mode, we're done */ - if (ret || mhi_cntrl->ee == MHI_EE_EDL) + if (ret) { + dev_err(dev, "MHI did not load SBL, ret:%d\n", ret); + return; + } + + if (mhi_cntrl->ee == MHI_EE_EDL) return; write_lock_irq(&mhi_cntrl->pm_lock); @@ -474,8 +473,10 @@ fw_load_ee_pthru: if (!mhi_cntrl->fbc_download) return; - if (ret) + if (ret) { + dev_err(dev, "MHI did not enter READY state\n"); goto error_read; + } /* Wait for the SBL event */ ret = wait_event_timeout(mhi_cntrl->state_event, @@ -493,6 +494,8 @@ fw_load_ee_pthru: ret = mhi_fw_load_amss(mhi_cntrl, /* Vector table is the last entry */ &image_info->mhi_buf[image_info->entries - 1]); + if (ret) + dev_err(dev, "MHI did not load AMSS, ret:%d\n", ret); release_firmware(firmware); diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c index 1f8c82603179..e43a190a7a36 100644 --- a/drivers/bus/mhi/core/init.c +++ b/drivers/bus/mhi/core/init.c @@ -34,6 +34,8 @@ const char * const dev_state_tran_str[DEV_ST_TRANSITION_MAX] = { [DEV_ST_TRANSITION_READY] = "READY", [DEV_ST_TRANSITION_SBL] = "SBL", [DEV_ST_TRANSITION_MISSION_MODE] = "MISSION_MODE", + [DEV_ST_TRANSITION_SYS_ERR] = "SYS_ERR", + [DEV_ST_TRANSITION_DISABLE] = "DISABLE", }; const char * const mhi_state_str[MHI_STATE_MAX] = { @@ -835,8 +837,6 @@ int mhi_register_controller(struct mhi_controller *mhi_cntrl, spin_lock_init(&mhi_cntrl->transition_lock); spin_lock_init(&mhi_cntrl->wlock); INIT_WORK(&mhi_cntrl->st_worker, mhi_pm_st_worker); - INIT_WORK(&mhi_cntrl->syserr_worker, mhi_pm_sys_err_worker); - INIT_WORK(&mhi_cntrl->fw_worker, mhi_fw_load_worker); init_waitqueue_head(&mhi_cntrl->state_event); mhi_cmd = mhi_cntrl->mhi_cmd; @@ -864,6 +864,10 @@ int mhi_register_controller(struct mhi_controller *mhi_cntrl, mutex_init(&mhi_chan->mutex); init_completion(&mhi_chan->completion); rwlock_init(&mhi_chan->lock); + + /* used in setting bei field of TRE */ + mhi_event = &mhi_cntrl->mhi_event[mhi_chan->er_index]; + mhi_chan->intmod = mhi_event->intmod; } if (mhi_cntrl->bounce_buf) { diff --git a/drivers/bus/mhi/core/internal.h b/drivers/bus/mhi/core/internal.h index 095d95bc0e37..b1f640b75a94 100644 --- a/drivers/bus/mhi/core/internal.h +++ b/drivers/bus/mhi/core/internal.h @@ -386,6 +386,8 @@ enum dev_st_transition { DEV_ST_TRANSITION_READY, DEV_ST_TRANSITION_SBL, DEV_ST_TRANSITION_MISSION_MODE, + DEV_ST_TRANSITION_SYS_ERR, + DEV_ST_TRANSITION_DISABLE, DEV_ST_TRANSITION_MAX, }; @@ -452,6 +454,7 @@ enum mhi_pm_state { #define PRIMARY_CMD_RING 0 #define MHI_DEV_WAKE_DB 127 #define MHI_MAX_MTU 0xffff +#define MHI_RANDOM_U32_NONZERO(bmsk) (prandom_u32_max(bmsk) + 1) enum mhi_er_type { MHI_ER_TYPE_INVALID = 0x0, @@ -586,7 +589,7 @@ enum mhi_ee_type mhi_get_exec_env(struct mhi_controller *mhi_cntrl); int mhi_queue_state_transition(struct mhi_controller *mhi_cntrl, enum dev_st_transition state); void mhi_pm_st_worker(struct work_struct *work); -void mhi_pm_sys_err_worker(struct work_struct *work); +void mhi_pm_sys_err_handler(struct mhi_controller *mhi_cntrl); void mhi_fw_load_worker(struct work_struct *work); int mhi_ready_state_transition(struct mhi_controller *mhi_cntrl); void mhi_ctrl_ev_task(unsigned long data); @@ -627,6 +630,7 @@ int mhi_init_irq_setup(struct mhi_controller *mhi_cntrl); void mhi_deinit_free_irq(struct mhi_controller *mhi_cntrl); void mhi_rddm_prepare(struct mhi_controller *mhi_cntrl, struct image_info *img_info); +void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl); int mhi_prepare_channel(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan); int mhi_init_chan_ctxt(struct mhi_controller *mhi_cntrl, @@ -670,8 +674,7 @@ irqreturn_t mhi_intvec_threaded_handler(int irq_number, void *dev); irqreturn_t mhi_intvec_handler(int irq_number, void *dev); int mhi_gen_tre(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan, - void *buf, void *cb, size_t buf_len, enum mhi_flags flags); - + struct mhi_buf_info *info, enum mhi_flags flags); int mhi_map_single_no_bb(struct mhi_controller *mhi_cntrl, struct mhi_buf_info *buf_info); int mhi_map_single_use_bb(struct mhi_controller *mhi_cntrl, diff --git a/drivers/bus/mhi/core/main.c b/drivers/bus/mhi/core/main.c index 97e06cc586e4..1f622ce6be8b 100644 --- a/drivers/bus/mhi/core/main.c +++ b/drivers/bus/mhi/core/main.c @@ -258,7 +258,7 @@ int mhi_destroy_device(struct device *dev, void *data) return 0; } -static void mhi_notify(struct mhi_device *mhi_dev, enum mhi_callback cb_reason) +void mhi_notify(struct mhi_device *mhi_dev, enum mhi_callback cb_reason) { struct mhi_driver *mhi_drv; @@ -270,6 +270,7 @@ static void mhi_notify(struct mhi_device *mhi_dev, enum mhi_callback cb_reason) if (mhi_drv->status_cb) mhi_drv->status_cb(mhi_dev, cb_reason); } +EXPORT_SYMBOL_GPL(mhi_notify); /* Bind MHI channels to MHI devices */ void mhi_create_devices(struct mhi_controller *mhi_cntrl) @@ -368,30 +369,37 @@ irqreturn_t mhi_irq_handler(int irq_number, void *dev) return IRQ_HANDLED; } -irqreturn_t mhi_intvec_threaded_handler(int irq_number, void *dev) +irqreturn_t mhi_intvec_threaded_handler(int irq_number, void *priv) { - struct mhi_controller *mhi_cntrl = dev; + struct mhi_controller *mhi_cntrl = priv; + struct device *dev = &mhi_cntrl->mhi_dev->dev; enum mhi_state state = MHI_STATE_MAX; enum mhi_pm_state pm_state = 0; enum mhi_ee_type ee = 0; write_lock_irq(&mhi_cntrl->pm_lock); - if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) { - state = mhi_get_mhi_state(mhi_cntrl); - ee = mhi_cntrl->ee; - mhi_cntrl->ee = mhi_get_exec_env(mhi_cntrl); + if (!MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) { + write_unlock_irq(&mhi_cntrl->pm_lock); + goto exit_intvec; } + state = mhi_get_mhi_state(mhi_cntrl); + ee = mhi_cntrl->ee; + mhi_cntrl->ee = mhi_get_exec_env(mhi_cntrl); + dev_dbg(dev, "local ee:%s device ee:%s dev_state:%s\n", + TO_MHI_EXEC_STR(mhi_cntrl->ee), TO_MHI_EXEC_STR(ee), + TO_MHI_STATE_STR(state)); + if (state == MHI_STATE_SYS_ERR) { - dev_dbg(&mhi_cntrl->mhi_dev->dev, "System error detected\n"); + dev_dbg(dev, "System error detected\n"); pm_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_SYS_ERR_DETECT); } write_unlock_irq(&mhi_cntrl->pm_lock); - /* If device in RDDM don't bother processing SYS error */ - if (mhi_cntrl->ee == MHI_EE_RDDM) { - if (mhi_cntrl->ee != ee) { + /* If device supports RDDM don't bother processing SYS error */ + if (mhi_cntrl->rddm_image) { + if (mhi_cntrl->ee == MHI_EE_RDDM && mhi_cntrl->ee != ee) { mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_EE_RDDM); wake_up_all(&mhi_cntrl->state_event); } @@ -405,7 +413,7 @@ irqreturn_t mhi_intvec_threaded_handler(int irq_number, void *dev) if (MHI_IN_PBL(ee)) mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_FATAL_ERROR); else - schedule_work(&mhi_cntrl->syserr_worker); + mhi_pm_sys_err_handler(mhi_cntrl); } exit_intvec: @@ -513,7 +521,10 @@ static int parse_xfer_event(struct mhi_controller *mhi_cntrl, mhi_cntrl->unmap_single(mhi_cntrl, buf_info); result.buf_addr = buf_info->cb_buf; - result.bytes_xferd = xfer_len; + + /* truncate to buf len if xfer_len is larger */ + result.bytes_xferd = + min_t(u16, xfer_len, buf_info->len); mhi_del_ring_element(mhi_cntrl, buf_ring); mhi_del_ring_element(mhi_cntrl, tre_ring); local_rp = tre_ring->rp; @@ -597,7 +608,9 @@ static int parse_rsc_event(struct mhi_controller *mhi_cntrl, result.transaction_status = (ev_code == MHI_EV_CC_OVERFLOW) ? -EOVERFLOW : 0; - result.bytes_xferd = xfer_len; + + /* truncate to buf len if xfer_len is larger */ + result.bytes_xferd = min_t(u16, xfer_len, buf_info->len); result.buf_addr = buf_info->cb_buf; result.dir = mhi_chan->dir; @@ -722,13 +735,18 @@ int mhi_process_ctrl_ev_ring(struct mhi_controller *mhi_cntrl, { enum mhi_pm_state new_state; + /* skip SYS_ERROR handling if RDDM supported */ + if (mhi_cntrl->ee == MHI_EE_RDDM || + mhi_cntrl->rddm_image) + break; + dev_dbg(dev, "System error detected\n"); write_lock_irq(&mhi_cntrl->pm_lock); new_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_SYS_ERR_DETECT); write_unlock_irq(&mhi_cntrl->pm_lock); if (new_state == MHI_PM_SYS_ERR_DETECT) - schedule_work(&mhi_cntrl->syserr_worker); + mhi_pm_sys_err_handler(mhi_cntrl); break; } default: @@ -774,9 +792,18 @@ int mhi_process_ctrl_ev_ring(struct mhi_controller *mhi_cntrl, } case MHI_PKT_TYPE_TX_EVENT: chan = MHI_TRE_GET_EV_CHID(local_rp); - mhi_chan = &mhi_cntrl->mhi_chan[chan]; - parse_xfer_event(mhi_cntrl, local_rp, mhi_chan); - event_quota--; + + WARN_ON(chan >= mhi_cntrl->max_chan); + + /* + * Only process the event ring elements whose channel + * ID is within the maximum supported range. + */ + if (chan < mhi_cntrl->max_chan) { + mhi_chan = &mhi_cntrl->mhi_chan[chan]; + parse_xfer_event(mhi_cntrl, local_rp, mhi_chan); + event_quota--; + } break; default: dev_err(dev, "Unhandled event type: %d\n", type); @@ -819,14 +846,23 @@ int mhi_process_data_event_ring(struct mhi_controller *mhi_cntrl, enum mhi_pkt_type type = MHI_TRE_GET_EV_TYPE(local_rp); chan = MHI_TRE_GET_EV_CHID(local_rp); - mhi_chan = &mhi_cntrl->mhi_chan[chan]; - if (likely(type == MHI_PKT_TYPE_TX_EVENT)) { - parse_xfer_event(mhi_cntrl, local_rp, mhi_chan); - event_quota--; - } else if (type == MHI_PKT_TYPE_RSC_TX_EVENT) { - parse_rsc_event(mhi_cntrl, local_rp, mhi_chan); - event_quota--; + WARN_ON(chan >= mhi_cntrl->max_chan); + + /* + * Only process the event ring elements whose channel + * ID is within the maximum supported range. + */ + if (chan < mhi_cntrl->max_chan) { + mhi_chan = &mhi_cntrl->mhi_chan[chan]; + + if (likely(type == MHI_PKT_TYPE_TX_EVENT)) { + parse_xfer_event(mhi_cntrl, local_rp, mhi_chan); + event_quota--; + } else if (type == MHI_PKT_TYPE_RSC_TX_EVENT) { + parse_rsc_event(mhi_cntrl, local_rp, mhi_chan); + event_quota--; + } } mhi_recycle_ev_ring_element(mhi_cntrl, ev_ring); @@ -896,7 +932,7 @@ void mhi_ctrl_ev_task(unsigned long data) } write_unlock_irq(&mhi_cntrl->pm_lock); if (pm_state == MHI_PM_SYS_ERR_DETECT) - schedule_work(&mhi_cntrl->syserr_worker); + mhi_pm_sys_err_handler(mhi_cntrl); } } @@ -918,9 +954,7 @@ int mhi_queue_skb(struct mhi_device *mhi_dev, enum dma_data_direction dir, struct mhi_chan *mhi_chan = (dir == DMA_TO_DEVICE) ? mhi_dev->ul_chan : mhi_dev->dl_chan; struct mhi_ring *tre_ring = &mhi_chan->tre_ring; - struct mhi_ring *buf_ring = &mhi_chan->buf_ring; - struct mhi_buf_info *buf_info; - struct mhi_tre *mhi_tre; + struct mhi_buf_info buf_info = { }; int ret; /* If MHI host pre-allocates buffers then client drivers cannot queue */ @@ -945,27 +979,15 @@ int mhi_queue_skb(struct mhi_device *mhi_dev, enum dma_data_direction dir, /* Toggle wake to exit out of M2 */ mhi_cntrl->wake_toggle(mhi_cntrl); - /* Generate the TRE */ - buf_info = buf_ring->wp; + buf_info.v_addr = skb->data; + buf_info.cb_buf = skb; + buf_info.len = len; - buf_info->v_addr = skb->data; - buf_info->cb_buf = skb; - buf_info->wp = tre_ring->wp; - buf_info->dir = mhi_chan->dir; - buf_info->len = len; - ret = mhi_cntrl->map_single(mhi_cntrl, buf_info); - if (ret) - goto map_error; - - mhi_tre = tre_ring->wp; - - mhi_tre->ptr = MHI_TRE_DATA_PTR(buf_info->p_addr); - mhi_tre->dword[0] = MHI_TRE_DATA_DWORD0(buf_info->len); - mhi_tre->dword[1] = MHI_TRE_DATA_DWORD1(1, 1, 0, 0); - - /* increment WP */ - mhi_add_ring_element(mhi_cntrl, tre_ring); - mhi_add_ring_element(mhi_cntrl, buf_ring); + ret = mhi_gen_tre(mhi_cntrl, mhi_chan, &buf_info, mflags); + if (unlikely(ret)) { + read_unlock_bh(&mhi_cntrl->pm_lock); + return ret; + } if (mhi_chan->dir == DMA_TO_DEVICE) atomic_inc(&mhi_cntrl->pending_pkts); @@ -979,11 +1001,6 @@ int mhi_queue_skb(struct mhi_device *mhi_dev, enum dma_data_direction dir, read_unlock_bh(&mhi_cntrl->pm_lock); return 0; - -map_error: - read_unlock_bh(&mhi_cntrl->pm_lock); - - return ret; } EXPORT_SYMBOL_GPL(mhi_queue_skb); @@ -995,9 +1012,8 @@ int mhi_queue_dma(struct mhi_device *mhi_dev, enum dma_data_direction dir, mhi_dev->dl_chan; struct device *dev = &mhi_cntrl->mhi_dev->dev; struct mhi_ring *tre_ring = &mhi_chan->tre_ring; - struct mhi_ring *buf_ring = &mhi_chan->buf_ring; - struct mhi_buf_info *buf_info; - struct mhi_tre *mhi_tre; + struct mhi_buf_info buf_info = { }; + int ret; /* If MHI host pre-allocates buffers then client drivers cannot queue */ if (mhi_chan->pre_alloc) @@ -1024,25 +1040,16 @@ int mhi_queue_dma(struct mhi_device *mhi_dev, enum dma_data_direction dir, /* Toggle wake to exit out of M2 */ mhi_cntrl->wake_toggle(mhi_cntrl); - /* Generate the TRE */ - buf_info = buf_ring->wp; - WARN_ON(buf_info->used); - buf_info->p_addr = mhi_buf->dma_addr; - buf_info->pre_mapped = true; - buf_info->cb_buf = mhi_buf; - buf_info->wp = tre_ring->wp; - buf_info->dir = mhi_chan->dir; - buf_info->len = len; + buf_info.p_addr = mhi_buf->dma_addr; + buf_info.cb_buf = mhi_buf; + buf_info.pre_mapped = true; + buf_info.len = len; - mhi_tre = tre_ring->wp; - - mhi_tre->ptr = MHI_TRE_DATA_PTR(buf_info->p_addr); - mhi_tre->dword[0] = MHI_TRE_DATA_DWORD0(buf_info->len); - mhi_tre->dword[1] = MHI_TRE_DATA_DWORD1(1, 1, 0, 0); - - /* increment WP */ - mhi_add_ring_element(mhi_cntrl, tre_ring); - mhi_add_ring_element(mhi_cntrl, buf_ring); + ret = mhi_gen_tre(mhi_cntrl, mhi_chan, &buf_info, mflags); + if (unlikely(ret)) { + read_unlock_bh(&mhi_cntrl->pm_lock); + return ret; + } if (mhi_chan->dir == DMA_TO_DEVICE) atomic_inc(&mhi_cntrl->pending_pkts); @@ -1060,7 +1067,7 @@ int mhi_queue_dma(struct mhi_device *mhi_dev, enum dma_data_direction dir, EXPORT_SYMBOL_GPL(mhi_queue_dma); int mhi_gen_tre(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan, - void *buf, void *cb, size_t buf_len, enum mhi_flags flags) + struct mhi_buf_info *info, enum mhi_flags flags) { struct mhi_ring *buf_ring, *tre_ring; struct mhi_tre *mhi_tre; @@ -1072,15 +1079,22 @@ int mhi_gen_tre(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan, tre_ring = &mhi_chan->tre_ring; buf_info = buf_ring->wp; - buf_info->v_addr = buf; - buf_info->cb_buf = cb; + WARN_ON(buf_info->used); + buf_info->pre_mapped = info->pre_mapped; + if (info->pre_mapped) + buf_info->p_addr = info->p_addr; + else + buf_info->v_addr = info->v_addr; + buf_info->cb_buf = info->cb_buf; buf_info->wp = tre_ring->wp; buf_info->dir = mhi_chan->dir; - buf_info->len = buf_len; + buf_info->len = info->len; - ret = mhi_cntrl->map_single(mhi_cntrl, buf_info); - if (ret) - return ret; + if (!info->pre_mapped) { + ret = mhi_cntrl->map_single(mhi_cntrl, buf_info); + if (ret) + return ret; + } eob = !!(flags & MHI_EOB); eot = !!(flags & MHI_EOT); @@ -1089,7 +1103,7 @@ int mhi_gen_tre(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan, mhi_tre = tre_ring->wp; mhi_tre->ptr = MHI_TRE_DATA_PTR(buf_info->p_addr); - mhi_tre->dword[0] = MHI_TRE_DATA_DWORD0(buf_len); + mhi_tre->dword[0] = MHI_TRE_DATA_DWORD0(info->len); mhi_tre->dword[1] = MHI_TRE_DATA_DWORD1(bei, eot, eob, chain); /* increment WP */ @@ -1106,6 +1120,7 @@ int mhi_queue_buf(struct mhi_device *mhi_dev, enum dma_data_direction dir, struct mhi_chan *mhi_chan = (dir == DMA_TO_DEVICE) ? mhi_dev->ul_chan : mhi_dev->dl_chan; struct mhi_ring *tre_ring; + struct mhi_buf_info buf_info = { }; unsigned long flags; int ret; @@ -1121,7 +1136,11 @@ int mhi_queue_buf(struct mhi_device *mhi_dev, enum dma_data_direction dir, if (mhi_is_ring_full(mhi_cntrl, tre_ring)) return -ENOMEM; - ret = mhi_gen_tre(mhi_cntrl, mhi_chan, buf, buf, len, mflags); + buf_info.v_addr = buf; + buf_info.cb_buf = buf; + buf_info.len = len; + + ret = mhi_gen_tre(mhi_cntrl, mhi_chan, &buf_info, mflags); if (unlikely(ret)) return ret; @@ -1322,7 +1341,7 @@ int mhi_prepare_channel(struct mhi_controller *mhi_cntrl, while (nr_el--) { void *buf; - + struct mhi_buf_info info = { }; buf = kmalloc(len, GFP_KERNEL); if (!buf) { ret = -ENOMEM; @@ -1330,8 +1349,10 @@ int mhi_prepare_channel(struct mhi_controller *mhi_cntrl, } /* Prepare transfer descriptors */ - ret = mhi_gen_tre(mhi_cntrl, mhi_chan, buf, buf, - len, MHI_EOT); + info.v_addr = buf; + info.cb_buf = buf; + info.len = len; + ret = mhi_gen_tre(mhi_cntrl, mhi_chan, &info, MHI_EOT); if (ret) { kfree(buf); goto error_pre_alloc; diff --git a/drivers/bus/mhi/core/pm.c b/drivers/bus/mhi/core/pm.c index dc83d65f7784..796098078083 100644 --- a/drivers/bus/mhi/core/pm.c +++ b/drivers/bus/mhi/core/pm.c @@ -288,14 +288,18 @@ int mhi_pm_m0_transition(struct mhi_controller *mhi_cntrl) for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) { struct mhi_ring *tre_ring = &mhi_chan->tre_ring; - write_lock_irq(&mhi_chan->lock); - if (mhi_chan->db_cfg.reset_req) + if (mhi_chan->db_cfg.reset_req) { + write_lock_irq(&mhi_chan->lock); mhi_chan->db_cfg.db_mode = true; + write_unlock_irq(&mhi_chan->lock); + } + + read_lock_irq(&mhi_chan->lock); /* Only ring DB if ring is not empty */ if (tre_ring->base && tre_ring->wp != tre_ring->rp) mhi_ring_chan_db(mhi_cntrl, mhi_chan); - write_unlock_irq(&mhi_chan->lock); + read_unlock_irq(&mhi_chan->lock); } mhi_cntrl->wake_put(mhi_cntrl, false); @@ -449,19 +453,8 @@ static void mhi_pm_disable_transition(struct mhi_controller *mhi_cntrl, to_mhi_pm_state_str(transition_state)); /* We must notify MHI control driver so it can clean up first */ - if (transition_state == MHI_PM_SYS_ERR_PROCESS) { - /* - * If controller supports RDDM, we do not process - * SYS error state, instead we will jump directly - * to RDDM state - */ - if (mhi_cntrl->rddm_image) { - dev_dbg(dev, - "Controller supports RDDM, so skip SYS_ERR\n"); - return; - } + if (transition_state == MHI_PM_SYS_ERR_PROCESS) mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_SYS_ERROR); - } mutex_lock(&mhi_cntrl->pm_mutex); write_lock_irq(&mhi_cntrl->pm_lock); @@ -527,8 +520,6 @@ static void mhi_pm_disable_transition(struct mhi_controller *mhi_cntrl, mutex_unlock(&mhi_cntrl->pm_mutex); dev_dbg(dev, "Waiting for all pending threads to complete\n"); wake_up_all(&mhi_cntrl->state_event); - flush_work(&mhi_cntrl->st_worker); - flush_work(&mhi_cntrl->fw_worker); dev_dbg(dev, "Reset all active channels and remove MHI devices\n"); device_for_each_child(mhi_cntrl->cntrl_dev, NULL, mhi_destroy_device); @@ -608,13 +599,17 @@ int mhi_queue_state_transition(struct mhi_controller *mhi_cntrl, } /* SYS_ERR worker */ -void mhi_pm_sys_err_worker(struct work_struct *work) +void mhi_pm_sys_err_handler(struct mhi_controller *mhi_cntrl) { - struct mhi_controller *mhi_cntrl = container_of(work, - struct mhi_controller, - syserr_worker); + struct device *dev = &mhi_cntrl->mhi_dev->dev; - mhi_pm_disable_transition(mhi_cntrl, MHI_PM_SYS_ERR_PROCESS); + /* skip if controller supports RDDM */ + if (mhi_cntrl->rddm_image) { + dev_dbg(dev, "Controller supports RDDM, skip SYS_ERROR\n"); + return; + } + + mhi_queue_state_transition(mhi_cntrl, DEV_ST_TRANSITION_SYS_ERR); } /* Device State Transition worker */ @@ -643,7 +638,7 @@ void mhi_pm_st_worker(struct work_struct *work) mhi_cntrl->ee = mhi_get_exec_env(mhi_cntrl); write_unlock_irq(&mhi_cntrl->pm_lock); if (MHI_IN_PBL(mhi_cntrl->ee)) - wake_up_all(&mhi_cntrl->state_event); + mhi_fw_load_handler(mhi_cntrl); break; case DEV_ST_TRANSITION_SBL: write_lock_irq(&mhi_cntrl->pm_lock); @@ -662,6 +657,14 @@ void mhi_pm_st_worker(struct work_struct *work) case DEV_ST_TRANSITION_READY: mhi_ready_state_transition(mhi_cntrl); break; + case DEV_ST_TRANSITION_SYS_ERR: + mhi_pm_disable_transition + (mhi_cntrl, MHI_PM_SYS_ERR_PROCESS); + break; + case DEV_ST_TRANSITION_DISABLE: + mhi_pm_disable_transition + (mhi_cntrl, MHI_PM_SHUTDOWN_PROCESS); + break; default: break; } @@ -669,6 +672,149 @@ void mhi_pm_st_worker(struct work_struct *work) } } +int mhi_pm_suspend(struct mhi_controller *mhi_cntrl) +{ + struct mhi_chan *itr, *tmp; + struct device *dev = &mhi_cntrl->mhi_dev->dev; + enum mhi_pm_state new_state; + int ret; + + if (mhi_cntrl->pm_state == MHI_PM_DISABLE) + return -EINVAL; + + if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) + return -EIO; + + /* Return busy if there are any pending resources */ + if (atomic_read(&mhi_cntrl->dev_wake)) + return -EBUSY; + + /* Take MHI out of M2 state */ + read_lock_bh(&mhi_cntrl->pm_lock); + mhi_cntrl->wake_get(mhi_cntrl, false); + read_unlock_bh(&mhi_cntrl->pm_lock); + + ret = wait_event_timeout(mhi_cntrl->state_event, + mhi_cntrl->dev_state == MHI_STATE_M0 || + mhi_cntrl->dev_state == MHI_STATE_M1 || + MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state), + msecs_to_jiffies(mhi_cntrl->timeout_ms)); + + read_lock_bh(&mhi_cntrl->pm_lock); + mhi_cntrl->wake_put(mhi_cntrl, false); + read_unlock_bh(&mhi_cntrl->pm_lock); + + if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) { + dev_err(dev, + "Could not enter M0/M1 state"); + return -EIO; + } + + write_lock_irq(&mhi_cntrl->pm_lock); + + if (atomic_read(&mhi_cntrl->dev_wake)) { + write_unlock_irq(&mhi_cntrl->pm_lock); + return -EBUSY; + } + + dev_info(dev, "Allowing M3 transition\n"); + new_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3_ENTER); + if (new_state != MHI_PM_M3_ENTER) { + write_unlock_irq(&mhi_cntrl->pm_lock); + dev_err(dev, + "Error setting to PM state: %s from: %s\n", + to_mhi_pm_state_str(MHI_PM_M3_ENTER), + to_mhi_pm_state_str(mhi_cntrl->pm_state)); + return -EIO; + } + + /* Set MHI to M3 and wait for completion */ + mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M3); + write_unlock_irq(&mhi_cntrl->pm_lock); + dev_info(dev, "Wait for M3 completion\n"); + + ret = wait_event_timeout(mhi_cntrl->state_event, + mhi_cntrl->dev_state == MHI_STATE_M3 || + MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state), + msecs_to_jiffies(mhi_cntrl->timeout_ms)); + + if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) { + dev_err(dev, + "Did not enter M3 state, MHI state: %s, PM state: %s\n", + TO_MHI_STATE_STR(mhi_cntrl->dev_state), + to_mhi_pm_state_str(mhi_cntrl->pm_state)); + return -EIO; + } + + /* Notify clients about entering LPM */ + list_for_each_entry_safe(itr, tmp, &mhi_cntrl->lpm_chans, node) { + mutex_lock(&itr->mutex); + if (itr->mhi_dev) + mhi_notify(itr->mhi_dev, MHI_CB_LPM_ENTER); + mutex_unlock(&itr->mutex); + } + + return 0; +} +EXPORT_SYMBOL_GPL(mhi_pm_suspend); + +int mhi_pm_resume(struct mhi_controller *mhi_cntrl) +{ + struct mhi_chan *itr, *tmp; + struct device *dev = &mhi_cntrl->mhi_dev->dev; + enum mhi_pm_state cur_state; + int ret; + + dev_info(dev, "Entered with PM state: %s, MHI state: %s\n", + to_mhi_pm_state_str(mhi_cntrl->pm_state), + TO_MHI_STATE_STR(mhi_cntrl->dev_state)); + + if (mhi_cntrl->pm_state == MHI_PM_DISABLE) + return 0; + + if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) + return -EIO; + + /* Notify clients about exiting LPM */ + list_for_each_entry_safe(itr, tmp, &mhi_cntrl->lpm_chans, node) { + mutex_lock(&itr->mutex); + if (itr->mhi_dev) + mhi_notify(itr->mhi_dev, MHI_CB_LPM_EXIT); + mutex_unlock(&itr->mutex); + } + + write_lock_irq(&mhi_cntrl->pm_lock); + cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3_EXIT); + if (cur_state != MHI_PM_M3_EXIT) { + write_unlock_irq(&mhi_cntrl->pm_lock); + dev_info(dev, + "Error setting to PM state: %s from: %s\n", + to_mhi_pm_state_str(MHI_PM_M3_EXIT), + to_mhi_pm_state_str(mhi_cntrl->pm_state)); + return -EIO; + } + + /* Set MHI to M0 and wait for completion */ + mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M0); + write_unlock_irq(&mhi_cntrl->pm_lock); + + ret = wait_event_timeout(mhi_cntrl->state_event, + mhi_cntrl->dev_state == MHI_STATE_M0 || + MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state), + msecs_to_jiffies(mhi_cntrl->timeout_ms)); + + if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) { + dev_err(dev, + "Did not enter M0 state, MHI state: %s, PM state: %s\n", + TO_MHI_STATE_STR(mhi_cntrl->dev_state), + to_mhi_pm_state_str(mhi_cntrl->pm_state)); + return -EIO; + } + + return 0; +} +EXPORT_SYMBOL_GPL(mhi_pm_resume); + int __mhi_device_get_sync(struct mhi_controller *mhi_cntrl) { int ret; @@ -760,6 +906,7 @@ static void mhi_deassert_dev_wake(struct mhi_controller *mhi_cntrl, int mhi_async_power_up(struct mhi_controller *mhi_cntrl) { + enum mhi_state state; enum mhi_ee_type current_ee; enum dev_st_transition next_state; struct device *dev = &mhi_cntrl->mhi_dev->dev; @@ -829,13 +976,36 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl) goto error_bhi_offset; } + state = mhi_get_mhi_state(mhi_cntrl); + if (state == MHI_STATE_SYS_ERR) { + mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET); + ret = wait_event_timeout(mhi_cntrl->state_event, + MHI_PM_IN_FATAL_STATE(mhi_cntrl->pm_state) || + mhi_read_reg_field(mhi_cntrl, + mhi_cntrl->regs, + MHICTRL, + MHICTRL_RESET_MASK, + MHICTRL_RESET_SHIFT, + &val) || + !val, + msecs_to_jiffies(mhi_cntrl->timeout_ms)); + if (ret) { + ret = -EIO; + dev_info(dev, "Failed to reset MHI due to syserr state\n"); + goto error_bhi_offset; + } + + /* + * device cleares INTVEC as part of RESET processing, + * re-program it + */ + mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0); + } + /* Transition to next state */ next_state = MHI_IN_PBL(current_ee) ? DEV_ST_TRANSITION_PBL : DEV_ST_TRANSITION_READY; - if (next_state == DEV_ST_TRANSITION_PBL) - schedule_work(&mhi_cntrl->fw_worker); - mhi_queue_state_transition(mhi_cntrl, next_state); mutex_unlock(&mhi_cntrl->pm_mutex); @@ -876,7 +1046,12 @@ void mhi_power_down(struct mhi_controller *mhi_cntrl, bool graceful) to_mhi_pm_state_str(MHI_PM_LD_ERR_FATAL_DETECT), to_mhi_pm_state_str(mhi_cntrl->pm_state)); } - mhi_pm_disable_transition(mhi_cntrl, MHI_PM_SHUTDOWN_PROCESS); + + mhi_queue_state_transition(mhi_cntrl, DEV_ST_TRANSITION_DISABLE); + + /* Wait for shutdown to complete */ + flush_work(&mhi_cntrl->st_worker); + mhi_deinit_free_irq(mhi_cntrl); if (!mhi_cntrl->pre_init) { diff --git a/drivers/char/mem.c b/drivers/char/mem.c index 43dd0891ca1e..31cae88a730b 100644 --- a/drivers/char/mem.c +++ b/drivers/char/mem.c @@ -31,11 +31,15 @@ #include #include #include +#include +#include +#include #ifdef CONFIG_IA64 # include #endif +#define DEVMEM_MINOR 1 #define DEVPORT_MINOR 4 static inline unsigned long size_inside_page(unsigned long start, @@ -805,12 +809,64 @@ static loff_t memory_lseek(struct file *file, loff_t offset, int orig) return ret; } +static struct inode *devmem_inode; + +#ifdef CONFIG_IO_STRICT_DEVMEM +void revoke_devmem(struct resource *res) +{ + struct inode *inode = READ_ONCE(devmem_inode); + + /* + * Check that the initialization has completed. Losing the race + * is ok because it means drivers are claiming resources before + * the fs_initcall level of init and prevent /dev/mem from + * establishing mappings. + */ + if (!inode) + return; + + /* + * The expectation is that the driver has successfully marked + * the resource busy by this point, so devmem_is_allowed() + * should start returning false, however for performance this + * does not iterate the entire resource range. + */ + if (devmem_is_allowed(PHYS_PFN(res->start)) && + devmem_is_allowed(PHYS_PFN(res->end))) { + /* + * *cringe* iomem=relaxed says "go ahead, what's the + * worst that can happen?" + */ + return; + } + + unmap_mapping_range(inode->i_mapping, res->start, resource_size(res), 1); +} +#endif + static int open_port(struct inode *inode, struct file *filp) { + int rc; + if (!capable(CAP_SYS_RAWIO)) return -EPERM; - return security_locked_down(LOCKDOWN_DEV_MEM); + rc = security_locked_down(LOCKDOWN_DEV_MEM); + if (rc) + return rc; + + if (iminor(inode) != DEVMEM_MINOR) + return 0; + + /* + * Use a unified address space to have a single point to manage + * revocations when drivers want to take over a /dev/mem mapped + * range. + */ + inode->i_mapping = devmem_inode->i_mapping; + filp->f_mapping = inode->i_mapping; + + return 0; } #define zero_lseek null_lseek @@ -885,7 +941,7 @@ static const struct memdev { fmode_t fmode; } devlist[] = { #ifdef CONFIG_DEVMEM - [1] = { "mem", 0, &mem_fops, FMODE_UNSIGNED_OFFSET }, + [DEVMEM_MINOR] = { "mem", 0, &mem_fops, FMODE_UNSIGNED_OFFSET }, #endif #ifdef CONFIG_DEVKMEM [2] = { "kmem", 0, &kmem_fops, FMODE_UNSIGNED_OFFSET }, @@ -939,6 +995,45 @@ static char *mem_devnode(struct device *dev, umode_t *mode) static struct class *mem_class; +static int devmem_fs_init_fs_context(struct fs_context *fc) +{ + return init_pseudo(fc, DEVMEM_MAGIC) ? 0 : -ENOMEM; +} + +static struct file_system_type devmem_fs_type = { + .name = "devmem", + .owner = THIS_MODULE, + .init_fs_context = devmem_fs_init_fs_context, + .kill_sb = kill_anon_super, +}; + +static int devmem_init_inode(void) +{ + static struct vfsmount *devmem_vfs_mount; + static int devmem_fs_cnt; + struct inode *inode; + int rc; + + rc = simple_pin_fs(&devmem_fs_type, &devmem_vfs_mount, &devmem_fs_cnt); + if (rc < 0) { + pr_err("Cannot mount /dev/mem pseudo filesystem: %d\n", rc); + return rc; + } + + inode = alloc_anon_inode(devmem_vfs_mount->mnt_sb); + if (IS_ERR(inode)) { + rc = PTR_ERR(inode); + pr_err("Cannot allocate inode for /dev/mem: %d\n", rc); + simple_release_fs(&devmem_vfs_mount, &devmem_fs_cnt); + return rc; + } + + /* publish /dev/mem initialized */ + WRITE_ONCE(devmem_inode, inode); + + return 0; +} + static int __init chr_dev_init(void) { int minor; @@ -960,6 +1055,8 @@ static int __init chr_dev_init(void) */ if ((minor == DEVPORT_MINOR) && !arch_has_dev_port()) continue; + if ((minor == DEVMEM_MINOR) && devmem_init_inode() != 0) + continue; device_create(mem_class, NULL, MKDEV(MEM_MAJOR, minor), NULL, devlist[minor].name); diff --git a/drivers/char/tlclk.c b/drivers/char/tlclk.c index 6d81bb3bb503..896a3550fba9 100644 --- a/drivers/char/tlclk.c +++ b/drivers/char/tlclk.c @@ -777,18 +777,22 @@ static int __init tlclk_init(void) { int ret; - ret = register_chrdev(tlclk_major, "telco_clock", &tlclk_fops); - if (ret < 0) { - printk(KERN_ERR "tlclk: can't get major %d.\n", tlclk_major); - return ret; - } - tlclk_major = ret; + telclk_interrupt = (inb(TLCLK_REG7) & 0x0f); + alarm_events = kzalloc( sizeof(struct tlclk_alarms), GFP_KERNEL); if (!alarm_events) { ret = -ENOMEM; goto out1; } + ret = register_chrdev(tlclk_major, "telco_clock", &tlclk_fops); + if (ret < 0) { + printk(KERN_ERR "tlclk: can't get major %d.\n", tlclk_major); + kfree(alarm_events); + return ret; + } + tlclk_major = ret; + /* Read telecom clock IRQ number (Set by BIOS) */ if (!request_region(TLCLK_BASE, 8, "telco_clock")) { printk(KERN_ERR "tlclk: request_region 0x%X failed.\n", @@ -796,7 +800,6 @@ static int __init tlclk_init(void) ret = -EBUSY; goto out2; } - telclk_interrupt = (inb(TLCLK_REG7) & 0x0f); if (0x0F == telclk_interrupt ) { /* not MCPBL0010 ? */ printk(KERN_ERR "telclk_interrupt = 0x%x non-mcpbl0010 hw.\n", @@ -837,8 +840,8 @@ out3: release_region(TLCLK_BASE, 8); out2: kfree(alarm_events); -out1: unregister_chrdev(tlclk_major, "telco_clock"); +out1: return ret; } diff --git a/drivers/clk/zynqmp/clk-gate-zynqmp.c b/drivers/clk/zynqmp/clk-gate-zynqmp.c index 83b236f20fff..10c9b889324f 100644 --- a/drivers/clk/zynqmp/clk-gate-zynqmp.c +++ b/drivers/clk/zynqmp/clk-gate-zynqmp.c @@ -37,9 +37,8 @@ static int zynqmp_clk_gate_enable(struct clk_hw *hw) const char *clk_name = clk_hw_get_name(hw); u32 clk_id = gate->clk_id; int ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); - ret = eemi_ops->clock_enable(clk_id); + ret = zynqmp_pm_clock_enable(clk_id); if (ret) pr_warn_once("%s() clock enabled failed for %s, ret = %d\n", @@ -58,9 +57,8 @@ static void zynqmp_clk_gate_disable(struct clk_hw *hw) const char *clk_name = clk_hw_get_name(hw); u32 clk_id = gate->clk_id; int ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); - ret = eemi_ops->clock_disable(clk_id); + ret = zynqmp_pm_clock_disable(clk_id); if (ret) pr_warn_once("%s() clock disable failed for %s, ret = %d\n", @@ -79,9 +77,8 @@ static int zynqmp_clk_gate_is_enabled(struct clk_hw *hw) const char *clk_name = clk_hw_get_name(hw); u32 clk_id = gate->clk_id; int state, ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); - ret = eemi_ops->clock_getstate(clk_id, &state); + ret = zynqmp_pm_clock_getstate(clk_id, &state); if (ret) { pr_warn_once("%s() clock get state failed for %s, ret = %d\n", __func__, clk_name, ret); diff --git a/drivers/clk/zynqmp/clk-mux-zynqmp.c b/drivers/clk/zynqmp/clk-mux-zynqmp.c index 0af8f74c5fa5..06194149be83 100644 --- a/drivers/clk/zynqmp/clk-mux-zynqmp.c +++ b/drivers/clk/zynqmp/clk-mux-zynqmp.c @@ -47,9 +47,8 @@ static u8 zynqmp_clk_mux_get_parent(struct clk_hw *hw) u32 clk_id = mux->clk_id; u32 val; int ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); - ret = eemi_ops->clock_getparent(clk_id, &val); + ret = zynqmp_pm_clock_getparent(clk_id, &val); if (ret) pr_warn_once("%s() getparent failed for clock: %s, ret = %d\n", @@ -71,9 +70,8 @@ static int zynqmp_clk_mux_set_parent(struct clk_hw *hw, u8 index) const char *clk_name = clk_hw_get_name(hw); u32 clk_id = mux->clk_id; int ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); - ret = eemi_ops->clock_setparent(clk_id, index); + ret = zynqmp_pm_clock_setparent(clk_id, index); if (ret) pr_warn_once("%s() set parent failed for clock: %s, ret = %d\n", diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c index 10e89f23880b..5eed5ce10179 100644 --- a/drivers/clk/zynqmp/clkc.c +++ b/drivers/clk/zynqmp/clkc.c @@ -134,7 +134,6 @@ static struct clk_hw *(* const clk_topology[]) (const char *name, u32 clk_id, static struct zynqmp_clock *clock; static struct clk_hw_onecell_data *zynqmp_data; static unsigned int clock_max_idx; -static const struct zynqmp_eemi_ops *eemi_ops; /** * zynqmp_is_valid_clock() - Check whether clock is valid or not @@ -206,7 +205,7 @@ static int zynqmp_pm_clock_get_num_clocks(u32 *nclocks) qdata.qid = PM_QID_CLOCK_GET_NUM_CLOCKS; - ret = eemi_ops->query_data(qdata, ret_payload); + ret = zynqmp_pm_query_data(qdata, ret_payload); *nclocks = ret_payload[1]; return ret; @@ -231,7 +230,7 @@ static int zynqmp_pm_clock_get_name(u32 clock_id, qdata.qid = PM_QID_CLOCK_GET_NAME; qdata.arg1 = clock_id; - eemi_ops->query_data(qdata, ret_payload); + zynqmp_pm_query_data(qdata, ret_payload); memcpy(response, ret_payload, sizeof(*response)); return 0; @@ -265,7 +264,7 @@ static int zynqmp_pm_clock_get_topology(u32 clock_id, u32 index, qdata.arg1 = clock_id; qdata.arg2 = index; - ret = eemi_ops->query_data(qdata, ret_payload); + ret = zynqmp_pm_query_data(qdata, ret_payload); memcpy(response, &ret_payload[1], sizeof(*response)); return ret; @@ -296,7 +295,7 @@ struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id, qdata.qid = PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS; qdata.arg1 = clk_id; - ret = eemi_ops->query_data(qdata, ret_payload); + ret = zynqmp_pm_query_data(qdata, ret_payload); if (ret) return ERR_PTR(ret); @@ -339,7 +338,7 @@ static int zynqmp_pm_clock_get_parents(u32 clock_id, u32 index, qdata.arg1 = clock_id; qdata.arg2 = index; - ret = eemi_ops->query_data(qdata, ret_payload); + ret = zynqmp_pm_query_data(qdata, ret_payload); memcpy(response, &ret_payload[1], sizeof(*response)); return ret; @@ -364,7 +363,7 @@ static int zynqmp_pm_clock_get_attributes(u32 clock_id, qdata.qid = PM_QID_CLOCK_GET_ATTRIBUTES; qdata.arg1 = clock_id; - ret = eemi_ops->query_data(qdata, ret_payload); + ret = zynqmp_pm_query_data(qdata, ret_payload); memcpy(response, &ret_payload[1], sizeof(*response)); return ret; @@ -738,10 +737,6 @@ static int zynqmp_clock_probe(struct platform_device *pdev) int ret; struct device *dev = &pdev->dev; - eemi_ops = zynqmp_pm_get_eemi_ops(); - if (IS_ERR(eemi_ops)) - return PTR_ERR(eemi_ops); - ret = zynqmp_clk_setup(dev->of_node); return ret; diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index 4be2cc76aa2e..8eed715707e3 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -83,9 +83,8 @@ static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw, u32 div_type = divider->div_type; u32 div, value; int ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); - ret = eemi_ops->clock_getdivider(clk_id, &div); + ret = zynqmp_pm_clock_getdivider(clk_id, &div); if (ret) pr_warn_once("%s() get divider failed for %s, ret = %d\n", @@ -163,11 +162,10 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, u32 div_type = divider->div_type; u32 bestdiv; int ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); /* if read only, just return current value */ if (divider->flags & CLK_DIVIDER_READ_ONLY) { - ret = eemi_ops->clock_getdivider(clk_id, &bestdiv); + ret = zynqmp_pm_clock_getdivider(clk_id, &bestdiv); if (ret) pr_warn_once("%s() get divider failed for %s, ret = %d\n", @@ -219,7 +217,6 @@ static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, u32 div_type = divider->div_type; u32 value, div; int ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); value = zynqmp_divider_get_val(parent_rate, rate, divider->flags); if (div_type == TYPE_DIV1) { @@ -233,7 +230,7 @@ static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) div = __ffs(div); - ret = eemi_ops->clock_setdivider(clk_id, div); + ret = zynqmp_pm_clock_setdivider(clk_id, div); if (ret) pr_warn_once("%s() set divider failed for %s, ret = %d\n", @@ -258,7 +255,6 @@ static const struct clk_ops zynqmp_clk_divider_ops = { */ u32 zynqmp_clk_get_max_divisor(u32 clk_id, u32 type) { - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); struct zynqmp_pm_query_data qdata = {0}; u32 ret_payload[PAYLOAD_ARG_CNT]; int ret; @@ -266,7 +262,7 @@ u32 zynqmp_clk_get_max_divisor(u32 clk_id, u32 type) qdata.qid = PM_QID_CLOCK_GET_MAX_DIVISOR; qdata.arg1 = clk_id; qdata.arg2 = type; - ret = eemi_ops->query_data(qdata, ret_payload); + ret = zynqmp_pm_query_data(qdata, ret_payload); /* * To maintain backward compatibility return maximum possible value * (0xFFFF) if query for max divisor is not successful. diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c index 89b599530105..92f449ed38e5 100644 --- a/drivers/clk/zynqmp/pll.c +++ b/drivers/clk/zynqmp/pll.c @@ -50,10 +50,8 @@ static inline enum pll_mode zynqmp_pll_get_mode(struct clk_hw *hw) const char *clk_name = clk_hw_get_name(hw); u32 ret_payload[PAYLOAD_ARG_CNT]; int ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); - ret = eemi_ops->ioctl(0, IOCTL_GET_PLL_FRAC_MODE, clk_id, 0, - ret_payload); + ret = zynqmp_pm_get_pll_frac_mode(clk_id, ret_payload); if (ret) pr_warn_once("%s() PLL get frac mode failed for %s, ret = %d\n", __func__, clk_name, ret); @@ -73,14 +71,13 @@ static inline void zynqmp_pll_set_mode(struct clk_hw *hw, bool on) const char *clk_name = clk_hw_get_name(hw); int ret; u32 mode; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); if (on) mode = PLL_MODE_FRAC; else mode = PLL_MODE_INT; - ret = eemi_ops->ioctl(0, IOCTL_SET_PLL_FRAC_MODE, clk_id, mode, NULL); + ret = zynqmp_pm_set_pll_frac_mode(clk_id, mode); if (ret) pr_warn_once("%s() PLL set frac mode failed for %s, ret = %d\n", __func__, clk_name, ret); @@ -139,17 +136,15 @@ static unsigned long zynqmp_pll_recalc_rate(struct clk_hw *hw, unsigned long rate, frac; u32 ret_payload[PAYLOAD_ARG_CNT]; int ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); - ret = eemi_ops->clock_getdivider(clk_id, &fbdiv); + ret = zynqmp_pm_clock_getdivider(clk_id, &fbdiv); if (ret) pr_warn_once("%s() get divider failed for %s, ret = %d\n", __func__, clk_name, ret); rate = parent_rate * fbdiv; if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) { - eemi_ops->ioctl(0, IOCTL_GET_PLL_FRAC_DATA, clk_id, 0, - ret_payload); + zynqmp_pm_get_pll_frac_data(clk_id, ret_payload); data = ret_payload[1]; frac = (parent_rate * data) / FRAC_DIV; rate = rate + frac; @@ -177,7 +172,6 @@ static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate, u32 fbdiv; long rate_div, frac, m, f; int ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) { rate_div = (rate * FRAC_DIV) / parent_rate; @@ -187,21 +181,21 @@ static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate, rate = parent_rate * m; frac = (parent_rate * f) / FRAC_DIV; - ret = eemi_ops->clock_setdivider(clk_id, m); + ret = zynqmp_pm_clock_setdivider(clk_id, m); if (ret == -EUSERS) WARN(1, "More than allowed devices are using the %s, which is forbidden\n", clk_name); else if (ret) pr_warn_once("%s() set divider failed for %s, ret = %d\n", __func__, clk_name, ret); - eemi_ops->ioctl(0, IOCTL_SET_PLL_FRAC_DATA, clk_id, f, NULL); + zynqmp_pm_set_pll_frac_data(clk_id, f); return rate + frac; } fbdiv = DIV_ROUND_CLOSEST(rate, parent_rate); fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX); - ret = eemi_ops->clock_setdivider(clk_id, fbdiv); + ret = zynqmp_pm_clock_setdivider(clk_id, fbdiv); if (ret) pr_warn_once("%s() set divider failed for %s, ret = %d\n", __func__, clk_name, ret); @@ -222,9 +216,8 @@ static int zynqmp_pll_is_enabled(struct clk_hw *hw) u32 clk_id = clk->clk_id; unsigned int state; int ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); - ret = eemi_ops->clock_getstate(clk_id, &state); + ret = zynqmp_pm_clock_getstate(clk_id, &state); if (ret) { pr_warn_once("%s() clock get state failed for %s, ret = %d\n", __func__, clk_name, ret); @@ -246,12 +239,11 @@ static int zynqmp_pll_enable(struct clk_hw *hw) const char *clk_name = clk_hw_get_name(hw); u32 clk_id = clk->clk_id; int ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); if (zynqmp_pll_is_enabled(hw)) return 0; - ret = eemi_ops->clock_enable(clk_id); + ret = zynqmp_pm_clock_enable(clk_id); if (ret) pr_warn_once("%s() clock enable failed for %s, ret = %d\n", __func__, clk_name, ret); @@ -269,12 +261,11 @@ static void zynqmp_pll_disable(struct clk_hw *hw) const char *clk_name = clk_hw_get_name(hw); u32 clk_id = clk->clk_id; int ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); if (!zynqmp_pll_is_enabled(hw)) return; - ret = eemi_ops->clock_disable(clk_id); + ret = zynqmp_pm_clock_disable(clk_id); if (ret) pr_warn_once("%s() clock disable failed for %s, ret = %d\n", __func__, clk_name, ret); diff --git a/drivers/crypto/xilinx/zynqmp-aes-gcm.c b/drivers/crypto/xilinx/zynqmp-aes-gcm.c index 09f7f468eef8..cd11558893cd 100644 --- a/drivers/crypto/xilinx/zynqmp-aes-gcm.c +++ b/drivers/crypto/xilinx/zynqmp-aes-gcm.c @@ -46,7 +46,6 @@ struct zynqmp_aead_drv_ctx { } alg; struct device *dev; struct crypto_engine *engine; - const struct zynqmp_eemi_ops *eemi_ops; }; struct zynqmp_aead_hw_req { @@ -80,21 +79,15 @@ static int zynqmp_aes_aead_cipher(struct aead_request *req) struct zynqmp_aead_tfm_ctx *tfm_ctx = crypto_aead_ctx(aead); struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(req); struct device *dev = tfm_ctx->dev; - struct aead_alg *alg = crypto_aead_alg(aead); - struct zynqmp_aead_drv_ctx *drv_ctx; struct zynqmp_aead_hw_req *hwreq; dma_addr_t dma_addr_data, dma_addr_hw_req; unsigned int data_size; unsigned int status; + int ret; size_t dma_size; char *kbuf; int err; - drv_ctx = container_of(alg, struct zynqmp_aead_drv_ctx, alg.aead); - - if (!drv_ctx->eemi_ops->aes) - return -ENOTSUPP; - if (tfm_ctx->keysrc == ZYNQMP_AES_KUP_KEY) dma_size = req->cryptlen + ZYNQMP_AES_KEY_SIZE + GCM_AES_IV_SIZE; @@ -136,9 +129,12 @@ static int zynqmp_aes_aead_cipher(struct aead_request *req) hwreq->key = 0; } - drv_ctx->eemi_ops->aes(dma_addr_hw_req, &status); + ret = zynqmp_pm_aes_engine(dma_addr_hw_req, &status); - if (status) { + if (ret) { + dev_err(dev, "ERROR: AES PM API failed\n"); + err = ret; + } else if (status) { switch (status) { case ZYNQMP_AES_GCM_TAG_MISMATCH_ERR: dev_err(dev, "ERROR: Gcm Tag mismatch\n"); @@ -388,12 +384,6 @@ static int zynqmp_aes_aead_probe(struct platform_device *pdev) else return -ENODEV; - aes_drv_ctx.eemi_ops = zynqmp_pm_get_eemi_ops(); - if (IS_ERR(aes_drv_ctx.eemi_ops)) { - dev_err(dev, "Failed to get ZynqMP EEMI interface\n"); - return PTR_ERR(aes_drv_ctx.eemi_ops); - } - err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(ZYNQMP_DMA_BIT_MASK)); if (err < 0) { dev_err(dev, "No usable DMA configuration\n"); diff --git a/drivers/dca/dca-sysfs.c b/drivers/dca/dca-sysfs.c index eb25627b059d..21ebd0af268b 100644 --- a/drivers/dca/dca-sysfs.c +++ b/drivers/dca/dca-sysfs.c @@ -24,9 +24,7 @@ int dca_sysfs_add_req(struct dca_provider *dca, struct device *dev, int slot) cd = device_create(dca_class, dca->cd, MKDEV(0, slot + 1), NULL, "requester%d", req_count++); - if (IS_ERR(cd)) - return PTR_ERR(cd); - return 0; + return PTR_ERR_OR_ZERO(cd); } void dca_sysfs_remove_req(struct dca_provider *dca, int slot) diff --git a/drivers/extcon/extcon-adc-jack.c b/drivers/extcon/extcon-adc-jack.c index ad02dc6747a4..0317b614b680 100644 --- a/drivers/extcon/extcon-adc-jack.c +++ b/drivers/extcon/extcon-adc-jack.c @@ -124,7 +124,7 @@ static int adc_jack_probe(struct platform_device *pdev) for (i = 0; data->adc_conditions[i].id != EXTCON_NONE; i++); data->num_conditions = i; - data->chan = iio_channel_get(&pdev->dev, pdata->consumer_channel); + data->chan = devm_iio_channel_get(&pdev->dev, pdata->consumer_channel); if (IS_ERR(data->chan)) return PTR_ERR(data->chan); @@ -164,7 +164,6 @@ static int adc_jack_remove(struct platform_device *pdev) free_irq(data->irq, data); cancel_work_sync(&data->handler.work); - iio_channel_release(data->chan); return 0; } diff --git a/drivers/extcon/extcon-arizona.c b/drivers/extcon/extcon-arizona.c index 7401733db08b..aae82db542a5 100644 --- a/drivers/extcon/extcon-arizona.c +++ b/drivers/extcon/extcon-arizona.c @@ -1460,7 +1460,7 @@ static int arizona_extcon_probe(struct platform_device *pdev) if (!info->input) { dev_err(arizona->dev, "Can't allocate input dev\n"); ret = -ENOMEM; - goto err_register; + return ret; } info->input->name = "Headset"; @@ -1492,7 +1492,7 @@ static int arizona_extcon_probe(struct platform_device *pdev) if (ret != 0) { dev_err(arizona->dev, "Failed to request GPIO%d: %d\n", pdata->micd_pol_gpio, ret); - goto err_register; + return ret; } info->micd_pol_gpio = gpio_to_desc(pdata->micd_pol_gpio); @@ -1515,7 +1515,7 @@ static int arizona_extcon_probe(struct platform_device *pdev) dev_err(arizona->dev, "Failed to get microphone polarity GPIO: %d\n", ret); - goto err_register; + return ret; } } @@ -1672,7 +1672,7 @@ static int arizona_extcon_probe(struct platform_device *pdev) if (ret != 0) { dev_err(&pdev->dev, "Failed to get JACKDET rise IRQ: %d\n", ret); - goto err_gpio; + goto err_pm; } ret = arizona_set_irq_wake(arizona, jack_irq_rise, 1); @@ -1721,14 +1721,14 @@ static int arizona_extcon_probe(struct platform_device *pdev) dev_warn(arizona->dev, "Failed to set MICVDD to bypass: %d\n", ret); - pm_runtime_put(&pdev->dev); - ret = input_register_device(info->input); if (ret) { dev_err(&pdev->dev, "Can't register input device: %d\n", ret); goto err_hpdet; } + pm_runtime_put(&pdev->dev); + return 0; err_hpdet: @@ -1743,10 +1743,11 @@ err_rise_wake: arizona_set_irq_wake(arizona, jack_irq_rise, 0); err_rise: arizona_free_irq(arizona, jack_irq_rise, info); +err_pm: + pm_runtime_put(&pdev->dev); + pm_runtime_disable(&pdev->dev); err_gpio: gpiod_put(info->micd_pol_gpio); -err_register: - pm_runtime_disable(&pdev->dev); return ret; } diff --git a/drivers/extcon/extcon-max14577.c b/drivers/extcon/extcon-max14577.c index 32f663436e6e..cc47d626095c 100644 --- a/drivers/extcon/extcon-max14577.c +++ b/drivers/extcon/extcon-max14577.c @@ -782,9 +782,19 @@ static const struct platform_device_id max14577_muic_id[] = { }; MODULE_DEVICE_TABLE(platform, max14577_muic_id); +static const struct of_device_id of_max14577_muic_dt_match[] = { + { .compatible = "maxim,max14577-muic", + .data = (void *)MAXIM_DEVICE_TYPE_MAX14577, }, + { .compatible = "maxim,max77836-muic", + .data = (void *)MAXIM_DEVICE_TYPE_MAX77836, }, + { }, +}; +MODULE_DEVICE_TABLE(of, of_max14577_muic_dt_match); + static struct platform_driver max14577_muic_driver = { .driver = { .name = "max14577-muic", + .of_match_table = of_max14577_muic_dt_match, }, .probe = max14577_muic_probe, .remove = max14577_muic_remove, diff --git a/drivers/extcon/extcon.c b/drivers/extcon/extcon.c index 2dfbfec572f9..0a6438cbb3f3 100644 --- a/drivers/extcon/extcon.c +++ b/drivers/extcon/extcon.c @@ -900,7 +900,7 @@ int extcon_register_notifier(struct extcon_dev *edev, unsigned int id, struct notifier_block *nb) { unsigned long flags; - int ret, idx = -EINVAL; + int ret, idx; if (!edev || !nb) return -EINVAL; diff --git a/drivers/firmware/stratix10-rsu.c b/drivers/firmware/stratix10-rsu.c index f8533338b018..4379475c99ed 100644 --- a/drivers/firmware/stratix10-rsu.c +++ b/drivers/firmware/stratix10-rsu.c @@ -72,7 +72,7 @@ static void rsu_status_callback(struct stratix10_svc_client *client, struct stratix10_rsu_priv *priv = client->priv; struct arm_smccc_res *res = (struct arm_smccc_res *)data->kaddr1; - if (data->status == BIT(SVC_STATUS_RSU_OK)) { + if (data->status == BIT(SVC_STATUS_OK)) { priv->status.version = FIELD_GET(RSU_VERSION_MASK, res->a2); priv->status.state = FIELD_GET(RSU_STATE_MASK, res->a2); @@ -108,9 +108,9 @@ static void rsu_command_callback(struct stratix10_svc_client *client, { struct stratix10_rsu_priv *priv = client->priv; - if (data->status == BIT(SVC_STATUS_RSU_NO_SUPPORT)) + if (data->status == BIT(SVC_STATUS_NO_SUPPORT)) dev_warn(client->dev, "Secure FW doesn't support notify\n"); - else if (data->status == BIT(SVC_STATUS_RSU_ERROR)) + else if (data->status == BIT(SVC_STATUS_ERROR)) dev_err(client->dev, "Failure, returned status is %lu\n", BIT(data->status)); @@ -133,9 +133,9 @@ static void rsu_retry_callback(struct stratix10_svc_client *client, struct stratix10_rsu_priv *priv = client->priv; unsigned int *counter = (unsigned int *)data->kaddr1; - if (data->status == BIT(SVC_STATUS_RSU_OK)) + if (data->status == BIT(SVC_STATUS_OK)) priv->retry_counter = *counter; - else if (data->status == BIT(SVC_STATUS_RSU_NO_SUPPORT)) + else if (data->status == BIT(SVC_STATUS_NO_SUPPORT)) dev_warn(client->dev, "Secure FW doesn't support retry\n"); else dev_err(client->dev, "Failed to get retry counter %lu\n", diff --git a/drivers/firmware/stratix10-svc.c b/drivers/firmware/stratix10-svc.c index d5f0769f3761..e0db8dbfc9d1 100644 --- a/drivers/firmware/stratix10-svc.c +++ b/drivers/firmware/stratix10-svc.c @@ -214,7 +214,7 @@ static void svc_thread_cmd_data_claim(struct stratix10_svc_controller *ctrl, complete(&ctrl->complete_status); break; } - cb_data->status = BIT(SVC_STATUS_RECONFIG_BUFFER_DONE); + cb_data->status = BIT(SVC_STATUS_BUFFER_DONE); cb_data->kaddr1 = svc_pa_to_va(res.a1); cb_data->kaddr2 = (res.a2) ? svc_pa_to_va(res.a2) : NULL; @@ -227,7 +227,7 @@ static void svc_thread_cmd_data_claim(struct stratix10_svc_controller *ctrl, __func__); } } while (res.a0 == INTEL_SIP_SMC_STATUS_OK || - res.a0 == INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY || + res.a0 == INTEL_SIP_SMC_STATUS_BUSY || wait_for_completion_timeout(&ctrl->complete_status, timeout)); } @@ -250,7 +250,7 @@ static void svc_thread_cmd_config_status(struct stratix10_svc_controller *ctrl, cb_data->kaddr1 = NULL; cb_data->kaddr2 = NULL; cb_data->kaddr3 = NULL; - cb_data->status = BIT(SVC_STATUS_RECONFIG_ERROR); + cb_data->status = BIT(SVC_STATUS_ERROR); pr_debug("%s: polling config status\n", __func__); @@ -259,7 +259,7 @@ static void svc_thread_cmd_config_status(struct stratix10_svc_controller *ctrl, ctrl->invoke_fn(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, 0, 0, 0, 0, 0, 0, 0, &res); if ((res.a0 == INTEL_SIP_SMC_STATUS_OK) || - (res.a0 == INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR)) + (res.a0 == INTEL_SIP_SMC_STATUS_ERROR)) break; /* @@ -271,7 +271,7 @@ static void svc_thread_cmd_config_status(struct stratix10_svc_controller *ctrl, } if (res.a0 == INTEL_SIP_SMC_STATUS_OK && count_in_sec) - cb_data->status = BIT(SVC_STATUS_RECONFIG_COMPLETED); + cb_data->status = BIT(SVC_STATUS_COMPLETED); p_data->chan->scl->receive_cb(p_data->chan->scl, cb_data); } @@ -294,24 +294,18 @@ static void svc_thread_recv_status_ok(struct stratix10_svc_data *p_data, switch (p_data->command) { case COMMAND_RECONFIG: - cb_data->status = BIT(SVC_STATUS_RECONFIG_REQUEST_OK); - break; - case COMMAND_RECONFIG_DATA_SUBMIT: - cb_data->status = BIT(SVC_STATUS_RECONFIG_BUFFER_SUBMITTED); - break; - case COMMAND_NOOP: - cb_data->status = BIT(SVC_STATUS_RECONFIG_BUFFER_SUBMITTED); - cb_data->kaddr1 = svc_pa_to_va(res.a1); - break; - case COMMAND_RECONFIG_STATUS: - cb_data->status = BIT(SVC_STATUS_RECONFIG_COMPLETED); - break; case COMMAND_RSU_UPDATE: case COMMAND_RSU_NOTIFY: - cb_data->status = BIT(SVC_STATUS_RSU_OK); + cb_data->status = BIT(SVC_STATUS_OK); + break; + case COMMAND_RECONFIG_DATA_SUBMIT: + cb_data->status = BIT(SVC_STATUS_BUFFER_SUBMITTED); + break; + case COMMAND_RECONFIG_STATUS: + cb_data->status = BIT(SVC_STATUS_COMPLETED); break; case COMMAND_RSU_RETRY: - cb_data->status = BIT(SVC_STATUS_RSU_OK); + cb_data->status = BIT(SVC_STATUS_OK); cb_data->kaddr1 = &res.a1; break; default: @@ -430,9 +424,9 @@ static int svc_normal_to_secure_thread(void *data) if (pdata->command == COMMAND_RSU_STATUS) { if (res.a0 == INTEL_SIP_SMC_RSU_ERROR) - cbdata->status = BIT(SVC_STATUS_RSU_ERROR); + cbdata->status = BIT(SVC_STATUS_ERROR); else - cbdata->status = BIT(SVC_STATUS_RSU_OK); + cbdata->status = BIT(SVC_STATUS_OK); cbdata->kaddr1 = &res; cbdata->kaddr2 = NULL; @@ -445,7 +439,7 @@ static int svc_normal_to_secure_thread(void *data) case INTEL_SIP_SMC_STATUS_OK: svc_thread_recv_status_ok(pdata, cbdata, res); break; - case INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY: + case INTEL_SIP_SMC_STATUS_BUSY: switch (pdata->command) { case COMMAND_RECONFIG_DATA_SUBMIT: svc_thread_cmd_data_claim(ctrl, @@ -460,33 +454,13 @@ static int svc_normal_to_secure_thread(void *data) break; } break; - case INTEL_SIP_SMC_FPGA_CONFIG_STATUS_REJECTED: + case INTEL_SIP_SMC_STATUS_REJECTED: pr_debug("%s: STATUS_REJECTED\n", __func__); break; - case INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR: + case INTEL_SIP_SMC_STATUS_ERROR: case INTEL_SIP_SMC_RSU_ERROR: pr_err("%s: STATUS_ERROR\n", __func__); - switch (pdata->command) { - /* for FPGA mgr */ - case COMMAND_RECONFIG_DATA_CLAIM: - case COMMAND_RECONFIG: - case COMMAND_RECONFIG_DATA_SUBMIT: - case COMMAND_RECONFIG_STATUS: - cbdata->status = - BIT(SVC_STATUS_RECONFIG_ERROR); - break; - - /* for RSU */ - case COMMAND_RSU_STATUS: - case COMMAND_RSU_UPDATE: - case COMMAND_RSU_NOTIFY: - case COMMAND_RSU_RETRY: - cbdata->status = - BIT(SVC_STATUS_RSU_ERROR); - break; - } - - cbdata->status = BIT(SVC_STATUS_RECONFIG_ERROR); + cbdata->status = BIT(SVC_STATUS_ERROR); cbdata->kaddr1 = NULL; cbdata->kaddr2 = NULL; cbdata->kaddr3 = NULL; @@ -502,7 +476,7 @@ static int svc_normal_to_secure_thread(void *data) if ((pdata->command == COMMAND_RSU_RETRY) || (pdata->command == COMMAND_RSU_NOTIFY)) { cbdata->status = - BIT(SVC_STATUS_RSU_NO_SUPPORT); + BIT(SVC_STATUS_NO_SUPPORT); cbdata->kaddr1 = NULL; cbdata->kaddr2 = NULL; cbdata->kaddr3 = NULL; diff --git a/drivers/firmware/xilinx/zynqmp-debug.c b/drivers/firmware/xilinx/zynqmp-debug.c index 43bc6cfdab45..99606b34975e 100644 --- a/drivers/firmware/xilinx/zynqmp-debug.c +++ b/drivers/firmware/xilinx/zynqmp-debug.c @@ -85,14 +85,13 @@ static int get_pm_api_id(char *pm_api_req, u32 *pm_id) static int process_api_request(u32 pm_id, u64 *pm_api_arg, u32 *pm_api_ret) { - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); u32 pm_api_version; int ret; struct zynqmp_pm_query_data qdata = {0}; switch (pm_id) { case PM_GET_API_VERSION: - ret = eemi_ops->get_api_version(&pm_api_version); + ret = zynqmp_pm_get_api_version(&pm_api_version); sprintf(debugfs_buf, "PM-API Version = %d.%d\n", pm_api_version >> 16, pm_api_version & 0xffff); break; @@ -102,7 +101,7 @@ static int process_api_request(u32 pm_id, u64 *pm_api_arg, u32 *pm_api_ret) qdata.arg2 = pm_api_arg[2]; qdata.arg3 = pm_api_arg[3]; - ret = eemi_ops->query_data(qdata, pm_api_ret); + ret = zynqmp_pm_query_data(qdata, pm_api_ret); if (ret) break; diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index 41b65164a367..8d1ff2454e2e 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -2,7 +2,7 @@ /* * Xilinx Zynq MPSoC Firmware layer * - * Copyright (C) 2014-2018 Xilinx, Inc. + * Copyright (C) 2014-2020 Xilinx, Inc. * * Michal Simek * Davorin Mista @@ -24,8 +24,6 @@ #include #include "zynqmp-debug.h" -static const struct zynqmp_eemi_ops *eemi_ops_tbl; - static bool feature_check_enabled; static u32 zynqmp_pm_features[PM_API_MAX]; @@ -219,7 +217,7 @@ static u32 pm_tz_version; * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_get_api_version(u32 *version) +int zynqmp_pm_get_api_version(u32 *version) { u32 ret_payload[PAYLOAD_ARG_CNT]; int ret; @@ -237,6 +235,7 @@ static int zynqmp_pm_get_api_version(u32 *version) return ret; } +EXPORT_SYMBOL_GPL(zynqmp_pm_get_api_version); /** * zynqmp_pm_get_chipid - Get silicon ID registers @@ -246,7 +245,7 @@ static int zynqmp_pm_get_api_version(u32 *version) * Return: Returns the status of the operation and the idcode and version * registers in @idcode and @version. */ -static int zynqmp_pm_get_chipid(u32 *idcode, u32 *version) +int zynqmp_pm_get_chipid(u32 *idcode, u32 *version) { u32 ret_payload[PAYLOAD_ARG_CNT]; int ret; @@ -260,6 +259,7 @@ static int zynqmp_pm_get_chipid(u32 *idcode, u32 *version) return ret; } +EXPORT_SYMBOL_GPL(zynqmp_pm_get_chipid); /** * zynqmp_pm_get_trustzone_version() - Get secure trustzone firmware version @@ -324,7 +324,7 @@ static int get_set_conduit_method(struct device_node *np) * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out) +int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out) { int ret; @@ -338,6 +338,7 @@ static int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out) */ return qdata.qid == PM_QID_CLOCK_GET_NAME ? 0 : ret; } +EXPORT_SYMBOL_GPL(zynqmp_pm_query_data); /** * zynqmp_pm_clock_enable() - Enable the clock for given id @@ -348,10 +349,11 @@ static int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out) * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_clock_enable(u32 clock_id) +int zynqmp_pm_clock_enable(u32 clock_id) { return zynqmp_pm_invoke_fn(PM_CLOCK_ENABLE, clock_id, 0, 0, 0, NULL); } +EXPORT_SYMBOL_GPL(zynqmp_pm_clock_enable); /** * zynqmp_pm_clock_disable() - Disable the clock for given id @@ -362,10 +364,11 @@ static int zynqmp_pm_clock_enable(u32 clock_id) * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_clock_disable(u32 clock_id) +int zynqmp_pm_clock_disable(u32 clock_id) { return zynqmp_pm_invoke_fn(PM_CLOCK_DISABLE, clock_id, 0, 0, 0, NULL); } +EXPORT_SYMBOL_GPL(zynqmp_pm_clock_disable); /** * zynqmp_pm_clock_getstate() - Get the clock state for given id @@ -377,7 +380,7 @@ static int zynqmp_pm_clock_disable(u32 clock_id) * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state) +int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state) { u32 ret_payload[PAYLOAD_ARG_CNT]; int ret; @@ -388,6 +391,7 @@ static int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state) return ret; } +EXPORT_SYMBOL_GPL(zynqmp_pm_clock_getstate); /** * zynqmp_pm_clock_setdivider() - Set the clock divider for given id @@ -399,11 +403,12 @@ static int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state) * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider) +int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider) { return zynqmp_pm_invoke_fn(PM_CLOCK_SETDIVIDER, clock_id, divider, 0, 0, NULL); } +EXPORT_SYMBOL_GPL(zynqmp_pm_clock_setdivider); /** * zynqmp_pm_clock_getdivider() - Get the clock divider for given id @@ -415,7 +420,7 @@ static int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider) * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider) +int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider) { u32 ret_payload[PAYLOAD_ARG_CNT]; int ret; @@ -426,6 +431,7 @@ static int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider) return ret; } +EXPORT_SYMBOL_GPL(zynqmp_pm_clock_getdivider); /** * zynqmp_pm_clock_setrate() - Set the clock rate for given id @@ -436,13 +442,14 @@ static int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider) * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate) +int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate) { return zynqmp_pm_invoke_fn(PM_CLOCK_SETRATE, clock_id, lower_32_bits(rate), upper_32_bits(rate), 0, NULL); } +EXPORT_SYMBOL_GPL(zynqmp_pm_clock_setrate); /** * zynqmp_pm_clock_getrate() - Get the clock rate for given id @@ -454,7 +461,7 @@ static int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate) * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate) +int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate) { u32 ret_payload[PAYLOAD_ARG_CNT]; int ret; @@ -465,6 +472,7 @@ static int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate) return ret; } +EXPORT_SYMBOL_GPL(zynqmp_pm_clock_getrate); /** * zynqmp_pm_clock_setparent() - Set the clock parent for given id @@ -475,11 +483,12 @@ static int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate) * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id) +int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id) { return zynqmp_pm_invoke_fn(PM_CLOCK_SETPARENT, clock_id, parent_id, 0, 0, NULL); } +EXPORT_SYMBOL_GPL(zynqmp_pm_clock_setparent); /** * zynqmp_pm_clock_getparent() - Get the clock parent for given id @@ -491,7 +500,7 @@ static int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id) * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id) +int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id) { u32 ret_payload[PAYLOAD_ARG_CNT]; int ret; @@ -502,48 +511,191 @@ static int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id) return ret; } +EXPORT_SYMBOL_GPL(zynqmp_pm_clock_getparent); /** - * zynqmp_is_valid_ioctl() - Check whether IOCTL ID is valid or not - * @ioctl_id: IOCTL ID + * zynqmp_pm_set_pll_frac_mode() - PM API for set PLL mode * - * Return: 1 if IOCTL is valid else 0 - */ -static inline int zynqmp_is_valid_ioctl(u32 ioctl_id) -{ - switch (ioctl_id) { - case IOCTL_SD_DLL_RESET: - case IOCTL_SET_SD_TAPDELAY: - case IOCTL_SET_PLL_FRAC_MODE: - case IOCTL_GET_PLL_FRAC_MODE: - case IOCTL_SET_PLL_FRAC_DATA: - case IOCTL_GET_PLL_FRAC_DATA: - return 1; - default: - return 0; - } -} - -/** - * zynqmp_pm_ioctl() - PM IOCTL API for device control and configs - * @node_id: Node ID of the device - * @ioctl_id: ID of the requested IOCTL - * @arg1: Argument 1 to requested IOCTL call - * @arg2: Argument 2 to requested IOCTL call - * @out: Returned output value + * @clk_id: PLL clock ID + * @mode: PLL mode (PLL_MODE_FRAC/PLL_MODE_INT) * - * This function calls IOCTL to firmware for device control and configuration. + * This function sets PLL mode * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_ioctl(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, - u32 *out) +int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode) { - if (!zynqmp_is_valid_ioctl(ioctl_id)) - return -EINVAL; + return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_SET_PLL_FRAC_MODE, + clk_id, mode, NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_set_pll_frac_mode); - return zynqmp_pm_invoke_fn(PM_IOCTL, node_id, ioctl_id, - arg1, arg2, out); +/** + * zynqmp_pm_get_pll_frac_mode() - PM API for get PLL mode + * + * @clk_id: PLL clock ID + * @mode: PLL mode + * + * This function return current PLL mode + * + * Return: Returns status, either success or error+reason + */ +int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode) +{ + return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_GET_PLL_FRAC_MODE, + clk_id, 0, mode); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_get_pll_frac_mode); + +/** + * zynqmp_pm_set_pll_frac_data() - PM API for setting pll fraction data + * + * @clk_id: PLL clock ID + * @data: fraction data + * + * This function sets fraction data. + * It is valid for fraction mode only. + * + * Return: Returns status, either success or error+reason + */ +int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data) +{ + return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_SET_PLL_FRAC_DATA, + clk_id, data, NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_set_pll_frac_data); + +/** + * zynqmp_pm_get_pll_frac_data() - PM API for getting pll fraction data + * + * @clk_id: PLL clock ID + * @data: fraction data + * + * This function returns fraction data value. + * + * Return: Returns status, either success or error+reason + */ +int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data) +{ + return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_GET_PLL_FRAC_DATA, + clk_id, 0, data); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_get_pll_frac_data); + +/** + * zynqmp_pm_set_sd_tapdelay() - Set tap delay for the SD device + * + * @node_id Node ID of the device + * @type Type of tap delay to set (input/output) + * @value Value to set fot the tap delay + * + * This function sets input/output tap delay for the SD device. + * + * @return Returns status, either success or error+reason + */ +int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value) +{ + return zynqmp_pm_invoke_fn(PM_IOCTL, node_id, IOCTL_SET_SD_TAPDELAY, + type, value, NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_set_sd_tapdelay); + +/** + * zynqmp_pm_sd_dll_reset() - Reset DLL logic + * + * @node_id Node ID of the device + * @type Reset type + * + * This function resets DLL logic for the SD device. + * + * @return Returns status, either success or error+reason + */ +int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type) +{ + return zynqmp_pm_invoke_fn(PM_IOCTL, node_id, IOCTL_SET_SD_TAPDELAY, + type, 0, NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_sd_dll_reset); + +/** + * zynqmp_pm_write_ggs() - PM API for writing global general storage (ggs) + * @index GGS register index + * @value Register value to be written + * + * This function writes value to GGS register. + * + * @return Returns status, either success or error+reason + */ +int zynqmp_pm_write_ggs(u32 index, u32 value) +{ + return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_WRITE_GGS, + index, value, NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_write_ggs); + +/** + * zynqmp_pm_write_ggs() - PM API for reading global general storage (ggs) + * @index GGS register index + * @value Register value to be written + * + * This function returns GGS register value. + * + * @return Returns status, either success or error+reason + */ +int zynqmp_pm_read_ggs(u32 index, u32 *value) +{ + return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_READ_GGS, + index, 0, value); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_read_ggs); + +/** + * zynqmp_pm_write_pggs() - PM API for writing persistent global general + * storage (pggs) + * @index PGGS register index + * @value Register value to be written + * + * This function writes value to PGGS register. + * + * @return Returns status, either success or error+reason + */ +int zynqmp_pm_write_pggs(u32 index, u32 value) +{ + return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_WRITE_PGGS, index, value, + NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_write_pggs); + +/** + * zynqmp_pm_write_pggs() - PM API for reading persistent global general + * storage (pggs) + * @index PGGS register index + * @value Register value to be written + * + * This function returns PGGS register value. + * + * @return Returns status, either success or error+reason + */ +int zynqmp_pm_read_pggs(u32 index, u32 *value) +{ + return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_READ_PGGS, index, 0, + value); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_read_pggs); + +/** + * zynqmp_pm_set_boot_health_status() - PM API for setting healthy boot status + * @value Status value to be written + * + * This function sets healthy bit value to indicate boot health status + * to firmware. + * + * @return Returns status, either success or error+reason + */ +int zynqmp_pm_set_boot_health_status(u32 value) +{ + return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_SET_BOOT_HEALTH_STATUS, + value, 0, NULL); } /** @@ -554,12 +706,13 @@ static int zynqmp_pm_ioctl(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset, - const enum zynqmp_pm_reset_action assert_flag) +int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset, + const enum zynqmp_pm_reset_action assert_flag) { return zynqmp_pm_invoke_fn(PM_RESET_ASSERT, reset, assert_flag, 0, 0, NULL); } +EXPORT_SYMBOL_GPL(zynqmp_pm_reset_assert); /** * zynqmp_pm_reset_get_status - Get status of the reset @@ -568,8 +721,7 @@ static int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset, * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, - u32 *status) +int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status) { u32 ret_payload[PAYLOAD_ARG_CNT]; int ret; @@ -583,6 +735,7 @@ static int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, return ret; } +EXPORT_SYMBOL_GPL(zynqmp_pm_reset_get_status); /** * zynqmp_pm_fpga_load - Perform the fpga load @@ -597,12 +750,12 @@ static int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_fpga_load(const u64 address, const u32 size, - const u32 flags) +int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags) { return zynqmp_pm_invoke_fn(PM_FPGA_LOAD, lower_32_bits(address), upper_32_bits(address), size, flags, NULL); } +EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_load); /** * zynqmp_pm_fpga_get_status - Read value from PCAP status register @@ -613,7 +766,7 @@ static int zynqmp_pm_fpga_load(const u64 address, const u32 size, * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_fpga_get_status(u32 *value) +int zynqmp_pm_fpga_get_status(u32 *value) { u32 ret_payload[PAYLOAD_ARG_CNT]; int ret; @@ -626,6 +779,7 @@ static int zynqmp_pm_fpga_get_status(u32 *value) return ret; } +EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_get_status); /** * zynqmp_pm_init_finalize() - PM call to inform firmware that the caller @@ -636,10 +790,11 @@ static int zynqmp_pm_fpga_get_status(u32 *value) * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_init_finalize(void) +int zynqmp_pm_init_finalize(void) { return zynqmp_pm_invoke_fn(PM_PM_INIT_FINALIZE, 0, 0, 0, 0, NULL); } +EXPORT_SYMBOL_GPL(zynqmp_pm_init_finalize); /** * zynqmp_pm_set_suspend_mode() - Set system suspend mode @@ -649,10 +804,11 @@ static int zynqmp_pm_init_finalize(void) * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_set_suspend_mode(u32 mode) +int zynqmp_pm_set_suspend_mode(u32 mode) { return zynqmp_pm_invoke_fn(PM_SET_SUSPEND_MODE, mode, 0, 0, 0, NULL); } +EXPORT_SYMBOL_GPL(zynqmp_pm_set_suspend_mode); /** * zynqmp_pm_request_node() - Request a node with specific capabilities @@ -666,13 +822,13 @@ static int zynqmp_pm_set_suspend_mode(u32 mode) * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_request_node(const u32 node, const u32 capabilities, - const u32 qos, - const enum zynqmp_pm_request_ack ack) +int zynqmp_pm_request_node(const u32 node, const u32 capabilities, + const u32 qos, const enum zynqmp_pm_request_ack ack) { return zynqmp_pm_invoke_fn(PM_REQUEST_NODE, node, capabilities, qos, ack, NULL); } +EXPORT_SYMBOL_GPL(zynqmp_pm_request_node); /** * zynqmp_pm_release_node() - Release a node @@ -684,10 +840,11 @@ static int zynqmp_pm_request_node(const u32 node, const u32 capabilities, * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_release_node(const u32 node) +int zynqmp_pm_release_node(const u32 node) { return zynqmp_pm_invoke_fn(PM_RELEASE_NODE, node, 0, 0, 0, NULL); } +EXPORT_SYMBOL_GPL(zynqmp_pm_release_node); /** * zynqmp_pm_set_requirement() - PM call to set requirement for PM slaves @@ -701,13 +858,14 @@ static int zynqmp_pm_release_node(const u32 node) * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, - const u32 qos, - const enum zynqmp_pm_request_ack ack) +int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, + const u32 qos, + const enum zynqmp_pm_request_ack ack) { return zynqmp_pm_invoke_fn(PM_SET_REQUIREMENT, node, capabilities, qos, ack, NULL); } +EXPORT_SYMBOL_GPL(zynqmp_pm_set_requirement); /** * zynqmp_pm_aes - Access AES hardware to encrypt/decrypt the data using @@ -717,7 +875,7 @@ static int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, * * Return: Returns status, either success or error code. */ -static int zynqmp_pm_aes_engine(const u64 address, u32 *out) +int zynqmp_pm_aes_engine(const u64 address, u32 *out) { u32 ret_payload[PAYLOAD_ARG_CNT]; int ret; @@ -732,47 +890,304 @@ static int zynqmp_pm_aes_engine(const u64 address, u32 *out) return ret; } - -static const struct zynqmp_eemi_ops eemi_ops = { - .get_api_version = zynqmp_pm_get_api_version, - .get_chipid = zynqmp_pm_get_chipid, - .query_data = zynqmp_pm_query_data, - .clock_enable = zynqmp_pm_clock_enable, - .clock_disable = zynqmp_pm_clock_disable, - .clock_getstate = zynqmp_pm_clock_getstate, - .clock_setdivider = zynqmp_pm_clock_setdivider, - .clock_getdivider = zynqmp_pm_clock_getdivider, - .clock_setrate = zynqmp_pm_clock_setrate, - .clock_getrate = zynqmp_pm_clock_getrate, - .clock_setparent = zynqmp_pm_clock_setparent, - .clock_getparent = zynqmp_pm_clock_getparent, - .ioctl = zynqmp_pm_ioctl, - .reset_assert = zynqmp_pm_reset_assert, - .reset_get_status = zynqmp_pm_reset_get_status, - .init_finalize = zynqmp_pm_init_finalize, - .set_suspend_mode = zynqmp_pm_set_suspend_mode, - .request_node = zynqmp_pm_request_node, - .release_node = zynqmp_pm_release_node, - .set_requirement = zynqmp_pm_set_requirement, - .fpga_load = zynqmp_pm_fpga_load, - .fpga_get_status = zynqmp_pm_fpga_get_status, - .aes = zynqmp_pm_aes_engine, -}; +EXPORT_SYMBOL_GPL(zynqmp_pm_aes_engine); /** - * zynqmp_pm_get_eemi_ops - Get eemi ops functions + * zynqmp_pm_system_shutdown - PM call to request a system shutdown or restart + * @type: Shutdown or restart? 0 for shutdown, 1 for restart + * @subtype: Specifies which system should be restarted or shut down * - * Return: Pointer of eemi_ops structure + * Return: Returns status, either success or error+reason */ -const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void) +int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype) { - if (eemi_ops_tbl) - return eemi_ops_tbl; - else - return ERR_PTR(-EPROBE_DEFER); - + return zynqmp_pm_invoke_fn(PM_SYSTEM_SHUTDOWN, type, subtype, + 0, 0, NULL); } -EXPORT_SYMBOL_GPL(zynqmp_pm_get_eemi_ops); + +/** + * struct zynqmp_pm_shutdown_scope - Struct for shutdown scope + * @subtype: Shutdown subtype + * @name: Matching string for scope argument + * + * This struct encapsulates mapping between shutdown scope ID and string. + */ +struct zynqmp_pm_shutdown_scope { + const enum zynqmp_pm_shutdown_subtype subtype; + const char *name; +}; + +static struct zynqmp_pm_shutdown_scope shutdown_scopes[] = { + [ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM] = { + .subtype = ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM, + .name = "subsystem", + }, + [ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY] = { + .subtype = ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY, + .name = "ps_only", + }, + [ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM] = { + .subtype = ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM, + .name = "system", + }, +}; + +static struct zynqmp_pm_shutdown_scope *selected_scope = + &shutdown_scopes[ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM]; + +/** + * zynqmp_pm_is_shutdown_scope_valid - Check if shutdown scope string is valid + * @scope_string: Shutdown scope string + * + * Return: Return pointer to matching shutdown scope struct from + * array of available options in system if string is valid, + * otherwise returns NULL. + */ +static struct zynqmp_pm_shutdown_scope* + zynqmp_pm_is_shutdown_scope_valid(const char *scope_string) +{ + int count; + + for (count = 0; count < ARRAY_SIZE(shutdown_scopes); count++) + if (sysfs_streq(scope_string, shutdown_scopes[count].name)) + return &shutdown_scopes[count]; + + return NULL; +} + +static ssize_t shutdown_scope_show(struct device *device, + struct device_attribute *attr, + char *buf) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(shutdown_scopes); i++) { + if (&shutdown_scopes[i] == selected_scope) { + strcat(buf, "["); + strcat(buf, shutdown_scopes[i].name); + strcat(buf, "]"); + } else { + strcat(buf, shutdown_scopes[i].name); + } + strcat(buf, " "); + } + strcat(buf, "\n"); + + return strlen(buf); +} + +static ssize_t shutdown_scope_store(struct device *device, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + struct zynqmp_pm_shutdown_scope *scope; + + scope = zynqmp_pm_is_shutdown_scope_valid(buf); + if (!scope) + return -EINVAL; + + ret = zynqmp_pm_system_shutdown(ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY, + scope->subtype); + if (ret) { + pr_err("unable to set shutdown scope %s\n", buf); + return ret; + } + + selected_scope = scope; + + return count; +} + +static DEVICE_ATTR_RW(shutdown_scope); + +static ssize_t health_status_store(struct device *device, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + unsigned int value; + + ret = kstrtouint(buf, 10, &value); + if (ret) + return ret; + + ret = zynqmp_pm_set_boot_health_status(value); + if (ret) { + dev_err(device, "unable to set healthy bit value to %u\n", + value); + return ret; + } + + return count; +} + +static DEVICE_ATTR_WO(health_status); + +static ssize_t ggs_show(struct device *device, + struct device_attribute *attr, + char *buf, + u32 reg) +{ + int ret; + u32 ret_payload[PAYLOAD_ARG_CNT]; + + ret = zynqmp_pm_read_ggs(reg, ret_payload); + if (ret) + return ret; + + return sprintf(buf, "0x%x\n", ret_payload[1]); +} + +static ssize_t ggs_store(struct device *device, + struct device_attribute *attr, + const char *buf, size_t count, + u32 reg) +{ + long value; + int ret; + + if (reg >= GSS_NUM_REGS) + return -EINVAL; + + ret = kstrtol(buf, 16, &value); + if (ret) { + count = -EFAULT; + goto err; + } + + ret = zynqmp_pm_write_ggs(reg, value); + if (ret) + count = -EFAULT; +err: + return count; +} + +/* GGS register show functions */ +#define GGS0_SHOW(N) \ + ssize_t ggs##N##_show(struct device *device, \ + struct device_attribute *attr, \ + char *buf) \ + { \ + return ggs_show(device, attr, buf, N); \ + } + +static GGS0_SHOW(0); +static GGS0_SHOW(1); +static GGS0_SHOW(2); +static GGS0_SHOW(3); + +/* GGS register store function */ +#define GGS0_STORE(N) \ + ssize_t ggs##N##_store(struct device *device, \ + struct device_attribute *attr, \ + const char *buf, \ + size_t count) \ + { \ + return ggs_store(device, attr, buf, count, N); \ + } + +static GGS0_STORE(0); +static GGS0_STORE(1); +static GGS0_STORE(2); +static GGS0_STORE(3); + +static ssize_t pggs_show(struct device *device, + struct device_attribute *attr, + char *buf, + u32 reg) +{ + int ret; + u32 ret_payload[PAYLOAD_ARG_CNT]; + + ret = zynqmp_pm_read_pggs(reg, ret_payload); + if (ret) + return ret; + + return sprintf(buf, "0x%x\n", ret_payload[1]); +} + +static ssize_t pggs_store(struct device *device, + struct device_attribute *attr, + const char *buf, size_t count, + u32 reg) +{ + long value; + int ret; + + if (reg >= GSS_NUM_REGS) + return -EINVAL; + + ret = kstrtol(buf, 16, &value); + if (ret) { + count = -EFAULT; + goto err; + } + + ret = zynqmp_pm_write_pggs(reg, value); + if (ret) + count = -EFAULT; + +err: + return count; +} + +#define PGGS0_SHOW(N) \ + ssize_t pggs##N##_show(struct device *device, \ + struct device_attribute *attr, \ + char *buf) \ + { \ + return pggs_show(device, attr, buf, N); \ + } + +#define PGGS0_STORE(N) \ + ssize_t pggs##N##_store(struct device *device, \ + struct device_attribute *attr, \ + const char *buf, \ + size_t count) \ + { \ + return pggs_store(device, attr, buf, count, N); \ + } + +/* PGGS register show functions */ +static PGGS0_SHOW(0); +static PGGS0_SHOW(1); +static PGGS0_SHOW(2); +static PGGS0_SHOW(3); + +/* PGGS register store functions */ +static PGGS0_STORE(0); +static PGGS0_STORE(1); +static PGGS0_STORE(2); +static PGGS0_STORE(3); + +/* GGS register attributes */ +static DEVICE_ATTR_RW(ggs0); +static DEVICE_ATTR_RW(ggs1); +static DEVICE_ATTR_RW(ggs2); +static DEVICE_ATTR_RW(ggs3); + +/* PGGS register attributes */ +static DEVICE_ATTR_RW(pggs0); +static DEVICE_ATTR_RW(pggs1); +static DEVICE_ATTR_RW(pggs2); +static DEVICE_ATTR_RW(pggs3); + +static struct attribute *zynqmp_firmware_attrs[] = { + &dev_attr_ggs0.attr, + &dev_attr_ggs1.attr, + &dev_attr_ggs2.attr, + &dev_attr_ggs3.attr, + &dev_attr_pggs0.attr, + &dev_attr_pggs1.attr, + &dev_attr_pggs2.attr, + &dev_attr_pggs3.attr, + &dev_attr_shutdown_scope.attr, + &dev_attr_health_status.attr, + NULL, +}; + +ATTRIBUTE_GROUPS(zynqmp_firmware); static int zynqmp_firmware_probe(struct platform_device *pdev) { @@ -820,11 +1235,6 @@ static int zynqmp_firmware_probe(struct platform_device *pdev) pr_info("%s Trustzone version v%d.%d\n", __func__, pm_tz_version >> 16, pm_tz_version & 0xFFFF); - /* Assign eemi_ops_table */ - eemi_ops_tbl = &eemi_ops; - - zynqmp_pm_api_debugfs_init(); - ret = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, firmware_devs, ARRAY_SIZE(firmware_devs), NULL, 0, NULL); if (ret) { @@ -832,6 +1242,8 @@ static int zynqmp_firmware_probe(struct platform_device *pdev) return ret; } + zynqmp_pm_api_debugfs_init(); + return of_platform_populate(dev->of_node, NULL, NULL, dev); } @@ -854,6 +1266,7 @@ static struct platform_driver zynqmp_firmware_driver = { .driver = { .name = "zynqmp_firmware", .of_match_table = zynqmp_firmware_of_match, + .dev_groups = zynqmp_firmware_groups, }, .probe = zynqmp_firmware_probe, .remove = zynqmp_firmware_remove, diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 72380e1d31c7..b2408a710662 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -156,7 +156,7 @@ config FPGA_DFL config FPGA_DFL_FME tristate "FPGA DFL FME Driver" - depends on FPGA_DFL && HWMON + depends on FPGA_DFL && HWMON && PERF_EVENTS help The FPGA Management Engine (FME) is a feature device implemented under Device Feature List (DFL) framework. Select this option to diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 4865b74b00a4..d8e21dfc6778 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_FPGA_DFL_FME_REGION) += dfl-fme-region.o obj-$(CONFIG_FPGA_DFL_AFU) += dfl-afu.o dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o dfl-fme-error.o +dfl-fme-objs += dfl-fme-perf.o dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-afu-dma-region.o dfl-afu-objs += dfl-afu-error.o diff --git a/drivers/fpga/dfl-afu-dma-region.c b/drivers/fpga/dfl-afu-dma-region.c index d902acb36d14..02d8cbad1ae2 100644 --- a/drivers/fpga/dfl-afu-dma-region.c +++ b/drivers/fpga/dfl-afu-dma-region.c @@ -61,10 +61,10 @@ static int afu_dma_pin_pages(struct dfl_feature_platform_data *pdata, region->pages); if (pinned < 0) { ret = pinned; - goto put_pages; + goto free_pages; } else if (pinned != npages) { ret = -EFAULT; - goto free_pages; + goto put_pages; } dev_dbg(dev, "%d pages pinned\n", pinned); diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c index 65437b6a6842..b0c31789a909 100644 --- a/drivers/fpga/dfl-afu-main.c +++ b/drivers/fpga/dfl-afu-main.c @@ -561,14 +561,16 @@ static int afu_open(struct inode *inode, struct file *filp) if (WARN_ON(!pdata)) return -ENODEV; - ret = dfl_feature_dev_use_begin(pdata); - if (ret) - return ret; + mutex_lock(&pdata->lock); + ret = dfl_feature_dev_use_begin(pdata, filp->f_flags & O_EXCL); + if (!ret) { + dev_dbg(&fdev->dev, "Device File Opened %d Times\n", + dfl_feature_dev_use_count(pdata)); + filp->private_data = fdev; + } + mutex_unlock(&pdata->lock); - dev_dbg(&fdev->dev, "Device File Open\n"); - filp->private_data = fdev; - - return 0; + return ret; } static int afu_release(struct inode *inode, struct file *filp) @@ -581,12 +583,14 @@ static int afu_release(struct inode *inode, struct file *filp) pdata = dev_get_platdata(&pdev->dev); mutex_lock(&pdata->lock); - __port_reset(pdev); - afu_dma_region_destroy(pdata); - mutex_unlock(&pdata->lock); - dfl_feature_dev_use_end(pdata); + if (!dfl_feature_dev_use_count(pdata)) { + __port_reset(pdev); + afu_dma_region_destroy(pdata); + } + mutex_unlock(&pdata->lock); + return 0; } @@ -746,6 +750,12 @@ static long afu_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) return -EINVAL; } +static const struct vm_operations_struct afu_vma_ops = { +#ifdef CONFIG_HAVE_IOREMAP_PROT + .access = generic_access_phys, +#endif +}; + static int afu_mmap(struct file *filp, struct vm_area_struct *vma) { struct platform_device *pdev = filp->private_data; @@ -775,6 +785,9 @@ static int afu_mmap(struct file *filp, struct vm_area_struct *vma) !(region.flags & DFL_PORT_REGION_WRITE)) return -EPERM; + /* Support debug access to the mapping */ + vma->vm_ops = &afu_vma_ops; + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); return remap_pfn_range(vma, vma->vm_start, diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl-fme-main.c index 1d4690c99268..fc210d4e1863 100644 --- a/drivers/fpga/dfl-fme-main.c +++ b/drivers/fpga/dfl-fme-main.c @@ -579,6 +579,10 @@ static struct dfl_feature_driver fme_feature_drvs[] = { .id_table = fme_power_mgmt_id_table, .ops = &fme_power_mgmt_ops, }, + { + .id_table = fme_perf_id_table, + .ops = &fme_perf_ops, + }, { .ops = NULL, }, @@ -600,14 +604,16 @@ static int fme_open(struct inode *inode, struct file *filp) if (WARN_ON(!pdata)) return -ENODEV; - ret = dfl_feature_dev_use_begin(pdata); - if (ret) - return ret; + mutex_lock(&pdata->lock); + ret = dfl_feature_dev_use_begin(pdata, filp->f_flags & O_EXCL); + if (!ret) { + dev_dbg(&fdev->dev, "Device File Opened %d Times\n", + dfl_feature_dev_use_count(pdata)); + filp->private_data = pdata; + } + mutex_unlock(&pdata->lock); - dev_dbg(&fdev->dev, "Device File Open\n"); - filp->private_data = pdata; - - return 0; + return ret; } static int fme_release(struct inode *inode, struct file *filp) @@ -616,7 +622,10 @@ static int fme_release(struct inode *inode, struct file *filp) struct platform_device *pdev = pdata->dev; dev_dbg(&pdev->dev, "Device File Release\n"); + + mutex_lock(&pdata->lock); dfl_feature_dev_use_end(pdata); + mutex_unlock(&pdata->lock); return 0; } diff --git a/drivers/fpga/dfl-fme-perf.c b/drivers/fpga/dfl-fme-perf.c new file mode 100644 index 000000000000..6ce1ed222ea4 --- /dev/null +++ b/drivers/fpga/dfl-fme-perf.c @@ -0,0 +1,1020 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for FPGA Management Engine (FME) Global Performance Reporting + * + * Copyright 2019 Intel Corporation, Inc. + * + * Authors: + * Kang Luwei + * Xiao Guangrong + * Wu Hao + * Xu Yilun + * Joseph Grecco + * Enno Luebbers + * Tim Whisonant + * Ananda Ravuri + * Mitchel, Henry + */ + +#include +#include "dfl.h" +#include "dfl-fme.h" + +/* + * Performance Counter Registers for Cache. + * + * Cache Events are listed below as CACHE_EVNT_*. + */ +#define CACHE_CTRL 0x8 +#define CACHE_RESET_CNTR BIT_ULL(0) +#define CACHE_FREEZE_CNTR BIT_ULL(8) +#define CACHE_CTRL_EVNT GENMASK_ULL(19, 16) +#define CACHE_EVNT_RD_HIT 0x0 +#define CACHE_EVNT_WR_HIT 0x1 +#define CACHE_EVNT_RD_MISS 0x2 +#define CACHE_EVNT_WR_MISS 0x3 +#define CACHE_EVNT_RSVD 0x4 +#define CACHE_EVNT_HOLD_REQ 0x5 +#define CACHE_EVNT_DATA_WR_PORT_CONTEN 0x6 +#define CACHE_EVNT_TAG_WR_PORT_CONTEN 0x7 +#define CACHE_EVNT_TX_REQ_STALL 0x8 +#define CACHE_EVNT_RX_REQ_STALL 0x9 +#define CACHE_EVNT_EVICTIONS 0xa +#define CACHE_EVNT_MAX CACHE_EVNT_EVICTIONS +#define CACHE_CHANNEL_SEL BIT_ULL(20) +#define CACHE_CHANNEL_RD 0 +#define CACHE_CHANNEL_WR 1 +#define CACHE_CNTR0 0x10 +#define CACHE_CNTR1 0x18 +#define CACHE_CNTR_EVNT_CNTR GENMASK_ULL(47, 0) +#define CACHE_CNTR_EVNT GENMASK_ULL(63, 60) + +/* + * Performance Counter Registers for Fabric. + * + * Fabric Events are listed below as FAB_EVNT_* + */ +#define FAB_CTRL 0x20 +#define FAB_RESET_CNTR BIT_ULL(0) +#define FAB_FREEZE_CNTR BIT_ULL(8) +#define FAB_CTRL_EVNT GENMASK_ULL(19, 16) +#define FAB_EVNT_PCIE0_RD 0x0 +#define FAB_EVNT_PCIE0_WR 0x1 +#define FAB_EVNT_PCIE1_RD 0x2 +#define FAB_EVNT_PCIE1_WR 0x3 +#define FAB_EVNT_UPI_RD 0x4 +#define FAB_EVNT_UPI_WR 0x5 +#define FAB_EVNT_MMIO_RD 0x6 +#define FAB_EVNT_MMIO_WR 0x7 +#define FAB_EVNT_MAX FAB_EVNT_MMIO_WR +#define FAB_PORT_ID GENMASK_ULL(21, 20) +#define FAB_PORT_FILTER BIT_ULL(23) +#define FAB_PORT_FILTER_DISABLE 0 +#define FAB_PORT_FILTER_ENABLE 1 +#define FAB_CNTR 0x28 +#define FAB_CNTR_EVNT_CNTR GENMASK_ULL(59, 0) +#define FAB_CNTR_EVNT GENMASK_ULL(63, 60) + +/* + * Performance Counter Registers for Clock. + * + * Clock Counter can't be reset or frozen by SW. + */ +#define CLK_CNTR 0x30 +#define BASIC_EVNT_CLK 0x0 +#define BASIC_EVNT_MAX BASIC_EVNT_CLK + +/* + * Performance Counter Registers for IOMMU / VT-D. + * + * VT-D Events are listed below as VTD_EVNT_* and VTD_SIP_EVNT_* + */ +#define VTD_CTRL 0x38 +#define VTD_RESET_CNTR BIT_ULL(0) +#define VTD_FREEZE_CNTR BIT_ULL(8) +#define VTD_CTRL_EVNT GENMASK_ULL(19, 16) +#define VTD_EVNT_AFU_MEM_RD_TRANS 0x0 +#define VTD_EVNT_AFU_MEM_WR_TRANS 0x1 +#define VTD_EVNT_AFU_DEVTLB_RD_HIT 0x2 +#define VTD_EVNT_AFU_DEVTLB_WR_HIT 0x3 +#define VTD_EVNT_DEVTLB_4K_FILL 0x4 +#define VTD_EVNT_DEVTLB_2M_FILL 0x5 +#define VTD_EVNT_DEVTLB_1G_FILL 0x6 +#define VTD_EVNT_MAX VTD_EVNT_DEVTLB_1G_FILL +#define VTD_CNTR 0x40 +#define VTD_CNTR_EVNT_CNTR GENMASK_ULL(47, 0) +#define VTD_CNTR_EVNT GENMASK_ULL(63, 60) + +#define VTD_SIP_CTRL 0x48 +#define VTD_SIP_RESET_CNTR BIT_ULL(0) +#define VTD_SIP_FREEZE_CNTR BIT_ULL(8) +#define VTD_SIP_CTRL_EVNT GENMASK_ULL(19, 16) +#define VTD_SIP_EVNT_IOTLB_4K_HIT 0x0 +#define VTD_SIP_EVNT_IOTLB_2M_HIT 0x1 +#define VTD_SIP_EVNT_IOTLB_1G_HIT 0x2 +#define VTD_SIP_EVNT_SLPWC_L3_HIT 0x3 +#define VTD_SIP_EVNT_SLPWC_L4_HIT 0x4 +#define VTD_SIP_EVNT_RCC_HIT 0x5 +#define VTD_SIP_EVNT_IOTLB_4K_MISS 0x6 +#define VTD_SIP_EVNT_IOTLB_2M_MISS 0x7 +#define VTD_SIP_EVNT_IOTLB_1G_MISS 0x8 +#define VTD_SIP_EVNT_SLPWC_L3_MISS 0x9 +#define VTD_SIP_EVNT_SLPWC_L4_MISS 0xa +#define VTD_SIP_EVNT_RCC_MISS 0xb +#define VTD_SIP_EVNT_MAX VTD_SIP_EVNT_SLPWC_L4_MISS +#define VTD_SIP_CNTR 0X50 +#define VTD_SIP_CNTR_EVNT_CNTR GENMASK_ULL(47, 0) +#define VTD_SIP_CNTR_EVNT GENMASK_ULL(63, 60) + +#define PERF_TIMEOUT 30 + +#define PERF_MAX_PORT_NUM 1U + +/** + * struct fme_perf_priv - priv data structure for fme perf driver + * + * @dev: parent device. + * @ioaddr: mapped base address of mmio region. + * @pmu: pmu data structure for fme perf counters. + * @id: id of this fme performance report private feature. + * @fab_users: current user number on fabric counters. + * @fab_port_id: used to indicate current working mode of fabric counters. + * @fab_lock: lock to protect fabric counters working mode. + * @cpu: active CPU to which the PMU is bound for accesses. + * @cpuhp_node: node for CPU hotplug notifier link. + * @cpuhp_state: state for CPU hotplug notification; + */ +struct fme_perf_priv { + struct device *dev; + void __iomem *ioaddr; + struct pmu pmu; + u64 id; + + u32 fab_users; + u32 fab_port_id; + spinlock_t fab_lock; + + unsigned int cpu; + struct hlist_node node; + enum cpuhp_state cpuhp_state; +}; + +/** + * struct fme_perf_event_ops - callbacks for fme perf events + * + * @event_init: callback invoked during event init. + * @event_destroy: callback invoked during event destroy. + * @read_counter: callback to read hardware counters. + */ +struct fme_perf_event_ops { + int (*event_init)(struct fme_perf_priv *priv, u32 event, u32 portid); + void (*event_destroy)(struct fme_perf_priv *priv, u32 event, + u32 portid); + u64 (*read_counter)(struct fme_perf_priv *priv, u32 event, u32 portid); +}; + +#define to_fme_perf_priv(_pmu) container_of(_pmu, struct fme_perf_priv, pmu) + +static ssize_t cpumask_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pmu *pmu = dev_get_drvdata(dev); + struct fme_perf_priv *priv; + + priv = to_fme_perf_priv(pmu); + + return cpumap_print_to_pagebuf(true, buf, cpumask_of(priv->cpu)); +} +static DEVICE_ATTR_RO(cpumask); + +static struct attribute *fme_perf_cpumask_attrs[] = { + &dev_attr_cpumask.attr, + NULL, +}; + +static struct attribute_group fme_perf_cpumask_group = { + .attrs = fme_perf_cpumask_attrs, +}; + +#define FME_EVENT_MASK GENMASK_ULL(11, 0) +#define FME_EVENT_SHIFT 0 +#define FME_EVTYPE_MASK GENMASK_ULL(15, 12) +#define FME_EVTYPE_SHIFT 12 +#define FME_EVTYPE_BASIC 0 +#define FME_EVTYPE_CACHE 1 +#define FME_EVTYPE_FABRIC 2 +#define FME_EVTYPE_VTD 3 +#define FME_EVTYPE_VTD_SIP 4 +#define FME_EVTYPE_MAX FME_EVTYPE_VTD_SIP +#define FME_PORTID_MASK GENMASK_ULL(23, 16) +#define FME_PORTID_SHIFT 16 +#define FME_PORTID_ROOT (0xffU) + +#define get_event(_config) FIELD_GET(FME_EVENT_MASK, _config) +#define get_evtype(_config) FIELD_GET(FME_EVTYPE_MASK, _config) +#define get_portid(_config) FIELD_GET(FME_PORTID_MASK, _config) + +PMU_FORMAT_ATTR(event, "config:0-11"); +PMU_FORMAT_ATTR(evtype, "config:12-15"); +PMU_FORMAT_ATTR(portid, "config:16-23"); + +static struct attribute *fme_perf_format_attrs[] = { + &format_attr_event.attr, + &format_attr_evtype.attr, + &format_attr_portid.attr, + NULL, +}; + +static struct attribute_group fme_perf_format_group = { + .name = "format", + .attrs = fme_perf_format_attrs, +}; + +/* + * There are no default events, but we need to create + * "events" group (with empty attrs) before updating + * it with detected events (using pmu->attr_update). + */ +static struct attribute *fme_perf_events_attrs_empty[] = { + NULL, +}; + +static struct attribute_group fme_perf_events_group = { + .name = "events", + .attrs = fme_perf_events_attrs_empty, +}; + +static const struct attribute_group *fme_perf_groups[] = { + &fme_perf_format_group, + &fme_perf_cpumask_group, + &fme_perf_events_group, + NULL, +}; + +static bool is_portid_root(u32 portid) +{ + return portid == FME_PORTID_ROOT; +} + +static bool is_portid_port(u32 portid) +{ + return portid < PERF_MAX_PORT_NUM; +} + +static bool is_portid_root_or_port(u32 portid) +{ + return is_portid_root(portid) || is_portid_port(portid); +} + +static u64 fme_read_perf_cntr_reg(void __iomem *addr) +{ + u32 low; + u64 v; + + /* + * For 64bit counter registers, the counter may increases and carries + * out of bit [31] between 2 32bit reads. So add extra reads to help + * to prevent this issue. This only happens in platforms which don't + * support 64bit read - readq is split into 2 readl. + */ + do { + v = readq(addr); + low = readl(addr); + } while (((u32)v) > low); + + return v; +} + +static int basic_event_init(struct fme_perf_priv *priv, u32 event, u32 portid) +{ + if (event <= BASIC_EVNT_MAX && is_portid_root(portid)) + return 0; + + return -EINVAL; +} + +static u64 basic_read_event_counter(struct fme_perf_priv *priv, + u32 event, u32 portid) +{ + void __iomem *base = priv->ioaddr; + + return fme_read_perf_cntr_reg(base + CLK_CNTR); +} + +static int cache_event_init(struct fme_perf_priv *priv, u32 event, u32 portid) +{ + if (priv->id == FME_FEATURE_ID_GLOBAL_IPERF && + event <= CACHE_EVNT_MAX && is_portid_root(portid)) + return 0; + + return -EINVAL; +} + +static u64 cache_read_event_counter(struct fme_perf_priv *priv, + u32 event, u32 portid) +{ + void __iomem *base = priv->ioaddr; + u64 v, count; + u8 channel; + + if (event == CACHE_EVNT_WR_HIT || event == CACHE_EVNT_WR_MISS || + event == CACHE_EVNT_DATA_WR_PORT_CONTEN || + event == CACHE_EVNT_TAG_WR_PORT_CONTEN) + channel = CACHE_CHANNEL_WR; + else + channel = CACHE_CHANNEL_RD; + + /* set channel access type and cache event code. */ + v = readq(base + CACHE_CTRL); + v &= ~(CACHE_CHANNEL_SEL | CACHE_CTRL_EVNT); + v |= FIELD_PREP(CACHE_CHANNEL_SEL, channel); + v |= FIELD_PREP(CACHE_CTRL_EVNT, event); + writeq(v, base + CACHE_CTRL); + + if (readq_poll_timeout_atomic(base + CACHE_CNTR0, v, + FIELD_GET(CACHE_CNTR_EVNT, v) == event, + 1, PERF_TIMEOUT)) { + dev_err(priv->dev, "timeout, unmatched cache event code in counter register.\n"); + return 0; + } + + v = fme_read_perf_cntr_reg(base + CACHE_CNTR0); + count = FIELD_GET(CACHE_CNTR_EVNT_CNTR, v); + v = fme_read_perf_cntr_reg(base + CACHE_CNTR1); + count += FIELD_GET(CACHE_CNTR_EVNT_CNTR, v); + + return count; +} + +static bool is_fabric_event_supported(struct fme_perf_priv *priv, u32 event, + u32 portid) +{ + if (event > FAB_EVNT_MAX || !is_portid_root_or_port(portid)) + return false; + + if (priv->id == FME_FEATURE_ID_GLOBAL_DPERF && + (event == FAB_EVNT_PCIE1_RD || event == FAB_EVNT_UPI_RD || + event == FAB_EVNT_PCIE1_WR || event == FAB_EVNT_UPI_WR)) + return false; + + return true; +} + +static int fabric_event_init(struct fme_perf_priv *priv, u32 event, u32 portid) +{ + void __iomem *base = priv->ioaddr; + int ret = 0; + u64 v; + + if (!is_fabric_event_supported(priv, event, portid)) + return -EINVAL; + + /* + * as fabric counter set only can be in either overall or port mode. + * In overall mode, it counts overall data for FPGA, and in port mode, + * it is configured to monitor on one individual port. + * + * so every time, a new event is initialized, driver checks + * current working mode and if someone is using this counter set. + */ + spin_lock(&priv->fab_lock); + if (priv->fab_users && priv->fab_port_id != portid) { + dev_dbg(priv->dev, "conflict fabric event monitoring mode.\n"); + ret = -EOPNOTSUPP; + goto exit; + } + + priv->fab_users++; + + /* + * skip if current working mode matches, otherwise change the working + * mode per input port_id, to monitor overall data or another port. + */ + if (priv->fab_port_id == portid) + goto exit; + + priv->fab_port_id = portid; + + v = readq(base + FAB_CTRL); + v &= ~(FAB_PORT_FILTER | FAB_PORT_ID); + + if (is_portid_root(portid)) { + v |= FIELD_PREP(FAB_PORT_FILTER, FAB_PORT_FILTER_DISABLE); + } else { + v |= FIELD_PREP(FAB_PORT_FILTER, FAB_PORT_FILTER_ENABLE); + v |= FIELD_PREP(FAB_PORT_ID, portid); + } + writeq(v, base + FAB_CTRL); + +exit: + spin_unlock(&priv->fab_lock); + return ret; +} + +static void fabric_event_destroy(struct fme_perf_priv *priv, u32 event, + u32 portid) +{ + spin_lock(&priv->fab_lock); + priv->fab_users--; + spin_unlock(&priv->fab_lock); +} + +static u64 fabric_read_event_counter(struct fme_perf_priv *priv, u32 event, + u32 portid) +{ + void __iomem *base = priv->ioaddr; + u64 v; + + v = readq(base + FAB_CTRL); + v &= ~FAB_CTRL_EVNT; + v |= FIELD_PREP(FAB_CTRL_EVNT, event); + writeq(v, base + FAB_CTRL); + + if (readq_poll_timeout_atomic(base + FAB_CNTR, v, + FIELD_GET(FAB_CNTR_EVNT, v) == event, + 1, PERF_TIMEOUT)) { + dev_err(priv->dev, "timeout, unmatched fab event code in counter register.\n"); + return 0; + } + + v = fme_read_perf_cntr_reg(base + FAB_CNTR); + return FIELD_GET(FAB_CNTR_EVNT_CNTR, v); +} + +static int vtd_event_init(struct fme_perf_priv *priv, u32 event, u32 portid) +{ + if (priv->id == FME_FEATURE_ID_GLOBAL_IPERF && + event <= VTD_EVNT_MAX && is_portid_port(portid)) + return 0; + + return -EINVAL; +} + +static u64 vtd_read_event_counter(struct fme_perf_priv *priv, u32 event, + u32 portid) +{ + void __iomem *base = priv->ioaddr; + u64 v; + + event += (portid * (VTD_EVNT_MAX + 1)); + + v = readq(base + VTD_CTRL); + v &= ~VTD_CTRL_EVNT; + v |= FIELD_PREP(VTD_CTRL_EVNT, event); + writeq(v, base + VTD_CTRL); + + if (readq_poll_timeout_atomic(base + VTD_CNTR, v, + FIELD_GET(VTD_CNTR_EVNT, v) == event, + 1, PERF_TIMEOUT)) { + dev_err(priv->dev, "timeout, unmatched vtd event code in counter register.\n"); + return 0; + } + + v = fme_read_perf_cntr_reg(base + VTD_CNTR); + return FIELD_GET(VTD_CNTR_EVNT_CNTR, v); +} + +static int vtd_sip_event_init(struct fme_perf_priv *priv, u32 event, u32 portid) +{ + if (priv->id == FME_FEATURE_ID_GLOBAL_IPERF && + event <= VTD_SIP_EVNT_MAX && is_portid_root(portid)) + return 0; + + return -EINVAL; +} + +static u64 vtd_sip_read_event_counter(struct fme_perf_priv *priv, u32 event, + u32 portid) +{ + void __iomem *base = priv->ioaddr; + u64 v; + + v = readq(base + VTD_SIP_CTRL); + v &= ~VTD_SIP_CTRL_EVNT; + v |= FIELD_PREP(VTD_SIP_CTRL_EVNT, event); + writeq(v, base + VTD_SIP_CTRL); + + if (readq_poll_timeout_atomic(base + VTD_SIP_CNTR, v, + FIELD_GET(VTD_SIP_CNTR_EVNT, v) == event, + 1, PERF_TIMEOUT)) { + dev_err(priv->dev, "timeout, unmatched vtd sip event code in counter register\n"); + return 0; + } + + v = fme_read_perf_cntr_reg(base + VTD_SIP_CNTR); + return FIELD_GET(VTD_SIP_CNTR_EVNT_CNTR, v); +} + +static struct fme_perf_event_ops fme_perf_event_ops[] = { + [FME_EVTYPE_BASIC] = {.event_init = basic_event_init, + .read_counter = basic_read_event_counter,}, + [FME_EVTYPE_CACHE] = {.event_init = cache_event_init, + .read_counter = cache_read_event_counter,}, + [FME_EVTYPE_FABRIC] = {.event_init = fabric_event_init, + .event_destroy = fabric_event_destroy, + .read_counter = fabric_read_event_counter,}, + [FME_EVTYPE_VTD] = {.event_init = vtd_event_init, + .read_counter = vtd_read_event_counter,}, + [FME_EVTYPE_VTD_SIP] = {.event_init = vtd_sip_event_init, + .read_counter = vtd_sip_read_event_counter,}, +}; + +static ssize_t fme_perf_event_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct dev_ext_attribute *eattr; + unsigned long config; + char *ptr = buf; + + eattr = container_of(attr, struct dev_ext_attribute, attr); + config = (unsigned long)eattr->var; + + ptr += sprintf(ptr, "event=0x%02x", (unsigned int)get_event(config)); + ptr += sprintf(ptr, ",evtype=0x%02x", (unsigned int)get_evtype(config)); + + if (is_portid_root(get_portid(config))) + ptr += sprintf(ptr, ",portid=0x%02x\n", FME_PORTID_ROOT); + else + ptr += sprintf(ptr, ",portid=?\n"); + + return (ssize_t)(ptr - buf); +} + +#define FME_EVENT_ATTR(_name) \ + __ATTR(_name, 0444, fme_perf_event_show, NULL) + +#define FME_PORT_EVENT_CONFIG(_event, _type) \ + (void *)((((_event) << FME_EVENT_SHIFT) & FME_EVENT_MASK) | \ + (((_type) << FME_EVTYPE_SHIFT) & FME_EVTYPE_MASK)) + +#define FME_EVENT_CONFIG(_event, _type) \ + (void *)((((_event) << FME_EVENT_SHIFT) & FME_EVENT_MASK) | \ + (((_type) << FME_EVTYPE_SHIFT) & FME_EVTYPE_MASK) | \ + (FME_PORTID_ROOT << FME_PORTID_SHIFT)) + +/* FME Perf Basic Events */ +#define FME_EVENT_BASIC(_name, _event) \ +static struct dev_ext_attribute fme_perf_event_##_name = { \ + .attr = FME_EVENT_ATTR(_name), \ + .var = FME_EVENT_CONFIG(_event, FME_EVTYPE_BASIC), \ +} + +FME_EVENT_BASIC(clock, BASIC_EVNT_CLK); + +static struct attribute *fme_perf_basic_events_attrs[] = { + &fme_perf_event_clock.attr.attr, + NULL, +}; + +static const struct attribute_group fme_perf_basic_events_group = { + .name = "events", + .attrs = fme_perf_basic_events_attrs, +}; + +/* FME Perf Cache Events */ +#define FME_EVENT_CACHE(_name, _event) \ +static struct dev_ext_attribute fme_perf_event_cache_##_name = { \ + .attr = FME_EVENT_ATTR(cache_##_name), \ + .var = FME_EVENT_CONFIG(_event, FME_EVTYPE_CACHE), \ +} + +FME_EVENT_CACHE(read_hit, CACHE_EVNT_RD_HIT); +FME_EVENT_CACHE(read_miss, CACHE_EVNT_RD_MISS); +FME_EVENT_CACHE(write_hit, CACHE_EVNT_WR_HIT); +FME_EVENT_CACHE(write_miss, CACHE_EVNT_WR_MISS); +FME_EVENT_CACHE(hold_request, CACHE_EVNT_HOLD_REQ); +FME_EVENT_CACHE(tx_req_stall, CACHE_EVNT_TX_REQ_STALL); +FME_EVENT_CACHE(rx_req_stall, CACHE_EVNT_RX_REQ_STALL); +FME_EVENT_CACHE(eviction, CACHE_EVNT_EVICTIONS); +FME_EVENT_CACHE(data_write_port_contention, CACHE_EVNT_DATA_WR_PORT_CONTEN); +FME_EVENT_CACHE(tag_write_port_contention, CACHE_EVNT_TAG_WR_PORT_CONTEN); + +static struct attribute *fme_perf_cache_events_attrs[] = { + &fme_perf_event_cache_read_hit.attr.attr, + &fme_perf_event_cache_read_miss.attr.attr, + &fme_perf_event_cache_write_hit.attr.attr, + &fme_perf_event_cache_write_miss.attr.attr, + &fme_perf_event_cache_hold_request.attr.attr, + &fme_perf_event_cache_tx_req_stall.attr.attr, + &fme_perf_event_cache_rx_req_stall.attr.attr, + &fme_perf_event_cache_eviction.attr.attr, + &fme_perf_event_cache_data_write_port_contention.attr.attr, + &fme_perf_event_cache_tag_write_port_contention.attr.attr, + NULL, +}; + +static umode_t fme_perf_events_visible(struct kobject *kobj, + struct attribute *attr, int n) +{ + struct pmu *pmu = dev_get_drvdata(kobj_to_dev(kobj)); + struct fme_perf_priv *priv = to_fme_perf_priv(pmu); + + return (priv->id == FME_FEATURE_ID_GLOBAL_IPERF) ? attr->mode : 0; +} + +static const struct attribute_group fme_perf_cache_events_group = { + .name = "events", + .attrs = fme_perf_cache_events_attrs, + .is_visible = fme_perf_events_visible, +}; + +/* FME Perf Fabric Events */ +#define FME_EVENT_FABRIC(_name, _event) \ +static struct dev_ext_attribute fme_perf_event_fab_##_name = { \ + .attr = FME_EVENT_ATTR(fab_##_name), \ + .var = FME_EVENT_CONFIG(_event, FME_EVTYPE_FABRIC), \ +} + +#define FME_EVENT_FABRIC_PORT(_name, _event) \ +static struct dev_ext_attribute fme_perf_event_fab_port_##_name = { \ + .attr = FME_EVENT_ATTR(fab_port_##_name), \ + .var = FME_PORT_EVENT_CONFIG(_event, FME_EVTYPE_FABRIC), \ +} + +FME_EVENT_FABRIC(pcie0_read, FAB_EVNT_PCIE0_RD); +FME_EVENT_FABRIC(pcie0_write, FAB_EVNT_PCIE0_WR); +FME_EVENT_FABRIC(pcie1_read, FAB_EVNT_PCIE1_RD); +FME_EVENT_FABRIC(pcie1_write, FAB_EVNT_PCIE1_WR); +FME_EVENT_FABRIC(upi_read, FAB_EVNT_UPI_RD); +FME_EVENT_FABRIC(upi_write, FAB_EVNT_UPI_WR); +FME_EVENT_FABRIC(mmio_read, FAB_EVNT_MMIO_RD); +FME_EVENT_FABRIC(mmio_write, FAB_EVNT_MMIO_WR); + +FME_EVENT_FABRIC_PORT(pcie0_read, FAB_EVNT_PCIE0_RD); +FME_EVENT_FABRIC_PORT(pcie0_write, FAB_EVNT_PCIE0_WR); +FME_EVENT_FABRIC_PORT(pcie1_read, FAB_EVNT_PCIE1_RD); +FME_EVENT_FABRIC_PORT(pcie1_write, FAB_EVNT_PCIE1_WR); +FME_EVENT_FABRIC_PORT(upi_read, FAB_EVNT_UPI_RD); +FME_EVENT_FABRIC_PORT(upi_write, FAB_EVNT_UPI_WR); +FME_EVENT_FABRIC_PORT(mmio_read, FAB_EVNT_MMIO_RD); +FME_EVENT_FABRIC_PORT(mmio_write, FAB_EVNT_MMIO_WR); + +static struct attribute *fme_perf_fabric_events_attrs[] = { + &fme_perf_event_fab_pcie0_read.attr.attr, + &fme_perf_event_fab_pcie0_write.attr.attr, + &fme_perf_event_fab_pcie1_read.attr.attr, + &fme_perf_event_fab_pcie1_write.attr.attr, + &fme_perf_event_fab_upi_read.attr.attr, + &fme_perf_event_fab_upi_write.attr.attr, + &fme_perf_event_fab_mmio_read.attr.attr, + &fme_perf_event_fab_mmio_write.attr.attr, + &fme_perf_event_fab_port_pcie0_read.attr.attr, + &fme_perf_event_fab_port_pcie0_write.attr.attr, + &fme_perf_event_fab_port_pcie1_read.attr.attr, + &fme_perf_event_fab_port_pcie1_write.attr.attr, + &fme_perf_event_fab_port_upi_read.attr.attr, + &fme_perf_event_fab_port_upi_write.attr.attr, + &fme_perf_event_fab_port_mmio_read.attr.attr, + &fme_perf_event_fab_port_mmio_write.attr.attr, + NULL, +}; + +static umode_t fme_perf_fabric_events_visible(struct kobject *kobj, + struct attribute *attr, int n) +{ + struct pmu *pmu = dev_get_drvdata(kobj_to_dev(kobj)); + struct fme_perf_priv *priv = to_fme_perf_priv(pmu); + struct dev_ext_attribute *eattr; + unsigned long var; + + eattr = container_of(attr, struct dev_ext_attribute, attr.attr); + var = (unsigned long)eattr->var; + + if (is_fabric_event_supported(priv, get_event(var), get_portid(var))) + return attr->mode; + + return 0; +} + +static const struct attribute_group fme_perf_fabric_events_group = { + .name = "events", + .attrs = fme_perf_fabric_events_attrs, + .is_visible = fme_perf_fabric_events_visible, +}; + +/* FME Perf VTD Events */ +#define FME_EVENT_VTD_PORT(_name, _event) \ +static struct dev_ext_attribute fme_perf_event_vtd_port_##_name = { \ + .attr = FME_EVENT_ATTR(vtd_port_##_name), \ + .var = FME_PORT_EVENT_CONFIG(_event, FME_EVTYPE_VTD), \ +} + +FME_EVENT_VTD_PORT(read_transaction, VTD_EVNT_AFU_MEM_RD_TRANS); +FME_EVENT_VTD_PORT(write_transaction, VTD_EVNT_AFU_MEM_WR_TRANS); +FME_EVENT_VTD_PORT(devtlb_read_hit, VTD_EVNT_AFU_DEVTLB_RD_HIT); +FME_EVENT_VTD_PORT(devtlb_write_hit, VTD_EVNT_AFU_DEVTLB_WR_HIT); +FME_EVENT_VTD_PORT(devtlb_4k_fill, VTD_EVNT_DEVTLB_4K_FILL); +FME_EVENT_VTD_PORT(devtlb_2m_fill, VTD_EVNT_DEVTLB_2M_FILL); +FME_EVENT_VTD_PORT(devtlb_1g_fill, VTD_EVNT_DEVTLB_1G_FILL); + +static struct attribute *fme_perf_vtd_events_attrs[] = { + &fme_perf_event_vtd_port_read_transaction.attr.attr, + &fme_perf_event_vtd_port_write_transaction.attr.attr, + &fme_perf_event_vtd_port_devtlb_read_hit.attr.attr, + &fme_perf_event_vtd_port_devtlb_write_hit.attr.attr, + &fme_perf_event_vtd_port_devtlb_4k_fill.attr.attr, + &fme_perf_event_vtd_port_devtlb_2m_fill.attr.attr, + &fme_perf_event_vtd_port_devtlb_1g_fill.attr.attr, + NULL, +}; + +static const struct attribute_group fme_perf_vtd_events_group = { + .name = "events", + .attrs = fme_perf_vtd_events_attrs, + .is_visible = fme_perf_events_visible, +}; + +/* FME Perf VTD SIP Events */ +#define FME_EVENT_VTD_SIP(_name, _event) \ +static struct dev_ext_attribute fme_perf_event_vtd_sip_##_name = { \ + .attr = FME_EVENT_ATTR(vtd_sip_##_name), \ + .var = FME_EVENT_CONFIG(_event, FME_EVTYPE_VTD_SIP), \ +} + +FME_EVENT_VTD_SIP(iotlb_4k_hit, VTD_SIP_EVNT_IOTLB_4K_HIT); +FME_EVENT_VTD_SIP(iotlb_2m_hit, VTD_SIP_EVNT_IOTLB_2M_HIT); +FME_EVENT_VTD_SIP(iotlb_1g_hit, VTD_SIP_EVNT_IOTLB_1G_HIT); +FME_EVENT_VTD_SIP(slpwc_l3_hit, VTD_SIP_EVNT_SLPWC_L3_HIT); +FME_EVENT_VTD_SIP(slpwc_l4_hit, VTD_SIP_EVNT_SLPWC_L4_HIT); +FME_EVENT_VTD_SIP(rcc_hit, VTD_SIP_EVNT_RCC_HIT); +FME_EVENT_VTD_SIP(iotlb_4k_miss, VTD_SIP_EVNT_IOTLB_4K_MISS); +FME_EVENT_VTD_SIP(iotlb_2m_miss, VTD_SIP_EVNT_IOTLB_2M_MISS); +FME_EVENT_VTD_SIP(iotlb_1g_miss, VTD_SIP_EVNT_IOTLB_1G_MISS); +FME_EVENT_VTD_SIP(slpwc_l3_miss, VTD_SIP_EVNT_SLPWC_L3_MISS); +FME_EVENT_VTD_SIP(slpwc_l4_miss, VTD_SIP_EVNT_SLPWC_L4_MISS); +FME_EVENT_VTD_SIP(rcc_miss, VTD_SIP_EVNT_RCC_MISS); + +static struct attribute *fme_perf_vtd_sip_events_attrs[] = { + &fme_perf_event_vtd_sip_iotlb_4k_hit.attr.attr, + &fme_perf_event_vtd_sip_iotlb_2m_hit.attr.attr, + &fme_perf_event_vtd_sip_iotlb_1g_hit.attr.attr, + &fme_perf_event_vtd_sip_slpwc_l3_hit.attr.attr, + &fme_perf_event_vtd_sip_slpwc_l4_hit.attr.attr, + &fme_perf_event_vtd_sip_rcc_hit.attr.attr, + &fme_perf_event_vtd_sip_iotlb_4k_miss.attr.attr, + &fme_perf_event_vtd_sip_iotlb_2m_miss.attr.attr, + &fme_perf_event_vtd_sip_iotlb_1g_miss.attr.attr, + &fme_perf_event_vtd_sip_slpwc_l3_miss.attr.attr, + &fme_perf_event_vtd_sip_slpwc_l4_miss.attr.attr, + &fme_perf_event_vtd_sip_rcc_miss.attr.attr, + NULL, +}; + +static const struct attribute_group fme_perf_vtd_sip_events_group = { + .name = "events", + .attrs = fme_perf_vtd_sip_events_attrs, + .is_visible = fme_perf_events_visible, +}; + +static const struct attribute_group *fme_perf_events_groups[] = { + &fme_perf_basic_events_group, + &fme_perf_cache_events_group, + &fme_perf_fabric_events_group, + &fme_perf_vtd_events_group, + &fme_perf_vtd_sip_events_group, + NULL, +}; + +static struct fme_perf_event_ops *get_event_ops(u32 evtype) +{ + if (evtype > FME_EVTYPE_MAX) + return NULL; + + return &fme_perf_event_ops[evtype]; +} + +static void fme_perf_event_destroy(struct perf_event *event) +{ + struct fme_perf_event_ops *ops = get_event_ops(event->hw.event_base); + struct fme_perf_priv *priv = to_fme_perf_priv(event->pmu); + + if (ops->event_destroy) + ops->event_destroy(priv, event->hw.idx, event->hw.config_base); +} + +static int fme_perf_event_init(struct perf_event *event) +{ + struct fme_perf_priv *priv = to_fme_perf_priv(event->pmu); + struct hw_perf_event *hwc = &event->hw; + struct fme_perf_event_ops *ops; + u32 eventid, evtype, portid; + + /* test the event attr type check for PMU enumeration */ + if (event->attr.type != event->pmu->type) + return -ENOENT; + + /* + * fme counters are shared across all cores. + * Therefore, it does not support per-process mode. + * Also, it does not support event sampling mode. + */ + if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) + return -EINVAL; + + if (event->cpu < 0) + return -EINVAL; + + if (event->cpu != priv->cpu) + return -EINVAL; + + eventid = get_event(event->attr.config); + portid = get_portid(event->attr.config); + evtype = get_evtype(event->attr.config); + if (evtype > FME_EVTYPE_MAX) + return -EINVAL; + + hwc->event_base = evtype; + hwc->idx = (int)eventid; + hwc->config_base = portid; + + event->destroy = fme_perf_event_destroy; + + dev_dbg(priv->dev, "%s event=0x%x, evtype=0x%x, portid=0x%x,\n", + __func__, eventid, evtype, portid); + + ops = get_event_ops(evtype); + if (ops->event_init) + return ops->event_init(priv, eventid, portid); + + return 0; +} + +static void fme_perf_event_update(struct perf_event *event) +{ + struct fme_perf_event_ops *ops = get_event_ops(event->hw.event_base); + struct fme_perf_priv *priv = to_fme_perf_priv(event->pmu); + struct hw_perf_event *hwc = &event->hw; + u64 now, prev, delta; + + now = ops->read_counter(priv, (u32)hwc->idx, hwc->config_base); + prev = local64_read(&hwc->prev_count); + delta = now - prev; + + local64_add(delta, &event->count); +} + +static void fme_perf_event_start(struct perf_event *event, int flags) +{ + struct fme_perf_event_ops *ops = get_event_ops(event->hw.event_base); + struct fme_perf_priv *priv = to_fme_perf_priv(event->pmu); + struct hw_perf_event *hwc = &event->hw; + u64 count; + + count = ops->read_counter(priv, (u32)hwc->idx, hwc->config_base); + local64_set(&hwc->prev_count, count); +} + +static void fme_perf_event_stop(struct perf_event *event, int flags) +{ + fme_perf_event_update(event); +} + +static int fme_perf_event_add(struct perf_event *event, int flags) +{ + if (flags & PERF_EF_START) + fme_perf_event_start(event, flags); + + return 0; +} + +static void fme_perf_event_del(struct perf_event *event, int flags) +{ + fme_perf_event_stop(event, PERF_EF_UPDATE); +} + +static void fme_perf_event_read(struct perf_event *event) +{ + fme_perf_event_update(event); +} + +static void fme_perf_setup_hardware(struct fme_perf_priv *priv) +{ + void __iomem *base = priv->ioaddr; + u64 v; + + /* read and save current working mode for fabric counters */ + v = readq(base + FAB_CTRL); + + if (FIELD_GET(FAB_PORT_FILTER, v) == FAB_PORT_FILTER_DISABLE) + priv->fab_port_id = FME_PORTID_ROOT; + else + priv->fab_port_id = FIELD_GET(FAB_PORT_ID, v); +} + +static int fme_perf_pmu_register(struct platform_device *pdev, + struct fme_perf_priv *priv) +{ + struct pmu *pmu = &priv->pmu; + char *name; + int ret; + + spin_lock_init(&priv->fab_lock); + + fme_perf_setup_hardware(priv); + + pmu->task_ctx_nr = perf_invalid_context; + pmu->attr_groups = fme_perf_groups; + pmu->attr_update = fme_perf_events_groups; + pmu->event_init = fme_perf_event_init; + pmu->add = fme_perf_event_add; + pmu->del = fme_perf_event_del; + pmu->start = fme_perf_event_start; + pmu->stop = fme_perf_event_stop; + pmu->read = fme_perf_event_read; + pmu->capabilities = PERF_PMU_CAP_NO_INTERRUPT | + PERF_PMU_CAP_NO_EXCLUDE; + + name = devm_kasprintf(priv->dev, GFP_KERNEL, "dfl_fme%d", pdev->id); + + ret = perf_pmu_register(pmu, name, -1); + if (ret) + return ret; + + return 0; +} + +static void fme_perf_pmu_unregister(struct fme_perf_priv *priv) +{ + perf_pmu_unregister(&priv->pmu); +} + +static int fme_perf_offline_cpu(unsigned int cpu, struct hlist_node *node) +{ + struct fme_perf_priv *priv; + int target; + + priv = hlist_entry_safe(node, struct fme_perf_priv, node); + + if (cpu != priv->cpu) + return 0; + + target = cpumask_any_but(cpu_online_mask, cpu); + if (target >= nr_cpu_ids) + return 0; + + priv->cpu = target; + return 0; +} + +static int fme_perf_init(struct platform_device *pdev, + struct dfl_feature *feature) +{ + struct fme_perf_priv *priv; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = &pdev->dev; + priv->ioaddr = feature->ioaddr; + priv->id = feature->id; + priv->cpu = raw_smp_processor_id(); + + ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, + "perf/fpga/dfl_fme:online", + NULL, fme_perf_offline_cpu); + if (ret < 0) + return ret; + + priv->cpuhp_state = ret; + + /* Register the pmu instance for cpu hotplug */ + ret = cpuhp_state_add_instance_nocalls(priv->cpuhp_state, &priv->node); + if (ret) + goto cpuhp_instance_err; + + ret = fme_perf_pmu_register(pdev, priv); + if (ret) + goto pmu_register_err; + + feature->priv = priv; + return 0; + +pmu_register_err: + cpuhp_state_remove_instance_nocalls(priv->cpuhp_state, &priv->node); +cpuhp_instance_err: + cpuhp_remove_multi_state(priv->cpuhp_state); + return ret; +} + +static void fme_perf_uinit(struct platform_device *pdev, + struct dfl_feature *feature) +{ + struct fme_perf_priv *priv = feature->priv; + + fme_perf_pmu_unregister(priv); + cpuhp_state_remove_instance_nocalls(priv->cpuhp_state, &priv->node); + cpuhp_remove_multi_state(priv->cpuhp_state); +} + +const struct dfl_feature_id fme_perf_id_table[] = { + {.id = FME_FEATURE_ID_GLOBAL_IPERF,}, + {.id = FME_FEATURE_ID_GLOBAL_DPERF,}, + {0,} +}; + +const struct dfl_feature_ops fme_perf_ops = { + .init = fme_perf_init, + .uinit = fme_perf_uinit, +}; diff --git a/drivers/fpga/dfl-fme.h b/drivers/fpga/dfl-fme.h index 6685c8ef965b..4195dd68193e 100644 --- a/drivers/fpga/dfl-fme.h +++ b/drivers/fpga/dfl-fme.h @@ -38,5 +38,7 @@ extern const struct dfl_feature_id fme_pr_mgmt_id_table[]; extern const struct dfl_feature_ops fme_global_err_ops; extern const struct dfl_feature_id fme_global_err_id_table[]; extern const struct attribute_group fme_global_err_group; +extern const struct dfl_feature_ops fme_perf_ops; +extern const struct dfl_feature_id fme_perf_id_table[]; #endif /* __DFL_FME_H */ diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c index 96a2b8274a33..990994874bf1 100644 --- a/drivers/fpga/dfl.c +++ b/drivers/fpga/dfl.c @@ -1079,6 +1079,7 @@ static int __init dfl_fpga_init(void) */ int dfl_fpga_cdev_release_port(struct dfl_fpga_cdev *cdev, int port_id) { + struct dfl_feature_platform_data *pdata; struct platform_device *port_pdev; int ret = -ENODEV; @@ -1093,7 +1094,11 @@ int dfl_fpga_cdev_release_port(struct dfl_fpga_cdev *cdev, int port_id) goto put_dev_exit; } - ret = dfl_feature_dev_use_begin(dev_get_platdata(&port_pdev->dev)); + pdata = dev_get_platdata(&port_pdev->dev); + + mutex_lock(&pdata->lock); + ret = dfl_feature_dev_use_begin(pdata, true); + mutex_unlock(&pdata->lock); if (ret) goto put_dev_exit; @@ -1120,6 +1125,7 @@ EXPORT_SYMBOL_GPL(dfl_fpga_cdev_release_port); */ int dfl_fpga_cdev_assign_port(struct dfl_fpga_cdev *cdev, int port_id) { + struct dfl_feature_platform_data *pdata; struct platform_device *port_pdev; int ret = -ENODEV; @@ -1138,7 +1144,12 @@ int dfl_fpga_cdev_assign_port(struct dfl_fpga_cdev *cdev, int port_id) if (ret) goto put_dev_exit; - dfl_feature_dev_use_end(dev_get_platdata(&port_pdev->dev)); + pdata = dev_get_platdata(&port_pdev->dev); + + mutex_lock(&pdata->lock); + dfl_feature_dev_use_end(pdata); + mutex_unlock(&pdata->lock); + cdev->released_port_num--; put_dev_exit: put_device(&port_pdev->dev); diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h index 9f0e656de720..2f5d3052e36e 100644 --- a/drivers/fpga/dfl.h +++ b/drivers/fpga/dfl.h @@ -197,16 +197,16 @@ struct dfl_feature_driver { * feature dev (platform device)'s reources. * @ioaddr: mapped mmio resource address. * @ops: ops of this sub feature. + * @priv: priv data of this feature. */ struct dfl_feature { u64 id; int resource_index; void __iomem *ioaddr; const struct dfl_feature_ops *ops; + void *priv; }; -#define DEV_STATUS_IN_USE 0 - #define FEATURE_DEV_ID_UNUSED (-1) /** @@ -219,8 +219,9 @@ struct dfl_feature { * @dfl_cdev: ptr to container device. * @id: id used for this feature device. * @disable_count: count for port disable. + * @excl_open: set on feature device exclusive open. + * @open_count: count for feature device open. * @num: number for sub features. - * @dev_status: dev status (e.g. DEV_STATUS_IN_USE). * @private: ptr to feature dev private data. * @features: sub features of this feature dev. */ @@ -232,26 +233,46 @@ struct dfl_feature_platform_data { struct dfl_fpga_cdev *dfl_cdev; int id; unsigned int disable_count; - unsigned long dev_status; + bool excl_open; + int open_count; void *private; int num; - struct dfl_feature features[0]; + struct dfl_feature features[]; }; static inline -int dfl_feature_dev_use_begin(struct dfl_feature_platform_data *pdata) +int dfl_feature_dev_use_begin(struct dfl_feature_platform_data *pdata, + bool excl) { - /* Test and set IN_USE flags to ensure file is exclusively used */ - if (test_and_set_bit_lock(DEV_STATUS_IN_USE, &pdata->dev_status)) + if (pdata->excl_open) return -EBUSY; + if (excl) { + if (pdata->open_count) + return -EBUSY; + + pdata->excl_open = true; + } + pdata->open_count++; + return 0; } static inline void dfl_feature_dev_use_end(struct dfl_feature_platform_data *pdata) { - clear_bit_unlock(DEV_STATUS_IN_USE, &pdata->dev_status); + pdata->excl_open = false; + + if (WARN_ON(pdata->open_count <= 0)) + return; + + pdata->open_count--; +} + +static inline +int dfl_feature_dev_use_count(struct dfl_feature_platform_data *pdata) +{ + return pdata->open_count; } static inline diff --git a/drivers/fpga/ice40-spi.c b/drivers/fpga/ice40-spi.c index 56e112e14a10..8d689fea0dab 100644 --- a/drivers/fpga/ice40-spi.c +++ b/drivers/fpga/ice40-spi.c @@ -46,10 +46,16 @@ static int ice40_fpga_ops_write_init(struct fpga_manager *mgr, struct spi_message message; struct spi_transfer assert_cs_then_reset_delay = { .cs_change = 1, - .delay_usecs = ICE40_SPI_RESET_DELAY + .delay = { + .value = ICE40_SPI_RESET_DELAY, + .unit = SPI_DELAY_UNIT_USECS + } }; struct spi_transfer housekeeping_delay_then_release_cs = { - .delay_usecs = ICE40_SPI_HOUSEKEEPING_DELAY + .delay = { + .value = ICE40_SPI_HOUSEKEEPING_DELAY, + .unit = SPI_DELAY_UNIT_USECS + } }; int ret; diff --git a/drivers/fpga/machxo2-spi.c b/drivers/fpga/machxo2-spi.c index 4d8a87641587..b316369156fe 100644 --- a/drivers/fpga/machxo2-spi.c +++ b/drivers/fpga/machxo2-spi.c @@ -157,7 +157,8 @@ static int machxo2_cleanup(struct fpga_manager *mgr) spi_message_init(&msg); tx[1].tx_buf = &refresh; tx[1].len = sizeof(refresh); - tx[1].delay_usecs = MACHXO2_REFRESH_USEC; + tx[1].delay.value = MACHXO2_REFRESH_USEC; + tx[1].delay.unit = SPI_DELAY_UNIT_USECS; spi_message_add_tail(&tx[1], &msg); ret = spi_sync(spi, &msg); if (ret) @@ -208,7 +209,8 @@ static int machxo2_write_init(struct fpga_manager *mgr, spi_message_init(&msg); tx[0].tx_buf = &enable; tx[0].len = sizeof(enable); - tx[0].delay_usecs = MACHXO2_LOW_DELAY_USEC; + tx[0].delay.value = MACHXO2_LOW_DELAY_USEC; + tx[0].delay.unit = SPI_DELAY_UNIT_USECS; spi_message_add_tail(&tx[0], &msg); tx[1].tx_buf = &erase; @@ -269,7 +271,8 @@ static int machxo2_write(struct fpga_manager *mgr, const char *buf, spi_message_init(&msg); tx.tx_buf = payload; tx.len = MACHXO2_BUF_SIZE; - tx.delay_usecs = MACHXO2_HIGH_DELAY_USEC; + tx.delay.value = MACHXO2_HIGH_DELAY_USEC; + tx.delay.unit = SPI_DELAY_UNIT_USECS; spi_message_add_tail(&tx, &msg); ret = spi_sync(spi, &msg); if (ret) { @@ -317,7 +320,8 @@ static int machxo2_write_complete(struct fpga_manager *mgr, spi_message_init(&msg); tx[1].tx_buf = &refresh; tx[1].len = sizeof(refresh); - tx[1].delay_usecs = MACHXO2_REFRESH_USEC; + tx[1].delay.value = MACHXO2_REFRESH_USEC; + tx[1].delay.unit = SPI_DELAY_UNIT_USECS; spi_message_add_tail(&tx[1], &msg); ret = spi_sync(spi, &msg); if (ret) diff --git a/drivers/fpga/stratix10-soc.c b/drivers/fpga/stratix10-soc.c index 215d33789c74..44b7c569d4dc 100644 --- a/drivers/fpga/stratix10-soc.c +++ b/drivers/fpga/stratix10-soc.c @@ -154,11 +154,11 @@ static void s10_receive_callback(struct stratix10_svc_client *client, * Here we set status bits as we receive them. Elsewhere, we always use * test_and_clear_bit() to check status in priv->status */ - for (i = 0; i <= SVC_STATUS_RECONFIG_ERROR; i++) + for (i = 0; i <= SVC_STATUS_ERROR; i++) if (status & (1 << i)) set_bit(i, &priv->status); - if (status & BIT(SVC_STATUS_RECONFIG_BUFFER_DONE)) { + if (status & BIT(SVC_STATUS_BUFFER_DONE)) { s10_unlock_bufs(priv, data->kaddr1); s10_unlock_bufs(priv, data->kaddr2); s10_unlock_bufs(priv, data->kaddr3); @@ -209,8 +209,7 @@ static int s10_ops_write_init(struct fpga_manager *mgr, } ret = 0; - if (!test_and_clear_bit(SVC_STATUS_RECONFIG_REQUEST_OK, - &priv->status)) { + if (!test_and_clear_bit(SVC_STATUS_OK, &priv->status)) { ret = -ETIMEDOUT; goto init_done; } @@ -323,17 +322,15 @@ static int s10_ops_write(struct fpga_manager *mgr, const char *buf, &priv->status_return_completion, S10_BUFFER_TIMEOUT); - if (test_and_clear_bit(SVC_STATUS_RECONFIG_BUFFER_DONE, - &priv->status) || - test_and_clear_bit(SVC_STATUS_RECONFIG_BUFFER_SUBMITTED, + if (test_and_clear_bit(SVC_STATUS_BUFFER_DONE, &priv->status) || + test_and_clear_bit(SVC_STATUS_BUFFER_SUBMITTED, &priv->status)) { ret = 0; continue; } - if (test_and_clear_bit(SVC_STATUS_RECONFIG_ERROR, - &priv->status)) { - dev_err(dev, "ERROR - giving up - SVC_STATUS_RECONFIG_ERROR\n"); + if (test_and_clear_bit(SVC_STATUS_ERROR, &priv->status)) { + dev_err(dev, "ERROR - giving up - SVC_STATUS_ERROR\n"); ret = -EFAULT; break; } @@ -393,13 +390,11 @@ static int s10_ops_write_complete(struct fpga_manager *mgr, timeout = ret; ret = 0; - if (test_and_clear_bit(SVC_STATUS_RECONFIG_COMPLETED, - &priv->status)) + if (test_and_clear_bit(SVC_STATUS_COMPLETED, &priv->status)) break; - if (test_and_clear_bit(SVC_STATUS_RECONFIG_ERROR, - &priv->status)) { - dev_err(dev, "ERROR - giving up - SVC_STATUS_RECONFIG_ERROR\n"); + if (test_and_clear_bit(SVC_STATUS_ERROR, &priv->status)) { + dev_err(dev, "ERROR - giving up - SVC_STATUS_ERROR\n"); ret = -EFAULT; break; } @@ -482,7 +477,8 @@ static int s10_remove(struct platform_device *pdev) } static const struct of_device_id s10_of_match[] = { - { .compatible = "intel,stratix10-soc-fpga-mgr", }, + {.compatible = "intel,stratix10-soc-fpga-mgr"}, + {.compatible = "intel,agilex-soc-fpga-mgr"}, {}, }; diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c index b8a88d21d038..4a1139e05280 100644 --- a/drivers/fpga/zynqmp-fpga.c +++ b/drivers/fpga/zynqmp-fpga.c @@ -40,16 +40,12 @@ static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr, static int zynqmp_fpga_ops_write(struct fpga_manager *mgr, const char *buf, size_t size) { - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); struct zynqmp_fpga_priv *priv; dma_addr_t dma_addr; u32 eemi_flags = 0; char *kbuf; int ret; - if (IS_ERR_OR_NULL(eemi_ops) || !eemi_ops->fpga_load) - return -ENXIO; - priv = mgr->priv; kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL); @@ -63,7 +59,7 @@ static int zynqmp_fpga_ops_write(struct fpga_manager *mgr, if (priv->flags & FPGA_MGR_PARTIAL_RECONFIG) eemi_flags |= XILINX_ZYNQMP_PM_FPGA_PARTIAL; - ret = eemi_ops->fpga_load(dma_addr, size, eemi_flags); + ret = zynqmp_pm_fpga_load(dma_addr, size, eemi_flags); dma_free_coherent(priv->dev, size, kbuf, dma_addr); @@ -78,13 +74,9 @@ static int zynqmp_fpga_ops_write_complete(struct fpga_manager *mgr, static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager *mgr) { - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); - u32 status; + u32 status = 0; - if (IS_ERR_OR_NULL(eemi_ops) || !eemi_ops->fpga_get_status) - return FPGA_MGR_STATE_UNKNOWN; - - eemi_ops->fpga_get_status(&status); + zynqmp_pm_fpga_get_status(&status); if (status & IXR_FPGA_DONE_MASK) return FPGA_MGR_STATE_OPERATING; diff --git a/drivers/gnss/serial.h b/drivers/gnss/serial.h index 980ffdc86c2a..621953f7821d 100644 --- a/drivers/gnss/serial.h +++ b/drivers/gnss/serial.h @@ -16,7 +16,7 @@ struct gnss_serial { struct gnss_device *gdev; speed_t speed; const struct gnss_serial_ops *ops; - unsigned long drvdata[0]; + unsigned long drvdata[]; }; enum gnss_serial_pm_state { diff --git a/drivers/gnss/sirf.c b/drivers/gnss/sirf.c index effed3a8d398..2ecb1d3e8eeb 100644 --- a/drivers/gnss/sirf.c +++ b/drivers/gnss/sirf.c @@ -439,14 +439,18 @@ static int sirf_probe(struct serdev_device *serdev) data->on_off = devm_gpiod_get_optional(dev, "sirf,onoff", GPIOD_OUT_LOW); - if (IS_ERR(data->on_off)) + if (IS_ERR(data->on_off)) { + ret = PTR_ERR(data->on_off); goto err_put_device; + } if (data->on_off) { data->wakeup = devm_gpiod_get_optional(dev, "sirf,wakeup", GPIOD_IN); - if (IS_ERR(data->wakeup)) + if (IS_ERR(data->wakeup)) { + ret = PTR_ERR(data->wakeup); goto err_put_device; + } ret = regulator_enable(data->vcc); if (ret) diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c index 02fc24026872..170aa7689110 100644 --- a/drivers/gpu/drm/drm_fb_helper.c +++ b/drivers/gpu/drm/drm_fb_helper.c @@ -307,13 +307,13 @@ static void drm_fb_helper_sysrq(int dummy1) schedule_work(&drm_fb_helper_restore_work); } -static struct sysrq_key_op sysrq_drm_fb_helper_restore_op = { +static const struct sysrq_key_op sysrq_drm_fb_helper_restore_op = { .handler = drm_fb_helper_sysrq, .help_msg = "force-fb(V)", .action_msg = "Restore framebuffer console", }; #else -static struct sysrq_key_op sysrq_drm_fb_helper_restore_op = { }; +static const struct sysrq_key_op sysrq_drm_fb_helper_restore_op = { }; #endif static void drm_fb_helper_dpms(struct fb_info *info, int dpms_mode) diff --git a/drivers/greybus/Kconfig b/drivers/greybus/Kconfig index b84fcaf8b105..aeea082f1418 100644 --- a/drivers/greybus/Kconfig +++ b/drivers/greybus/Kconfig @@ -3,7 +3,7 @@ menuconfig GREYBUS tristate "Greybus support" depends on SYSFS ---help--- - This option enables the Greybus driver core. Greybus is an + This option enables the Greybus driver core. Greybus is a hardware protocol that was designed to provide Unipro with a sane application layer. It was originally designed for the ARA project, a module phone system, but has shown up in other @@ -12,7 +12,7 @@ menuconfig GREYBUS Say Y here to enable support for these types of drivers. - To compile this code as a module, chose M here: the module + To compile this code as a module, choose M here: the module will be called greybus.ko if GREYBUS @@ -25,7 +25,7 @@ config GREYBUS_ES2 acts as a Greybus "host controller". This device is a bridge from a USB device to a Unipro network. - To compile this code as a module, chose M here: the module + To compile this code as a module, choose M here: the module will be called gb-es2.ko endif # GREYBUS diff --git a/drivers/greybus/arpc.h b/drivers/greybus/arpc.h index c8b83c5cfa79..b9ea81b55b29 100644 --- a/drivers/greybus/arpc.h +++ b/drivers/greybus/arpc.h @@ -21,7 +21,7 @@ struct arpc_request_message { __le16 id; /* RPC unique id */ __le16 size; /* Size in bytes of header + payload */ __u8 type; /* RPC type */ - __u8 data[0]; /* ARPC data */ + __u8 data[]; /* ARPC data */ } __packed; struct arpc_response_message { diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index 0e3e72f0f510..19497d1d92bf 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -2,7 +2,8 @@ # # Makefile for CoreSight drivers. # -obj-$(CONFIG_CORESIGHT) += coresight.o coresight-etm-perf.o coresight-platform.o +obj-$(CONFIG_CORESIGHT) += coresight.o coresight-etm-perf.o \ + coresight-platform.o coresight-sysfs.o obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o \ coresight-tmc-etf.o \ coresight-tmc-etr.o diff --git a/drivers/hwtracing/coresight/coresight-cti-platform.c b/drivers/hwtracing/coresight/coresight-cti-platform.c index 2fdaeec80ee5..98f830c6ed50 100644 --- a/drivers/hwtracing/coresight/coresight-cti-platform.c +++ b/drivers/hwtracing/coresight/coresight-cti-platform.c @@ -2,11 +2,17 @@ /* * Copyright (c) 2019, The Linaro Limited. All rights reserved. */ +#include +#include +#include +#include +#include +#include #include -#include #include "coresight-cti.h" +#include "coresight-priv.h" /* Number of CTI signals in the v8 architecturally defined connection */ #define NR_V8PE_IN_SIGS 2 @@ -429,8 +435,7 @@ static int cti_plat_create_impdef_connections(struct device *dev, } /* get the hardware configuration & connection data. */ -int cti_plat_get_hw_data(struct device *dev, - struct cti_drvdata *drvdata) +static int cti_plat_get_hw_data(struct device *dev, struct cti_drvdata *drvdata) { int rc = 0; struct cti_device *cti_dev = &drvdata->ctidev; diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index 1f8fb7c15e80..392757f3a019 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -4,7 +4,13 @@ * Author: Mike Leach */ +#include #include +#include +#include +#include +#include +#include #include "coresight-cti.h" @@ -1036,8 +1042,8 @@ static int cti_create_con_sysfs_attr(struct device *dev, enum cti_conn_attr_type attr_type, int attr_idx) { - struct dev_ext_attribute *eattr = 0; - char *name = 0; + struct dev_ext_attribute *eattr; + char *name; eattr = devm_kzalloc(dev, sizeof(struct dev_ext_attribute), GFP_KERNEL); @@ -1139,7 +1145,7 @@ static int cti_create_con_attr_set(struct device *dev, int con_idx, } /* create the array of group pointers for the CTI sysfs groups */ -int cti_create_cons_groups(struct device *dev, struct cti_device *ctidev) +static int cti_create_cons_groups(struct device *dev, struct cti_device *ctidev) { int nr_groups; @@ -1156,8 +1162,8 @@ int cti_create_cons_groups(struct device *dev, struct cti_device *ctidev) int cti_create_cons_sysfs(struct device *dev, struct cti_drvdata *drvdata) { struct cti_device *ctidev = &drvdata->ctidev; - int err = 0, con_idx = 0, i; - struct cti_trig_con *tc = NULL; + int err, con_idx = 0, i; + struct cti_trig_con *tc; err = cti_create_cons_groups(dev, ctidev); if (err) diff --git a/drivers/hwtracing/coresight/coresight-cti.c b/drivers/hwtracing/coresight/coresight-cti.c index aa6e0249bd70..40387d58c8e7 100644 --- a/drivers/hwtracing/coresight/coresight-cti.c +++ b/drivers/hwtracing/coresight/coresight-cti.c @@ -4,7 +4,22 @@ * Author: Mike Leach */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include #include +#include + +#include "coresight-priv.h" #include "coresight-cti.h" /** @@ -19,7 +34,7 @@ */ /* net of CTI devices connected via CTM */ -LIST_HEAD(ect_net); +static LIST_HEAD(ect_net); /* protect the list */ static DEFINE_MUTEX(ect_mutex); @@ -27,6 +42,12 @@ static DEFINE_MUTEX(ect_mutex); #define csdev_to_cti_drvdata(csdev) \ dev_get_drvdata(csdev->dev.parent) +/* power management handling */ +static int nr_cti_cpu; + +/* quick lookup list for CPU bound CTIs when power handling */ +static struct cti_drvdata *cti_cpu_drvdata[NR_CPUS]; + /* * CTI naming. CTI bound to cores will have the name cti_cpu where * N is the CPU ID. System CTIs will have the name cti_sys where I @@ -116,6 +137,35 @@ cti_err_not_enabled: return rc; } +/* re-enable CTI on CPU when using CPU hotplug */ +static void cti_cpuhp_enable_hw(struct cti_drvdata *drvdata) +{ + struct cti_config *config = &drvdata->config; + struct device *dev = &drvdata->csdev->dev; + + pm_runtime_get_sync(dev->parent); + spin_lock(&drvdata->spinlock); + config->hw_powered = true; + + /* no need to do anything if no enable request */ + if (!atomic_read(&drvdata->config.enable_req_count)) + goto cti_hp_not_enabled; + + /* try to claim the device */ + if (coresight_claim_device(drvdata->base)) + goto cti_hp_not_enabled; + + cti_write_all_hw_regs(drvdata); + config->hw_enabled = true; + spin_unlock(&drvdata->spinlock); + return; + + /* did not re-enable due to no claim / no request */ +cti_hp_not_enabled: + spin_unlock(&drvdata->spinlock); + pm_runtime_put(dev->parent); +} + /* disable hardware */ static int cti_disable_hw(struct cti_drvdata *drvdata) { @@ -442,6 +492,34 @@ int cti_channel_setop(struct device *dev, enum cti_chan_set_op op, return err; } +static bool cti_add_sysfs_link(struct cti_drvdata *drvdata, + struct cti_trig_con *tc) +{ + struct coresight_sysfs_link link_info; + int link_err = 0; + + link_info.orig = drvdata->csdev; + link_info.orig_name = tc->con_dev_name; + link_info.target = tc->con_dev; + link_info.target_name = dev_name(&drvdata->csdev->dev); + + link_err = coresight_add_sysfs_link(&link_info); + if (link_err) + dev_warn(&drvdata->csdev->dev, + "Failed to set CTI sysfs link %s<=>%s\n", + link_info.orig_name, link_info.target_name); + return !link_err; +} + +static void cti_remove_sysfs_link(struct cti_trig_con *tc) +{ + struct coresight_sysfs_link link_info; + + link_info.orig_name = tc->con_dev_name; + link_info.target = tc->con_dev; + coresight_remove_sysfs_link(&link_info); +} + /* * Look for a matching connection device name in the list of connections. * If found then swap in the csdev name, set trig con association pointer @@ -452,6 +530,8 @@ cti_match_fixup_csdev(struct cti_device *ctidev, const char *node_name, struct coresight_device *csdev) { struct cti_trig_con *tc; + struct cti_drvdata *drvdata = container_of(ctidev, struct cti_drvdata, + ctidev); list_for_each_entry(tc, &ctidev->trig_cons, node) { if (tc->con_dev_name) { @@ -459,7 +539,12 @@ cti_match_fixup_csdev(struct cti_device *ctidev, const char *node_name, /* match: so swap in csdev name & dev */ tc->con_dev_name = dev_name(&csdev->dev); tc->con_dev = csdev; - return true; + /* try to set sysfs link */ + if (cti_add_sysfs_link(drvdata, tc)) + return true; + /* link failed - remove CTI reference */ + tc->con_dev = NULL; + break; } } } @@ -522,6 +607,7 @@ void cti_remove_assoc_from_csdev(struct coresight_device *csdev) ctidev = &ctidrv->ctidev; list_for_each_entry(tc, &ctidev->trig_cons, node) { if (tc->con_dev == csdev->ect_dev) { + cti_remove_sysfs_link(tc); tc->con_dev = NULL; break; } @@ -543,10 +629,16 @@ static void cti_update_conn_xrefs(struct cti_drvdata *drvdata) struct cti_device *ctidev = &drvdata->ctidev; list_for_each_entry(tc, &ctidev->trig_cons, node) { - if (tc->con_dev) - /* set tc->con_dev->ect_dev */ - coresight_set_assoc_ectdev_mutex(tc->con_dev, + if (tc->con_dev) { + /* if we can set the sysfs link */ + if (cti_add_sysfs_link(drvdata, tc)) + /* set the CTI/csdev association */ + coresight_set_assoc_ectdev_mutex(tc->con_dev, drvdata->csdev); + else + /* otherwise remove reference from CTI */ + tc->con_dev = NULL; + } } } @@ -559,10 +651,116 @@ static void cti_remove_conn_xrefs(struct cti_drvdata *drvdata) if (tc->con_dev) { coresight_set_assoc_ectdev_mutex(tc->con_dev, NULL); + cti_remove_sysfs_link(tc); + tc->con_dev = NULL; } } } +/** cti PM callbacks **/ +static int cti_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd, + void *v) +{ + struct cti_drvdata *drvdata; + unsigned int cpu = smp_processor_id(); + int notify_res = NOTIFY_OK; + + if (!cti_cpu_drvdata[cpu]) + return NOTIFY_OK; + + drvdata = cti_cpu_drvdata[cpu]; + + if (WARN_ON_ONCE(drvdata->ctidev.cpu != cpu)) + return NOTIFY_BAD; + + spin_lock(&drvdata->spinlock); + + switch (cmd) { + case CPU_PM_ENTER: + /* CTI regs all static - we have a copy & nothing to save */ + drvdata->config.hw_powered = false; + if (drvdata->config.hw_enabled) + coresight_disclaim_device(drvdata->base); + break; + + case CPU_PM_ENTER_FAILED: + drvdata->config.hw_powered = true; + if (drvdata->config.hw_enabled) { + if (coresight_claim_device(drvdata->base)) + drvdata->config.hw_enabled = false; + } + break; + + case CPU_PM_EXIT: + /* write hardware registers to re-enable. */ + drvdata->config.hw_powered = true; + drvdata->config.hw_enabled = false; + + /* check enable reference count to enable HW */ + if (atomic_read(&drvdata->config.enable_req_count)) { + /* check we can claim the device as we re-power */ + if (coresight_claim_device(drvdata->base)) + goto cti_notify_exit; + + drvdata->config.hw_enabled = true; + cti_write_all_hw_regs(drvdata); + } + break; + + default: + notify_res = NOTIFY_DONE; + break; + } + +cti_notify_exit: + spin_unlock(&drvdata->spinlock); + return notify_res; +} + +static struct notifier_block cti_cpu_pm_nb = { + .notifier_call = cti_cpu_pm_notify, +}; + +/* CPU HP handlers */ +static int cti_starting_cpu(unsigned int cpu) +{ + struct cti_drvdata *drvdata = cti_cpu_drvdata[cpu]; + + if (!drvdata) + return 0; + + cti_cpuhp_enable_hw(drvdata); + return 0; +} + +static int cti_dying_cpu(unsigned int cpu) +{ + struct cti_drvdata *drvdata = cti_cpu_drvdata[cpu]; + + if (!drvdata) + return 0; + + spin_lock(&drvdata->spinlock); + drvdata->config.hw_powered = false; + coresight_disclaim_device(drvdata->base); + spin_unlock(&drvdata->spinlock); + return 0; +} + +/* release PM registrations */ +static void cti_pm_release(struct cti_drvdata *drvdata) +{ + if (drvdata->ctidev.cpu >= 0) { + if (--nr_cti_cpu == 0) { + cpu_pm_unregister_notifier(&cti_cpu_pm_nb); + + cpuhp_remove_state_nocalls( + CPUHP_AP_ARM_CORESIGHT_CTI_STARTING); + } + cti_cpu_drvdata[drvdata->ctidev.cpu] = NULL; + } +} + /** cti ect operations **/ int cti_enable(struct coresight_device *csdev) { @@ -578,12 +776,12 @@ int cti_disable(struct coresight_device *csdev) return cti_disable_hw(drvdata); } -const struct coresight_ops_ect cti_ops_ect = { +static const struct coresight_ops_ect cti_ops_ect = { .enable = cti_enable, .disable = cti_disable, }; -const struct coresight_ops cti_ops = { +static const struct coresight_ops cti_ops = { .ect_ops = &cti_ops_ect, }; @@ -598,6 +796,7 @@ static void cti_device_release(struct device *dev) mutex_lock(&ect_mutex); cti_remove_conn_xrefs(drvdata); + cti_pm_release(drvdata); /* remove from the list */ list_for_each_entry_safe(ect_item, ect_tmp, &ect_net, node) { @@ -673,6 +872,24 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) goto err_out; } + /* setup CPU power management handling for CPU bound CTI devices. */ + if (drvdata->ctidev.cpu >= 0) { + cti_cpu_drvdata[drvdata->ctidev.cpu] = drvdata; + if (!nr_cti_cpu++) { + cpus_read_lock(); + ret = cpuhp_setup_state_nocalls_cpuslocked( + CPUHP_AP_ARM_CORESIGHT_CTI_STARTING, + "arm/coresight_cti:starting", + cti_starting_cpu, cti_dying_cpu); + + if (!ret) + ret = cpu_pm_register_notifier(&cti_cpu_pm_nb); + cpus_read_unlock(); + if (ret) + goto err_out; + } + } + /* create dynamic attributes for connections */ ret = cti_create_cons_sysfs(dev, drvdata); if (ret) { @@ -711,6 +928,7 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) return 0; err_out: + cti_pm_release(drvdata); return ret; } diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h index 004df3ab9dd0..acf7b545e6b9 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -7,8 +7,14 @@ #ifndef _CORESIGHT_CORESIGHT_CTI_H #define _CORESIGHT_CORESIGHT_CTI_H -#include +#include +#include +#include +#include #include +#include +#include + #include "coresight-priv.h" /* diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 3810290e6d07..03e3f2590191 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -717,7 +717,7 @@ static const struct attribute_group coresight_etb_mgmt_group = { .name = "mgmt", }; -const struct attribute_group *coresight_etb_groups[] = { +static const struct attribute_group *coresight_etb_groups[] = { &coresight_etb_group, &coresight_etb_mgmt_group, NULL, diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index e2cb6873c3f2..bf22dcfd3327 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -504,7 +504,7 @@ static int etm_enable_perf(struct coresight_device *csdev, static int etm_enable_sysfs(struct coresight_device *csdev) { struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - struct etm_enable_arg arg = { 0 }; + struct etm_enable_arg arg = { }; int ret; spin_lock(&drvdata->spinlock); diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index ce41482431f9..b673e738bc9a 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -205,7 +205,7 @@ static ssize_t reset_store(struct device *dev, * started state. ARM recommends start-stop logic is set before * each trace run. */ - config->vinst_ctrl |= BIT(0); + config->vinst_ctrl = BIT(0); if (drvdata->nr_addr_cmp == true) { config->mode |= ETM_MODE_VIEWINST_STARTSTOP; /* SSSTATUS, bit[9] */ diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index a90d757f7043..747afc875f91 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -412,7 +412,7 @@ out: static int etm4_enable_sysfs(struct coresight_device *csdev) { struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - struct etm4_enable_arg arg = { 0 }; + struct etm4_enable_arg arg = { }; int ret; spin_lock(&drvdata->spinlock); @@ -791,7 +791,7 @@ static void etm4_set_default_config(struct etmv4_config *config) config->ts_ctrl = 0x0; /* TRCVICTLR::EVENT = 0x01, select the always on logic */ - config->vinst_ctrl |= BIT(0); + config->vinst_ctrl = BIT(0); } static u64 etm4_get_ns_access_type(struct etmv4_config *config) @@ -894,17 +894,8 @@ static void etm4_set_start_stop_filter(struct etmv4_config *config, static void etm4_set_default_filter(struct etmv4_config *config) { - u64 start, stop; - - /* - * Configure address range comparator '0' to encompass all - * possible addresses. - */ - start = 0x0; - stop = ~0x0; - - etm4_set_comparator_filter(config, start, stop, - ETM_DEFAULT_ADDR_COMP); + /* Trace everything 'default' filter achieved by no filtering */ + config->viiectlr = 0x0; /* * TRCVICTLR::SSSTATUS == 1, the start-stop logic is @@ -925,11 +916,9 @@ static void etm4_set_default(struct etmv4_config *config) /* * Make default initialisation trace everything * - * Select the "always true" resource selector on the - * "Enablign Event" line and configure address range comparator - * '0' to trace all the possible address range. From there - * configure the "include/exclude" engine to include address - * range comparator '0'. + * This is done by a minimum default config sufficient to enable + * full instruction trace - with a default filter for trace all + * achieved by having no filtering. */ etm4_set_default_config(config); etm4_set_default_filter(config); @@ -1527,6 +1516,7 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) return 0; err_arch_supported: + etmdrvdata[drvdata->cpu] = NULL; if (--etm4_count == 0) { etm4_cpu_pm_unregister(); @@ -1552,10 +1542,13 @@ static const struct amba_id etm4_ids[] = { CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */ CS_AMBA_ID(0x000bb959), /* Cortex-A73 */ CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */ + CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */ CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */ CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */ - CS_AMBA_ID(0x000bb802), /* Qualcomm Kryo 385 Cortex-A55 */ - CS_AMBA_ID(0x000bb803), /* Qualcomm Kryo 385 Cortex-A75 */ + CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A55 */ + CS_AMBA_UCI_ID(0x000bb803, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A75 */ + CS_AMBA_UCI_ID(0x000bb805, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A55 */ + CS_AMBA_UCI_ID(0x000bb804, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A76 */ CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */ {}, }; diff --git a/drivers/hwtracing/coresight/coresight-platform.c b/drivers/hwtracing/coresight/coresight-platform.c index 43418a2126ff..e4912abda3aa 100644 --- a/drivers/hwtracing/coresight/coresight-platform.c +++ b/drivers/hwtracing/coresight/coresight-platform.c @@ -87,6 +87,7 @@ static void of_coresight_get_ports_legacy(const struct device_node *node, int *nr_inport, int *nr_outport) { struct device_node *ep = NULL; + struct of_endpoint endpoint; int in = 0, out = 0; do { @@ -94,10 +95,16 @@ static void of_coresight_get_ports_legacy(const struct device_node *node, if (!ep) break; - if (of_coresight_legacy_ep_is_input(ep)) - in++; - else - out++; + if (of_graph_parse_endpoint(ep, &endpoint)) + continue; + + if (of_coresight_legacy_ep_is_input(ep)) { + in = (endpoint.port + 1 > in) ? + endpoint.port + 1 : in; + } else { + out = (endpoint.port + 1) > out ? + endpoint.port + 1 : out; + } } while (ep); @@ -137,9 +144,16 @@ of_coresight_count_ports(struct device_node *port_parent) { int i = 0; struct device_node *ep = NULL; + struct of_endpoint endpoint; + + while ((ep = of_graph_get_next_endpoint(port_parent, ep))) { + /* Defer error handling to parsing */ + if (of_graph_parse_endpoint(ep, &endpoint)) + continue; + if (endpoint.port + 1 > i) + i = endpoint.port + 1; + } - while ((ep = of_graph_get_next_endpoint(port_parent, ep))) - i++; return i; } @@ -191,14 +205,12 @@ static int of_coresight_get_cpu(struct device *dev) * Parses the local port, remote device name and the remote port. * * Returns : - * 1 - If the parsing is successful and a connection record - * was created for an output connection. * 0 - If the parsing completed without any fatal errors. * -Errno - Fatal error, abort the scanning. */ static int of_coresight_parse_endpoint(struct device *dev, struct device_node *ep, - struct coresight_connection *conn) + struct coresight_platform_data *pdata) { int ret = 0; struct of_endpoint endpoint, rendpoint; @@ -206,6 +218,7 @@ static int of_coresight_parse_endpoint(struct device *dev, struct device_node *rep = NULL; struct device *rdev = NULL; struct fwnode_handle *rdev_fwnode; + struct coresight_connection *conn; do { /* Parse the local port details */ @@ -232,6 +245,13 @@ static int of_coresight_parse_endpoint(struct device *dev, break; } + conn = &pdata->conns[endpoint.port]; + if (conn->child_fwnode) { + dev_warn(dev, "Duplicate output port %d\n", + endpoint.port); + ret = -EINVAL; + break; + } conn->outport = endpoint.port; /* * Hold the refcount to the target device. This could be @@ -244,7 +264,6 @@ static int of_coresight_parse_endpoint(struct device *dev, conn->child_fwnode = fwnode_handle_get(rdev_fwnode); conn->child_port = rendpoint.port; /* Connection record updated */ - ret = 1; } while (0); of_node_put(rparent); @@ -258,7 +277,6 @@ static int of_get_coresight_platform_data(struct device *dev, struct coresight_platform_data *pdata) { int ret = 0; - struct coresight_connection *conn; struct device_node *ep = NULL; const struct device_node *parent = NULL; bool legacy_binding = false; @@ -287,8 +305,6 @@ static int of_get_coresight_platform_data(struct device *dev, dev_warn_once(dev, "Uses obsolete Coresight DT bindings\n"); } - conn = pdata->conns; - /* Iterate through each output port to discover topology */ while ((ep = of_graph_get_next_endpoint(parent, ep))) { /* @@ -300,15 +316,9 @@ static int of_get_coresight_platform_data(struct device *dev, if (legacy_binding && of_coresight_legacy_ep_is_input(ep)) continue; - ret = of_coresight_parse_endpoint(dev, ep, conn); - switch (ret) { - case 1: - conn++; /* Fall through */ - case 0: - break; - default: + ret = of_coresight_parse_endpoint(dev, ep, pdata); + if (ret) return ret; - } } return 0; @@ -501,7 +511,7 @@ static inline bool acpi_validate_dsd_graph(const union acpi_object *graph) } /* acpi_get_dsd_graph - Find the _DSD Graph property for the given device. */ -const union acpi_object * +static const union acpi_object * acpi_get_dsd_graph(struct acpi_device *adev) { int i; @@ -564,7 +574,7 @@ acpi_validate_coresight_graph(const union acpi_object *cs_graph) * Returns the pointer to the CoreSight Graph Package when found. Otherwise * returns NULL. */ -const union acpi_object * +static const union acpi_object * acpi_get_coresight_graph(struct acpi_device *adev) { const union acpi_object *graph_list, *graph; @@ -647,6 +657,16 @@ static int acpi_coresight_parse_link(struct acpi_device *adev, * coresight_remove_match(). */ conn->child_fwnode = fwnode_handle_get(&r_adev->fwnode); + } else if (dir == ACPI_CORESIGHT_LINK_SLAVE) { + /* + * We are only interested in the port number + * for the input ports at this component. + * Store the port number in child_port. + */ + conn->child_port = fields[0].integer.value; + } else { + /* Invalid direction */ + return -EINVAL; } return dir; @@ -692,10 +712,20 @@ static int acpi_coresight_parse_graph(struct acpi_device *adev, return dir; if (dir == ACPI_CORESIGHT_LINK_MASTER) { - pdata->nr_outport++; + if (ptr->outport > pdata->nr_outport) + pdata->nr_outport = ptr->outport; ptr++; } else { - pdata->nr_inport++; + WARN_ON(pdata->nr_inport == ptr->child_port); + /* + * We do not track input port connections for a device. + * However we need the highest port number described, + * which can be recorded now and reuse this connection + * record for an output connection. Hence, do not move + * the ptr for input connections + */ + if (ptr->child_port > pdata->nr_inport) + pdata->nr_inport = ptr->child_port; } } @@ -704,8 +734,13 @@ static int acpi_coresight_parse_graph(struct acpi_device *adev, return rc; /* Copy the connection information to the final location */ - for (i = 0; i < pdata->nr_outport; i++) - pdata->conns[i] = conns[i]; + for (i = 0; conns + i < ptr; i++) { + int port = conns[i].outport; + + /* Duplicate output port */ + WARN_ON(pdata->conns[port].child_fwnode); + pdata->conns[port] = conns[i]; + } devm_kfree(&adev->dev, conns); return 0; @@ -822,7 +857,7 @@ coresight_get_platform_data(struct device *dev) error: if (!IS_ERR_OR_NULL(pdata)) /* Cleanup the connection information */ - coresight_release_platform_data(pdata); + coresight_release_platform_data(NULL, pdata); return ERR_PTR(ret); } EXPORT_SYMBOL_GPL(coresight_get_platform_data); diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index 890f9a5c97c6..36c943ae94d5 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -153,6 +153,15 @@ struct coresight_device *coresight_get_sink_by_id(u32 id); struct list_head *coresight_build_path(struct coresight_device *csdev, struct coresight_device *sink); void coresight_release_path(struct list_head *path); +int coresight_add_sysfs_link(struct coresight_sysfs_link *info); +void coresight_remove_sysfs_link(struct coresight_sysfs_link *info); +int coresight_create_conns_sysfs_group(struct coresight_device *csdev); +void coresight_remove_conns_sysfs_group(struct coresight_device *csdev); +int coresight_make_links(struct coresight_device *orig, + struct coresight_connection *conn, + struct coresight_device *target); +void coresight_remove_links(struct coresight_device *orig, + struct coresight_connection *conn); #ifdef CONFIG_CORESIGHT_SOURCE_ETM3X extern int etm_readl_cp14(u32 off, unsigned int *val); @@ -206,12 +215,16 @@ cti_remove_assoc_from_csdev(struct coresight_device *csdev) {} /* extract the data value from a UCI structure given amba_id pointer. */ static inline void *coresight_get_uci_data(const struct amba_id *id) { - if (id->data) - return ((struct amba_cs_uci_id *)(id->data))->data; - return 0; + struct amba_cs_uci_id *uci_id = id->data; + + if (!uci_id) + return NULL; + + return uci_id->data; } -void coresight_release_platform_data(struct coresight_platform_data *pdata); +void coresight_release_platform_data(struct coresight_device *csdev, + struct coresight_platform_data *pdata); struct coresight_device * coresight_find_csdev_by_fwnode(struct fwnode_handle *r_fwnode); void coresight_set_assoc_ectdev_mutex(struct coresight_device *csdev, diff --git a/drivers/hwtracing/coresight/coresight-sysfs.c b/drivers/hwtracing/coresight/coresight-sysfs.c new file mode 100644 index 000000000000..82afeaf2ccc4 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-sysfs.c @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019, Linaro Limited, All rights reserved. + * Author: Mike Leach + */ + +#include +#include + +#include "coresight-priv.h" + +/* + * Connections group - links attribute. + * Count of created links between coresight components in the group. + */ +static ssize_t nr_links_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct coresight_device *csdev = to_coresight_device(dev); + + return sprintf(buf, "%d\n", csdev->nr_links); +} +static DEVICE_ATTR_RO(nr_links); + +static struct attribute *coresight_conns_attrs[] = { + &dev_attr_nr_links.attr, + NULL, +}; + +static struct attribute_group coresight_conns_group = { + .attrs = coresight_conns_attrs, + .name = "connections", +}; + +/* + * Create connections group for CoreSight devices. + * This group will then be used to collate the sysfs links between + * devices. + */ +int coresight_create_conns_sysfs_group(struct coresight_device *csdev) +{ + int ret = 0; + + if (!csdev) + return -EINVAL; + + ret = sysfs_create_group(&csdev->dev.kobj, &coresight_conns_group); + if (ret) + return ret; + + csdev->has_conns_grp = true; + return ret; +} + +void coresight_remove_conns_sysfs_group(struct coresight_device *csdev) +{ + if (!csdev) + return; + + if (csdev->has_conns_grp) { + sysfs_remove_group(&csdev->dev.kobj, &coresight_conns_group); + csdev->has_conns_grp = false; + } +} + +int coresight_add_sysfs_link(struct coresight_sysfs_link *info) +{ + int ret = 0; + + if (!info) + return -EINVAL; + if (!info->orig || !info->target || + !info->orig_name || !info->target_name) + return -EINVAL; + if (!info->orig->has_conns_grp || !info->target->has_conns_grp) + return -EINVAL; + + /* first link orig->target */ + ret = sysfs_add_link_to_group(&info->orig->dev.kobj, + coresight_conns_group.name, + &info->target->dev.kobj, + info->orig_name); + if (ret) + return ret; + + /* second link target->orig */ + ret = sysfs_add_link_to_group(&info->target->dev.kobj, + coresight_conns_group.name, + &info->orig->dev.kobj, + info->target_name); + + /* error in second link - remove first - otherwise inc counts */ + if (ret) { + sysfs_remove_link_from_group(&info->orig->dev.kobj, + coresight_conns_group.name, + info->orig_name); + } else { + info->orig->nr_links++; + info->target->nr_links++; + } + + return ret; +} + +void coresight_remove_sysfs_link(struct coresight_sysfs_link *info) +{ + if (!info) + return; + if (!info->orig || !info->target || + !info->orig_name || !info->target_name) + return; + + sysfs_remove_link_from_group(&info->orig->dev.kobj, + coresight_conns_group.name, + info->orig_name); + + sysfs_remove_link_from_group(&info->target->dev.kobj, + coresight_conns_group.name, + info->target_name); + + info->orig->nr_links--; + info->target->nr_links--; +} + +/* + * coresight_make_links: Make a link for a connection from a @orig + * device to @target, represented by @conn. + * + * e.g, for devOrig[output_X] -> devTarget[input_Y] is represented + * as two symbolic links : + * + * /sys/.../devOrig/out:X -> /sys/.../devTarget/ + * /sys/.../devTarget/in:Y -> /sys/.../devOrig/ + * + * The link names are allocated for a device where it appears. i.e, the + * "out" link on the master and "in" link on the slave device. + * The link info is stored in the connection record for avoiding + * the reconstruction of names for removal. + */ +int coresight_make_links(struct coresight_device *orig, + struct coresight_connection *conn, + struct coresight_device *target) +{ + int ret = -ENOMEM; + char *outs = NULL, *ins = NULL; + struct coresight_sysfs_link *link = NULL; + + do { + outs = devm_kasprintf(&orig->dev, GFP_KERNEL, + "out:%d", conn->outport); + if (!outs) + break; + ins = devm_kasprintf(&target->dev, GFP_KERNEL, + "in:%d", conn->child_port); + if (!ins) + break; + link = devm_kzalloc(&orig->dev, + sizeof(struct coresight_sysfs_link), + GFP_KERNEL); + if (!link) + break; + + link->orig = orig; + link->target = target; + link->orig_name = outs; + link->target_name = ins; + + ret = coresight_add_sysfs_link(link); + if (ret) + break; + + conn->link = link; + + /* + * Install the device connection. This also indicates that + * the links are operational on both ends. + */ + conn->child_dev = target; + return 0; + } while (0); + + return ret; +} + +/* + * coresight_remove_links: Remove the sysfs links for a given connection @conn, + * from @orig device to @target device. See coresight_make_links() for more + * details. + */ +void coresight_remove_links(struct coresight_device *orig, + struct coresight_connection *conn) +{ + if (!orig || !conn->link) + return; + + coresight_remove_sysfs_link(conn->link); + + devm_kfree(&conn->child_dev->dev, conn->link->target_name); + devm_kfree(&orig->dev, conn->link->orig_name); + devm_kfree(&orig->dev, conn->link); + conn->link = NULL; + conn->child_dev = NULL; +} diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index d0cc3985b72a..36cce2bfb744 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -596,13 +596,6 @@ int tmc_read_prepare_etb(struct tmc_drvdata *drvdata) goto out; } - /* There is no point in reading a TMC in HW FIFO mode */ - mode = readl_relaxed(drvdata->base + TMC_MODE); - if (mode != TMC_MODE_CIRCULAR_BUFFER) { - ret = -EINVAL; - goto out; - } - /* Don't interfere if operated from Perf */ if (drvdata->mode == CS_MODE_PERF) { ret = -EINVAL; @@ -616,8 +609,15 @@ int tmc_read_prepare_etb(struct tmc_drvdata *drvdata) } /* Disable the TMC if need be */ - if (drvdata->mode == CS_MODE_SYSFS) + if (drvdata->mode == CS_MODE_SYSFS) { + /* There is no point in reading a TMC in HW FIFO mode */ + mode = readl_relaxed(drvdata->base + TMC_MODE); + if (mode != TMC_MODE_CIRCULAR_BUFFER) { + ret = -EINVAL; + goto out; + } __tmc_etb_disable_hw(drvdata); + } drvdata->reading = true; out: diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c index 1cf82fa58289..39fba1d16e6e 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.c +++ b/drivers/hwtracing/coresight/coresight-tmc.c @@ -361,7 +361,7 @@ static const struct attribute_group coresight_tmc_mgmt_group = { .name = "mgmt", }; -const struct attribute_group *coresight_tmc_groups[] = { +static const struct attribute_group *coresight_tmc_groups[] = { &coresight_tmc_group, &coresight_tmc_mgmt_group, NULL, diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c index c71553c09f8e..f3efbb3b2b4d 100644 --- a/drivers/hwtracing/coresight/coresight.c +++ b/drivers/hwtracing/coresight/coresight.c @@ -1031,7 +1031,7 @@ static void coresight_device_release(struct device *dev) static int coresight_orphan_match(struct device *dev, void *data) { - int i; + int i, ret = 0; bool still_orphan = false; struct coresight_device *csdev, *i_csdev; struct coresight_connection *conn; @@ -1053,49 +1053,62 @@ static int coresight_orphan_match(struct device *dev, void *data) for (i = 0; i < i_csdev->pdata->nr_outport; i++) { conn = &i_csdev->pdata->conns[i]; + /* Skip the port if FW doesn't describe it */ + if (!conn->child_fwnode) + continue; /* We have found at least one orphan connection */ if (conn->child_dev == NULL) { /* Does it match this newly added device? */ - if (conn->child_fwnode == csdev->dev.fwnode) - conn->child_dev = csdev; - else + if (conn->child_fwnode == csdev->dev.fwnode) { + ret = coresight_make_links(i_csdev, + conn, csdev); + if (ret) + return ret; + } else { /* This component still has an orphan */ still_orphan = true; + } } } i_csdev->orphan = still_orphan; /* - * Returning '0' ensures that all known component on the - * bus will be checked. + * Returning '0' in case we didn't encounter any error, + * ensures that all known component on the bus will be checked. */ return 0; } -static void coresight_fixup_orphan_conns(struct coresight_device *csdev) +static int coresight_fixup_orphan_conns(struct coresight_device *csdev) { - /* - * No need to check for a return value as orphan connection(s) - * are hooked-up with each newly added component. - */ - bus_for_each_dev(&coresight_bustype, NULL, + return bus_for_each_dev(&coresight_bustype, NULL, csdev, coresight_orphan_match); } -static void coresight_fixup_device_conns(struct coresight_device *csdev) +static int coresight_fixup_device_conns(struct coresight_device *csdev) { - int i; + int i, ret = 0; for (i = 0; i < csdev->pdata->nr_outport; i++) { struct coresight_connection *conn = &csdev->pdata->conns[i]; + if (!conn->child_fwnode) + continue; conn->child_dev = coresight_find_csdev_by_fwnode(conn->child_fwnode); - if (!conn->child_dev) + if (conn->child_dev) { + ret = coresight_make_links(csdev, conn, + conn->child_dev); + if (ret) + break; + } else { csdev->orphan = true; + } } + + return 0; } static int coresight_remove_match(struct device *dev, void *data) @@ -1118,12 +1131,12 @@ static int coresight_remove_match(struct device *dev, void *data) for (i = 0; i < iterator->pdata->nr_outport; i++) { conn = &iterator->pdata->conns[i]; - if (conn->child_dev == NULL) + if (conn->child_dev == NULL || conn->child_fwnode == NULL) continue; if (csdev->dev.fwnode == conn->child_fwnode) { iterator->orphan = true; - conn->child_dev = NULL; + coresight_remove_links(iterator, conn); /* * Drop the reference to the handle for the remote * device acquired in parsing the connections from @@ -1213,16 +1226,27 @@ postcore_initcall(coresight_init); * coresight_release_platform_data: Release references to the devices connected * to the output port of this device. */ -void coresight_release_platform_data(struct coresight_platform_data *pdata) +void coresight_release_platform_data(struct coresight_device *csdev, + struct coresight_platform_data *pdata) { int i; + struct coresight_connection *conns = pdata->conns; for (i = 0; i < pdata->nr_outport; i++) { - if (pdata->conns[i].child_fwnode) { - fwnode_handle_put(pdata->conns[i].child_fwnode); + /* If we have made the links, remove them now */ + if (csdev && conns[i].child_dev) + coresight_remove_links(csdev, &conns[i]); + /* + * Drop the refcount and clear the handle as this device + * is going away + */ + if (conns[i].child_fwnode) { + fwnode_handle_put(conns[i].child_fwnode); pdata->conns[i].child_fwnode = NULL; } } + if (csdev) + coresight_remove_conns_sysfs_group(csdev); } struct coresight_device *coresight_register(struct coresight_desc *desc) @@ -1304,11 +1328,19 @@ struct coresight_device *coresight_register(struct coresight_desc *desc) mutex_lock(&coresight_mutex); - coresight_fixup_device_conns(csdev); - coresight_fixup_orphan_conns(csdev); - cti_add_assoc_to_csdev(csdev); + ret = coresight_create_conns_sysfs_group(csdev); + if (!ret) + ret = coresight_fixup_device_conns(csdev); + if (!ret) + ret = coresight_fixup_orphan_conns(csdev); + if (!ret) + cti_add_assoc_to_csdev(csdev); mutex_unlock(&coresight_mutex); + if (ret) { + coresight_unregister(csdev); + return ERR_PTR(ret); + } return csdev; @@ -1316,7 +1348,7 @@ err_free_csdev: kfree(csdev); err_out: /* Cleanup the connection information */ - coresight_release_platform_data(desc->pdata); + coresight_release_platform_data(NULL, desc->pdata); return ERR_PTR(ret); } EXPORT_SYMBOL_GPL(coresight_register); @@ -1326,7 +1358,7 @@ void coresight_unregister(struct coresight_device *csdev) etm_perf_del_symlink_sink(csdev); /* Remove references of that device in the topology */ coresight_remove_conns(csdev); - coresight_release_platform_data(csdev->pdata); + coresight_release_platform_data(csdev, csdev->pdata); device_unregister(&csdev->dev); } EXPORT_SYMBOL_GPL(coresight_unregister); diff --git a/drivers/iio/accel/Kconfig b/drivers/iio/accel/Kconfig index 5d91a6dda894..1080637ca40e 100644 --- a/drivers/iio/accel/Kconfig +++ b/drivers/iio/accel/Kconfig @@ -89,13 +89,13 @@ config ADXL372_I2C module will be called adxl372_i2c. config BMA180 - tristate "Bosch BMA180/BMA25x 3-Axis Accelerometer Driver" - depends on I2C + tristate "Bosch BMA023/BMA1x0/BMA25x 3-Axis Accelerometer Driver" + depends on I2C && INPUT_BMA150=n select IIO_BUFFER select IIO_TRIGGERED_BUFFER help - Say Y here if you want to build a driver for the Bosch BMA180 or - BMA25x triaxial acceleration sensor. + Say Y here if you want to build a driver for the Bosch BMA023, BMA150 + BMA180, SMB380, or BMA25x triaxial acceleration sensor. To compile this driver as a module, choose M here: the module will be called bma180. @@ -238,7 +238,7 @@ config IIO_ST_ACCEL_3AXIS Say yes here to build support for STMicroelectronics accelerometers: LSM303DLH, LSM303DLHC, LIS3DH, LSM330D, LSM330DL, LSM330DLC, LIS331DLH, LSM303DL, LSM303DLM, LSM330, LIS2DH12, H3LIS331DL, - LNG2DM, LIS3DE, LIS2DE12 + LNG2DM, LIS3DE, LIS2DE12, LIS2HH12 This driver can also be built as a module. If so, these modules will be created: diff --git a/drivers/iio/accel/bma180.c b/drivers/iio/accel/bma180.c index fcd91d5f05fd..265722e4b13f 100644 --- a/drivers/iio/accel/bma180.c +++ b/drivers/iio/accel/bma180.c @@ -7,6 +7,7 @@ * Support for BMA250 (c) Peter Meerwald * * SPI is not supported by driver + * BMA023/BMA150/SMB380: 7-bit I2C slave address 0x38 * BMA180: 7-bit I2C slave address 0x40 or 0x41 * BMA250: 7-bit I2C slave address 0x18 or 0x19 * BMA254: 7-bit I2C slave address 0x18 or 0x19 @@ -33,6 +34,8 @@ #define BMA180_IRQ_NAME "bma180_event" enum chip_ids { + BMA023, + BMA150, BMA180, BMA250, BMA254, @@ -48,7 +51,7 @@ struct bma180_part_info { unsigned int num_scales; const int *bw_table; unsigned int num_bw; - int center_temp; + int temp_offset; u8 int_reset_reg, int_reset_mask; u8 sleep_reg, sleep_mask; @@ -57,13 +60,25 @@ struct bma180_part_info { u8 power_reg, power_mask, lowpower_val; u8 int_enable_reg, int_enable_mask; u8 int_map_reg, int_enable_dataready_int1_mask; - u8 softreset_reg; + u8 softreset_reg, softreset_val; int (*chip_config)(struct bma180_data *data); void (*chip_disable)(struct bma180_data *data); }; /* Register set */ +#define BMA023_CTRL_REG0 0x0a +#define BMA023_CTRL_REG1 0x0b +#define BMA023_CTRL_REG2 0x14 +#define BMA023_CTRL_REG3 0x15 + +#define BMA023_RANGE_MASK GENMASK(4, 3) /* Range of accel values */ +#define BMA023_BW_MASK GENMASK(2, 0) /* Accel bandwidth */ +#define BMA023_SLEEP BIT(0) +#define BMA023_INT_RESET_MASK BIT(6) +#define BMA023_NEW_DATA_INT BIT(5) /* Intr every new accel data is ready */ +#define BMA023_RESET_VAL BIT(1) + #define BMA180_CHIP_ID 0x00 /* Need to distinguish BMA180 from other */ #define BMA180_ACC_X_LSB 0x02 /* First of 6 registers of accel data */ #define BMA180_TEMP 0x08 @@ -94,6 +109,7 @@ struct bma180_part_info { /* We have to write this value in reset register to do soft reset */ #define BMA180_RESET_VAL 0xb6 +#define BMA023_ID_REG_VAL 0x02 #define BMA180_ID_REG_VAL 0x03 #define BMA250_ID_REG_VAL 0x03 #define BMA254_ID_REG_VAL 0xfa /* 250 decimal */ @@ -156,6 +172,9 @@ enum bma180_chan { TEMP }; +static int bma023_bw_table[] = { 25, 50, 100, 190, 375, 750, 1500 }; /* Hz */ +static int bma023_scale_table[] = { 2452, 4903, 9709, }; + static int bma180_bw_table[] = { 10, 20, 40, 75, 150, 300 }; /* Hz */ static int bma180_scale_table[] = { 1275, 1863, 2452, 3727, 4903, 9709, 19417 }; @@ -319,7 +338,8 @@ static int bma180_set_pmode(struct bma180_data *data, bool mode) static int bma180_soft_reset(struct bma180_data *data) { int ret = i2c_smbus_write_byte_data(data->client, - data->part_info->softreset_reg, BMA180_RESET_VAL); + data->part_info->softreset_reg, + data->part_info->softreset_val); if (ret) dev_err(&data->client->dev, "failed to reset the chip\n"); @@ -349,17 +369,37 @@ static int bma180_chip_init(struct bma180_data *data) */ msleep(20); - ret = bma180_set_new_data_intr_state(data, false); - if (ret) - return ret; + return bma180_set_new_data_intr_state(data, false); +} - return bma180_set_pmode(data, false); +static int bma023_chip_config(struct bma180_data *data) +{ + int ret = bma180_chip_init(data); + + if (ret) + goto err; + + ret = bma180_set_bw(data, 50); /* 50 Hz */ + if (ret) + goto err; + ret = bma180_set_scale(data, 2452); /* 2 G */ + if (ret) + goto err; + + return 0; + +err: + dev_err(&data->client->dev, "failed to config the chip\n"); + return ret; } static int bma180_chip_config(struct bma180_data *data) { int ret = bma180_chip_init(data); + if (ret) + goto err; + ret = bma180_set_pmode(data, false); if (ret) goto err; ret = bma180_set_bits(data, BMA180_CTRL_REG0, BMA180_DIS_WAKE_UP, 1); @@ -389,6 +429,9 @@ static int bma25x_chip_config(struct bma180_data *data) { int ret = bma180_chip_init(data); + if (ret) + goto err; + ret = bma180_set_pmode(data, false); if (ret) goto err; ret = bma180_set_bw(data, 16); /* 16 Hz */ @@ -413,6 +456,17 @@ err: return ret; } +static void bma023_chip_disable(struct bma180_data *data) +{ + if (bma180_set_sleep_state(data, true)) + goto err; + + return; + +err: + dev_err(&data->client->dev, "failed to disable the chip\n"); +} + static void bma180_chip_disable(struct bma180_data *data) { if (bma180_set_new_data_intr_state(data, false)) @@ -512,8 +566,12 @@ static int bma180_read_raw(struct iio_dev *indio_dev, iio_device_release_direct_mode(indio_dev); if (ret < 0) return ret; - *val = sign_extend32(ret >> chan->scan_type.shift, - chan->scan_type.realbits - 1); + if (chan->scan_type.sign == 's') { + *val = sign_extend32(ret >> chan->scan_type.shift, + chan->scan_type.realbits - 1); + } else { + *val = ret; + } return IIO_VAL_INT; case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: *val = data->bw; @@ -531,7 +589,7 @@ static int bma180_read_raw(struct iio_dev *indio_dev, return -EINVAL; } case IIO_CHAN_INFO_OFFSET: - *val = data->part_info->center_temp; + *val = data->part_info->temp_offset; return IIO_VAL_INT; default: return -EINVAL; @@ -609,6 +667,11 @@ static const struct iio_enum bma180_power_mode_enum = { .set = bma180_set_power_mode, }; +static const struct iio_chan_spec_ext_info bma023_ext_info[] = { + IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bma180_accel_get_mount_matrix), + { } +}; + static const struct iio_chan_spec_ext_info bma180_ext_info[] = { IIO_ENUM("power_mode", true, &bma180_power_mode_enum), IIO_ENUM_AVAILABLE("power_mode", &bma180_power_mode_enum), @@ -616,6 +679,35 @@ static const struct iio_chan_spec_ext_info bma180_ext_info[] = { { } }; +#define BMA023_ACC_CHANNEL(_axis, _bits) { \ + .type = IIO_ACCEL, \ + .modified = 1, \ + .channel2 = IIO_MOD_##_axis, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ + .scan_index = AXIS_##_axis, \ + .scan_type = { \ + .sign = 's', \ + .realbits = _bits, \ + .storagebits = 16, \ + .shift = 16 - _bits, \ + }, \ + .ext_info = bma023_ext_info, \ +} + +#define BMA150_TEMP_CHANNEL { \ + .type = IIO_TEMP, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET), \ + .scan_index = TEMP, \ + .scan_type = { \ + .sign = 'u', \ + .realbits = 8, \ + .storagebits = 16, \ + }, \ +} + #define BMA180_ACC_CHANNEL(_axis, _bits) { \ .type = IIO_ACCEL, \ .modified = 1, \ @@ -645,6 +737,21 @@ static const struct iio_chan_spec_ext_info bma180_ext_info[] = { }, \ } +static const struct iio_chan_spec bma023_channels[] = { + BMA023_ACC_CHANNEL(X, 10), + BMA023_ACC_CHANNEL(Y, 10), + BMA023_ACC_CHANNEL(Z, 10), + IIO_CHAN_SOFT_TIMESTAMP(4), +}; + +static const struct iio_chan_spec bma150_channels[] = { + BMA023_ACC_CHANNEL(X, 10), + BMA023_ACC_CHANNEL(Y, 10), + BMA023_ACC_CHANNEL(Z, 10), + BMA150_TEMP_CHANNEL, + IIO_CHAN_SOFT_TIMESTAMP(4), +}; + static const struct iio_chan_spec bma180_channels[] = { BMA180_ACC_CHANNEL(X, 14), BMA180_ACC_CHANNEL(Y, 14), @@ -670,6 +777,63 @@ static const struct iio_chan_spec bma254_channels[] = { }; static const struct bma180_part_info bma180_part_info[] = { + [BMA023] = { + .chip_id = BMA023_ID_REG_VAL, + .channels = bma023_channels, + .num_channels = ARRAY_SIZE(bma023_channels), + .scale_table = bma023_scale_table, + .num_scales = ARRAY_SIZE(bma023_scale_table), + .bw_table = bma023_bw_table, + .num_bw = ARRAY_SIZE(bma023_bw_table), + /* No temperature channel */ + .temp_offset = 0, + .int_reset_reg = BMA023_CTRL_REG0, + .int_reset_mask = BMA023_INT_RESET_MASK, + .sleep_reg = BMA023_CTRL_REG0, + .sleep_mask = BMA023_SLEEP, + .bw_reg = BMA023_CTRL_REG2, + .bw_mask = BMA023_BW_MASK, + .scale_reg = BMA023_CTRL_REG2, + .scale_mask = BMA023_RANGE_MASK, + /* No power mode on bma023 */ + .power_reg = 0, + .power_mask = 0, + .lowpower_val = 0, + .int_enable_reg = BMA023_CTRL_REG3, + .int_enable_mask = BMA023_NEW_DATA_INT, + .softreset_reg = BMA023_CTRL_REG0, + .softreset_val = BMA023_RESET_VAL, + .chip_config = bma023_chip_config, + .chip_disable = bma023_chip_disable, + }, + [BMA150] = { + .chip_id = BMA023_ID_REG_VAL, + .channels = bma150_channels, + .num_channels = ARRAY_SIZE(bma150_channels), + .scale_table = bma023_scale_table, + .num_scales = ARRAY_SIZE(bma023_scale_table), + .bw_table = bma023_bw_table, + .num_bw = ARRAY_SIZE(bma023_bw_table), + .temp_offset = -60, /* 0 LSB @ -30 degree C */ + .int_reset_reg = BMA023_CTRL_REG0, + .int_reset_mask = BMA023_INT_RESET_MASK, + .sleep_reg = BMA023_CTRL_REG0, + .sleep_mask = BMA023_SLEEP, + .bw_reg = BMA023_CTRL_REG2, + .bw_mask = BMA023_BW_MASK, + .scale_reg = BMA023_CTRL_REG2, + .scale_mask = BMA023_RANGE_MASK, + /* No power mode on bma150 */ + .power_reg = 0, + .power_mask = 0, + .lowpower_val = 0, + .int_enable_reg = BMA023_CTRL_REG3, + .int_enable_mask = BMA023_NEW_DATA_INT, + .softreset_reg = BMA023_CTRL_REG0, + .softreset_val = BMA023_RESET_VAL, + .chip_config = bma023_chip_config, + .chip_disable = bma023_chip_disable, + }, [BMA180] = { .chip_id = BMA180_ID_REG_VAL, .channels = bma180_channels, @@ -678,7 +842,7 @@ static const struct bma180_part_info bma180_part_info[] = { .num_scales = ARRAY_SIZE(bma180_scale_table), .bw_table = bma180_bw_table, .num_bw = ARRAY_SIZE(bma180_bw_table), - .center_temp = 48, /* 0 LSB @ 24 degree C */ + .temp_offset = 48, /* 0 LSB @ 24 degree C */ .int_reset_reg = BMA180_CTRL_REG0, .int_reset_mask = BMA180_RESET_INT, .sleep_reg = BMA180_CTRL_REG0, @@ -693,6 +857,7 @@ static const struct bma180_part_info bma180_part_info[] = { .int_enable_reg = BMA180_CTRL_REG3, .int_enable_mask = BMA180_NEW_DATA_INT, .softreset_reg = BMA180_RESET, + .softreset_val = BMA180_RESET_VAL, .chip_config = bma180_chip_config, .chip_disable = bma180_chip_disable, }, @@ -704,7 +869,7 @@ static const struct bma180_part_info bma180_part_info[] = { .num_scales = ARRAY_SIZE(bma25x_scale_table), .bw_table = bma25x_bw_table, .num_bw = ARRAY_SIZE(bma25x_bw_table), - .center_temp = 48, /* 0 LSB @ 24 degree C */ + .temp_offset = 48, /* 0 LSB @ 24 degree C */ .int_reset_reg = BMA250_INT_RESET_REG, .int_reset_mask = BMA250_INT_RESET_MASK, .sleep_reg = BMA250_POWER_REG, @@ -721,6 +886,7 @@ static const struct bma180_part_info bma180_part_info[] = { .int_map_reg = BMA250_INT_MAP_REG, .int_enable_dataready_int1_mask = BMA250_INT1_DATA_MASK, .softreset_reg = BMA250_RESET_REG, + .softreset_val = BMA180_RESET_VAL, .chip_config = bma25x_chip_config, .chip_disable = bma25x_chip_disable, }, @@ -732,7 +898,7 @@ static const struct bma180_part_info bma180_part_info[] = { .num_scales = ARRAY_SIZE(bma25x_scale_table), .bw_table = bma25x_bw_table, .num_bw = ARRAY_SIZE(bma25x_bw_table), - .center_temp = 46, /* 0 LSB @ 23 degree C */ + .temp_offset = 46, /* 0 LSB @ 23 degree C */ .int_reset_reg = BMA254_INT_RESET_REG, .int_reset_mask = BMA254_INT_RESET_MASK, .sleep_reg = BMA254_POWER_REG, @@ -749,6 +915,7 @@ static const struct bma180_part_info bma180_part_info[] = { .int_map_reg = BMA254_INT_MAP_REG, .int_enable_dataready_int1_mask = BMA254_INT1_DATA_MASK, .softreset_reg = BMA254_RESET_REG, + .softreset_val = BMA180_RESET_VAL, .chip_config = bma25x_chip_config, .chip_disable = bma25x_chip_disable, }, @@ -990,15 +1157,26 @@ static SIMPLE_DEV_PM_OPS(bma180_pm_ops, bma180_suspend, bma180_resume); #endif static const struct i2c_device_id bma180_ids[] = { + { "bma023", BMA023 }, + { "bma150", BMA150 }, { "bma180", BMA180 }, { "bma250", BMA250 }, { "bma254", BMA254 }, + { "smb380", BMA150 }, { } }; MODULE_DEVICE_TABLE(i2c, bma180_ids); static const struct of_device_id bma180_of_match[] = { + { + .compatible = "bosch,bma023", + .data = (void *)BMA023 + }, + { + .compatible = "bosch,bma150", + .data = (void *)BMA150 + }, { .compatible = "bosch,bma180", .data = (void *)BMA180 @@ -1011,6 +1189,10 @@ static const struct of_device_id bma180_of_match[] = { .compatible = "bosch,bma254", .data = (void *)BMA254 }, + { + .compatible = "bosch,smb380", + .data = (void *)BMA150 + }, { } }; MODULE_DEVICE_TABLE(of, bma180_of_match); @@ -1030,5 +1212,5 @@ module_i2c_driver(bma180_driver); MODULE_AUTHOR("Kravchenko Oleksandr "); MODULE_AUTHOR("Texas Instruments, Inc."); -MODULE_DESCRIPTION("Bosch BMA180/BMA25x triaxial acceleration sensor"); +MODULE_DESCRIPTION("Bosch BMA023/BMA1x0/BMA25x triaxial acceleration sensor"); MODULE_LICENSE("GPL"); diff --git a/drivers/iio/accel/dmard06.c b/drivers/iio/accel/dmard06.c index 2bf210fa4ba6..ef89bded7390 100644 --- a/drivers/iio/accel/dmard06.c +++ b/drivers/iio/accel/dmard06.c @@ -6,6 +6,7 @@ */ #include +#include #include #include @@ -226,7 +227,7 @@ static struct i2c_driver dmard06_driver = { .id_table = dmard06_id, .driver = { .name = DMARD06_DRV_NAME, - .of_match_table = of_match_ptr(dmard06_of_match), + .of_match_table = dmard06_of_match, .pm = DMARD06_PM_OPS, }, }; diff --git a/drivers/iio/accel/hid-sensor-accel-3d.c b/drivers/iio/accel/hid-sensor-accel-3d.c index 0d9e2def2b25..0ec0533448bc 100644 --- a/drivers/iio/accel/hid-sensor-accel-3d.c +++ b/drivers/iio/accel/hid-sensor-accel-3d.c @@ -14,8 +14,6 @@ #include #include #include -#include -#include #include "../common/hid-sensors/hid-sensor-trigger.h" enum accel_3d_channel { @@ -391,18 +389,13 @@ static int hid_accel_3d_probe(struct platform_device *pdev) indio_dev->name = name; indio_dev->modes = INDIO_DIRECT_MODE; - ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time, - NULL, NULL); - if (ret) { - dev_err(&pdev->dev, "failed to initialize trigger buffer\n"); - goto error_free_dev_mem; - } atomic_set(&accel_state->common_attributes.data_ready, 0); + ret = hid_sensor_setup_trigger(indio_dev, name, &accel_state->common_attributes); if (ret < 0) { dev_err(&pdev->dev, "trigger setup failed\n"); - goto error_unreg_buffer_funcs; + goto error_free_dev_mem; } ret = iio_device_register(indio_dev); @@ -426,9 +419,7 @@ static int hid_accel_3d_probe(struct platform_device *pdev) error_iio_unreg: iio_device_unregister(indio_dev); error_remove_trigger: - hid_sensor_remove_trigger(&accel_state->common_attributes); -error_unreg_buffer_funcs: - iio_triggered_buffer_cleanup(indio_dev); + hid_sensor_remove_trigger(indio_dev, &accel_state->common_attributes); error_free_dev_mem: kfree(indio_dev->channels); return ret; @@ -443,8 +434,7 @@ static int hid_accel_3d_remove(struct platform_device *pdev) sensor_hub_remove_callback(hsdev, hsdev->usage); iio_device_unregister(indio_dev); - hid_sensor_remove_trigger(&accel_state->common_attributes); - iio_triggered_buffer_cleanup(indio_dev); + hid_sensor_remove_trigger(indio_dev, &accel_state->common_attributes); kfree(indio_dev->channels); return 0; diff --git a/drivers/iio/accel/kxsd9-i2c.c b/drivers/iio/accel/kxsd9-i2c.c index 38411e1c155b..b580d605f848 100644 --- a/drivers/iio/accel/kxsd9-i2c.c +++ b/drivers/iio/accel/kxsd9-i2c.c @@ -2,6 +2,7 @@ #include #include #include +#include #include #include #include @@ -21,8 +22,8 @@ static int kxsd9_i2c_probe(struct i2c_client *i2c, regmap = devm_regmap_init_i2c(i2c, &config); if (IS_ERR(regmap)) { - dev_err(&i2c->dev, "Failed to register i2c regmap %d\n", - (int)PTR_ERR(regmap)); + dev_err(&i2c->dev, "Failed to register i2c regmap: %pe\n", + regmap); return PTR_ERR(regmap); } @@ -36,15 +37,11 @@ static int kxsd9_i2c_remove(struct i2c_client *client) return kxsd9_common_remove(&client->dev); } -#ifdef CONFIG_OF static const struct of_device_id kxsd9_of_match[] = { { .compatible = "kionix,kxsd9", }, { }, }; MODULE_DEVICE_TABLE(of, kxsd9_of_match); -#else -#define kxsd9_of_match NULL -#endif static const struct i2c_device_id kxsd9_i2c_id[] = { {"kxsd9", 0}, @@ -55,7 +52,7 @@ MODULE_DEVICE_TABLE(i2c, kxsd9_i2c_id); static struct i2c_driver kxsd9_i2c_driver = { .driver = { .name = "kxsd9", - .of_match_table = of_match_ptr(kxsd9_of_match), + .of_match_table = kxsd9_of_match, .pm = &kxsd9_dev_pm_ops, }, .probe = kxsd9_i2c_probe, diff --git a/drivers/iio/accel/mxc4005.c b/drivers/iio/accel/mxc4005.c index 3d5bea651923..9d07642c0de1 100644 --- a/drivers/iio/accel/mxc4005.c +++ b/drivers/iio/accel/mxc4005.c @@ -135,7 +135,7 @@ static int mxc4005_read_xyz(struct mxc4005_data *data) int ret; ret = regmap_bulk_read(data->regmap, MXC4005_REG_XOUT_UPPER, - (u8 *) data->buffer, sizeof(data->buffer)); + data->buffer, sizeof(data->buffer)); if (ret < 0) { dev_err(data->dev, "failed to read axes\n"); return ret; @@ -150,7 +150,7 @@ static int mxc4005_read_axis(struct mxc4005_data *data, __be16 reg; int ret; - ret = regmap_bulk_read(data->regmap, addr, (u8 *) ®, sizeof(reg)); + ret = regmap_bulk_read(data->regmap, addr, ®, sizeof(reg)); if (ret < 0) { dev_err(data->dev, "failed to read reg %02x\n", addr); return ret; diff --git a/drivers/iio/accel/st_accel.h b/drivers/iio/accel/st_accel.h index 5b13e293cade..5d356288e001 100644 --- a/drivers/iio/accel/st_accel.h +++ b/drivers/iio/accel/st_accel.h @@ -35,6 +35,7 @@ enum st_accel_type { LIS2DW12, LIS3DHH, LIS2DE12, + LIS2HH12, ST_ACCEL_MAX, }; @@ -59,6 +60,7 @@ enum st_accel_type { #define LIS3DHH_ACCEL_DEV_NAME "lis3dhh" #define LIS3DE_ACCEL_DEV_NAME "lis3de" #define LIS2DE12_ACCEL_DEV_NAME "lis2de12" +#define LIS2HH12_ACCEL_DEV_NAME "lis2hh12" /** * struct st_sensors_platform_data - default accel platform data diff --git a/drivers/iio/accel/st_accel_buffer.c b/drivers/iio/accel/st_accel_buffer.c index 9f2b40474b8e..b5c814ef1637 100644 --- a/drivers/iio/accel/st_accel_buffer.c +++ b/drivers/iio/accel/st_accel_buffer.c @@ -37,8 +37,7 @@ static int st_accel_buffer_postenable(struct iio_dev *indio_dev) if (err < 0) return err; - err = st_sensors_set_axis_enable(indio_dev, - (u8)indio_dev->active_scan_mask[0]); + err = st_sensors_set_axis_enable(indio_dev, indio_dev->active_scan_mask[0]); if (err < 0) goto st_accel_buffer_predisable; diff --git a/drivers/iio/accel/st_accel_core.c b/drivers/iio/accel/st_accel_core.c index 7320275c7e56..43c50167d220 100644 --- a/drivers/iio/accel/st_accel_core.c +++ b/drivers/iio/accel/st_accel_core.c @@ -904,6 +904,83 @@ static const struct st_sensor_settings st_accel_sensors_settings[] = { .multi_read_bit = true, .bootime = 2, }, + { + .wai = 0x41, + .wai_addr = ST_SENSORS_DEFAULT_WAI_ADDRESS, + .sensors_supported = { + [0] = LIS2HH12_ACCEL_DEV_NAME, + }, + .ch = (struct iio_chan_spec *)st_accel_16bit_channels, + .odr = { + .addr = 0x20, + .mask = 0x70, + .odr_avl = { + { .hz = 10, .value = 0x01, }, + { .hz = 50, .value = 0x02, }, + { .hz = 100, .value = 0x03, }, + { .hz = 200, .value = 0x04, }, + { .hz = 400, .value = 0x05, }, + { .hz = 800, .value = 0x06, }, + }, + }, + .pw = { + .addr = 0x20, + .mask = 0x70, + .value_off = ST_SENSORS_DEFAULT_POWER_OFF_VALUE, + }, + .enable_axis = { + .addr = ST_SENSORS_DEFAULT_AXIS_ADDR, + .mask = ST_SENSORS_DEFAULT_AXIS_MASK, + }, + .fs = { + .addr = 0x23, + .mask = 0x30, + .fs_avl = { + [0] = { + .num = ST_ACCEL_FS_AVL_2G, + .value = 0x00, + .gain = IIO_G_TO_M_S_2(61), + }, + [1] = { + .num = ST_ACCEL_FS_AVL_4G, + .value = 0x02, + .gain = IIO_G_TO_M_S_2(122), + }, + [2] = { + .num = ST_ACCEL_FS_AVL_8G, + .value = 0x03, + .gain = IIO_G_TO_M_S_2(244), + }, + }, + }, + .bdu = { + .addr = 0x20, + .mask = 0x08, + }, + .drdy_irq = { + .int1 = { + .addr = 0x22, + .mask = 0x01, + }, + .int2 = { + .addr = 0x25, + .mask = 0x01, + }, + .addr_ihl = 0x24, + .mask_ihl = 0x02, + .stat_drdy = { + .addr = ST_SENSORS_DEFAULT_STAT_ADDR, + .mask = 0x07, + }, + }, + .sim = { + .addr = 0x23, + .value = BIT(0), + }, + .multi_read_bit = true, + .bootime = 2, + }, + }; static int st_accel_read_raw(struct iio_dev *indio_dev, @@ -1170,8 +1247,7 @@ EXPORT_SYMBOL(st_accel_get_settings); int st_accel_common_probe(struct iio_dev *indio_dev) { struct st_sensor_data *adata = iio_priv(indio_dev); - struct st_sensors_platform_data *pdata = - (struct st_sensors_platform_data *)adata->dev->platform_data; + struct st_sensors_platform_data *pdata = dev_get_platdata(adata->dev); struct iio_chan_spec *channels; size_t channels_size; int err; @@ -1204,8 +1280,7 @@ int st_accel_common_probe(struct iio_dev *indio_dev) "failed to apply ACPI orientation data: %d\n", err); indio_dev->channels = channels; - adata->current_fullscale = (struct st_sensor_fullscale_avl *) - &adata->sensor_settings->fs.fs_avl[0]; + adata->current_fullscale = &adata->sensor_settings->fs.fs_avl[0]; adata->odr = adata->sensor_settings->odr.odr_avl[0].hz; if (!pdata) diff --git a/drivers/iio/accel/st_accel_i2c.c b/drivers/iio/accel/st_accel_i2c.c index 6b283be26ebc..360e16f2cadb 100644 --- a/drivers/iio/accel/st_accel_i2c.c +++ b/drivers/iio/accel/st_accel_i2c.c @@ -104,6 +104,10 @@ static const struct of_device_id st_accel_of_match[] = { .compatible = "st,lis2de12", .data = LIS2DE12_ACCEL_DEV_NAME, }, + { + .compatible = "st,lis2hh12", + .data = LIS2HH12_ACCEL_DEV_NAME, + }, {}, }; MODULE_DEVICE_TABLE(of, st_accel_of_match); @@ -138,6 +142,7 @@ static const struct i2c_device_id st_accel_id_table[] = { { LIS2DW12_ACCEL_DEV_NAME }, { LIS3DE_ACCEL_DEV_NAME }, { LIS2DE12_ACCEL_DEV_NAME }, + { LIS2HH12_ACCEL_DEV_NAME }, {}, }; MODULE_DEVICE_TABLE(i2c, st_accel_id_table); diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index a864ede98114..ff3569635ce0 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -246,6 +246,41 @@ config AD799X To compile this driver as a module, choose M here: the module will be called ad799x. +config AD9467 + tristate "Analog Devices AD9467 High Speed ADC driver" + depends on SPI + select ADI_AXI_ADC + help + Say yes here to build support for Analog Devices: + * AD9467 16-Bit, 200 MSPS/250 MSPS Analog-to-Digital Converter + + The driver requires the assistance of the AXI ADC IP core to operate, + since SPI is used for configuration only, while data has to be + streamed into memory via DMA. + + To compile this driver as a module, choose M here: the module will be + called ad9467. + +config ADI_AXI_ADC + tristate "Analog Devices Generic AXI ADC IP core driver" + select IIO_BUFFER + select IIO_BUFFER_HW_CONSUMER + select IIO_BUFFER_DMAENGINE + help + Say yes here to build support for Analog Devices Generic + AXI ADC IP core. The IP core is used for interfacing with + analog-to-digital (ADC) converters that require either a high-speed + serial interface (JESD204B/C) or a source synchronous parallel + interface (LVDS/CMOS). + Typically (for such devices) SPI will be used for configuration only, + while this IP core handles the streaming of data into memory via DMA. + + Link: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip + If unsure, say N (but it's safe to say "Y"). + + To compile this driver as a module, choose M here: the + module will be called adi-axi-adc. + config ASPEED_ADC tristate "Aspeed ADC" depends on ARCH_ASPEED || COMPILE_TEST @@ -595,6 +630,16 @@ config MAX1118 To compile this driver as a module, choose M here: the module will be called max1118. +config MAX1241 + tristate "Maxim max1241 ADC driver" + depends on SPI_MASTER + help + Say yes here to build support for Maxim max1241 12-bit, single-channel + ADC. + + To compile this driver as a module, choose M here: the module will be + called max1241. + config MAX1363 tristate "Maxim max1363 ADC driver" depends on I2C diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index 78a1963a14f3..90f94ada7b30 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -26,6 +26,8 @@ obj-$(CONFIG_AD7793) += ad7793.o obj-$(CONFIG_AD7887) += ad7887.o obj-$(CONFIG_AD7949) += ad7949.o obj-$(CONFIG_AD799X) += ad799x.o +obj-$(CONFIG_AD9467) += ad9467.o +obj-$(CONFIG_ADI_AXI_ADC) += adi-axi-adc.o obj-$(CONFIG_ASPEED_ADC) += aspeed_adc.o obj-$(CONFIG_AT91_ADC) += at91_adc.o obj-$(CONFIG_AT91_SAMA5D2_ADC) += at91-sama5d2_adc.o @@ -57,6 +59,7 @@ obj-$(CONFIG_LTC2497) += ltc2497.o ltc2497-core.o obj-$(CONFIG_MAX1027) += max1027.o obj-$(CONFIG_MAX11100) += max11100.o obj-$(CONFIG_MAX1118) += max1118.o +obj-$(CONFIG_MAX1241) += max1241.o obj-$(CONFIG_MAX1363) += max1363.o obj-$(CONFIG_MAX9611) += max9611.o obj-$(CONFIG_MCP320X) += mcp320x.o diff --git a/drivers/iio/adc/ad7476.c b/drivers/iio/adc/ad7476.c index 76747488044b..4e816d714ad2 100644 --- a/drivers/iio/adc/ad7476.c +++ b/drivers/iio/adc/ad7476.c @@ -12,9 +12,11 @@ #include #include #include +#include #include #include #include +#include #include #include @@ -27,6 +29,8 @@ struct ad7476_state; struct ad7476_chip_info { unsigned int int_vref_uv; struct iio_chan_spec channel[2]; + /* channels used when convst gpio is defined */ + struct iio_chan_spec convst_channel[2]; void (*reset)(struct ad7476_state *); }; @@ -34,6 +38,7 @@ struct ad7476_state { struct spi_device *spi; const struct ad7476_chip_info *chip_info; struct regulator *reg; + struct gpio_desc *convst_gpio; struct spi_transfer xfer; struct spi_message msg; /* @@ -64,6 +69,17 @@ enum ad7476_supported_device_ids { ID_ADS7868, }; +static void ad7091_convst(struct ad7476_state *st) +{ + if (!st->convst_gpio) + return; + + gpiod_set_value(st->convst_gpio, 0); + udelay(1); /* CONVST pulse width: 10 ns min */ + gpiod_set_value(st->convst_gpio, 1); + udelay(1); /* Conversion time: 650 ns max */ +} + static irqreturn_t ad7476_trigger_handler(int irq, void *p) { struct iio_poll_func *pf = p; @@ -71,6 +87,8 @@ static irqreturn_t ad7476_trigger_handler(int irq, void *p) struct ad7476_state *st = iio_priv(indio_dev); int b_sent; + ad7091_convst(st); + b_sent = spi_sync(st->spi, &st->msg); if (b_sent < 0) goto done; @@ -93,6 +111,8 @@ static int ad7476_scan_direct(struct ad7476_state *st) { int ret; + ad7091_convst(st); + ret = spi_sync(st->spi, &st->msg); if (ret) return ret; @@ -160,6 +180,8 @@ static int ad7476_read_raw(struct iio_dev *indio_dev, #define AD7940_CHAN(bits) _AD7476_CHAN((bits), 15 - (bits), \ BIT(IIO_CHAN_INFO_RAW)) #define AD7091R_CHAN(bits) _AD7476_CHAN((bits), 16 - (bits), 0) +#define AD7091R_CONVST_CHAN(bits) _AD7476_CHAN((bits), 16 - (bits), \ + BIT(IIO_CHAN_INFO_RAW)) #define ADS786X_CHAN(bits) _AD7476_CHAN((bits), 12 - (bits), \ BIT(IIO_CHAN_INFO_RAW)) @@ -167,6 +189,8 @@ static const struct ad7476_chip_info ad7476_chip_info_tbl[] = { [ID_AD7091R] = { .channel[0] = AD7091R_CHAN(12), .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), + .convst_channel[0] = AD7091R_CONVST_CHAN(12), + .convst_channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), .reset = ad7091_reset, }, [ID_AD7276] = { @@ -232,6 +256,13 @@ static const struct iio_info ad7476_info = { .read_raw = &ad7476_read_raw, }; +static void ad7476_reg_disable(void *data) +{ + struct ad7476_state *st = data; + + regulator_disable(st->reg); +} + static int ad7476_probe(struct spi_device *spi) { struct ad7476_state *st; @@ -254,6 +285,17 @@ static int ad7476_probe(struct spi_device *spi) if (ret) return ret; + ret = devm_add_action_or_reset(&spi->dev, ad7476_reg_disable, + st); + if (ret) + return ret; + + st->convst_gpio = devm_gpiod_get_optional(&spi->dev, + "adi,conversion-start", + GPIOD_OUT_LOW); + if (IS_ERR(st->convst_gpio)) + return PTR_ERR(st->convst_gpio); + spi_set_drvdata(spi, indio_dev); st->spi = spi; @@ -266,6 +308,9 @@ static int ad7476_probe(struct spi_device *spi) indio_dev->channels = st->chip_info->channel; indio_dev->num_channels = 2; indio_dev->info = &ad7476_info; + + if (st->convst_gpio) + indio_dev->channels = st->chip_info->convst_channel; /* Setup default message */ st->xfer.rx_buf = &st->data; @@ -295,19 +340,8 @@ error_disable_reg: return ret; } -static int ad7476_remove(struct spi_device *spi) -{ - struct iio_dev *indio_dev = spi_get_drvdata(spi); - struct ad7476_state *st = iio_priv(indio_dev); - - iio_device_unregister(indio_dev); - iio_triggered_buffer_cleanup(indio_dev); - regulator_disable(st->reg); - - return 0; -} - static const struct spi_device_id ad7476_id[] = { + {"ad7091", ID_AD7091R}, {"ad7091r", ID_AD7091R}, {"ad7273", ID_AD7277}, {"ad7274", ID_AD7276}, @@ -343,7 +377,6 @@ static struct spi_driver ad7476_driver = { .name = "ad7476", }, .probe = ad7476_probe, - .remove = ad7476_remove, .id_table = ad7476_id, }; module_spi_driver(ad7476_driver); diff --git a/drivers/iio/adc/ad7780.c b/drivers/iio/adc/ad7780.c index 291c1a898129..f47606ebbbbe 100644 --- a/drivers/iio/adc/ad7780.c +++ b/drivers/iio/adc/ad7780.c @@ -206,10 +206,29 @@ static const struct ad_sigma_delta_info ad7780_sigma_delta_info = { .irq_flags = IRQF_TRIGGER_LOW, }; -#define AD7780_CHANNEL(bits, wordsize) \ - AD_SD_CHANNEL(1, 0, 0, bits, 32, (wordsize) - (bits)) -#define AD7170_CHANNEL(bits, wordsize) \ - AD_SD_CHANNEL_NO_SAMP_FREQ(1, 0, 0, bits, 32, (wordsize) - (bits)) +#define _AD7780_CHANNEL(_bits, _wordsize, _mask_all) \ +{ \ + .type = IIO_VOLTAGE, \ + .indexed = 1, \ + .channel = 0, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_OFFSET), \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ + .info_mask_shared_by_all = _mask_all, \ + .scan_index = 1, \ + .scan_type = { \ + .sign = 'u', \ + .realbits = (_bits), \ + .storagebits = 32, \ + .shift = (_wordsize) - (_bits), \ + .endianness = IIO_BE, \ + }, \ +} + +#define AD7780_CHANNEL(_bits, _wordsize) \ + _AD7780_CHANNEL(_bits, _wordsize, BIT(IIO_CHAN_INFO_SAMP_FREQ)) +#define AD7170_CHANNEL(_bits, _wordsize) \ + _AD7780_CHANNEL(_bits, _wordsize, 0) static const struct ad7780_chip_info ad7780_chip_info_tbl[] = { [ID_AD7170] = { diff --git a/drivers/iio/adc/ad7791.c b/drivers/iio/adc/ad7791.c index abb239392631..48432b6f6002 100644 --- a/drivers/iio/adc/ad7791.c +++ b/drivers/iio/adc/ad7791.c @@ -64,25 +64,73 @@ #define AD7791_MODE_SEL_MASK (0x3 << 6) #define AD7791_MODE_SEL(x) ((x) << 6) +#define __AD7991_CHANNEL(_si, _channel1, _channel2, _address, _bits, \ + _storagebits, _shift, _extend_name, _type, _mask_all) \ + { \ + .type = (_type), \ + .differential = (_channel2 == -1 ? 0 : 1), \ + .indexed = 1, \ + .channel = (_channel1), \ + .channel2 = (_channel2), \ + .address = (_address), \ + .extend_name = (_extend_name), \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_OFFSET), \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ + .info_mask_shared_by_all = _mask_all, \ + .scan_index = (_si), \ + .scan_type = { \ + .sign = 'u', \ + .realbits = (_bits), \ + .storagebits = (_storagebits), \ + .shift = (_shift), \ + .endianness = IIO_BE, \ + }, \ + } + +#define AD7991_SHORTED_CHANNEL(_si, _channel, _address, _bits, \ + _storagebits, _shift) \ + __AD7991_CHANNEL(_si, _channel, _channel, _address, _bits, \ + _storagebits, _shift, "shorted", IIO_VOLTAGE, \ + BIT(IIO_CHAN_INFO_SAMP_FREQ)) + +#define AD7991_CHANNEL(_si, _channel, _address, _bits, \ + _storagebits, _shift) \ + __AD7991_CHANNEL(_si, _channel, -1, _address, _bits, \ + _storagebits, _shift, NULL, IIO_VOLTAGE, \ + BIT(IIO_CHAN_INFO_SAMP_FREQ)) + +#define AD7991_DIFF_CHANNEL(_si, _channel1, _channel2, _address, _bits, \ + _storagebits, _shift) \ + __AD7991_CHANNEL(_si, _channel1, _channel2, _address, _bits, \ + _storagebits, _shift, NULL, IIO_VOLTAGE, \ + BIT(IIO_CHAN_INFO_SAMP_FREQ)) + +#define AD7991_SUPPLY_CHANNEL(_si, _channel, _address, _bits, _storagebits, \ + _shift) \ + __AD7991_CHANNEL(_si, _channel, -1, _address, _bits, \ + _storagebits, _shift, "supply", IIO_VOLTAGE, \ + BIT(IIO_CHAN_INFO_SAMP_FREQ)) + #define DECLARE_AD7787_CHANNELS(name, bits, storagebits) \ const struct iio_chan_spec name[] = { \ - AD_SD_DIFF_CHANNEL(0, 0, 0, AD7791_CH_AIN1P_AIN1N, \ + AD7991_DIFF_CHANNEL(0, 0, 0, AD7791_CH_AIN1P_AIN1N, \ (bits), (storagebits), 0), \ - AD_SD_CHANNEL(1, 1, AD7791_CH_AIN2, (bits), (storagebits), 0), \ - AD_SD_SHORTED_CHANNEL(2, 0, AD7791_CH_AIN1N_AIN1N, \ + AD7991_CHANNEL(1, 1, AD7791_CH_AIN2, (bits), (storagebits), 0), \ + AD7991_SHORTED_CHANNEL(2, 0, AD7791_CH_AIN1N_AIN1N, \ (bits), (storagebits), 0), \ - AD_SD_SUPPLY_CHANNEL(3, 2, AD7791_CH_AVDD_MONITOR, \ + AD7991_SUPPLY_CHANNEL(3, 2, AD7791_CH_AVDD_MONITOR, \ (bits), (storagebits), 0), \ IIO_CHAN_SOFT_TIMESTAMP(4), \ } #define DECLARE_AD7791_CHANNELS(name, bits, storagebits) \ const struct iio_chan_spec name[] = { \ - AD_SD_DIFF_CHANNEL(0, 0, 0, AD7791_CH_AIN1P_AIN1N, \ + AD7991_DIFF_CHANNEL(0, 0, 0, AD7791_CH_AIN1P_AIN1N, \ (bits), (storagebits), 0), \ - AD_SD_SHORTED_CHANNEL(1, 0, AD7791_CH_AIN1N_AIN1N, \ + AD7991_SHORTED_CHANNEL(1, 0, AD7791_CH_AIN1N_AIN1N, \ (bits), (storagebits), 0), \ - AD_SD_SUPPLY_CHANNEL(2, 1, AD7791_CH_AVDD_MONITOR, \ + AD7991_SUPPLY_CHANNEL(2, 1, AD7791_CH_AVDD_MONITOR, \ (bits), (storagebits), 0), \ IIO_CHAN_SOFT_TIMESTAMP(3), \ } @@ -444,5 +492,5 @@ static struct spi_driver ad7791_driver = { module_spi_driver(ad7791_driver); MODULE_AUTHOR("Lars-Peter Clausen "); -MODULE_DESCRIPTION("Analog Device AD7787/AD7788/AD7789/AD7790/AD7791 ADC driver"); +MODULE_DESCRIPTION("Analog Devices AD7787/AD7788/AD7789/AD7790/AD7791 ADC driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/iio/adc/ad7793.c b/drivers/iio/adc/ad7793.c index e5691e330323..808485f42415 100644 --- a/drivers/iio/adc/ad7793.c +++ b/drivers/iio/adc/ad7793.c @@ -354,29 +354,28 @@ static IIO_CONST_ATTR_SAMP_FREQ_AVAIL( static IIO_CONST_ATTR_NAMED(sampling_frequency_available_ad7797, sampling_frequency_available, "123 62 50 33 17 16 12 10 8 6 4"); -static ssize_t ad7793_show_scale_available(struct device *dev, - struct device_attribute *attr, char *buf) +static int ad7793_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, int *type, int *length, + long mask) { - struct iio_dev *indio_dev = dev_to_iio_dev(dev); struct ad7793_state *st = iio_priv(indio_dev); - int i, len = 0; - for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) - len += sprintf(buf + len, "%d.%09u ", st->scale_avail[i][0], - st->scale_avail[i][1]); + switch (mask) { + case IIO_CHAN_INFO_SCALE: + *vals = (int *)st->scale_avail; + *type = IIO_VAL_INT_PLUS_NANO; + /* Values are stored in a 2D matrix */ + *length = ARRAY_SIZE(st->scale_avail) * 2; - len += sprintf(buf + len, "\n"); - - return len; + return IIO_AVAIL_LIST; + default: + return -EINVAL; + } } -static IIO_DEVICE_ATTR_NAMED(in_m_in_scale_available, - in_voltage-voltage_scale_available, S_IRUGO, - ad7793_show_scale_available, NULL, 0); - static struct attribute *ad7793_attributes[] = { &iio_const_attr_sampling_frequency_available.dev_attr.attr, - &iio_dev_attr_in_m_in_scale_available.dev_attr.attr, NULL }; @@ -534,6 +533,7 @@ static const struct iio_info ad7793_info = { .read_raw = &ad7793_read_raw, .write_raw = &ad7793_write_raw, .write_raw_get_fmt = &ad7793_write_raw_get_fmt, + .read_avail = ad7793_read_avail, .attrs = &ad7793_attribute_group, .validate_trigger = ad_sd_validate_trigger, }; @@ -546,47 +546,113 @@ static const struct iio_info ad7797_info = { .validate_trigger = ad_sd_validate_trigger, }; +#define __AD7793_CHANNEL(_si, _channel1, _channel2, _address, _bits, \ + _storagebits, _shift, _extend_name, _type, _mask_type_av, _mask_all) \ + { \ + .type = (_type), \ + .differential = (_channel2 == -1 ? 0 : 1), \ + .indexed = 1, \ + .channel = (_channel1), \ + .channel2 = (_channel2), \ + .address = (_address), \ + .extend_name = (_extend_name), \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_OFFSET), \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ + .info_mask_shared_by_type_available = (_mask_type_av), \ + .info_mask_shared_by_all = _mask_all, \ + .scan_index = (_si), \ + .scan_type = { \ + .sign = 'u', \ + .realbits = (_bits), \ + .storagebits = (_storagebits), \ + .shift = (_shift), \ + .endianness = IIO_BE, \ + }, \ + } + +#define AD7793_DIFF_CHANNEL(_si, _channel1, _channel2, _address, _bits, \ + _storagebits, _shift) \ + __AD7793_CHANNEL(_si, _channel1, _channel2, _address, _bits, \ + _storagebits, _shift, NULL, IIO_VOLTAGE, \ + BIT(IIO_CHAN_INFO_SCALE), \ + BIT(IIO_CHAN_INFO_SAMP_FREQ)) + +#define AD7793_SHORTED_CHANNEL(_si, _channel, _address, _bits, \ + _storagebits, _shift) \ + __AD7793_CHANNEL(_si, _channel, _channel, _address, _bits, \ + _storagebits, _shift, "shorted", IIO_VOLTAGE, \ + BIT(IIO_CHAN_INFO_SCALE), \ + BIT(IIO_CHAN_INFO_SAMP_FREQ)) + +#define AD7793_TEMP_CHANNEL(_si, _address, _bits, _storagebits, _shift) \ + __AD7793_CHANNEL(_si, 0, -1, _address, _bits, \ + _storagebits, _shift, NULL, IIO_TEMP, \ + 0, \ + BIT(IIO_CHAN_INFO_SAMP_FREQ)) + +#define AD7793_SUPPLY_CHANNEL(_si, _channel, _address, _bits, _storagebits, \ + _shift) \ + __AD7793_CHANNEL(_si, _channel, -1, _address, _bits, \ + _storagebits, _shift, "supply", IIO_VOLTAGE, \ + 0, \ + BIT(IIO_CHAN_INFO_SAMP_FREQ)) + +#define AD7797_DIFF_CHANNEL(_si, _channel1, _channel2, _address, _bits, \ + _storagebits, _shift) \ + __AD7793_CHANNEL(_si, _channel1, _channel2, _address, _bits, \ + _storagebits, _shift, NULL, IIO_VOLTAGE, \ + 0, \ + BIT(IIO_CHAN_INFO_SAMP_FREQ)) + +#define AD7797_SHORTED_CHANNEL(_si, _channel, _address, _bits, \ + _storagebits, _shift) \ + __AD7793_CHANNEL(_si, _channel, _channel, _address, _bits, \ + _storagebits, _shift, "shorted", IIO_VOLTAGE, \ + 0, \ + BIT(IIO_CHAN_INFO_SAMP_FREQ)) + #define DECLARE_AD7793_CHANNELS(_name, _b, _sb, _s) \ const struct iio_chan_spec _name##_channels[] = { \ - AD_SD_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), (_s)), \ - AD_SD_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), (_s)), \ - AD_SD_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), (_s)), \ - AD_SD_SHORTED_CHANNEL(3, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), (_s)), \ - AD_SD_TEMP_CHANNEL(4, AD7793_CH_TEMP, (_b), (_sb), (_s)), \ - AD_SD_SUPPLY_CHANNEL(5, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), (_s)), \ + AD7793_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), (_s)), \ + AD7793_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), (_s)), \ + AD7793_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), (_s)), \ + AD7793_SHORTED_CHANNEL(3, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), (_s)), \ + AD7793_TEMP_CHANNEL(4, AD7793_CH_TEMP, (_b), (_sb), (_s)), \ + AD7793_SUPPLY_CHANNEL(5, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), (_s)), \ IIO_CHAN_SOFT_TIMESTAMP(6), \ } #define DECLARE_AD7795_CHANNELS(_name, _b, _sb) \ const struct iio_chan_spec _name##_channels[] = { \ - AD_SD_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \ - AD_SD_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), 0), \ - AD_SD_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), 0), \ - AD_SD_DIFF_CHANNEL(3, 3, 3, AD7795_CH_AIN4P_AIN4M, (_b), (_sb), 0), \ - AD_SD_DIFF_CHANNEL(4, 4, 4, AD7795_CH_AIN5P_AIN5M, (_b), (_sb), 0), \ - AD_SD_DIFF_CHANNEL(5, 5, 5, AD7795_CH_AIN6P_AIN6M, (_b), (_sb), 0), \ - AD_SD_SHORTED_CHANNEL(6, 0, AD7795_CH_AIN1M_AIN1M, (_b), (_sb), 0), \ - AD_SD_TEMP_CHANNEL(7, AD7793_CH_TEMP, (_b), (_sb), 0), \ - AD_SD_SUPPLY_CHANNEL(8, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \ + AD7793_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \ + AD7793_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), 0), \ + AD7793_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), 0), \ + AD7793_DIFF_CHANNEL(3, 3, 3, AD7795_CH_AIN4P_AIN4M, (_b), (_sb), 0), \ + AD7793_DIFF_CHANNEL(4, 4, 4, AD7795_CH_AIN5P_AIN5M, (_b), (_sb), 0), \ + AD7793_DIFF_CHANNEL(5, 5, 5, AD7795_CH_AIN6P_AIN6M, (_b), (_sb), 0), \ + AD7793_SHORTED_CHANNEL(6, 0, AD7795_CH_AIN1M_AIN1M, (_b), (_sb), 0), \ + AD7793_TEMP_CHANNEL(7, AD7793_CH_TEMP, (_b), (_sb), 0), \ + AD7793_SUPPLY_CHANNEL(8, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \ IIO_CHAN_SOFT_TIMESTAMP(9), \ } #define DECLARE_AD7797_CHANNELS(_name, _b, _sb) \ const struct iio_chan_spec _name##_channels[] = { \ - AD_SD_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \ - AD_SD_SHORTED_CHANNEL(1, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), 0), \ - AD_SD_TEMP_CHANNEL(2, AD7793_CH_TEMP, (_b), (_sb), 0), \ - AD_SD_SUPPLY_CHANNEL(3, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \ + AD7797_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \ + AD7797_SHORTED_CHANNEL(1, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), 0), \ + AD7793_TEMP_CHANNEL(2, AD7793_CH_TEMP, (_b), (_sb), 0), \ + AD7793_SUPPLY_CHANNEL(3, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \ IIO_CHAN_SOFT_TIMESTAMP(4), \ } #define DECLARE_AD7799_CHANNELS(_name, _b, _sb) \ const struct iio_chan_spec _name##_channels[] = { \ - AD_SD_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \ - AD_SD_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), 0), \ - AD_SD_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), 0), \ - AD_SD_SHORTED_CHANNEL(3, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), 0), \ - AD_SD_SUPPLY_CHANNEL(4, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \ + AD7793_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \ + AD7793_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), 0), \ + AD7793_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), 0), \ + AD7793_SHORTED_CHANNEL(3, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), 0), \ + AD7793_SUPPLY_CHANNEL(4, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \ IIO_CHAN_SOFT_TIMESTAMP(5), \ } diff --git a/drivers/iio/adc/ad9467.c b/drivers/iio/adc/ad9467.c new file mode 100644 index 000000000000..1e8fd83b9bc2 --- /dev/null +++ b/drivers/iio/adc/ad9467.c @@ -0,0 +1,422 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Analog Devices AD9467 SPI ADC driver + * + * Copyright 2012-2020 Analog Devices Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#include +#include + +#include + +#include + +/* + * ADI High-Speed ADC common spi interface registers + * See Application-Note AN-877: + * https://www.analog.com/media/en/technical-documentation/application-notes/AN-877.pdf + */ + +#define AN877_ADC_REG_CHIP_PORT_CONF 0x00 +#define AN877_ADC_REG_CHIP_ID 0x01 +#define AN877_ADC_REG_CHIP_GRADE 0x02 +#define AN877_ADC_REG_CHAN_INDEX 0x05 +#define AN877_ADC_REG_TRANSFER 0xFF +#define AN877_ADC_REG_MODES 0x08 +#define AN877_ADC_REG_TEST_IO 0x0D +#define AN877_ADC_REG_ADC_INPUT 0x0F +#define AN877_ADC_REG_OFFSET 0x10 +#define AN877_ADC_REG_OUTPUT_MODE 0x14 +#define AN877_ADC_REG_OUTPUT_ADJUST 0x15 +#define AN877_ADC_REG_OUTPUT_PHASE 0x16 +#define AN877_ADC_REG_OUTPUT_DELAY 0x17 +#define AN877_ADC_REG_VREF 0x18 +#define AN877_ADC_REG_ANALOG_INPUT 0x2C + +/* AN877_ADC_REG_TEST_IO */ +#define AN877_ADC_TESTMODE_OFF 0x0 +#define AN877_ADC_TESTMODE_MIDSCALE_SHORT 0x1 +#define AN877_ADC_TESTMODE_POS_FULLSCALE 0x2 +#define AN877_ADC_TESTMODE_NEG_FULLSCALE 0x3 +#define AN877_ADC_TESTMODE_ALT_CHECKERBOARD 0x4 +#define AN877_ADC_TESTMODE_PN23_SEQ 0x5 +#define AN877_ADC_TESTMODE_PN9_SEQ 0x6 +#define AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE 0x7 +#define AN877_ADC_TESTMODE_USER 0x8 +#define AN877_ADC_TESTMODE_BIT_TOGGLE 0x9 +#define AN877_ADC_TESTMODE_SYNC 0xA +#define AN877_ADC_TESTMODE_ONE_BIT_HIGH 0xB +#define AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY 0xC +#define AN877_ADC_TESTMODE_RAMP 0xF + +/* AN877_ADC_REG_TRANSFER */ +#define AN877_ADC_TRANSFER_SYNC 0x1 + +/* AN877_ADC_REG_OUTPUT_MODE */ +#define AN877_ADC_OUTPUT_MODE_OFFSET_BINARY 0x0 +#define AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT 0x1 +#define AN877_ADC_OUTPUT_MODE_GRAY_CODE 0x2 + +/* AN877_ADC_REG_OUTPUT_PHASE */ +#define AN877_ADC_OUTPUT_EVEN_ODD_MODE_EN 0x20 +#define AN877_ADC_INVERT_DCO_CLK 0x80 + +/* AN877_ADC_REG_OUTPUT_DELAY */ +#define AN877_ADC_DCO_DELAY_ENABLE 0x80 + +/* + * Analog Devices AD9467 16-Bit, 200/250 MSPS ADC + */ + +#define CHIPID_AD9467 0x50 +#define AD9467_DEF_OUTPUT_MODE 0x08 +#define AD9467_REG_VREF_MASK 0x0F + +enum { + ID_AD9467, +}; + +struct ad9467_state { + struct spi_device *spi; + struct clk *clk; + unsigned int output_mode; + + struct gpio_desc *pwrdown_gpio; + struct gpio_desc *reset_gpio; +}; + +static int ad9467_spi_read(struct spi_device *spi, unsigned int reg) +{ + unsigned char tbuf[2], rbuf[1]; + int ret; + + tbuf[0] = 0x80 | (reg >> 8); + tbuf[1] = reg & 0xFF; + + ret = spi_write_then_read(spi, + tbuf, ARRAY_SIZE(tbuf), + rbuf, ARRAY_SIZE(rbuf)); + + if (ret < 0) + return ret; + + return rbuf[0]; +} + +static int ad9467_spi_write(struct spi_device *spi, unsigned int reg, + unsigned int val) +{ + unsigned char buf[3]; + + buf[0] = reg >> 8; + buf[1] = reg & 0xFF; + buf[2] = val; + + return spi_write(spi, buf, ARRAY_SIZE(buf)); +} + +static int ad9467_reg_access(struct adi_axi_adc_conv *conv, unsigned int reg, + unsigned int writeval, unsigned int *readval) +{ + struct ad9467_state *st = adi_axi_adc_conv_priv(conv); + struct spi_device *spi = st->spi; + int ret; + + if (readval == NULL) { + ret = ad9467_spi_write(spi, reg, writeval); + ad9467_spi_write(spi, AN877_ADC_REG_TRANSFER, + AN877_ADC_TRANSFER_SYNC); + return ret; + } + + ret = ad9467_spi_read(spi, reg); + if (ret < 0) + return ret; + *readval = ret; + + return 0; +} + +static const unsigned int ad9467_scale_table[][2] = { + {2000, 0}, {2100, 6}, {2200, 7}, + {2300, 8}, {2400, 9}, {2500, 10}, +}; + +static void __ad9467_get_scale(struct adi_axi_adc_conv *conv, int index, + unsigned int *val, unsigned int *val2) +{ + const struct adi_axi_adc_chip_info *info = conv->chip_info; + const struct iio_chan_spec *chan = &info->channels[0]; + unsigned int tmp; + + tmp = (info->scale_table[index][0] * 1000000ULL) >> + chan->scan_type.realbits; + *val = tmp / 1000000; + *val2 = tmp % 1000000; +} + +#define AD9467_CHAN(_chan, _si, _bits, _sign) \ +{ \ + .type = IIO_VOLTAGE, \ + .indexed = 1, \ + .channel = _chan, \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .scan_index = _si, \ + .scan_type = { \ + .sign = _sign, \ + .realbits = _bits, \ + .storagebits = 16, \ + }, \ +} + +static const struct iio_chan_spec ad9467_channels[] = { + AD9467_CHAN(0, 0, 16, 'S'), +}; + +static const struct adi_axi_adc_chip_info ad9467_chip_tbl[] = { + [ID_AD9467] = { + .id = CHIPID_AD9467, + .max_rate = 250000000UL, + .scale_table = ad9467_scale_table, + .num_scales = ARRAY_SIZE(ad9467_scale_table), + .channels = ad9467_channels, + .num_channels = ARRAY_SIZE(ad9467_channels), + }, +}; + +static int ad9467_get_scale(struct adi_axi_adc_conv *conv, int *val, int *val2) +{ + const struct adi_axi_adc_chip_info *info = conv->chip_info; + struct ad9467_state *st = adi_axi_adc_conv_priv(conv); + unsigned int i, vref_val, vref_mask; + + vref_val = ad9467_spi_read(st->spi, AN877_ADC_REG_VREF); + + switch (info->id) { + case CHIPID_AD9467: + vref_mask = AD9467_REG_VREF_MASK; + break; + default: + vref_mask = 0xFFFF; + break; + } + + vref_val &= vref_mask; + + for (i = 0; i < info->num_scales; i++) { + if (vref_val == info->scale_table[i][1]) + break; + } + + if (i == info->num_scales) + return -ERANGE; + + __ad9467_get_scale(conv, i, val, val2); + + return IIO_VAL_INT_PLUS_MICRO; +} + +static int ad9467_set_scale(struct adi_axi_adc_conv *conv, int val, int val2) +{ + const struct adi_axi_adc_chip_info *info = conv->chip_info; + struct ad9467_state *st = adi_axi_adc_conv_priv(conv); + unsigned int scale_val[2]; + unsigned int i; + + if (val != 0) + return -EINVAL; + + for (i = 0; i < info->num_scales; i++) { + __ad9467_get_scale(conv, i, &scale_val[0], &scale_val[1]); + if (scale_val[0] != val || scale_val[1] != val2) + continue; + + ad9467_spi_write(st->spi, AN877_ADC_REG_VREF, + info->scale_table[i][1]); + ad9467_spi_write(st->spi, AN877_ADC_REG_TRANSFER, + AN877_ADC_TRANSFER_SYNC); + return 0; + } + + return -EINVAL; +} + +static int ad9467_read_raw(struct adi_axi_adc_conv *conv, + struct iio_chan_spec const *chan, + int *val, int *val2, long m) +{ + struct ad9467_state *st = adi_axi_adc_conv_priv(conv); + + switch (m) { + case IIO_CHAN_INFO_SCALE: + return ad9467_get_scale(conv, val, val2); + case IIO_CHAN_INFO_SAMP_FREQ: + *val = clk_get_rate(st->clk); + + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static int ad9467_write_raw(struct adi_axi_adc_conv *conv, + struct iio_chan_spec const *chan, + int val, int val2, long mask) +{ + const struct adi_axi_adc_chip_info *info = conv->chip_info; + struct ad9467_state *st = adi_axi_adc_conv_priv(conv); + long r_clk; + + switch (mask) { + case IIO_CHAN_INFO_SCALE: + return ad9467_set_scale(conv, val, val2); + case IIO_CHAN_INFO_SAMP_FREQ: + r_clk = clk_round_rate(st->clk, val); + if (r_clk < 0 || r_clk > info->max_rate) { + dev_warn(&st->spi->dev, + "Error setting ADC sample rate %ld", r_clk); + return -EINVAL; + } + + return clk_set_rate(st->clk, r_clk); + default: + return -EINVAL; + } +} + +static int ad9467_outputmode_set(struct spi_device *spi, unsigned int mode) +{ + int ret; + + ret = ad9467_spi_write(spi, AN877_ADC_REG_OUTPUT_MODE, mode); + if (ret < 0) + return ret; + + return ad9467_spi_write(spi, AN877_ADC_REG_TRANSFER, + AN877_ADC_TRANSFER_SYNC); +} + +static int ad9467_preenable_setup(struct adi_axi_adc_conv *conv) +{ + struct ad9467_state *st = adi_axi_adc_conv_priv(conv); + + return ad9467_outputmode_set(st->spi, st->output_mode); +} + +static int ad9467_setup(struct ad9467_state *st, unsigned int chip_id) +{ + switch (chip_id) { + case CHIPID_AD9467: + st->output_mode = AD9467_DEF_OUTPUT_MODE | + AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT; + return 0; + default: + return -EINVAL; + } +} + +static void ad9467_clk_disable(void *data) +{ + struct ad9467_state *st = data; + + clk_disable_unprepare(st->clk); +} + +static int ad9467_probe(struct spi_device *spi) +{ + const struct adi_axi_adc_chip_info *info; + struct adi_axi_adc_conv *conv; + struct ad9467_state *st; + unsigned int id; + int ret; + + info = of_device_get_match_data(&spi->dev); + if (!info) + return -ENODEV; + + conv = devm_adi_axi_adc_conv_register(&spi->dev, sizeof(*st)); + if (IS_ERR(conv)) + return PTR_ERR(conv); + + st = adi_axi_adc_conv_priv(conv); + st->spi = spi; + + st->clk = devm_clk_get(&spi->dev, "adc-clk"); + if (IS_ERR(st->clk)) + return PTR_ERR(st->clk); + + ret = clk_prepare_enable(st->clk); + if (ret < 0) + return ret; + + ret = devm_add_action_or_reset(&spi->dev, ad9467_clk_disable, st); + if (ret) + return ret; + + st->pwrdown_gpio = devm_gpiod_get_optional(&spi->dev, "powerdown", + GPIOD_OUT_LOW); + if (IS_ERR(st->pwrdown_gpio)) + return PTR_ERR(st->pwrdown_gpio); + + st->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset", + GPIOD_OUT_LOW); + if (IS_ERR(st->reset_gpio)) + return PTR_ERR(st->reset_gpio); + + if (st->reset_gpio) { + udelay(1); + ret = gpiod_direction_output(st->reset_gpio, 1); + if (ret) + return ret; + mdelay(10); + } + + spi_set_drvdata(spi, st); + + conv->chip_info = info; + + id = ad9467_spi_read(spi, AN877_ADC_REG_CHIP_ID); + if (id != conv->chip_info->id) { + dev_err(&spi->dev, "Unrecognized CHIP_ID 0x%X\n", id); + return -ENODEV; + } + + conv->reg_access = ad9467_reg_access; + conv->write_raw = ad9467_write_raw; + conv->read_raw = ad9467_read_raw; + conv->preenable_setup = ad9467_preenable_setup; + + return ad9467_setup(st, id); +} + +static const struct of_device_id ad9467_of_match[] = { + { .compatible = "adi,ad9467", .data = &ad9467_chip_tbl[ID_AD9467], }, + {} +}; +MODULE_DEVICE_TABLE(of, ad9467_of_match); + +static struct spi_driver ad9467_driver = { + .driver = { + .name = "ad9467", + .of_match_table = ad9467_of_match, + }, + .probe = ad9467_probe, +}; +module_spi_driver(ad9467_driver); + +MODULE_AUTHOR("Michael Hennerich "); +MODULE_DESCRIPTION("Analog Devices AD9467 ADC driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/iio/adc/ad_sigma_delta.c b/drivers/iio/adc/ad_sigma_delta.c index 8115b6de1d6c..dd3d54b3bc8b 100644 --- a/drivers/iio/adc/ad_sigma_delta.c +++ b/drivers/iio/adc/ad_sigma_delta.c @@ -70,9 +70,7 @@ int ad_sd_write_reg(struct ad_sigma_delta *sigma_delta, unsigned int reg, switch (size) { case 3: - data[1] = val >> 16; - data[2] = val >> 8; - data[3] = val; + put_unaligned_be24(val, &data[1]); break; case 2: put_unaligned_be16(val, &data[1]); @@ -157,9 +155,7 @@ int ad_sd_read_reg(struct ad_sigma_delta *sigma_delta, *val = get_unaligned_be32(sigma_delta->data); break; case 3: - *val = (sigma_delta->data[0] << 16) | - (sigma_delta->data[1] << 8) | - sigma_delta->data[2]; + *val = get_unaligned_be24(&sigma_delta->data[0]); break; case 2: *val = get_unaligned_be16(sigma_delta->data); diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c new file mode 100644 index 000000000000..c24c8da99eb4 --- /dev/null +++ b/drivers/iio/adc/adi-axi-adc.c @@ -0,0 +1,482 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Analog Devices Generic AXI ADC IP core + * Link: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip + * + * Copyright 2012-2020 Analog Devices Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +/** + * Register definitions: + * https://wiki.analog.com/resources/fpga/docs/axi_adc_ip#register_map + */ + +/* ADC controls */ + +#define ADI_AXI_REG_RSTN 0x0040 +#define ADI_AXI_REG_RSTN_CE_N BIT(2) +#define ADI_AXI_REG_RSTN_MMCM_RSTN BIT(1) +#define ADI_AXI_REG_RSTN_RSTN BIT(0) + +/* ADC Channel controls */ + +#define ADI_AXI_REG_CHAN_CTRL(c) (0x0400 + (c) * 0x40) +#define ADI_AXI_REG_CHAN_CTRL_LB_OWR BIT(11) +#define ADI_AXI_REG_CHAN_CTRL_PN_SEL_OWR BIT(10) +#define ADI_AXI_REG_CHAN_CTRL_IQCOR_EN BIT(9) +#define ADI_AXI_REG_CHAN_CTRL_DCFILT_EN BIT(8) +#define ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT BIT(6) +#define ADI_AXI_REG_CHAN_CTRL_FMT_TYPE BIT(5) +#define ADI_AXI_REG_CHAN_CTRL_FMT_EN BIT(4) +#define ADI_AXI_REG_CHAN_CTRL_PN_TYPE_OWR BIT(1) +#define ADI_AXI_REG_CHAN_CTRL_ENABLE BIT(0) + +#define ADI_AXI_REG_CHAN_CTRL_DEFAULTS \ + (ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT | \ + ADI_AXI_REG_CHAN_CTRL_FMT_EN | \ + ADI_AXI_REG_CHAN_CTRL_ENABLE) + +struct adi_axi_adc_core_info { + unsigned int version; +}; + +struct adi_axi_adc_state { + struct mutex lock; + + struct adi_axi_adc_client *client; + void __iomem *regs; +}; + +struct adi_axi_adc_client { + struct list_head entry; + struct adi_axi_adc_conv conv; + struct adi_axi_adc_state *state; + struct device *dev; + const struct adi_axi_adc_core_info *info; +}; + +static LIST_HEAD(registered_clients); +static DEFINE_MUTEX(registered_clients_lock); + +static struct adi_axi_adc_client *conv_to_client(struct adi_axi_adc_conv *conv) +{ + return container_of(conv, struct adi_axi_adc_client, conv); +} + +void *adi_axi_adc_conv_priv(struct adi_axi_adc_conv *conv) +{ + struct adi_axi_adc_client *cl = conv_to_client(conv); + + return (char *)cl + ALIGN(sizeof(struct adi_axi_adc_client), IIO_ALIGN); +} +EXPORT_SYMBOL_GPL(adi_axi_adc_conv_priv); + +static void adi_axi_adc_write(struct adi_axi_adc_state *st, + unsigned int reg, + unsigned int val) +{ + iowrite32(val, st->regs + reg); +} + +static unsigned int adi_axi_adc_read(struct adi_axi_adc_state *st, + unsigned int reg) +{ + return ioread32(st->regs + reg); +} + +static int adi_axi_adc_config_dma_buffer(struct device *dev, + struct iio_dev *indio_dev) +{ + struct iio_buffer *buffer; + const char *dma_name; + + if (!device_property_present(dev, "dmas")) + return 0; + + if (device_property_read_string(dev, "dma-names", &dma_name)) + dma_name = "rx"; + + buffer = devm_iio_dmaengine_buffer_alloc(indio_dev->dev.parent, + dma_name); + if (IS_ERR(buffer)) + return PTR_ERR(buffer); + + indio_dev->modes |= INDIO_BUFFER_HARDWARE; + iio_device_attach_buffer(indio_dev, buffer); + + return 0; +} + +static int adi_axi_adc_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct adi_axi_adc_state *st = iio_priv(indio_dev); + struct adi_axi_adc_conv *conv = &st->client->conv; + + if (!conv->read_raw) + return -EOPNOTSUPP; + + return conv->read_raw(conv, chan, val, val2, mask); +} + +static int adi_axi_adc_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long mask) +{ + struct adi_axi_adc_state *st = iio_priv(indio_dev); + struct adi_axi_adc_conv *conv = &st->client->conv; + + if (!conv->write_raw) + return -EOPNOTSUPP; + + return conv->write_raw(conv, chan, val, val2, mask); +} + +static int adi_axi_adc_update_scan_mode(struct iio_dev *indio_dev, + const unsigned long *scan_mask) +{ + struct adi_axi_adc_state *st = iio_priv(indio_dev); + struct adi_axi_adc_conv *conv = &st->client->conv; + unsigned int i, ctrl; + + for (i = 0; i < conv->chip_info->num_channels; i++) { + ctrl = adi_axi_adc_read(st, ADI_AXI_REG_CHAN_CTRL(i)); + + if (test_bit(i, scan_mask)) + ctrl |= ADI_AXI_REG_CHAN_CTRL_ENABLE; + else + ctrl &= ~ADI_AXI_REG_CHAN_CTRL_ENABLE; + + adi_axi_adc_write(st, ADI_AXI_REG_CHAN_CTRL(i), ctrl); + } + + return 0; +} + +static struct adi_axi_adc_conv *adi_axi_adc_conv_register(struct device *dev, + size_t sizeof_priv) +{ + struct adi_axi_adc_client *cl; + size_t alloc_size; + + alloc_size = ALIGN(sizeof(struct adi_axi_adc_client), IIO_ALIGN); + if (sizeof_priv) + alloc_size += ALIGN(sizeof_priv, IIO_ALIGN); + + cl = kzalloc(alloc_size, GFP_KERNEL); + if (!cl) + return ERR_PTR(-ENOMEM); + + mutex_lock(®istered_clients_lock); + + cl->dev = get_device(dev); + + list_add_tail(&cl->entry, ®istered_clients); + + mutex_unlock(®istered_clients_lock); + + return &cl->conv; +} + +static void adi_axi_adc_conv_unregister(struct adi_axi_adc_conv *conv) +{ + struct adi_axi_adc_client *cl = conv_to_client(conv); + + mutex_lock(®istered_clients_lock); + + list_del(&cl->entry); + put_device(cl->dev); + + mutex_unlock(®istered_clients_lock); + + kfree(cl); +} + +static void devm_adi_axi_adc_conv_release(struct device *dev, void *res) +{ + adi_axi_adc_conv_unregister(*(struct adi_axi_adc_conv **)res); +} + +struct adi_axi_adc_conv *devm_adi_axi_adc_conv_register(struct device *dev, + size_t sizeof_priv) +{ + struct adi_axi_adc_conv **ptr, *conv; + + ptr = devres_alloc(devm_adi_axi_adc_conv_release, sizeof(*ptr), + GFP_KERNEL); + if (!ptr) + return ERR_PTR(-ENOMEM); + + conv = adi_axi_adc_conv_register(dev, sizeof_priv); + if (IS_ERR(conv)) { + devres_free(ptr); + return ERR_CAST(conv); + } + + *ptr = conv; + devres_add(dev, ptr); + + return conv; +} +EXPORT_SYMBOL_GPL(devm_adi_axi_adc_conv_register); + +static ssize_t in_voltage_scale_available_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev = dev_to_iio_dev(dev); + struct adi_axi_adc_state *st = iio_priv(indio_dev); + struct adi_axi_adc_conv *conv = &st->client->conv; + size_t len = 0; + int i; + + for (i = 0; i < conv->chip_info->num_scales; i++) { + const unsigned int *s = conv->chip_info->scale_table[i]; + + len += scnprintf(buf + len, PAGE_SIZE - len, + "%u.%06u ", s[0], s[1]); + } + buf[len - 1] = '\n'; + + return len; +} + +static IIO_DEVICE_ATTR_RO(in_voltage_scale_available, 0); + +enum { + ADI_AXI_ATTR_SCALE_AVAIL, +}; + +#define ADI_AXI_ATTR(_en_, _file_) \ + [ADI_AXI_ATTR_##_en_] = &iio_dev_attr_##_file_.dev_attr.attr + +static struct attribute *adi_axi_adc_attributes[] = { + ADI_AXI_ATTR(SCALE_AVAIL, in_voltage_scale_available), + NULL +}; + +static umode_t axi_adc_attr_is_visible(struct kobject *kobj, + struct attribute *attr, int n) +{ + struct device *dev = container_of(kobj, struct device, kobj); + struct iio_dev *indio_dev = dev_to_iio_dev(dev); + struct adi_axi_adc_state *st = iio_priv(indio_dev); + struct adi_axi_adc_conv *conv = &st->client->conv; + + switch (n) { + case ADI_AXI_ATTR_SCALE_AVAIL: + if (!conv->chip_info->num_scales) + return 0; + return attr->mode; + default: + return attr->mode; + } +} + +static const struct attribute_group adi_axi_adc_attribute_group = { + .attrs = adi_axi_adc_attributes, + .is_visible = axi_adc_attr_is_visible, +}; + +static const struct iio_info adi_axi_adc_info = { + .read_raw = &adi_axi_adc_read_raw, + .write_raw = &adi_axi_adc_write_raw, + .attrs = &adi_axi_adc_attribute_group, + .update_scan_mode = &adi_axi_adc_update_scan_mode, +}; + +static const struct adi_axi_adc_core_info adi_axi_adc_10_0_a_info = { + .version = ADI_AXI_PCORE_VER(10, 0, 'a'), +}; + +static struct adi_axi_adc_client *adi_axi_adc_attach_client(struct device *dev) +{ + const struct adi_axi_adc_core_info *info; + struct adi_axi_adc_client *cl; + struct device_node *cln; + + info = of_device_get_match_data(dev); + if (!info) + return ERR_PTR(-ENODEV); + + cln = of_parse_phandle(dev->of_node, "adi,adc-dev", 0); + if (!cln) { + dev_err(dev, "No 'adi,adc-dev' node defined\n"); + return ERR_PTR(-ENODEV); + } + + mutex_lock(®istered_clients_lock); + + list_for_each_entry(cl, ®istered_clients, entry) { + if (!cl->dev) + continue; + + if (cl->dev->of_node != cln) + continue; + + if (!try_module_get(dev->driver->owner)) { + mutex_unlock(®istered_clients_lock); + return ERR_PTR(-ENODEV); + } + + get_device(dev); + cl->info = info; + mutex_unlock(®istered_clients_lock); + return cl; + } + + mutex_unlock(®istered_clients_lock); + + return ERR_PTR(-EPROBE_DEFER); +} + +static int adi_axi_adc_setup_channels(struct device *dev, + struct adi_axi_adc_state *st) +{ + struct adi_axi_adc_conv *conv = &st->client->conv; + int i, ret; + + if (conv->preenable_setup) { + ret = conv->preenable_setup(conv); + if (ret) + return ret; + } + + for (i = 0; i < conv->chip_info->num_channels; i++) { + adi_axi_adc_write(st, ADI_AXI_REG_CHAN_CTRL(i), + ADI_AXI_REG_CHAN_CTRL_DEFAULTS); + } + + return 0; +} + +static void axi_adc_reset(struct adi_axi_adc_state *st) +{ + adi_axi_adc_write(st, ADI_AXI_REG_RSTN, 0); + mdelay(10); + adi_axi_adc_write(st, ADI_AXI_REG_RSTN, ADI_AXI_REG_RSTN_MMCM_RSTN); + mdelay(10); + adi_axi_adc_write(st, ADI_AXI_REG_RSTN, + ADI_AXI_REG_RSTN_RSTN | ADI_AXI_REG_RSTN_MMCM_RSTN); +} + +static void adi_axi_adc_cleanup(void *data) +{ + struct adi_axi_adc_client *cl = data; + + put_device(cl->dev); + module_put(cl->dev->driver->owner); +} + +static int adi_axi_adc_probe(struct platform_device *pdev) +{ + struct adi_axi_adc_conv *conv; + struct iio_dev *indio_dev; + struct adi_axi_adc_client *cl; + struct adi_axi_adc_state *st; + unsigned int ver; + int ret; + + cl = adi_axi_adc_attach_client(&pdev->dev); + if (IS_ERR(cl)) + return PTR_ERR(cl); + + ret = devm_add_action_or_reset(&pdev->dev, adi_axi_adc_cleanup, cl); + if (ret) + return ret; + + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st)); + if (indio_dev == NULL) + return -ENOMEM; + + st = iio_priv(indio_dev); + st->client = cl; + cl->state = st; + mutex_init(&st->lock); + + st->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(st->regs)) + return PTR_ERR(st->regs); + + conv = &st->client->conv; + + axi_adc_reset(st); + + ver = adi_axi_adc_read(st, ADI_AXI_REG_VERSION); + + if (cl->info->version > ver) { + dev_err(&pdev->dev, + "IP core version is too old. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n", + ADI_AXI_PCORE_VER_MAJOR(cl->info->version), + ADI_AXI_PCORE_VER_MINOR(cl->info->version), + ADI_AXI_PCORE_VER_PATCH(cl->info->version), + ADI_AXI_PCORE_VER_MAJOR(ver), + ADI_AXI_PCORE_VER_MINOR(ver), + ADI_AXI_PCORE_VER_PATCH(ver)); + return -ENODEV; + } + + indio_dev->info = &adi_axi_adc_info; + indio_dev->dev.parent = &pdev->dev; + indio_dev->name = "adi-axi-adc"; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->num_channels = conv->chip_info->num_channels; + indio_dev->channels = conv->chip_info->channels; + + ret = adi_axi_adc_config_dma_buffer(&pdev->dev, indio_dev); + if (ret) + return ret; + + ret = adi_axi_adc_setup_channels(&pdev->dev, st); + if (ret) + return ret; + + ret = devm_iio_device_register(&pdev->dev, indio_dev); + if (ret) + return ret; + + dev_info(&pdev->dev, "AXI ADC IP core (%d.%.2d.%c) probed\n", + ADI_AXI_PCORE_VER_MAJOR(ver), + ADI_AXI_PCORE_VER_MINOR(ver), + ADI_AXI_PCORE_VER_PATCH(ver)); + + return 0; +} + +/* Match table for of_platform binding */ +static const struct of_device_id adi_axi_adc_of_match[] = { + { .compatible = "adi,axi-adc-10.0.a", .data = &adi_axi_adc_10_0_a_info }, + { /* end of list */ } +}; +MODULE_DEVICE_TABLE(of, adi_axi_adc_of_match); + +static struct platform_driver adi_axi_adc_driver = { + .driver = { + .name = KBUILD_MODNAME, + .of_match_table = adi_axi_adc_of_match, + }, + .probe = adi_axi_adc_probe, +}; +module_platform_driver(adi_axi_adc_driver); + +MODULE_AUTHOR("Michael Hennerich "); +MODULE_DESCRIPTION("Analog Devices Generic AXI ADC IP core driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index 9d96f7d08b95..9abbbdcc7420 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -100,6 +101,8 @@ #define AT91_SAMA5D2_IER_YRDY BIT(21) /* Interrupt Enable Register - TS pressure measurement ready */ #define AT91_SAMA5D2_IER_PRDY BIT(22) +/* Interrupt Enable Register - Data ready */ +#define AT91_SAMA5D2_IER_DRDY BIT(24) /* Interrupt Enable Register - general overrun error */ #define AT91_SAMA5D2_IER_GOVRE BIT(25) /* Interrupt Enable Register - Pen detect */ @@ -486,6 +489,21 @@ static inline int at91_adc_of_xlate(struct iio_dev *indio_dev, return at91_adc_chan_xlate(indio_dev, iiospec->args[0]); } +static unsigned int at91_adc_active_scan_mask_to_reg(struct iio_dev *indio_dev) +{ + u32 mask = 0; + u8 bit; + + for_each_set_bit(bit, indio_dev->active_scan_mask, + indio_dev->num_channels) { + struct iio_chan_spec const *chan = + at91_adc_chan_get(indio_dev, bit); + mask |= BIT(chan->channel); + } + + return mask & GENMASK(11, 0); +} + static void at91_adc_config_emr(struct at91_adc_state *st) { /* configure the extended mode register */ @@ -710,7 +728,6 @@ static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) struct iio_dev *indio = iio_trigger_get_drvdata(trig); struct at91_adc_state *st = iio_priv(indio); u32 status = at91_adc_readl(st, AT91_SAMA5D2_TRGR); - u8 bit; /* clear TRGMOD */ status &= ~AT91_SAMA5D2_TRGR_TRGMOD_MASK; @@ -721,50 +738,6 @@ static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) /* set/unset hw trigger */ at91_adc_writel(st, AT91_SAMA5D2_TRGR, status); - for_each_set_bit(bit, indio->active_scan_mask, indio->num_channels) { - struct iio_chan_spec const *chan = at91_adc_chan_get(indio, bit); - u32 cor; - - if (!chan) - continue; - /* these channel types cannot be handled by this trigger */ - if (chan->type == IIO_POSITIONRELATIVE || - chan->type == IIO_PRESSURE) - continue; - - if (state) { - cor = at91_adc_readl(st, AT91_SAMA5D2_COR); - - if (chan->differential) - cor |= (BIT(chan->channel) | - BIT(chan->channel2)) << - AT91_SAMA5D2_COR_DIFF_OFFSET; - else - cor &= ~(BIT(chan->channel) << - AT91_SAMA5D2_COR_DIFF_OFFSET); - - at91_adc_writel(st, AT91_SAMA5D2_COR, cor); - } - - if (state) { - at91_adc_writel(st, AT91_SAMA5D2_CHER, - BIT(chan->channel)); - /* enable irq only if not using DMA */ - if (!st->dma_st.dma_chan) { - at91_adc_writel(st, AT91_SAMA5D2_IER, - BIT(chan->channel)); - } - } else { - /* disable irq only if not using DMA */ - if (!st->dma_st.dma_chan) { - at91_adc_writel(st, AT91_SAMA5D2_IDR, - BIT(chan->channel)); - } - at91_adc_writel(st, AT91_SAMA5D2_CHDR, - BIT(chan->channel)); - } - } - return 0; } @@ -781,6 +754,7 @@ static int at91_adc_reenable_trigger(struct iio_trigger *trig) /* Needed to ACK the DRDY interruption */ at91_adc_readl(st, AT91_SAMA5D2_LCDR); + return 0; } @@ -888,18 +862,37 @@ static int at91_adc_dma_start(struct iio_dev *indio_dev) return 0; } -static int at91_adc_buffer_postenable(struct iio_dev *indio_dev) +static bool at91_adc_buffer_check_use_irq(struct iio_dev *indio, + struct at91_adc_state *st) +{ + /* if using DMA, we do not use our own IRQ (we use DMA-controller) */ + if (st->dma_st.dma_chan) + return false; + /* if the trigger is not ours, then it has its own IRQ */ + if (iio_trigger_validate_own_device(indio->trig, indio)) + return false; + return true; +} + +static bool at91_adc_current_chan_is_touch(struct iio_dev *indio_dev) +{ + struct at91_adc_state *st = iio_priv(indio_dev); + + return !!bitmap_subset(indio_dev->active_scan_mask, + &st->touch_st.channels_bitmask, + AT91_SAMA5D2_MAX_CHAN_IDX + 1); +} + +static int at91_adc_buffer_preenable(struct iio_dev *indio_dev) { int ret; + u8 bit; struct at91_adc_state *st = iio_priv(indio_dev); /* check if we are enabling triggered buffer or the touchscreen */ - if (bitmap_subset(indio_dev->active_scan_mask, - &st->touch_st.channels_bitmask, - AT91_SAMA5D2_MAX_CHAN_IDX + 1)) { - /* touchscreen enabling */ + if (at91_adc_current_chan_is_touch(indio_dev)) return at91_adc_configure_touch(st, true); - } + /* if we are not in triggered mode, we cannot enable the buffer. */ if (!(indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES)) return -EINVAL; @@ -911,41 +904,65 @@ static int at91_adc_buffer_postenable(struct iio_dev *indio_dev) return ret; } + for_each_set_bit(bit, indio_dev->active_scan_mask, + indio_dev->num_channels) { + struct iio_chan_spec const *chan = + at91_adc_chan_get(indio_dev, bit); + u32 cor; + + if (!chan) + continue; + /* these channel types cannot be handled by this trigger */ + if (chan->type == IIO_POSITIONRELATIVE || + chan->type == IIO_PRESSURE) + continue; + + cor = at91_adc_readl(st, AT91_SAMA5D2_COR); + + if (chan->differential) + cor |= (BIT(chan->channel) | BIT(chan->channel2)) << + AT91_SAMA5D2_COR_DIFF_OFFSET; + else + cor &= ~(BIT(chan->channel) << + AT91_SAMA5D2_COR_DIFF_OFFSET); + + at91_adc_writel(st, AT91_SAMA5D2_COR, cor); + + at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel)); + } + + if (at91_adc_buffer_check_use_irq(indio_dev, st)) + at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_DRDY); + + return 0; +} + +static int at91_adc_buffer_postenable(struct iio_dev *indio_dev) +{ + if (at91_adc_current_chan_is_touch(indio_dev)) + return 0; + return iio_triggered_buffer_postenable(indio_dev); } -static int at91_adc_buffer_predisable(struct iio_dev *indio_dev) +static int at91_adc_buffer_postdisable(struct iio_dev *indio_dev) { struct at91_adc_state *st = iio_priv(indio_dev); - int ret; u8 bit; /* check if we are disabling triggered buffer or the touchscreen */ - if (bitmap_subset(indio_dev->active_scan_mask, - &st->touch_st.channels_bitmask, - AT91_SAMA5D2_MAX_CHAN_IDX + 1)) { - /* touchscreen disable */ + if (at91_adc_current_chan_is_touch(indio_dev)) return at91_adc_configure_touch(st, false); - } + /* if we are not in triggered mode, nothing to do here */ if (!(indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES)) return -EINVAL; - /* continue with the triggered buffer */ - ret = iio_triggered_buffer_predisable(indio_dev); - if (ret < 0) - dev_err(&indio_dev->dev, "buffer predisable failed\n"); - - if (!st->dma_st.dma_chan) - return ret; - - /* if we are using DMA we must clear registers and end DMA */ - dmaengine_terminate_sync(st->dma_st.dma_chan); - /* - * For each enabled channel we must read the last converted value + * For each enable channel we must disable it in hardware. + * In the case of DMA, we must read the last converted value * to clear EOC status and not get a possible interrupt later. - * This value is being read by DMA from LCDR anyway + * This value is being read by DMA from LCDR anyway, so it's not lost. */ for_each_set_bit(bit, indio_dev->active_scan_mask, indio_dev->num_channels) { @@ -958,16 +975,37 @@ static int at91_adc_buffer_predisable(struct iio_dev *indio_dev) if (chan->type == IIO_POSITIONRELATIVE || chan->type == IIO_PRESSURE) continue; + + at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel)); + if (st->dma_st.dma_chan) at91_adc_readl(st, chan->address); } + if (at91_adc_buffer_check_use_irq(indio_dev, st)) + at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_DRDY); + /* read overflow register to clear possible overflow status */ at91_adc_readl(st, AT91_SAMA5D2_OVER); - return ret; + + /* if we are using DMA we must clear registers and end DMA */ + if (st->dma_st.dma_chan) + dmaengine_terminate_sync(st->dma_st.dma_chan); + + return 0; +} + +static int at91_adc_buffer_predisable(struct iio_dev *indio_dev) +{ + if (at91_adc_current_chan_is_touch(indio_dev)) + return 0; + + return iio_triggered_buffer_predisable(indio_dev); } static const struct iio_buffer_setup_ops at91_buffer_setup_ops = { + .preenable = &at91_adc_buffer_preenable, + .postdisable = &at91_adc_buffer_postdisable, .postenable = &at91_adc_buffer_postenable, .predisable = &at91_adc_buffer_predisable, }; @@ -1015,6 +1053,22 @@ static void at91_adc_trigger_handler_nodma(struct iio_dev *indio_dev, int i = 0; int val; u8 bit; + u32 mask = at91_adc_active_scan_mask_to_reg(indio_dev); + unsigned int timeout = 50; + + /* + * Check if the conversion is ready. If not, wait a little bit, and + * in case of timeout exit with an error. + */ + while ((at91_adc_readl(st, AT91_SAMA5D2_ISR) & mask) != mask && + timeout) { + usleep_range(50, 100); + timeout--; + } + + /* Cannot read data, not ready. Continue without reporting data */ + if (!timeout) + return; for_each_set_bit(bit, indio_dev->active_scan_mask, indio_dev->num_channels) { @@ -1102,6 +1156,13 @@ static irqreturn_t at91_adc_trigger_handler(int irq, void *p) struct iio_dev *indio_dev = pf->indio_dev; struct at91_adc_state *st = iio_priv(indio_dev); + /* + * If it's not our trigger, start a conversion now, as we are + * actually polling the trigger now. + */ + if (iio_trigger_validate_own_device(indio_dev->trig, indio_dev)) + at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_START); + if (st->dma_st.dma_chan) at91_adc_trigger_handler_dma(indio_dev); else @@ -1114,20 +1175,9 @@ static irqreturn_t at91_adc_trigger_handler(int irq, void *p) static int at91_adc_buffer_init(struct iio_dev *indio) { - struct at91_adc_state *st = iio_priv(indio); - - if (st->selected_trig->hw_trig) { - return devm_iio_triggered_buffer_setup(&indio->dev, indio, - &iio_pollfunc_store_time, - &at91_adc_trigger_handler, &at91_buffer_setup_ops); - } - /* - * we need to prepare the buffer ops in case we will get - * another buffer attached (like a callback buffer for the touchscreen) - */ - indio->setup_ops = &at91_buffer_setup_ops; - - return 0; + return devm_iio_triggered_buffer_setup(&indio->dev, indio, + &iio_pollfunc_store_time, + &at91_adc_trigger_handler, &at91_buffer_setup_ops); } static unsigned at91_adc_startup_time(unsigned startup_time_min, @@ -1281,7 +1331,8 @@ static irqreturn_t at91_adc_interrupt(int irq, void *private) status = at91_adc_readl(st, AT91_SAMA5D2_XPOSR); status = at91_adc_readl(st, AT91_SAMA5D2_YPOSR); status = at91_adc_readl(st, AT91_SAMA5D2_PRESSR); - } else if (iio_buffer_enabled(indio) && !st->dma_st.dma_chan) { + } else if (iio_buffer_enabled(indio) && + (status & AT91_SAMA5D2_IER_DRDY)) { /* triggered buffer without DMA */ disable_irq_nosync(irq); iio_trigger_poll(indio->trig); @@ -1901,14 +1952,10 @@ static __maybe_unused int at91_adc_resume(struct device *dev) return 0; /* check if we are enabling triggered buffer or the touchscreen */ - if (bitmap_subset(indio_dev->active_scan_mask, - &st->touch_st.channels_bitmask, - AT91_SAMA5D2_MAX_CHAN_IDX + 1)) { - /* touchscreen enabling */ + if (at91_adc_current_chan_is_touch(indio_dev)) return at91_adc_configure_touch(st, true); - } else { + else return at91_adc_configure_trigger(st->trig, true); - } /* not needed but more explicit */ return 0; diff --git a/drivers/iio/adc/at91_adc.c b/drivers/iio/adc/at91_adc.c index abe99856c823..0368b6dc6d60 100644 --- a/drivers/iio/adc/at91_adc.c +++ b/drivers/iio/adc/at91_adc.c @@ -1152,7 +1152,6 @@ static int at91_adc_probe(struct platform_device *pdev) int ret; struct iio_dev *idev; struct at91_adc_state *st; - struct resource *res; u32 reg; idev = devm_iio_device_alloc(&pdev->dev, sizeof(struct at91_adc_state)); @@ -1182,9 +1181,7 @@ static int at91_adc_probe(struct platform_device *pdev) if (st->irq < 0) return -ENODEV; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - - st->reg_base = devm_ioremap_resource(&pdev->dev, res); + st->reg_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(st->reg_base)) return PTR_ERR(st->reg_base); diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c index 22131a677445..6bda4f4d89fe 100644 --- a/drivers/iio/adc/exynos_adc.c +++ b/drivers/iio/adc/exynos_adc.c @@ -449,9 +449,6 @@ static void exynos_adc_exynos7_init_hw(struct exynos_adc *info) { u32 con1, con2; - if (info->data->needs_adc_phy) - regmap_write(info->pmu_map, info->data->phy_offset, 1); - con1 = ADC_V2_CON1_SOFT_RESET; writel(con1, ADC_V2_CON1(info->regs)); @@ -531,8 +528,19 @@ static int exynos_read_raw(struct iio_dev *indio_dev, unsigned long timeout; int ret; - if (mask != IIO_CHAN_INFO_RAW) + if (mask == IIO_CHAN_INFO_SCALE) { + ret = regulator_get_voltage(info->vdd); + if (ret < 0) + return ret; + + /* Regulator voltage is in uV, but need mV */ + *val = ret / 1000; + *val2 = info->data->mask; + + return IIO_VAL_FRACTIONAL; + } else if (mask != IIO_CHAN_INFO_RAW) { return -EINVAL; + } mutex_lock(&indio_dev->mlock); reinit_completion(&info->completion); @@ -683,6 +691,7 @@ static const struct iio_info exynos_adc_iio_info = { .channel = _index, \ .address = _index, \ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE), \ .datasheet_name = _id, \ } diff --git a/drivers/iio/adc/fsl-imx25-gcq.c b/drivers/iio/adc/fsl-imx25-gcq.c index fa71489195c6..b0a4dc88ba9b 100644 --- a/drivers/iio/adc/fsl-imx25-gcq.c +++ b/drivers/iio/adc/fsl-imx25-gcq.c @@ -294,7 +294,6 @@ static int mx25_gcq_probe(struct platform_device *pdev) struct mx25_gcq_priv *priv; struct mx25_tsadc *tsadc = dev_get_drvdata(pdev->dev.parent); struct device *dev = &pdev->dev; - struct resource *res; void __iomem *mem; int ret; int i; @@ -305,8 +304,7 @@ static int mx25_gcq_probe(struct platform_device *pdev) priv = iio_priv(indio_dev); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - mem = devm_ioremap_resource(dev, res); + mem = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(mem)) return PTR_ERR(mem); diff --git a/drivers/iio/adc/intel_mrfld_adc.c b/drivers/iio/adc/intel_mrfld_adc.c index c35a1beb817c..a6d2e1f27e76 100644 --- a/drivers/iio/adc/intel_mrfld_adc.c +++ b/drivers/iio/adc/intel_mrfld_adc.c @@ -75,7 +75,7 @@ static int mrfld_adc_single_conv(struct iio_dev *indio_dev, struct regmap *regmap = adc->regmap; unsigned int req; long timeout; - u8 buf[2]; + __be16 value; int ret; reinit_completion(&adc->completion); @@ -105,11 +105,11 @@ static int mrfld_adc_single_conv(struct iio_dev *indio_dev, goto done; } - ret = regmap_bulk_read(regmap, chan->address, buf, 2); + ret = regmap_bulk_read(regmap, chan->address, &value, sizeof(value)); if (ret) goto done; - *result = get_unaligned_be16(buf); + *result = be16_to_cpu(value); ret = IIO_VAL_INT; done: diff --git a/drivers/iio/adc/max1241.c b/drivers/iio/adc/max1241.c new file mode 100644 index 000000000000..541939c7abca --- /dev/null +++ b/drivers/iio/adc/max1241.c @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * MAX1241 low-power, 12-bit serial ADC + * + * Datasheet: https://datasheets.maximintegrated.com/en/ds/MAX1240-MAX1241.pdf + */ + +#include +#include +#include +#include +#include +#include + +#define MAX1241_VAL_MASK GENMASK(11, 0) +#define MAX1241_SHUTDOWN_DELAY_USEC 4 + +enum max1241_id { + max1241, +}; + +struct max1241 { + struct spi_device *spi; + struct mutex lock; + struct regulator *vdd; + struct regulator *vref; + struct gpio_desc *shutdown; + + __be16 data ____cacheline_aligned; +}; + +static const struct iio_chan_spec max1241_channels[] = { + { + .type = IIO_VOLTAGE, + .indexed = 1, + .channel = 0, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + }, +}; + +static int max1241_read(struct max1241 *adc) +{ + struct spi_transfer xfers[] = { + /* + * Begin conversion by bringing /CS low for at least + * tconv us. + */ + { + .len = 0, + .delay.value = 8, + .delay.unit = SPI_DELAY_UNIT_USECS, + }, + /* + * Then read two bytes of data in our RX buffer. + */ + { + .rx_buf = &adc->data, + .len = 2, + }, + }; + + return spi_sync_transfer(adc->spi, xfers, ARRAY_SIZE(xfers)); +} + +static int max1241_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + int ret, vref_uV; + struct max1241 *adc = iio_priv(indio_dev); + + switch (mask) { + case IIO_CHAN_INFO_RAW: + mutex_lock(&adc->lock); + + if (adc->shutdown) { + gpiod_set_value(adc->shutdown, 0); + udelay(MAX1241_SHUTDOWN_DELAY_USEC); + ret = max1241_read(adc); + gpiod_set_value(adc->shutdown, 1); + } else + ret = max1241_read(adc); + + if (ret) { + mutex_unlock(&adc->lock); + return ret; + } + + *val = (be16_to_cpu(adc->data) >> 3) & MAX1241_VAL_MASK; + + mutex_unlock(&adc->lock); + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + vref_uV = regulator_get_voltage(adc->vref); + + if (vref_uV < 0) + return vref_uV; + + *val = vref_uV / 1000; + *val2 = 12; + + return IIO_VAL_FRACTIONAL_LOG2; + default: + return -EINVAL; + } +} + +static const struct iio_info max1241_info = { + .read_raw = max1241_read_raw, +}; + +static void max1241_disable_vdd_action(void *data) +{ + struct max1241 *adc = data; + struct device *dev = &adc->spi->dev; + int err; + + err = regulator_disable(adc->vdd); + if (err) + dev_err(dev, "could not disable vdd regulator.\n"); +} + +static void max1241_disable_vref_action(void *data) +{ + struct max1241 *adc = data; + struct device *dev = &adc->spi->dev; + int err; + + err = regulator_disable(adc->vref); + if (err) + dev_err(dev, "could not disable vref regulator.\n"); +} + +static int max1241_probe(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + struct iio_dev *indio_dev; + struct max1241 *adc; + int ret; + + indio_dev = devm_iio_device_alloc(dev, sizeof(*adc)); + if (!indio_dev) + return -ENOMEM; + + adc = iio_priv(indio_dev); + adc->spi = spi; + mutex_init(&adc->lock); + + spi_set_drvdata(spi, indio_dev); + + adc->vdd = devm_regulator_get(dev, "vdd"); + if (IS_ERR(adc->vdd)) { + dev_err(dev, "failed to get vdd regulator\n"); + return PTR_ERR(adc->vdd); + } + + ret = regulator_enable(adc->vdd); + if (ret) + return ret; + + ret = devm_add_action_or_reset(dev, max1241_disable_vdd_action, adc); + if (ret) { + dev_err(dev, "could not set up vdd regulator cleanup action\n"); + return ret; + } + + adc->vref = devm_regulator_get(dev, "vref"); + if (IS_ERR(adc->vref)) { + dev_err(dev, "failed to get vref regulator\n"); + return PTR_ERR(adc->vref); + } + + ret = regulator_enable(adc->vref); + if (ret) + return ret; + + ret = devm_add_action_or_reset(dev, max1241_disable_vref_action, adc); + if (ret) { + dev_err(dev, "could not set up vref regulator cleanup action\n"); + return ret; + } + + adc->shutdown = devm_gpiod_get_optional(dev, "shutdown", + GPIOD_OUT_HIGH); + if (IS_ERR(adc->shutdown)) + return PTR_ERR(adc->shutdown); + + if (adc->shutdown) + dev_dbg(dev, "shutdown pin passed, low-power mode enabled"); + else + dev_dbg(dev, "no shutdown pin passed, low-power mode disabled"); + + indio_dev->name = spi_get_device_id(spi)->name; + indio_dev->dev.parent = dev; + indio_dev->info = &max1241_info; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->channels = max1241_channels; + indio_dev->num_channels = ARRAY_SIZE(max1241_channels); + + return devm_iio_device_register(dev, indio_dev); +} + +static const struct spi_device_id max1241_id[] = { + { "max1241", max1241 }, + {} +}; + +static const struct of_device_id max1241_dt_ids[] = { + { .compatible = "maxim,max1241" }, + {} +}; +MODULE_DEVICE_TABLE(of, max1241_dt_ids); + +static struct spi_driver max1241_spi_driver = { + .driver = { + .name = "max1241", + .of_match_table = max1241_dt_ids, + }, + .probe = max1241_probe, + .id_table = max1241_id, +}; +module_spi_driver(max1241_spi_driver); + +MODULE_AUTHOR("Alexandru Lazar "); +MODULE_DESCRIPTION("MAX1241 ADC driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/iio/adc/max1363.c b/drivers/iio/adc/max1363.c index 5c2cc61b666e..9d92017c79b2 100644 --- a/drivers/iio/adc/max1363.c +++ b/drivers/iio/adc/max1363.c @@ -150,6 +150,7 @@ struct max1363_chip_info { * @current_mode: the scan mode of this chip * @requestedmask: a valid requested set of channels * @reg: supply regulator + * @lock lock to ensure state is consistent * @monitor_on: whether monitor mode is enabled * @monitor_speed: parameter corresponding to device monitor speed setting * @mask_high: bitmask for enabled high thresholds @@ -169,6 +170,7 @@ struct max1363_state { const struct max1363_mode *current_mode; u32 requestedmask; struct regulator *reg; + struct mutex lock; /* Using monitor modes and buffer at the same time is currently not supported */ @@ -364,7 +366,11 @@ static int max1363_read_single_chan(struct iio_dev *indio_dev, struct max1363_state *st = iio_priv(indio_dev); struct i2c_client *client = st->client; - mutex_lock(&indio_dev->mlock); + ret = iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; + mutex_lock(&st->lock); + /* * If monitor mode is enabled, the method for reading a single * channel will have to be rather different and has not yet @@ -372,7 +378,7 @@ static int max1363_read_single_chan(struct iio_dev *indio_dev, * * Also, cannot read directly if buffered capture enabled. */ - if (st->monitor_on || iio_buffer_enabled(indio_dev)) { + if (st->monitor_on) { ret = -EBUSY; goto error_ret; } @@ -404,8 +410,10 @@ static int max1363_read_single_chan(struct iio_dev *indio_dev, data = rxbuf[0]; } *val = data; + error_ret: - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); + iio_device_release_direct_mode(indio_dev); return ret; } @@ -705,9 +713,9 @@ static ssize_t max1363_monitor_store_freq(struct device *dev, if (!found) return -EINVAL; - mutex_lock(&indio_dev->mlock); + mutex_lock(&st->lock); st->monitor_speed = i; - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); return 0; } @@ -810,12 +818,12 @@ static int max1363_read_event_config(struct iio_dev *indio_dev, int val; int number = chan->channel; - mutex_lock(&indio_dev->mlock); + mutex_lock(&st->lock); if (dir == IIO_EV_DIR_FALLING) val = (1 << number) & st->mask_low; else val = (1 << number) & st->mask_high; - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); return val; } @@ -962,7 +970,11 @@ static int max1363_write_event_config(struct iio_dev *indio_dev, u16 unifiedmask; int number = chan->channel; - mutex_lock(&indio_dev->mlock); + ret = iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; + mutex_lock(&st->lock); + unifiedmask = st->mask_low | st->mask_high; if (dir == IIO_EV_DIR_FALLING) { @@ -989,7 +1001,8 @@ static int max1363_write_event_config(struct iio_dev *indio_dev, max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low)); error_ret: - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); + iio_device_release_direct_mode(indio_dev); return ret; } @@ -1587,6 +1600,7 @@ static int max1363_probe(struct i2c_client *client, st = iio_priv(indio_dev); + mutex_init(&st->lock); st->reg = devm_regulator_get(&client->dev, "vcc"); if (IS_ERR(st->reg)) { ret = PTR_ERR(st->reg); diff --git a/drivers/iio/adc/mcp3422.c b/drivers/iio/adc/mcp3422.c index ea24d7c58b12..d86c0b5d80a3 100644 --- a/drivers/iio/adc/mcp3422.c +++ b/drivers/iio/adc/mcp3422.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -117,11 +118,11 @@ static int mcp3422_read(struct mcp3422 *adc, int *value, u8 *config) if (sample_rate == MCP3422_SRATE_3) { ret = i2c_master_recv(adc->i2c, buf, 4); - temp = buf[0] << 16 | buf[1] << 8 | buf[2]; + temp = get_unaligned_be24(&buf[0]); *config = buf[3]; } else { ret = i2c_master_recv(adc->i2c, buf, 3); - temp = buf[0] << 8 | buf[1]; + temp = get_unaligned_be16(&buf[0]); *config = buf[2]; } diff --git a/drivers/iio/adc/stm32-adc-core.c b/drivers/iio/adc/stm32-adc-core.c index 2df88d2b880a..0e2068ec068b 100644 --- a/drivers/iio/adc/stm32-adc-core.c +++ b/drivers/iio/adc/stm32-adc-core.c @@ -65,12 +65,14 @@ struct stm32_adc_priv; * @clk_sel: clock selection routine * @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet) * @has_syscfg: SYSCFG capability flags + * @num_irqs: number of interrupt lines */ struct stm32_adc_priv_cfg { const struct stm32_adc_common_regs *regs; int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *); u32 max_clk_rate_hz; unsigned int has_syscfg; + unsigned int num_irqs; }; /** @@ -375,21 +377,15 @@ static int stm32_adc_irq_probe(struct platform_device *pdev, struct device_node *np = pdev->dev.of_node; unsigned int i; - for (i = 0; i < STM32_ADC_MAX_ADCS; i++) { + /* + * Interrupt(s) must be provided, depending on the compatible: + * - stm32f4/h7 shares a common interrupt line. + * - stm32mp1, has one line per ADC + */ + for (i = 0; i < priv->cfg->num_irqs; i++) { priv->irq[i] = platform_get_irq(pdev, i); - if (priv->irq[i] < 0) { - /* - * At least one interrupt must be provided, make others - * optional: - * - stm32f4/h7 shares a common interrupt. - * - stm32mp1, has one line per ADC (either for ADC1, - * ADC2 or both). - */ - if (i && priv->irq[i] == -ENXIO) - continue; - + if (priv->irq[i] < 0) return priv->irq[i]; - } } priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0, @@ -400,9 +396,7 @@ static int stm32_adc_irq_probe(struct platform_device *pdev, return -ENOMEM; } - for (i = 0; i < STM32_ADC_MAX_ADCS; i++) { - if (priv->irq[i] < 0) - continue; + for (i = 0; i < priv->cfg->num_irqs; i++) { irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler); irq_set_handler_data(priv->irq[i], priv); } @@ -420,11 +414,8 @@ static void stm32_adc_irq_remove(struct platform_device *pdev, irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq)); irq_domain_remove(priv->domain); - for (i = 0; i < STM32_ADC_MAX_ADCS; i++) { - if (priv->irq[i] < 0) - continue; + for (i = 0; i < priv->cfg->num_irqs; i++) irq_set_chained_handler(priv->irq[i], NULL); - } } static int stm32_adc_core_switches_supply_en(struct stm32_adc_priv *priv, @@ -817,6 +808,7 @@ static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = { .regs = &stm32f4_adc_common_regs, .clk_sel = stm32f4_adc_clk_sel, .max_clk_rate_hz = 36000000, + .num_irqs = 1, }; static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = { @@ -824,6 +816,7 @@ static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = { .clk_sel = stm32h7_adc_clk_sel, .max_clk_rate_hz = 36000000, .has_syscfg = HAS_VBOOSTER, + .num_irqs = 1, }; static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = { @@ -831,6 +824,7 @@ static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = { .clk_sel = stm32h7_adc_clk_sel, .max_clk_rate_hz = 40000000, .has_syscfg = HAS_VBOOSTER | HAS_ANASWVDD, + .num_irqs = 2, }; static const struct of_device_id stm32_adc_of_match[] = { diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c b/drivers/iio/adc/sun4i-gpadc-iio.c index 176e1cb4abb1..0f2c1738a90d 100644 --- a/drivers/iio/adc/sun4i-gpadc-iio.c +++ b/drivers/iio/adc/sun4i-gpadc-iio.c @@ -496,7 +496,6 @@ static int sun4i_gpadc_probe_dt(struct platform_device *pdev, struct iio_dev *indio_dev) { struct sun4i_gpadc_iio *info = iio_priv(indio_dev); - struct resource *mem; void __iomem *base; int ret; @@ -508,8 +507,7 @@ static int sun4i_gpadc_probe_dt(struct platform_device *pdev, indio_dev->num_channels = ARRAY_SIZE(sun8i_a33_gpadc_channels); indio_dev->channels = sun8i_a33_gpadc_channels; - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(&pdev->dev, mem); + base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); diff --git a/drivers/iio/adc/ti-ads124s08.c b/drivers/iio/adc/ti-ads124s08.c index 552c2be8d87a..f1ee3b1e2827 100644 --- a/drivers/iio/adc/ti-ads124s08.c +++ b/drivers/iio/adc/ti-ads124s08.c @@ -22,6 +22,8 @@ #include #include +#include + /* Commands */ #define ADS124S08_CMD_NOP 0x00 #define ADS124S08_CMD_WAKEUP 0x02 @@ -188,7 +190,6 @@ static int ads124s_read(struct iio_dev *indio_dev, unsigned int chan) { struct ads124s_private *priv = iio_priv(indio_dev); int ret; - u32 tmp; struct spi_transfer t[] = { { .tx_buf = &priv->data[0], @@ -208,9 +209,7 @@ static int ads124s_read(struct iio_dev *indio_dev, unsigned int chan) if (ret < 0) return ret; - tmp = priv->data[2] << 16 | priv->data[3] << 8 | priv->data[4]; - - return tmp; + return get_unaligned_be24(&priv->data[2]); } static int ads124s_read_raw(struct iio_dev *indio_dev, diff --git a/drivers/iio/adc/xilinx-xadc-core.c b/drivers/iio/adc/xilinx-xadc-core.c index 6fd06e4eff73..d7fecab9252e 100644 --- a/drivers/iio/adc/xilinx-xadc-core.c +++ b/drivers/iio/adc/xilinx-xadc-core.c @@ -3,7 +3,7 @@ * Xilinx XADC driver * * Copyright 2013-2014 Analog Devices Inc. - * Author: Lars-Peter Clauen + * Author: Lars-Peter Clausen * * Documentation for the parts can be found at: * - XADC hardmacro: Xilinx UG480 @@ -663,7 +663,7 @@ static int xadc_trigger_set_state(struct iio_trigger *trigger, bool state) mutex_lock(&xadc->mutex); if (state) { - /* Only one of the two triggers can be active at the a time. */ + /* Only one of the two triggers can be active at a time. */ if (xadc->trigger != NULL) { ret = -EBUSY; goto err_out; diff --git a/drivers/iio/adc/xilinx-xadc-events.c b/drivers/iio/adc/xilinx-xadc-events.c index dbfd5da290a4..2357f585720a 100644 --- a/drivers/iio/adc/xilinx-xadc-events.c +++ b/drivers/iio/adc/xilinx-xadc-events.c @@ -3,7 +3,7 @@ * Xilinx XADC driver * * Copyright 2013 Analog Devices Inc. - * Author: Lars-Peter Clauen + * Author: Lars-Peter Clausen */ #include diff --git a/drivers/iio/adc/xilinx-xadc.h b/drivers/iio/adc/xilinx-xadc.h index 4017f18b0a4f..25abed9c0285 100644 --- a/drivers/iio/adc/xilinx-xadc.h +++ b/drivers/iio/adc/xilinx-xadc.h @@ -3,7 +3,7 @@ * Xilinx XADC driver * * Copyright 2013 Analog Devices Inc. - * Author: Lars-Peter Clauen + * Author: Lars-Peter Clausen */ #ifndef __IIO_XILINX_XADC__ diff --git a/drivers/iio/buffer/industrialio-buffer-dma.c b/drivers/iio/buffer/industrialio-buffer-dma.c index a74bd9c0587c..d348af8b9705 100644 --- a/drivers/iio/buffer/industrialio-buffer-dma.c +++ b/drivers/iio/buffer/industrialio-buffer-dma.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/iio/buffer/industrialio-buffer-dmaengine.c b/drivers/iio/buffer/industrialio-buffer-dmaengine.c index b129693af0fd..6dedf12b69a4 100644 --- a/drivers/iio/buffer/industrialio-buffer-dmaengine.c +++ b/drivers/iio/buffer/industrialio-buffer-dmaengine.c @@ -134,7 +134,7 @@ static ssize_t iio_dmaengine_buffer_get_length_align(struct device *dev, struct dmaengine_buffer *dmaengine_buffer = iio_buffer_to_dmaengine_buffer(indio_dev->buffer); - return sprintf(buf, "%u\n", dmaengine_buffer->align); + return sprintf(buf, "%zu\n", dmaengine_buffer->align); } static IIO_DEVICE_ATTR(length_align_bytes, 0444, @@ -229,6 +229,45 @@ void iio_dmaengine_buffer_free(struct iio_buffer *buffer) } EXPORT_SYMBOL_GPL(iio_dmaengine_buffer_free); +static void __devm_iio_dmaengine_buffer_free(struct device *dev, void *res) +{ + iio_dmaengine_buffer_free(*(struct iio_buffer **)res); +} + +/** + * devm_iio_dmaengine_buffer_alloc() - Resource-managed iio_dmaengine_buffer_alloc() + * @dev: Parent device for the buffer + * @channel: DMA channel name, typically "rx". + * + * This allocates a new IIO buffer which internally uses the DMAengine framework + * to perform its transfers. The parent device will be used to request the DMA + * channel. + * + * The buffer will be automatically de-allocated once the device gets destroyed. + */ +struct iio_buffer *devm_iio_dmaengine_buffer_alloc(struct device *dev, + const char *channel) +{ + struct iio_buffer **bufferp, *buffer; + + bufferp = devres_alloc(__devm_iio_dmaengine_buffer_free, + sizeof(*bufferp), GFP_KERNEL); + if (!bufferp) + return ERR_PTR(-ENOMEM); + + buffer = iio_dmaengine_buffer_alloc(dev, channel); + if (IS_ERR(buffer)) { + devres_free(bufferp); + return buffer; + } + + *bufferp = buffer; + devres_add(dev, bufferp); + + return buffer; +} +EXPORT_SYMBOL_GPL(devm_iio_dmaengine_buffer_alloc); + MODULE_AUTHOR("Lars-Peter Clausen "); MODULE_DESCRIPTION("DMA buffer for the IIO framework"); MODULE_LICENSE("GPL"); diff --git a/drivers/iio/buffer/industrialio-hw-consumer.c b/drivers/iio/buffer/industrialio-hw-consumer.c index 95165697d8ae..f2d27788f666 100644 --- a/drivers/iio/buffer/industrialio-hw-consumer.c +++ b/drivers/iio/buffer/industrialio-hw-consumer.c @@ -142,17 +142,6 @@ static void devm_iio_hw_consumer_release(struct device *dev, void *res) iio_hw_consumer_free(*(struct iio_hw_consumer **)res); } -static int devm_iio_hw_consumer_match(struct device *dev, void *res, void *data) -{ - struct iio_hw_consumer **r = res; - - if (!r || !*r) { - WARN_ON(!r || !*r); - return 0; - } - return *r == data; -} - /** * devm_iio_hw_consumer_alloc - Resource-managed iio_hw_consumer_alloc() * @dev: Pointer to consumer device. @@ -160,9 +149,6 @@ static int devm_iio_hw_consumer_match(struct device *dev, void *res, void *data) * Managed iio_hw_consumer_alloc. iio_hw_consumer allocated with this function * is automatically freed on driver detach. * - * If an iio_hw_consumer allocated with this function needs to be freed - * separately, devm_iio_hw_consumer_free() must be used. - * * returns pointer to allocated iio_hw_consumer on success, NULL on failure. */ struct iio_hw_consumer *devm_iio_hw_consumer_alloc(struct device *dev) @@ -186,23 +172,6 @@ struct iio_hw_consumer *devm_iio_hw_consumer_alloc(struct device *dev) } EXPORT_SYMBOL_GPL(devm_iio_hw_consumer_alloc); -/** - * devm_iio_hw_consumer_free - Resource-managed iio_hw_consumer_free() - * @dev: Pointer to consumer device. - * @hwc: iio_hw_consumer to free. - * - * Free iio_hw_consumer allocated with devm_iio_hw_consumer_alloc(). - */ -void devm_iio_hw_consumer_free(struct device *dev, struct iio_hw_consumer *hwc) -{ - int rc; - - rc = devres_release(dev, devm_iio_hw_consumer_release, - devm_iio_hw_consumer_match, hwc); - WARN_ON(rc); -} -EXPORT_SYMBOL_GPL(devm_iio_hw_consumer_free); - /** * iio_hw_consumer_enable() - Enable IIO hardware consumer * @hwc: iio_hw_consumer to enable. diff --git a/drivers/iio/buffer/industrialio-triggered-buffer.c b/drivers/iio/buffer/industrialio-triggered-buffer.c index cb322b2f09cd..e8046c1ecd6b 100644 --- a/drivers/iio/buffer/industrialio-triggered-buffer.c +++ b/drivers/iio/buffer/industrialio-triggered-buffer.c @@ -126,17 +126,6 @@ int devm_iio_triggered_buffer_setup(struct device *dev, } EXPORT_SYMBOL_GPL(devm_iio_triggered_buffer_setup); -void devm_iio_triggered_buffer_cleanup(struct device *dev, - struct iio_dev *indio_dev) -{ - int rc; - - rc = devres_release(dev, devm_iio_triggered_buffer_clean, - devm_iio_device_match, indio_dev); - WARN_ON(rc); -} -EXPORT_SYMBOL_GPL(devm_iio_triggered_buffer_cleanup); - MODULE_AUTHOR("Lars-Peter Clausen "); MODULE_DESCRIPTION("IIO helper functions for setting up triggered buffers"); MODULE_LICENSE("GPL"); diff --git a/drivers/iio/buffer/kfifo_buf.c b/drivers/iio/buffer/kfifo_buf.c index 3150f8ab984b..1359abed3b31 100644 --- a/drivers/iio/buffer/kfifo_buf.c +++ b/drivers/iio/buffer/kfifo_buf.c @@ -179,16 +179,6 @@ static void devm_iio_kfifo_release(struct device *dev, void *res) iio_kfifo_free(*(struct iio_buffer **)res); } -static int devm_iio_kfifo_match(struct device *dev, void *res, void *data) -{ - struct iio_buffer **r = res; - - if (WARN_ON(!r || !*r)) - return 0; - - return *r == data; -} - /** * devm_iio_fifo_allocate - Resource-managed iio_kfifo_allocate() * @dev: Device to allocate kfifo buffer for @@ -216,16 +206,4 @@ struct iio_buffer *devm_iio_kfifo_allocate(struct device *dev) } EXPORT_SYMBOL(devm_iio_kfifo_allocate); -/** - * devm_iio_fifo_free - Resource-managed iio_kfifo_free() - * @dev: Device the buffer belongs to - * @r: The buffer associated with the device - */ -void devm_iio_kfifo_free(struct device *dev, struct iio_buffer *r) -{ - WARN_ON(devres_release(dev, devm_iio_kfifo_release, - devm_iio_kfifo_match, r)); -} -EXPORT_SYMBOL(devm_iio_kfifo_free); - MODULE_LICENSE("GPL"); diff --git a/drivers/iio/chemical/Kconfig b/drivers/iio/chemical/Kconfig index a7e65a59bf42..7f21afd73b1c 100644 --- a/drivers/iio/chemical/Kconfig +++ b/drivers/iio/chemical/Kconfig @@ -22,6 +22,17 @@ config ATLAS_PH_SENSOR To compile this driver as module, choose M here: the module will be called atlas-ph-sensor. +config ATLAS_EZO_SENSOR + tristate "Atlas Scientific EZO sensors" + depends on I2C + help + Say Y here to build I2C interface support for the following + Atlas Scientific EZO sensors + * CO2 EZO Sensor + + To compile this driver as module, choose M here: the + module will be called atlas-ezo-sensor. + config BME680 tristate "Bosch Sensortec BME680 sensor driver" depends on (I2C || SPI) diff --git a/drivers/iio/chemical/Makefile b/drivers/iio/chemical/Makefile index 33d3a595dda9..aba4167db745 100644 --- a/drivers/iio/chemical/Makefile +++ b/drivers/iio/chemical/Makefile @@ -5,6 +5,7 @@ # When adding new entries keep the list in alphabetical order obj-$(CONFIG_ATLAS_PH_SENSOR) += atlas-sensor.o +obj-$(CONFIG_ATLAS_EZO_SENSOR) += atlas-ezo-sensor.o obj-$(CONFIG_BME680) += bme680_core.o obj-$(CONFIG_BME680_I2C) += bme680_i2c.o obj-$(CONFIG_BME680_SPI) += bme680_spi.o diff --git a/drivers/iio/chemical/atlas-ezo-sensor.c b/drivers/iio/chemical/atlas-ezo-sensor.c new file mode 100644 index 000000000000..f5a6d8ec6d4d --- /dev/null +++ b/drivers/iio/chemical/atlas-ezo-sensor.c @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * atlas-ezo-sensor.c - Support for Atlas Scientific EZO sensors + * + * Copyright (C) 2020 Konsulko Group + * Author: Matt Ranostay + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define ATLAS_EZO_DRV_NAME "atlas-ezo-sensor" +#define ATLAS_CO2_INT_TIME_IN_MS 950 + +enum { + ATLAS_CO2_EZO, +}; + +struct atlas_ezo_device { + const struct iio_chan_spec *channels; + int num_channels; + int delay; +}; + +struct atlas_ezo_data { + struct i2c_client *client; + struct atlas_ezo_device *chip; + + /* lock to avoid multiple concurrent read calls */ + struct mutex lock; + + u8 buffer[8]; +}; + +static const struct iio_chan_spec atlas_co2_ezo_channels[] = { + { + .type = IIO_CONCENTRATION, + .modified = 1, + .channel2 = IIO_MOD_CO2, + .info_mask_separate = + BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), + .scan_index = 0, + .scan_type = { + .sign = 'u', + .realbits = 32, + .storagebits = 32, + .endianness = IIO_CPU, + }, + }, +}; + +static struct atlas_ezo_device atlas_ezo_devices[] = { + [ATLAS_CO2_EZO] = { + .channels = atlas_co2_ezo_channels, + .num_channels = 1, + .delay = ATLAS_CO2_INT_TIME_IN_MS, + }, +}; + +static int atlas_ezo_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct atlas_ezo_data *data = iio_priv(indio_dev); + struct i2c_client *client = data->client; + int ret = 0; + + if (chan->type != IIO_CONCENTRATION) + return -EINVAL; + + switch (mask) { + case IIO_CHAN_INFO_RAW: { + long tmp; + + mutex_lock(&data->lock); + + tmp = i2c_smbus_write_byte(client, 'R'); + + if (tmp < 0) { + mutex_unlock(&data->lock); + return tmp; + } + + msleep(data->chip->delay); + + tmp = i2c_master_recv(client, data->buffer, sizeof(data->buffer)); + + if (tmp < 0 || data->buffer[0] != 1) { + mutex_unlock(&data->lock); + return -EBUSY; + } + + ret = kstrtol(data->buffer + 1, 10, &tmp); + + *val = tmp; + + mutex_unlock(&data->lock); + + return ret ? ret : IIO_VAL_INT; + } + case IIO_CHAN_INFO_SCALE: + *val = 0; + *val2 = 100; /* 0.0001 */ + return IIO_VAL_INT_PLUS_MICRO; + } + + return ret; +} + +static const struct iio_info atlas_info = { + .read_raw = atlas_ezo_read_raw, +}; + +static const struct i2c_device_id atlas_ezo_id[] = { + { "atlas-co2-ezo", ATLAS_CO2_EZO }, + {} +}; +MODULE_DEVICE_TABLE(i2c, atlas_ezo_id); + +static const struct of_device_id atlas_ezo_dt_ids[] = { + { .compatible = "atlas,co2-ezo", .data = (void *)ATLAS_CO2_EZO, }, + {} +}; +MODULE_DEVICE_TABLE(of, atlas_ezo_dt_ids); + +static int atlas_ezo_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct atlas_ezo_data *data; + struct atlas_ezo_device *chip; + const struct of_device_id *of_id; + struct iio_dev *indio_dev; + + indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); + if (!indio_dev) + return -ENOMEM; + + of_id = of_match_device(atlas_ezo_dt_ids, &client->dev); + if (!of_id) + chip = &atlas_ezo_devices[id->driver_data]; + else + chip = &atlas_ezo_devices[(unsigned long)of_id->data]; + + indio_dev->info = &atlas_info; + indio_dev->name = ATLAS_EZO_DRV_NAME; + indio_dev->channels = chip->channels; + indio_dev->num_channels = chip->num_channels; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->dev.parent = &client->dev; + + data = iio_priv(indio_dev); + data->client = client; + data->chip = chip; + mutex_init(&data->lock); + + return devm_iio_device_register(&client->dev, indio_dev); +}; + +static struct i2c_driver atlas_ezo_driver = { + .driver = { + .name = ATLAS_EZO_DRV_NAME, + .of_match_table = atlas_ezo_dt_ids, + }, + .probe = atlas_ezo_probe, + .id_table = atlas_ezo_id, +}; +module_i2c_driver(atlas_ezo_driver); + +MODULE_AUTHOR("Matt Ranostay "); +MODULE_DESCRIPTION("Atlas Scientific EZO sensors"); +MODULE_LICENSE("GPL"); diff --git a/drivers/iio/chemical/atlas-sensor.c b/drivers/iio/chemical/atlas-sensor.c index 7b199ce16ecf..78a27e36bf32 100644 --- a/drivers/iio/chemical/atlas-sensor.c +++ b/drivers/iio/chemical/atlas-sensor.c @@ -53,6 +53,8 @@ #define ATLAS_REG_DO_CALIB_STATUS_PRESSURE BIT(0) #define ATLAS_REG_DO_CALIB_STATUS_DO BIT(1) +#define ATLAS_REG_RTD_DATA 0x0e + #define ATLAS_REG_PH_TEMP_DATA 0x0e #define ATLAS_REG_PH_DATA 0x16 @@ -72,12 +74,14 @@ #define ATLAS_EC_INT_TIME_IN_MS 650 #define ATLAS_ORP_INT_TIME_IN_MS 450 #define ATLAS_DO_INT_TIME_IN_MS 450 +#define ATLAS_RTD_INT_TIME_IN_MS 450 enum { ATLAS_PH_SM, ATLAS_EC_SM, ATLAS_ORP_SM, ATLAS_DO_SM, + ATLAS_RTD_SM, }; struct atlas_data { @@ -218,6 +222,22 @@ static const struct iio_chan_spec atlas_do_channels[] = { }, }; +static const struct iio_chan_spec atlas_rtd_channels[] = { + { + .type = IIO_TEMP, + .address = ATLAS_REG_RTD_DATA, + .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), + .scan_index = 0, + .scan_type = { + .sign = 's', + .realbits = 32, + .storagebits = 32, + .endianness = IIO_BE, + }, + }, + IIO_CHAN_SOFT_TIMESTAMP(1), +}; + static int atlas_check_ph_calibration(struct atlas_data *data) { struct device *dev = &data->client->dev; @@ -362,6 +382,12 @@ static struct atlas_device atlas_devices[] = { .calibration = &atlas_check_do_calibration, .delay = ATLAS_DO_INT_TIME_IN_MS, }, + [ATLAS_RTD_SM] = { + .channels = atlas_rtd_channels, + .num_channels = 2, + .data_reg = ATLAS_REG_RTD_DATA, + .delay = ATLAS_RTD_INT_TIME_IN_MS, + }, }; static int atlas_set_powermode(struct atlas_data *data, int on) @@ -438,8 +464,7 @@ static irqreturn_t atlas_trigger_handler(int irq, void *private) int ret; ret = regmap_bulk_read(data->regmap, data->chip->data_reg, - (u8 *) &data->buffer, - sizeof(__be32) * channels); + &data->buffer, sizeof(__be32) * channels); if (!ret) iio_push_to_buffers_with_timestamp(indio_dev, data->buffer, @@ -475,7 +500,7 @@ static int atlas_read_measurement(struct atlas_data *data, int reg, __be32 *val) if (suspended) msleep(data->chip->delay); - ret = regmap_bulk_read(data->regmap, reg, (u8 *) val, sizeof(*val)); + ret = regmap_bulk_read(data->regmap, reg, val, sizeof(*val)); pm_runtime_mark_last_busy(dev); pm_runtime_put_autosuspend(dev); @@ -490,6 +515,7 @@ static int atlas_read_raw(struct iio_dev *indio_dev, struct atlas_data *data = iio_priv(indio_dev); switch (mask) { + case IIO_CHAN_INFO_PROCESSED: case IIO_CHAN_INFO_RAW: { int ret; __be32 reg; @@ -497,7 +523,7 @@ static int atlas_read_raw(struct iio_dev *indio_dev, switch (chan->type) { case IIO_TEMP: ret = regmap_bulk_read(data->regmap, chan->address, - (u8 *) ®, sizeof(reg)); + ®, sizeof(reg)); break; case IIO_PH: case IIO_CONCENTRATION: @@ -578,6 +604,7 @@ static const struct i2c_device_id atlas_id[] = { { "atlas-ec-sm", ATLAS_EC_SM}, { "atlas-orp-sm", ATLAS_ORP_SM}, { "atlas-do-sm", ATLAS_DO_SM}, + { "atlas-rtd-sm", ATLAS_RTD_SM}, {} }; MODULE_DEVICE_TABLE(i2c, atlas_id); @@ -587,6 +614,7 @@ static const struct of_device_id atlas_dt_ids[] = { { .compatible = "atlas,ec-sm", .data = (void *)ATLAS_EC_SM, }, { .compatible = "atlas,orp-sm", .data = (void *)ATLAS_ORP_SM, }, { .compatible = "atlas,do-sm", .data = (void *)ATLAS_DO_SM, }, + { .compatible = "atlas,rtd-sm", .data = (void *)ATLAS_RTD_SM, }, { } }; MODULE_DEVICE_TABLE(of, atlas_dt_ids); diff --git a/drivers/iio/chemical/bme680_core.c b/drivers/iio/chemical/bme680_core.c index ccde4c65ff93..13773e01699b 100644 --- a/drivers/iio/chemical/bme680_core.c +++ b/drivers/iio/chemical/bme680_core.c @@ -114,14 +114,16 @@ static int bme680_read_calib(struct bme680_data *data, __le16 buf; /* Temperature related coefficients */ - ret = regmap_bulk_read(data->regmap, BME680_T1_LSB_REG, (u8 *) &buf, 2); + ret = regmap_bulk_read(data->regmap, BME680_T1_LSB_REG, + &buf, sizeof(buf)); if (ret < 0) { dev_err(dev, "failed to read BME680_T1_LSB_REG\n"); return ret; } calib->par_t1 = le16_to_cpu(buf); - ret = regmap_bulk_read(data->regmap, BME680_T2_LSB_REG, (u8 *) &buf, 2); + ret = regmap_bulk_read(data->regmap, BME680_T2_LSB_REG, + &buf, sizeof(buf)); if (ret < 0) { dev_err(dev, "failed to read BME680_T2_LSB_REG\n"); return ret; @@ -136,14 +138,16 @@ static int bme680_read_calib(struct bme680_data *data, calib->par_t3 = tmp; /* Pressure related coefficients */ - ret = regmap_bulk_read(data->regmap, BME680_P1_LSB_REG, (u8 *) &buf, 2); + ret = regmap_bulk_read(data->regmap, BME680_P1_LSB_REG, + &buf, sizeof(buf)); if (ret < 0) { dev_err(dev, "failed to read BME680_P1_LSB_REG\n"); return ret; } calib->par_p1 = le16_to_cpu(buf); - ret = regmap_bulk_read(data->regmap, BME680_P2_LSB_REG, (u8 *) &buf, 2); + ret = regmap_bulk_read(data->regmap, BME680_P2_LSB_REG, + &buf, sizeof(buf)); if (ret < 0) { dev_err(dev, "failed to read BME680_P2_LSB_REG\n"); return ret; @@ -157,14 +161,16 @@ static int bme680_read_calib(struct bme680_data *data, } calib->par_p3 = tmp; - ret = regmap_bulk_read(data->regmap, BME680_P4_LSB_REG, (u8 *) &buf, 2); + ret = regmap_bulk_read(data->regmap, BME680_P4_LSB_REG, + &buf, sizeof(buf)); if (ret < 0) { dev_err(dev, "failed to read BME680_P4_LSB_REG\n"); return ret; } calib->par_p4 = le16_to_cpu(buf); - ret = regmap_bulk_read(data->regmap, BME680_P5_LSB_REG, (u8 *) &buf, 2); + ret = regmap_bulk_read(data->regmap, BME680_P5_LSB_REG, + &buf, sizeof(buf)); if (ret < 0) { dev_err(dev, "failed to read BME680_P5_LSB_REG\n"); return ret; @@ -185,14 +191,16 @@ static int bme680_read_calib(struct bme680_data *data, } calib->par_p7 = tmp; - ret = regmap_bulk_read(data->regmap, BME680_P8_LSB_REG, (u8 *) &buf, 2); + ret = regmap_bulk_read(data->regmap, BME680_P8_LSB_REG, + &buf, sizeof(buf)); if (ret < 0) { dev_err(dev, "failed to read BME680_P8_LSB_REG\n"); return ret; } calib->par_p8 = le16_to_cpu(buf); - ret = regmap_bulk_read(data->regmap, BME680_P9_LSB_REG, (u8 *) &buf, 2); + ret = regmap_bulk_read(data->regmap, BME680_P9_LSB_REG, + &buf, sizeof(buf)); if (ret < 0) { dev_err(dev, "failed to read BME680_P9_LSB_REG\n"); return ret; @@ -276,8 +284,8 @@ static int bme680_read_calib(struct bme680_data *data, } calib->par_gh1 = tmp; - ret = regmap_bulk_read(data->regmap, BME680_GH2_LSB_REG, (u8 *) &buf, - 2); + ret = regmap_bulk_read(data->regmap, BME680_GH2_LSB_REG, + &buf, sizeof(buf)); if (ret < 0) { dev_err(dev, "failed to read BME680_GH2_LSB_REG\n"); return ret; @@ -615,7 +623,7 @@ static int bme680_read_temp(struct bme680_data *data, int *val) return ret; ret = regmap_bulk_read(data->regmap, BME680_REG_TEMP_MSB, - (u8 *) &tmp, 3); + &tmp, 3); if (ret < 0) { dev_err(dev, "failed to read temperature\n"); return ret; @@ -656,7 +664,7 @@ static int bme680_read_press(struct bme680_data *data, return ret; ret = regmap_bulk_read(data->regmap, BME680_REG_PRESS_MSB, - (u8 *) &tmp, 3); + &tmp, 3); if (ret < 0) { dev_err(dev, "failed to read pressure\n"); return ret; @@ -689,7 +697,7 @@ static int bme680_read_humid(struct bme680_data *data, return ret; ret = regmap_bulk_read(data->regmap, BM6880_REG_HUMIDITY_MSB, - (u8 *) &tmp, 2); + &tmp, sizeof(tmp)); if (ret < 0) { dev_err(dev, "failed to read humidity\n"); return ret; @@ -754,7 +762,7 @@ static int bme680_read_gas(struct bme680_data *data, } ret = regmap_bulk_read(data->regmap, BME680_REG_GAS_MSB, - (u8 *) &tmp, 2); + &tmp, sizeof(tmp)); if (ret < 0) { dev_err(dev, "failed to read gas resistance\n"); return ret; diff --git a/drivers/iio/chemical/ccs811.c b/drivers/iio/chemical/ccs811.c index 2ebdfc35bcda..3ecd633f9ed3 100644 --- a/drivers/iio/chemical/ccs811.c +++ b/drivers/iio/chemical/ccs811.c @@ -16,6 +16,7 @@ */ #include +#include #include #include #include @@ -36,6 +37,7 @@ #define CCS811_ERR 0xE0 /* Used to transition from boot to application mode */ #define CCS811_APP_START 0xF4 +#define CCS811_SW_RESET 0xFF /* Status register flags */ #define CCS811_STATUS_ERROR BIT(0) @@ -74,6 +76,7 @@ struct ccs811_data { struct mutex lock; /* Protect readings */ struct ccs811_reading buffer; struct iio_trigger *drdy_trig; + struct gpio_desc *wakeup_gpio; bool drdy_trig_on; }; @@ -166,10 +169,25 @@ static int ccs811_setup(struct i2c_client *client) CCS811_MODE_IAQ_1SEC); } +static void ccs811_set_wakeup(struct ccs811_data *data, bool enable) +{ + if (!data->wakeup_gpio) + return; + + gpiod_set_value(data->wakeup_gpio, enable); + + if (enable) + usleep_range(50, 60); + else + usleep_range(20, 30); +} + static int ccs811_get_measurement(struct ccs811_data *data) { int ret, tries = 11; + ccs811_set_wakeup(data, true); + /* Maximum waiting time: 1s, as measurements are made every second */ while (tries-- > 0) { ret = i2c_smbus_read_byte_data(data->client, CCS811_STATUS); @@ -183,9 +201,12 @@ static int ccs811_get_measurement(struct ccs811_data *data) if (!(ret & CCS811_STATUS_DATA_READY)) return -EIO; - return i2c_smbus_read_i2c_block_data(data->client, + ret = i2c_smbus_read_i2c_block_data(data->client, CCS811_ALG_RESULT_DATA, 8, (char *)&data->buffer); + ccs811_set_wakeup(data, false); + + return ret; } static int ccs811_read_raw(struct iio_dev *indio_dev, @@ -336,6 +357,45 @@ static irqreturn_t ccs811_data_rdy_trigger_poll(int irq, void *private) return IRQ_HANDLED; } +static int ccs811_reset(struct i2c_client *client) +{ + struct gpio_desc *reset_gpio; + int ret; + + reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", + GPIOD_OUT_LOW); + if (IS_ERR(reset_gpio)) + return PTR_ERR(reset_gpio); + + /* Try to reset using nRESET pin if available else do SW reset */ + if (reset_gpio) { + gpiod_set_value(reset_gpio, 1); + usleep_range(20, 30); + gpiod_set_value(reset_gpio, 0); + } else { + /* + * As per the datasheet, this sequence of values needs to be + * written to the SW_RESET register for triggering the soft + * reset in the device and placing it in boot mode. + */ + static const u8 reset_seq[] = { + 0x11, 0xE5, 0x72, 0x8A, + }; + + ret = i2c_smbus_write_i2c_block_data(client, CCS811_SW_RESET, + sizeof(reset_seq), reset_seq); + if (ret < 0) { + dev_err(&client->dev, "Failed to reset sensor\n"); + return ret; + } + } + + /* tSTART delay required after reset */ + usleep_range(1000, 2000); + + return 0; +} + static int ccs811_probe(struct i2c_client *client, const struct i2c_device_id *id) { @@ -348,37 +408,60 @@ static int ccs811_probe(struct i2c_client *client, | I2C_FUNC_SMBUS_READ_I2C_BLOCK)) return -EOPNOTSUPP; - /* Check hardware id (should be 0x81 for this family of devices) */ - ret = i2c_smbus_read_byte_data(client, CCS811_HW_ID); - if (ret < 0) - return ret; - - if (ret != CCS811_HW_ID_VALUE) { - dev_err(&client->dev, "hardware id doesn't match CCS81x\n"); - return -ENODEV; - } - - ret = i2c_smbus_read_byte_data(client, CCS811_HW_VERSION); - if (ret < 0) - return ret; - - if ((ret & CCS811_HW_VERSION_MASK) != CCS811_HW_VERSION_VALUE) { - dev_err(&client->dev, "no CCS811 sensor\n"); - return -ENODEV; - } - indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); if (!indio_dev) return -ENOMEM; - ret = ccs811_setup(client); - if (ret < 0) - return ret; - data = iio_priv(indio_dev); i2c_set_clientdata(client, indio_dev); data->client = client; + data->wakeup_gpio = devm_gpiod_get_optional(&client->dev, "wakeup", + GPIOD_OUT_HIGH); + if (IS_ERR(data->wakeup_gpio)) + return PTR_ERR(data->wakeup_gpio); + + ccs811_set_wakeup(data, true); + + ret = ccs811_reset(client); + if (ret) { + ccs811_set_wakeup(data, false); + return ret; + } + + /* Check hardware id (should be 0x81 for this family of devices) */ + ret = i2c_smbus_read_byte_data(client, CCS811_HW_ID); + if (ret < 0) { + ccs811_set_wakeup(data, false); + return ret; + } + + if (ret != CCS811_HW_ID_VALUE) { + dev_err(&client->dev, "hardware id doesn't match CCS81x\n"); + ccs811_set_wakeup(data, false); + return -ENODEV; + } + + ret = i2c_smbus_read_byte_data(client, CCS811_HW_VERSION); + if (ret < 0) { + ccs811_set_wakeup(data, false); + return ret; + } + + if ((ret & CCS811_HW_VERSION_MASK) != CCS811_HW_VERSION_VALUE) { + dev_err(&client->dev, "no CCS811 sensor\n"); + ccs811_set_wakeup(data, false); + return -ENODEV; + } + + ret = ccs811_setup(client); + if (ret < 0) { + ccs811_set_wakeup(data, false); + return ret; + } + + ccs811_set_wakeup(data, false); + mutex_init(&data->lock); indio_dev->dev.parent = &client->dev; @@ -466,9 +549,16 @@ static const struct i2c_device_id ccs811_id[] = { }; MODULE_DEVICE_TABLE(i2c, ccs811_id); +static const struct of_device_id ccs811_dt_ids[] = { + { .compatible = "ams,ccs811" }, + { } +}; +MODULE_DEVICE_TABLE(of, ccs811_dt_ids); + static struct i2c_driver ccs811_driver = { .driver = { .name = "ccs811", + .of_match_table = ccs811_dt_ids, }, .probe = ccs811_probe, .remove = ccs811_remove, diff --git a/drivers/iio/chemical/pms7003.c b/drivers/iio/chemical/pms7003.c index 23c9ab252470..07bb90d72434 100644 --- a/drivers/iio/chemical/pms7003.c +++ b/drivers/iio/chemical/pms7003.c @@ -73,6 +73,11 @@ struct pms7003_state { struct pms7003_frame frame; struct completion frame_ready; struct mutex lock; /* must be held whenever state gets touched */ + /* Used to construct scan to push to the IIO buffer */ + struct { + u16 data[3]; /* PM1, PM2P5, PM10 */ + s64 ts; + } scan; }; static int pms7003_do_cmd(struct pms7003_state *state, enum pms7003_cmd cmd) @@ -104,7 +109,6 @@ static irqreturn_t pms7003_trigger_handler(int irq, void *p) struct iio_dev *indio_dev = pf->indio_dev; struct pms7003_state *state = iio_priv(indio_dev); struct pms7003_frame *frame = &state->frame; - u16 data[3 + 1 + 4]; /* PM1, PM2P5, PM10, padding, timestamp */ int ret; mutex_lock(&state->lock); @@ -114,12 +118,15 @@ static irqreturn_t pms7003_trigger_handler(int irq, void *p) goto err; } - data[PM1] = pms7003_get_pm(frame->data + PMS7003_PM1_OFFSET); - data[PM2P5] = pms7003_get_pm(frame->data + PMS7003_PM2P5_OFFSET); - data[PM10] = pms7003_get_pm(frame->data + PMS7003_PM10_OFFSET); + state->scan.data[PM1] = + pms7003_get_pm(frame->data + PMS7003_PM1_OFFSET); + state->scan.data[PM2P5] = + pms7003_get_pm(frame->data + PMS7003_PM2P5_OFFSET); + state->scan.data[PM10] = + pms7003_get_pm(frame->data + PMS7003_PM10_OFFSET); mutex_unlock(&state->lock); - iio_push_to_buffers_with_timestamp(indio_dev, data, + iio_push_to_buffers_with_timestamp(indio_dev, &state->scan, iio_get_time_ns(indio_dev)); err: iio_trigger_notify_done(indio_dev->trig); diff --git a/drivers/iio/chemical/sps30.c b/drivers/iio/chemical/sps30.c index acb9f8ecbb3d..a88c1fb875a0 100644 --- a/drivers/iio/chemical/sps30.c +++ b/drivers/iio/chemical/sps30.c @@ -230,15 +230,18 @@ static irqreturn_t sps30_trigger_handler(int irq, void *p) struct iio_dev *indio_dev = pf->indio_dev; struct sps30_state *state = iio_priv(indio_dev); int ret; - s32 data[4 + 2]; /* PM1, PM2P5, PM4, PM10, timestamp */ + struct { + s32 data[4]; /* PM1, PM2P5, PM4, PM10 */ + s64 ts; + } scan; mutex_lock(&state->lock); - ret = sps30_do_meas(state, data, 4); + ret = sps30_do_meas(state, scan.data, ARRAY_SIZE(scan.data)); mutex_unlock(&state->lock); if (ret) goto err; - iio_push_to_buffers_with_timestamp(indio_dev, data, + iio_push_to_buffers_with_timestamp(indio_dev, &scan, iio_get_time_ns(indio_dev)); err: iio_trigger_notify_done(indio_dev->trig); diff --git a/drivers/iio/common/hid-sensors/hid-sensor-trigger.c b/drivers/iio/common/hid-sensors/hid-sensor-trigger.c index 906d87780419..ff375790b7e8 100644 --- a/drivers/iio/common/hid-sensors/hid-sensor-trigger.c +++ b/drivers/iio/common/hid-sensors/hid-sensor-trigger.c @@ -13,6 +13,8 @@ #include #include #include +#include +#include #include #include #include "hid-sensor-trigger.h" @@ -222,7 +224,8 @@ static int hid_sensor_data_rdy_trigger_set_state(struct iio_trigger *trig, return hid_sensor_power_state(iio_trigger_get_drvdata(trig), state); } -void hid_sensor_remove_trigger(struct hid_sensor_common *attrb) +void hid_sensor_remove_trigger(struct iio_dev *indio_dev, + struct hid_sensor_common *attrb) { if (atomic_read(&attrb->runtime_pm_enable)) pm_runtime_disable(&attrb->pdev->dev); @@ -233,6 +236,7 @@ void hid_sensor_remove_trigger(struct hid_sensor_common *attrb) cancel_work_sync(&attrb->work); iio_trigger_unregister(attrb->trigger); iio_trigger_free(attrb->trigger); + iio_triggered_buffer_cleanup(indio_dev); } EXPORT_SYMBOL(hid_sensor_remove_trigger); @@ -246,11 +250,18 @@ int hid_sensor_setup_trigger(struct iio_dev *indio_dev, const char *name, int ret; struct iio_trigger *trig; + ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time, + NULL, NULL); + if (ret) { + dev_err(&indio_dev->dev, "Triggered Buffer Setup Failed\n"); + return ret; + } + trig = iio_trigger_alloc("%s-dev%d", name, indio_dev->id); if (trig == NULL) { dev_err(&indio_dev->dev, "Trigger Allocate Failed\n"); ret = -ENOMEM; - goto error_ret; + goto error_triggered_buffer_cleanup; } trig->dev.parent = indio_dev->dev.parent; @@ -284,7 +295,8 @@ error_unreg_trigger: iio_trigger_unregister(trig); error_free_trig: iio_trigger_free(trig); -error_ret: +error_triggered_buffer_cleanup: + iio_triggered_buffer_cleanup(indio_dev); return ret; } EXPORT_SYMBOL(hid_sensor_setup_trigger); diff --git a/drivers/iio/common/hid-sensors/hid-sensor-trigger.h b/drivers/iio/common/hid-sensors/hid-sensor-trigger.h index f47b940ff170..bb45cc89e551 100644 --- a/drivers/iio/common/hid-sensors/hid-sensor-trigger.h +++ b/drivers/iio/common/hid-sensors/hid-sensor-trigger.h @@ -13,7 +13,8 @@ extern const struct dev_pm_ops hid_sensor_pm_ops; int hid_sensor_setup_trigger(struct iio_dev *indio_dev, const char *name, struct hid_sensor_common *attrb); -void hid_sensor_remove_trigger(struct hid_sensor_common *attrb); +void hid_sensor_remove_trigger(struct iio_dev *indio_dev, + struct hid_sensor_common *attrb); int hid_sensor_power_state(struct hid_sensor_common *st, bool state); #endif diff --git a/drivers/iio/common/st_sensors/st_sensors_core.c b/drivers/iio/common/st_sensors/st_sensors_core.c index 13bdfbbf5f71..7a69c1be7393 100644 --- a/drivers/iio/common/st_sensors/st_sensors_core.c +++ b/drivers/iio/common/st_sensors/st_sensors_core.c @@ -20,11 +20,6 @@ #include "st_sensors_core.h" -static inline u32 st_sensors_get_unaligned_le24(const u8 *p) -{ - return (s32)((p[0] | p[1] << 8 | p[2] << 16) << 8) >> 8; -} - int st_sensors_write_data_with_mask(struct iio_dev *indio_dev, u8 reg_addr, u8 mask, u8 data) { @@ -150,8 +145,7 @@ static int st_sensors_set_fullscale(struct iio_dev *indio_dev, unsigned int fs) if (err < 0) goto st_accel_set_fullscale_error; - sdata->current_fullscale = (struct st_sensor_fullscale_avl *) - &sdata->sensor_settings->fs.fs_avl[i]; + sdata->current_fullscale = &sdata->sensor_settings->fs.fs_avl[i]; return err; st_accel_set_fullscale_error: @@ -278,8 +272,7 @@ static int st_sensors_set_drdy_int_pin(struct iio_dev *indio_dev, !sdata->sensor_settings->drdy_irq.int2.addr) { if (pdata->drdy_int_pin) dev_info(&indio_dev->dev, - "DRDY on pin INT%d specified, but sensor " - "does not support interrupts\n", + "DRDY on pin INT%d specified, but sensor does not support interrupts\n", pdata->drdy_int_pin); return 0; } @@ -545,7 +538,7 @@ static int st_sensors_read_axis_data(struct iio_dev *indio_dev, else if (byte_for_channel == 2) *data = (s16)get_unaligned_le16(outdata); else if (byte_for_channel == 3) - *data = (s32)st_sensors_get_unaligned_le24(outdata); + *data = (s32)sign_extend32(get_unaligned_le24(outdata), 23); st_sensors_free_memory: kfree(outdata); diff --git a/drivers/iio/common/st_sensors/st_sensors_i2c.c b/drivers/iio/common/st_sensors/st_sensors_i2c.c index 286830fb5d35..b400560bac93 100644 --- a/drivers/iio/common/st_sensors/st_sensors_i2c.c +++ b/drivers/iio/common/st_sensors/st_sensors_i2c.c @@ -49,8 +49,8 @@ int st_sensors_i2c_configure(struct iio_dev *indio_dev, sdata->regmap = devm_regmap_init_i2c(client, config); if (IS_ERR(sdata->regmap)) { - dev_err(&client->dev, "Failed to register i2c regmap (%d)\n", - (int)PTR_ERR(sdata->regmap)); + dev_err(&client->dev, "Failed to register i2c regmap (%ld)\n", + PTR_ERR(sdata->regmap)); return PTR_ERR(sdata->regmap); } diff --git a/drivers/iio/common/st_sensors/st_sensors_spi.c b/drivers/iio/common/st_sensors/st_sensors_spi.c index 1275fb0eda31..ee70515bb89f 100644 --- a/drivers/iio/common/st_sensors/st_sensors_spi.c +++ b/drivers/iio/common/st_sensors/st_sensors_spi.c @@ -44,7 +44,7 @@ static bool st_sensors_is_spi_3_wire(struct spi_device *spi) if (device_property_read_bool(dev, "spi-3wire")) return true; - pdata = (struct st_sensors_platform_data *)dev->platform_data; + pdata = dev_get_platdata(dev); if (pdata && pdata->spi_3wire) return true; @@ -101,8 +101,8 @@ int st_sensors_spi_configure(struct iio_dev *indio_dev, sdata->regmap = devm_regmap_init_spi(spi, config); if (IS_ERR(sdata->regmap)) { - dev_err(&spi->dev, "Failed to register spi regmap (%d)\n", - (int)PTR_ERR(sdata->regmap)); + dev_err(&spi->dev, "Failed to register spi regmap (%ld)\n", + PTR_ERR(sdata->regmap)); return PTR_ERR(sdata->regmap); } diff --git a/drivers/iio/common/st_sensors/st_sensors_trigger.c b/drivers/iio/common/st_sensors/st_sensors_trigger.c index e817537cdfb5..0507283bd4c1 100644 --- a/drivers/iio/common/st_sensors/st_sensors_trigger.c +++ b/drivers/iio/common/st_sensors/st_sensors_trigger.c @@ -44,8 +44,7 @@ static int st_sensors_new_samples_available(struct iio_dev *indio_dev, sdata->sensor_settings->drdy_irq.stat_drdy.addr, &status); if (ret < 0) { - dev_err(sdata->dev, - "error checking samples available\n"); + dev_err(sdata->dev, "error checking samples available\n"); return ret; } @@ -148,9 +147,7 @@ int st_sensors_allocate_trigger(struct iio_dev *indio_dev, case IRQF_TRIGGER_LOW: if (!sdata->sensor_settings->drdy_irq.addr_ihl) { dev_err(&indio_dev->dev, - "falling/low specified for IRQ " - "but hardware supports only rising/high: " - "will request rising/high\n"); + "falling/low specified for IRQ but hardware supports only rising/high: will request rising/high\n"); if (irq_trig == IRQF_TRIGGER_FALLING) irq_trig = IRQF_TRIGGER_RISING; if (irq_trig == IRQF_TRIGGER_LOW) @@ -163,8 +160,7 @@ int st_sensors_allocate_trigger(struct iio_dev *indio_dev, if (err < 0) goto iio_trigger_free; dev_info(&indio_dev->dev, - "interrupts on the falling edge or " - "active low level\n"); + "interrupts on the falling edge or active low level\n"); } break; case IRQF_TRIGGER_RISING: @@ -178,8 +174,7 @@ int st_sensors_allocate_trigger(struct iio_dev *indio_dev, default: /* This is the most preferred mode, if possible */ dev_err(&indio_dev->dev, - "unsupported IRQ trigger specified (%lx), enforce " - "rising edge\n", irq_trig); + "unsupported IRQ trigger specified (%lx), enforce rising edge\n", irq_trig); irq_trig = IRQF_TRIGGER_RISING; } diff --git a/drivers/iio/dac/Kconfig b/drivers/iio/dac/Kconfig index 93744011b63f..3728f6325501 100644 --- a/drivers/iio/dac/Kconfig +++ b/drivers/iio/dac/Kconfig @@ -279,12 +279,12 @@ config LTC1660 module will be called ltc1660. config LTC2632 - tristate "Linear Technology LTC2632-12/10/8 and LTC2636-12/10/8 DAC spi driver" + tristate "Linear Technology LTC2632-12/10/8 and similar DAC spi driver" depends on SPI help Say yes here to build support for Linear Technology - LTC2632-12, LTC2632-10, LTC2632-8, LTC2636-12, LTC2636-10 and - LTC2636-8 converters (DAC). + LTC2632, LTC2634 and LTC2636 DAC resolution 12/10/8 bit + low 0-2.5V and high 0-4.096V range converters. To compile this driver as a module, choose M here: the module will be called ltc2632. diff --git a/drivers/iio/dac/ad5360.c b/drivers/iio/dac/ad5360.c index 2ac428b957e3..3e0c9e84e8da 100644 --- a/drivers/iio/dac/ad5360.c +++ b/drivers/iio/dac/ad5360.c @@ -67,6 +67,7 @@ struct ad5360_chip_info { * @chip_info: chip model specific constants, available modes etc * @vref_reg: vref supply regulators * @ctrl: control register cache + * @lock lock to protect the data buffer during SPI ops * @data: spi transfer buffers */ @@ -75,6 +76,7 @@ struct ad5360_state { const struct ad5360_chip_info *chip_info; struct regulator_bulk_data vref_reg[3]; unsigned int ctrl; + struct mutex lock; /* * DMA (thus cache coherency maintenance) requires the @@ -205,10 +207,11 @@ static int ad5360_write(struct iio_dev *indio_dev, unsigned int cmd, unsigned int addr, unsigned int val, unsigned int shift) { int ret; + struct ad5360_state *st = iio_priv(indio_dev); - mutex_lock(&indio_dev->mlock); + mutex_lock(&st->lock); ret = ad5360_write_unlocked(indio_dev, cmd, addr, val, shift); - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); return ret; } @@ -229,7 +232,7 @@ static int ad5360_read(struct iio_dev *indio_dev, unsigned int type, }, }; - mutex_lock(&indio_dev->mlock); + mutex_lock(&st->lock); st->data[0].d32 = cpu_to_be32(AD5360_CMD(AD5360_CMD_SPECIAL_FUNCTION) | AD5360_ADDR(AD5360_REG_SF_READBACK) | @@ -240,7 +243,7 @@ static int ad5360_read(struct iio_dev *indio_dev, unsigned int type, if (ret >= 0) ret = be32_to_cpu(st->data[1].d32) & 0xffff; - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); return ret; } @@ -261,7 +264,7 @@ static int ad5360_update_ctrl(struct iio_dev *indio_dev, unsigned int set, struct ad5360_state *st = iio_priv(indio_dev); unsigned int ret; - mutex_lock(&indio_dev->mlock); + mutex_lock(&st->lock); st->ctrl |= set; st->ctrl &= ~clr; @@ -269,7 +272,7 @@ static int ad5360_update_ctrl(struct iio_dev *indio_dev, unsigned int set, ret = ad5360_write_unlocked(indio_dev, AD5360_CMD_SPECIAL_FUNCTION, AD5360_REG_SF_CTRL, st->ctrl, 0); - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); return ret; } @@ -479,6 +482,8 @@ static int ad5360_probe(struct spi_device *spi) indio_dev->modes = INDIO_DIRECT_MODE; indio_dev->num_channels = st->chip_info->num_channels; + mutex_init(&st->lock); + ret = ad5360_alloc_channels(indio_dev); if (ret) { dev_err(&spi->dev, "Failed to allocate channel spec: %d\n", ret); diff --git a/drivers/iio/dac/ad5380.c b/drivers/iio/dac/ad5380.c index 2ebe08326048..b37e5675f716 100644 --- a/drivers/iio/dac/ad5380.c +++ b/drivers/iio/dac/ad5380.c @@ -51,6 +51,7 @@ struct ad5380_chip_info { * @vref_reg: vref supply regulator * @vref: actual reference voltage used in uA * @pwr_down: whether the chip is currently in power down mode + * @lock lock to protect the data buffer during regmap ops */ struct ad5380_state { @@ -59,6 +60,7 @@ struct ad5380_state { struct regulator *vref_reg; int vref; bool pwr_down; + struct mutex lock; }; enum ad5380_type { @@ -98,7 +100,7 @@ static ssize_t ad5380_write_dac_powerdown(struct iio_dev *indio_dev, if (ret) return ret; - mutex_lock(&indio_dev->mlock); + mutex_lock(&st->lock); if (pwr_down) ret = regmap_write(st->regmap, AD5380_REG_SF_PWR_DOWN, 0); @@ -107,7 +109,7 @@ static ssize_t ad5380_write_dac_powerdown(struct iio_dev *indio_dev, st->pwr_down = pwr_down; - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); return ret ? ret : len; } @@ -390,6 +392,8 @@ static int ad5380_probe(struct device *dev, struct regmap *regmap, indio_dev->modes = INDIO_DIRECT_MODE; indio_dev->num_channels = st->chip_info->num_channels; + mutex_init(&st->lock); + ret = ad5380_alloc_channels(indio_dev); if (ret) { dev_err(dev, "Failed to allocate channel spec: %d\n", ret); diff --git a/drivers/iio/dac/ad5421.c b/drivers/iio/dac/ad5421.c index 63063e85cd0a..fec27764cea8 100644 --- a/drivers/iio/dac/ad5421.c +++ b/drivers/iio/dac/ad5421.c @@ -62,12 +62,14 @@ * @current_range: current range which the device is configured for * @data: spi transfer buffers * @fault_mask: software masking of events + * @lock lock to protect the data buffer during SPI ops */ struct ad5421_state { struct spi_device *spi; unsigned int ctrl; enum ad5421_current_range current_range; unsigned int fault_mask; + struct mutex lock; /* * DMA (thus cache coherency maintenance) requires the @@ -142,11 +144,12 @@ static int ad5421_write_unlocked(struct iio_dev *indio_dev, static int ad5421_write(struct iio_dev *indio_dev, unsigned int reg, unsigned int val) { + struct ad5421_state *st = iio_priv(indio_dev); int ret; - mutex_lock(&indio_dev->mlock); + mutex_lock(&st->lock); ret = ad5421_write_unlocked(indio_dev, reg, val); - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); return ret; } @@ -166,7 +169,7 @@ static int ad5421_read(struct iio_dev *indio_dev, unsigned int reg) }, }; - mutex_lock(&indio_dev->mlock); + mutex_lock(&st->lock); st->data[0].d32 = cpu_to_be32((1 << 23) | (reg << 16)); @@ -174,7 +177,7 @@ static int ad5421_read(struct iio_dev *indio_dev, unsigned int reg) if (ret >= 0) ret = be32_to_cpu(st->data[1].d32) & 0xffff; - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); return ret; } @@ -185,14 +188,14 @@ static int ad5421_update_ctrl(struct iio_dev *indio_dev, unsigned int set, struct ad5421_state *st = iio_priv(indio_dev); unsigned int ret; - mutex_lock(&indio_dev->mlock); + mutex_lock(&st->lock); st->ctrl &= ~clr; st->ctrl |= set; ret = ad5421_write_unlocked(indio_dev, AD5421_REG_CTRL, st->ctrl); - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); return ret; } @@ -400,12 +403,12 @@ static int ad5421_write_event_config(struct iio_dev *indio_dev, return -EINVAL; } - mutex_lock(&indio_dev->mlock); + mutex_lock(&st->lock); if (state) st->fault_mask |= mask; else st->fault_mask &= ~mask; - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); return 0; } @@ -491,6 +494,8 @@ static int ad5421_probe(struct spi_device *spi) indio_dev->channels = ad5421_channels; indio_dev->num_channels = ARRAY_SIZE(ad5421_channels); + mutex_init(&st->lock); + st->ctrl = AD5421_CTRL_WATCHDOG_DISABLE | AD5421_CTRL_AUTO_FAULT_READBACK; diff --git a/drivers/iio/dac/ad5446.c b/drivers/iio/dac/ad5446.c index 61c670f7fc5f..8f8afc8999bc 100644 --- a/drivers/iio/dac/ad5446.c +++ b/drivers/iio/dac/ad5446.c @@ -21,6 +21,8 @@ #include #include +#include + #define MODE_PWRDWN_1k 0x1 #define MODE_PWRDWN_100k 0x2 #define MODE_PWRDWN_TRISTATE 0x3 @@ -31,6 +33,7 @@ * @chip_info: chip model specific constants, available modes etc * @reg: supply regulator * @vref_mv: actual reference voltage used + * @lock lock to protect the data buffer during write ops */ struct ad5446_state { @@ -41,6 +44,7 @@ struct ad5446_state { unsigned cached_val; unsigned pwr_down_mode; unsigned pwr_down; + struct mutex lock; }; /** @@ -110,7 +114,7 @@ static ssize_t ad5446_write_dac_powerdown(struct iio_dev *indio_dev, if (ret) return ret; - mutex_lock(&indio_dev->mlock); + mutex_lock(&st->lock); st->pwr_down = powerdown; if (st->pwr_down) { @@ -121,7 +125,7 @@ static ssize_t ad5446_write_dac_powerdown(struct iio_dev *indio_dev, } ret = st->chip_info->write(st, val); - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); return ret ? ret : len; } @@ -195,11 +199,11 @@ static int ad5446_write_raw(struct iio_dev *indio_dev, return -EINVAL; val <<= chan->scan_type.shift; - mutex_lock(&indio_dev->mlock); + mutex_lock(&st->lock); st->cached_val = val; if (!st->pwr_down) ret = st->chip_info->write(st, val); - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); break; default: ret = -EINVAL; @@ -254,6 +258,8 @@ static int ad5446_probe(struct device *dev, const char *name, indio_dev->channels = &st->chip_info->channel; indio_dev->num_channels = 1; + mutex_init(&st->lock); + st->pwr_down_mode = MODE_PWRDWN_1k; if (st->chip_info->int_vref_mv) @@ -302,9 +308,7 @@ static int ad5660_write(struct ad5446_state *st, unsigned val) struct spi_device *spi = to_spi_device(st->dev); uint8_t data[3]; - data[0] = (val >> 16) & 0xFF; - data[1] = (val >> 8) & 0xFF; - data[2] = val & 0xFF; + put_unaligned_be24(val, &data[0]); return spi_write(spi, data, sizeof(data)); } diff --git a/drivers/iio/dac/ad5449.c b/drivers/iio/dac/ad5449.c index fed3ebaccac4..d739b10e5236 100644 --- a/drivers/iio/dac/ad5449.c +++ b/drivers/iio/dac/ad5449.c @@ -56,11 +56,13 @@ struct ad5449_chip_info { * @has_sdo: whether the SDO line is connected * @dac_cache: Cache for the DAC values * @data: spi transfer buffers + * @lock lock to protect the data buffer during SPI ops */ struct ad5449 { struct spi_device *spi; const struct ad5449_chip_info *chip_info; struct regulator_bulk_data vref_reg[AD5449_MAX_VREFS]; + struct mutex lock; bool has_sdo; uint16_t dac_cache[AD5449_MAX_CHANNELS]; @@ -87,10 +89,10 @@ static int ad5449_write(struct iio_dev *indio_dev, unsigned int addr, struct ad5449 *st = iio_priv(indio_dev); int ret; - mutex_lock(&indio_dev->mlock); + mutex_lock(&st->lock); st->data[0] = cpu_to_be16((addr << 12) | val); ret = spi_write(st->spi, st->data, 2); - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); return ret; } @@ -112,7 +114,7 @@ static int ad5449_read(struct iio_dev *indio_dev, unsigned int addr, }, }; - mutex_lock(&indio_dev->mlock); + mutex_lock(&st->lock); st->data[0] = cpu_to_be16(addr << 12); st->data[1] = cpu_to_be16(AD5449_CMD_NOOP); @@ -123,7 +125,7 @@ static int ad5449_read(struct iio_dev *indio_dev, unsigned int addr, *val = be16_to_cpu(st->data[1]); out_unlock: - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); return ret; } @@ -302,6 +304,8 @@ static int ad5449_spi_probe(struct spi_device *spi) indio_dev->channels = st->chip_info->channels; indio_dev->num_channels = st->chip_info->num_channels; + mutex_init(&st->lock); + if (st->chip_info->has_ctrl) { unsigned int ctrl = 0x00; if (pdata) { diff --git a/drivers/iio/dac/ad5592r-base.c b/drivers/iio/dac/ad5592r-base.c index e2110113e884..410e90e5f75f 100644 --- a/drivers/iio/dac/ad5592r-base.c +++ b/drivers/iio/dac/ad5592r-base.c @@ -156,7 +156,6 @@ static void ad5592r_gpio_cleanup(struct ad5592r_state *st) static int ad5592r_reset(struct ad5592r_state *st) { struct gpio_desc *gpio; - struct iio_dev *iio_dev = iio_priv_to_dev(st); gpio = devm_gpiod_get_optional(st->dev, "reset", GPIOD_OUT_LOW); if (IS_ERR(gpio)) @@ -166,10 +165,10 @@ static int ad5592r_reset(struct ad5592r_state *st) udelay(1); gpiod_set_value(gpio, 1); } else { - mutex_lock(&iio_dev->mlock); + mutex_lock(&st->lock); /* Writing this magic value resets the device */ st->ops->reg_write(st, AD5592R_REG_RESET, 0xdac); - mutex_unlock(&iio_dev->mlock); + mutex_unlock(&st->lock); } udelay(250); @@ -197,7 +196,6 @@ static int ad5592r_set_channel_modes(struct ad5592r_state *st) const struct ad5592r_rw_ops *ops = st->ops; int ret; unsigned i; - struct iio_dev *iio_dev = iio_priv_to_dev(st); u8 pulldown = 0, tristate = 0, dac = 0, adc = 0; u16 read_back; @@ -247,7 +245,7 @@ static int ad5592r_set_channel_modes(struct ad5592r_state *st) } } - mutex_lock(&iio_dev->mlock); + mutex_lock(&st->lock); /* Pull down unused pins to GND */ ret = ops->reg_write(st, AD5592R_REG_PULLDOWN, pulldown); @@ -285,7 +283,7 @@ static int ad5592r_set_channel_modes(struct ad5592r_state *st) ret = -EIO; err_unlock: - mutex_unlock(&iio_dev->mlock); + mutex_unlock(&st->lock); return ret; } @@ -314,11 +312,11 @@ static int ad5592r_write_raw(struct iio_dev *iio_dev, if (!chan->output) return -EINVAL; - mutex_lock(&iio_dev->mlock); + mutex_lock(&st->lock); ret = st->ops->write_dac(st, chan->channel, val); if (!ret) st->cached_dac[chan->channel] = val; - mutex_unlock(&iio_dev->mlock); + mutex_unlock(&st->lock); return ret; case IIO_CHAN_INFO_SCALE: if (chan->type == IIO_VOLTAGE) { @@ -333,12 +331,12 @@ static int ad5592r_write_raw(struct iio_dev *iio_dev, else return -EINVAL; - mutex_lock(&iio_dev->mlock); + mutex_lock(&st->lock); ret = st->ops->reg_read(st, AD5592R_REG_CTRL, &st->cached_gp_ctrl); if (ret < 0) { - mutex_unlock(&iio_dev->mlock); + mutex_unlock(&st->lock); return ret; } @@ -360,7 +358,7 @@ static int ad5592r_write_raw(struct iio_dev *iio_dev, ret = st->ops->reg_write(st, AD5592R_REG_CTRL, st->cached_gp_ctrl); - mutex_unlock(&iio_dev->mlock); + mutex_unlock(&st->lock); return ret; } @@ -382,7 +380,7 @@ static int ad5592r_read_raw(struct iio_dev *iio_dev, switch (m) { case IIO_CHAN_INFO_RAW: - mutex_lock(&iio_dev->mlock); + mutex_lock(&st->lock); if (!chan->output) { ret = st->ops->read_adc(st, chan->channel, &read_val); @@ -419,7 +417,7 @@ static int ad5592r_read_raw(struct iio_dev *iio_dev, } else { int mult; - mutex_lock(&iio_dev->mlock); + mutex_lock(&st->lock); if (chan->output) mult = !!(st->cached_gp_ctrl & @@ -437,7 +435,7 @@ static int ad5592r_read_raw(struct iio_dev *iio_dev, case IIO_CHAN_INFO_OFFSET: ret = ad5592r_get_vref(st); - mutex_lock(&iio_dev->mlock); + mutex_lock(&st->lock); if (st->cached_gp_ctrl & AD5592R_REG_CTRL_ADC_RANGE) *val = (-34365 * 25) / ret; @@ -450,7 +448,7 @@ static int ad5592r_read_raw(struct iio_dev *iio_dev, } unlock: - mutex_unlock(&iio_dev->mlock); + mutex_unlock(&st->lock); return ret; } @@ -625,6 +623,8 @@ int ad5592r_probe(struct device *dev, const char *name, iio_dev->info = &ad5592r_info; iio_dev->modes = INDIO_DIRECT_MODE; + mutex_init(&st->lock); + ad5592r_init_scales(st, ad5592r_get_vref(st)); ret = ad5592r_reset(st); diff --git a/drivers/iio/dac/ad5592r-base.h b/drivers/iio/dac/ad5592r-base.h index 4774e4cd9c11..23dac2f1ff8a 100644 --- a/drivers/iio/dac/ad5592r-base.h +++ b/drivers/iio/dac/ad5592r-base.h @@ -52,6 +52,7 @@ struct ad5592r_state { struct regulator *reg; struct gpio_chip gpiochip; struct mutex gpio_lock; /* Protect cached gpio_out, gpio_val, etc. */ + struct mutex lock; unsigned int num_channels; const struct ad5592r_rw_ops *ops; int scale_avail[2][2]; diff --git a/drivers/iio/dac/ad5592r.c b/drivers/iio/dac/ad5592r.c index 34ba059a77da..49308ad13c4b 100644 --- a/drivers/iio/dac/ad5592r.c +++ b/drivers/iio/dac/ad5592r.c @@ -98,7 +98,7 @@ static int ad5592r_reg_read(struct ad5592r_state *st, u8 reg, u16 *value) return 0; } -static int ad5593r_gpio_read(struct ad5592r_state *st, u8 *value) +static int ad5592r_gpio_read(struct ad5592r_state *st, u8 *value) { int ret; @@ -121,7 +121,7 @@ static const struct ad5592r_rw_ops ad5592r_rw_ops = { .read_adc = ad5592r_read_adc, .reg_write = ad5592r_reg_write, .reg_read = ad5592r_reg_read, - .gpio_read = ad5593r_gpio_read, + .gpio_read = ad5592r_gpio_read, }; static int ad5592r_spi_probe(struct spi_device *spi) diff --git a/drivers/iio/dac/ad5593r.c b/drivers/iio/dac/ad5593r.c index 44ea3b8117d0..1fbe9c019c7f 100644 --- a/drivers/iio/dac/ad5593r.c +++ b/drivers/iio/dac/ad5593r.c @@ -134,5 +134,5 @@ static struct i2c_driver ad5593r_driver = { module_i2c_driver(ad5593r_driver); MODULE_AUTHOR("Paul Cercueil "); -MODULE_DESCRIPTION("Analog Devices AD5592R multi-channel converters"); +MODULE_DESCRIPTION("Analog Devices AD5593R multi-channel converters"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/iio/dac/ad5624r_spi.c b/drivers/iio/dac/ad5624r_spi.c index e6c022e1dc1c..2015a5df840c 100644 --- a/drivers/iio/dac/ad5624r_spi.c +++ b/drivers/iio/dac/ad5624r_spi.c @@ -18,6 +18,8 @@ #include #include +#include + #include "ad5624r.h" static int ad5624r_spi_write(struct spi_device *spi, @@ -35,11 +37,9 @@ static int ad5624r_spi_write(struct spi_device *spi, * for the AD5664R, AD5644R, and AD5624R, respectively. */ data = (0 << 22) | (cmd << 19) | (addr << 16) | (val << shift); - msg[0] = data >> 16; - msg[1] = data >> 8; - msg[2] = data; + put_unaligned_be24(data, &msg[0]); - return spi_write(spi, msg, 3); + return spi_write(spi, msg, sizeof(msg)); } static int ad5624r_read_raw(struct iio_dev *indio_dev, diff --git a/drivers/iio/dac/ad5686.c b/drivers/iio/dac/ad5686.c index e06b29c565b9..8dd67da0a7da 100644 --- a/drivers/iio/dac/ad5686.c +++ b/drivers/iio/dac/ad5686.c @@ -127,9 +127,9 @@ static int ad5686_read_raw(struct iio_dev *indio_dev, switch (m) { case IIO_CHAN_INFO_RAW: - mutex_lock(&indio_dev->mlock); + mutex_lock(&st->lock); ret = st->read(st, chan->address); - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); if (ret < 0) return ret; *val = (ret >> chan->scan_type.shift) & @@ -157,12 +157,12 @@ static int ad5686_write_raw(struct iio_dev *indio_dev, if (val > (1 << chan->scan_type.realbits) || val < 0) return -EINVAL; - mutex_lock(&indio_dev->mlock); + mutex_lock(&st->lock); ret = st->write(st, AD5686_CMD_WRITE_INPUT_N_UPDATE_N, chan->address, val << chan->scan_type.shift); - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); break; default: ret = -EINVAL; @@ -468,6 +468,8 @@ int ad5686_probe(struct device *dev, indio_dev->channels = st->chip_info->channels; indio_dev->num_channels = st->chip_info->num_channels; + mutex_init(&st->lock); + switch (st->chip_info->regmap_type) { case AD5310_REGMAP: cmd = AD5686_CMD_CONTROL_REG; diff --git a/drivers/iio/dac/ad5686.h b/drivers/iio/dac/ad5686.h index 70a779939ddb..52009b5eef88 100644 --- a/drivers/iio/dac/ad5686.h +++ b/drivers/iio/dac/ad5686.h @@ -117,6 +117,7 @@ struct ad5686_chip_info { * @pwr_down_mask: power down mask * @pwr_down_mode: current power down mode * @use_internal_vref: set to true if the internal reference voltage is used + * @lock lock to protect the data buffer during regmap ops * @data: spi transfer buffers */ @@ -130,6 +131,7 @@ struct ad5686_state { ad5686_write_func write; ad5686_read_func read; bool use_internal_vref; + struct mutex lock; /* * DMA (thus cache coherency maintenance) requires the diff --git a/drivers/iio/dac/ad5755.c b/drivers/iio/dac/ad5755.c index 388ddd14bfd0..7723bd313fc6 100644 --- a/drivers/iio/dac/ad5755.c +++ b/drivers/iio/dac/ad5755.c @@ -82,6 +82,7 @@ struct ad5755_chip_info { * @pwr_down: bitmask which contains hether a channel is powered down or not * @ctrl: software shadow of the channel ctrl registers * @channels: iio channel spec for the device + * @lock lock to protect the data buffer during SPI ops * @data: spi transfer buffers */ struct ad5755_state { @@ -90,6 +91,7 @@ struct ad5755_state { unsigned int pwr_down; unsigned int ctrl[AD5755_NUM_CHANNELS]; struct iio_chan_spec channels[AD5755_NUM_CHANNELS]; + struct mutex lock; /* * DMA (thus cache coherency maintenance) requires the @@ -174,11 +176,12 @@ static int ad5755_write_ctrl_unlocked(struct iio_dev *indio_dev, static int ad5755_write(struct iio_dev *indio_dev, unsigned int reg, unsigned int val) { + struct ad5755_state *st = iio_priv(indio_dev); int ret; - mutex_lock(&indio_dev->mlock); + mutex_lock(&st->lock); ret = ad5755_write_unlocked(indio_dev, reg, val); - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); return ret; } @@ -186,11 +189,12 @@ static int ad5755_write(struct iio_dev *indio_dev, unsigned int reg, static int ad5755_write_ctrl(struct iio_dev *indio_dev, unsigned int channel, unsigned int reg, unsigned int val) { + struct ad5755_state *st = iio_priv(indio_dev); int ret; - mutex_lock(&indio_dev->mlock); + mutex_lock(&st->lock); ret = ad5755_write_ctrl_unlocked(indio_dev, channel, reg, val); - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); return ret; } @@ -211,7 +215,7 @@ static int ad5755_read(struct iio_dev *indio_dev, unsigned int addr) }, }; - mutex_lock(&indio_dev->mlock); + mutex_lock(&st->lock); st->data[0].d32 = cpu_to_be32(AD5755_READ_FLAG | (addr << 16)); st->data[1].d32 = cpu_to_be32(AD5755_NOOP); @@ -220,7 +224,7 @@ static int ad5755_read(struct iio_dev *indio_dev, unsigned int addr) if (ret >= 0) ret = be32_to_cpu(st->data[1].d32) & 0xffff; - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); return ret; } @@ -246,7 +250,7 @@ static int ad5755_set_channel_pwr_down(struct iio_dev *indio_dev, struct ad5755_state *st = iio_priv(indio_dev); unsigned int mask = BIT(channel); - mutex_lock(&indio_dev->mlock); + mutex_lock(&st->lock); if ((bool)(st->pwr_down & mask) == pwr_down) goto out_unlock; @@ -266,7 +270,7 @@ static int ad5755_set_channel_pwr_down(struct iio_dev *indio_dev, } out_unlock: - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); return 0; } @@ -746,6 +750,8 @@ static int ad5755_probe(struct spi_device *spi) indio_dev->modes = INDIO_DIRECT_MODE; indio_dev->num_channels = AD5755_NUM_CHANNELS; + mutex_init(&st->lock); + if (spi->dev.of_node) pdata = ad5755_parse_dt(&spi->dev); else diff --git a/drivers/iio/dac/ad5761.c b/drivers/iio/dac/ad5761.c index 7468fbd11684..67c4fa75c6f1 100644 --- a/drivers/iio/dac/ad5761.c +++ b/drivers/iio/dac/ad5761.c @@ -57,11 +57,13 @@ enum ad5761_supported_device_ids { * @use_intref: true when the internal voltage reference is used * @vref: actual voltage reference in mVolts * @range: output range mode used + * @lock lock to protect the data buffer during SPI ops * @data: cache aligned spi buffer */ struct ad5761_state { struct spi_device *spi; struct regulator *vref_reg; + struct mutex lock; bool use_intref; int vref; @@ -124,9 +126,9 @@ static int ad5761_spi_write(struct iio_dev *indio_dev, u8 addr, u16 val) struct ad5761_state *st = iio_priv(indio_dev); int ret; - mutex_lock(&indio_dev->mlock); + mutex_lock(&st->lock); ret = _ad5761_spi_write(st, addr, val); - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); return ret; } @@ -163,9 +165,9 @@ static int ad5761_spi_read(struct iio_dev *indio_dev, u8 addr, u16 *val) struct ad5761_state *st = iio_priv(indio_dev); int ret; - mutex_lock(&indio_dev->mlock); + mutex_lock(&st->lock); ret = _ad5761_spi_read(st, addr, val); - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); return ret; } @@ -368,6 +370,8 @@ static int ad5761_probe(struct spi_device *spi) if (pdata) voltage_range = pdata->voltage_range; + mutex_init(&st->lock); + ret = ad5761_spi_set_range(st, voltage_range); if (ret) goto disable_regulator_err; diff --git a/drivers/iio/dac/ad5764.c b/drivers/iio/dac/ad5764.c index f7ab211604a1..5b0f0fe354f6 100644 --- a/drivers/iio/dac/ad5764.c +++ b/drivers/iio/dac/ad5764.c @@ -46,6 +46,7 @@ struct ad5764_chip_info { * @spi: spi_device * @chip_info: chip info * @vref_reg: vref supply regulators + * @lock lock to protect the data buffer during SPI ops * @data: spi transfer buffers */ @@ -53,6 +54,7 @@ struct ad5764_state { struct spi_device *spi; const struct ad5764_chip_info *chip_info; struct regulator_bulk_data vref_reg[2]; + struct mutex lock; /* * DMA (thus cache coherency maintenance) requires the @@ -126,11 +128,11 @@ static int ad5764_write(struct iio_dev *indio_dev, unsigned int reg, struct ad5764_state *st = iio_priv(indio_dev); int ret; - mutex_lock(&indio_dev->mlock); + mutex_lock(&st->lock); st->data[0].d32 = cpu_to_be32((reg << 16) | val); ret = spi_write(st->spi, &st->data[0].d8[1], 3); - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); return ret; } @@ -151,7 +153,7 @@ static int ad5764_read(struct iio_dev *indio_dev, unsigned int reg, }, }; - mutex_lock(&indio_dev->mlock); + mutex_lock(&st->lock); st->data[0].d32 = cpu_to_be32((1 << 23) | (reg << 16)); @@ -159,7 +161,7 @@ static int ad5764_read(struct iio_dev *indio_dev, unsigned int reg, if (ret >= 0) *val = be32_to_cpu(st->data[1].d32) & 0xffff; - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); return ret; } @@ -295,6 +297,8 @@ static int ad5764_probe(struct spi_device *spi) indio_dev->num_channels = AD5764_NUM_CHANNELS; indio_dev->channels = st->chip_info->channels; + mutex_init(&st->lock); + if (st->chip_info->int_vref == 0) { st->vref_reg[0].supply = "vrefAB"; st->vref_reg[1].supply = "vrefCD"; diff --git a/drivers/iio/dac/ltc2632.c b/drivers/iio/dac/ltc2632.c index 7adc91056aa1..f891311f05cf 100644 --- a/drivers/iio/dac/ltc2632.c +++ b/drivers/iio/dac/ltc2632.c @@ -12,6 +12,8 @@ #include #include +#include + #define LTC2632_CMD_WRITE_INPUT_N 0x0 #define LTC2632_CMD_UPDATE_DAC_N 0x1 #define LTC2632_CMD_WRITE_INPUT_N_UPDATE_ALL 0x2 @@ -24,6 +26,7 @@ /** * struct ltc2632_chip_info - chip specific information * @channels: channel spec for the DAC + * @num_channels: DAC channel count of the chip * @vref_mv: internal reference voltage */ struct ltc2632_chip_info { @@ -53,6 +56,12 @@ enum ltc2632_supported_device_ids { ID_LTC2632H12, ID_LTC2632H10, ID_LTC2632H8, + ID_LTC2634L12, + ID_LTC2634L10, + ID_LTC2634L8, + ID_LTC2634H12, + ID_LTC2634H10, + ID_LTC2634H8, ID_LTC2636L12, ID_LTC2636L10, ID_LTC2636L8, @@ -75,9 +84,7 @@ static int ltc2632_spi_write(struct spi_device *spi, * 10-, 8-bit input code followed by 4, 6, or 8 don't care bits. */ data = (cmd << 20) | (addr << 16) | (val << shift); - msg[0] = data >> 16; - msg[1] = data >> 8; - msg[2] = data; + put_unaligned_be24(data, &msg[0]); return spi_write(spi, msg, sizeof(msg)); } @@ -235,6 +242,36 @@ static const struct ltc2632_chip_info ltc2632_chip_info_tbl[] = { .num_channels = 2, .vref_mv = 4096, }, + [ID_LTC2634L12] = { + .channels = ltc2632x12_channels, + .num_channels = 4, + .vref_mv = 2500, + }, + [ID_LTC2634L10] = { + .channels = ltc2632x10_channels, + .num_channels = 4, + .vref_mv = 2500, + }, + [ID_LTC2634L8] = { + .channels = ltc2632x8_channels, + .num_channels = 4, + .vref_mv = 2500, + }, + [ID_LTC2634H12] = { + .channels = ltc2632x12_channels, + .num_channels = 4, + .vref_mv = 4096, + }, + [ID_LTC2634H10] = { + .channels = ltc2632x10_channels, + .num_channels = 4, + .vref_mv = 4096, + }, + [ID_LTC2634H8] = { + .channels = ltc2632x8_channels, + .num_channels = 4, + .vref_mv = 4096, + }, [ID_LTC2636L12] = { .channels = ltc2632x12_channels, .num_channels = 8, @@ -356,6 +393,12 @@ static const struct spi_device_id ltc2632_id[] = { { "ltc2632-h12", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2632H12] }, { "ltc2632-h10", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2632H10] }, { "ltc2632-h8", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2632H8] }, + { "ltc2634-l12", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2634L12] }, + { "ltc2634-l10", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2634L10] }, + { "ltc2634-l8", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2634L8] }, + { "ltc2634-h12", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2634H12] }, + { "ltc2634-h10", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2634H10] }, + { "ltc2634-h8", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2634H8] }, { "ltc2636-l12", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2636L12] }, { "ltc2636-l10", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2636L10] }, { "ltc2636-l8", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2636L8] }, @@ -385,6 +428,24 @@ static const struct of_device_id ltc2632_of_match[] = { }, { .compatible = "lltc,ltc2632-h8", .data = <c2632_chip_info_tbl[ID_LTC2632H8] + }, { + .compatible = "lltc,ltc2634-l12", + .data = <c2632_chip_info_tbl[ID_LTC2634L12] + }, { + .compatible = "lltc,ltc2634-l10", + .data = <c2632_chip_info_tbl[ID_LTC2634L10] + }, { + .compatible = "lltc,ltc2634-l8", + .data = <c2632_chip_info_tbl[ID_LTC2634L8] + }, { + .compatible = "lltc,ltc2634-h12", + .data = <c2632_chip_info_tbl[ID_LTC2634H12] + }, { + .compatible = "lltc,ltc2634-h10", + .data = <c2632_chip_info_tbl[ID_LTC2634H10] + }, { + .compatible = "lltc,ltc2634-h8", + .data = <c2632_chip_info_tbl[ID_LTC2634H8] }, { .compatible = "lltc,ltc2636-l12", .data = <c2632_chip_info_tbl[ID_LTC2636L12] diff --git a/drivers/iio/dac/vf610_dac.c b/drivers/iio/dac/vf610_dac.c index 7f1e9317c3f3..9417a4a3e22a 100644 --- a/drivers/iio/dac/vf610_dac.c +++ b/drivers/iio/dac/vf610_dac.c @@ -36,6 +36,7 @@ struct vf610_dac { struct device *dev; enum vf610_conversion_mode_sel conv_mode; void __iomem *regs; + struct mutex lock; }; static void vf610_dac_init(struct vf610_dac *info) @@ -64,7 +65,7 @@ static int vf610_set_conversion_mode(struct iio_dev *indio_dev, struct vf610_dac *info = iio_priv(indio_dev); int val; - mutex_lock(&indio_dev->mlock); + mutex_lock(&info->lock); info->conv_mode = mode; val = readl(info->regs + VF610_DACx_STATCTRL); if (mode) @@ -72,7 +73,7 @@ static int vf610_set_conversion_mode(struct iio_dev *indio_dev, else val &= ~VF610_DAC_LPEN; writel(val, info->regs + VF610_DACx_STATCTRL); - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&info->lock); return 0; } @@ -147,9 +148,9 @@ static int vf610_write_raw(struct iio_dev *indio_dev, switch (mask) { case IIO_CHAN_INFO_RAW: - mutex_lock(&indio_dev->mlock); + mutex_lock(&info->lock); writel(VF610_DAC_DAT0(val), info->regs); - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&info->lock); return 0; default: @@ -205,6 +206,8 @@ static int vf610_dac_probe(struct platform_device *pdev) indio_dev->channels = vf610_dac_iio_channels; indio_dev->num_channels = ARRAY_SIZE(vf610_dac_iio_channels); + mutex_init(&info->lock); + ret = clk_prepare_enable(info->clk); if (ret) { dev_err(&pdev->dev, diff --git a/drivers/iio/gyro/Kconfig b/drivers/iio/gyro/Kconfig index 7eaf77707b0b..6daeddf37f60 100644 --- a/drivers/iio/gyro/Kconfig +++ b/drivers/iio/gyro/Kconfig @@ -61,7 +61,7 @@ config BMG160 help Say yes here to build support for BOSCH BMG160 Tri-axis Gyro Sensor driver connected via I2C or SPI. This driver also supports BMI055 - gyroscope. + and BMI088 gyroscope. This driver can also be built as a module. If so, the module will be called bmg160_i2c or bmg160_spi. diff --git a/drivers/iio/gyro/adis16130.c b/drivers/iio/gyro/adis16130.c index 79e63c8a2ea8..2a9ec08ec561 100644 --- a/drivers/iio/gyro/adis16130.c +++ b/drivers/iio/gyro/adis16130.c @@ -12,6 +12,8 @@ #include +#include + #define ADIS16130_CON 0x0 #define ADIS16130_CON_RD (1 << 6) #define ADIS16130_IOP 0x1 @@ -59,7 +61,7 @@ static int adis16130_spi_read(struct iio_dev *indio_dev, u8 reg_addr, u32 *val) ret = spi_sync_transfer(st->us, &xfer, 1); if (ret == 0) - *val = (st->buf[1] << 16) | (st->buf[2] << 8) | st->buf[3]; + *val = get_unaligned_be24(&st->buf[1]); mutex_unlock(&st->buf_lock); return ret; diff --git a/drivers/iio/gyro/adis16136.c b/drivers/iio/gyro/adis16136.c index a4c967a5fc5c..afdc57af475d 100644 --- a/drivers/iio/gyro/adis16136.c +++ b/drivers/iio/gyro/adis16136.c @@ -148,16 +148,14 @@ DEFINE_DEBUGFS_ATTRIBUTE(adis16136_flash_count_fops, static int adis16136_debugfs_init(struct iio_dev *indio_dev) { struct adis16136 *adis16136 = iio_priv(indio_dev); + struct dentry *d = iio_get_debugfs_dentry(indio_dev); debugfs_create_file_unsafe("serial_number", 0400, - indio_dev->debugfs_dentry, adis16136, - &adis16136_serial_fops); + d, adis16136, &adis16136_serial_fops); debugfs_create_file_unsafe("product_id", 0400, - indio_dev->debugfs_dentry, - adis16136, &adis16136_product_id_fops); + d, adis16136, &adis16136_product_id_fops); debugfs_create_file_unsafe("flash_count", 0400, - indio_dev->debugfs_dentry, - adis16136, &adis16136_flash_count_fops); + d, adis16136, &adis16136_flash_count_fops); return 0; } diff --git a/drivers/iio/gyro/bmg160_i2c.c b/drivers/iio/gyro/bmg160_i2c.c index 4fc9c6a3321f..b3fa46bd02cb 100644 --- a/drivers/iio/gyro/bmg160_i2c.c +++ b/drivers/iio/gyro/bmg160_i2c.c @@ -21,8 +21,8 @@ static int bmg160_i2c_probe(struct i2c_client *client, regmap = devm_regmap_init_i2c(client, &bmg160_regmap_i2c_conf); if (IS_ERR(regmap)) { - dev_err(&client->dev, "Failed to register i2c regmap %d\n", - (int)PTR_ERR(regmap)); + dev_err(&client->dev, "Failed to register i2c regmap: %pe\n", + regmap); return PTR_ERR(regmap); } @@ -42,6 +42,7 @@ static int bmg160_i2c_remove(struct i2c_client *client) static const struct acpi_device_id bmg160_acpi_match[] = { {"BMG0160", 0}, {"BMI055B", 0}, + {"BMI088B", 0}, {}, }; @@ -50,6 +51,7 @@ MODULE_DEVICE_TABLE(acpi, bmg160_acpi_match); static const struct i2c_device_id bmg160_i2c_id[] = { {"bmg160", 0}, {"bmi055_gyro", 0}, + {"bmi088_gyro", 0}, {} }; diff --git a/drivers/iio/gyro/bmg160_spi.c b/drivers/iio/gyro/bmg160_spi.c index 182a59c42507..745962e1e423 100644 --- a/drivers/iio/gyro/bmg160_spi.c +++ b/drivers/iio/gyro/bmg160_spi.c @@ -19,8 +19,8 @@ static int bmg160_spi_probe(struct spi_device *spi) regmap = devm_regmap_init_spi(spi, &bmg160_regmap_spi_conf); if (IS_ERR(regmap)) { - dev_err(&spi->dev, "Failed to register spi regmap %d\n", - (int)PTR_ERR(regmap)); + dev_err(&spi->dev, "Failed to register spi regmap: %pe\n", + regmap); return PTR_ERR(regmap); } @@ -37,6 +37,7 @@ static int bmg160_spi_remove(struct spi_device *spi) static const struct spi_device_id bmg160_spi_id[] = { {"bmg160", 0}, {"bmi055_gyro", 0}, + {"bmi088_gyro", 0}, {} }; diff --git a/drivers/iio/gyro/hid-sensor-gyro-3d.c b/drivers/iio/gyro/hid-sensor-gyro-3d.c index 08cacbbf31e6..7f382aae1dfd 100644 --- a/drivers/iio/gyro/hid-sensor-gyro-3d.c +++ b/drivers/iio/gyro/hid-sensor-gyro-3d.c @@ -14,8 +14,6 @@ #include #include #include -#include -#include #include "../common/hid-sensors/hid-sensor-trigger.h" enum gyro_3d_channel { @@ -326,18 +324,13 @@ static int hid_gyro_3d_probe(struct platform_device *pdev) indio_dev->name = name; indio_dev->modes = INDIO_DIRECT_MODE; - ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time, - NULL, NULL); - if (ret) { - dev_err(&pdev->dev, "failed to initialize trigger buffer\n"); - goto error_free_dev_mem; - } atomic_set(&gyro_state->common_attributes.data_ready, 0); + ret = hid_sensor_setup_trigger(indio_dev, name, &gyro_state->common_attributes); if (ret < 0) { dev_err(&pdev->dev, "trigger setup failed\n"); - goto error_unreg_buffer_funcs; + goto error_free_dev_mem; } ret = iio_device_register(indio_dev); @@ -361,9 +354,7 @@ static int hid_gyro_3d_probe(struct platform_device *pdev) error_iio_unreg: iio_device_unregister(indio_dev); error_remove_trigger: - hid_sensor_remove_trigger(&gyro_state->common_attributes); -error_unreg_buffer_funcs: - iio_triggered_buffer_cleanup(indio_dev); + hid_sensor_remove_trigger(indio_dev, &gyro_state->common_attributes); error_free_dev_mem: kfree(indio_dev->channels); return ret; @@ -378,8 +369,7 @@ static int hid_gyro_3d_remove(struct platform_device *pdev) sensor_hub_remove_callback(hsdev, HID_USAGE_SENSOR_GYRO_3D); iio_device_unregister(indio_dev); - hid_sensor_remove_trigger(&gyro_state->common_attributes); - iio_triggered_buffer_cleanup(indio_dev); + hid_sensor_remove_trigger(indio_dev, &gyro_state->common_attributes); kfree(indio_dev->channels); return 0; diff --git a/drivers/iio/gyro/mpu3050-i2c.c b/drivers/iio/gyro/mpu3050-i2c.c index afa8018b9238..ef5bcbc4b45b 100644 --- a/drivers/iio/gyro/mpu3050-i2c.c +++ b/drivers/iio/gyro/mpu3050-i2c.c @@ -51,8 +51,8 @@ static int mpu3050_i2c_probe(struct i2c_client *client, regmap = devm_regmap_init_i2c(client, &mpu3050_i2c_regmap_config); if (IS_ERR(regmap)) { - dev_err(&client->dev, "Failed to register i2c regmap %d\n", - (int)PTR_ERR(regmap)); + dev_err(&client->dev, "Failed to register i2c regmap: %pe\n", + regmap); return PTR_ERR(regmap); } diff --git a/drivers/iio/gyro/st_gyro_buffer.c b/drivers/iio/gyro/st_gyro_buffer.c index 7465ad62391c..9c92ff7a82be 100644 --- a/drivers/iio/gyro/st_gyro_buffer.c +++ b/drivers/iio/gyro/st_gyro_buffer.c @@ -37,8 +37,7 @@ static int st_gyro_buffer_postenable(struct iio_dev *indio_dev) if (err < 0) return err; - err = st_sensors_set_axis_enable(indio_dev, - (u8)indio_dev->active_scan_mask[0]); + err = st_sensors_set_axis_enable(indio_dev, indio_dev->active_scan_mask[0]); if (err < 0) goto st_gyro_buffer_predisable; diff --git a/drivers/iio/gyro/st_gyro_core.c b/drivers/iio/gyro/st_gyro_core.c index 26c50b24bc08..c8aa051995d3 100644 --- a/drivers/iio/gyro/st_gyro_core.c +++ b/drivers/iio/gyro/st_gyro_core.c @@ -460,6 +460,7 @@ EXPORT_SYMBOL(st_gyro_get_settings); int st_gyro_common_probe(struct iio_dev *indio_dev) { struct st_sensor_data *gdata = iio_priv(indio_dev); + struct st_sensors_platform_data *pdata; int err; indio_dev->modes = INDIO_DIRECT_MODE; @@ -477,12 +478,12 @@ int st_gyro_common_probe(struct iio_dev *indio_dev) indio_dev->channels = gdata->sensor_settings->ch; indio_dev->num_channels = ST_SENSORS_NUMBER_ALL_CHANNELS; - gdata->current_fullscale = (struct st_sensor_fullscale_avl *) - &gdata->sensor_settings->fs.fs_avl[0]; + gdata->current_fullscale = &gdata->sensor_settings->fs.fs_avl[0]; gdata->odr = gdata->sensor_settings->odr.odr_avl[0].hz; - err = st_sensors_init_sensor(indio_dev, - (struct st_sensors_platform_data *)&gyro_pdata); + pdata = (struct st_sensors_platform_data *)&gyro_pdata; + + err = st_sensors_init_sensor(indio_dev, pdata); if (err < 0) goto st_gyro_power_off; diff --git a/drivers/iio/health/afe4403.c b/drivers/iio/health/afe4403.c index dc22dc363a99..e9f87e42ff4f 100644 --- a/drivers/iio/health/afe4403.c +++ b/drivers/iio/health/afe4403.c @@ -23,6 +23,8 @@ #include #include +#include + #include "afe440x.h" #define AFE4403_DRIVER_NAME "afe4403" @@ -220,13 +222,11 @@ static int afe4403_read(struct afe4403_data *afe, unsigned int reg, u32 *val) if (ret) return ret; - ret = spi_write_then_read(afe->spi, ®, 1, rx, 3); + ret = spi_write_then_read(afe->spi, ®, 1, rx, sizeof(rx)); if (ret) return ret; - *val = (rx[0] << 16) | - (rx[1] << 8) | - (rx[2]); + *val = get_unaligned_be24(&rx[0]); /* Disable reading from the device */ tx[3] = AFE440X_CONTROL0_WRITE; @@ -322,13 +322,11 @@ static irqreturn_t afe4403_trigger_handler(int irq, void *private) indio_dev->masklength) { ret = spi_write_then_read(afe->spi, &afe4403_channel_values[bit], 1, - rx, 3); + rx, sizeof(rx)); if (ret) goto err; - buffer[i++] = (rx[0] << 16) | - (rx[1] << 8) | - (rx[2]); + buffer[i++] = get_unaligned_be24(&rx[0]); } /* Disable reading from the device */ diff --git a/drivers/iio/health/max30100.c b/drivers/iio/health/max30100.c index 84010501762d..546fc37ad75d 100644 --- a/drivers/iio/health/max30100.c +++ b/drivers/iio/health/max30100.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include #include @@ -267,11 +267,10 @@ static int max30100_get_current_idx(unsigned int val, int *reg) static int max30100_led_init(struct max30100_data *data) { struct device *dev = &data->client->dev; - struct device_node *np = dev->of_node; unsigned int val[2]; int reg, ret; - ret = of_property_read_u32_array(np, "maxim,led-current-microamp", + ret = device_property_read_u32_array(dev, "maxim,led-current-microamp", (unsigned int *) &val, 2); if (ret) { /* Default to 24 mA RED LED, 50 mA IR LED */ @@ -502,7 +501,7 @@ MODULE_DEVICE_TABLE(of, max30100_dt_ids); static struct i2c_driver max30100_driver = { .driver = { .name = MAX30100_DRV_NAME, - .of_match_table = of_match_ptr(max30100_dt_ids), + .of_match_table = max30100_dt_ids, }, .probe = max30100_probe, .remove = max30100_remove, diff --git a/drivers/iio/humidity/hid-sensor-humidity.c b/drivers/iio/humidity/hid-sensor-humidity.c index c99b54b0568d..d2318c4aab0f 100644 --- a/drivers/iio/humidity/hid-sensor-humidity.c +++ b/drivers/iio/humidity/hid-sensor-humidity.c @@ -7,8 +7,6 @@ #include #include #include -#include -#include #include #include @@ -233,12 +231,8 @@ static int hid_humidity_probe(struct platform_device *pdev) indio_dev->name = name; indio_dev->modes = INDIO_DIRECT_MODE; - ret = devm_iio_triggered_buffer_setup(&pdev->dev, indio_dev, - &iio_pollfunc_store_time, NULL, NULL); - if (ret) - return ret; - atomic_set(&humid_st->common_attributes.data_ready, 0); + ret = hid_sensor_setup_trigger(indio_dev, name, &humid_st->common_attributes); if (ret) @@ -261,7 +255,7 @@ static int hid_humidity_probe(struct platform_device *pdev) error_remove_callback: sensor_hub_remove_callback(hsdev, HID_USAGE_SENSOR_HUMIDITY); error_remove_trigger: - hid_sensor_remove_trigger(&humid_st->common_attributes); + hid_sensor_remove_trigger(indio_dev, &humid_st->common_attributes); return ret; } @@ -274,7 +268,7 @@ static int hid_humidity_remove(struct platform_device *pdev) iio_device_unregister(indio_dev); sensor_hub_remove_callback(hsdev, HID_USAGE_SENSOR_HUMIDITY); - hid_sensor_remove_trigger(&humid_st->common_attributes); + hid_sensor_remove_trigger(indio_dev, &humid_st->common_attributes); return 0; } diff --git a/drivers/iio/humidity/hts221_buffer.c b/drivers/iio/humidity/hts221_buffer.c index 81d50a861c22..9fb3f33614d4 100644 --- a/drivers/iio/humidity/hts221_buffer.c +++ b/drivers/iio/humidity/hts221_buffer.c @@ -74,10 +74,9 @@ static irqreturn_t hts221_trigger_handler_thread(int irq, void *private) int hts221_allocate_trigger(struct hts221_hw *hw) { + struct st_sensors_platform_data *pdata = dev_get_platdata(hw->dev); struct iio_dev *iio_dev = iio_priv_to_dev(hw); bool irq_active_low = false, open_drain = false; - struct device_node *np = hw->dev->of_node; - struct st_sensors_platform_data *pdata; unsigned long irq_type; int err; @@ -106,8 +105,7 @@ int hts221_allocate_trigger(struct hts221_hw *hw) if (err < 0) return err; - pdata = (struct st_sensors_platform_data *)hw->dev->platform_data; - if ((np && of_property_read_bool(np, "drive-open-drain")) || + if (device_property_read_bool(hw->dev, "drive-open-drain") || (pdata && pdata->open_drain)) { irq_type |= IRQF_SHARED; open_drain = true; diff --git a/drivers/iio/humidity/hts221_i2c.c b/drivers/iio/humidity/hts221_i2c.c index 4272b7030c44..cab39c4756f8 100644 --- a/drivers/iio/humidity/hts221_i2c.c +++ b/drivers/iio/humidity/hts221_i2c.c @@ -32,8 +32,8 @@ static int hts221_i2c_probe(struct i2c_client *client, regmap = devm_regmap_init_i2c(client, &hts221_i2c_regmap_config); if (IS_ERR(regmap)) { - dev_err(&client->dev, "Failed to register i2c regmap %d\n", - (int)PTR_ERR(regmap)); + dev_err(&client->dev, "Failed to register i2c regmap %ld\n", + PTR_ERR(regmap)); return PTR_ERR(regmap); } @@ -63,7 +63,7 @@ static struct i2c_driver hts221_driver = { .driver = { .name = "hts221_i2c", .pm = &hts221_pm_ops, - .of_match_table = of_match_ptr(hts221_i2c_of_match), + .of_match_table = hts221_i2c_of_match, .acpi_match_table = ACPI_PTR(hts221_acpi_match), }, .probe = hts221_i2c_probe, diff --git a/drivers/iio/humidity/hts221_spi.c b/drivers/iio/humidity/hts221_spi.c index 055dba8897d2..729e86e433b1 100644 --- a/drivers/iio/humidity/hts221_spi.c +++ b/drivers/iio/humidity/hts221_spi.c @@ -31,8 +31,8 @@ static int hts221_spi_probe(struct spi_device *spi) regmap = devm_regmap_init_spi(spi, &hts221_spi_regmap_config); if (IS_ERR(regmap)) { - dev_err(&spi->dev, "Failed to register spi regmap %d\n", - (int)PTR_ERR(regmap)); + dev_err(&spi->dev, "Failed to register spi regmap %ld\n", + PTR_ERR(regmap)); return PTR_ERR(regmap); } @@ -56,7 +56,7 @@ static struct spi_driver hts221_driver = { .driver = { .name = "hts221_spi", .pm = &hts221_pm_ops, - .of_match_table = of_match_ptr(hts221_spi_of_match), + .of_match_table = hts221_spi_of_match, }, .probe = hts221_spi_probe, .id_table = hts221_spi_id_table, diff --git a/drivers/iio/imu/Kconfig b/drivers/iio/imu/Kconfig index 60bb1029e759..fc4123d518bc 100644 --- a/drivers/iio/imu/Kconfig +++ b/drivers/iio/imu/Kconfig @@ -29,6 +29,19 @@ config ADIS16460 To compile this driver as a module, choose M here: the module will be called adis16460. +config ADIS16475 + tristate "Analog Devices ADIS16475 and similar IMU driver" + depends on SPI + select IIO_ADIS_LIB + select IIO_ADIS_LIB_BUFFER if IIO_BUFFER + help + Say yes here to build support for Analog Devices ADIS16470, ADIS16475, + ADIS16477, ADIS16465, ADIS16467, ADIS16500, ADIS16505, ADIS16507 inertial + sensors. + + To compile this driver as a module, choose M here: the module will be + called adis16475. + config ADIS16480 tristate "Analog Devices ADIS16480 and similar IMU driver" depends on SPI diff --git a/drivers/iio/imu/Makefile b/drivers/iio/imu/Makefile index 5237fd4bc384..88b2c4555230 100644 --- a/drivers/iio/imu/Makefile +++ b/drivers/iio/imu/Makefile @@ -6,6 +6,7 @@ # When adding new entries keep the list in alphabetical order obj-$(CONFIG_ADIS16400) += adis16400.o obj-$(CONFIG_ADIS16460) += adis16460.o +obj-$(CONFIG_ADIS16475) += adis16475.o obj-$(CONFIG_ADIS16480) += adis16480.o adis_lib-y += adis.o diff --git a/drivers/iio/imu/adis.c b/drivers/iio/imu/adis.c index a8afd01de4f3..c539dfa3b8d3 100644 --- a/drivers/iio/imu/adis.c +++ b/drivers/iio/imu/adis.c @@ -223,6 +223,31 @@ int __adis_read_reg(struct adis *adis, unsigned int reg, return ret; } EXPORT_SYMBOL_GPL(__adis_read_reg); +/** + * __adis_update_bits_base() - ADIS Update bits function - Unlocked version + * @adis: The adis device + * @reg: The address of the lower of the two registers + * @mask: Bitmask to change + * @val: Value to be written + * @size: Size of the register to update + * + * Updates the desired bits of @reg in accordance with @mask and @val. + */ +int __adis_update_bits_base(struct adis *adis, unsigned int reg, const u32 mask, + const u32 val, u8 size) +{ + int ret; + u32 __val; + + ret = __adis_read_reg(adis, reg, &__val, size); + if (ret) + return ret; + + __val = (__val & ~mask) | (val & mask); + + return __adis_write_reg(adis, reg, __val, size); +} +EXPORT_SYMBOL_GPL(__adis_update_bits_base); #ifdef CONFIG_DEBUG_FS @@ -419,7 +444,7 @@ int __adis_initial_startup(struct adis *adis) if (prod_id != adis->data->prod_id) dev_warn(&adis->spi->dev, - "Device ID(%u) and product ID(%u) do not match.", + "Device ID(%u) and product ID(%u) do not match.\n", adis->data->prod_id, prod_id); return 0; diff --git a/drivers/iio/imu/adis16400.c b/drivers/iio/imu/adis16400.c index 05e70c1c4835..229f2ff98469 100644 --- a/drivers/iio/imu/adis16400.c +++ b/drivers/iio/imu/adis16400.c @@ -258,7 +258,7 @@ static int adis16400_show_product_id(void *arg, u64 *val) return 0; } -DEFINE_SIMPLE_ATTRIBUTE(adis16400_product_id_fops, +DEFINE_DEBUGFS_ATTRIBUTE(adis16400_product_id_fops, adis16400_show_product_id, NULL, "%lld\n"); static int adis16400_show_flash_count(void *arg, u64 *val) @@ -275,23 +275,22 @@ static int adis16400_show_flash_count(void *arg, u64 *val) return 0; } -DEFINE_SIMPLE_ATTRIBUTE(adis16400_flash_count_fops, +DEFINE_DEBUGFS_ATTRIBUTE(adis16400_flash_count_fops, adis16400_show_flash_count, NULL, "%lld\n"); static int adis16400_debugfs_init(struct iio_dev *indio_dev) { struct adis16400_state *st = iio_priv(indio_dev); + struct dentry *d = iio_get_debugfs_dentry(indio_dev); if (st->variant->flags & ADIS16400_HAS_SERIAL_NUMBER) - debugfs_create_file("serial_number", 0400, - indio_dev->debugfs_dentry, st, - &adis16400_serial_number_fops); + debugfs_create_file_unsafe("serial_number", 0400, + d, st, &adis16400_serial_number_fops); if (st->variant->flags & ADIS16400_HAS_PROD_ID) - debugfs_create_file("product_id", 0400, - indio_dev->debugfs_dentry, st, - &adis16400_product_id_fops); - debugfs_create_file("flash_count", 0400, indio_dev->debugfs_dentry, - st, &adis16400_flash_count_fops); + debugfs_create_file_unsafe("product_id", 0400, + d, st, &adis16400_product_id_fops); + debugfs_create_file_unsafe("flash_count", 0400, + d, st, &adis16400_flash_count_fops); return 0; } @@ -1194,7 +1193,7 @@ static int adis16400_probe(struct spi_device *spi) indio_dev->available_scan_masks = st->avail_scan_mask; st->adis.burst = &adis16400_burst; if (st->variant->flags & ADIS16400_BURST_DIAG_STAT) - st->adis.burst->extra_len = sizeof(u16); + st->adis.burst_extra_len = sizeof(u16); } adis16400_data = &st->variant->adis_data; diff --git a/drivers/iio/imu/adis16460.c b/drivers/iio/imu/adis16460.c index 0027683d0256..ad20c488a3ba 100644 --- a/drivers/iio/imu/adis16460.c +++ b/drivers/iio/imu/adis16460.c @@ -87,8 +87,8 @@ static int adis16460_show_serial_number(void *arg, u64 *val) return 0; } -DEFINE_SIMPLE_ATTRIBUTE(adis16460_serial_number_fops, - adis16460_show_serial_number, NULL, "0x%.4llx\n"); +DEFINE_DEBUGFS_ATTRIBUTE(adis16460_serial_number_fops, + adis16460_show_serial_number, NULL, "0x%.4llx\n"); static int adis16460_show_product_id(void *arg, u64 *val) { @@ -105,8 +105,8 @@ static int adis16460_show_product_id(void *arg, u64 *val) return 0; } -DEFINE_SIMPLE_ATTRIBUTE(adis16460_product_id_fops, - adis16460_show_product_id, NULL, "%llu\n"); +DEFINE_DEBUGFS_ATTRIBUTE(adis16460_product_id_fops, + adis16460_show_product_id, NULL, "%llu\n"); static int adis16460_show_flash_count(void *arg, u64 *val) { @@ -123,19 +123,20 @@ static int adis16460_show_flash_count(void *arg, u64 *val) return 0; } -DEFINE_SIMPLE_ATTRIBUTE(adis16460_flash_count_fops, - adis16460_show_flash_count, NULL, "%lld\n"); +DEFINE_DEBUGFS_ATTRIBUTE(adis16460_flash_count_fops, + adis16460_show_flash_count, NULL, "%lld\n"); static int adis16460_debugfs_init(struct iio_dev *indio_dev) { struct adis16460 *adis16460 = iio_priv(indio_dev); + struct dentry *d = iio_get_debugfs_dentry(indio_dev); - debugfs_create_file("serial_number", 0400, indio_dev->debugfs_dentry, - adis16460, &adis16460_serial_number_fops); - debugfs_create_file("product_id", 0400, indio_dev->debugfs_dentry, - adis16460, &adis16460_product_id_fops); - debugfs_create_file("flash_count", 0400, indio_dev->debugfs_dentry, - adis16460, &adis16460_flash_count_fops); + debugfs_create_file_unsafe("serial_number", 0400, + d, adis16460, &adis16460_serial_number_fops); + debugfs_create_file_unsafe("product_id", 0400, + d, adis16460, &adis16460_product_id_fops); + debugfs_create_file_unsafe("flash_count", 0400, + d, adis16460, &adis16460_flash_count_fops); return 0; } diff --git a/drivers/iio/imu/adis16475.c b/drivers/iio/imu/adis16475.c new file mode 100644 index 000000000000..c6dac4fc67a1 --- /dev/null +++ b/drivers/iio/imu/adis16475.c @@ -0,0 +1,1338 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ADIS16475 IMU driver + * + * Copyright 2019 Analog Devices Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ADIS16475_REG_DIAG_STAT 0x02 +#define ADIS16475_REG_X_GYRO_L 0x04 +#define ADIS16475_REG_Y_GYRO_L 0x08 +#define ADIS16475_REG_Z_GYRO_L 0x0C +#define ADIS16475_REG_X_ACCEL_L 0x10 +#define ADIS16475_REG_Y_ACCEL_L 0x14 +#define ADIS16475_REG_Z_ACCEL_L 0x18 +#define ADIS16475_REG_TEMP_OUT 0x1c +#define ADIS16475_REG_X_GYRO_BIAS_L 0x40 +#define ADIS16475_REG_Y_GYRO_BIAS_L 0x44 +#define ADIS16475_REG_Z_GYRO_BIAS_L 0x48 +#define ADIS16475_REG_X_ACCEL_BIAS_L 0x4c +#define ADIS16475_REG_Y_ACCEL_BIAS_L 0x50 +#define ADIS16475_REG_Z_ACCEL_BIAS_L 0x54 +#define ADIS16475_REG_FILT_CTRL 0x5c +#define ADIS16475_FILT_CTRL_MASK GENMASK(2, 0) +#define ADIS16475_FILT_CTRL(x) FIELD_PREP(ADIS16475_FILT_CTRL_MASK, x) +#define ADIS16475_REG_MSG_CTRL 0x60 +#define ADIS16475_MSG_CTRL_DR_POL_MASK BIT(0) +#define ADIS16475_MSG_CTRL_DR_POL(x) \ + FIELD_PREP(ADIS16475_MSG_CTRL_DR_POL_MASK, x) +#define ADIS16475_SYNC_MODE_MASK GENMASK(4, 2) +#define ADIS16475_SYNC_MODE(x) FIELD_PREP(ADIS16475_SYNC_MODE_MASK, x) +#define ADIS16475_REG_UP_SCALE 0x62 +#define ADIS16475_REG_DEC_RATE 0x64 +#define ADIS16475_REG_GLOB_CMD 0x68 +#define ADIS16475_REG_FIRM_REV 0x6c +#define ADIS16475_REG_FIRM_DM 0x6e +#define ADIS16475_REG_FIRM_Y 0x70 +#define ADIS16475_REG_PROD_ID 0x72 +#define ADIS16475_REG_SERIAL_NUM 0x74 +#define ADIS16475_REG_FLASH_CNT 0x7c +#define ADIS16500_BURST32_MASK BIT(9) +#define ADIS16500_BURST32(x) FIELD_PREP(ADIS16500_BURST32_MASK, x) +/* number of data elements in burst mode */ +#define ADIS16475_BURST32_MAX_DATA 32 +#define ADIS16475_BURST_MAX_DATA 20 +#define ADIS16475_MAX_SCAN_DATA 20 +/* spi max speed in brust mode */ +#define ADIS16475_BURST_MAX_SPEED 1000000 +#define ADIS16475_LSB_DEC_MASK BIT(0) +#define ADIS16475_LSB_FIR_MASK BIT(1) + +enum { + ADIS16475_SYNC_DIRECT = 1, + ADIS16475_SYNC_SCALED, + ADIS16475_SYNC_OUTPUT, + ADIS16475_SYNC_PULSE = 5, +}; + +struct adis16475_sync { + u16 sync_mode; + u16 min_rate; + u16 max_rate; +}; + +struct adis16475_chip_info { + const struct iio_chan_spec *channels; + const struct adis16475_sync *sync; + const struct adis_data adis_data; + const char *name; + u32 num_channels; + u32 gyro_max_val; + u32 gyro_max_scale; + u32 accel_max_val; + u32 accel_max_scale; + u32 temp_scale; + u32 int_clk; + u16 max_dec; + u8 num_sync; + bool has_burst32; +}; + +struct adis16475 { + const struct adis16475_chip_info *info; + struct adis adis; + u32 clk_freq; + bool burst32; + unsigned long lsb_flag; + /* Alignment needed for the timestamp */ + __be16 data[ADIS16475_MAX_SCAN_DATA] __aligned(8); +}; + +enum { + ADIS16475_SCAN_GYRO_X, + ADIS16475_SCAN_GYRO_Y, + ADIS16475_SCAN_GYRO_Z, + ADIS16475_SCAN_ACCEL_X, + ADIS16475_SCAN_ACCEL_Y, + ADIS16475_SCAN_ACCEL_Z, + ADIS16475_SCAN_TEMP, + ADIS16475_SCAN_DIAG_S_FLAGS, + ADIS16475_SCAN_CRC_FAILURE, +}; + +#ifdef CONFIG_DEBUG_FS +static ssize_t adis16475_show_firmware_revision(struct file *file, + char __user *userbuf, + size_t count, loff_t *ppos) +{ + struct adis16475 *st = file->private_data; + char buf[7]; + size_t len; + u16 rev; + int ret; + + ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_REV, &rev); + if (ret) + return ret; + + len = scnprintf(buf, sizeof(buf), "%x.%x\n", rev >> 8, rev & 0xff); + + return simple_read_from_buffer(userbuf, count, ppos, buf, len); +} + +static const struct file_operations adis16475_firmware_revision_fops = { + .open = simple_open, + .read = adis16475_show_firmware_revision, + .llseek = default_llseek, + .owner = THIS_MODULE, +}; + +static ssize_t adis16475_show_firmware_date(struct file *file, + char __user *userbuf, + size_t count, loff_t *ppos) +{ + struct adis16475 *st = file->private_data; + u16 md, year; + char buf[12]; + size_t len; + int ret; + + ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_Y, &year); + if (ret) + return ret; + + ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_DM, &md); + if (ret) + return ret; + + len = snprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n", md >> 8, md & 0xff, + year); + + return simple_read_from_buffer(userbuf, count, ppos, buf, len); +} + +static const struct file_operations adis16475_firmware_date_fops = { + .open = simple_open, + .read = adis16475_show_firmware_date, + .llseek = default_llseek, + .owner = THIS_MODULE, +}; + +static int adis16475_show_serial_number(void *arg, u64 *val) +{ + struct adis16475 *st = arg; + u16 serial; + int ret; + + ret = adis_read_reg_16(&st->adis, ADIS16475_REG_SERIAL_NUM, &serial); + if (ret) + return ret; + + *val = serial; + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(adis16475_serial_number_fops, + adis16475_show_serial_number, NULL, "0x%.4llx\n"); + +static int adis16475_show_product_id(void *arg, u64 *val) +{ + struct adis16475 *st = arg; + u16 prod_id; + int ret; + + ret = adis_read_reg_16(&st->adis, ADIS16475_REG_PROD_ID, &prod_id); + if (ret) + return ret; + + *val = prod_id; + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(adis16475_product_id_fops, + adis16475_show_product_id, NULL, "%llu\n"); + +static int adis16475_show_flash_count(void *arg, u64 *val) +{ + struct adis16475 *st = arg; + u32 flash_count; + int ret; + + ret = adis_read_reg_32(&st->adis, ADIS16475_REG_FLASH_CNT, + &flash_count); + if (ret) + return ret; + + *val = flash_count; + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(adis16475_flash_count_fops, + adis16475_show_flash_count, NULL, "%lld\n"); + +static void adis16475_debugfs_init(struct iio_dev *indio_dev) +{ + struct adis16475 *st = iio_priv(indio_dev); + struct dentry *d = iio_get_debugfs_dentry(indio_dev); + + debugfs_create_file_unsafe("serial_number", 0400, + d, st, &adis16475_serial_number_fops); + debugfs_create_file_unsafe("product_id", 0400, + d, st, &adis16475_product_id_fops); + debugfs_create_file_unsafe("flash_count", 0400, + d, st, &adis16475_flash_count_fops); + debugfs_create_file("firmware_revision", 0400, + d, st, &adis16475_firmware_revision_fops); + debugfs_create_file("firmware_date", 0400, d, + st, &adis16475_firmware_date_fops); +} +#else +static void adis16475_debugfs_init(struct iio_dev *indio_dev) +{ +} +#endif + +static int adis16475_get_freq(struct adis16475 *st, u32 *freq) +{ + int ret; + u16 dec; + + ret = adis_read_reg_16(&st->adis, ADIS16475_REG_DEC_RATE, &dec); + if (ret) + return -EINVAL; + + *freq = DIV_ROUND_CLOSEST(st->clk_freq, dec + 1); + + return 0; +} + +static int adis16475_set_freq(struct adis16475 *st, const u32 freq) +{ + u16 dec; + int ret; + + if (!freq) + return -EINVAL; + + dec = DIV_ROUND_CLOSEST(st->clk_freq, freq); + + if (dec) + dec--; + + if (dec > st->info->max_dec) + dec = st->info->max_dec; + + ret = adis_write_reg_16(&st->adis, ADIS16475_REG_DEC_RATE, dec); + if (ret) + return ret; + + /* + * If decimation is used, then gyro and accel data will have meaningful + * bits on the LSB registers. This info is used on the trigger handler. + */ + assign_bit(ADIS16475_LSB_DEC_MASK, &st->lsb_flag, dec); + + return 0; +} + +/* The values are approximated. */ +static const u32 adis16475_3db_freqs[] = { + [0] = 720, /* Filter disabled, full BW (~720Hz) */ + [1] = 360, + [2] = 164, + [3] = 80, + [4] = 40, + [5] = 20, + [6] = 10, +}; + +static int adis16475_get_filter(struct adis16475 *st, u32 *filter) +{ + u16 filter_sz; + int ret; + const int mask = ADIS16475_FILT_CTRL_MASK; + + ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FILT_CTRL, &filter_sz); + if (ret) + return ret; + + *filter = adis16475_3db_freqs[filter_sz & mask]; + + return 0; +} + +static int adis16475_set_filter(struct adis16475 *st, const u32 filter) +{ + int i = ARRAY_SIZE(adis16475_3db_freqs); + int ret; + + while (--i) { + if (adis16475_3db_freqs[i] >= filter) + break; + } + + ret = adis_write_reg_16(&st->adis, ADIS16475_REG_FILT_CTRL, + ADIS16475_FILT_CTRL(i)); + if (ret) + return ret; + + /* + * If FIR is used, then gyro and accel data will have meaningful + * bits on the LSB registers. This info is used on the trigger handler. + */ + assign_bit(ADIS16475_LSB_FIR_MASK, &st->lsb_flag, i); + + return 0; +} + +static const u32 adis16475_calib_regs[] = { + [ADIS16475_SCAN_GYRO_X] = ADIS16475_REG_X_GYRO_BIAS_L, + [ADIS16475_SCAN_GYRO_Y] = ADIS16475_REG_Y_GYRO_BIAS_L, + [ADIS16475_SCAN_GYRO_Z] = ADIS16475_REG_Z_GYRO_BIAS_L, + [ADIS16475_SCAN_ACCEL_X] = ADIS16475_REG_X_ACCEL_BIAS_L, + [ADIS16475_SCAN_ACCEL_Y] = ADIS16475_REG_Y_ACCEL_BIAS_L, + [ADIS16475_SCAN_ACCEL_Z] = ADIS16475_REG_Z_ACCEL_BIAS_L, +}; + +static int adis16475_read_raw(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + int *val, int *val2, long info) +{ + struct adis16475 *st = iio_priv(indio_dev); + int ret; + u32 tmp; + + switch (info) { + case IIO_CHAN_INFO_RAW: + return adis_single_conversion(indio_dev, chan, 0, val); + case IIO_CHAN_INFO_SCALE: + switch (chan->type) { + case IIO_ANGL_VEL: + *val = st->info->gyro_max_val; + *val2 = st->info->gyro_max_scale; + return IIO_VAL_FRACTIONAL; + case IIO_ACCEL: + *val = st->info->accel_max_val; + *val2 = st->info->accel_max_scale; + return IIO_VAL_FRACTIONAL; + case IIO_TEMP: + *val = st->info->temp_scale; + return IIO_VAL_INT; + default: + return -EINVAL; + } + case IIO_CHAN_INFO_CALIBBIAS: + ret = adis_read_reg_32(&st->adis, + adis16475_calib_regs[chan->scan_index], + val); + if (ret) + return ret; + + return IIO_VAL_INT; + case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: + ret = adis16475_get_filter(st, val); + if (ret) + return ret; + + return IIO_VAL_INT; + case IIO_CHAN_INFO_SAMP_FREQ: + ret = adis16475_get_freq(st, &tmp); + if (ret) + return ret; + + *val = tmp / 1000; + *val2 = (tmp % 1000) * 1000; + return IIO_VAL_INT_PLUS_MICRO; + default: + return -EINVAL; + } +} + +static int adis16475_write_raw(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + int val, int val2, long info) +{ + struct adis16475 *st = iio_priv(indio_dev); + u32 tmp; + + switch (info) { + case IIO_CHAN_INFO_SAMP_FREQ: + tmp = val * 1000 + val2 / 1000; + return adis16475_set_freq(st, tmp); + case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: + return adis16475_set_filter(st, val); + case IIO_CHAN_INFO_CALIBBIAS: + return adis_write_reg_32(&st->adis, + adis16475_calib_regs[chan->scan_index], + val); + default: + return -EINVAL; + } +} + +#define ADIS16475_MOD_CHAN(_type, _mod, _address, _si, _r_bits, _s_bits) \ + { \ + .type = (_type), \ + .modified = 1, \ + .channel2 = (_mod), \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_CALIBBIAS), \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ + .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ + BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ + .address = (_address), \ + .scan_index = (_si), \ + .scan_type = { \ + .sign = 's', \ + .realbits = (_r_bits), \ + .storagebits = (_s_bits), \ + .endianness = IIO_BE, \ + }, \ + } + +#define ADIS16475_GYRO_CHANNEL(_mod) \ + ADIS16475_MOD_CHAN(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \ + ADIS16475_REG_ ## _mod ## _GYRO_L, \ + ADIS16475_SCAN_GYRO_ ## _mod, 32, 32) + +#define ADIS16475_ACCEL_CHANNEL(_mod) \ + ADIS16475_MOD_CHAN(IIO_ACCEL, IIO_MOD_ ## _mod, \ + ADIS16475_REG_ ## _mod ## _ACCEL_L, \ + ADIS16475_SCAN_ACCEL_ ## _mod, 32, 32) + +#define ADIS16475_TEMP_CHANNEL() { \ + .type = IIO_TEMP, \ + .indexed = 1, \ + .channel = 0, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_SCALE), \ + .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ + BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ + .address = ADIS16475_REG_TEMP_OUT, \ + .scan_index = ADIS16475_SCAN_TEMP, \ + .scan_type = { \ + .sign = 's', \ + .realbits = 16, \ + .storagebits = 16, \ + .endianness = IIO_BE, \ + }, \ + } + +static const struct iio_chan_spec adis16475_channels[] = { + ADIS16475_GYRO_CHANNEL(X), + ADIS16475_GYRO_CHANNEL(Y), + ADIS16475_GYRO_CHANNEL(Z), + ADIS16475_ACCEL_CHANNEL(X), + ADIS16475_ACCEL_CHANNEL(Y), + ADIS16475_ACCEL_CHANNEL(Z), + ADIS16475_TEMP_CHANNEL(), + IIO_CHAN_SOFT_TIMESTAMP(7) +}; + +enum adis16475_variant { + ADIS16470, + ADIS16475_1, + ADIS16475_2, + ADIS16475_3, + ADIS16477_1, + ADIS16477_2, + ADIS16477_3, + ADIS16465_1, + ADIS16465_2, + ADIS16465_3, + ADIS16467_1, + ADIS16467_2, + ADIS16467_3, + ADIS16500, + ADIS16505_1, + ADIS16505_2, + ADIS16505_3, + ADIS16507_1, + ADIS16507_2, + ADIS16507_3, +}; + +enum { + ADIS16475_DIAG_STAT_DATA_PATH = 1, + ADIS16475_DIAG_STAT_FLASH_MEM, + ADIS16475_DIAG_STAT_SPI, + ADIS16475_DIAG_STAT_STANDBY, + ADIS16475_DIAG_STAT_SENSOR, + ADIS16475_DIAG_STAT_MEMORY, + ADIS16475_DIAG_STAT_CLK, +}; + +static const char * const adis16475_status_error_msgs[] = { + [ADIS16475_DIAG_STAT_DATA_PATH] = "Data Path Overrun", + [ADIS16475_DIAG_STAT_FLASH_MEM] = "Flash memory update failure", + [ADIS16475_DIAG_STAT_SPI] = "SPI communication error", + [ADIS16475_DIAG_STAT_STANDBY] = "Standby mode", + [ADIS16475_DIAG_STAT_SENSOR] = "Sensor failure", + [ADIS16475_DIAG_STAT_MEMORY] = "Memory failure", + [ADIS16475_DIAG_STAT_CLK] = "Clock error", +}; + +static int adis16475_enable_irq(struct adis *adis, bool enable) +{ + /* + * There is no way to gate the data-ready signal internally inside the + * ADIS16475. We can only control it's polarity... + */ + if (enable) + enable_irq(adis->spi->irq); + else + disable_irq(adis->spi->irq); + + return 0; +} + +#define ADIS16475_DATA(_prod_id, _timeouts) \ +{ \ + .msc_ctrl_reg = ADIS16475_REG_MSG_CTRL, \ + .glob_cmd_reg = ADIS16475_REG_GLOB_CMD, \ + .diag_stat_reg = ADIS16475_REG_DIAG_STAT, \ + .prod_id_reg = ADIS16475_REG_PROD_ID, \ + .prod_id = (_prod_id), \ + .self_test_mask = BIT(2), \ + .self_test_reg = ADIS16475_REG_GLOB_CMD, \ + .cs_change_delay = 16, \ + .read_delay = 5, \ + .write_delay = 5, \ + .status_error_msgs = adis16475_status_error_msgs, \ + .status_error_mask = BIT(ADIS16475_DIAG_STAT_DATA_PATH) | \ + BIT(ADIS16475_DIAG_STAT_FLASH_MEM) | \ + BIT(ADIS16475_DIAG_STAT_SPI) | \ + BIT(ADIS16475_DIAG_STAT_STANDBY) | \ + BIT(ADIS16475_DIAG_STAT_SENSOR) | \ + BIT(ADIS16475_DIAG_STAT_MEMORY) | \ + BIT(ADIS16475_DIAG_STAT_CLK), \ + .enable_irq = adis16475_enable_irq, \ + .timeouts = (_timeouts), \ +} + +static const struct adis16475_sync adis16475_sync_mode[] = { + { ADIS16475_SYNC_OUTPUT }, + { ADIS16475_SYNC_DIRECT, 1900, 2100 }, + { ADIS16475_SYNC_SCALED, 1, 128 }, + { ADIS16475_SYNC_PULSE, 1000, 2100 }, +}; + +static const struct adis_timeout adis16475_timeouts = { + .reset_ms = 200, + .sw_reset_ms = 200, + .self_test_ms = 20, +}; + +static const struct adis_timeout adis1650x_timeouts = { + .reset_ms = 260, + .sw_reset_ms = 260, + .self_test_ms = 30, +}; + +static const struct adis16475_chip_info adis16475_chip_info[] = { + [ADIS16470] = { + .name = "adis16470", + .num_channels = ARRAY_SIZE(adis16475_channels), + .channels = adis16475_channels, + .gyro_max_val = 1, + .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), + .accel_max_val = 1, + .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), + .temp_scale = 100, + .int_clk = 2000, + .max_dec = 1999, + .sync = adis16475_sync_mode, + .num_sync = ARRAY_SIZE(adis16475_sync_mode), + .adis_data = ADIS16475_DATA(16470, &adis16475_timeouts), + }, + [ADIS16475_1] = { + .name = "adis16475-1", + .num_channels = ARRAY_SIZE(adis16475_channels), + .channels = adis16475_channels, + .gyro_max_val = 1, + .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), + .accel_max_val = 1, + .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), + .temp_scale = 100, + .int_clk = 2000, + .max_dec = 1999, + .sync = adis16475_sync_mode, + .num_sync = ARRAY_SIZE(adis16475_sync_mode), + .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts), + }, + [ADIS16475_2] = { + .name = "adis16475-2", + .num_channels = ARRAY_SIZE(adis16475_channels), + .channels = adis16475_channels, + .gyro_max_val = 1, + .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), + .accel_max_val = 1, + .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), + .temp_scale = 100, + .int_clk = 2000, + .max_dec = 1999, + .sync = adis16475_sync_mode, + .num_sync = ARRAY_SIZE(adis16475_sync_mode), + .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts), + }, + [ADIS16475_3] = { + .name = "adis16475-3", + .num_channels = ARRAY_SIZE(adis16475_channels), + .channels = adis16475_channels, + .gyro_max_val = 1, + .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), + .accel_max_val = 1, + .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), + .temp_scale = 100, + .int_clk = 2000, + .max_dec = 1999, + .sync = adis16475_sync_mode, + .num_sync = ARRAY_SIZE(adis16475_sync_mode), + .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts), + }, + [ADIS16477_1] = { + .name = "adis16477-1", + .num_channels = ARRAY_SIZE(adis16475_channels), + .channels = adis16475_channels, + .gyro_max_val = 1, + .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), + .accel_max_val = 1, + .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), + .temp_scale = 100, + .int_clk = 2000, + .max_dec = 1999, + .sync = adis16475_sync_mode, + .num_sync = ARRAY_SIZE(adis16475_sync_mode), + .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts), + }, + [ADIS16477_2] = { + .name = "adis16477-2", + .num_channels = ARRAY_SIZE(adis16475_channels), + .channels = adis16475_channels, + .gyro_max_val = 1, + .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), + .accel_max_val = 1, + .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), + .temp_scale = 100, + .int_clk = 2000, + .max_dec = 1999, + .sync = adis16475_sync_mode, + .num_sync = ARRAY_SIZE(adis16475_sync_mode), + .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts), + }, + [ADIS16477_3] = { + .name = "adis16477-3", + .num_channels = ARRAY_SIZE(adis16475_channels), + .channels = adis16475_channels, + .gyro_max_val = 1, + .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), + .accel_max_val = 1, + .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), + .temp_scale = 100, + .int_clk = 2000, + .max_dec = 1999, + .sync = adis16475_sync_mode, + .num_sync = ARRAY_SIZE(adis16475_sync_mode), + .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts), + }, + [ADIS16465_1] = { + .name = "adis16465-1", + .num_channels = ARRAY_SIZE(adis16475_channels), + .channels = adis16475_channels, + .gyro_max_val = 1, + .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), + .accel_max_val = 1, + .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), + .temp_scale = 100, + .int_clk = 2000, + .max_dec = 1999, + .sync = adis16475_sync_mode, + .num_sync = ARRAY_SIZE(adis16475_sync_mode), + .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts), + }, + [ADIS16465_2] = { + .name = "adis16465-2", + .num_channels = ARRAY_SIZE(adis16475_channels), + .channels = adis16475_channels, + .gyro_max_val = 1, + .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), + .accel_max_val = 1, + .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), + .temp_scale = 100, + .int_clk = 2000, + .max_dec = 1999, + .sync = adis16475_sync_mode, + .num_sync = ARRAY_SIZE(adis16475_sync_mode), + .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts), + }, + [ADIS16465_3] = { + .name = "adis16465-3", + .num_channels = ARRAY_SIZE(adis16475_channels), + .channels = adis16475_channels, + .gyro_max_val = 1, + .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), + .accel_max_val = 1, + .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), + .temp_scale = 100, + .int_clk = 2000, + .max_dec = 1999, + .sync = adis16475_sync_mode, + .num_sync = ARRAY_SIZE(adis16475_sync_mode), + .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts), + }, + [ADIS16467_1] = { + .name = "adis16467-1", + .num_channels = ARRAY_SIZE(adis16475_channels), + .channels = adis16475_channels, + .gyro_max_val = 1, + .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), + .accel_max_val = 1, + .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), + .temp_scale = 100, + .int_clk = 2000, + .max_dec = 1999, + .sync = adis16475_sync_mode, + .num_sync = ARRAY_SIZE(adis16475_sync_mode), + .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts), + }, + [ADIS16467_2] = { + .name = "adis16467-2", + .num_channels = ARRAY_SIZE(adis16475_channels), + .channels = adis16475_channels, + .gyro_max_val = 1, + .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), + .accel_max_val = 1, + .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), + .temp_scale = 100, + .int_clk = 2000, + .max_dec = 1999, + .sync = adis16475_sync_mode, + .num_sync = ARRAY_SIZE(adis16475_sync_mode), + .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts), + }, + [ADIS16467_3] = { + .name = "adis16467-3", + .num_channels = ARRAY_SIZE(adis16475_channels), + .channels = adis16475_channels, + .gyro_max_val = 1, + .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), + .accel_max_val = 1, + .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), + .temp_scale = 100, + .int_clk = 2000, + .max_dec = 1999, + .sync = adis16475_sync_mode, + .num_sync = ARRAY_SIZE(adis16475_sync_mode), + .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts), + }, + [ADIS16500] = { + .name = "adis16500", + .num_channels = ARRAY_SIZE(adis16475_channels), + .channels = adis16475_channels, + .gyro_max_val = 1, + .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), + .accel_max_val = 392, + .accel_max_scale = 32000 << 16, + .temp_scale = 100, + .int_clk = 2000, + .max_dec = 1999, + .sync = adis16475_sync_mode, + /* pulse sync not supported */ + .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, + .has_burst32 = true, + .adis_data = ADIS16475_DATA(16500, &adis1650x_timeouts), + }, + [ADIS16505_1] = { + .name = "adis16505-1", + .num_channels = ARRAY_SIZE(adis16475_channels), + .channels = adis16475_channels, + .gyro_max_val = 1, + .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), + .accel_max_val = 78, + .accel_max_scale = 32000 << 16, + .temp_scale = 100, + .int_clk = 2000, + .max_dec = 1999, + .sync = adis16475_sync_mode, + /* pulse sync not supported */ + .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, + .has_burst32 = true, + .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts), + }, + [ADIS16505_2] = { + .name = "adis16505-2", + .num_channels = ARRAY_SIZE(adis16475_channels), + .channels = adis16475_channels, + .gyro_max_val = 1, + .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), + .accel_max_val = 78, + .accel_max_scale = 32000 << 16, + .temp_scale = 100, + .int_clk = 2000, + .max_dec = 1999, + .sync = adis16475_sync_mode, + /* pulse sync not supported */ + .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, + .has_burst32 = true, + .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts), + }, + [ADIS16505_3] = { + .name = "adis16505-3", + .num_channels = ARRAY_SIZE(adis16475_channels), + .channels = adis16475_channels, + .gyro_max_val = 1, + .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), + .accel_max_val = 78, + .accel_max_scale = 32000 << 16, + .temp_scale = 100, + .int_clk = 2000, + .max_dec = 1999, + .sync = adis16475_sync_mode, + /* pulse sync not supported */ + .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, + .has_burst32 = true, + .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts), + }, + [ADIS16507_1] = { + .name = "adis16507-1", + .num_channels = ARRAY_SIZE(adis16475_channels), + .channels = adis16475_channels, + .gyro_max_val = 1, + .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), + .accel_max_val = 392, + .accel_max_scale = 32000 << 16, + .temp_scale = 100, + .int_clk = 2000, + .max_dec = 1999, + .sync = adis16475_sync_mode, + /* pulse sync not supported */ + .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, + .has_burst32 = true, + .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts), + }, + [ADIS16507_2] = { + .name = "adis16507-2", + .num_channels = ARRAY_SIZE(adis16475_channels), + .channels = adis16475_channels, + .gyro_max_val = 1, + .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), + .accel_max_val = 392, + .accel_max_scale = 32000 << 16, + .temp_scale = 100, + .int_clk = 2000, + .max_dec = 1999, + .sync = adis16475_sync_mode, + /* pulse sync not supported */ + .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, + .has_burst32 = true, + .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts), + }, + [ADIS16507_3] = { + .name = "adis16507-3", + .num_channels = ARRAY_SIZE(adis16475_channels), + .channels = adis16475_channels, + .gyro_max_val = 1, + .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), + .accel_max_val = 392, + .accel_max_scale = 32000 << 16, + .temp_scale = 100, + .int_clk = 2000, + .max_dec = 1999, + .sync = adis16475_sync_mode, + /* pulse sync not supported */ + .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, + .has_burst32 = true, + .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts), + }, +}; + +static const struct iio_info adis16475_info = { + .read_raw = &adis16475_read_raw, + .write_raw = &adis16475_write_raw, + .update_scan_mode = adis_update_scan_mode, + .debugfs_reg_access = adis_debugfs_reg_access, +}; + +static struct adis_burst adis16475_burst = { + .en = true, + .reg_cmd = ADIS16475_REG_GLOB_CMD, + /* + * adis_update_scan_mode_burst() sets the burst length in respect with + * the number of channels and allocates 16 bits for each. However, + * adis1647x devices also need space for DIAG_STAT, DATA_CNTR or + * TIME_STAMP (depending on the clock mode but for us these bytes are + * don't care...) and CRC. + */ + .extra_len = 3 * sizeof(u16), + .burst_max_len = ADIS16475_BURST32_MAX_DATA, +}; + +static bool adis16475_validate_crc(const u8 *buffer, u16 crc, + const bool burst32) +{ + int i; + /* extra 6 elements for low gyro and accel */ + const u16 sz = burst32 ? ADIS16475_BURST32_MAX_DATA : + ADIS16475_BURST_MAX_DATA; + + for (i = 0; i < sz - 2; i++) + crc -= buffer[i]; + + return crc == 0; +} + +static void adis16475_burst32_check(struct adis16475 *st) +{ + int ret; + struct adis *adis = &st->adis; + + if (!st->info->has_burst32) + return; + + if (st->lsb_flag && !st->burst32) { + const u16 en = ADIS16500_BURST32(1); + + ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, + ADIS16500_BURST32_MASK, en); + if (ret) + return; + + st->burst32 = true; + + /* + * In 32-bit mode we need extra 2 bytes for all gyro + * and accel channels. + */ + adis->burst_extra_len = 6 * sizeof(u16); + adis->xfer[1].len += 6 * sizeof(u16); + dev_dbg(&adis->spi->dev, "Enable burst32 mode, xfer:%d", + adis->xfer[1].len); + + } else if (!st->lsb_flag && st->burst32) { + const u16 en = ADIS16500_BURST32(0); + + ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, + ADIS16500_BURST32_MASK, en); + if (ret) + return; + + st->burst32 = false; + + /* Remove the extra bits */ + adis->burst_extra_len = 0; + adis->xfer[1].len -= 6 * sizeof(u16); + dev_dbg(&adis->spi->dev, "Disable burst32 mode, xfer:%d\n", + adis->xfer[1].len); + } +} + +static irqreturn_t adis16475_trigger_handler(int irq, void *p) +{ + struct iio_poll_func *pf = p; + struct iio_dev *indio_dev = pf->indio_dev; + struct adis16475 *st = iio_priv(indio_dev); + struct adis *adis = &st->adis; + int ret, bit, i = 0; + __be16 *buffer; + u16 crc; + bool valid; + /* offset until the first element after gyro and accel */ + const u8 offset = st->burst32 ? 13 : 7; + const u32 cached_spi_speed_hz = adis->spi->max_speed_hz; + + adis->spi->max_speed_hz = ADIS16475_BURST_MAX_SPEED; + + ret = spi_sync(adis->spi, &adis->msg); + if (ret) + return ret; + + adis->spi->max_speed_hz = cached_spi_speed_hz; + buffer = adis->buffer; + + crc = be16_to_cpu(buffer[offset + 2]); + valid = adis16475_validate_crc(adis->buffer, crc, st->burst32); + if (!valid) { + dev_err(&adis->spi->dev, "Invalid crc\n"); + goto check_burst32; + } + + for_each_set_bit(bit, indio_dev->active_scan_mask, + indio_dev->masklength) { + /* + * When burst mode is used, system flags is the first data + * channel in the sequence, but the scan index is 7. + */ + switch (bit) { + case ADIS16475_SCAN_TEMP: + st->data[i++] = buffer[offset]; + break; + case ADIS16475_SCAN_GYRO_X ... ADIS16475_SCAN_ACCEL_Z: + /* + * The first 2 bytes on the received data are the + * DIAG_STAT reg, hence the +1 offset here... + */ + if (st->burst32) { + /* upper 16 */ + st->data[i++] = buffer[bit * 2 + 2]; + /* lower 16 */ + st->data[i++] = buffer[bit * 2 + 1]; + } else { + st->data[i++] = buffer[bit + 1]; + /* + * Don't bother in doing the manual read if the + * device supports burst32. burst32 will be + * enabled in the next call to + * adis16475_burst32_check()... + */ + if (st->lsb_flag && !st->info->has_burst32) { + u16 val = 0; + const u32 reg = ADIS16475_REG_X_GYRO_L + + bit * 4; + + adis_read_reg_16(adis, reg, &val); + st->data[i++] = cpu_to_be16(val); + } else { + /* lower not used */ + st->data[i++] = 0; + } + } + break; + } + } + + iio_push_to_buffers_with_timestamp(indio_dev, st->data, pf->timestamp); +check_burst32: + /* + * We only check the burst mode at the end of the current capture since + * it takes a full data ready cycle for the device to update the burst + * array. + */ + adis16475_burst32_check(st); + iio_trigger_notify_done(indio_dev->trig); + + return IRQ_HANDLED; +} + +static void adis16475_disable_clk(void *data) +{ + clk_disable_unprepare((struct clk *)data); +} + +static int adis16475_config_sync_mode(struct adis16475 *st) +{ + int ret; + struct device *dev = &st->adis.spi->dev; + const struct adis16475_sync *sync; + u32 sync_mode; + + /* default to internal clk */ + st->clk_freq = st->info->int_clk * 1000; + + ret = device_property_read_u32(dev, "adi,sync-mode", &sync_mode); + if (ret) + return 0; + + if (sync_mode >= st->info->num_sync) { + dev_err(dev, "Invalid sync mode: %u for %s\n", sync_mode, + st->info->name); + return -EINVAL; + } + + sync = &st->info->sync[sync_mode]; + + /* All the other modes require external input signal */ + if (sync->sync_mode != ADIS16475_SYNC_OUTPUT) { + struct clk *clk = devm_clk_get(dev, NULL); + + if (IS_ERR(clk)) + return PTR_ERR(clk); + + ret = clk_prepare_enable(clk); + if (ret) + return ret; + + ret = devm_add_action_or_reset(dev, adis16475_disable_clk, clk); + if (ret) + return ret; + + st->clk_freq = clk_get_rate(clk); + if (st->clk_freq < sync->min_rate || + st->clk_freq > sync->max_rate) { + dev_err(dev, + "Clk rate:%u not in a valid range:[%u %u]\n", + st->clk_freq, sync->min_rate, sync->max_rate); + return -EINVAL; + } + + if (sync->sync_mode == ADIS16475_SYNC_SCALED) { + u16 up_scale; + u32 scaled_out_freq = 0; + /* + * If we are in scaled mode, we must have an up_scale. + * In scaled mode the allowable input clock range is + * 1 Hz to 128 Hz, and the allowable output range is + * 1900 to 2100 Hz. Hence, a scale must be given to + * get the allowable output. + */ + ret = device_property_read_u32(dev, + "adi,scaled-output-hz", + &scaled_out_freq); + if (ret) { + dev_err(dev, "adi,scaled-output-hz must be given when in scaled sync mode"); + return -EINVAL; + } else if (scaled_out_freq < 1900 || + scaled_out_freq > 2100) { + dev_err(dev, "Invalid value: %u for adi,scaled-output-hz", + scaled_out_freq); + return -EINVAL; + } + + up_scale = DIV_ROUND_CLOSEST(scaled_out_freq, + st->clk_freq); + + ret = __adis_write_reg_16(&st->adis, + ADIS16475_REG_UP_SCALE, + up_scale); + if (ret) + return ret; + + st->clk_freq = scaled_out_freq; + } + + st->clk_freq *= 1000; + } + /* + * Keep in mind that the mask for the clk modes in adis1650* + * chips is different (1100 instead of 11100). However, we + * are not configuring BIT(4) in these chips and the default + * value is 0, so we are fine in doing the below operations. + * I'm keeping this for simplicity and avoiding extra variables + * in chip_info. + */ + ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, + ADIS16475_SYNC_MODE_MASK, sync->sync_mode); + if (ret) + return ret; + + usleep_range(250, 260); + + return 0; +} + +static int adis16475_config_irq_pin(struct adis16475 *st) +{ + int ret; + struct irq_data *desc; + u32 irq_type; + u16 val = 0; + u8 polarity; + struct spi_device *spi = st->adis.spi; + + desc = irq_get_irq_data(spi->irq); + if (!desc) { + dev_err(&spi->dev, "Could not find IRQ %d\n", spi->irq); + return -EINVAL; + } + /* + * It is possible to configure the data ready polarity. Furthermore, we + * need to update the adis struct if we want data ready as active low. + */ + irq_type = irqd_get_trigger_type(desc); + if (irq_type == IRQ_TYPE_EDGE_RISING) { + polarity = 1; + st->adis.irq_flag = IRQF_TRIGGER_RISING; + } else if (irq_type == IRQ_TYPE_EDGE_FALLING) { + polarity = 0; + st->adis.irq_flag = IRQF_TRIGGER_FALLING; + } else { + dev_err(&spi->dev, "Invalid interrupt type 0x%x specified\n", + irq_type); + return -EINVAL; + } + + val = ADIS16475_MSG_CTRL_DR_POL(polarity); + ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, + ADIS16475_MSG_CTRL_DR_POL_MASK, val); + if (ret) + return ret; + /* + * There is a delay writing to any bits written to the MSC_CTRL + * register. It should not be bigger than 200us, so 250 should be more + * than enough! + */ + usleep_range(250, 260); + + return 0; +} + +static const struct of_device_id adis16475_of_match[] = { + { .compatible = "adi,adis16470", + .data = &adis16475_chip_info[ADIS16470] }, + { .compatible = "adi,adis16475-1", + .data = &adis16475_chip_info[ADIS16475_1] }, + { .compatible = "adi,adis16475-2", + .data = &adis16475_chip_info[ADIS16475_2] }, + { .compatible = "adi,adis16475-3", + .data = &adis16475_chip_info[ADIS16475_3] }, + { .compatible = "adi,adis16477-1", + .data = &adis16475_chip_info[ADIS16477_1] }, + { .compatible = "adi,adis16477-2", + .data = &adis16475_chip_info[ADIS16477_2] }, + { .compatible = "adi,adis16477-3", + .data = &adis16475_chip_info[ADIS16477_3] }, + { .compatible = "adi,adis16465-1", + .data = &adis16475_chip_info[ADIS16465_1] }, + { .compatible = "adi,adis16465-2", + .data = &adis16475_chip_info[ADIS16465_2] }, + { .compatible = "adi,adis16465-3", + .data = &adis16475_chip_info[ADIS16465_3] }, + { .compatible = "adi,adis16467-1", + .data = &adis16475_chip_info[ADIS16467_1] }, + { .compatible = "adi,adis16467-2", + .data = &adis16475_chip_info[ADIS16467_2] }, + { .compatible = "adi,adis16467-3", + .data = &adis16475_chip_info[ADIS16467_3] }, + { .compatible = "adi,adis16500", + .data = &adis16475_chip_info[ADIS16500] }, + { .compatible = "adi,adis16505-1", + .data = &adis16475_chip_info[ADIS16505_1] }, + { .compatible = "adi,adis16505-2", + .data = &adis16475_chip_info[ADIS16505_2] }, + { .compatible = "adi,adis16505-3", + .data = &adis16475_chip_info[ADIS16505_3] }, + { .compatible = "adi,adis16507-1", + .data = &adis16475_chip_info[ADIS16507_1] }, + { .compatible = "adi,adis16507-2", + .data = &adis16475_chip_info[ADIS16507_2] }, + { .compatible = "adi,adis16507-3", + .data = &adis16475_chip_info[ADIS16507_3] }, + { }, +}; +MODULE_DEVICE_TABLE(of, adis16475_of_match); + +static int adis16475_probe(struct spi_device *spi) +{ + struct iio_dev *indio_dev; + struct adis16475 *st; + int ret; + + indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st = iio_priv(indio_dev); + spi_set_drvdata(spi, indio_dev); + st->adis.burst = &adis16475_burst; + + st->info = device_get_match_data(&spi->dev); + if (!st->info) + return -EINVAL; + + ret = adis_init(&st->adis, indio_dev, spi, &st->info->adis_data); + if (ret) + return ret; + + indio_dev->dev.parent = &spi->dev; + indio_dev->name = st->info->name; + indio_dev->channels = st->info->channels; + indio_dev->num_channels = st->info->num_channels; + indio_dev->info = &adis16475_info; + indio_dev->modes = INDIO_DIRECT_MODE; + + ret = __adis_initial_startup(&st->adis); + if (ret) + return ret; + + ret = adis16475_config_irq_pin(st); + if (ret) + return ret; + + ret = adis16475_config_sync_mode(st); + if (ret) + return ret; + + ret = devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev, + adis16475_trigger_handler); + if (ret) + return ret; + + adis16475_enable_irq(&st->adis, false); + + ret = devm_iio_device_register(&spi->dev, indio_dev); + if (ret) + return ret; + + adis16475_debugfs_init(indio_dev); + + return 0; +} + +static struct spi_driver adis16475_driver = { + .driver = { + .name = "adis16475", + .of_match_table = adis16475_of_match, + }, + .probe = adis16475_probe, +}; +module_spi_driver(adis16475_driver); + +MODULE_AUTHOR("Nuno Sa "); +MODULE_DESCRIPTION("Analog Devices ADIS16475 IMU driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/iio/imu/adis16480.c b/drivers/iio/imu/adis16480.c index cfae0e4476e7..6a471eee110e 100644 --- a/drivers/iio/imu/adis16480.c +++ b/drivers/iio/imu/adis16480.c @@ -284,22 +284,18 @@ DEFINE_DEBUGFS_ATTRIBUTE(adis16480_flash_count_fops, static int adis16480_debugfs_init(struct iio_dev *indio_dev) { struct adis16480 *adis16480 = iio_priv(indio_dev); + struct dentry *d = iio_get_debugfs_dentry(indio_dev); debugfs_create_file_unsafe("firmware_revision", 0400, - indio_dev->debugfs_dentry, adis16480, - &adis16480_firmware_revision_fops); + d, adis16480, &adis16480_firmware_revision_fops); debugfs_create_file_unsafe("firmware_date", 0400, - indio_dev->debugfs_dentry, adis16480, - &adis16480_firmware_date_fops); + d, adis16480, &adis16480_firmware_date_fops); debugfs_create_file_unsafe("serial_number", 0400, - indio_dev->debugfs_dentry, adis16480, - &adis16480_serial_number_fops); + d, adis16480, &adis16480_serial_number_fops); debugfs_create_file_unsafe("product_id", 0400, - indio_dev->debugfs_dentry, adis16480, - &adis16480_product_id_fops); + d, adis16480, &adis16480_product_id_fops); debugfs_create_file_unsafe("flash_count", 0400, - indio_dev->debugfs_dentry, adis16480, - &adis16480_flash_count_fops); + d, adis16480, &adis16480_flash_count_fops); return 0; } diff --git a/drivers/iio/imu/adis_buffer.c b/drivers/iio/imu/adis_buffer.c index 04e5e2a0fd6b..5b4225ee09b9 100644 --- a/drivers/iio/imu/adis_buffer.c +++ b/drivers/iio/imu/adis_buffer.c @@ -23,25 +23,30 @@ static int adis_update_scan_mode_burst(struct iio_dev *indio_dev, const unsigned long *scan_mask) { struct adis *adis = iio_device_get_drvdata(indio_dev); - unsigned int burst_length; + unsigned int burst_length, burst_max_length; u8 *tx; /* All but the timestamp channel */ burst_length = (indio_dev->num_channels - 1) * sizeof(u16); - burst_length += adis->burst->extra_len; + burst_length += adis->burst->extra_len + adis->burst_extra_len; + + if (adis->burst->burst_max_len) + burst_max_length = adis->burst->burst_max_len; + else + burst_max_length = burst_length; adis->xfer = kcalloc(2, sizeof(*adis->xfer), GFP_KERNEL); if (!adis->xfer) return -ENOMEM; - adis->buffer = kzalloc(burst_length + sizeof(u16), GFP_KERNEL); + adis->buffer = kzalloc(burst_max_length + sizeof(u16), GFP_KERNEL); if (!adis->buffer) { kfree(adis->xfer); adis->xfer = NULL; return -ENOMEM; } - tx = adis->buffer + burst_length; + tx = adis->buffer + burst_max_length; tx[0] = ADIS_READ_REG(adis->burst->reg_cmd); tx[1] = 0; @@ -156,6 +161,14 @@ static irqreturn_t adis_trigger_handler(int irq, void *p) return IRQ_HANDLED; } +static void adis_buffer_cleanup(void *arg) +{ + struct adis *adis = arg; + + kfree(adis->buffer); + kfree(adis->xfer); +} + /** * adis_setup_buffer_and_trigger() - Sets up buffer and trigger for the adis device * @adis: The adis device. @@ -198,6 +211,43 @@ error_buffer_cleanup: } EXPORT_SYMBOL_GPL(adis_setup_buffer_and_trigger); +/** + * devm_adis_setup_buffer_and_trigger() - Sets up buffer and trigger for + * the managed adis device + * @adis: The adis device + * @indio_dev: The IIO device + * @trigger_handler: Optional trigger handler, may be NULL. + * + * Returns 0 on success, a negative error code otherwise. + * + * This function perfoms exactly the same as adis_setup_buffer_and_trigger() + */ +int +devm_adis_setup_buffer_and_trigger(struct adis *adis, struct iio_dev *indio_dev, + irq_handler_t trigger_handler) +{ + int ret; + + if (!trigger_handler) + trigger_handler = adis_trigger_handler; + + ret = devm_iio_triggered_buffer_setup(&adis->spi->dev, indio_dev, + &iio_pollfunc_store_time, + trigger_handler, NULL); + if (ret) + return ret; + + if (adis->spi->irq) { + ret = devm_adis_probe_trigger(adis, indio_dev); + if (ret) + return ret; + } + + return devm_add_action_or_reset(&adis->spi->dev, adis_buffer_cleanup, + adis); +} +EXPORT_SYMBOL_GPL(devm_adis_setup_buffer_and_trigger); + /** * adis_cleanup_buffer_and_trigger() - Free buffer and trigger resources * @adis: The adis device. diff --git a/drivers/iio/imu/adis_trigger.c b/drivers/iio/imu/adis_trigger.c index 8b9cd02c0f9f..8afe71947c00 100644 --- a/drivers/iio/imu/adis_trigger.c +++ b/drivers/iio/imu/adis_trigger.c @@ -27,6 +27,34 @@ static const struct iio_trigger_ops adis_trigger_ops = { .set_trigger_state = &adis_data_rdy_trigger_set_state, }; +static void adis_trigger_setup(struct adis *adis) +{ + adis->trig->dev.parent = &adis->spi->dev; + adis->trig->ops = &adis_trigger_ops; + iio_trigger_set_drvdata(adis->trig, adis); +} + +static int adis_validate_irq_flag(struct adis *adis) +{ + /* + * Typically this devices have data ready either on the rising edge or + * on the falling edge of the data ready pin. This checks enforces that + * one of those is set in the drivers... It defaults to + * IRQF_TRIGGER_RISING for backward compatibility wiht devices that + * don't support changing the pin polarity. + */ + if (!adis->irq_flag) { + adis->irq_flag = IRQF_TRIGGER_RISING; + return 0; + } else if (adis->irq_flag != IRQF_TRIGGER_RISING && + adis->irq_flag != IRQF_TRIGGER_FALLING) { + dev_err(&adis->spi->dev, "Invalid IRQ mask: %08lx\n", + adis->irq_flag); + return -EINVAL; + } + + return 0; +} /** * adis_probe_trigger() - Sets up trigger for a adis device * @adis: The adis device @@ -45,13 +73,15 @@ int adis_probe_trigger(struct adis *adis, struct iio_dev *indio_dev) if (adis->trig == NULL) return -ENOMEM; - adis->trig->dev.parent = &adis->spi->dev; - adis->trig->ops = &adis_trigger_ops; - iio_trigger_set_drvdata(adis->trig, adis); + adis_trigger_setup(adis); + + ret = adis_validate_irq_flag(adis); + if (ret) + return ret; ret = request_irq(adis->spi->irq, &iio_trigger_generic_data_rdy_poll, - IRQF_TRIGGER_RISING, + adis->irq_flag, indio_dev->name, adis->trig); if (ret) @@ -73,6 +103,40 @@ error_free_trig: } EXPORT_SYMBOL_GPL(adis_probe_trigger); +/** + * devm_adis_probe_trigger() - Sets up trigger for a managed adis device + * @adis: The adis device + * @indio_dev: The IIO device + * + * Returns 0 on success or a negative error code + */ +int devm_adis_probe_trigger(struct adis *adis, struct iio_dev *indio_dev) +{ + int ret; + + adis->trig = devm_iio_trigger_alloc(&adis->spi->dev, "%s-dev%d", + indio_dev->name, indio_dev->id); + if (!adis->trig) + return -ENOMEM; + + adis_trigger_setup(adis); + + ret = adis_validate_irq_flag(adis); + if (ret) + return ret; + + ret = devm_request_irq(&adis->spi->dev, adis->spi->irq, + &iio_trigger_generic_data_rdy_poll, + adis->irq_flag, + indio_dev->name, + adis->trig); + if (ret) + return ret; + + return devm_iio_trigger_register(&adis->spi->dev, adis->trig); +} +EXPORT_SYMBOL_GPL(devm_adis_probe_trigger); + /** * adis_remove_trigger() - Remove trigger for a adis devices * @adis: The adis device diff --git a/drivers/iio/imu/bmi160/bmi160_i2c.c b/drivers/iio/imu/bmi160/bmi160_i2c.c index e36f5e82d400..26398614eddf 100644 --- a/drivers/iio/imu/bmi160/bmi160_i2c.c +++ b/drivers/iio/imu/bmi160/bmi160_i2c.c @@ -24,8 +24,8 @@ static int bmi160_i2c_probe(struct i2c_client *client, regmap = devm_regmap_init_i2c(client, &bmi160_regmap_config); if (IS_ERR(regmap)) { - dev_err(&client->dev, "Failed to register i2c regmap %d\n", - (int)PTR_ERR(regmap)); + dev_err(&client->dev, "Failed to register i2c regmap: %pe\n", + regmap); return PTR_ERR(regmap); } diff --git a/drivers/iio/imu/bmi160/bmi160_spi.c b/drivers/iio/imu/bmi160/bmi160_spi.c index c19e3df35559..61389b41c6d9 100644 --- a/drivers/iio/imu/bmi160/bmi160_spi.c +++ b/drivers/iio/imu/bmi160/bmi160_spi.c @@ -20,8 +20,8 @@ static int bmi160_spi_probe(struct spi_device *spi) regmap = devm_regmap_init_spi(spi, &bmi160_regmap_config); if (IS_ERR(regmap)) { - dev_err(&spi->dev, "Failed to register spi regmap %d\n", - (int)PTR_ERR(regmap)); + dev_err(&spi->dev, "Failed to register spi regmap: %pe\n", + regmap); return PTR_ERR(regmap); } return bmi160_core_probe(&spi->dev, regmap, id->name, true); diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_acpi.c b/drivers/iio/imu/inv_mpu6050/inv_mpu_acpi.c index 2f8560ba4572..c27d06035c8b 100644 --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_acpi.c +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_acpi.c @@ -135,6 +135,7 @@ int inv_mpu_acpi_create_mux_client(struct i2c_client *client) st->mux_client = NULL; if (ACPI_HANDLE(&client->dev)) { struct i2c_board_info info; + struct i2c_client *mux_client; struct acpi_device *adev; int ret = -1; @@ -172,9 +173,10 @@ int inv_mpu_acpi_create_mux_client(struct i2c_client *client) } else return 0; /* no secondary addr, which is OK */ } - st->mux_client = i2c_new_device(st->muxc->adapter[0], &info); - if (!st->mux_client) - return -ENODEV; + mux_client = i2c_new_client_device(st->muxc->adapter[0], &info); + if (IS_ERR(mux_client)) + return PTR_ERR(mux_client); + st->mux_client = mux_client; } return 0; diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c b/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c index 0b8d2f7a0165..4d604fe842e5 100644 --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c @@ -526,7 +526,7 @@ static int inv_mpu6050_sensor_set(struct inv_mpu6050_state *st, int reg, __be16 d = cpu_to_be16(val); ind = (axis - IIO_MOD_X) * 2; - result = regmap_bulk_write(st->map, reg + ind, (u8 *)&d, 2); + result = regmap_bulk_write(st->map, reg + ind, &d, sizeof(d)); if (result) return -EINVAL; @@ -540,7 +540,7 @@ static int inv_mpu6050_sensor_show(struct inv_mpu6050_state *st, int reg, __be16 d; ind = (axis - IIO_MOD_X) * 2; - result = regmap_bulk_read(st->map, reg + ind, (u8 *)&d, 2); + result = regmap_bulk_read(st->map, reg + ind, &d, sizeof(d)); if (result) return -EINVAL; *val = (short)be16_to_cpup(&d); @@ -1248,12 +1248,31 @@ static const struct attribute_group inv_attribute_group = { .attrs = inv_attributes }; +static int inv_mpu6050_reg_access(struct iio_dev *indio_dev, + unsigned int reg, + unsigned int writeval, + unsigned int *readval) +{ + struct inv_mpu6050_state *st = iio_priv(indio_dev); + int ret; + + mutex_lock(&st->lock); + if (readval) + ret = regmap_read(st->map, reg, readval); + else + ret = regmap_write(st->map, reg, writeval); + mutex_unlock(&st->lock); + + return ret; +} + static const struct iio_info mpu_info = { .read_raw = &inv_mpu6050_read_raw, .write_raw = &inv_mpu6050_write_raw, .write_raw_get_fmt = &inv_write_raw_get_fmt, .attrs = &inv_attribute_group, .validate_trigger = inv_mpu6050_validate_trigger, + .debugfs_reg_access = &inv_mpu6050_reg_access, }; /** diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_i2c.c b/drivers/iio/imu/inv_mpu6050/inv_mpu_i2c.c index 6993d3b87bb0..28cfae1e61cf 100644 --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_i2c.c +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_i2c.c @@ -122,8 +122,8 @@ static int inv_mpu_probe(struct i2c_client *client, regmap = devm_regmap_init_i2c(client, &inv_mpu_regmap_config); if (IS_ERR(regmap)) { - dev_err(&client->dev, "Failed to register i2c regmap %d\n", - (int)PTR_ERR(regmap)); + dev_err(&client->dev, "Failed to register i2c regmap: %pe\n", + regmap); return PTR_ERR(regmap); } diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_spi.c b/drivers/iio/imu/inv_mpu6050/inv_mpu_spi.c index 673b198e6368..6f968ce687e1 100644 --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_spi.c +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_spi.c @@ -53,8 +53,8 @@ static int inv_mpu_probe(struct spi_device *spi) regmap = devm_regmap_init_spi(spi, &inv_mpu_regmap_config); if (IS_ERR(regmap)) { - dev_err(&spi->dev, "Failed to register spi regmap %d\n", - (int)PTR_ERR(regmap)); + dev_err(&spi->dev, "Failed to register spi regmap: %pe\n", + regmap); return PTR_ERR(regmap); } diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h index 41cb20cb3809..b56df409ed0f 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h @@ -111,7 +111,7 @@ struct st_lsm6dsx_odr { u8 val; }; -#define ST_LSM6DSX_ODR_LIST_SIZE 6 +#define ST_LSM6DSX_ODR_LIST_SIZE 8 struct st_lsm6dsx_odr_table_entry { struct st_lsm6dsx_reg reg; diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c index 4426524b59f2..0b776cb91928 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c @@ -27,7 +27,8 @@ * - FIFO size: 4KB * * - LSM6DSO/LSM6DSOX/ASM330LHH/LSM6DSR/ISM330DHCX: - * - Accelerometer/Gyroscope supported ODR [Hz]: 13, 26, 52, 104, 208, 416 + * - Accelerometer/Gyroscope supported ODR [Hz]: 13, 26, 52, 104, 208, 416, + * 833 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16 * - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000 * - FIFO size: 3KB @@ -791,7 +792,8 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = { .odr_avl[3] = { 104000, 0x04 }, .odr_avl[4] = { 208000, 0x05 }, .odr_avl[5] = { 416000, 0x06 }, - .odr_len = 6, + .odr_avl[6] = { 833000, 0x07 }, + .odr_len = 7, }, [ST_LSM6DSX_ID_GYRO] = { .reg = { @@ -804,7 +806,8 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = { .odr_avl[3] = { 104000, 0x04 }, .odr_avl[4] = { 208000, 0x05 }, .odr_avl[5] = { 416000, 0x06 }, - .odr_len = 6, + .odr_avl[6] = { 833000, 0x07 }, + .odr_len = 7, }, }, .fs_table = { @@ -994,7 +997,8 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = { .odr_avl[3] = { 104000, 0x04 }, .odr_avl[4] = { 208000, 0x05 }, .odr_avl[5] = { 416000, 0x06 }, - .odr_len = 6, + .odr_avl[6] = { 833000, 0x07 }, + .odr_len = 7, }, [ST_LSM6DSX_ID_GYRO] = { .reg = { @@ -1007,7 +1011,8 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = { .odr_avl[3] = { 104000, 0x04 }, .odr_avl[4] = { 208000, 0x05 }, .odr_avl[5] = { 416000, 0x06 }, - .odr_len = 6, + .odr_avl[6] = { 833000, 0x07 }, + .odr_len = 7, }, }, .fs_table = { @@ -1171,7 +1176,8 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = { .odr_avl[3] = { 104000, 0x04 }, .odr_avl[4] = { 208000, 0x05 }, .odr_avl[5] = { 416000, 0x06 }, - .odr_len = 6, + .odr_avl[6] = { 833000, 0x07 }, + .odr_len = 7, }, [ST_LSM6DSX_ID_GYRO] = { .reg = { @@ -1184,7 +1190,8 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = { .odr_avl[3] = { 104000, 0x04 }, .odr_avl[4] = { 208000, 0x05 }, .odr_avl[5] = { 416000, 0x06 }, - .odr_len = 6, + .odr_avl[6] = { 833000, 0x07 }, + .odr_len = 7, }, }, .fs_table = { diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c index 1cf98195f84d..c1f83fe0d8da 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c @@ -88,6 +88,69 @@ static const struct st_lsm6dsx_ext_dev_settings st_lsm6dsx_ext_dev_table[] = { .len = 6, }, }, + /* LIS3MDL */ + { + .i2c_addr = { 0x1e }, + .wai = { + .addr = 0x0f, + .val = 0x3d, + }, + .id = ST_LSM6DSX_ID_MAGN, + .odr_table = { + .reg = { + .addr = 0x20, + .mask = GENMASK(4, 2), + }, + .odr_avl[0] = { 1000, 0x0 }, + .odr_avl[1] = { 2000, 0x1 }, + .odr_avl[2] = { 3000, 0x2 }, + .odr_avl[3] = { 5000, 0x3 }, + .odr_avl[4] = { 10000, 0x4 }, + .odr_avl[5] = { 20000, 0x5 }, + .odr_avl[6] = { 40000, 0x6 }, + .odr_avl[7] = { 80000, 0x7 }, + .odr_len = 8, + }, + .fs_table = { + .reg = { + .addr = 0x21, + .mask = GENMASK(6, 5), + }, + .fs_avl[0] = { + .gain = 146, + .val = 0x00, + }, /* 4000 uG/LSB */ + .fs_avl[1] = { + .gain = 292, + .val = 0x01, + }, /* 8000 uG/LSB */ + .fs_avl[2] = { + .gain = 438, + .val = 0x02, + }, /* 12000 uG/LSB */ + .fs_avl[3] = { + .gain = 584, + .val = 0x03, + }, /* 16000 uG/LSB */ + .fs_len = 4, + }, + .pwr_table = { + .reg = { + .addr = 0x22, + .mask = GENMASK(1, 0), + }, + .off_val = 0x2, + .on_val = 0x0, + }, + .bdu = { + .addr = 0x24, + .mask = BIT(6), + }, + .out = { + .addr = 0x28, + .len = 6, + }, + }, }; static void st_lsm6dsx_shub_wait_complete(struct st_lsm6dsx_hw *hw) @@ -518,6 +581,36 @@ st_lsm6dsx_shub_read_raw(struct iio_dev *iio_dev, return ret; } +static int +st_lsm6dsx_shub_set_full_scale(struct st_lsm6dsx_sensor *sensor, + u32 gain) +{ + const struct st_lsm6dsx_fs_table_entry *fs_table; + int i, err; + + fs_table = &sensor->ext_info.settings->fs_table; + if (!fs_table->reg.addr) + return -ENOTSUPP; + + for (i = 0; i < fs_table->fs_len; i++) { + if (fs_table->fs_avl[i].gain == gain) + break; + } + + if (i == fs_table->fs_len) + return -EINVAL; + + err = st_lsm6dsx_shub_write_with_mask(sensor, fs_table->reg.addr, + fs_table->reg.mask, + fs_table->fs_avl[i].val); + if (err < 0) + return err; + + sensor->gain = gain; + + return 0; +} + static int st_lsm6dsx_shub_write_raw(struct iio_dev *iio_dev, struct iio_chan_spec const *chan, @@ -554,6 +647,9 @@ st_lsm6dsx_shub_write_raw(struct iio_dev *iio_dev, } break; } + case IIO_CHAN_INFO_SCALE: + err = st_lsm6dsx_shub_set_full_scale(sensor, val2); + break; default: err = -EINVAL; break; diff --git a/drivers/iio/industrialio-buffer.c b/drivers/iio/industrialio-buffer.c index 4ada5592aa2b..9fa238c0a7d4 100644 --- a/drivers/iio/industrialio-buffer.c +++ b/drivers/iio/industrialio-buffer.c @@ -189,10 +189,12 @@ __poll_t iio_buffer_poll(struct file *filp, */ void iio_buffer_wakeup_poll(struct iio_dev *indio_dev) { - if (!indio_dev->buffer) + struct iio_buffer *buffer = indio_dev->buffer; + + if (!buffer) return; - wake_up(&indio_dev->buffer->pollq); + wake_up(&buffer->pollq); } void iio_buffer_init(struct iio_buffer *buffer) @@ -262,10 +264,11 @@ static ssize_t iio_scan_el_show(struct device *dev, { int ret; struct iio_dev *indio_dev = dev_to_iio_dev(dev); + struct iio_buffer *buffer = indio_dev->buffer; /* Ensure ret is 0 or 1. */ ret = !!test_bit(to_iio_dev_attr(attr)->address, - indio_dev->buffer->scan_mask); + buffer->scan_mask); return sprintf(buf, "%d\n", ret); } @@ -316,8 +319,7 @@ static int iio_scan_mask_set(struct iio_dev *indio_dev, const unsigned long *mask; unsigned long *trialmask; - trialmask = kcalloc(BITS_TO_LONGS(indio_dev->masklength), - sizeof(*trialmask), GFP_KERNEL); + trialmask = bitmap_zalloc(indio_dev->masklength, GFP_KERNEL); if (trialmask == NULL) return -ENOMEM; if (!indio_dev->masklength) { @@ -382,7 +384,7 @@ static ssize_t iio_scan_el_store(struct device *dev, if (ret < 0) return ret; mutex_lock(&indio_dev->mlock); - if (iio_buffer_is_active(indio_dev->buffer)) { + if (iio_buffer_is_active(buffer)) { ret = -EBUSY; goto error_ret; } @@ -411,7 +413,9 @@ static ssize_t iio_scan_el_ts_show(struct device *dev, char *buf) { struct iio_dev *indio_dev = dev_to_iio_dev(dev); - return sprintf(buf, "%d\n", indio_dev->buffer->scan_timestamp); + struct iio_buffer *buffer = indio_dev->buffer; + + return sprintf(buf, "%d\n", buffer->scan_timestamp); } static ssize_t iio_scan_el_ts_store(struct device *dev, @@ -421,6 +425,7 @@ static ssize_t iio_scan_el_ts_store(struct device *dev, { int ret; struct iio_dev *indio_dev = dev_to_iio_dev(dev); + struct iio_buffer *buffer = indio_dev->buffer; bool state; ret = strtobool(buf, &state); @@ -428,11 +433,11 @@ static ssize_t iio_scan_el_ts_store(struct device *dev, return ret; mutex_lock(&indio_dev->mlock); - if (iio_buffer_is_active(indio_dev->buffer)) { + if (iio_buffer_is_active(buffer)) { ret = -EBUSY; goto error_ret; } - indio_dev->buffer->scan_timestamp = state; + buffer->scan_timestamp = state; error_ret: mutex_unlock(&indio_dev->mlock); @@ -440,10 +445,10 @@ error_ret: } static int iio_buffer_add_channel_sysfs(struct iio_dev *indio_dev, + struct iio_buffer *buffer, const struct iio_chan_spec *chan) { int ret, attrcount = 0; - struct iio_buffer *buffer = indio_dev->buffer; ret = __iio_add_chan_devattr("index", chan, @@ -519,7 +524,7 @@ static ssize_t iio_buffer_write_length(struct device *dev, return len; mutex_lock(&indio_dev->mlock); - if (iio_buffer_is_active(indio_dev->buffer)) { + if (iio_buffer_is_active(buffer)) { ret = -EBUSY; } else { buffer->access->set_length(buffer, val); @@ -540,7 +545,9 @@ static ssize_t iio_buffer_show_enable(struct device *dev, char *buf) { struct iio_dev *indio_dev = dev_to_iio_dev(dev); - return sprintf(buf, "%d\n", iio_buffer_is_active(indio_dev->buffer)); + struct iio_buffer *buffer = indio_dev->buffer; + + return sprintf(buf, "%d\n", iio_buffer_is_active(buffer)); } static unsigned int iio_storage_bytes_for_si(struct iio_dev *indio_dev, @@ -687,6 +694,13 @@ static int iio_verify_update(struct iio_dev *indio_dev, bool scan_timestamp; unsigned int modes; + if (insert_buffer && + bitmap_empty(insert_buffer->scan_mask, indio_dev->masklength)) { + dev_dbg(&indio_dev->dev, + "At least one scan element must be enabled first\n"); + return -EINVAL; + } + memset(config, 0, sizeof(*config)); config->watermark = ~0; @@ -913,6 +927,7 @@ static int iio_enable_buffers(struct iio_dev *indio_dev, indio_dev->active_scan_mask = config->scan_mask; indio_dev->scan_timestamp = config->scan_timestamp; indio_dev->scan_bytes = config->scan_bytes; + indio_dev->currentmode = config->mode; iio_update_demux(indio_dev); @@ -948,8 +963,6 @@ static int iio_enable_buffers(struct iio_dev *indio_dev, goto err_disable_buffers; } - indio_dev->currentmode = config->mode; - if (indio_dev->setup_ops->postenable) { ret = indio_dev->setup_ops->postenable(indio_dev); if (ret) { @@ -966,10 +979,10 @@ err_disable_buffers: buffer_list) iio_buffer_disable(buffer, indio_dev); err_run_postdisable: - indio_dev->currentmode = INDIO_DIRECT_MODE; if (indio_dev->setup_ops->postdisable) indio_dev->setup_ops->postdisable(indio_dev); err_undo_config: + indio_dev->currentmode = INDIO_DIRECT_MODE; indio_dev->active_scan_mask = NULL; return ret; @@ -1004,8 +1017,6 @@ static int iio_disable_buffers(struct iio_dev *indio_dev) ret = ret2; } - indio_dev->currentmode = INDIO_DIRECT_MODE; - if (indio_dev->setup_ops->postdisable) { ret2 = indio_dev->setup_ops->postdisable(indio_dev); if (ret2 && !ret) @@ -1014,6 +1025,7 @@ static int iio_disable_buffers(struct iio_dev *indio_dev) iio_free_scan_mask(indio_dev, indio_dev->active_scan_mask); indio_dev->active_scan_mask = NULL; + indio_dev->currentmode = INDIO_DIRECT_MODE; return ret; } @@ -1123,6 +1135,7 @@ static ssize_t iio_buffer_store_enable(struct device *dev, int ret; bool requested_state; struct iio_dev *indio_dev = dev_to_iio_dev(dev); + struct iio_buffer *buffer = indio_dev->buffer; bool inlist; ret = strtobool(buf, &requested_state); @@ -1132,17 +1145,15 @@ static ssize_t iio_buffer_store_enable(struct device *dev, mutex_lock(&indio_dev->mlock); /* Find out if it is in the list */ - inlist = iio_buffer_is_active(indio_dev->buffer); + inlist = iio_buffer_is_active(buffer); /* Already in desired state */ if (inlist == requested_state) goto done; if (requested_state) - ret = __iio_update_buffers(indio_dev, - indio_dev->buffer, NULL); + ret = __iio_update_buffers(indio_dev, buffer, NULL); else - ret = __iio_update_buffers(indio_dev, - NULL, indio_dev->buffer); + ret = __iio_update_buffers(indio_dev, NULL, buffer); done: mutex_unlock(&indio_dev->mlock); @@ -1184,7 +1195,7 @@ static ssize_t iio_buffer_store_watermark(struct device *dev, goto out; } - if (iio_buffer_is_active(indio_dev->buffer)) { + if (iio_buffer_is_active(buffer)) { ret = -EBUSY; goto out; } @@ -1201,11 +1212,9 @@ static ssize_t iio_dma_show_data_available(struct device *dev, char *buf) { struct iio_dev *indio_dev = dev_to_iio_dev(dev); - size_t bytes; + struct iio_buffer *buffer = indio_dev->buffer; - bytes = iio_buffer_data_available(indio_dev->buffer); - - return sprintf(buf, "%zu\n", bytes); + return sprintf(buf, "%zu\n", iio_buffer_data_available(buffer)); } static DEVICE_ATTR(length, S_IRUGO | S_IWUSR, iio_buffer_read_length, @@ -1233,7 +1242,7 @@ int iio_buffer_alloc_sysfs_and_mask(struct iio_dev *indio_dev) struct iio_dev_attr *p; struct attribute **attr; struct iio_buffer *buffer = indio_dev->buffer; - int ret, i, attrn, attrcount, attrcount_orig = 0; + int ret, i, attrn, attrcount; const struct iio_chan_spec *channels; channels = indio_dev->channels; @@ -1277,12 +1286,7 @@ int iio_buffer_alloc_sysfs_and_mask(struct iio_dev *indio_dev) indio_dev->groups[indio_dev->groupcounter++] = &buffer->buffer_group; - if (buffer->scan_el_attrs != NULL) { - attr = buffer->scan_el_attrs->attrs; - while (*attr++ != NULL) - attrcount_orig++; - } - attrcount = attrcount_orig; + attrcount = 0; INIT_LIST_HEAD(&buffer->scan_el_dev_attr_list); channels = indio_dev->channels; if (channels) { @@ -1291,7 +1295,7 @@ int iio_buffer_alloc_sysfs_and_mask(struct iio_dev *indio_dev) if (channels[i].scan_index < 0) continue; - ret = iio_buffer_add_channel_sysfs(indio_dev, + ret = iio_buffer_add_channel_sysfs(indio_dev, buffer, &channels[i]); if (ret < 0) goto error_cleanup_dynamic; @@ -1319,10 +1323,7 @@ int iio_buffer_alloc_sysfs_and_mask(struct iio_dev *indio_dev) ret = -ENOMEM; goto error_free_scan_mask; } - if (buffer->scan_el_attrs) - memcpy(buffer->scan_el_group.attrs, buffer->scan_el_attrs, - sizeof(buffer->scan_el_group.attrs[0])*attrcount_orig); - attrn = attrcount_orig; + attrn = 0; list_for_each_entry(p, &buffer->scan_el_dev_attr_list, l) buffer->scan_el_group.attrs[attrn++] = &p->dev_attr.attr; @@ -1334,20 +1335,22 @@ error_free_scan_mask: bitmap_free(buffer->scan_mask); error_cleanup_dynamic: iio_free_chan_devattr_list(&buffer->scan_el_dev_attr_list); - kfree(indio_dev->buffer->buffer_group.attrs); + kfree(buffer->buffer_group.attrs); return ret; } void iio_buffer_free_sysfs_and_mask(struct iio_dev *indio_dev) { - if (!indio_dev->buffer) + struct iio_buffer *buffer = indio_dev->buffer; + + if (!buffer) return; - bitmap_free(indio_dev->buffer->scan_mask); - kfree(indio_dev->buffer->buffer_group.attrs); - kfree(indio_dev->buffer->scan_el_group.attrs); - iio_free_chan_devattr_list(&indio_dev->buffer->scan_el_dev_attr_list); + bitmap_free(buffer->scan_mask); + kfree(buffer->buffer_group.attrs); + kfree(buffer->scan_el_group.attrs); + iio_free_chan_devattr_list(&buffer->scan_el_dev_attr_list); } /** diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-core.c index 24f7bbff4938..1527f01a44f1 100644 --- a/drivers/iio/industrialio-core.c +++ b/drivers/iio/industrialio-core.c @@ -572,46 +572,46 @@ static ssize_t __iio_format_value(char *buf, size_t len, unsigned int type, switch (type) { case IIO_VAL_INT: - return snprintf(buf, len, "%d", vals[0]); + return scnprintf(buf, len, "%d", vals[0]); case IIO_VAL_INT_PLUS_MICRO_DB: scale_db = true; /* fall through */ case IIO_VAL_INT_PLUS_MICRO: if (vals[1] < 0) - return snprintf(buf, len, "-%d.%06u%s", abs(vals[0]), + return scnprintf(buf, len, "-%d.%06u%s", abs(vals[0]), -vals[1], scale_db ? " dB" : ""); else - return snprintf(buf, len, "%d.%06u%s", vals[0], vals[1], + return scnprintf(buf, len, "%d.%06u%s", vals[0], vals[1], scale_db ? " dB" : ""); case IIO_VAL_INT_PLUS_NANO: if (vals[1] < 0) - return snprintf(buf, len, "-%d.%09u", abs(vals[0]), + return scnprintf(buf, len, "-%d.%09u", abs(vals[0]), -vals[1]); else - return snprintf(buf, len, "%d.%09u", vals[0], vals[1]); + return scnprintf(buf, len, "%d.%09u", vals[0], vals[1]); case IIO_VAL_FRACTIONAL: tmp = div_s64((s64)vals[0] * 1000000000LL, vals[1]); tmp1 = vals[1]; tmp0 = (int)div_s64_rem(tmp, 1000000000, &tmp1); - return snprintf(buf, len, "%d.%09u", tmp0, abs(tmp1)); + return scnprintf(buf, len, "%d.%09u", tmp0, abs(tmp1)); case IIO_VAL_FRACTIONAL_LOG2: tmp = shift_right((s64)vals[0] * 1000000000LL, vals[1]); tmp0 = (int)div_s64_rem(tmp, 1000000000LL, &tmp1); - return snprintf(buf, len, "%d.%09u", tmp0, abs(tmp1)); + return scnprintf(buf, len, "%d.%09u", tmp0, abs(tmp1)); case IIO_VAL_INT_MULTIPLE: { int i; int l = 0; for (i = 0; i < size; ++i) { - l += snprintf(&buf[l], len - l, "%d ", vals[i]); + l += scnprintf(&buf[l], len - l, "%d ", vals[i]); if (l >= len) break; } return l; } case IIO_VAL_CHAR: - return snprintf(buf, len, "%c", (char)vals[0]); + return scnprintf(buf, len, "%c", (char)vals[0]); default: return 0; } @@ -682,10 +682,10 @@ static ssize_t iio_format_avail_list(char *buf, const int *vals, if (len >= PAGE_SIZE) return -EFBIG; if (i < length - 1) - len += snprintf(buf + len, PAGE_SIZE - len, + len += scnprintf(buf + len, PAGE_SIZE - len, " "); else - len += snprintf(buf + len, PAGE_SIZE - len, + len += scnprintf(buf + len, PAGE_SIZE - len, "\n"); if (len >= PAGE_SIZE) return -EFBIG; @@ -698,10 +698,10 @@ static ssize_t iio_format_avail_list(char *buf, const int *vals, if (len >= PAGE_SIZE) return -EFBIG; if (i < length / 2 - 1) - len += snprintf(buf + len, PAGE_SIZE - len, + len += scnprintf(buf + len, PAGE_SIZE - len, " "); else - len += snprintf(buf + len, PAGE_SIZE - len, + len += scnprintf(buf + len, PAGE_SIZE - len, "\n"); if (len >= PAGE_SIZE) return -EFBIG; @@ -725,10 +725,10 @@ static ssize_t iio_format_avail_range(char *buf, const int *vals, int type) if (len >= PAGE_SIZE) return -EFBIG; if (i < 2) - len += snprintf(buf + len, PAGE_SIZE - len, + len += scnprintf(buf + len, PAGE_SIZE - len, " "); else - len += snprintf(buf + len, PAGE_SIZE - len, + len += scnprintf(buf + len, PAGE_SIZE - len, "]\n"); if (len >= PAGE_SIZE) return -EFBIG; @@ -741,10 +741,10 @@ static ssize_t iio_format_avail_range(char *buf, const int *vals, int type) if (len >= PAGE_SIZE) return -EFBIG; if (i < 2) - len += snprintf(buf + len, PAGE_SIZE - len, + len += scnprintf(buf + len, PAGE_SIZE - len, " "); else - len += snprintf(buf + len, PAGE_SIZE - len, + len += scnprintf(buf + len, PAGE_SIZE - len, "]\n"); if (len >= PAGE_SIZE) return -EFBIG; @@ -1507,27 +1507,27 @@ struct iio_dev *iio_device_alloc(int sizeof_priv) alloc_size += IIO_ALIGN - 1; dev = kzalloc(alloc_size, GFP_KERNEL); + if (!dev) + return NULL; - if (dev) { - dev->dev.groups = dev->groups; - dev->dev.type = &iio_device_type; - dev->dev.bus = &iio_bus_type; - device_initialize(&dev->dev); - dev_set_drvdata(&dev->dev, (void *)dev); - mutex_init(&dev->mlock); - mutex_init(&dev->info_exist_lock); - INIT_LIST_HEAD(&dev->channel_attr_list); + dev->dev.groups = dev->groups; + dev->dev.type = &iio_device_type; + dev->dev.bus = &iio_bus_type; + device_initialize(&dev->dev); + dev_set_drvdata(&dev->dev, (void *)dev); + mutex_init(&dev->mlock); + mutex_init(&dev->info_exist_lock); + INIT_LIST_HEAD(&dev->channel_attr_list); - dev->id = ida_simple_get(&iio_ida, 0, 0, GFP_KERNEL); - if (dev->id < 0) { - /* cannot use a dev_err as the name isn't available */ - pr_err("failed to get device id\n"); - kfree(dev); - return NULL; - } - dev_set_name(&dev->dev, "iio:device%d", dev->id); - INIT_LIST_HEAD(&dev->buffer_list); + dev->id = ida_simple_get(&iio_ida, 0, 0, GFP_KERNEL); + if (dev->id < 0) { + /* cannot use a dev_err as the name isn't available */ + pr_err("failed to get device id\n"); + kfree(dev); + return NULL; } + dev_set_name(&dev->dev, "iio:device%d", dev->id); + INIT_LIST_HEAD(&dev->buffer_list); return dev; } @@ -1549,17 +1549,6 @@ static void devm_iio_device_release(struct device *dev, void *res) iio_device_free(*(struct iio_dev **)res); } -int devm_iio_device_match(struct device *dev, void *res, void *data) -{ - struct iio_dev **r = res; - if (!r || !*r) { - WARN_ON(!r || !*r); - return 0; - } - return *r == data; -} -EXPORT_SYMBOL_GPL(devm_iio_device_match); - /** * devm_iio_device_alloc - Resource-managed iio_device_alloc() * @dev: Device to allocate iio_dev for @@ -1568,9 +1557,6 @@ EXPORT_SYMBOL_GPL(devm_iio_device_match); * Managed iio_device_alloc. iio_dev allocated with this function is * automatically freed on driver detach. * - * If an iio_dev allocated with this function needs to be freed separately, - * devm_iio_device_free() must be used. - * * RETURNS: * Pointer to allocated iio_dev on success, NULL on failure. */ @@ -1595,23 +1581,6 @@ struct iio_dev *devm_iio_device_alloc(struct device *dev, int sizeof_priv) } EXPORT_SYMBOL_GPL(devm_iio_device_alloc); -/** - * devm_iio_device_free - Resource-managed iio_device_free() - * @dev: Device this iio_dev belongs to - * @iio_dev: the iio_dev associated with the device - * - * Free iio_dev allocated with devm_iio_device_alloc(). - */ -void devm_iio_device_free(struct device *dev, struct iio_dev *iio_dev) -{ - int rc; - - rc = devres_release(dev, devm_iio_device_release, - devm_iio_device_match, iio_dev); - WARN_ON(rc); -} -EXPORT_SYMBOL_GPL(devm_iio_device_free); - /** * iio_chrdev_open() - chrdev file open for buffer access and ioctls * @inode: Inode structure for identifying the device in the file system @@ -1714,6 +1683,9 @@ int __iio_device_register(struct iio_dev *indio_dev, struct module *this_mod) { int ret; + if (!indio_dev->info) + return -EINVAL; + indio_dev->driver_module = this_mod; /* If the calling driver did not initialize of_node, do it here */ if (!indio_dev->dev.of_node && indio_dev->dev.parent) @@ -1726,9 +1698,6 @@ int __iio_device_register(struct iio_dev *indio_dev, struct module *this_mod) if (ret < 0) return ret; - if (!indio_dev->info) - return -EINVAL; - /* configure elements for the chrdev */ indio_dev->dev.devt = MKDEV(MAJOR(iio_devt), indio_dev->id); @@ -1833,23 +1802,6 @@ int __devm_iio_device_register(struct device *dev, struct iio_dev *indio_dev, } EXPORT_SYMBOL_GPL(__devm_iio_device_register); -/** - * devm_iio_device_unregister - Resource-managed iio_device_unregister() - * @dev: Device this iio_dev belongs to - * @indio_dev: the iio_dev associated with the device - * - * Unregister iio_dev registered with devm_iio_device_register(). - */ -void devm_iio_device_unregister(struct device *dev, struct iio_dev *indio_dev) -{ - int rc; - - rc = devres_release(dev, devm_iio_device_unreg, - devm_iio_device_match, indio_dev); - WARN_ON(rc); -} -EXPORT_SYMBOL_GPL(devm_iio_device_unregister); - /** * iio_device_claim_direct_mode - Keep device in direct mode * @indio_dev: the iio_dev associated with the device diff --git a/drivers/iio/industrialio-trigger.c b/drivers/iio/industrialio-trigger.c index 3908a9a90035..53d1931f6be8 100644 --- a/drivers/iio/industrialio-trigger.c +++ b/drivers/iio/industrialio-trigger.c @@ -585,18 +585,6 @@ static void devm_iio_trigger_release(struct device *dev, void *res) iio_trigger_free(*(struct iio_trigger **)res); } -static int devm_iio_trigger_match(struct device *dev, void *res, void *data) -{ - struct iio_trigger **r = res; - - if (!r || !*r) { - WARN_ON(!r || !*r); - return 0; - } - - return *r == data; -} - /** * devm_iio_trigger_alloc - Resource-managed iio_trigger_alloc() * @dev: Device to allocate iio_trigger for @@ -608,9 +596,6 @@ static int devm_iio_trigger_match(struct device *dev, void *res, void *data) * Managed iio_trigger_alloc. iio_trigger allocated with this function is * automatically freed on driver detach. * - * If an iio_trigger allocated with this function needs to be freed separately, - * devm_iio_trigger_free() must be used. - * * RETURNS: * Pointer to allocated iio_trigger on success, NULL on failure. */ @@ -640,23 +625,6 @@ struct iio_trigger *devm_iio_trigger_alloc(struct device *dev, } EXPORT_SYMBOL_GPL(devm_iio_trigger_alloc); -/** - * devm_iio_trigger_free - Resource-managed iio_trigger_free() - * @dev: Device this iio_dev belongs to - * @iio_trig: the iio_trigger associated with the device - * - * Free iio_trigger allocated with devm_iio_trigger_alloc(). - */ -void devm_iio_trigger_free(struct device *dev, struct iio_trigger *iio_trig) -{ - int rc; - - rc = devres_release(dev, devm_iio_trigger_release, - devm_iio_trigger_match, iio_trig); - WARN_ON(rc); -} -EXPORT_SYMBOL_GPL(devm_iio_trigger_free); - static void devm_iio_trigger_unreg(struct device *dev, void *res) { iio_trigger_unregister(*(struct iio_trigger **)res); @@ -673,9 +641,6 @@ static void devm_iio_trigger_unreg(struct device *dev, void *res) * calls iio_trigger_register() internally. Refer to that function for more * information. * - * If an iio_trigger registered with this function needs to be unregistered - * separately, devm_iio_trigger_unregister() must be used. - * * RETURNS: * 0 on success, negative error number on failure. */ @@ -701,24 +666,6 @@ int __devm_iio_trigger_register(struct device *dev, } EXPORT_SYMBOL_GPL(__devm_iio_trigger_register); -/** - * devm_iio_trigger_unregister - Resource-managed iio_trigger_unregister() - * @dev: device this iio_trigger belongs to - * @trig_info: the trigger associated with the device - * - * Unregister trigger registered with devm_iio_trigger_register(). - */ -void devm_iio_trigger_unregister(struct device *dev, - struct iio_trigger *trig_info) -{ - int rc; - - rc = devres_release(dev, devm_iio_trigger_unreg, devm_iio_trigger_match, - trig_info); - WARN_ON(rc); -} -EXPORT_SYMBOL_GPL(devm_iio_trigger_unregister); - bool iio_trigger_using_own(struct iio_dev *indio_dev) { return indio_dev->trig->attached_own_device; diff --git a/drivers/iio/inkern.c b/drivers/iio/inkern.c index 5a8351c9a426..ede99e0d5371 100644 --- a/drivers/iio/inkern.c +++ b/drivers/iio/inkern.c @@ -360,18 +360,6 @@ static void devm_iio_channel_free(struct device *dev, void *res) iio_channel_release(channel); } -static int devm_iio_channel_match(struct device *dev, void *res, void *data) -{ - struct iio_channel **r = res; - - if (!r || !*r) { - WARN_ON(!r || !*r); - return 0; - } - - return *r == data; -} - struct iio_channel *devm_iio_channel_get(struct device *dev, const char *channel_name) { @@ -394,13 +382,6 @@ struct iio_channel *devm_iio_channel_get(struct device *dev, } EXPORT_SYMBOL_GPL(devm_iio_channel_get); -void devm_iio_channel_release(struct device *dev, struct iio_channel *channel) -{ - WARN_ON(devres_release(dev, devm_iio_channel_free, - devm_iio_channel_match, channel)); -} -EXPORT_SYMBOL_GPL(devm_iio_channel_release); - struct iio_channel *iio_channel_get_all(struct device *dev) { const char *name; @@ -514,14 +495,6 @@ struct iio_channel *devm_iio_channel_get_all(struct device *dev) } EXPORT_SYMBOL_GPL(devm_iio_channel_get_all); -void devm_iio_channel_release_all(struct device *dev, - struct iio_channel *channels) -{ - WARN_ON(devres_release(dev, devm_iio_channel_free_all, - devm_iio_channel_match, channels)); -} -EXPORT_SYMBOL_GPL(devm_iio_channel_release_all); - static int iio_channel_read(struct iio_channel *chan, int *val, int *val2, enum iio_chan_info_enum info) { diff --git a/drivers/iio/light/Kconfig b/drivers/iio/light/Kconfig index b27719cefcf9..182bd18c4bb2 100644 --- a/drivers/iio/light/Kconfig +++ b/drivers/iio/light/Kconfig @@ -516,6 +516,8 @@ config US5182D config VCNL4000 tristate "VCNL4000/4010/4020/4200 combined ALS and proximity sensor" + select IIO_BUFFER + select IIO_TRIGGERED_BUFFER depends on I2C help Say Y here if you want to build a driver for the Vishay VCNL4000, diff --git a/drivers/iio/light/bh1780.c b/drivers/iio/light/bh1780.c index a8361006dcd9..03f2d8d123c4 100644 --- a/drivers/iio/light/bh1780.c +++ b/drivers/iio/light/bh1780.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include @@ -273,13 +273,11 @@ static const struct i2c_device_id bh1780_id[] = { MODULE_DEVICE_TABLE(i2c, bh1780_id); -#ifdef CONFIG_OF static const struct of_device_id of_bh1780_match[] = { { .compatible = "rohm,bh1780gli", }, {}, }; MODULE_DEVICE_TABLE(of, of_bh1780_match); -#endif static struct i2c_driver bh1780_driver = { .probe = bh1780_probe, @@ -288,7 +286,7 @@ static struct i2c_driver bh1780_driver = { .driver = { .name = "bh1780", .pm = &bh1780_dev_pm_ops, - .of_match_table = of_match_ptr(of_bh1780_match), + .of_match_table = of_bh1780_match, }, }; diff --git a/drivers/iio/light/cm32181.c b/drivers/iio/light/cm32181.c index 5f4fb5674fa0..160eb3f99795 100644 --- a/drivers/iio/light/cm32181.c +++ b/drivers/iio/light/cm32181.c @@ -4,11 +4,13 @@ * Author: Kevin Tsai */ +#include #include #include #include #include #include +#include #include #include #include @@ -18,17 +20,24 @@ /* Registers Address */ #define CM32181_REG_ADDR_CMD 0x00 +#define CM32181_REG_ADDR_WH 0x01 +#define CM32181_REG_ADDR_WL 0x02 +#define CM32181_REG_ADDR_TEST 0x03 #define CM32181_REG_ADDR_ALS 0x04 #define CM32181_REG_ADDR_STATUS 0x06 #define CM32181_REG_ADDR_ID 0x07 /* Number of Configurable Registers */ -#define CM32181_CONF_REG_NUM 0x01 +#define CM32181_CONF_REG_NUM 4 /* CMD register */ -#define CM32181_CMD_ALS_ENABLE 0x00 -#define CM32181_CMD_ALS_DISABLE 0x01 -#define CM32181_CMD_ALS_INT_EN 0x02 +#define CM32181_CMD_ALS_DISABLE BIT(0) +#define CM32181_CMD_ALS_INT_EN BIT(1) +#define CM32181_CMD_ALS_THRES_WINDOW BIT(2) + +#define CM32181_CMD_ALS_PERS_SHIFT 4 +#define CM32181_CMD_ALS_PERS_MASK (0x03 << CM32181_CMD_ALS_PERS_SHIFT) +#define CM32181_CMD_ALS_PERS_DEFAULT (0x01 << CM32181_CMD_ALS_PERS_SHIFT) #define CM32181_CMD_ALS_IT_SHIFT 6 #define CM32181_CMD_ALS_IT_MASK (0x0F << CM32181_CMD_ALS_IT_SHIFT) @@ -38,27 +47,133 @@ #define CM32181_CMD_ALS_SM_MASK (0x03 << CM32181_CMD_ALS_SM_SHIFT) #define CM32181_CMD_ALS_SM_DEFAULT (0x01 << CM32181_CMD_ALS_SM_SHIFT) -#define CM32181_MLUX_PER_BIT 5 /* ALS_SM=01 IT=800ms */ -#define CM32181_MLUX_PER_BIT_BASE_IT 800000 /* Based on IT=800ms */ -#define CM32181_CALIBSCALE_DEFAULT 1000 -#define CM32181_CALIBSCALE_RESOLUTION 1000 -#define MLUX_PER_LUX 1000 +#define CM32181_LUX_PER_BIT 500 /* ALS_SM=01 IT=800ms */ +#define CM32181_LUX_PER_BIT_RESOLUTION 100000 +#define CM32181_LUX_PER_BIT_BASE_IT 800000 /* Based on IT=800ms */ +#define CM32181_CALIBSCALE_DEFAULT 100000 +#define CM32181_CALIBSCALE_RESOLUTION 100000 -static const u8 cm32181_reg[CM32181_CONF_REG_NUM] = { - CM32181_REG_ADDR_CMD, +#define SMBUS_ALERT_RESPONSE_ADDRESS 0x0c + +/* CPM0 Index 0: device-id (3218 or 32181), 1: Unknown, 2: init_regs_bitmap */ +#define CPM0_REGS_BITMAP 2 +#define CPM0_HEADER_SIZE 3 + +/* CPM1 Index 0: lux_per_bit, 1: calibscale, 2: resolution (100000) */ +#define CPM1_LUX_PER_BIT 0 +#define CPM1_CALIBSCALE 1 +#define CPM1_SIZE 3 + +/* CM3218 Family */ +static const int cm3218_als_it_bits[] = { 0, 1, 2, 3 }; +static const int cm3218_als_it_values[] = { 100000, 200000, 400000, 800000 }; + +/* CM32181 Family */ +static const int cm32181_als_it_bits[] = { 12, 8, 0, 1, 2, 3 }; +static const int cm32181_als_it_values[] = { + 25000, 50000, 100000, 200000, 400000, 800000 }; -static const int als_it_bits[] = {12, 8, 0, 1, 2, 3}; -static const int als_it_value[] = {25000, 50000, 100000, 200000, 400000, - 800000}; - struct cm32181_chip { struct i2c_client *client; + struct device *dev; struct mutex lock; u16 conf_regs[CM32181_CONF_REG_NUM]; + unsigned long init_regs_bitmap; int calibscale; + int lux_per_bit; + int lux_per_bit_base_it; + int num_als_it; + const int *als_it_bits; + const int *als_it_values; }; +static int cm32181_read_als_it(struct cm32181_chip *cm32181, int *val2); + +#ifdef CONFIG_ACPI +/** + * cm32181_acpi_get_cpm() - Get CPM object from ACPI + * @client pointer of struct i2c_client. + * @obj_name pointer of ACPI object name. + * @count maximum size of return array. + * @vals pointer of array for return elements. + * + * Convert ACPI CPM table to array. + * + * Return: -ENODEV for fail. Otherwise is number of elements. + */ +static int cm32181_acpi_get_cpm(struct device *dev, char *obj_name, + u64 *values, int count) +{ + struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; + union acpi_object *cpm, *elem; + acpi_handle handle; + acpi_status status; + int i; + + handle = ACPI_HANDLE(dev); + if (!handle) + return -ENODEV; + + status = acpi_evaluate_object(handle, obj_name, NULL, &buffer); + if (ACPI_FAILURE(status)) { + dev_err(dev, "object %s not found\n", obj_name); + return -ENODEV; + } + + cpm = buffer.pointer; + if (cpm->package.count > count) + dev_warn(dev, "%s table contains %u values, only using first %d values\n", + obj_name, cpm->package.count, count); + + count = min_t(int, cpm->package.count, count); + for (i = 0; i < count; i++) { + elem = &(cpm->package.elements[i]); + values[i] = elem->integer.value; + } + + kfree(buffer.pointer); + + return count; +} + +static void cm32181_acpi_parse_cpm_tables(struct cm32181_chip *cm32181) +{ + u64 vals[CPM0_HEADER_SIZE + CM32181_CONF_REG_NUM]; + struct device *dev = cm32181->dev; + int i, count; + + count = cm32181_acpi_get_cpm(dev, "CPM0", vals, ARRAY_SIZE(vals)); + if (count <= CPM0_HEADER_SIZE) + return; + + count -= CPM0_HEADER_SIZE; + + cm32181->init_regs_bitmap = vals[CPM0_REGS_BITMAP]; + cm32181->init_regs_bitmap &= GENMASK(count - 1, 0); + for_each_set_bit(i, &cm32181->init_regs_bitmap, count) + cm32181->conf_regs[i] = vals[CPM0_HEADER_SIZE + i]; + + count = cm32181_acpi_get_cpm(dev, "CPM1", vals, ARRAY_SIZE(vals)); + if (count != CPM1_SIZE) + return; + + cm32181->lux_per_bit = vals[CPM1_LUX_PER_BIT]; + + /* Check for uncalibrated devices */ + if (vals[CPM1_CALIBSCALE] == CM32181_CALIBSCALE_DEFAULT) + return; + + cm32181->calibscale = vals[CPM1_CALIBSCALE]; + /* CPM1 lux_per_bit is for the current it value */ + cm32181_read_als_it(cm32181, &cm32181->lux_per_bit_base_it); +} +#else +static void cm32181_acpi_parse_cpm_tables(struct cm32181_chip *cm32181) +{ +} +#endif /* CONFIG_ACPI */ + /** * cm32181_reg_init() - Initialize CM32181 registers * @cm32181: pointer of struct cm32181. @@ -78,18 +193,37 @@ static int cm32181_reg_init(struct cm32181_chip *cm32181) return ret; /* check device ID */ - if ((ret & 0xFF) != 0x81) + switch (ret & 0xFF) { + case 0x18: /* CM3218 */ + cm32181->num_als_it = ARRAY_SIZE(cm3218_als_it_bits); + cm32181->als_it_bits = cm3218_als_it_bits; + cm32181->als_it_values = cm3218_als_it_values; + break; + case 0x81: /* CM32181 */ + case 0x82: /* CM32182, fully compat. with CM32181 */ + cm32181->num_als_it = ARRAY_SIZE(cm32181_als_it_bits); + cm32181->als_it_bits = cm32181_als_it_bits; + cm32181->als_it_values = cm32181_als_it_values; + break; + default: return -ENODEV; + } /* Default Values */ - cm32181->conf_regs[CM32181_REG_ADDR_CMD] = CM32181_CMD_ALS_ENABLE | + cm32181->conf_regs[CM32181_REG_ADDR_CMD] = CM32181_CMD_ALS_IT_DEFAULT | CM32181_CMD_ALS_SM_DEFAULT; + cm32181->init_regs_bitmap = BIT(CM32181_REG_ADDR_CMD); cm32181->calibscale = CM32181_CALIBSCALE_DEFAULT; + cm32181->lux_per_bit = CM32181_LUX_PER_BIT; + cm32181->lux_per_bit_base_it = CM32181_LUX_PER_BIT_BASE_IT; + + if (ACPI_HANDLE(cm32181->dev)) + cm32181_acpi_parse_cpm_tables(cm32181); /* Initialize registers*/ - for (i = 0; i < CM32181_CONF_REG_NUM; i++) { - ret = i2c_smbus_write_word_data(client, cm32181_reg[i], - cm32181->conf_regs[i]); + for_each_set_bit(i, &cm32181->init_regs_bitmap, CM32181_CONF_REG_NUM) { + ret = i2c_smbus_write_word_data(client, i, + cm32181->conf_regs[i]); if (ret < 0) return ret; } @@ -102,7 +236,7 @@ static int cm32181_reg_init(struct cm32181_chip *cm32181) * @cm32181: pointer of struct cm32181 * @val2: pointer of int to load the als_it value. * - * Report the current integartion time by millisecond. + * Report the current integration time in milliseconds. * * Return: IIO_VAL_INT_PLUS_MICRO for success, otherwise -EINVAL. */ @@ -114,9 +248,9 @@ static int cm32181_read_als_it(struct cm32181_chip *cm32181, int *val2) als_it = cm32181->conf_regs[CM32181_REG_ADDR_CMD]; als_it &= CM32181_CMD_ALS_IT_MASK; als_it >>= CM32181_CMD_ALS_IT_SHIFT; - for (i = 0; i < ARRAY_SIZE(als_it_bits); i++) { - if (als_it == als_it_bits[i]) { - *val2 = als_it_value[i]; + for (i = 0; i < cm32181->num_als_it; i++) { + if (als_it == cm32181->als_it_bits[i]) { + *val2 = cm32181->als_it_values[i]; return IIO_VAL_INT_PLUS_MICRO; } } @@ -139,14 +273,14 @@ static int cm32181_write_als_it(struct cm32181_chip *cm32181, int val) u16 als_it; int ret, i, n; - n = ARRAY_SIZE(als_it_value); + n = cm32181->num_als_it; for (i = 0; i < n; i++) - if (val <= als_it_value[i]) + if (val <= cm32181->als_it_values[i]) break; if (i >= n) i = n - 1; - als_it = als_it_bits[i]; + als_it = cm32181->als_it_bits[i]; als_it <<= CM32181_CMD_ALS_IT_SHIFT; mutex_lock(&cm32181->lock); @@ -175,15 +309,15 @@ static int cm32181_get_lux(struct cm32181_chip *cm32181) struct i2c_client *client = cm32181->client; int ret; int als_it; - unsigned long lux; + u64 lux; ret = cm32181_read_als_it(cm32181, &als_it); if (ret < 0) return -EINVAL; - lux = CM32181_MLUX_PER_BIT; - lux *= CM32181_MLUX_PER_BIT_BASE_IT; - lux /= als_it; + lux = cm32181->lux_per_bit; + lux *= cm32181->lux_per_bit_base_it; + lux = div_u64(lux, als_it); ret = i2c_smbus_read_word_data(client, CM32181_REG_ADDR_ALS); if (ret < 0) @@ -191,8 +325,8 @@ static int cm32181_get_lux(struct cm32181_chip *cm32181) lux *= ret; lux *= cm32181->calibscale; - lux /= CM32181_CALIBSCALE_RESOLUTION; - lux /= MLUX_PER_LUX; + lux = div_u64(lux, CM32181_CALIBSCALE_RESOLUTION); + lux = div_u64(lux, CM32181_LUX_PER_BIT_RESOLUTION); if (lux > 0xFFFF) lux = 0xFFFF; @@ -258,11 +392,12 @@ static int cm32181_write_raw(struct iio_dev *indio_dev, static ssize_t cm32181_get_it_available(struct device *dev, struct device_attribute *attr, char *buf) { + struct cm32181_chip *cm32181 = iio_priv(dev_to_iio_dev(dev)); int i, n, len; - n = ARRAY_SIZE(als_it_value); + n = cm32181->num_als_it; for (i = 0, len = 0; i < n; i++) - len += sprintf(buf + len, "0.%06u ", als_it_value[i]); + len += sprintf(buf + len, "0.%06u ", cm32181->als_it_values[i]); return len + sprintf(buf + len, "\n"); } @@ -294,70 +429,86 @@ static const struct iio_info cm32181_info = { .attrs = &cm32181_attribute_group, }; -static int cm32181_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int cm32181_probe(struct i2c_client *client) { + struct device *dev = &client->dev; struct cm32181_chip *cm32181; struct iio_dev *indio_dev; int ret; - indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*cm32181)); - if (!indio_dev) { - dev_err(&client->dev, "devm_iio_device_alloc failed\n"); + indio_dev = devm_iio_device_alloc(dev, sizeof(*cm32181)); + if (!indio_dev) return -ENOMEM; + + /* + * Some ACPI systems list 2 I2C resources for the CM3218 sensor, the + * SMBus Alert Response Address (ARA, 0x0c) and the actual I2C address. + * Detect this and take the following step to deal with it: + * 1. When a SMBus Alert capable sensor has an Alert asserted, it will + * not respond on its actual I2C address. Read a byte from the ARA + * to clear any pending Alerts. + * 2. Create a "dummy" client for the actual I2C address and + * use that client to communicate with the sensor. + */ + if (ACPI_HANDLE(dev) && client->addr == SMBUS_ALERT_RESPONSE_ADDRESS) { + struct i2c_board_info board_info = { .type = "dummy" }; + + i2c_smbus_read_byte(client); + + client = i2c_acpi_new_device(dev, 1, &board_info); + if (IS_ERR(client)) + return PTR_ERR(client); } cm32181 = iio_priv(indio_dev); - i2c_set_clientdata(client, indio_dev); cm32181->client = client; + cm32181->dev = dev; mutex_init(&cm32181->lock); - indio_dev->dev.parent = &client->dev; + indio_dev->dev.parent = dev; indio_dev->channels = cm32181_channels; indio_dev->num_channels = ARRAY_SIZE(cm32181_channels); indio_dev->info = &cm32181_info; - indio_dev->name = id->name; + indio_dev->name = dev_name(dev); indio_dev->modes = INDIO_DIRECT_MODE; ret = cm32181_reg_init(cm32181); if (ret) { - dev_err(&client->dev, - "%s: register init failed\n", - __func__); + dev_err(dev, "%s: register init failed\n", __func__); return ret; } - ret = devm_iio_device_register(&client->dev, indio_dev); + ret = devm_iio_device_register(dev, indio_dev); if (ret) { - dev_err(&client->dev, - "%s: regist device failed\n", - __func__); + dev_err(dev, "%s: regist device failed\n", __func__); return ret; } return 0; } -static const struct i2c_device_id cm32181_id[] = { - { "cm32181", 0 }, - { } -}; - -MODULE_DEVICE_TABLE(i2c, cm32181_id); - static const struct of_device_id cm32181_of_match[] = { + { .compatible = "capella,cm3218" }, { .compatible = "capella,cm32181" }, { } }; MODULE_DEVICE_TABLE(of, cm32181_of_match); +#ifdef CONFIG_ACPI +static const struct acpi_device_id cm32181_acpi_match[] = { + { "CPLM3218", 0 }, + { } +}; +MODULE_DEVICE_TABLE(acpi, cm32181_acpi_match); +#endif + static struct i2c_driver cm32181_driver = { .driver = { .name = "cm32181", - .of_match_table = of_match_ptr(cm32181_of_match), + .acpi_match_table = ACPI_PTR(cm32181_acpi_match), + .of_match_table = cm32181_of_match, }, - .id_table = cm32181_id, - .probe = cm32181_probe, + .probe_new = cm32181_probe, }; module_i2c_driver(cm32181_driver); diff --git a/drivers/iio/light/cm3232.c b/drivers/iio/light/cm3232.c index cd3cfb7d02bd..867200825686 100644 --- a/drivers/iio/light/cm3232.c +++ b/drivers/iio/light/cm3232.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include @@ -418,7 +419,7 @@ MODULE_DEVICE_TABLE(of, cm3232_of_match); static struct i2c_driver cm3232_driver = { .driver = { .name = "cm3232", - .of_match_table = of_match_ptr(cm3232_of_match), + .of_match_table = cm3232_of_match, #ifdef CONFIG_PM_SLEEP .pm = &cm3232_pm_ops, #endif diff --git a/drivers/iio/light/gp2ap002.c b/drivers/iio/light/gp2ap002.c index b7ef16b28280..7a2679bdc987 100644 --- a/drivers/iio/light/gp2ap002.c +++ b/drivers/iio/light/gp2ap002.c @@ -158,6 +158,9 @@ static irqreturn_t gp2ap002_prox_irq(int irq, void *d) int val; int ret; + if (!gp2ap002->enabled) + goto err_retrig; + ret = regmap_read(gp2ap002->map, GP2AP002_PROX, &val); if (ret) { dev_err(gp2ap002->dev, "error reading proximity\n"); @@ -247,6 +250,8 @@ static int gp2ap002_read_raw(struct iio_dev *indio_dev, struct gp2ap002 *gp2ap002 = iio_priv(indio_dev); int ret; + pm_runtime_get_sync(gp2ap002->dev); + switch (mask) { case IIO_CHAN_INFO_RAW: switch (chan->type) { @@ -255,13 +260,21 @@ static int gp2ap002_read_raw(struct iio_dev *indio_dev, if (ret < 0) return ret; *val = ret; - return IIO_VAL_INT; + ret = IIO_VAL_INT; + goto out; default: - return -EINVAL; + ret = -EINVAL; + goto out; } default: - return -EINVAL; + ret = -EINVAL; } + +out: + pm_runtime_mark_last_busy(gp2ap002->dev); + pm_runtime_put_autosuspend(gp2ap002->dev); + + return ret; } static int gp2ap002_init(struct gp2ap002 *gp2ap002) diff --git a/drivers/iio/light/gp2ap020a00f.c b/drivers/iio/light/gp2ap020a00f.c index 7fbbce0d4bc7..070d4cd0cf54 100644 --- a/drivers/iio/light/gp2ap020a00f.c +++ b/drivers/iio/light/gp2ap020a00f.c @@ -38,8 +38,8 @@ #include #include #include +#include #include -#include #include #include #include @@ -1617,18 +1617,16 @@ static const struct i2c_device_id gp2ap020a00f_id[] = { MODULE_DEVICE_TABLE(i2c, gp2ap020a00f_id); -#ifdef CONFIG_OF static const struct of_device_id gp2ap020a00f_of_match[] = { { .compatible = "sharp,gp2ap020a00f" }, { } }; MODULE_DEVICE_TABLE(of, gp2ap020a00f_of_match); -#endif static struct i2c_driver gp2ap020a00f_driver = { .driver = { .name = GP2A_I2C_NAME, - .of_match_table = of_match_ptr(gp2ap020a00f_of_match), + .of_match_table = gp2ap020a00f_of_match, }, .probe = gp2ap020a00f_probe, .remove = gp2ap020a00f_remove, diff --git a/drivers/iio/light/hid-sensor-als.c b/drivers/iio/light/hid-sensor-als.c index b6cd299517d1..81fa2a422797 100644 --- a/drivers/iio/light/hid-sensor-als.c +++ b/drivers/iio/light/hid-sensor-als.c @@ -14,8 +14,6 @@ #include #include #include -#include -#include #include "../common/hid-sensors/hid-sensor-trigger.h" enum { @@ -308,18 +306,13 @@ static int hid_als_probe(struct platform_device *pdev) indio_dev->name = name; indio_dev->modes = INDIO_DIRECT_MODE; - ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time, - NULL, NULL); - if (ret) { - dev_err(&pdev->dev, "failed to initialize trigger buffer\n"); - goto error_free_dev_mem; - } atomic_set(&als_state->common_attributes.data_ready, 0); + ret = hid_sensor_setup_trigger(indio_dev, name, &als_state->common_attributes); if (ret < 0) { dev_err(&pdev->dev, "trigger setup failed\n"); - goto error_unreg_buffer_funcs; + goto error_free_dev_mem; } ret = iio_device_register(indio_dev); @@ -343,9 +336,7 @@ static int hid_als_probe(struct platform_device *pdev) error_iio_unreg: iio_device_unregister(indio_dev); error_remove_trigger: - hid_sensor_remove_trigger(&als_state->common_attributes); -error_unreg_buffer_funcs: - iio_triggered_buffer_cleanup(indio_dev); + hid_sensor_remove_trigger(indio_dev, &als_state->common_attributes); error_free_dev_mem: kfree(indio_dev->channels); return ret; @@ -360,8 +351,7 @@ static int hid_als_remove(struct platform_device *pdev) sensor_hub_remove_callback(hsdev, HID_USAGE_SENSOR_ALS); iio_device_unregister(indio_dev); - hid_sensor_remove_trigger(&als_state->common_attributes); - iio_triggered_buffer_cleanup(indio_dev); + hid_sensor_remove_trigger(indio_dev, &als_state->common_attributes); kfree(indio_dev->channels); return 0; diff --git a/drivers/iio/light/hid-sensor-prox.c b/drivers/iio/light/hid-sensor-prox.c index 7e1030af9ba3..e9c04df07344 100644 --- a/drivers/iio/light/hid-sensor-prox.c +++ b/drivers/iio/light/hid-sensor-prox.c @@ -14,8 +14,6 @@ #include #include #include -#include -#include #include "../common/hid-sensors/hid-sensor-trigger.h" #define CHANNEL_SCAN_INDEX_PRESENCE 0 @@ -286,18 +284,13 @@ static int hid_prox_probe(struct platform_device *pdev) indio_dev->name = name; indio_dev->modes = INDIO_DIRECT_MODE; - ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time, - NULL, NULL); - if (ret) { - dev_err(&pdev->dev, "failed to initialize trigger buffer\n"); - goto error_free_dev_mem; - } atomic_set(&prox_state->common_attributes.data_ready, 0); + ret = hid_sensor_setup_trigger(indio_dev, name, &prox_state->common_attributes); if (ret) { dev_err(&pdev->dev, "trigger setup failed\n"); - goto error_unreg_buffer_funcs; + goto error_free_dev_mem; } ret = iio_device_register(indio_dev); @@ -321,9 +314,7 @@ static int hid_prox_probe(struct platform_device *pdev) error_iio_unreg: iio_device_unregister(indio_dev); error_remove_trigger: - hid_sensor_remove_trigger(&prox_state->common_attributes); -error_unreg_buffer_funcs: - iio_triggered_buffer_cleanup(indio_dev); + hid_sensor_remove_trigger(indio_dev, &prox_state->common_attributes); error_free_dev_mem: kfree(indio_dev->channels); return ret; @@ -338,8 +329,7 @@ static int hid_prox_remove(struct platform_device *pdev) sensor_hub_remove_callback(hsdev, HID_USAGE_SENSOR_PROX); iio_device_unregister(indio_dev); - hid_sensor_remove_trigger(&prox_state->common_attributes); - iio_triggered_buffer_cleanup(indio_dev); + hid_sensor_remove_trigger(indio_dev, &prox_state->common_attributes); kfree(indio_dev->channels); return 0; diff --git a/drivers/iio/light/isl29125.c b/drivers/iio/light/isl29125.c index e37894f0ae0b..95611f5eff01 100644 --- a/drivers/iio/light/isl29125.c +++ b/drivers/iio/light/isl29125.c @@ -213,13 +213,24 @@ static const struct iio_info isl29125_info = { .attrs = &isl29125_attribute_group, }; -static int isl29125_buffer_preenable(struct iio_dev *indio_dev) +static int isl29125_buffer_postenable(struct iio_dev *indio_dev) { struct isl29125_data *data = iio_priv(indio_dev); + int err; + + err = iio_triggered_buffer_postenable(indio_dev); + if (err) + return err; data->conf1 |= ISL29125_MODE_RGB; - return i2c_smbus_write_byte_data(data->client, ISL29125_CONF1, + err = i2c_smbus_write_byte_data(data->client, ISL29125_CONF1, data->conf1); + if (err) { + iio_triggered_buffer_predisable(indio_dev); + return err; + } + + return 0; } static int isl29125_buffer_predisable(struct iio_dev *indio_dev) @@ -227,19 +238,18 @@ static int isl29125_buffer_predisable(struct iio_dev *indio_dev) struct isl29125_data *data = iio_priv(indio_dev); int ret; - ret = iio_triggered_buffer_predisable(indio_dev); - if (ret < 0) - return ret; - data->conf1 &= ~ISL29125_MODE_MASK; data->conf1 |= ISL29125_MODE_PD; - return i2c_smbus_write_byte_data(data->client, ISL29125_CONF1, + ret = i2c_smbus_write_byte_data(data->client, ISL29125_CONF1, data->conf1); + + iio_triggered_buffer_predisable(indio_dev); + + return ret; } static const struct iio_buffer_setup_ops isl29125_buffer_setup_ops = { - .preenable = isl29125_buffer_preenable, - .postenable = &iio_triggered_buffer_postenable, + .postenable = isl29125_buffer_postenable, .predisable = isl29125_buffer_predisable, }; diff --git a/drivers/iio/light/ltr501.c b/drivers/iio/light/ltr501.c index 71f99d2a22c1..5a3fcb127cd2 100644 --- a/drivers/iio/light/ltr501.c +++ b/drivers/iio/light/ltr501.c @@ -101,12 +101,12 @@ struct ltr501_gain { int uscale; }; -static struct ltr501_gain ltr501_als_gain_tbl[] = { +static const struct ltr501_gain ltr501_als_gain_tbl[] = { {1, 0}, {0, 5000}, }; -static struct ltr501_gain ltr559_als_gain_tbl[] = { +static const struct ltr501_gain ltr559_als_gain_tbl[] = { {1, 0}, {0, 500000}, {0, 250000}, @@ -117,14 +117,14 @@ static struct ltr501_gain ltr559_als_gain_tbl[] = { {0, 10000}, }; -static struct ltr501_gain ltr501_ps_gain_tbl[] = { +static const struct ltr501_gain ltr501_ps_gain_tbl[] = { {1, 0}, {0, 250000}, {0, 125000}, {0, 62500}, }; -static struct ltr501_gain ltr559_ps_gain_tbl[] = { +static const struct ltr501_gain ltr559_ps_gain_tbl[] = { {0, 62500}, /* x16 gain */ {0, 31250}, /* x32 gain */ {0, 15625}, /* bits X1 are for x64 gain */ @@ -133,9 +133,9 @@ static struct ltr501_gain ltr559_ps_gain_tbl[] = { struct ltr501_chip_info { u8 partid; - struct ltr501_gain *als_gain; + const struct ltr501_gain *als_gain; int als_gain_tbl_size; - struct ltr501_gain *ps_gain; + const struct ltr501_gain *ps_gain; int ps_gain_tbl_size; u8 als_mode_active; u8 als_gain_mask; @@ -192,7 +192,7 @@ static int ltr501_match_samp_freq(const struct ltr501_samp_table *tab, return -EINVAL; } -static int ltr501_als_read_samp_freq(struct ltr501_data *data, +static int ltr501_als_read_samp_freq(const struct ltr501_data *data, int *val, int *val2) { int ret, i; @@ -210,7 +210,7 @@ static int ltr501_als_read_samp_freq(struct ltr501_data *data, return IIO_VAL_INT_PLUS_MICRO; } -static int ltr501_ps_read_samp_freq(struct ltr501_data *data, +static int ltr501_ps_read_samp_freq(const struct ltr501_data *data, int *val, int *val2) { int ret, i; @@ -266,7 +266,7 @@ static int ltr501_ps_write_samp_freq(struct ltr501_data *data, return ret; } -static int ltr501_als_read_samp_period(struct ltr501_data *data, int *val) +static int ltr501_als_read_samp_period(const struct ltr501_data *data, int *val) { int ret, i; @@ -282,7 +282,7 @@ static int ltr501_als_read_samp_period(struct ltr501_data *data, int *val) return IIO_VAL_INT; } -static int ltr501_ps_read_samp_period(struct ltr501_data *data, int *val) +static int ltr501_ps_read_samp_period(const struct ltr501_data *data, int *val) { int ret, i; @@ -321,7 +321,7 @@ static unsigned long ltr501_calculate_lux(u16 vis_data, u16 ir_data) return lux / 1000; } -static int ltr501_drdy(struct ltr501_data *data, u8 drdy_mask) +static int ltr501_drdy(const struct ltr501_data *data, u8 drdy_mask) { int tries = 100; int ret, status; @@ -373,7 +373,8 @@ static int ltr501_set_it_time(struct ltr501_data *data, int it) } /* read int time in micro seconds */ -static int ltr501_read_it_time(struct ltr501_data *data, int *val, int *val2) +static int ltr501_read_it_time(const struct ltr501_data *data, + int *val, int *val2) { int ret, index; @@ -391,7 +392,7 @@ static int ltr501_read_it_time(struct ltr501_data *data, int *val, int *val2) return IIO_VAL_INT_PLUS_MICRO; } -static int ltr501_read_als(struct ltr501_data *data, __le16 buf[2]) +static int ltr501_read_als(const struct ltr501_data *data, __le16 buf[2]) { int ret; @@ -403,7 +404,7 @@ static int ltr501_read_als(struct ltr501_data *data, __le16 buf[2]) buf, 2 * sizeof(__le16)); } -static int ltr501_read_ps(struct ltr501_data *data) +static int ltr501_read_ps(const struct ltr501_data *data) { int ret, status; @@ -419,7 +420,7 @@ static int ltr501_read_ps(struct ltr501_data *data) return status; } -static int ltr501_read_intr_prst(struct ltr501_data *data, +static int ltr501_read_intr_prst(const struct ltr501_data *data, enum iio_chan_type type, int *val2) { @@ -716,7 +717,7 @@ static int ltr501_read_raw(struct iio_dev *indio_dev, return -EINVAL; } -static int ltr501_get_gain_index(struct ltr501_gain *gain, int size, +static int ltr501_get_gain_index(const struct ltr501_gain *gain, int size, int val, int val2) { int i; @@ -848,14 +849,14 @@ static int ltr501_write_raw(struct iio_dev *indio_dev, return ret; } -static int ltr501_read_thresh(struct iio_dev *indio_dev, +static int ltr501_read_thresh(const struct iio_dev *indio_dev, const struct iio_chan_spec *chan, enum iio_event_type type, enum iio_event_direction dir, enum iio_event_info info, int *val, int *val2) { - struct ltr501_data *data = iio_priv(indio_dev); + const struct ltr501_data *data = iio_priv(indio_dev); int ret, thresh_data; switch (chan->type) { @@ -1263,7 +1264,7 @@ static irqreturn_t ltr501_trigger_handler(int irq, void *p) if (mask & LTR501_STATUS_ALS_RDY) { ret = regmap_bulk_read(data->regmap, LTR501_ALS_DATA1, - (u8 *)als_buf, sizeof(als_buf)); + als_buf, sizeof(als_buf)); if (ret < 0) return ret; if (test_bit(0, indio_dev->active_scan_mask)) @@ -1359,7 +1360,7 @@ static bool ltr501_is_volatile_reg(struct device *dev, unsigned int reg) } } -static struct regmap_config ltr501_regmap_config = { +static const struct regmap_config ltr501_regmap_config = { .name = LTR501_REGMAP_NAME, .reg_bits = 8, .val_bits = 8, diff --git a/drivers/iio/light/opt3001.c b/drivers/iio/light/opt3001.c index 92004a2563ea..82abfa57b59c 100644 --- a/drivers/iio/light/opt3001.c +++ b/drivers/iio/light/opt3001.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -844,7 +845,7 @@ static struct i2c_driver opt3001_driver = { .driver = { .name = "opt3001", - .of_match_table = of_match_ptr(opt3001_of_match), + .of_match_table = opt3001_of_match, }, }; diff --git a/drivers/iio/light/si1133.c b/drivers/iio/light/si1133.c index 9174ab928880..c1adab2a50fd 100644 --- a/drivers/iio/light/si1133.c +++ b/drivers/iio/light/si1133.c @@ -17,6 +17,8 @@ #include +#include + #define SI1133_REG_PART_ID 0x00 #define SI1133_REG_REV_ID 0x01 #define SI1133_REG_MFR_ID 0x02 @@ -104,8 +106,6 @@ #define SI1133_LUX_BUFFER_SIZE 9 #define SI1133_MEASURE_BUFFER_SIZE 3 -#define SI1133_SIGN_BIT_INDEX 23 - static const int si1133_scale_available[] = { 1, 2, 4, 8, 16, 32, 64, 128}; @@ -633,8 +633,7 @@ static int si1133_measure(struct si1133_data *data, if (err) return err; - *val = sign_extend32((buffer[0] << 16) | (buffer[1] << 8) | buffer[2], - SI1133_SIGN_BIT_INDEX); + *val = sign_extend32(get_unaligned_be24(&buffer[0]), 23); return err; } @@ -723,16 +722,11 @@ static int si1133_get_lux(struct si1133_data *data, int *val) if (err) return err; - high_vis = - sign_extend32((buffer[0] << 16) | (buffer[1] << 8) | buffer[2], - SI1133_SIGN_BIT_INDEX); + high_vis = sign_extend32(get_unaligned_be24(&buffer[0]), 23); - low_vis = - sign_extend32((buffer[3] << 16) | (buffer[4] << 8) | buffer[5], - SI1133_SIGN_BIT_INDEX); + low_vis = sign_extend32(get_unaligned_be24(&buffer[3]), 23); - ir = sign_extend32((buffer[6] << 16) | (buffer[7] << 8) | buffer[8], - SI1133_SIGN_BIT_INDEX); + ir = sign_extend32(get_unaligned_be24(&buffer[6]), 23); if (high_vis > SI1133_ADC_THRESHOLD || ir > SI1133_ADC_THRESHOLD) lux = si1133_calc_polynomial(high_vis, ir, diff --git a/drivers/iio/light/st_uvis25_i2c.c b/drivers/iio/light/st_uvis25_i2c.c index 4889bbeb0c73..98cd49eefe45 100644 --- a/drivers/iio/light/st_uvis25_i2c.c +++ b/drivers/iio/light/st_uvis25_i2c.c @@ -9,6 +9,7 @@ #include #include +#include #include #include #include @@ -31,8 +32,8 @@ static int st_uvis25_i2c_probe(struct i2c_client *client, regmap = devm_regmap_init_i2c(client, &st_uvis25_i2c_regmap_config); if (IS_ERR(regmap)) { - dev_err(&client->dev, "Failed to register i2c regmap %d\n", - (int)PTR_ERR(regmap)); + dev_err(&client->dev, "Failed to register i2c regmap %ld\n", + PTR_ERR(regmap)); return PTR_ERR(regmap); } @@ -55,7 +56,7 @@ static struct i2c_driver st_uvis25_driver = { .driver = { .name = "st_uvis25_i2c", .pm = &st_uvis25_pm_ops, - .of_match_table = of_match_ptr(st_uvis25_i2c_of_match), + .of_match_table = st_uvis25_i2c_of_match, }, .probe = st_uvis25_i2c_probe, .id_table = st_uvis25_i2c_id_table, diff --git a/drivers/iio/light/st_uvis25_spi.c b/drivers/iio/light/st_uvis25_spi.c index a9ceae4f58b3..af9d94d12787 100644 --- a/drivers/iio/light/st_uvis25_spi.c +++ b/drivers/iio/light/st_uvis25_spi.c @@ -9,6 +9,7 @@ #include #include +#include #include #include #include @@ -31,8 +32,8 @@ static int st_uvis25_spi_probe(struct spi_device *spi) regmap = devm_regmap_init_spi(spi, &st_uvis25_spi_regmap_config); if (IS_ERR(regmap)) { - dev_err(&spi->dev, "Failed to register spi regmap %d\n", - (int)PTR_ERR(regmap)); + dev_err(&spi->dev, "Failed to register spi regmap %ld\n", + PTR_ERR(regmap)); return PTR_ERR(regmap); } @@ -55,7 +56,7 @@ static struct spi_driver st_uvis25_driver = { .driver = { .name = "st_uvis25_spi", .pm = &st_uvis25_pm_ops, - .of_match_table = of_match_ptr(st_uvis25_spi_of_match), + .of_match_table = st_uvis25_spi_of_match, }, .probe = st_uvis25_spi_probe, .id_table = st_uvis25_spi_id_table, diff --git a/drivers/iio/light/tsl2563.c b/drivers/iio/light/tsl2563.c index d8c40a83097d..27a5c28aac7f 100644 --- a/drivers/iio/light/tsl2563.c +++ b/drivers/iio/light/tsl2563.c @@ -69,7 +69,7 @@ #define TSL2563_TIMING_GAIN16 0x10 #define TSL2563_TIMING_GAIN1 0x00 -#define TSL2563_INT_DISBLED 0x00 +#define TSL2563_INT_DISABLED 0x00 #define TSL2563_INT_LEVEL 0x10 #define TSL2563_INT_PERSIST(n) ((n) & 0x0F) diff --git a/drivers/iio/light/tsl2772.c b/drivers/iio/light/tsl2772.c index be37fcbd4654..9fbde9b71b63 100644 --- a/drivers/iio/light/tsl2772.c +++ b/drivers/iio/light/tsl2772.c @@ -932,7 +932,7 @@ static ssize_t in_illuminance0_target_input_show(struct device *dev, { struct tsl2772_chip *chip = iio_priv(dev_to_iio_dev(dev)); - return snprintf(buf, PAGE_SIZE, "%d\n", chip->settings.als_cal_target); + return scnprintf(buf, PAGE_SIZE, "%d\n", chip->settings.als_cal_target); } static ssize_t in_illuminance0_target_input_store(struct device *dev, @@ -986,7 +986,7 @@ static ssize_t in_illuminance0_lux_table_show(struct device *dev, int offset = 0; while (i < TSL2772_MAX_LUX_TABLE_SIZE) { - offset += snprintf(buf + offset, PAGE_SIZE, "%u,%u,", + offset += scnprintf(buf + offset, PAGE_SIZE - offset, "%u,%u,", chip->tsl2772_device_lux[i].ch0, chip->tsl2772_device_lux[i].ch1); if (chip->tsl2772_device_lux[i].ch0 == 0) { @@ -1000,7 +1000,7 @@ static ssize_t in_illuminance0_lux_table_show(struct device *dev, i++; } - offset += snprintf(buf + offset, PAGE_SIZE, "\n"); + offset += scnprintf(buf + offset, PAGE_SIZE - offset, "\n"); return offset; } diff --git a/drivers/iio/light/vcnl4000.c b/drivers/iio/light/vcnl4000.c index ec803c1e81df..2a4b3d331055 100644 --- a/drivers/iio/light/vcnl4000.c +++ b/drivers/iio/light/vcnl4000.c @@ -5,6 +5,7 @@ * * Copyright 2012 Peter Meerwald * Copyright 2019 Pursim SPC + * Copyright 2020 Mathieu Othacehe * * IIO driver for: * VCNL4000/10/20 (7-bit I2C slave address 0x13) @@ -13,9 +14,7 @@ * * TODO: * allow to adjust IR current - * proximity threshold and event handling - * periodic ALS/proximity measurement (VCNL4010/20) - * interrupts (VCNL4010/20/40, VCNL4200) + * interrupts (VCNL4040, VCNL4200) */ #include @@ -23,9 +22,15 @@ #include #include #include +#include +#include +#include #include #include +#include +#include +#include #define VCNL4000_DRV_NAME "vcnl4000" #define VCNL4000_PROD_ID 0x01 @@ -35,14 +40,22 @@ #define VCNL4000_COMMAND 0x80 /* Command register */ #define VCNL4000_PROD_REV 0x81 /* Product ID and Revision ID */ +#define VCNL4010_PROX_RATE 0x82 /* Proximity rate */ #define VCNL4000_LED_CURRENT 0x83 /* IR LED current for proximity mode */ #define VCNL4000_AL_PARAM 0x84 /* Ambient light parameter register */ +#define VCNL4010_ALS_PARAM 0x84 /* ALS rate */ #define VCNL4000_AL_RESULT_HI 0x85 /* Ambient light result register, MSB */ #define VCNL4000_AL_RESULT_LO 0x86 /* Ambient light result register, LSB */ #define VCNL4000_PS_RESULT_HI 0x87 /* Proximity result register, MSB */ #define VCNL4000_PS_RESULT_LO 0x88 /* Proximity result register, LSB */ #define VCNL4000_PS_MEAS_FREQ 0x89 /* Proximity test signal frequency */ +#define VCNL4010_INT_CTRL 0x89 /* Interrupt control */ #define VCNL4000_PS_MOD_ADJ 0x8a /* Proximity modulator timing adjustment */ +#define VCNL4010_LOW_THR_HI 0x8a /* Low threshold, MSB */ +#define VCNL4010_LOW_THR_LO 0x8b /* Low threshold, LSB */ +#define VCNL4010_HIGH_THR_HI 0x8c /* High threshold, MSB */ +#define VCNL4010_HIGH_THR_LO 0x8d /* High threshold, LSB */ +#define VCNL4010_ISR 0x8e /* Interrupt status */ #define VCNL4200_AL_CONF 0x00 /* Ambient light configuration */ #define VCNL4200_PS_CONF1 0x03 /* Proximity configuration */ @@ -57,6 +70,36 @@ #define VCNL4000_PS_RDY BIT(5) /* proximity data ready? */ #define VCNL4000_AL_OD BIT(4) /* start on-demand ALS measurement */ #define VCNL4000_PS_OD BIT(3) /* start on-demand proximity measurement */ +#define VCNL4000_ALS_EN BIT(2) /* start ALS measurement */ +#define VCNL4000_PROX_EN BIT(1) /* start proximity measurement */ +#define VCNL4000_SELF_TIMED_EN BIT(0) /* start self-timed measurement */ + +/* Bit masks for interrupt registers. */ +#define VCNL4010_INT_THR_SEL BIT(0) /* Select threshold interrupt source */ +#define VCNL4010_INT_THR_EN BIT(1) /* Threshold interrupt type */ +#define VCNL4010_INT_ALS_EN BIT(2) /* Enable on ALS data ready */ +#define VCNL4010_INT_PROX_EN BIT(3) /* Enable on proximity data ready */ + +#define VCNL4010_INT_THR_HIGH 0 /* High threshold exceeded */ +#define VCNL4010_INT_THR_LOW 1 /* Low threshold exceeded */ +#define VCNL4010_INT_ALS 2 /* ALS data ready */ +#define VCNL4010_INT_PROXIMITY 3 /* Proximity data ready */ + +#define VCNL4010_INT_THR \ + (BIT(VCNL4010_INT_THR_LOW) | BIT(VCNL4010_INT_THR_HIGH)) +#define VCNL4010_INT_DRDY \ + (BIT(VCNL4010_INT_PROXIMITY) | BIT(VCNL4010_INT_ALS)) + +static const int vcnl4010_prox_sampling_frequency[][2] = { + {1, 950000}, + {3, 906250}, + {7, 812500}, + {16, 625000}, + {31, 250000}, + {62, 500000}, + {125, 0}, + {250, 0}, +}; #define VCNL4000_SLEEP_DELAY_MS 2000 /* before we enter pm_runtime_suspend */ @@ -83,10 +126,15 @@ struct vcnl4000_data { struct mutex vcnl4000_lock; struct vcnl4200_channel vcnl4200_al; struct vcnl4200_channel vcnl4200_ps; + uint32_t near_level; }; struct vcnl4000_chip_spec { const char *prod; + struct iio_chan_spec const *channels; + const int num_channels; + const struct iio_info *info; + bool irq_support; int (*init)(struct vcnl4000_data *data); int (*measure_light)(struct vcnl4000_data *data, int *val); int (*measure_proximity)(struct vcnl4000_data *data, int *val); @@ -215,11 +263,31 @@ static int vcnl4200_init(struct vcnl4000_data *data) return 0; }; +static int vcnl4000_read_data(struct vcnl4000_data *data, u8 data_reg, int *val) +{ + s32 ret; + + ret = i2c_smbus_read_word_swapped(data->client, data_reg); + if (ret < 0) + return ret; + + *val = ret; + return 0; +} + +static int vcnl4000_write_data(struct vcnl4000_data *data, u8 data_reg, int val) +{ + if (val > U16_MAX) + return -ERANGE; + + return i2c_smbus_write_word_swapped(data->client, data_reg, val); +} + + static int vcnl4000_measure(struct vcnl4000_data *data, u8 req_mask, u8 rdy_mask, u8 data_reg, int *val) { int tries = 20; - __be16 buf; int ret; mutex_lock(&data->vcnl4000_lock); @@ -246,13 +314,11 @@ static int vcnl4000_measure(struct vcnl4000_data *data, u8 req_mask, goto fail; } - ret = i2c_smbus_read_i2c_block_data(data->client, - data_reg, sizeof(buf), (u8 *) &buf); + ret = vcnl4000_read_data(data, data_reg, val); if (ret < 0) goto fail; mutex_unlock(&data->vcnl4000_lock); - *val = be16_to_cpu(buf); return 0; @@ -312,47 +378,34 @@ static int vcnl4200_measure_proximity(struct vcnl4000_data *data, int *val) return vcnl4200_measure(data, &data->vcnl4200_ps, val); } -static const struct vcnl4000_chip_spec vcnl4000_chip_spec_cfg[] = { - [VCNL4000] = { - .prod = "VCNL4000", - .init = vcnl4000_init, - .measure_light = vcnl4000_measure_light, - .measure_proximity = vcnl4000_measure_proximity, - .set_power_state = vcnl4000_set_power_state, - }, - [VCNL4010] = { - .prod = "VCNL4010/4020", - .init = vcnl4000_init, - .measure_light = vcnl4000_measure_light, - .measure_proximity = vcnl4000_measure_proximity, - .set_power_state = vcnl4000_set_power_state, - }, - [VCNL4040] = { - .prod = "VCNL4040", - .init = vcnl4200_init, - .measure_light = vcnl4200_measure_light, - .measure_proximity = vcnl4200_measure_proximity, - .set_power_state = vcnl4200_set_power_state, - }, - [VCNL4200] = { - .prod = "VCNL4200", - .init = vcnl4200_init, - .measure_light = vcnl4200_measure_light, - .measure_proximity = vcnl4200_measure_proximity, - .set_power_state = vcnl4200_set_power_state, - }, -}; +static int vcnl4010_read_proxy_samp_freq(struct vcnl4000_data *data, int *val, + int *val2) +{ + int ret; -static const struct iio_chan_spec vcnl4000_channels[] = { - { - .type = IIO_LIGHT, - .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | - BIT(IIO_CHAN_INFO_SCALE), - }, { - .type = IIO_PROXIMITY, - .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), - } -}; + ret = i2c_smbus_read_byte_data(data->client, VCNL4010_PROX_RATE); + if (ret < 0) + return ret; + + if (ret >= ARRAY_SIZE(vcnl4010_prox_sampling_frequency)) + return -EINVAL; + + *val = vcnl4010_prox_sampling_frequency[ret][0]; + *val2 = vcnl4010_prox_sampling_frequency[ret][1]; + + return 0; +} + +static bool vcnl4010_is_in_periodic_mode(struct vcnl4000_data *data) +{ + int ret; + + ret = i2c_smbus_read_byte_data(data->client, VCNL4000_COMMAND); + if (ret < 0) + return false; + + return !!(ret & VCNL4000_SELF_TIMED_EN); +} static int vcnl4000_set_pm_runtime_state(struct vcnl4000_data *data, bool on) { @@ -412,10 +465,571 @@ static int vcnl4000_read_raw(struct iio_dev *indio_dev, } } +static int vcnl4010_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + int ret; + struct vcnl4000_data *data = iio_priv(indio_dev); + + switch (mask) { + case IIO_CHAN_INFO_RAW: + case IIO_CHAN_INFO_SCALE: + ret = iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; + + /* Protect against event capture. */ + if (vcnl4010_is_in_periodic_mode(data)) { + ret = -EBUSY; + } else { + ret = vcnl4000_read_raw(indio_dev, chan, val, val2, + mask); + } + + iio_device_release_direct_mode(indio_dev); + return ret; + case IIO_CHAN_INFO_SAMP_FREQ: + switch (chan->type) { + case IIO_PROXIMITY: + ret = vcnl4010_read_proxy_samp_freq(data, val, val2); + if (ret < 0) + return ret; + return IIO_VAL_INT_PLUS_MICRO; + default: + return -EINVAL; + } + default: + return -EINVAL; + } +} + +static int vcnl4010_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, int *type, int *length, + long mask) +{ + switch (mask) { + case IIO_CHAN_INFO_SAMP_FREQ: + *vals = (int *)vcnl4010_prox_sampling_frequency; + *type = IIO_VAL_INT_PLUS_MICRO; + *length = 2 * ARRAY_SIZE(vcnl4010_prox_sampling_frequency); + return IIO_AVAIL_LIST; + default: + return -EINVAL; + } +} + +static int vcnl4010_write_proxy_samp_freq(struct vcnl4000_data *data, int val, + int val2) +{ + unsigned int i; + int index = -1; + + for (i = 0; i < ARRAY_SIZE(vcnl4010_prox_sampling_frequency); i++) { + if (val == vcnl4010_prox_sampling_frequency[i][0] && + val2 == vcnl4010_prox_sampling_frequency[i][1]) { + index = i; + break; + } + } + + if (index < 0) + return -EINVAL; + + return i2c_smbus_write_byte_data(data->client, VCNL4010_PROX_RATE, + index); +} + +static int vcnl4010_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long mask) +{ + int ret; + struct vcnl4000_data *data = iio_priv(indio_dev); + + ret = iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; + + /* Protect against event capture. */ + if (vcnl4010_is_in_periodic_mode(data)) { + ret = -EBUSY; + goto end; + } + + switch (mask) { + case IIO_CHAN_INFO_SAMP_FREQ: + switch (chan->type) { + case IIO_PROXIMITY: + ret = vcnl4010_write_proxy_samp_freq(data, val, val2); + goto end; + default: + ret = -EINVAL; + goto end; + } + default: + ret = -EINVAL; + goto end; + } + +end: + iio_device_release_direct_mode(indio_dev); + return ret; +} + +static int vcnl4010_read_event(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + enum iio_event_info info, + int *val, int *val2) +{ + int ret; + struct vcnl4000_data *data = iio_priv(indio_dev); + + switch (info) { + case IIO_EV_INFO_VALUE: + switch (dir) { + case IIO_EV_DIR_RISING: + ret = vcnl4000_read_data(data, VCNL4010_HIGH_THR_HI, + val); + if (ret < 0) + return ret; + return IIO_VAL_INT; + case IIO_EV_DIR_FALLING: + ret = vcnl4000_read_data(data, VCNL4010_LOW_THR_HI, + val); + if (ret < 0) + return ret; + return IIO_VAL_INT; + default: + return -EINVAL; + } + default: + return -EINVAL; + } +} + +static int vcnl4010_write_event(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + enum iio_event_info info, + int val, int val2) +{ + int ret; + struct vcnl4000_data *data = iio_priv(indio_dev); + + switch (info) { + case IIO_EV_INFO_VALUE: + switch (dir) { + case IIO_EV_DIR_RISING: + ret = vcnl4000_write_data(data, VCNL4010_HIGH_THR_HI, + val); + if (ret < 0) + return ret; + return IIO_VAL_INT; + case IIO_EV_DIR_FALLING: + ret = vcnl4000_write_data(data, VCNL4010_LOW_THR_HI, + val); + if (ret < 0) + return ret; + return IIO_VAL_INT; + default: + return -EINVAL; + } + default: + return -EINVAL; + } +} + +static bool vcnl4010_is_thr_enabled(struct vcnl4000_data *data) +{ + int ret; + + ret = i2c_smbus_read_byte_data(data->client, VCNL4010_INT_CTRL); + if (ret < 0) + return false; + + return !!(ret & VCNL4010_INT_THR_EN); +} + +static int vcnl4010_read_event_config(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir) +{ + struct vcnl4000_data *data = iio_priv(indio_dev); + + switch (chan->type) { + case IIO_PROXIMITY: + return vcnl4010_is_thr_enabled(data); + default: + return -EINVAL; + } +} + +static int vcnl4010_config_threshold(struct iio_dev *indio_dev, bool state) +{ + struct vcnl4000_data *data = iio_priv(indio_dev); + int ret; + int icr; + int command; + + if (state) { + ret = iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; + + /* Enable periodic measurement of proximity data. */ + command = VCNL4000_SELF_TIMED_EN | VCNL4000_PROX_EN; + + /* + * Enable interrupts on threshold, for proximity data by + * default. + */ + icr = VCNL4010_INT_THR_EN; + } else { + if (!vcnl4010_is_thr_enabled(data)) + return 0; + + command = 0; + icr = 0; + } + + ret = i2c_smbus_write_byte_data(data->client, VCNL4000_COMMAND, + command); + if (ret < 0) + goto end; + + ret = i2c_smbus_write_byte_data(data->client, VCNL4010_INT_CTRL, icr); + +end: + if (state) + iio_device_release_direct_mode(indio_dev); + + return ret; +} + +static int vcnl4010_write_event_config(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + int state) +{ + switch (chan->type) { + case IIO_PROXIMITY: + return vcnl4010_config_threshold(indio_dev, state); + default: + return -EINVAL; + } +} + +static ssize_t vcnl4000_read_near_level(struct iio_dev *indio_dev, + uintptr_t priv, + const struct iio_chan_spec *chan, + char *buf) +{ + struct vcnl4000_data *data = iio_priv(indio_dev); + + return sprintf(buf, "%u\n", data->near_level); +} + +static const struct iio_chan_spec_ext_info vcnl4000_ext_info[] = { + { + .name = "nearlevel", + .shared = IIO_SEPARATE, + .read = vcnl4000_read_near_level, + }, + { /* sentinel */ } +}; + +static const struct iio_event_spec vcnl4000_event_spec[] = { + { + .type = IIO_EV_TYPE_THRESH, + .dir = IIO_EV_DIR_RISING, + .mask_separate = BIT(IIO_EV_INFO_VALUE), + }, { + .type = IIO_EV_TYPE_THRESH, + .dir = IIO_EV_DIR_FALLING, + .mask_separate = BIT(IIO_EV_INFO_VALUE), + }, { + .type = IIO_EV_TYPE_THRESH, + .dir = IIO_EV_DIR_EITHER, + .mask_separate = BIT(IIO_EV_INFO_ENABLE), + } +}; + +static const struct iio_chan_spec vcnl4000_channels[] = { + { + .type = IIO_LIGHT, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + }, { + .type = IIO_PROXIMITY, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), + .ext_info = vcnl4000_ext_info, + } +}; + +static const struct iio_chan_spec vcnl4010_channels[] = { + { + .type = IIO_LIGHT, + .scan_index = -1, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + }, { + .type = IIO_PROXIMITY, + .scan_index = 0, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SAMP_FREQ), + .info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), + .event_spec = vcnl4000_event_spec, + .num_event_specs = ARRAY_SIZE(vcnl4000_event_spec), + .ext_info = vcnl4000_ext_info, + .scan_type = { + .sign = 'u', + .realbits = 16, + .storagebits = 16, + .endianness = IIO_CPU, + }, + }, + IIO_CHAN_SOFT_TIMESTAMP(1), +}; + static const struct iio_info vcnl4000_info = { .read_raw = vcnl4000_read_raw, }; +static const struct iio_info vcnl4010_info = { + .read_raw = vcnl4010_read_raw, + .read_avail = vcnl4010_read_avail, + .write_raw = vcnl4010_write_raw, + .read_event_value = vcnl4010_read_event, + .write_event_value = vcnl4010_write_event, + .read_event_config = vcnl4010_read_event_config, + .write_event_config = vcnl4010_write_event_config, +}; + +static const struct vcnl4000_chip_spec vcnl4000_chip_spec_cfg[] = { + [VCNL4000] = { + .prod = "VCNL4000", + .init = vcnl4000_init, + .measure_light = vcnl4000_measure_light, + .measure_proximity = vcnl4000_measure_proximity, + .set_power_state = vcnl4000_set_power_state, + .channels = vcnl4000_channels, + .num_channels = ARRAY_SIZE(vcnl4000_channels), + .info = &vcnl4000_info, + .irq_support = false, + }, + [VCNL4010] = { + .prod = "VCNL4010/4020", + .init = vcnl4000_init, + .measure_light = vcnl4000_measure_light, + .measure_proximity = vcnl4000_measure_proximity, + .set_power_state = vcnl4000_set_power_state, + .channels = vcnl4010_channels, + .num_channels = ARRAY_SIZE(vcnl4010_channels), + .info = &vcnl4010_info, + .irq_support = true, + }, + [VCNL4040] = { + .prod = "VCNL4040", + .init = vcnl4200_init, + .measure_light = vcnl4200_measure_light, + .measure_proximity = vcnl4200_measure_proximity, + .set_power_state = vcnl4200_set_power_state, + .channels = vcnl4000_channels, + .num_channels = ARRAY_SIZE(vcnl4000_channels), + .info = &vcnl4000_info, + .irq_support = false, + }, + [VCNL4200] = { + .prod = "VCNL4200", + .init = vcnl4200_init, + .measure_light = vcnl4200_measure_light, + .measure_proximity = vcnl4200_measure_proximity, + .set_power_state = vcnl4200_set_power_state, + .channels = vcnl4000_channels, + .num_channels = ARRAY_SIZE(vcnl4000_channels), + .info = &vcnl4000_info, + .irq_support = false, + }, +}; + +static irqreturn_t vcnl4010_irq_thread(int irq, void *p) +{ + struct iio_dev *indio_dev = p; + struct vcnl4000_data *data = iio_priv(indio_dev); + unsigned long isr; + int ret; + + ret = i2c_smbus_read_byte_data(data->client, VCNL4010_ISR); + if (ret < 0) + goto end; + + isr = ret; + + if (isr & VCNL4010_INT_THR) { + if (test_bit(VCNL4010_INT_THR_LOW, &isr)) { + iio_push_event(indio_dev, + IIO_UNMOD_EVENT_CODE( + IIO_PROXIMITY, + 1, + IIO_EV_TYPE_THRESH, + IIO_EV_DIR_FALLING), + iio_get_time_ns(indio_dev)); + } + + if (test_bit(VCNL4010_INT_THR_HIGH, &isr)) { + iio_push_event(indio_dev, + IIO_UNMOD_EVENT_CODE( + IIO_PROXIMITY, + 1, + IIO_EV_TYPE_THRESH, + IIO_EV_DIR_RISING), + iio_get_time_ns(indio_dev)); + } + + i2c_smbus_write_byte_data(data->client, VCNL4010_ISR, + isr & VCNL4010_INT_THR); + } + + if (isr & VCNL4010_INT_DRDY && iio_buffer_enabled(indio_dev)) + iio_trigger_poll_chained(indio_dev->trig); + +end: + return IRQ_HANDLED; +} + +static irqreturn_t vcnl4010_trigger_handler(int irq, void *p) +{ + struct iio_poll_func *pf = p; + struct iio_dev *indio_dev = pf->indio_dev; + struct vcnl4000_data *data = iio_priv(indio_dev); + const unsigned long *active_scan_mask = indio_dev->active_scan_mask; + u16 buffer[8] = {0}; /* 1x16-bit + ts */ + bool data_read = false; + unsigned long isr; + int val = 0; + int ret; + + ret = i2c_smbus_read_byte_data(data->client, VCNL4010_ISR); + if (ret < 0) + goto end; + + isr = ret; + + if (test_bit(0, active_scan_mask)) { + if (test_bit(VCNL4010_INT_PROXIMITY, &isr)) { + ret = vcnl4000_read_data(data, + VCNL4000_PS_RESULT_HI, + &val); + if (ret < 0) + goto end; + + buffer[0] = val; + data_read = true; + } + } + + ret = i2c_smbus_write_byte_data(data->client, VCNL4010_ISR, + isr & VCNL4010_INT_DRDY); + if (ret < 0) + goto end; + + if (!data_read) + goto end; + + iio_push_to_buffers_with_timestamp(indio_dev, buffer, + iio_get_time_ns(indio_dev)); + +end: + iio_trigger_notify_done(indio_dev->trig); + return IRQ_HANDLED; +} + +static int vcnl4010_buffer_postenable(struct iio_dev *indio_dev) +{ + struct vcnl4000_data *data = iio_priv(indio_dev); + int ret; + int cmd; + + ret = iio_triggered_buffer_postenable(indio_dev); + if (ret) + return ret; + + /* Do not enable the buffer if we are already capturing events. */ + if (vcnl4010_is_in_periodic_mode(data)) { + ret = -EBUSY; + goto end; + } + + ret = i2c_smbus_write_byte_data(data->client, VCNL4010_INT_CTRL, + VCNL4010_INT_PROX_EN); + if (ret < 0) + goto end; + + cmd = VCNL4000_SELF_TIMED_EN | VCNL4000_PROX_EN; + ret = i2c_smbus_write_byte_data(data->client, VCNL4000_COMMAND, cmd); + if (ret < 0) + goto end; + + return 0; +end: + iio_triggered_buffer_predisable(indio_dev); + + return ret; +} + +static int vcnl4010_buffer_predisable(struct iio_dev *indio_dev) +{ + struct vcnl4000_data *data = iio_priv(indio_dev); + int ret, ret_disable; + + ret = i2c_smbus_write_byte_data(data->client, VCNL4010_INT_CTRL, 0); + if (ret < 0) + goto end; + + ret = i2c_smbus_write_byte_data(data->client, VCNL4000_COMMAND, 0); + +end: + ret_disable = iio_triggered_buffer_predisable(indio_dev); + if (ret == 0) + ret = ret_disable; + + return ret; +} + +static const struct iio_buffer_setup_ops vcnl4010_buffer_ops = { + .postenable = &vcnl4010_buffer_postenable, + .predisable = &vcnl4010_buffer_predisable, +}; + +static const struct iio_trigger_ops vcnl4010_trigger_ops = { + .validate_device = iio_trigger_validate_own_device, +}; + +static int vcnl4010_probe_trigger(struct iio_dev *indio_dev) +{ + struct vcnl4000_data *data = iio_priv(indio_dev); + struct i2c_client *client = data->client; + struct iio_trigger *trigger; + + trigger = devm_iio_trigger_alloc(&client->dev, "%s-dev%d", + indio_dev->name, indio_dev->id); + if (!trigger) + return -ENOMEM; + + trigger->dev.parent = &client->dev; + trigger->ops = &vcnl4010_trigger_ops; + iio_trigger_set_drvdata(trigger, indio_dev); + + return devm_iio_trigger_register(&client->dev, trigger); +} + static int vcnl4000_probe(struct i2c_client *client, const struct i2c_device_id *id) { @@ -440,13 +1054,44 @@ static int vcnl4000_probe(struct i2c_client *client, dev_dbg(&client->dev, "%s Ambient light/proximity sensor, Rev: %02x\n", data->chip_spec->prod, data->rev); + if (device_property_read_u32(&client->dev, "proximity-near-level", + &data->near_level)) + data->near_level = 0; + indio_dev->dev.parent = &client->dev; - indio_dev->info = &vcnl4000_info; - indio_dev->channels = vcnl4000_channels; - indio_dev->num_channels = ARRAY_SIZE(vcnl4000_channels); + indio_dev->info = data->chip_spec->info; + indio_dev->channels = data->chip_spec->channels; + indio_dev->num_channels = data->chip_spec->num_channels; indio_dev->name = VCNL4000_DRV_NAME; indio_dev->modes = INDIO_DIRECT_MODE; + if (client->irq && data->chip_spec->irq_support) { + ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, + NULL, + vcnl4010_trigger_handler, + &vcnl4010_buffer_ops); + if (ret < 0) { + dev_err(&client->dev, + "unable to setup iio triggered buffer\n"); + return ret; + } + + ret = devm_request_threaded_irq(&client->dev, client->irq, + NULL, vcnl4010_irq_thread, + IRQF_TRIGGER_FALLING | + IRQF_ONESHOT, + "vcnl4010_irq", + indio_dev); + if (ret < 0) { + dev_err(&client->dev, "irq request failed\n"); + return ret; + } + + ret = vcnl4010_probe_trigger(indio_dev); + if (ret < 0) + return ret; + } + ret = pm_runtime_set_active(&client->dev); if (ret < 0) goto fail_poweroff; @@ -540,5 +1185,6 @@ static struct i2c_driver vcnl4000_driver = { module_i2c_driver(vcnl4000_driver); MODULE_AUTHOR("Peter Meerwald "); +MODULE_AUTHOR("Mathieu Othacehe "); MODULE_DESCRIPTION("Vishay VCNL4000 proximity/ambient light sensor driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/iio/light/vl6180.c b/drivers/iio/light/vl6180.c index d9533a76b8f6..ed7b02765b97 100644 --- a/drivers/iio/light/vl6180.c +++ b/drivers/iio/light/vl6180.c @@ -16,6 +16,7 @@ */ #include +#include #include #include #include @@ -537,7 +538,7 @@ MODULE_DEVICE_TABLE(i2c, vl6180_id); static struct i2c_driver vl6180_driver = { .driver = { .name = VL6180_DRV_NAME, - .of_match_table = of_match_ptr(vl6180_of_match), + .of_match_table = vl6180_of_match, }, .probe = vl6180_probe, .id_table = vl6180_id, diff --git a/drivers/iio/light/zopt2201.c b/drivers/iio/light/zopt2201.c index 5f54f39e7a4c..80ae530720cd 100644 --- a/drivers/iio/light/zopt2201.c +++ b/drivers/iio/light/zopt2201.c @@ -19,6 +19,8 @@ #include #include +#include + #define ZOPT2201_DRV_NAME "zopt2201" /* Registers */ @@ -219,7 +221,7 @@ static int zopt2201_read(struct zopt2201_data *data, u8 reg) goto fail; mutex_unlock(&data->lock); - return (buf[2] << 16) | (buf[1] << 8) | buf[0]; + return get_unaligned_le24(&buf[0]); fail: mutex_unlock(&data->lock); diff --git a/drivers/iio/magnetometer/ak8974.c b/drivers/iio/magnetometer/ak8974.c index d32996702110..810fdfd37c88 100644 --- a/drivers/iio/magnetometer/ak8974.c +++ b/drivers/iio/magnetometer/ak8974.c @@ -49,6 +49,7 @@ #define AK8974_WHOAMI_VALUE_AMI306 0x46 #define AK8974_WHOAMI_VALUE_AMI305 0x47 #define AK8974_WHOAMI_VALUE_AK8974 0x48 +#define AK8974_WHOAMI_VALUE_HSCDTD008A 0x49 #define AK8974_DATA_X 0x10 #define AK8974_DATA_Y 0x12 @@ -140,6 +141,12 @@ #define AK8974_INT_CTRL_PULSE BIT(1) /* 0 = latched; 1 = pulse (50 usec) */ #define AK8974_INT_CTRL_RESDEF (AK8974_INT_CTRL_XYZEN | AK8974_INT_CTRL_POL) +/* HSCDTD008A-specific control register */ +#define HSCDTD008A_CTRL4 0x1E +#define HSCDTD008A_CTRL4_MMD BIT(7) /* must be set to 1 */ +#define HSCDTD008A_CTRL4_RANGE BIT(4) /* 0 = 14-bit output; 1 = 15-bit output */ +#define HSCDTD008A_CTRL4_RESDEF (HSCDTD008A_CTRL4_MMD | HSCDTD008A_CTRL4_RANGE) + /* The AMI305 has elaborate FW version and serial number registers */ #define AMI305_VER 0xE8 #define AMI305_SN 0xEA @@ -241,10 +248,17 @@ static int ak8974_reset(struct ak8974 *ak8974) ret = regmap_write(ak8974->map, AK8974_CTRL3, AK8974_CTRL3_RESDEF); if (ret) return ret; - ret = regmap_write(ak8974->map, AK8974_INT_CTRL, - AK8974_INT_CTRL_RESDEF); - if (ret) - return ret; + if (ak8974->variant != AK8974_WHOAMI_VALUE_HSCDTD008A) { + ret = regmap_write(ak8974->map, AK8974_INT_CTRL, + AK8974_INT_CTRL_RESDEF); + if (ret) + return ret; + } else { + ret = regmap_write(ak8974->map, HSCDTD008A_CTRL4, + HSCDTD008A_CTRL4_RESDEF); + if (ret) + return ret; + } /* After reset, power off is default state */ return ak8974_set_power(ak8974, AK8974_PWR_OFF); @@ -267,6 +281,8 @@ static int ak8974_configure(struct ak8974 *ak8974) if (ret) return ret; } + if (ak8974->variant == AK8974_WHOAMI_VALUE_HSCDTD008A) + return 0; ret = regmap_write(ak8974->map, AK8974_INT_CTRL, AK8974_INT_CTRL_POL); if (ret) return ret; @@ -495,6 +511,10 @@ static int ak8974_detect(struct ak8974 *ak8974) name = "ak8974"; dev_info(&ak8974->i2c->dev, "detected AK8974\n"); break; + case AK8974_WHOAMI_VALUE_HSCDTD008A: + name = "hscdtd008a"; + dev_info(&ak8974->i2c->dev, "detected hscdtd008a\n"); + break; default: dev_err(&ak8974->i2c->dev, "unsupported device (%02x) ", whoami); @@ -534,47 +554,103 @@ static int ak8974_detect(struct ak8974 *ak8974) return 0; } +static int ak8974_measure_channel(struct ak8974 *ak8974, unsigned long address, + int *val) +{ + __le16 hw_values[3]; + int ret; + + pm_runtime_get_sync(&ak8974->i2c->dev); + mutex_lock(&ak8974->lock); + + /* + * We read all axes and discard all but one, for optimized + * reading, use the triggered buffer. + */ + ret = ak8974_trigmeas(ak8974); + if (ret) + goto out_unlock; + ret = ak8974_getresult(ak8974, hw_values); + if (ret) + goto out_unlock; + /* + * This explicit cast to (s16) is necessary as the measurement + * is done in 2's complement with positive and negative values. + * The follwing assignment to *val will then convert the signed + * s16 value to a signed int value. + */ + *val = (s16)le16_to_cpu(hw_values[address]); +out_unlock: + mutex_unlock(&ak8974->lock); + pm_runtime_mark_last_busy(&ak8974->i2c->dev); + pm_runtime_put_autosuspend(&ak8974->i2c->dev); + + return ret; +} + static int ak8974_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) { struct ak8974 *ak8974 = iio_priv(indio_dev); - __le16 hw_values[3]; - int ret = -EINVAL; - - pm_runtime_get_sync(&ak8974->i2c->dev); - mutex_lock(&ak8974->lock); + int ret; switch (mask) { case IIO_CHAN_INFO_RAW: if (chan->address > 2) { dev_err(&ak8974->i2c->dev, "faulty channel address\n"); - ret = -EIO; - goto out_unlock; + return -EIO; } - ret = ak8974_trigmeas(ak8974); + ret = ak8974_measure_channel(ak8974, chan->address, val); if (ret) - goto out_unlock; - ret = ak8974_getresult(ak8974, hw_values); - if (ret) - goto out_unlock; - - /* - * We read all axes and discard all but one, for optimized - * reading, use the triggered buffer. - */ - *val = (s16)le16_to_cpu(hw_values[chan->address]); - - ret = IIO_VAL_INT; + return ret; + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + switch (ak8974->variant) { + case AK8974_WHOAMI_VALUE_AMI306: + case AK8974_WHOAMI_VALUE_AMI305: + /* + * The datasheet for AMI305 and AMI306, page 6 + * specifies the range of the sensor to be + * +/- 12 Gauss. + */ + *val = 12; + /* + * 12 bits are used, +/- 2^11 + * [ -2048 .. 2047 ] (manual page 20) + * [ 0xf800 .. 0x07ff ] + */ + *val2 = 11; + return IIO_VAL_FRACTIONAL_LOG2; + case AK8974_WHOAMI_VALUE_HSCDTD008A: + /* + * The datasheet for HSCDTF008A, page 3 specifies the + * range of the sensor as +/- 2.4 mT per axis, which + * corresponds to +/- 2400 uT = +/- 24 Gauss. + */ + *val = 24; + /* + * 15 bits are used (set up in CTRL4), +/- 2^14 + * [ -16384 .. 16383 ] (manual page 24) + * [ 0xc000 .. 0x3fff ] + */ + *val2 = 14; + return IIO_VAL_FRACTIONAL_LOG2; + default: + /* GUESSING +/- 12 Gauss */ + *val = 12; + /* GUESSING 12 bits ADC +/- 2^11 */ + *val2 = 11; + return IIO_VAL_FRACTIONAL_LOG2; + } + break; + default: + /* Unknown request */ + break; } - out_unlock: - mutex_unlock(&ak8974->lock); - pm_runtime_mark_last_busy(&ak8974->i2c->dev); - pm_runtime_put_autosuspend(&ak8974->i2c->dev); - - return ret; + return -EINVAL; } static void ak8974_fill_buffer(struct iio_dev *indio_dev) @@ -631,27 +707,44 @@ static const struct iio_chan_spec_ext_info ak8974_ext_info[] = { { }, }; -#define AK8974_AXIS_CHANNEL(axis, index) \ +#define AK8974_AXIS_CHANNEL(axis, index, bits) \ { \ .type = IIO_MAGN, \ .modified = 1, \ .channel2 = IIO_MOD_##axis, \ - .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_SCALE), \ .ext_info = ak8974_ext_info, \ .address = index, \ .scan_index = index, \ .scan_type = { \ .sign = 's', \ - .realbits = 16, \ + .realbits = bits, \ .storagebits = 16, \ .endianness = IIO_LE \ }, \ } -static const struct iio_chan_spec ak8974_channels[] = { - AK8974_AXIS_CHANNEL(X, 0), - AK8974_AXIS_CHANNEL(Y, 1), - AK8974_AXIS_CHANNEL(Z, 2), +/* + * We have no datasheet for the AK8974 but we guess that its + * ADC is 12 bits. The AMI305 and AMI306 certainly has 12bit + * ADC. + */ +static const struct iio_chan_spec ak8974_12_bits_channels[] = { + AK8974_AXIS_CHANNEL(X, 0, 12), + AK8974_AXIS_CHANNEL(Y, 1, 12), + AK8974_AXIS_CHANNEL(Z, 2, 12), + IIO_CHAN_SOFT_TIMESTAMP(3), +}; + +/* + * The HSCDTD008A has 15 bits resolution the way we set it up + * in CTRL4. + */ +static const struct iio_chan_spec ak8974_15_bits_channels[] = { + AK8974_AXIS_CHANNEL(X, 0, 15), + AK8974_AXIS_CHANNEL(Y, 1, 15), + AK8974_AXIS_CHANNEL(Z, 2, 15), IIO_CHAN_SOFT_TIMESTAMP(3), }; @@ -674,18 +767,18 @@ static bool ak8974_writeable_reg(struct device *dev, unsigned int reg) case AK8974_INT_CTRL: case AK8974_INT_THRES: case AK8974_INT_THRES + 1: + return true; case AK8974_PRESET: case AK8974_PRESET + 1: - return true; + return ak8974->variant != AK8974_WHOAMI_VALUE_HSCDTD008A; case AK8974_OFFSET_X: case AK8974_OFFSET_X + 1: case AK8974_OFFSET_Y: case AK8974_OFFSET_Y + 1: case AK8974_OFFSET_Z: case AK8974_OFFSET_Z + 1: - if (ak8974->variant == AK8974_WHOAMI_VALUE_AK8974) - return true; - return false; + return ak8974->variant == AK8974_WHOAMI_VALUE_AK8974 || + ak8974->variant == AK8974_WHOAMI_VALUE_HSCDTD008A; case AMI305_OFFSET_X: case AMI305_OFFSET_X + 1: case AMI305_OFFSET_Y: @@ -746,7 +839,12 @@ static int ak8974_probe(struct i2c_client *i2c, ARRAY_SIZE(ak8974->regs), ak8974->regs); if (ret < 0) { - dev_err(&i2c->dev, "cannot get regulators\n"); + if (ret != -EPROBE_DEFER) + dev_err(&i2c->dev, "cannot get regulators: %d\n", ret); + else + dev_dbg(&i2c->dev, + "regulators unavailable, deferring probe\n"); + return ret; } @@ -795,8 +893,21 @@ static int ak8974_probe(struct i2c_client *i2c, pm_runtime_put(&i2c->dev); indio_dev->dev.parent = &i2c->dev; - indio_dev->channels = ak8974_channels; - indio_dev->num_channels = ARRAY_SIZE(ak8974_channels); + switch (ak8974->variant) { + case AK8974_WHOAMI_VALUE_AMI306: + case AK8974_WHOAMI_VALUE_AMI305: + indio_dev->channels = ak8974_12_bits_channels; + indio_dev->num_channels = ARRAY_SIZE(ak8974_12_bits_channels); + break; + case AK8974_WHOAMI_VALUE_HSCDTD008A: + indio_dev->channels = ak8974_15_bits_channels; + indio_dev->num_channels = ARRAY_SIZE(ak8974_15_bits_channels); + break; + default: + indio_dev->channels = ak8974_12_bits_channels; + indio_dev->num_channels = ARRAY_SIZE(ak8974_12_bits_channels); + break; + } indio_dev->info = &ak8974_info; indio_dev->available_scan_masks = ak8974_scan_masks; indio_dev->modes = INDIO_DIRECT_MODE; @@ -926,12 +1037,14 @@ static const struct i2c_device_id ak8974_id[] = { {"ami305", 0 }, {"ami306", 0 }, {"ak8974", 0 }, + {"hscdtd008a", 0 }, {} }; MODULE_DEVICE_TABLE(i2c, ak8974_id); static const struct of_device_id ak8974_of_match[] = { { .compatible = "asahi-kasei,ak8974", }, + { .compatible = "alps,hscdtd008a", }, {} }; MODULE_DEVICE_TABLE(of, ak8974_of_match); diff --git a/drivers/iio/magnetometer/bmc150_magn_spi.c b/drivers/iio/magnetometer/bmc150_magn_spi.c index ed9be0490d77..c6ed3ea8460a 100644 --- a/drivers/iio/magnetometer/bmc150_magn_spi.c +++ b/drivers/iio/magnetometer/bmc150_magn_spi.c @@ -22,8 +22,8 @@ static int bmc150_magn_spi_probe(struct spi_device *spi) regmap = devm_regmap_init_spi(spi, &bmc150_magn_regmap_config); if (IS_ERR(regmap)) { - dev_err(&spi->dev, "Failed to register spi regmap %d\n", - (int)PTR_ERR(regmap)); + dev_err(&spi->dev, "Failed to register spi regmap: %pe\n", + regmap); return PTR_ERR(regmap); } return bmc150_magn_probe(&spi->dev, regmap, spi->irq, id->name); diff --git a/drivers/iio/magnetometer/hid-sensor-magn-3d.c b/drivers/iio/magnetometer/hid-sensor-magn-3d.c index 25e60b233e08..0c09daf87794 100644 --- a/drivers/iio/magnetometer/hid-sensor-magn-3d.c +++ b/drivers/iio/magnetometer/hid-sensor-magn-3d.c @@ -14,8 +14,6 @@ #include #include #include -#include -#include #include "../common/hid-sensors/hid-sensor-trigger.h" enum magn_3d_channel { @@ -519,18 +517,13 @@ static int hid_magn_3d_probe(struct platform_device *pdev) indio_dev->name = name; indio_dev->modes = INDIO_DIRECT_MODE; - ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time, - NULL, NULL); - if (ret) { - dev_err(&pdev->dev, "failed to initialize trigger buffer\n"); - return ret; - } atomic_set(&magn_state->magn_flux_attributes.data_ready, 0); + ret = hid_sensor_setup_trigger(indio_dev, name, &magn_state->magn_flux_attributes); if (ret < 0) { dev_err(&pdev->dev, "trigger setup failed\n"); - goto error_unreg_buffer_funcs; + return ret; } ret = iio_device_register(indio_dev); @@ -554,9 +547,7 @@ static int hid_magn_3d_probe(struct platform_device *pdev) error_iio_unreg: iio_device_unregister(indio_dev); error_remove_trigger: - hid_sensor_remove_trigger(&magn_state->magn_flux_attributes); -error_unreg_buffer_funcs: - iio_triggered_buffer_cleanup(indio_dev); + hid_sensor_remove_trigger(indio_dev, &magn_state->magn_flux_attributes); return ret; } @@ -569,8 +560,7 @@ static int hid_magn_3d_remove(struct platform_device *pdev) sensor_hub_remove_callback(hsdev, HID_USAGE_SENSOR_COMPASS_3D); iio_device_unregister(indio_dev); - hid_sensor_remove_trigger(&magn_state->magn_flux_attributes); - iio_triggered_buffer_cleanup(indio_dev); + hid_sensor_remove_trigger(indio_dev, &magn_state->magn_flux_attributes); return 0; } diff --git a/drivers/iio/magnetometer/mmc35240.c b/drivers/iio/magnetometer/mmc35240.c index 425cdd07b4e5..1787d656d009 100644 --- a/drivers/iio/magnetometer/mmc35240.c +++ b/drivers/iio/magnetometer/mmc35240.c @@ -239,7 +239,7 @@ static int mmc35240_init(struct mmc35240_data *data) return ret; ret = regmap_bulk_read(data->regmap, MMC35240_OTP_START_ADDR, - (u8 *)otp_data, sizeof(otp_data)); + otp_data, sizeof(otp_data)); if (ret < 0) return ret; @@ -295,7 +295,7 @@ static int mmc35240_read_measurement(struct mmc35240_data *data, __le16 buf[3]) if (ret < 0) return ret; - return regmap_bulk_read(data->regmap, MMC35240_REG_XOUT_L, (u8 *)buf, + return regmap_bulk_read(data->regmap, MMC35240_REG_XOUT_L, buf, 3 * sizeof(__le16)); } diff --git a/drivers/iio/magnetometer/rm3100-core.c b/drivers/iio/magnetometer/rm3100-core.c index 7c20918d8108..43a2e420c9c4 100644 --- a/drivers/iio/magnetometer/rm3100-core.c +++ b/drivers/iio/magnetometer/rm3100-core.c @@ -22,6 +22,8 @@ #include #include +#include + #include "rm3100.h" /* Cycle Count Registers. */ @@ -223,8 +225,7 @@ static int rm3100_read_mag(struct rm3100_data *data, int idx, int *val) goto unlock_return; mutex_unlock(&data->lock); - *val = sign_extend32((buffer[0] << 16) | (buffer[1] << 8) | buffer[2], - 23); + *val = sign_extend32(get_unaligned_be24(&buffer[0]), 23); return IIO_VAL_INT; diff --git a/drivers/iio/magnetometer/st_magn_core.c b/drivers/iio/magnetometer/st_magn_core.c index e68184a93a6d..79de721e6015 100644 --- a/drivers/iio/magnetometer/st_magn_core.c +++ b/drivers/iio/magnetometer/st_magn_core.c @@ -506,8 +506,7 @@ int st_magn_common_probe(struct iio_dev *indio_dev) indio_dev->channels = mdata->sensor_settings->ch; indio_dev->num_channels = ST_SENSORS_NUMBER_ALL_CHANNELS; - mdata->current_fullscale = (struct st_sensor_fullscale_avl *) - &mdata->sensor_settings->fs.fs_avl[0]; + mdata->current_fullscale = &mdata->sensor_settings->fs.fs_avl[0]; mdata->odr = mdata->sensor_settings->odr.odr_avl[0].hz; err = st_sensors_init_sensor(indio_dev, NULL); diff --git a/drivers/iio/orientation/hid-sensor-incl-3d.c b/drivers/iio/orientation/hid-sensor-incl-3d.c index 00af68764cda..6aac8bea233a 100644 --- a/drivers/iio/orientation/hid-sensor-incl-3d.c +++ b/drivers/iio/orientation/hid-sensor-incl-3d.c @@ -15,8 +15,6 @@ #include #include #include -#include -#include #include "../common/hid-sensors/hid-sensor-trigger.h" enum incl_3d_channel { @@ -346,18 +344,13 @@ static int hid_incl_3d_probe(struct platform_device *pdev) indio_dev->name = name; indio_dev->modes = INDIO_DIRECT_MODE; - ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time, - NULL, NULL); - if (ret) { - dev_err(&pdev->dev, "failed to initialize trigger buffer\n"); - goto error_free_dev_mem; - } atomic_set(&incl_state->common_attributes.data_ready, 0); + ret = hid_sensor_setup_trigger(indio_dev, name, &incl_state->common_attributes); if (ret) { dev_err(&pdev->dev, "trigger setup failed\n"); - goto error_unreg_buffer_funcs; + goto error_free_dev_mem; } ret = iio_device_register(indio_dev); @@ -382,9 +375,7 @@ static int hid_incl_3d_probe(struct platform_device *pdev) error_iio_unreg: iio_device_unregister(indio_dev); error_remove_trigger: - hid_sensor_remove_trigger(&incl_state->common_attributes); -error_unreg_buffer_funcs: - iio_triggered_buffer_cleanup(indio_dev); + hid_sensor_remove_trigger(indio_dev, &incl_state->common_attributes); error_free_dev_mem: kfree(indio_dev->channels); return ret; @@ -399,8 +390,7 @@ static int hid_incl_3d_remove(struct platform_device *pdev) sensor_hub_remove_callback(hsdev, HID_USAGE_SENSOR_INCLINOMETER_3D); iio_device_unregister(indio_dev); - hid_sensor_remove_trigger(&incl_state->common_attributes); - iio_triggered_buffer_cleanup(indio_dev); + hid_sensor_remove_trigger(indio_dev, &incl_state->common_attributes); kfree(indio_dev->channels); return 0; diff --git a/drivers/iio/orientation/hid-sensor-rotation.c b/drivers/iio/orientation/hid-sensor-rotation.c index 64ae7d04a200..b99f41240e3e 100644 --- a/drivers/iio/orientation/hid-sensor-rotation.c +++ b/drivers/iio/orientation/hid-sensor-rotation.c @@ -14,8 +14,6 @@ #include #include #include -#include -#include #include "../common/hid-sensors/hid-sensor-trigger.h" struct dev_rot_state { @@ -288,18 +286,13 @@ static int hid_dev_rot_probe(struct platform_device *pdev) indio_dev->name = name; indio_dev->modes = INDIO_DIRECT_MODE; - ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time, - NULL, NULL); - if (ret) { - dev_err(&pdev->dev, "failed to initialize trigger buffer\n"); - return ret; - } atomic_set(&rot_state->common_attributes.data_ready, 0); + ret = hid_sensor_setup_trigger(indio_dev, name, &rot_state->common_attributes); if (ret) { dev_err(&pdev->dev, "trigger setup failed\n"); - goto error_unreg_buffer_funcs; + return ret; } ret = iio_device_register(indio_dev); @@ -323,9 +316,7 @@ static int hid_dev_rot_probe(struct platform_device *pdev) error_iio_unreg: iio_device_unregister(indio_dev); error_remove_trigger: - hid_sensor_remove_trigger(&rot_state->common_attributes); -error_unreg_buffer_funcs: - iio_triggered_buffer_cleanup(indio_dev); + hid_sensor_remove_trigger(indio_dev, &rot_state->common_attributes); return ret; } @@ -338,8 +329,7 @@ static int hid_dev_rot_remove(struct platform_device *pdev) sensor_hub_remove_callback(hsdev, hsdev->usage); iio_device_unregister(indio_dev); - hid_sensor_remove_trigger(&rot_state->common_attributes); - iio_triggered_buffer_cleanup(indio_dev); + hid_sensor_remove_trigger(indio_dev, &rot_state->common_attributes); return 0; } diff --git a/drivers/iio/pressure/bmp280-core.c b/drivers/iio/pressure/bmp280-core.c index 29c209cc1108..126a56d31b6e 100644 --- a/drivers/iio/pressure/bmp280-core.c +++ b/drivers/iio/pressure/bmp280-core.c @@ -271,6 +271,8 @@ static u32 bmp280_compensate_humidity(struct bmp280_data *data, + (s32)2097152) * calib->H2 + 8192) >> 14); var -= ((((var >> 15) * (var >> 15)) >> 7) * (s32)calib->H1) >> 4; + var = clamp_val(var, 0, 419430400); + return var >> 12; }; @@ -337,8 +339,7 @@ static int bmp280_read_temp(struct bmp280_data *data, __be32 tmp = 0; s32 adc_temp, comp_temp; - ret = regmap_bulk_read(data->regmap, BMP280_REG_TEMP_MSB, - (u8 *) &tmp, 3); + ret = regmap_bulk_read(data->regmap, BMP280_REG_TEMP_MSB, &tmp, 3); if (ret < 0) { dev_err(data->dev, "failed to read temperature\n"); return ret; @@ -377,8 +378,7 @@ static int bmp280_read_press(struct bmp280_data *data, if (ret < 0) return ret; - ret = regmap_bulk_read(data->regmap, BMP280_REG_PRESS_MSB, - (u8 *) &tmp, 3); + ret = regmap_bulk_read(data->regmap, BMP280_REG_PRESS_MSB, &tmp, 3); if (ret < 0) { dev_err(data->dev, "failed to read pressure\n"); return ret; @@ -400,8 +400,8 @@ static int bmp280_read_press(struct bmp280_data *data, static int bmp280_read_humid(struct bmp280_data *data, int *val, int *val2) { + __be16 tmp; int ret; - __be16 tmp = 0; s32 adc_humidity; u32 comp_humidity; @@ -410,8 +410,7 @@ static int bmp280_read_humid(struct bmp280_data *data, int *val, int *val2) if (ret < 0) return ret; - ret = regmap_bulk_read(data->regmap, BMP280_REG_HUMIDITY_MSB, - (u8 *) &tmp, 2); + ret = regmap_bulk_read(data->regmap, BMP280_REG_HUMIDITY_MSB, &tmp, 2); if (ret < 0) { dev_err(data->dev, "failed to read humidity\n"); return ret; @@ -575,57 +574,38 @@ static int bmp280_write_raw(struct iio_dev *indio_dev, return ret; } -static ssize_t bmp280_show_avail(char *buf, const int *vals, const int n) +static int bmp280_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, int *type, int *length, + long mask) { - size_t len = 0; - int i; + struct bmp280_data *data = iio_priv(indio_dev); - for (i = 0; i < n; i++) - len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", vals[i]); - - buf[len - 1] = '\n'; - - return len; + switch (mask) { + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + switch (chan->type) { + case IIO_PRESSURE: + *vals = data->chip_info->oversampling_press_avail; + *length = data->chip_info->num_oversampling_press_avail; + break; + case IIO_TEMP: + *vals = data->chip_info->oversampling_temp_avail; + *length = data->chip_info->num_oversampling_temp_avail; + break; + default: + return -EINVAL; + } + *type = IIO_VAL_INT; + return IIO_AVAIL_LIST; + default: + return -EINVAL; + } } -static ssize_t bmp280_show_temp_oversampling_avail(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct bmp280_data *data = iio_priv(dev_to_iio_dev(dev)); - - return bmp280_show_avail(buf, data->chip_info->oversampling_temp_avail, - data->chip_info->num_oversampling_temp_avail); -} - -static ssize_t bmp280_show_press_oversampling_avail(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct bmp280_data *data = iio_priv(dev_to_iio_dev(dev)); - - return bmp280_show_avail(buf, data->chip_info->oversampling_press_avail, - data->chip_info->num_oversampling_press_avail); -} - -static IIO_DEVICE_ATTR(in_temp_oversampling_ratio_available, - S_IRUGO, bmp280_show_temp_oversampling_avail, NULL, 0); - -static IIO_DEVICE_ATTR(in_pressure_oversampling_ratio_available, - S_IRUGO, bmp280_show_press_oversampling_avail, NULL, 0); - -static struct attribute *bmp280_attributes[] = { - &iio_dev_attr_in_temp_oversampling_ratio_available.dev_attr.attr, - &iio_dev_attr_in_pressure_oversampling_ratio_available.dev_attr.attr, - NULL, -}; - -static const struct attribute_group bmp280_attrs_group = { - .attrs = bmp280_attributes, -}; - static const struct iio_info bmp280_info = { .read_raw = &bmp280_read_raw, + .read_avail = &bmp280_read_avail, .write_raw = &bmp280_write_raw, - .attrs = &bmp280_attrs_group, }; static int bmp280_chip_config(struct bmp280_data *data) @@ -713,7 +693,7 @@ static int bmp180_measure(struct bmp280_data *data, u8 ctrl_meas) unsigned int ctrl; if (data->use_eoc) - init_completion(&data->done); + reinit_completion(&data->done); ret = regmap_write(data->regmap, BMP280_REG_CTRL_MEAS, ctrl_meas); if (ret) @@ -752,14 +732,14 @@ static int bmp180_measure(struct bmp280_data *data, u8 ctrl_meas) static int bmp180_read_adc_temp(struct bmp280_data *data, int *val) { + __be16 tmp; int ret; - __be16 tmp = 0; ret = bmp180_measure(data, BMP180_MEAS_TEMP); if (ret) return ret; - ret = regmap_bulk_read(data->regmap, BMP180_REG_OUT_MSB, (u8 *)&tmp, 2); + ret = regmap_bulk_read(data->regmap, BMP180_REG_OUT_MSB, &tmp, 2); if (ret) return ret; @@ -856,7 +836,7 @@ static int bmp180_read_adc_press(struct bmp280_data *data, int *val) if (ret) return ret; - ret = regmap_bulk_read(data->regmap, BMP180_REG_OUT_MSB, (u8 *)&tmp, 3); + ret = regmap_bulk_read(data->regmap, BMP180_REG_OUT_MSB, &tmp, 3); if (ret) return ret; @@ -965,10 +945,12 @@ static int bmp085_fetch_eoc_irq(struct device *dev, irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq)); if (irq_trig != IRQF_TRIGGER_RISING) { - dev_err(dev, "non-rising trigger given for EOC interrupt, " - "trying to enforce it\n"); + dev_err(dev, "non-rising trigger given for EOC interrupt, trying to enforce it\n"); irq_trig = IRQF_TRIGGER_RISING; } + + init_completion(&data->done); + ret = devm_request_threaded_irq(dev, irq, bmp085_eoc_irq, @@ -1082,9 +1064,9 @@ int bmp280_common_probe(struct device *dev, usleep_range(data->start_up_time, data->start_up_time + 100); /* Bring chip out of reset if there is an assigned GPIO line */ - gpiod = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); + gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); /* Deassert the signal */ - if (!IS_ERR(gpiod)) { + if (gpiod) { dev_info(dev, "release reset\n"); gpiod_set_value(gpiod, 0); } diff --git a/drivers/iio/pressure/hid-sensor-press.c b/drivers/iio/pressure/hid-sensor-press.c index 953235052155..5e6663f757ae 100644 --- a/drivers/iio/pressure/hid-sensor-press.c +++ b/drivers/iio/pressure/hid-sensor-press.c @@ -14,8 +14,6 @@ #include #include #include -#include -#include #include "../common/hid-sensors/hid-sensor-trigger.h" #define CHANNEL_SCAN_INDEX_PRESSURE 0 @@ -290,18 +288,13 @@ static int hid_press_probe(struct platform_device *pdev) indio_dev->name = name; indio_dev->modes = INDIO_DIRECT_MODE; - ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time, - NULL, NULL); - if (ret) { - dev_err(&pdev->dev, "failed to initialize trigger buffer\n"); - goto error_free_dev_mem; - } atomic_set(&press_state->common_attributes.data_ready, 0); + ret = hid_sensor_setup_trigger(indio_dev, name, &press_state->common_attributes); if (ret) { dev_err(&pdev->dev, "trigger setup failed\n"); - goto error_unreg_buffer_funcs; + goto error_free_dev_mem; } ret = iio_device_register(indio_dev); @@ -325,9 +318,7 @@ static int hid_press_probe(struct platform_device *pdev) error_iio_unreg: iio_device_unregister(indio_dev); error_remove_trigger: - hid_sensor_remove_trigger(&press_state->common_attributes); -error_unreg_buffer_funcs: - iio_triggered_buffer_cleanup(indio_dev); + hid_sensor_remove_trigger(indio_dev, &press_state->common_attributes); error_free_dev_mem: kfree(indio_dev->channels); return ret; @@ -342,8 +333,7 @@ static int hid_press_remove(struct platform_device *pdev) sensor_hub_remove_callback(hsdev, HID_USAGE_SENSOR_PRESSURE); iio_device_unregister(indio_dev); - hid_sensor_remove_trigger(&press_state->common_attributes); - iio_triggered_buffer_cleanup(indio_dev); + hid_sensor_remove_trigger(indio_dev, &press_state->common_attributes); kfree(indio_dev->channels); return 0; diff --git a/drivers/iio/pressure/hp206c.c b/drivers/iio/pressure/hp206c.c index 3ac3632e7242..1f931f5b7a65 100644 --- a/drivers/iio/pressure/hp206c.c +++ b/drivers/iio/pressure/hp206c.c @@ -18,6 +18,8 @@ #include #include +#include + /* I2C commands: */ #define HP206C_CMD_SOFT_RST 0x06 @@ -93,12 +95,12 @@ static int hp206c_read_20bit(struct i2c_client *client, u8 cmd) int ret; u8 values[3]; - ret = i2c_smbus_read_i2c_block_data(client, cmd, 3, values); + ret = i2c_smbus_read_i2c_block_data(client, cmd, sizeof(values), values); if (ret < 0) return ret; - if (ret != 3) + if (ret != sizeof(values)) return -EIO; - return ((values[0] & 0xF) << 16) | (values[1] << 8) | (values[2]); + return get_unaligned_be24(&values[0]) & GENMASK(19, 0); } /* Spin for max 160ms until DEV_RDY is 1, or return error. */ diff --git a/drivers/iio/pressure/ms5611_i2c.c b/drivers/iio/pressure/ms5611_i2c.c index 8089c59adce5..072c106dd66d 100644 --- a/drivers/iio/pressure/ms5611_i2c.c +++ b/drivers/iio/pressure/ms5611_i2c.c @@ -16,6 +16,8 @@ #include #include +#include + #include "ms5611.h" static int ms5611_i2c_reset(struct device *dev) @@ -50,7 +52,7 @@ static int ms5611_i2c_read_adc(struct ms5611_state *st, s32 *val) if (ret < 0) return ret; - *val = (buf[0] << 16) | (buf[1] << 8) | buf[2]; + *val = get_unaligned_be24(&buf[0]); return 0; } diff --git a/drivers/iio/pressure/ms5611_spi.c b/drivers/iio/pressure/ms5611_spi.c index b463eaa799ab..4799aa57135e 100644 --- a/drivers/iio/pressure/ms5611_spi.c +++ b/drivers/iio/pressure/ms5611_spi.c @@ -11,6 +11,8 @@ #include #include +#include + #include "ms5611.h" static int ms5611_spi_reset(struct device *dev) @@ -45,7 +47,7 @@ static int ms5611_spi_read_adc(struct device *dev, s32 *val) if (ret < 0) return ret; - *val = (buf[0] << 16) | (buf[1] << 8) | buf[2]; + *val = get_unaligned_be24(&buf[0]); return 0; } diff --git a/drivers/iio/pressure/st_pressure_core.c b/drivers/iio/pressure/st_pressure_core.c index bd972cec4830..789a2928504a 100644 --- a/drivers/iio/pressure/st_pressure_core.c +++ b/drivers/iio/pressure/st_pressure_core.c @@ -683,8 +683,7 @@ EXPORT_SYMBOL(st_press_get_settings); int st_press_common_probe(struct iio_dev *indio_dev) { struct st_sensor_data *press_data = iio_priv(indio_dev); - struct st_sensors_platform_data *pdata = - (struct st_sensors_platform_data *)press_data->dev->platform_data; + struct st_sensors_platform_data *pdata = dev_get_platdata(press_data->dev); int err; indio_dev->modes = INDIO_DIRECT_MODE; @@ -708,9 +707,7 @@ int st_press_common_probe(struct iio_dev *indio_dev) indio_dev->channels = press_data->sensor_settings->ch; indio_dev->num_channels = press_data->sensor_settings->num_ch; - press_data->current_fullscale = - (struct st_sensor_fullscale_avl *) - &press_data->sensor_settings->fs.fs_avl[0]; + press_data->current_fullscale = &press_data->sensor_settings->fs.fs_avl[0]; press_data->odr = press_data->sensor_settings->odr.odr_avl[0].hz; diff --git a/drivers/iio/pressure/zpa2326.c b/drivers/iio/pressure/zpa2326.c index 99dfe33ee402..37fe851f89af 100644 --- a/drivers/iio/pressure/zpa2326.c +++ b/drivers/iio/pressure/zpa2326.c @@ -64,6 +64,7 @@ #include #include #include +#include #include "zpa2326.h" /* 200 ms should be enough for the longest conversion time in one-shot mode. */ @@ -1005,22 +1006,20 @@ static int zpa2326_fetch_raw_sample(const struct iio_dev *indio_dev, struct regmap *regs = ((struct zpa2326_private *) iio_priv(indio_dev))->regmap; int err; + u8 v[3]; switch (type) { case IIO_PRESSURE: zpa2326_dbg(indio_dev, "fetching raw pressure sample"); - err = regmap_bulk_read(regs, ZPA2326_PRESS_OUT_XL_REG, value, - 3); + err = regmap_bulk_read(regs, ZPA2326_PRESS_OUT_XL_REG, v, sizeof(v)); if (err) { zpa2326_warn(indio_dev, "failed to fetch pressure (%d)", err); return err; } - /* Pressure is a 24 bits wide little-endian unsigned int. */ - *value = (((u8 *)value)[2] << 16) | (((u8 *)value)[1] << 8) | - ((u8 *)value)[0]; + *value = get_unaligned_le24(&v[0]); return IIO_VAL_INT; diff --git a/drivers/iio/proximity/Kconfig b/drivers/iio/proximity/Kconfig index 37606d400805..12672a0e89ed 100644 --- a/drivers/iio/proximity/Kconfig +++ b/drivers/iio/proximity/Kconfig @@ -101,6 +101,19 @@ config SRF04 To compile this driver as a module, choose M here: the module will be called srf04. +config SX9310 + tristate "SX9310/SX9311 Semtech proximity sensor" + select IIO_BUFFER + select IIO_TRIGGERED_BUFFER + select REGMAP_I2C + depends on I2C + help + Say Y here to build a driver for Semtech's SX9310/SX9311 capacitive + proximity/button sensor. + + To compile this driver as a module, choose M here: the + module will be called sx9310. + config SX9500 tristate "SX9500 Semtech proximity sensor" select IIO_BUFFER @@ -127,6 +140,17 @@ config SRF08 To compile this driver as a module, choose M here: the module will be called srf08. +config VCNL3020 + tristate "VCNL3020 proximity sensor" + select REGMAP_I2C + depends on I2C + help + Say Y here if you want to build a driver for the Vishay VCNL3020 + proximity sensor. + + To compile this driver as a module, choose M here: the + module will be called vcnl3020. + config VL53L0X_I2C tristate "STMicroelectronics VL53L0X ToF ranger sensor (I2C)" depends on I2C diff --git a/drivers/iio/proximity/Makefile b/drivers/iio/proximity/Makefile index c591b019304e..9c1aca1a8b79 100644 --- a/drivers/iio/proximity/Makefile +++ b/drivers/iio/proximity/Makefile @@ -12,6 +12,8 @@ obj-$(CONFIG_PING) += ping.o obj-$(CONFIG_RFD77402) += rfd77402.o obj-$(CONFIG_SRF04) += srf04.o obj-$(CONFIG_SRF08) += srf08.o +obj-$(CONFIG_SX9310) += sx9310.o obj-$(CONFIG_SX9500) += sx9500.o +obj-$(CONFIG_VCNL3020) += vcnl3020.o obj-$(CONFIG_VL53L0X_I2C) += vl53l0x-i2c.o diff --git a/drivers/iio/proximity/ping.c b/drivers/iio/proximity/ping.c index 12b893c5b0ee..2e99eeb27f2e 100644 --- a/drivers/iio/proximity/ping.c +++ b/drivers/iio/proximity/ping.c @@ -89,14 +89,14 @@ static irqreturn_t ping_handle_irq(int irq, void *dev_id) return IRQ_HANDLED; } -static int ping_read(struct ping_data *data) +static int ping_read(struct iio_dev *indio_dev) { + struct ping_data *data = iio_priv(indio_dev); int ret; ktime_t ktime_dt; s64 dt_ns; u32 time_ns, distance_mm; struct platform_device *pdev = to_platform_device(data->dev); - struct iio_dev *indio_dev = iio_priv_to_dev(data); /* * just one read-echo-cycle can take place at a time @@ -228,7 +228,6 @@ static int ping_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *channel, int *val, int *val2, long info) { - struct ping_data *data = iio_priv(indio_dev); int ret; if (channel->type != IIO_DISTANCE) @@ -236,7 +235,7 @@ static int ping_read_raw(struct iio_dev *indio_dev, switch (info) { case IIO_CHAN_INFO_RAW: - ret = ping_read(data); + ret = ping_read(indio_dev); if (ret < 0) return ret; *val = ret; diff --git a/drivers/iio/proximity/sx9310.c b/drivers/iio/proximity/sx9310.c new file mode 100644 index 000000000000..d161f3061e35 --- /dev/null +++ b/drivers/iio/proximity/sx9310.c @@ -0,0 +1,1069 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2018 Google LLC. + * + * Driver for Semtech's SX9310/SX9311 capacitive proximity/button solution. + * Based on SX9500 driver and Semtech driver using the input framework + * . + * Reworked April 2019 by Evan Green + * and January 2020 by Daniel Campello + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +/* Register definitions. */ +#define SX9310_REG_IRQ_SRC 0x00 +#define SX9310_REG_STAT0 0x01 +#define SX9310_REG_STAT1 0x02 +#define SX9310_REG_IRQ_MSK 0x03 +#define SX9310_CONVDONE_IRQ BIT(3) +#define SX9310_FAR_IRQ BIT(5) +#define SX9310_CLOSE_IRQ BIT(6) +#define SX9310_EVENT_IRQ (SX9310_FAR_IRQ | \ + SX9310_CLOSE_IRQ) +#define SX9310_REG_IRQ_FUNC 0x04 + +#define SX9310_REG_PROX_CTRL0 0x10 +#define SX9310_REG_PROX_CTRL0_PROXSTAT2 0x10 +#define SX9310_REG_PROX_CTRL0_EN_MASK 0x0F +#define SX9310_REG_PROX_CTRL1 0x11 +#define SX9310_REG_PROX_CTRL2 0x12 +#define SX9310_REG_PROX_CTRL2_COMBMODE_ALL 0x80 +#define SX9310_REG_PROX_CTRL2_SHIELDEN_DYNAMIC 0x04 +#define SX9310_REG_PROX_CTRL3 0x13 +#define SX9310_REG_PROX_CTRL3_GAIN0_X8 0x0c +#define SX9310_REG_PROX_CTRL3_GAIN12_X4 0x02 +#define SX9310_REG_PROX_CTRL4 0x14 +#define SX9310_REG_PROX_CTRL4_RESOLUTION_FINEST 0x07 +#define SX9310_REG_PROX_CTRL5 0x15 +#define SX9310_REG_PROX_CTRL5_RANGE_SMALL 0xc0 +#define SX9310_REG_PROX_CTRL5_STARTUPSENS_CS1 0x04 +#define SX9310_REG_PROX_CTRL5_RAWFILT_1P25 0x02 +#define SX9310_REG_PROX_CTRL6 0x16 +#define SX9310_REG_PROX_CTRL6_COMP_COMMON 0x20 +#define SX9310_REG_PROX_CTRL7 0x17 +#define SX9310_REG_PROX_CTRL7_AVGNEGFILT_2 0x08 +#define SX9310_REG_PROX_CTRL7_AVGPOSFILT_512 0x05 +#define SX9310_REG_PROX_CTRL8 0x18 +#define SX9310_REG_PROX_CTRL9 0x19 +#define SX9310_REG_PROX_CTRL8_9_PTHRESH12_28 0x40 +#define SX9310_REG_PROX_CTRL8_9_PTHRESH_96 0x88 +#define SX9310_REG_PROX_CTRL8_9_BODYTHRESH_900 0x03 +#define SX9310_REG_PROX_CTRL8_9_BODYTHRESH_1500 0x05 +#define SX9310_REG_PROX_CTRL10 0x1a +#define SX9310_REG_PROX_CTRL10_HYST_6PCT 0x10 +#define SX9310_REG_PROX_CTRL10_CLOSE_DEBOUNCE_8 0x12 +#define SX9310_REG_PROX_CTRL10_FAR_DEBOUNCE_8 0x03 +#define SX9310_REG_PROX_CTRL11 0x1b +#define SX9310_REG_PROX_CTRL12 0x1c +#define SX9310_REG_PROX_CTRL13 0x1d +#define SX9310_REG_PROX_CTRL14 0x1e +#define SX9310_REG_PROX_CTRL15 0x1f +#define SX9310_REG_PROX_CTRL16 0x20 +#define SX9310_REG_PROX_CTRL17 0x21 +#define SX9310_REG_PROX_CTRL18 0x22 +#define SX9310_REG_PROX_CTRL19 0x23 +#define SX9310_REG_SAR_CTRL0 0x2a +#define SX9310_REG_SAR_CTRL0_SARDEB_4_SAMPLES 0x40 +#define SX9310_REG_SAR_CTRL0_SARHYST_8 0x10 +#define SX9310_REG_SAR_CTRL1 0x2b +/* Each increment of the slope register is 0.0078125. */ +#define SX9310_REG_SAR_CTRL1_SLOPE(_hnslope) (_hnslope / 78125) +#define SX9310_REG_SAR_CTRL2 0x2c +#define SX9310_REG_SAR_CTRL2_SAROFFSET_DEFAULT 0x3c + +#define SX9310_REG_SENSOR_SEL 0x30 + +#define SX9310_REG_USE_MSB 0x31 +#define SX9310_REG_USE_LSB 0x32 + +#define SX9310_REG_AVG_MSB 0x33 +#define SX9310_REG_AVG_LSB 0x34 + +#define SX9310_REG_DIFF_MSB 0x35 +#define SX9310_REG_DIFF_LSB 0x36 + +#define SX9310_REG_OFFSET_MSB 0x37 +#define SX9310_REG_OFFSET_LSB 0x38 + +#define SX9310_REG_SAR_MSB 0x39 +#define SX9310_REG_SAR_LSB 0x3a + +#define SX9310_REG_I2CADDR 0x40 +#define SX9310_REG_PAUSE 0x41 +#define SX9310_REG_WHOAMI 0x42 +#define SX9310_WHOAMI_VALUE 0x01 +#define SX9311_WHOAMI_VALUE 0x02 + +#define SX9310_REG_RESET 0x7f +#define SX9310_SOFT_RESET 0xde + +#define SX9310_SCAN_PERIOD_MASK GENMASK(7, 4) +#define SX9310_SCAN_PERIOD_SHIFT 4 + +#define SX9310_COMPSTAT_MASK GENMASK(3, 0) + +/* 4 hardware channels, as defined in STAT0: COMB, CS2, CS1 and CS0. */ +#define SX9310_NUM_CHANNELS 4 +#define SX9310_CHAN_ENABLED_MASK GENMASK(3, 0) + +struct sx9310_data { + /* Serialize access to registers and channel configuration */ + struct mutex mutex; + struct i2c_client *client; + struct iio_trigger *trig; + struct regmap *regmap; + /* + * Last reading of the proximity status for each channel. + * We only send an event to user space when this changes. + */ + bool prox_stat[SX9310_NUM_CHANNELS]; + bool trigger_enabled; + __be16 buffer[SX9310_NUM_CHANNELS + + 4]; /* 64-bit data + 64-bit timestamp */ + /* Remember enabled channels and sample rate during suspend. */ + unsigned int suspend_ctrl0; + struct completion completion; + unsigned int chan_read, chan_event; + int channel_users[SX9310_NUM_CHANNELS]; + int whoami; +}; + +static const struct iio_event_spec sx9310_events[] = { + { + .type = IIO_EV_TYPE_THRESH, + .dir = IIO_EV_DIR_EITHER, + .mask_separate = BIT(IIO_EV_INFO_ENABLE), + }, +}; + +#define SX9310_NAMED_CHANNEL(idx, name) \ + { \ + .type = IIO_PROXIMITY, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .indexed = 1, \ + .channel = idx, \ + .extend_name = name, \ + .address = SX9310_REG_DIFF_MSB, \ + .event_spec = sx9310_events, \ + .num_event_specs = ARRAY_SIZE(sx9310_events), \ + .scan_index = idx, \ + .scan_type = { \ + .sign = 's', \ + .realbits = 12, \ + .storagebits = 16, \ + .endianness = IIO_BE, \ + }, \ + } +#define SX9310_CHANNEL(idx) SX9310_NAMED_CHANNEL(idx, NULL) + +static const struct iio_chan_spec sx9310_channels[] = { + SX9310_CHANNEL(0), /* CS0 */ + SX9310_CHANNEL(1), /* CS1 */ + SX9310_CHANNEL(2), /* CS2 */ + SX9310_NAMED_CHANNEL(3, "comb"), /* COMB */ + + IIO_CHAN_SOFT_TIMESTAMP(4), +}; + +/* + * Each entry contains the integer part (val) and the fractional part, in micro + * seconds. It conforms to the IIO output IIO_VAL_INT_PLUS_MICRO. + */ +static const struct { + int val; + int val2; +} sx9310_samp_freq_table[] = { + { 500, 0 }, /* 0000: Min (no idle time) */ + { 66, 666666 }, /* 0001: 15 ms */ + { 33, 333333 }, /* 0010: 30 ms (Typ.) */ + { 22, 222222 }, /* 0011: 45 ms */ + { 16, 666666 }, /* 0100: 60 ms */ + { 11, 111111 }, /* 0101: 90 ms */ + { 8, 333333 }, /* 0110: 120 ms */ + { 5, 0 }, /* 0111: 200 ms */ + { 2, 500000 }, /* 1000: 400 ms */ + { 1, 666666 }, /* 1001: 600 ms */ + { 1, 250000 }, /* 1010: 800 ms */ + { 1, 0 }, /* 1011: 1 s */ + { 0, 500000 }, /* 1100: 2 s */ + { 0, 333333 }, /* 1101: 3 s */ + { 0, 250000 }, /* 1110: 4 s */ + { 0, 200000 }, /* 1111: 5 s */ +}; +static const unsigned int sx9310_scan_period_table[] = { + 2, 15, 30, 45, 60, 90, 120, 200, + 400, 600, 800, 1000, 2000, 3000, 4000, 5000, +}; + +static ssize_t sx9310_show_samp_freq_avail(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + size_t len = 0; + int i; + + for (i = 0; i < ARRAY_SIZE(sx9310_samp_freq_table); i++) + len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%d ", + sx9310_samp_freq_table[i].val, + sx9310_samp_freq_table[i].val2); + buf[len - 1] = '\n'; + return len; +} +static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(sx9310_show_samp_freq_avail); + +static const struct regmap_range sx9310_writable_reg_ranges[] = { + regmap_reg_range(SX9310_REG_IRQ_MSK, SX9310_REG_IRQ_FUNC), + regmap_reg_range(SX9310_REG_PROX_CTRL0, SX9310_REG_PROX_CTRL19), + regmap_reg_range(SX9310_REG_SAR_CTRL0, SX9310_REG_SAR_CTRL2), + regmap_reg_range(SX9310_REG_SENSOR_SEL, SX9310_REG_SENSOR_SEL), + regmap_reg_range(SX9310_REG_OFFSET_MSB, SX9310_REG_OFFSET_LSB), + regmap_reg_range(SX9310_REG_PAUSE, SX9310_REG_PAUSE), + regmap_reg_range(SX9310_REG_RESET, SX9310_REG_RESET), +}; + +static const struct regmap_access_table sx9310_writeable_regs = { + .yes_ranges = sx9310_writable_reg_ranges, + .n_yes_ranges = ARRAY_SIZE(sx9310_writable_reg_ranges), +}; + +static const struct regmap_range sx9310_readable_reg_ranges[] = { + regmap_reg_range(SX9310_REG_IRQ_SRC, SX9310_REG_IRQ_FUNC), + regmap_reg_range(SX9310_REG_PROX_CTRL0, SX9310_REG_PROX_CTRL19), + regmap_reg_range(SX9310_REG_SAR_CTRL0, SX9310_REG_SAR_CTRL2), + regmap_reg_range(SX9310_REG_SENSOR_SEL, SX9310_REG_SAR_LSB), + regmap_reg_range(SX9310_REG_I2CADDR, SX9310_REG_WHOAMI), + regmap_reg_range(SX9310_REG_RESET, SX9310_REG_RESET), +}; + +static const struct regmap_access_table sx9310_readable_regs = { + .yes_ranges = sx9310_readable_reg_ranges, + .n_yes_ranges = ARRAY_SIZE(sx9310_readable_reg_ranges), +}; + +static const struct regmap_range sx9310_volatile_reg_ranges[] = { + regmap_reg_range(SX9310_REG_IRQ_SRC, SX9310_REG_STAT1), + regmap_reg_range(SX9310_REG_USE_MSB, SX9310_REG_DIFF_LSB), + regmap_reg_range(SX9310_REG_SAR_MSB, SX9310_REG_SAR_LSB), + regmap_reg_range(SX9310_REG_RESET, SX9310_REG_RESET), +}; + +static const struct regmap_access_table sx9310_volatile_regs = { + .yes_ranges = sx9310_volatile_reg_ranges, + .n_yes_ranges = ARRAY_SIZE(sx9310_volatile_reg_ranges), +}; + +static const struct regmap_config sx9310_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + + .max_register = SX9310_REG_RESET, + .cache_type = REGCACHE_RBTREE, + + .wr_table = &sx9310_writeable_regs, + .rd_table = &sx9310_readable_regs, + .volatile_table = &sx9310_volatile_regs, +}; + +static int sx9310_update_chan_en(struct sx9310_data *data, + unsigned int chan_read, + unsigned int chan_event) +{ + int ret; + + if ((data->chan_read | data->chan_event) != (chan_read | chan_event)) { + ret = regmap_update_bits(data->regmap, SX9310_REG_PROX_CTRL0, + SX9310_CHAN_ENABLED_MASK, + chan_read | chan_event); + if (ret) + return ret; + } + data->chan_read = chan_read; + data->chan_event = chan_event; + return 0; +} + +static int sx9310_get_read_channel(struct sx9310_data *data, int channel) +{ + return sx9310_update_chan_en(data, data->chan_read | BIT(channel), + data->chan_event); +} + +static int sx9310_put_read_channel(struct sx9310_data *data, int channel) +{ + return sx9310_update_chan_en(data, data->chan_read & ~BIT(channel), + data->chan_event); +} + +static int sx9310_get_event_channel(struct sx9310_data *data, int channel) +{ + return sx9310_update_chan_en(data, data->chan_read, + data->chan_event | BIT(channel)); +} + +static int sx9310_put_event_channel(struct sx9310_data *data, int channel) +{ + return sx9310_update_chan_en(data, data->chan_read, + data->chan_event & ~BIT(channel)); +} + +static int sx9310_enable_irq(struct sx9310_data *data, unsigned int irq) +{ + return regmap_update_bits(data->regmap, SX9310_REG_IRQ_MSK, irq, irq); +} + +static int sx9310_disable_irq(struct sx9310_data *data, unsigned int irq) +{ + return regmap_update_bits(data->regmap, SX9310_REG_IRQ_MSK, irq, 0); +} + +static int sx9310_read_prox_data(struct sx9310_data *data, + const struct iio_chan_spec *chan, __be16 *val) +{ + int ret; + + ret = regmap_write(data->regmap, SX9310_REG_SENSOR_SEL, chan->channel); + if (ret < 0) + return ret; + + return regmap_bulk_read(data->regmap, chan->address, val, 2); +} + +/* + * If we have no interrupt support, we have to wait for a scan period + * after enabling a channel to get a result. + */ +static int sx9310_wait_for_sample(struct sx9310_data *data) +{ + int ret; + unsigned int val; + + ret = regmap_read(data->regmap, SX9310_REG_PROX_CTRL0, &val); + if (ret < 0) + return ret; + + val = (val & SX9310_SCAN_PERIOD_MASK) >> SX9310_SCAN_PERIOD_SHIFT; + + msleep(sx9310_scan_period_table[val]); + + return 0; +} + +static int sx9310_read_proximity(struct sx9310_data *data, + const struct iio_chan_spec *chan, int *val) +{ + int ret = 0; + __be16 rawval; + + mutex_lock(&data->mutex); + + ret = sx9310_get_read_channel(data, chan->channel); + if (ret < 0) + goto out; + + ret = sx9310_enable_irq(data, SX9310_CONVDONE_IRQ); + if (ret < 0) + goto out_put_channel; + + mutex_unlock(&data->mutex); + + if (data->client->irq > 0) { + ret = wait_for_completion_interruptible(&data->completion); + reinit_completion(&data->completion); + } else { + ret = sx9310_wait_for_sample(data); + } + + mutex_lock(&data->mutex); + + if (ret < 0) + goto out_disable_irq; + + ret = sx9310_read_prox_data(data, chan, &rawval); + if (ret < 0) + goto out_disable_irq; + + *val = sign_extend32(be16_to_cpu(rawval), + (chan->address == SX9310_REG_DIFF_MSB ? 11 : 15)); + + ret = sx9310_disable_irq(data, SX9310_CONVDONE_IRQ); + if (ret < 0) + goto out_put_channel; + + ret = sx9310_put_read_channel(data, chan->channel); + if (ret < 0) + goto out; + + mutex_unlock(&data->mutex); + + return IIO_VAL_INT; + +out_disable_irq: + sx9310_disable_irq(data, SX9310_CONVDONE_IRQ); +out_put_channel: + sx9310_put_read_channel(data, chan->channel); +out: + mutex_unlock(&data->mutex); + + return ret; +} + +static int sx9310_read_samp_freq(struct sx9310_data *data, int *val, int *val2) +{ + unsigned int regval; + int ret = regmap_read(data->regmap, SX9310_REG_PROX_CTRL0, ®val); + + if (ret < 0) + return ret; + + regval = (regval & SX9310_SCAN_PERIOD_MASK) >> SX9310_SCAN_PERIOD_SHIFT; + *val = sx9310_samp_freq_table[regval].val; + *val2 = sx9310_samp_freq_table[regval].val2; + + return IIO_VAL_INT_PLUS_MICRO; +} + +static int sx9310_read_raw(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, int *val, + int *val2, long mask) +{ + struct sx9310_data *data = iio_priv(indio_dev); + int ret; + + if (chan->type != IIO_PROXIMITY) + return -EINVAL; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + ret = iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; + + ret = sx9310_read_proximity(data, chan, val); + iio_device_release_direct_mode(indio_dev); + return ret; + case IIO_CHAN_INFO_SAMP_FREQ: + return sx9310_read_samp_freq(data, val, val2); + default: + return -EINVAL; + } +} + +static int sx9310_set_samp_freq(struct sx9310_data *data, int val, int val2) +{ + int i, ret; + + for (i = 0; i < ARRAY_SIZE(sx9310_samp_freq_table); i++) + if (val == sx9310_samp_freq_table[i].val && + val2 == sx9310_samp_freq_table[i].val2) + break; + + if (i == ARRAY_SIZE(sx9310_samp_freq_table)) + return -EINVAL; + + mutex_lock(&data->mutex); + + ret = regmap_update_bits(data->regmap, SX9310_REG_PROX_CTRL0, + SX9310_SCAN_PERIOD_MASK, + i << SX9310_SCAN_PERIOD_SHIFT); + + mutex_unlock(&data->mutex); + + return ret; +} + +static int sx9310_write_raw(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, int val, int val2, + long mask) +{ + struct sx9310_data *data = iio_priv(indio_dev); + + if (chan->type != IIO_PROXIMITY) + return -EINVAL; + + if (mask != IIO_CHAN_INFO_SAMP_FREQ) + return -EINVAL; + + return sx9310_set_samp_freq(data, val, val2); +} + +static irqreturn_t sx9310_irq_handler(int irq, void *private) +{ + struct iio_dev *indio_dev = private; + struct sx9310_data *data = iio_priv(indio_dev); + + if (data->trigger_enabled) + iio_trigger_poll(data->trig); + + /* + * Even if no event is enabled, we need to wake the thread to + * clear the interrupt state by reading SX9310_REG_IRQ_SRC. It + * is not possible to do that here because regmap_read takes a + * mutex. + */ + return IRQ_WAKE_THREAD; +} + +static void sx9310_push_events(struct iio_dev *indio_dev) +{ + int ret; + unsigned int val, chan; + struct sx9310_data *data = iio_priv(indio_dev); + s64 timestamp = iio_get_time_ns(indio_dev); + + /* Read proximity state on all channels */ + ret = regmap_read(data->regmap, SX9310_REG_STAT0, &val); + if (ret < 0) { + dev_err(&data->client->dev, "i2c transfer error in irq\n"); + return; + } + + for (chan = 0; chan < SX9310_NUM_CHANNELS; chan++) { + int dir; + u64 ev; + bool new_prox = val & BIT(chan); + + if (!(data->chan_event & BIT(chan))) + continue; + if (new_prox == data->prox_stat[chan]) + /* No change on this channel. */ + continue; + + dir = new_prox ? IIO_EV_DIR_FALLING : IIO_EV_DIR_RISING; + ev = IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, chan, + IIO_EV_TYPE_THRESH, dir); + + iio_push_event(indio_dev, ev, timestamp); + data->prox_stat[chan] = new_prox; + } +} + +static irqreturn_t sx9310_irq_thread_handler(int irq, void *private) +{ + struct iio_dev *indio_dev = private; + struct sx9310_data *data = iio_priv(indio_dev); + int ret; + unsigned int val; + + mutex_lock(&data->mutex); + + ret = regmap_read(data->regmap, SX9310_REG_IRQ_SRC, &val); + if (ret < 0) { + dev_err(&data->client->dev, "i2c transfer error in irq\n"); + goto out; + } + + if (val & SX9310_EVENT_IRQ) + sx9310_push_events(indio_dev); + + if (val & SX9310_CONVDONE_IRQ) + complete(&data->completion); + +out: + mutex_unlock(&data->mutex); + + return IRQ_HANDLED; +} + +static int sx9310_read_event_config(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir) +{ + struct sx9310_data *data = iio_priv(indio_dev); + + return !!(data->chan_event & BIT(chan->channel)); +} + +static int sx9310_write_event_config(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, int state) +{ + struct sx9310_data *data = iio_priv(indio_dev); + int ret; + + /* If the state hasn't changed, there's nothing to do. */ + if (!!(data->chan_event & BIT(chan->channel)) == state) + return 0; + + mutex_lock(&data->mutex); + if (state) { + ret = sx9310_get_event_channel(data, chan->channel); + if (ret < 0) + goto out_unlock; + if (!(data->chan_event & ~BIT(chan->channel))) { + ret = sx9310_enable_irq(data, SX9310_EVENT_IRQ); + if (ret < 0) + sx9310_put_event_channel(data, chan->channel); + } + } else { + ret = sx9310_put_event_channel(data, chan->channel); + if (ret < 0) + goto out_unlock; + if (!data->chan_event) { + ret = sx9310_disable_irq(data, SX9310_EVENT_IRQ); + if (ret < 0) + sx9310_get_event_channel(data, chan->channel); + } + } + +out_unlock: + mutex_unlock(&data->mutex); + return ret; +} + +static struct attribute *sx9310_attributes[] = { + &iio_dev_attr_sampling_frequency_available.dev_attr.attr, + NULL, +}; + +static const struct attribute_group sx9310_attribute_group = { + .attrs = sx9310_attributes, +}; + +static const struct iio_info sx9310_info = { + .attrs = &sx9310_attribute_group, + .read_raw = sx9310_read_raw, + .write_raw = sx9310_write_raw, + .read_event_config = sx9310_read_event_config, + .write_event_config = sx9310_write_event_config, +}; + +static int sx9310_set_trigger_state(struct iio_trigger *trig, bool state) +{ + struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); + struct sx9310_data *data = iio_priv(indio_dev); + int ret = 0; + + mutex_lock(&data->mutex); + + if (state) + ret = sx9310_enable_irq(data, SX9310_CONVDONE_IRQ); + else if (!data->chan_read) + ret = sx9310_disable_irq(data, SX9310_CONVDONE_IRQ); + if (ret < 0) + goto out; + + data->trigger_enabled = state; + +out: + mutex_unlock(&data->mutex); + + return ret; +} + +static const struct iio_trigger_ops sx9310_trigger_ops = { + .set_trigger_state = sx9310_set_trigger_state, +}; + +static irqreturn_t sx9310_trigger_handler(int irq, void *private) +{ + struct iio_poll_func *pf = private; + struct iio_dev *indio_dev = pf->indio_dev; + struct sx9310_data *data = iio_priv(indio_dev); + __be16 val; + int bit, ret, i = 0; + + mutex_lock(&data->mutex); + + for_each_set_bit(bit, indio_dev->active_scan_mask, + indio_dev->masklength) { + ret = sx9310_read_prox_data(data, &indio_dev->channels[bit], + &val); + if (ret < 0) + goto out; + + data->buffer[i++] = val; + } + + iio_push_to_buffers_with_timestamp(indio_dev, data->buffer, + pf->timestamp); + +out: + mutex_unlock(&data->mutex); + + iio_trigger_notify_done(indio_dev->trig); + + return IRQ_HANDLED; +} + +static int sx9310_buffer_preenable(struct iio_dev *indio_dev) +{ + struct sx9310_data *data = iio_priv(indio_dev); + unsigned int channels = 0; + int bit, ret; + + mutex_lock(&data->mutex); + for_each_set_bit(bit, indio_dev->active_scan_mask, + indio_dev->masklength) + channels |= BIT(indio_dev->channels[bit].channel); + + ret = sx9310_update_chan_en(data, channels, data->chan_event); + mutex_unlock(&data->mutex); + return ret; +} + +static int sx9310_buffer_postdisable(struct iio_dev *indio_dev) +{ + struct sx9310_data *data = iio_priv(indio_dev); + int ret; + + mutex_lock(&data->mutex); + ret = sx9310_update_chan_en(data, 0, data->chan_event); + mutex_unlock(&data->mutex); + return ret; +} + +static const struct iio_buffer_setup_ops sx9310_buffer_setup_ops = { + .preenable = sx9310_buffer_preenable, + .postenable = iio_triggered_buffer_postenable, + .predisable = iio_triggered_buffer_predisable, + .postdisable = sx9310_buffer_postdisable, +}; + +struct sx9310_reg_default { + u8 reg; + u8 def; +}; + +#define SX_INIT(_reg, _def) \ + { \ + .reg = SX9310_REG_##_reg, \ + .def = _def, \ + } + +static const struct sx9310_reg_default sx9310_default_regs[] = { + SX_INIT(IRQ_MSK, 0x00), + SX_INIT(IRQ_FUNC, 0x00), + /* + * The lower 4 bits should not be set as it enable sensors measurements. + * Turning the detection on before the configuration values are set to + * good values can cause the device to return erroneous readings. + */ + SX_INIT(PROX_CTRL0, SX9310_REG_PROX_CTRL0_PROXSTAT2), + SX_INIT(PROX_CTRL1, 0x00), + SX_INIT(PROX_CTRL2, SX9310_REG_PROX_CTRL2_COMBMODE_ALL | + SX9310_REG_PROX_CTRL2_SHIELDEN_DYNAMIC), + SX_INIT(PROX_CTRL3, SX9310_REG_PROX_CTRL3_GAIN0_X8 | + SX9310_REG_PROX_CTRL3_GAIN12_X4), + SX_INIT(PROX_CTRL4, SX9310_REG_PROX_CTRL4_RESOLUTION_FINEST), + SX_INIT(PROX_CTRL5, SX9310_REG_PROX_CTRL5_RANGE_SMALL | + SX9310_REG_PROX_CTRL5_STARTUPSENS_CS1 | + SX9310_REG_PROX_CTRL5_RAWFILT_1P25), + SX_INIT(PROX_CTRL6, SX9310_REG_PROX_CTRL6_COMP_COMMON), + SX_INIT(PROX_CTRL7, SX9310_REG_PROX_CTRL7_AVGNEGFILT_2 | + SX9310_REG_PROX_CTRL7_AVGPOSFILT_512), + SX_INIT(PROX_CTRL8, SX9310_REG_PROX_CTRL8_9_PTHRESH_96 | + SX9310_REG_PROX_CTRL8_9_BODYTHRESH_1500), + SX_INIT(PROX_CTRL9, SX9310_REG_PROX_CTRL8_9_PTHRESH12_28 | + SX9310_REG_PROX_CTRL8_9_BODYTHRESH_900), + SX_INIT(PROX_CTRL10, SX9310_REG_PROX_CTRL10_HYST_6PCT | + SX9310_REG_PROX_CTRL10_CLOSE_DEBOUNCE_8 | + SX9310_REG_PROX_CTRL10_FAR_DEBOUNCE_8), + SX_INIT(PROX_CTRL11, 0x00), + SX_INIT(PROX_CTRL12, 0x00), + SX_INIT(PROX_CTRL13, 0x00), + SX_INIT(PROX_CTRL14, 0x00), + SX_INIT(PROX_CTRL15, 0x00), + SX_INIT(PROX_CTRL16, 0x00), + SX_INIT(PROX_CTRL17, 0x00), + SX_INIT(PROX_CTRL18, 0x00), + SX_INIT(PROX_CTRL19, 0x00), + SX_INIT(SAR_CTRL0, SX9310_REG_SAR_CTRL0_SARDEB_4_SAMPLES | + SX9310_REG_SAR_CTRL0_SARHYST_8), + SX_INIT(SAR_CTRL1, SX9310_REG_SAR_CTRL1_SLOPE(10781250)), + SX_INIT(SAR_CTRL2, SX9310_REG_SAR_CTRL2_SAROFFSET_DEFAULT), +}; + +/* Activate all channels and perform an initial compensation. */ +static int sx9310_init_compensation(struct iio_dev *indio_dev) +{ + struct sx9310_data *data = iio_priv(indio_dev); + int i, ret; + unsigned int val; + unsigned int ctrl0; + + ret = regmap_read(data->regmap, SX9310_REG_PROX_CTRL0, &ctrl0); + if (ret < 0) + return ret; + + /* run the compensation phase on all channels */ + ret = regmap_write(data->regmap, SX9310_REG_PROX_CTRL0, + ctrl0 | SX9310_REG_PROX_CTRL0_EN_MASK); + if (ret < 0) + return ret; + + for (i = 100; i >= 0; i--) { + msleep(20); + ret = regmap_read(data->regmap, SX9310_REG_STAT1, &val); + if (ret < 0) + goto out; + if (!(val & SX9310_COMPSTAT_MASK)) + break; + } + + if (i < 0) { + dev_err(&data->client->dev, + "initial compensation timed out: 0x%02x", val); + ret = -ETIMEDOUT; + } + +out: + regmap_write(data->regmap, SX9310_REG_PROX_CTRL0, ctrl0); + return ret; +} + +static int sx9310_init_device(struct iio_dev *indio_dev) +{ + struct sx9310_data *data = iio_priv(indio_dev); + const struct sx9310_reg_default *initval; + int ret; + unsigned int i, val; + + ret = regmap_write(data->regmap, SX9310_REG_RESET, SX9310_SOFT_RESET); + if (ret < 0) + return ret; + + usleep_range(1000, 2000); /* power-up time is ~1ms. */ + + /* Clear reset interrupt state by reading SX9310_REG_IRQ_SRC. */ + ret = regmap_read(data->regmap, SX9310_REG_IRQ_SRC, &val); + if (ret < 0) + return ret; + + /* Program some sane defaults. */ + for (i = 0; i < ARRAY_SIZE(sx9310_default_regs); i++) { + initval = &sx9310_default_regs[i]; + ret = regmap_write(data->regmap, initval->reg, initval->def); + if (ret < 0) + return ret; + } + + return sx9310_init_compensation(indio_dev); +} + +static int sx9310_set_indio_dev_name(struct device *dev, + struct iio_dev *indio_dev, + const struct i2c_device_id *id, int whoami) +{ + const struct acpi_device_id *acpi_id; + + /* id will be NULL when enumerated via ACPI */ + if (id) { + if (id->driver_data != whoami) + dev_err(dev, "WHOAMI does not match i2c_device_id: %s", + id->name); + } else if (ACPI_HANDLE(dev)) { + acpi_id = acpi_match_device(dev->driver->acpi_match_table, dev); + if (!acpi_id) + return -ENODEV; + if (acpi_id->driver_data != whoami) + dev_err(dev, "WHOAMI does not match acpi_device_id: %s", + acpi_id->id); + } else + return -ENODEV; + + switch (whoami) { + case SX9310_WHOAMI_VALUE: + indio_dev->name = "sx9310"; + break; + case SX9311_WHOAMI_VALUE: + indio_dev->name = "sx9311"; + break; + default: + dev_err(dev, "unexpected WHOAMI response: %u", whoami); + return -ENODEV; + } + + return 0; +} + +static int sx9310_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int ret; + struct iio_dev *indio_dev; + struct sx9310_data *data; + + indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); + if (indio_dev == NULL) + return -ENOMEM; + + data = iio_priv(indio_dev); + data->client = client; + mutex_init(&data->mutex); + init_completion(&data->completion); + + data->regmap = devm_regmap_init_i2c(client, &sx9310_regmap_config); + if (IS_ERR(data->regmap)) + return PTR_ERR(data->regmap); + + ret = regmap_read(data->regmap, SX9310_REG_WHOAMI, &data->whoami); + if (ret < 0) { + dev_err(&client->dev, "error in reading WHOAMI register: %d", + ret); + return ret; + } + + ret = sx9310_set_indio_dev_name(&client->dev, indio_dev, id, + data->whoami); + if (ret < 0) + return ret; + + ACPI_COMPANION_SET(&indio_dev->dev, ACPI_COMPANION(&client->dev)); + indio_dev->dev.parent = &client->dev; + indio_dev->channels = sx9310_channels; + indio_dev->num_channels = ARRAY_SIZE(sx9310_channels); + indio_dev->info = &sx9310_info; + indio_dev->modes = INDIO_DIRECT_MODE; + i2c_set_clientdata(client, indio_dev); + + ret = sx9310_init_device(indio_dev); + if (ret < 0) + return ret; + + if (client->irq) { + ret = devm_request_threaded_irq(&client->dev, client->irq, + sx9310_irq_handler, + sx9310_irq_thread_handler, + IRQF_TRIGGER_LOW | IRQF_ONESHOT, + "sx9310_event", indio_dev); + if (ret < 0) + return ret; + + data->trig = + devm_iio_trigger_alloc(&client->dev, "%s-dev%d", + indio_dev->name, indio_dev->id); + if (!data->trig) + return -ENOMEM; + + data->trig->dev.parent = &client->dev; + data->trig->ops = &sx9310_trigger_ops; + iio_trigger_set_drvdata(data->trig, indio_dev); + + ret = devm_iio_trigger_register(&client->dev, data->trig); + if (ret) + return ret; + } + + ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, + iio_pollfunc_store_time, + sx9310_trigger_handler, + &sx9310_buffer_setup_ops); + if (ret < 0) + return ret; + + return devm_iio_device_register(&client->dev, indio_dev); +} + +static int __maybe_unused sx9310_suspend(struct device *dev) +{ + struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); + struct sx9310_data *data = iio_priv(indio_dev); + u8 ctrl0; + int ret; + + disable_irq_nosync(data->client->irq); + + mutex_lock(&data->mutex); + ret = regmap_read(data->regmap, SX9310_REG_PROX_CTRL0, + &data->suspend_ctrl0); + + if (ret) + goto out; + + ctrl0 = data->suspend_ctrl0 & ~SX9310_REG_PROX_CTRL0_EN_MASK; + ret = regmap_write(data->regmap, SX9310_REG_PROX_CTRL0, ctrl0); + if (ret) + goto out; + + ret = regmap_write(data->regmap, SX9310_REG_PAUSE, 0); + +out: + mutex_unlock(&data->mutex); + return ret; +} + +static int __maybe_unused sx9310_resume(struct device *dev) +{ + struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); + struct sx9310_data *data = iio_priv(indio_dev); + int ret; + + mutex_lock(&data->mutex); + ret = regmap_write(data->regmap, SX9310_REG_PAUSE, 1); + if (ret) + goto out; + + ret = regmap_write(data->regmap, SX9310_REG_PROX_CTRL0, + data->suspend_ctrl0); + +out: + mutex_unlock(&data->mutex); + + enable_irq(data->client->irq); + + return ret; +} + +static const struct dev_pm_ops sx9310_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(sx9310_suspend, sx9310_resume) +}; + +static const struct acpi_device_id sx9310_acpi_match[] = { + { "STH9310", SX9310_WHOAMI_VALUE }, + { "STH9311", SX9311_WHOAMI_VALUE }, + {}, +}; +MODULE_DEVICE_TABLE(acpi, sx9310_acpi_match); + +static const struct of_device_id sx9310_of_match[] = { + { .compatible = "semtech,sx9310" }, + { .compatible = "semtech,sx9311" }, + {}, +}; +MODULE_DEVICE_TABLE(of, sx9310_of_match); + +static const struct i2c_device_id sx9310_id[] = { + { "sx9310", SX9310_WHOAMI_VALUE }, + { "sx9311", SX9311_WHOAMI_VALUE }, + {}, +}; +MODULE_DEVICE_TABLE(i2c, sx9310_id); + +static struct i2c_driver sx9310_driver = { + .driver = { + .name = "sx9310", + .acpi_match_table = ACPI_PTR(sx9310_acpi_match), + .of_match_table = of_match_ptr(sx9310_of_match), + .pm = &sx9310_pm_ops, + }, + .probe = sx9310_probe, + .id_table = sx9310_id, +}; +module_i2c_driver(sx9310_driver); + +MODULE_AUTHOR("Gwendal Grignou "); +MODULE_AUTHOR("Daniel Campello "); +MODULE_DESCRIPTION("Driver for Semtech SX9310/SX9311 proximity sensor"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/iio/proximity/vcnl3020.c b/drivers/iio/proximity/vcnl3020.c new file mode 100644 index 000000000000..9ff1a164c2e6 --- /dev/null +++ b/drivers/iio/proximity/vcnl3020.c @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Support for Vishay VCNL3020 proximity sensor on i2c bus. + * Based on Vishay VCNL4000 driver code. + * + * TODO: interrupts. + */ + +#include +#include +#include +#include +#include + +#include +#include + +#define VCNL3020_PROD_ID 0x21 + +#define VCNL_COMMAND 0x80 /* Command register */ +#define VCNL_PROD_REV 0x81 /* Product ID and Revision ID */ +#define VCNL_PROXIMITY_RATE 0x82 /* Rate of Proximity Measurement */ +#define VCNL_LED_CURRENT 0x83 /* IR LED current for proximity mode */ +#define VCNL_PS_RESULT_HI 0x87 /* Proximity result register, MSB */ +#define VCNL_PS_RESULT_LO 0x88 /* Proximity result register, LSB */ +#define VCNL_PS_ICR 0x89 /* Interrupt Control Register */ +#define VCNL_PS_LO_THR_HI 0x8a /* High byte of low threshold value */ +#define VCNL_PS_LO_THR_LO 0x8b /* Low byte of low threshold value */ +#define VCNL_PS_HI_THR_HI 0x8c /* High byte of high threshold value */ +#define VCNL_PS_HI_THR_LO 0x8d /* Low byte of high threshold value */ +#define VCNL_ISR 0x8e /* Interrupt Status Register */ +#define VCNL_PS_MOD_ADJ 0x8f /* Proximity Modulator Timing Adjustment */ + +/* Bit masks for COMMAND register */ +#define VCNL_PS_RDY BIT(5) /* proximity data ready? */ +#define VCNL_PS_OD BIT(3) /* start on-demand proximity + * measurement + */ + +#define VCNL_ON_DEMAND_TIMEOUT_US 100000 +#define VCNL_POLL_US 20000 + +/** + * struct vcnl3020_data - vcnl3020 specific data. + * @regmap: device register map. + * @dev: vcnl3020 device. + * @rev: revision id. + * @lock: lock for protecting access to device hardware registers. + */ +struct vcnl3020_data { + struct regmap *regmap; + struct device *dev; + u8 rev; + struct mutex lock; +}; + +/** + * struct vcnl3020_property - vcnl3020 property. + * @name: property name. + * @reg: i2c register offset. + * @conversion_func: conversion function. + */ +struct vcnl3020_property { + const char *name; + u32 reg; + u32 (*conversion_func)(u32 *val); +}; + +static u32 microamp_to_reg(u32 *val) +{ + /* + * An example of conversion from uA to reg val: + * 200000 uA == 200 mA == 20 + */ + return *val /= 10000; +}; + +static struct vcnl3020_property vcnl3020_led_current_property = { + .name = "vishay,led-current-microamp", + .reg = VCNL_LED_CURRENT, + .conversion_func = microamp_to_reg, +}; + +static int vcnl3020_get_and_apply_property(struct vcnl3020_data *data, + struct vcnl3020_property prop) +{ + int rc; + u32 val; + + rc = device_property_read_u32(data->dev, prop.name, &val); + if (rc) + return 0; + + if (prop.conversion_func) + prop.conversion_func(&val); + + rc = regmap_write(data->regmap, prop.reg, val); + if (rc) { + dev_err(data->dev, "Error (%d) setting property (%s)\n", + rc, prop.name); + } + + return rc; +} + +static int vcnl3020_init(struct vcnl3020_data *data) +{ + int rc; + unsigned int reg; + + rc = regmap_read(data->regmap, VCNL_PROD_REV, ®); + if (rc) { + dev_err(data->dev, + "Error (%d) reading product revision\n", rc); + return rc; + } + + if (reg != VCNL3020_PROD_ID) { + dev_err(data->dev, + "Product id (%x) did not match vcnl3020 (%x)\n", reg, + VCNL3020_PROD_ID); + return -ENODEV; + } + + data->rev = reg; + mutex_init(&data->lock); + + return vcnl3020_get_and_apply_property(data, + vcnl3020_led_current_property); +}; + +static int vcnl3020_measure_proximity(struct vcnl3020_data *data, int *val) +{ + int rc; + unsigned int reg; + __be16 res; + + mutex_lock(&data->lock); + + rc = regmap_write(data->regmap, VCNL_COMMAND, VCNL_PS_OD); + if (rc) + goto err_unlock; + + /* wait for data to become ready */ + rc = regmap_read_poll_timeout(data->regmap, VCNL_COMMAND, reg, + reg & VCNL_PS_RDY, VCNL_POLL_US, + VCNL_ON_DEMAND_TIMEOUT_US); + if (rc) { + dev_err(data->dev, + "Error (%d) reading vcnl3020 command register\n", rc); + goto err_unlock; + } + + /* high & low result bytes read */ + rc = regmap_bulk_read(data->regmap, VCNL_PS_RESULT_HI, &res, + sizeof(res)); + if (rc) + goto err_unlock; + + *val = be16_to_cpu(res); + +err_unlock: + mutex_unlock(&data->lock); + + return rc; +} + +static const struct iio_chan_spec vcnl3020_channels[] = { + { + .type = IIO_PROXIMITY, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), + }, +}; + +static int vcnl3020_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, + int *val2, long mask) +{ + int rc; + struct vcnl3020_data *data = iio_priv(indio_dev); + + switch (mask) { + case IIO_CHAN_INFO_RAW: + rc = vcnl3020_measure_proximity(data, val); + if (rc) + return rc; + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static const struct iio_info vcnl3020_info = { + .read_raw = vcnl3020_read_raw, +}; + +static const struct regmap_config vcnl3020_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = VCNL_PS_MOD_ADJ, +}; + +static int vcnl3020_probe(struct i2c_client *client) +{ + struct vcnl3020_data *data; + struct iio_dev *indio_dev; + struct regmap *regmap; + int rc; + + regmap = devm_regmap_init_i2c(client, &vcnl3020_regmap_config); + if (IS_ERR(regmap)) { + dev_err(&client->dev, "regmap_init failed\n"); + return PTR_ERR(regmap); + } + + indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); + if (!indio_dev) + return -ENOMEM; + + data = iio_priv(indio_dev); + i2c_set_clientdata(client, indio_dev); + data->regmap = regmap; + data->dev = &client->dev; + + rc = vcnl3020_init(data); + if (rc) + return rc; + + indio_dev->dev.parent = &client->dev; + indio_dev->info = &vcnl3020_info; + indio_dev->channels = vcnl3020_channels; + indio_dev->num_channels = ARRAY_SIZE(vcnl3020_channels); + indio_dev->name = "vcnl3020"; + indio_dev->modes = INDIO_DIRECT_MODE; + + return devm_iio_device_register(&client->dev, indio_dev); +} + +static const struct of_device_id vcnl3020_of_match[] = { + { + .compatible = "vishay,vcnl3020", + }, + {} +}; +MODULE_DEVICE_TABLE(of, vcnl3020_of_match); + +static struct i2c_driver vcnl3020_driver = { + .driver = { + .name = "vcnl3020", + .of_match_table = vcnl3020_of_match, + }, + .probe_new = vcnl3020_probe, +}; +module_i2c_driver(vcnl3020_driver); + +MODULE_AUTHOR("Ivan Mikhaylov "); +MODULE_DESCRIPTION("Vishay VCNL3020 proximity sensor driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/iio/temperature/hid-sensor-temperature.c b/drivers/iio/temperature/hid-sensor-temperature.c index eda55b9c1e9b..8d1f434f109d 100644 --- a/drivers/iio/temperature/hid-sensor-temperature.c +++ b/drivers/iio/temperature/hid-sensor-temperature.c @@ -7,8 +7,6 @@ #include #include #include -#include -#include #include #include @@ -230,12 +228,8 @@ static int hid_temperature_probe(struct platform_device *pdev) indio_dev->name = name; indio_dev->modes = INDIO_DIRECT_MODE; - ret = devm_iio_triggered_buffer_setup(&pdev->dev, indio_dev, - &iio_pollfunc_store_time, NULL, NULL); - if (ret) - return ret; - atomic_set(&temp_st->common_attributes.data_ready, 0); + ret = hid_sensor_setup_trigger(indio_dev, name, &temp_st->common_attributes); if (ret) @@ -258,7 +252,7 @@ static int hid_temperature_probe(struct platform_device *pdev) error_remove_callback: sensor_hub_remove_callback(hsdev, HID_USAGE_SENSOR_TEMPERATURE); error_remove_trigger: - hid_sensor_remove_trigger(&temp_st->common_attributes); + hid_sensor_remove_trigger(indio_dev, &temp_st->common_attributes); return ret; } @@ -270,7 +264,7 @@ static int hid_temperature_remove(struct platform_device *pdev) struct temperature_state *temp_st = iio_priv(indio_dev); sensor_hub_remove_callback(hsdev, HID_USAGE_SENSOR_TEMPERATURE); - hid_sensor_remove_trigger(&temp_st->common_attributes); + hid_sensor_remove_trigger(indio_dev, &temp_st->common_attributes); return 0; } diff --git a/drivers/iio/temperature/ltc2983.c b/drivers/iio/temperature/ltc2983.c index d39c0d6b77f1..8976e8d59826 100644 --- a/drivers/iio/temperature/ltc2983.c +++ b/drivers/iio/temperature/ltc2983.c @@ -390,8 +390,8 @@ static struct ltc2983_custom_sensor *__ltc2983_custom_sensor_new( * For custom steinhart, the full u32 is taken. For all the others * the MSB is discarded. */ - const u8 n_size = (is_steinhart == true) ? 4 : 3; - const u8 e_size = (is_steinhart == true) ? sizeof(u32) : sizeof(u64); + const u8 n_size = is_steinhart ? 4 : 3; + const u8 e_size = is_steinhart ? sizeof(u32) : sizeof(u64); n_entries = of_property_count_elems_of_size(np, propname, e_size); /* n_entries must be an even number */ diff --git a/drivers/iio/temperature/max31856.c b/drivers/iio/temperature/max31856.c index b4cb21ab2e85..b4c49a5d3685 100644 --- a/drivers/iio/temperature/max31856.c +++ b/drivers/iio/temperature/max31856.c @@ -14,6 +14,7 @@ #include #include #include +#include #include /* * The MSB of the register value determines whether the following byte will @@ -168,7 +169,7 @@ static int max31856_thermocouple_read(struct max31856_data *data, if (ret) return ret; /* Skip last 5 dead bits of LTCBL */ - *val = (reg_val[0] << 16 | reg_val[1] << 8 | reg_val[2]) >> 5; + *val = get_unaligned_be24(®_val[0]) >> 5; /* Check 7th bit of LTCBH reg. value for sign*/ if (reg_val[0] & 0x80) *val -= 0x80000; @@ -185,7 +186,7 @@ static int max31856_thermocouple_read(struct max31856_data *data, /* Get Cold Junction Temp. offset register value */ offset_cjto = reg_val[0]; /* Get CJTH and CJTL value and skip last 2 dead bits of CJTL */ - *val = (reg_val[1] << 8 | reg_val[2]) >> 2; + *val = get_unaligned_be16(®_val[1]) >> 2; /* As per datasheet add offset into CJTH and CJTL */ *val += offset_cjto; /* Check 7th bit of CJTH reg. value for sign */ diff --git a/drivers/iio/trigger/iio-trig-hrtimer.c b/drivers/iio/trigger/iio-trig-hrtimer.c index a5e670726717..f59bf8d58586 100644 --- a/drivers/iio/trigger/iio-trig-hrtimer.c +++ b/drivers/iio/trigger/iio-trig-hrtimer.c @@ -4,7 +4,7 @@ * * Copyright (C) Intuitive Aerial AB * Written by Marten Svanfeldt, marten@intuitiveaerial.com - * Copyright (C) 2012, Analog Device Inc. + * Copyright (C) 2012, Analog Devices Inc. * Author: Lars-Peter Clausen * Copyright (C) 2015, Intel Corporation */ diff --git a/drivers/interconnect/Kconfig b/drivers/interconnect/Kconfig index bfa4ca3ab7a9..5b7204ee2eb2 100644 --- a/drivers/interconnect/Kconfig +++ b/drivers/interconnect/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only menuconfig INTERCONNECT - tristate "On-Chip Interconnect management support" + bool "On-Chip Interconnect management support" help Support for management of the on-chip interconnects. @@ -11,6 +11,7 @@ menuconfig INTERCONNECT if INTERCONNECT +source "drivers/interconnect/imx/Kconfig" source "drivers/interconnect/qcom/Kconfig" endif diff --git a/drivers/interconnect/Makefile b/drivers/interconnect/Makefile index 725029ae7a2c..4825c287ca13 100644 --- a/drivers/interconnect/Makefile +++ b/drivers/interconnect/Makefile @@ -4,4 +4,5 @@ CFLAGS_core.o := -I$(src) icc-core-objs := core.o obj-$(CONFIG_INTERCONNECT) += icc-core.o +obj-$(CONFIG_INTERCONNECT_IMX) += imx/ obj-$(CONFIG_INTERCONNECT_QCOM) += qcom/ diff --git a/drivers/interconnect/core.c b/drivers/interconnect/core.c index 2c6515e3ecf1..ece2a579a9b0 100644 --- a/drivers/interconnect/core.c +++ b/drivers/interconnect/core.c @@ -158,6 +158,7 @@ static struct icc_path *path_init(struct device *dev, struct icc_node *dst, hlist_add_head(&path->reqs[i].req_node, &node->req_list); path->reqs[i].node = node; path->reqs[i].dev = dev; + path->reqs[i].enabled = true; /* reference to previous node was saved during path traversal */ node = node->reverse; } @@ -249,9 +250,12 @@ static int aggregate_requests(struct icc_node *node) if (p->pre_aggregate) p->pre_aggregate(node); - hlist_for_each_entry(r, &node->req_list, req_node) + hlist_for_each_entry(r, &node->req_list, req_node) { + if (!r->enabled) + continue; p->aggregate(node, r->tag, r->avg_bw, r->peak_bw, &node->avg_bw, &node->peak_bw); + } return 0; } @@ -350,10 +354,35 @@ static struct icc_node *of_icc_get_from_provider(struct of_phandle_args *spec) return node; } +static void devm_icc_release(struct device *dev, void *res) +{ + icc_put(*(struct icc_path **)res); +} + +struct icc_path *devm_of_icc_get(struct device *dev, const char *name) +{ + struct icc_path **ptr, *path; + + ptr = devres_alloc(devm_icc_release, sizeof(**ptr), GFP_KERNEL); + if (!ptr) + return ERR_PTR(-ENOMEM); + + path = of_icc_get(dev, name); + if (!IS_ERR(path)) { + *ptr = path; + devres_add(dev, ptr); + } else { + devres_free(ptr); + } + + return path; +} +EXPORT_SYMBOL_GPL(devm_of_icc_get); + /** - * of_icc_get() - get a path handle from a DT node based on name + * of_icc_get_by_index() - get a path handle from a DT node based on index * @dev: device pointer for the consumer device - * @name: interconnect path name + * @idx: interconnect path index * * This function will search for a path between two endpoints and return an * icc_path handle on success. Use icc_put() to release constraints when they @@ -365,13 +394,12 @@ static struct icc_node *of_icc_get_from_provider(struct of_phandle_args *spec) * Return: icc_path pointer on success or ERR_PTR() on error. NULL is returned * when the API is disabled or the "interconnects" DT property is missing. */ -struct icc_path *of_icc_get(struct device *dev, const char *name) +struct icc_path *of_icc_get_by_index(struct device *dev, int idx) { - struct icc_path *path = ERR_PTR(-EPROBE_DEFER); + struct icc_path *path; struct icc_node *src_node, *dst_node; - struct device_node *np = NULL; + struct device_node *np; struct of_phandle_args src_args, dst_args; - int idx = 0; int ret; if (!dev || !dev->of_node) @@ -391,12 +419,6 @@ struct icc_path *of_icc_get(struct device *dev, const char *name) * lets support only global ids and extend this in the future if needed * without breaking DT compatibility. */ - if (name) { - idx = of_property_match_string(np, "interconnect-names", name); - if (idx < 0) - return ERR_PTR(idx); - } - ret = of_parse_phandle_with_args(np, "interconnects", "#interconnect-cells", idx * 2, &src_args); @@ -439,12 +461,8 @@ struct icc_path *of_icc_get(struct device *dev, const char *name) return path; } - if (name) - path->name = kstrdup_const(name, GFP_KERNEL); - else - path->name = kasprintf(GFP_KERNEL, "%s-%s", - src_node->name, dst_node->name); - + path->name = kasprintf(GFP_KERNEL, "%s-%s", + src_node->name, dst_node->name); if (!path->name) { kfree(path); return ERR_PTR(-ENOMEM); @@ -452,6 +470,53 @@ struct icc_path *of_icc_get(struct device *dev, const char *name) return path; } +EXPORT_SYMBOL_GPL(of_icc_get_by_index); + +/** + * of_icc_get() - get a path handle from a DT node based on name + * @dev: device pointer for the consumer device + * @name: interconnect path name + * + * This function will search for a path between two endpoints and return an + * icc_path handle on success. Use icc_put() to release constraints when they + * are not needed anymore. + * If the interconnect API is disabled, NULL is returned and the consumer + * drivers will still build. Drivers are free to handle this specifically, + * but they don't have to. + * + * Return: icc_path pointer on success or ERR_PTR() on error. NULL is returned + * when the API is disabled or the "interconnects" DT property is missing. + */ +struct icc_path *of_icc_get(struct device *dev, const char *name) +{ + struct device_node *np; + int idx = 0; + + if (!dev || !dev->of_node) + return ERR_PTR(-ENODEV); + + np = dev->of_node; + + /* + * When the consumer DT node do not have "interconnects" property + * return a NULL path to skip setting constraints. + */ + if (!of_find_property(np, "interconnects", NULL)) + return NULL; + + /* + * We use a combination of phandle and specifier for endpoint. For now + * lets support only global ids and extend this in the future if needed + * without breaking DT compatibility. + */ + if (name) { + idx = of_property_match_string(np, "interconnect-names", name); + if (idx < 0) + return ERR_PTR(idx); + } + + return of_icc_get_by_index(dev, idx); +} EXPORT_SYMBOL_GPL(of_icc_get); /** @@ -546,6 +611,39 @@ int icc_set_bw(struct icc_path *path, u32 avg_bw, u32 peak_bw) } EXPORT_SYMBOL_GPL(icc_set_bw); +static int __icc_enable(struct icc_path *path, bool enable) +{ + int i; + + if (!path) + return 0; + + if (WARN_ON(IS_ERR(path) || !path->num_nodes)) + return -EINVAL; + + mutex_lock(&icc_lock); + + for (i = 0; i < path->num_nodes; i++) + path->reqs[i].enabled = enable; + + mutex_unlock(&icc_lock); + + return icc_set_bw(path, path->reqs[0].avg_bw, + path->reqs[0].peak_bw); +} + +int icc_enable(struct icc_path *path) +{ + return __icc_enable(path, true); +} +EXPORT_SYMBOL_GPL(icc_enable); + +int icc_disable(struct icc_path *path) +{ + return __icc_enable(path, false); +} +EXPORT_SYMBOL_GPL(icc_disable); + /** * icc_get() - return a handle for path between two endpoints * @dev: the device requesting the path @@ -908,12 +1006,7 @@ static int __init icc_init(void) return 0; } -static void __exit icc_exit(void) -{ - debugfs_remove_recursive(icc_debugfs_dir); -} -module_init(icc_init); -module_exit(icc_exit); +device_initcall(icc_init); MODULE_AUTHOR("Georgi Djakov "); MODULE_DESCRIPTION("Interconnect Driver Core"); diff --git a/drivers/interconnect/imx/Kconfig b/drivers/interconnect/imx/Kconfig new file mode 100644 index 000000000000..be2928362bb7 --- /dev/null +++ b/drivers/interconnect/imx/Kconfig @@ -0,0 +1,17 @@ +config INTERCONNECT_IMX + tristate "i.MX interconnect drivers" + depends on ARCH_MXC || COMPILE_TEST + help + Generic interconnect drivers for i.MX SOCs + +config INTERCONNECT_IMX8MM + tristate "i.MX8MM interconnect driver" + depends on INTERCONNECT_IMX + +config INTERCONNECT_IMX8MN + tristate "i.MX8MN interconnect driver" + depends on INTERCONNECT_IMX + +config INTERCONNECT_IMX8MQ + tristate "i.MX8MQ interconnect driver" + depends on INTERCONNECT_IMX diff --git a/drivers/interconnect/imx/Makefile b/drivers/interconnect/imx/Makefile new file mode 100644 index 000000000000..21fd5233754f --- /dev/null +++ b/drivers/interconnect/imx/Makefile @@ -0,0 +1,9 @@ +imx-interconnect-objs := imx.o +imx8mm-interconnect-objs := imx8mm.o +imx8mq-interconnect-objs := imx8mq.o +imx8mn-interconnect-objs := imx8mn.o + +obj-$(CONFIG_INTERCONNECT_IMX) += imx-interconnect.o +obj-$(CONFIG_INTERCONNECT_IMX8MM) += imx8mm-interconnect.o +obj-$(CONFIG_INTERCONNECT_IMX8MQ) += imx8mq-interconnect.o +obj-$(CONFIG_INTERCONNECT_IMX8MN) += imx8mn-interconnect.o diff --git a/drivers/interconnect/imx/imx.c b/drivers/interconnect/imx/imx.c new file mode 100644 index 000000000000..ac420f86008e --- /dev/null +++ b/drivers/interconnect/imx/imx.c @@ -0,0 +1,284 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Interconnect framework driver for i.MX SoC + * + * Copyright (c) 2019, BayLibre + * Copyright (c) 2019-2020, NXP + * Author: Alexandre Bailon + * Author: Leonard Crestez + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "imx.h" + +/* private icc_node data */ +struct imx_icc_node { + const struct imx_icc_node_desc *desc; + struct device *qos_dev; + struct dev_pm_qos_request qos_req; +}; + +static int imx_icc_node_set(struct icc_node *node) +{ + struct device *dev = node->provider->dev; + struct imx_icc_node *node_data = node->data; + u64 freq; + + if (!node_data->qos_dev) + return 0; + + freq = (node->avg_bw + node->peak_bw) * node_data->desc->adj->bw_mul; + do_div(freq, node_data->desc->adj->bw_div); + dev_dbg(dev, "node %s device %s avg_bw %ukBps peak_bw %ukBps min_freq %llukHz\n", + node->name, dev_name(node_data->qos_dev), + node->avg_bw, node->peak_bw, freq); + + if (freq > S32_MAX) { + dev_err(dev, "%s can't request more than S32_MAX freq\n", + node->name); + return -ERANGE; + } + + dev_pm_qos_update_request(&node_data->qos_req, freq); + + return 0; +} + +static int imx_icc_set(struct icc_node *src, struct icc_node *dst) +{ + return imx_icc_node_set(dst); +} + +/* imx_icc_node_destroy() - Destroy an imx icc_node, including private data */ +static void imx_icc_node_destroy(struct icc_node *node) +{ + struct imx_icc_node *node_data = node->data; + int ret; + + if (dev_pm_qos_request_active(&node_data->qos_req)) { + ret = dev_pm_qos_remove_request(&node_data->qos_req); + if (ret) + dev_warn(node->provider->dev, + "failed to remove qos request for %s\n", + dev_name(node_data->qos_dev)); + } + + put_device(node_data->qos_dev); + icc_node_del(node); + icc_node_destroy(node->id); +} + +static int imx_icc_node_init_qos(struct icc_provider *provider, + struct icc_node *node) +{ + struct imx_icc_node *node_data = node->data; + const struct imx_icc_node_adj_desc *adj = node_data->desc->adj; + struct device *dev = provider->dev; + struct device_node *dn = NULL; + struct platform_device *pdev; + + if (adj->main_noc) { + node_data->qos_dev = dev; + dev_dbg(dev, "icc node %s[%d] is main noc itself\n", + node->name, node->id); + } else { + dn = of_parse_phandle(dev->of_node, adj->phandle_name, 0); + if (!dn) { + dev_warn(dev, "Failed to parse %s\n", + adj->phandle_name); + return -ENODEV; + } + /* Allow scaling to be disabled on a per-node basis */ + if (!dn || !of_device_is_available(dn)) { + dev_warn(dev, "Missing property %s, skip scaling %s\n", + adj->phandle_name, node->name); + return 0; + } + + pdev = of_find_device_by_node(dn); + of_node_put(dn); + if (!pdev) { + dev_warn(dev, "node %s[%d] missing device for %pOF\n", + node->name, node->id, dn); + return -EPROBE_DEFER; + } + node_data->qos_dev = &pdev->dev; + dev_dbg(dev, "node %s[%d] has device node %pOF\n", + node->name, node->id, dn); + } + + return dev_pm_qos_add_request(node_data->qos_dev, + &node_data->qos_req, + DEV_PM_QOS_MIN_FREQUENCY, 0); +} + +static struct icc_node *imx_icc_node_add(struct icc_provider *provider, + const struct imx_icc_node_desc *node_desc) +{ + struct device *dev = provider->dev; + struct imx_icc_node *node_data; + struct icc_node *node; + int ret; + + node = icc_node_create(node_desc->id); + if (IS_ERR(node)) { + dev_err(dev, "failed to create node %d\n", node_desc->id); + return node; + } + + if (node->data) { + dev_err(dev, "already created node %s id=%d\n", + node_desc->name, node_desc->id); + return ERR_PTR(-EEXIST); + } + + node_data = devm_kzalloc(dev, sizeof(*node_data), GFP_KERNEL); + if (!node_data) { + icc_node_destroy(node->id); + return ERR_PTR(-ENOMEM); + } + + node->name = node_desc->name; + node->data = node_data; + node_data->desc = node_desc; + icc_node_add(node, provider); + + if (node_desc->adj) { + ret = imx_icc_node_init_qos(provider, node); + if (ret < 0) { + imx_icc_node_destroy(node); + return ERR_PTR(ret); + } + } + + return node; +} + +static void imx_icc_unregister_nodes(struct icc_provider *provider) +{ + struct icc_node *node, *tmp; + + list_for_each_entry_safe(node, tmp, &provider->nodes, node_list) + imx_icc_node_destroy(node); +} + +static int imx_icc_register_nodes(struct icc_provider *provider, + const struct imx_icc_node_desc *descs, + int count) +{ + struct icc_onecell_data *provider_data = provider->data; + int ret; + int i; + + for (i = 0; i < count; i++) { + struct icc_node *node; + const struct imx_icc_node_desc *node_desc = &descs[i]; + size_t j; + + node = imx_icc_node_add(provider, node_desc); + if (IS_ERR(node)) { + ret = PTR_ERR(node); + if (ret != -EPROBE_DEFER) + dev_err(provider->dev, "failed to add %s: %d\n", + node_desc->name, ret); + goto err; + } + provider_data->nodes[node->id] = node; + + for (j = 0; j < node_desc->num_links; j++) { + ret = icc_link_create(node, node_desc->links[j]); + if (ret) { + dev_err(provider->dev, "failed to link node %d to %d: %d\n", + node->id, node_desc->links[j], ret); + goto err; + } + } + } + + return 0; + +err: + imx_icc_unregister_nodes(provider); + + return ret; +} + +static int get_max_node_id(struct imx_icc_node_desc *nodes, int nodes_count) +{ + int i, ret = 0; + + for (i = 0; i < nodes_count; ++i) + if (nodes[i].id > ret) + ret = nodes[i].id; + + return ret; +} + +int imx_icc_register(struct platform_device *pdev, + struct imx_icc_node_desc *nodes, int nodes_count) +{ + struct device *dev = &pdev->dev; + struct icc_onecell_data *data; + struct icc_provider *provider; + int max_node_id; + int ret; + + /* icc_onecell_data is indexed by node_id, unlike nodes param */ + max_node_id = get_max_node_id(nodes, nodes_count); + data = devm_kzalloc(dev, struct_size(data, nodes, max_node_id), + GFP_KERNEL); + if (!data) + return -ENOMEM; + data->num_nodes = max_node_id; + + provider = devm_kzalloc(dev, sizeof(*provider), GFP_KERNEL); + if (!provider) + return -ENOMEM; + provider->set = imx_icc_set; + provider->aggregate = icc_std_aggregate; + provider->xlate = of_icc_xlate_onecell; + provider->data = data; + provider->dev = dev->parent; + platform_set_drvdata(pdev, provider); + + ret = icc_provider_add(provider); + if (ret) { + dev_err(dev, "error adding interconnect provider: %d\n", ret); + return ret; + } + + ret = imx_icc_register_nodes(provider, nodes, nodes_count); + if (ret) + goto provider_del; + + return 0; + +provider_del: + icc_provider_del(provider); + return ret; +} +EXPORT_SYMBOL_GPL(imx_icc_register); + +int imx_icc_unregister(struct platform_device *pdev) +{ + struct icc_provider *provider = platform_get_drvdata(pdev); + int ret; + + imx_icc_unregister_nodes(provider); + + ret = icc_provider_del(provider); + if (ret) + return ret; + + return 0; +} +EXPORT_SYMBOL_GPL(imx_icc_unregister); + +MODULE_LICENSE("GPL v2"); diff --git a/drivers/interconnect/imx/imx.h b/drivers/interconnect/imx/imx.h new file mode 100644 index 000000000000..75da51076c68 --- /dev/null +++ b/drivers/interconnect/imx/imx.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Interconnect framework driver for i.MX SoC + * + * Copyright (c) 2019, BayLibre + * Copyright (c) 2019-2020, NXP + * Author: Alexandre Bailon + * Author: Leonard Crestez + */ +#ifndef __DRIVERS_INTERCONNECT_IMX_H +#define __DRIVERS_INTERCONNECT_IMX_H + +#include + +#define IMX_ICC_MAX_LINKS 4 + +/* + * struct imx_icc_node_adj - Describe a dynamic adjustable node + */ +struct imx_icc_node_adj_desc { + unsigned int bw_mul, bw_div; + const char *phandle_name; + bool main_noc; +}; + +/* + * struct imx_icc_node - Describe an interconnect node + * @name: name of the node + * @id: an unique id to identify the node + * @links: an array of slaves' node id + * @num_links: number of id defined in links + */ +struct imx_icc_node_desc { + const char *name; + u16 id; + u16 links[IMX_ICC_MAX_LINKS]; + u16 num_links; + const struct imx_icc_node_adj_desc *adj; +}; + +#define DEFINE_BUS_INTERCONNECT(_name, _id, _adj, ...) \ + { \ + .id = _id, \ + .name = _name, \ + .adj = _adj, \ + .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \ + .links = { __VA_ARGS__ }, \ + } + +#define DEFINE_BUS_MASTER(_name, _id, _dest_id) \ + DEFINE_BUS_INTERCONNECT(_name, _id, NULL, _dest_id) + +#define DEFINE_BUS_SLAVE(_name, _id, _adj) \ + DEFINE_BUS_INTERCONNECT(_name, _id, _adj) + +int imx_icc_register(struct platform_device *pdev, + struct imx_icc_node_desc *nodes, + int nodes_count); +int imx_icc_unregister(struct platform_device *pdev); + +#endif /* __DRIVERS_INTERCONNECT_IMX_H */ diff --git a/drivers/interconnect/imx/imx8mm.c b/drivers/interconnect/imx/imx8mm.c new file mode 100644 index 000000000000..1083490bb391 --- /dev/null +++ b/drivers/interconnect/imx/imx8mm.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Interconnect framework driver for i.MX8MM SoC + * + * Copyright (c) 2019, BayLibre + * Copyright (c) 2019-2020, NXP + * Author: Alexandre Bailon + * Author: Leonard Crestez + */ + +#include +#include +#include + +#include "imx.h" + +static const struct imx_icc_node_adj_desc imx8mm_dram_adj = { + .bw_mul = 1, + .bw_div = 16, + .phandle_name = "fsl,ddrc", +}; + +static const struct imx_icc_node_adj_desc imx8mm_noc_adj = { + .bw_mul = 1, + .bw_div = 16, + .main_noc = true, +}; + +/* + * Describe bus masters, slaves and connections between them + * + * This is a simplified subset of the bus diagram, there are several other + * PL301 nics which are skipped/merged into PL301_MAIN + */ +static struct imx_icc_node_desc nodes[] = { + DEFINE_BUS_INTERCONNECT("NOC", IMX8MM_ICN_NOC, &imx8mm_noc_adj, + IMX8MM_ICS_DRAM, IMX8MM_ICN_MAIN), + + DEFINE_BUS_SLAVE("DRAM", IMX8MM_ICS_DRAM, &imx8mm_dram_adj), + DEFINE_BUS_SLAVE("OCRAM", IMX8MM_ICS_OCRAM, NULL), + DEFINE_BUS_MASTER("A53", IMX8MM_ICM_A53, IMX8MM_ICN_NOC), + + /* VPUMIX */ + DEFINE_BUS_MASTER("VPU H1", IMX8MM_ICM_VPU_H1, IMX8MM_ICN_VIDEO), + DEFINE_BUS_MASTER("VPU G1", IMX8MM_ICM_VPU_G1, IMX8MM_ICN_VIDEO), + DEFINE_BUS_MASTER("VPU G2", IMX8MM_ICM_VPU_G2, IMX8MM_ICN_VIDEO), + DEFINE_BUS_INTERCONNECT("PL301_VIDEO", IMX8MM_ICN_VIDEO, NULL, IMX8MM_ICN_NOC), + + /* GPUMIX */ + DEFINE_BUS_MASTER("GPU 2D", IMX8MM_ICM_GPU2D, IMX8MM_ICN_GPU), + DEFINE_BUS_MASTER("GPU 3D", IMX8MM_ICM_GPU3D, IMX8MM_ICN_GPU), + DEFINE_BUS_INTERCONNECT("PL301_GPU", IMX8MM_ICN_GPU, NULL, IMX8MM_ICN_NOC), + + /* DISPLAYMIX */ + DEFINE_BUS_MASTER("CSI", IMX8MM_ICM_CSI, IMX8MM_ICN_MIPI), + DEFINE_BUS_MASTER("LCDIF", IMX8MM_ICM_LCDIF, IMX8MM_ICN_MIPI), + DEFINE_BUS_INTERCONNECT("PL301_MIPI", IMX8MM_ICN_MIPI, NULL, IMX8MM_ICN_NOC), + + /* HSIO */ + DEFINE_BUS_MASTER("USB1", IMX8MM_ICM_USB1, IMX8MM_ICN_HSIO), + DEFINE_BUS_MASTER("USB2", IMX8MM_ICM_USB2, IMX8MM_ICN_HSIO), + DEFINE_BUS_MASTER("PCIE", IMX8MM_ICM_PCIE, IMX8MM_ICN_HSIO), + DEFINE_BUS_INTERCONNECT("PL301_HSIO", IMX8MM_ICN_HSIO, NULL, IMX8MM_ICN_NOC), + + /* Audio */ + DEFINE_BUS_MASTER("SDMA2", IMX8MM_ICM_SDMA2, IMX8MM_ICN_AUDIO), + DEFINE_BUS_MASTER("SDMA3", IMX8MM_ICM_SDMA3, IMX8MM_ICN_AUDIO), + DEFINE_BUS_INTERCONNECT("PL301_AUDIO", IMX8MM_ICN_AUDIO, NULL, IMX8MM_ICN_MAIN), + + /* Ethernet */ + DEFINE_BUS_MASTER("ENET", IMX8MM_ICM_ENET, IMX8MM_ICN_ENET), + DEFINE_BUS_INTERCONNECT("PL301_ENET", IMX8MM_ICN_ENET, NULL, IMX8MM_ICN_MAIN), + + /* Other */ + DEFINE_BUS_MASTER("SDMA1", IMX8MM_ICM_SDMA1, IMX8MM_ICN_MAIN), + DEFINE_BUS_MASTER("NAND", IMX8MM_ICM_NAND, IMX8MM_ICN_MAIN), + DEFINE_BUS_MASTER("USDHC1", IMX8MM_ICM_USDHC1, IMX8MM_ICN_MAIN), + DEFINE_BUS_MASTER("USDHC2", IMX8MM_ICM_USDHC2, IMX8MM_ICN_MAIN), + DEFINE_BUS_MASTER("USDHC3", IMX8MM_ICM_USDHC3, IMX8MM_ICN_MAIN), + DEFINE_BUS_INTERCONNECT("PL301_MAIN", IMX8MM_ICN_MAIN, NULL, + IMX8MM_ICN_NOC, IMX8MM_ICS_OCRAM), +}; + +static int imx8mm_icc_probe(struct platform_device *pdev) +{ + return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes)); +} + +static int imx8mm_icc_remove(struct platform_device *pdev) +{ + return imx_icc_unregister(pdev); +} + +static struct platform_driver imx8mm_icc_driver = { + .probe = imx8mm_icc_probe, + .remove = imx8mm_icc_remove, + .driver = { + .name = "imx8mm-interconnect", + }, +}; + +module_platform_driver(imx8mm_icc_driver); +MODULE_AUTHOR("Alexandre Bailon "); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:imx8mm-interconnect"); diff --git a/drivers/interconnect/imx/imx8mn.c b/drivers/interconnect/imx/imx8mn.c new file mode 100644 index 000000000000..ad97e55fd4e5 --- /dev/null +++ b/drivers/interconnect/imx/imx8mn.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Interconnect framework driver for i.MX8MN SoC + * + * Copyright (c) 2019-2020, NXP + */ + +#include +#include +#include + +#include "imx.h" + +static const struct imx_icc_node_adj_desc imx8mn_dram_adj = { + .bw_mul = 1, + .bw_div = 4, + .phandle_name = "fsl,ddrc", +}; + +static const struct imx_icc_node_adj_desc imx8mn_noc_adj = { + .bw_mul = 1, + .bw_div = 4, + .main_noc = true, +}; + +/* + * Describe bus masters, slaves and connections between them + * + * This is a simplified subset of the bus diagram, there are several other + * PL301 nics which are skipped/merged into PL301_MAIN + */ +static struct imx_icc_node_desc nodes[] = { + DEFINE_BUS_INTERCONNECT("NOC", IMX8MN_ICN_NOC, &imx8mn_noc_adj, + IMX8MN_ICS_DRAM, IMX8MN_ICN_MAIN), + + DEFINE_BUS_SLAVE("DRAM", IMX8MN_ICS_DRAM, &imx8mn_dram_adj), + DEFINE_BUS_SLAVE("OCRAM", IMX8MN_ICS_OCRAM, NULL), + DEFINE_BUS_MASTER("A53", IMX8MN_ICM_A53, IMX8MN_ICN_NOC), + + /* GPUMIX */ + DEFINE_BUS_MASTER("GPU", IMX8MN_ICM_GPU, IMX8MN_ICN_GPU), + DEFINE_BUS_INTERCONNECT("PL301_GPU", IMX8MN_ICN_GPU, NULL, IMX8MN_ICN_NOC), + + /* DISPLAYMIX */ + DEFINE_BUS_MASTER("CSI1", IMX8MN_ICM_CSI1, IMX8MN_ICN_MIPI), + DEFINE_BUS_MASTER("CSI2", IMX8MN_ICM_CSI2, IMX8MN_ICN_MIPI), + DEFINE_BUS_MASTER("ISI", IMX8MN_ICM_ISI, IMX8MN_ICN_MIPI), + DEFINE_BUS_MASTER("LCDIF", IMX8MN_ICM_LCDIF, IMX8MN_ICN_MIPI), + DEFINE_BUS_INTERCONNECT("PL301_MIPI", IMX8MN_ICN_MIPI, NULL, IMX8MN_ICN_NOC), + + /* USB goes straight to NOC */ + DEFINE_BUS_MASTER("USB", IMX8MN_ICM_USB, IMX8MN_ICN_NOC), + + /* Audio */ + DEFINE_BUS_MASTER("SDMA2", IMX8MN_ICM_SDMA2, IMX8MN_ICN_AUDIO), + DEFINE_BUS_MASTER("SDMA3", IMX8MN_ICM_SDMA3, IMX8MN_ICN_AUDIO), + DEFINE_BUS_INTERCONNECT("PL301_AUDIO", IMX8MN_ICN_AUDIO, NULL, IMX8MN_ICN_MAIN), + + /* Ethernet */ + DEFINE_BUS_MASTER("ENET", IMX8MN_ICM_ENET, IMX8MN_ICN_ENET), + DEFINE_BUS_INTERCONNECT("PL301_ENET", IMX8MN_ICN_ENET, NULL, IMX8MN_ICN_MAIN), + + /* Other */ + DEFINE_BUS_MASTER("SDMA1", IMX8MN_ICM_SDMA1, IMX8MN_ICN_MAIN), + DEFINE_BUS_MASTER("NAND", IMX8MN_ICM_NAND, IMX8MN_ICN_MAIN), + DEFINE_BUS_MASTER("USDHC1", IMX8MN_ICM_USDHC1, IMX8MN_ICN_MAIN), + DEFINE_BUS_MASTER("USDHC2", IMX8MN_ICM_USDHC2, IMX8MN_ICN_MAIN), + DEFINE_BUS_MASTER("USDHC3", IMX8MN_ICM_USDHC3, IMX8MN_ICN_MAIN), + DEFINE_BUS_INTERCONNECT("PL301_MAIN", IMX8MN_ICN_MAIN, NULL, + IMX8MN_ICN_NOC, IMX8MN_ICS_OCRAM), +}; + +static int imx8mn_icc_probe(struct platform_device *pdev) +{ + return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes)); +} + +static int imx8mn_icc_remove(struct platform_device *pdev) +{ + return imx_icc_unregister(pdev); +} + +static struct platform_driver imx8mn_icc_driver = { + .probe = imx8mn_icc_probe, + .remove = imx8mn_icc_remove, + .driver = { + .name = "imx8mn-interconnect", + }, +}; + +module_platform_driver(imx8mn_icc_driver); +MODULE_ALIAS("platform:imx8mn-interconnect"); +MODULE_AUTHOR("Leonard Crestez "); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/interconnect/imx/imx8mq.c b/drivers/interconnect/imx/imx8mq.c new file mode 100644 index 000000000000..ba43a15aefec --- /dev/null +++ b/drivers/interconnect/imx/imx8mq.c @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Interconnect framework driver for i.MX8MQ SoC + * + * Copyright (c) 2019-2020, NXP + */ + +#include +#include +#include + +#include "imx.h" + +static const struct imx_icc_node_adj_desc imx8mq_dram_adj = { + .bw_mul = 1, + .bw_div = 4, + .phandle_name = "fsl,ddrc", +}; + +static const struct imx_icc_node_adj_desc imx8mq_noc_adj = { + .bw_mul = 1, + .bw_div = 4, + .main_noc = true, +}; + +/* + * Describe bus masters, slaves and connections between them + * + * This is a simplified subset of the bus diagram, there are several other + * PL301 nics which are skipped/merged into PL301_MAIN + */ +static struct imx_icc_node_desc nodes[] = { + DEFINE_BUS_INTERCONNECT("NOC", IMX8MQ_ICN_NOC, &imx8mq_noc_adj, + IMX8MQ_ICS_DRAM, IMX8MQ_ICN_MAIN), + + DEFINE_BUS_SLAVE("DRAM", IMX8MQ_ICS_DRAM, &imx8mq_dram_adj), + DEFINE_BUS_SLAVE("OCRAM", IMX8MQ_ICS_OCRAM, NULL), + DEFINE_BUS_MASTER("A53", IMX8MQ_ICM_A53, IMX8MQ_ICN_NOC), + + /* VPUMIX */ + DEFINE_BUS_MASTER("VPU", IMX8MQ_ICM_VPU, IMX8MQ_ICN_VIDEO), + DEFINE_BUS_INTERCONNECT("PL301_VIDEO", IMX8MQ_ICN_VIDEO, NULL, IMX8MQ_ICN_NOC), + + /* GPUMIX */ + DEFINE_BUS_MASTER("GPU", IMX8MQ_ICM_GPU, IMX8MQ_ICN_GPU), + DEFINE_BUS_INTERCONNECT("PL301_GPU", IMX8MQ_ICN_GPU, NULL, IMX8MQ_ICN_NOC), + + /* DISPMIX (only for DCSS) */ + DEFINE_BUS_MASTER("DC", IMX8MQ_ICM_DCSS, IMX8MQ_ICN_DCSS), + DEFINE_BUS_INTERCONNECT("PL301_DC", IMX8MQ_ICN_DCSS, NULL, IMX8MQ_ICN_NOC), + + /* USBMIX */ + DEFINE_BUS_MASTER("USB1", IMX8MQ_ICM_USB1, IMX8MQ_ICN_USB), + DEFINE_BUS_MASTER("USB2", IMX8MQ_ICM_USB2, IMX8MQ_ICN_USB), + DEFINE_BUS_INTERCONNECT("PL301_USB", IMX8MQ_ICN_USB, NULL, IMX8MQ_ICN_NOC), + + /* PL301_DISPLAY (IPs other than DCSS, inside SUPERMIX) */ + DEFINE_BUS_MASTER("CSI1", IMX8MQ_ICM_CSI1, IMX8MQ_ICN_DISPLAY), + DEFINE_BUS_MASTER("CSI2", IMX8MQ_ICM_CSI2, IMX8MQ_ICN_DISPLAY), + DEFINE_BUS_MASTER("LCDIF", IMX8MQ_ICM_LCDIF, IMX8MQ_ICN_DISPLAY), + DEFINE_BUS_INTERCONNECT("PL301_DISPLAY", IMX8MQ_ICN_DISPLAY, NULL, IMX8MQ_ICN_MAIN), + + /* AUDIO */ + DEFINE_BUS_MASTER("SDMA2", IMX8MQ_ICM_SDMA2, IMX8MQ_ICN_AUDIO), + DEFINE_BUS_INTERCONNECT("PL301_AUDIO", IMX8MQ_ICN_AUDIO, NULL, IMX8MQ_ICN_DISPLAY), + + /* ENET */ + DEFINE_BUS_MASTER("ENET", IMX8MQ_ICM_ENET, IMX8MQ_ICN_ENET), + DEFINE_BUS_INTERCONNECT("PL301_ENET", IMX8MQ_ICN_ENET, NULL, IMX8MQ_ICN_MAIN), + + /* OTHER */ + DEFINE_BUS_MASTER("SDMA1", IMX8MQ_ICM_SDMA1, IMX8MQ_ICN_MAIN), + DEFINE_BUS_MASTER("NAND", IMX8MQ_ICM_NAND, IMX8MQ_ICN_MAIN), + DEFINE_BUS_MASTER("USDHC1", IMX8MQ_ICM_USDHC1, IMX8MQ_ICN_MAIN), + DEFINE_BUS_MASTER("USDHC2", IMX8MQ_ICM_USDHC2, IMX8MQ_ICN_MAIN), + DEFINE_BUS_MASTER("PCIE1", IMX8MQ_ICM_PCIE1, IMX8MQ_ICN_MAIN), + DEFINE_BUS_MASTER("PCIE2", IMX8MQ_ICM_PCIE2, IMX8MQ_ICN_MAIN), + DEFINE_BUS_INTERCONNECT("PL301_MAIN", IMX8MQ_ICN_MAIN, NULL, + IMX8MQ_ICN_NOC, IMX8MQ_ICS_OCRAM), +}; + +static int imx8mq_icc_probe(struct platform_device *pdev) +{ + return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes)); +} + +static int imx8mq_icc_remove(struct platform_device *pdev) +{ + return imx_icc_unregister(pdev); +} + +static struct platform_driver imx8mq_icc_driver = { + .probe = imx8mq_icc_probe, + .remove = imx8mq_icc_remove, + .driver = { + .name = "imx8mq-interconnect", + }, +}; + +module_platform_driver(imx8mq_icc_driver); +MODULE_ALIAS("platform:imx8mq-interconnect"); +MODULE_AUTHOR("Leonard Crestez "); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/interconnect/internal.h b/drivers/interconnect/internal.h index bf18cb7239df..f5f82a5c939e 100644 --- a/drivers/interconnect/internal.h +++ b/drivers/interconnect/internal.h @@ -14,6 +14,7 @@ * @req_node: entry in list of requests for the particular @node * @node: the interconnect node to which this constraint applies * @dev: reference to the device that sets the constraints + * @enabled: indicates whether the path with this request is enabled * @tag: path tag (optional) * @avg_bw: an integer describing the average bandwidth in kBps * @peak_bw: an integer describing the peak bandwidth in kBps @@ -22,6 +23,7 @@ struct icc_req { struct hlist_node req_node; struct icc_node *node; struct device *dev; + bool enabled; u32 tag; u32 avg_bw; u32 peak_bw; diff --git a/drivers/misc/cardreader/rts5249.c b/drivers/misc/cardreader/rts5249.c index 1a81cda948c1..6c6c9e95a29f 100644 --- a/drivers/misc/cardreader/rts5249.c +++ b/drivers/misc/cardreader/rts5249.c @@ -347,31 +347,6 @@ static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) return rtsx_pci_send_cmd(pcr, 100); } -static void rts5249_set_aspm(struct rtsx_pcr *pcr, bool enable) -{ - struct rtsx_cr_option *option = &pcr->option; - u8 val = 0; - - if (pcr->aspm_enabled == enable) - return; - - if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) { - if (enable) - val = pcr->aspm_en; - rtsx_pci_update_cfg_byte(pcr, - pcr->pcie_cap + PCI_EXP_LNKCTL, - ASPM_MASK_NEG, val); - } else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) { - u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0; - - if (!enable) - val = FORCE_ASPM_CTL0; - rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); - } - - pcr->aspm_enabled = enable; -} - static const struct pcr_ops rts5249_pcr_ops = { .fetch_vendor_settings = rtsx_base_fetch_vendor_settings, .extra_init_hw = rts5249_extra_init_hw, @@ -384,7 +359,6 @@ static const struct pcr_ops rts5249_pcr_ops = { .card_power_off = rtsx_base_card_power_off, .switch_output_voltage = rtsx_base_switch_output_voltage, .force_power_down = rtsx_base_force_power_down, - .set_aspm = rts5249_set_aspm, }; /* SD Pull Control Enable: @@ -471,7 +445,6 @@ void rts5249_init_params(struct rtsx_pcr *pcr) option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF; option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF; option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF; - option->dev_aspm_mode = DEV_ASPM_DYNAMIC; option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF; option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5249_DEF; option->ltr_l1off_snooze_sspwrgate = @@ -612,7 +585,6 @@ static const struct pcr_ops rts524a_pcr_ops = { .switch_output_voltage = rtsx_base_switch_output_voltage, .force_power_down = rtsx_base_force_power_down, .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0, - .set_aspm = rts5249_set_aspm, }; void rts524a_init_params(struct rtsx_pcr *pcr) @@ -728,7 +700,6 @@ static const struct pcr_ops rts525a_pcr_ops = { .switch_output_voltage = rts525a_switch_output_voltage, .force_power_down = rtsx_base_force_power_down, .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0, - .set_aspm = rts5249_set_aspm, }; void rts525a_init_params(struct rtsx_pcr *pcr) diff --git a/drivers/misc/cardreader/rts5260.c b/drivers/misc/cardreader/rts5260.c index 711054ebad74..7a9dbb778e84 100644 --- a/drivers/misc/cardreader/rts5260.c +++ b/drivers/misc/cardreader/rts5260.c @@ -570,30 +570,6 @@ static int rts5260_extra_init_hw(struct rtsx_pcr *pcr) return 0; } -static void rts5260_set_aspm(struct rtsx_pcr *pcr, bool enable) -{ - struct rtsx_cr_option *option = &pcr->option; - u8 val = 0; - - if (pcr->aspm_enabled == enable) - return; - - if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) { - if (enable) - val = pcr->aspm_en; - rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL, - ASPM_MASK_NEG, val); - } else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) { - u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0; - - if (!enable) - val = FORCE_ASPM_CTL0; - rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); - } - - pcr->aspm_enabled = enable; -} - static void rts5260_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active) { struct rtsx_cr_option *option = &pcr->option; @@ -639,7 +615,6 @@ static const struct pcr_ops rts5260_pcr_ops = { .switch_output_voltage = rts5260_switch_output_voltage, .force_power_down = rtsx_base_force_power_down, .stop_cmd = rts5260_stop_cmd, - .set_aspm = rts5260_set_aspm, .set_l1off_cfg_sub_d0 = rts5260_set_l1off_cfg_sub_d0, .enable_ocp = rts5260_enable_ocp, .disable_ocp = rts5260_disable_ocp, @@ -683,7 +658,6 @@ void rts5260_init_params(struct rtsx_pcr *pcr) option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF; option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF; option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF; - option->dev_aspm_mode = DEV_ASPM_DYNAMIC; option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF; option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF; option->ltr_l1off_snooze_sspwrgate = diff --git a/drivers/misc/cardreader/rts5261.c b/drivers/misc/cardreader/rts5261.c index 78c3b1d424c3..195822ec858e 100644 --- a/drivers/misc/cardreader/rts5261.c +++ b/drivers/misc/cardreader/rts5261.c @@ -518,51 +518,22 @@ static int rts5261_extra_init_hw(struct rtsx_pcr *pcr) static void rts5261_enable_aspm(struct rtsx_pcr *pcr, bool enable) { - struct rtsx_cr_option *option = &pcr->option; - u8 val = 0; - if (pcr->aspm_enabled == enable) return; - if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) { - val = pcr->aspm_en; - rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL, - ASPM_MASK_NEG, val); - } else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) { - u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0; - - val = FORCE_ASPM_CTL0; - val |= (pcr->aspm_en & 0x02); - rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); - val = pcr->aspm_en; - rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL, - ASPM_MASK_NEG, val); - } + pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en); pcr->aspm_enabled = enable; } static void rts5261_disable_aspm(struct rtsx_pcr *pcr, bool enable) { - struct rtsx_cr_option *option = &pcr->option; - u8 val = 0; - if (pcr->aspm_enabled == enable) return; - if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) { - val = 0; - rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL, - ASPM_MASK_NEG, val); - } else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) { - u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0; - - val = 0; - rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL, - ASPM_MASK_NEG, val); - val = FORCE_ASPM_CTL0; - rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); - } + pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_ASPMC, 0); rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); udelay(10); pcr->aspm_enabled = enable; @@ -639,8 +610,13 @@ int rts5261_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, if (initial_mode) { /* We use 250k(around) here, in initial stage */ - clk_divider = SD_CLK_DIVIDE_128; - card_clock = 30000000; + if (is_version(pcr, PID_5261, IC_VER_D)) { + clk_divider = SD_CLK_DIVIDE_256; + card_clock = 60000000; + } else { + clk_divider = SD_CLK_DIVIDE_128; + card_clock = 30000000; + } } else { clk_divider = SD_CLK_DIVIDE_0; } @@ -784,7 +760,6 @@ void rts5261_init_params(struct rtsx_pcr *pcr) option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF; option->ltr_l1off_sspwrgate = 0x7F; option->ltr_l1off_snooze_sspwrgate = 0x78; - option->dev_aspm_mode = DEV_ASPM_DYNAMIC; option->ocp_en = 1; hw_param->interrupt_en |= SD_OC_INT_EN; diff --git a/drivers/misc/cardreader/rtsx_pcr.c b/drivers/misc/cardreader/rtsx_pcr.c index 55da6428ceb0..0d5928bc1b6d 100644 --- a/drivers/misc/cardreader/rtsx_pcr.c +++ b/drivers/misc/cardreader/rtsx_pcr.c @@ -55,16 +55,10 @@ static const struct pci_device_id rtsx_pci_ids[] = { MODULE_DEVICE_TABLE(pci, rtsx_pci_ids); -static inline void rtsx_pci_enable_aspm(struct rtsx_pcr *pcr) -{ - rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL, - 0xFC, pcr->aspm_en); -} - static inline void rtsx_pci_disable_aspm(struct rtsx_pcr *pcr) { - rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL, - 0xFC, 0); + pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_ASPMC, 0); } static int rtsx_comm_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency) @@ -85,32 +79,17 @@ static int rtsx_comm_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency) int rtsx_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency) { - if (pcr->ops->set_ltr_latency) - return pcr->ops->set_ltr_latency(pcr, latency); - else - return rtsx_comm_set_ltr_latency(pcr, latency); + return rtsx_comm_set_ltr_latency(pcr, latency); } static void rtsx_comm_set_aspm(struct rtsx_pcr *pcr, bool enable) { - struct rtsx_cr_option *option = &pcr->option; - if (pcr->aspm_enabled == enable) return; - if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) { - if (enable) - rtsx_pci_enable_aspm(pcr); - else - rtsx_pci_disable_aspm(pcr); - } else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) { - u8 mask = FORCE_ASPM_VAL_MASK; - u8 val = 0; - - if (enable) - val = pcr->aspm_en; - rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); - } + pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_ASPMC, + enable ? pcr->aspm_en : 0); pcr->aspm_enabled = enable; } @@ -154,10 +133,7 @@ static void rtsx_comm_pm_full_on(struct rtsx_pcr *pcr) static void rtsx_pm_full_on(struct rtsx_pcr *pcr) { - if (pcr->ops->full_on) - pcr->ops->full_on(pcr); - else - rtsx_comm_pm_full_on(pcr); + rtsx_comm_pm_full_on(pcr); } void rtsx_pci_start_run(struct rtsx_pcr *pcr) @@ -1111,10 +1087,7 @@ static void rtsx_comm_pm_power_saving(struct rtsx_pcr *pcr) static void rtsx_pm_power_saving(struct rtsx_pcr *pcr) { - if (pcr->ops->power_saving) - pcr->ops->power_saving(pcr); - else - rtsx_comm_pm_power_saving(pcr); + rtsx_comm_pm_power_saving(pcr); } static void rtsx_pci_idle_work(struct work_struct *work) diff --git a/drivers/misc/cardreader/rtsx_pcr.h b/drivers/misc/cardreader/rtsx_pcr.h index ed391df52f4f..024cbd998b2a 100644 --- a/drivers/misc/cardreader/rtsx_pcr.h +++ b/drivers/misc/cardreader/rtsx_pcr.h @@ -29,7 +29,6 @@ #define LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF 0xAC #define LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF 0xF8 #define CMD_TIMEOUT_DEF 100 -#define ASPM_MASK_NEG 0xFC #define MASK_8_BIT_DEF 0xFF #define SSC_CLOCK_STABLE_WAIT 130 diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c index e3e085e33d46..7939c55daceb 100644 --- a/drivers/misc/fastrpc.c +++ b/drivers/misc/fastrpc.c @@ -904,6 +904,7 @@ static int fastrpc_invoke_send(struct fastrpc_session_ctx *sctx, struct fastrpc_channel_ctx *cctx; struct fastrpc_user *fl = ctx->fl; struct fastrpc_msg *msg = &ctx->msg; + int ret; cctx = fl->cctx; msg->pid = fl->tgid; @@ -919,7 +920,13 @@ static int fastrpc_invoke_send(struct fastrpc_session_ctx *sctx, msg->size = roundup(ctx->msg_sz, PAGE_SIZE); fastrpc_context_get(ctx); - return rpmsg_send(cctx->rpdev->ept, (void *)msg, sizeof(*msg)); + ret = rpmsg_send(cctx->rpdev->ept, (void *)msg, sizeof(*msg)); + + if (ret) + fastrpc_context_put(ctx); + + return ret; + } static int fastrpc_internal_invoke(struct fastrpc_user *fl, u32 kernel, @@ -1613,8 +1620,10 @@ static int fastrpc_rpmsg_probe(struct rpmsg_device *rpdev) domains[domain_id]); data->miscdev.fops = &fastrpc_fops; err = misc_register(&data->miscdev); - if (err) + if (err) { + kfree(data); return err; + } kref_init(&data->refcount); diff --git a/drivers/misc/genwqe/card_utils.c b/drivers/misc/genwqe/card_utils.c index 2e1c4d2905e8..60460a053b2d 100644 --- a/drivers/misc/genwqe/card_utils.c +++ b/drivers/misc/genwqe/card_utils.c @@ -514,30 +514,6 @@ int genwqe_free_sync_sgl(struct genwqe_dev *cd, struct genwqe_sgl *sgl) return rc; } -/** - * genwqe_free_user_pages() - Give pinned pages back - * - * Documentation of get_user_pages is in mm/gup.c: - * - * If the page is written to, set_page_dirty (or set_page_dirty_lock, - * as appropriate) must be called after the page is finished with, and - * before put_page is called. - */ -static int genwqe_free_user_pages(struct page **page_list, - unsigned int nr_pages, int dirty) -{ - unsigned int i; - - for (i = 0; i < nr_pages; i++) { - if (page_list[i] != NULL) { - if (dirty) - set_page_dirty_lock(page_list[i]); - put_page(page_list[i]); - } - } - return 0; -} - /** * genwqe_user_vmap() - Map user-space memory to virtual kernel memory * @cd: pointer to genwqe device @@ -597,18 +573,18 @@ int genwqe_user_vmap(struct genwqe_dev *cd, struct dma_mapping *m, void *uaddr, m->dma_list = (dma_addr_t *)(m->page_list + m->nr_pages); /* pin user pages in memory */ - rc = get_user_pages_fast(data & PAGE_MASK, /* page aligned addr */ + rc = pin_user_pages_fast(data & PAGE_MASK, /* page aligned addr */ m->nr_pages, m->write ? FOLL_WRITE : 0, /* readable/writable */ m->page_list); /* ptrs to pages */ if (rc < 0) - goto fail_get_user_pages; + goto fail_pin_user_pages; - /* assumption: get_user_pages can be killed by signals. */ + /* assumption: pin_user_pages can be killed by signals. */ if (rc < m->nr_pages) { - genwqe_free_user_pages(m->page_list, rc, m->write); + unpin_user_pages_dirty_lock(m->page_list, rc, m->write); rc = -EFAULT; - goto fail_get_user_pages; + goto fail_pin_user_pages; } rc = genwqe_map_pages(cd, m->page_list, m->nr_pages, m->dma_list); @@ -618,9 +594,9 @@ int genwqe_user_vmap(struct genwqe_dev *cd, struct dma_mapping *m, void *uaddr, return 0; fail_free_user_pages: - genwqe_free_user_pages(m->page_list, m->nr_pages, m->write); + unpin_user_pages_dirty_lock(m->page_list, m->nr_pages, m->write); - fail_get_user_pages: + fail_pin_user_pages: kfree(m->page_list); m->page_list = NULL; m->dma_list = NULL; @@ -650,8 +626,8 @@ int genwqe_user_vunmap(struct genwqe_dev *cd, struct dma_mapping *m) genwqe_unmap_pages(cd, m->dma_list, m->nr_pages); if (m->page_list) { - genwqe_free_user_pages(m->page_list, m->nr_pages, m->write); - + unpin_user_pages_dirty_lock(m->page_list, m->nr_pages, + m->write); kfree(m->page_list); m->page_list = NULL; m->dma_list = NULL; diff --git a/drivers/misc/habanalabs/Makefile b/drivers/misc/habanalabs/Makefile index 482f6227dbba..421ebd903069 100644 --- a/drivers/misc/habanalabs/Makefile +++ b/drivers/misc/habanalabs/Makefile @@ -13,3 +13,6 @@ habanalabs-$(CONFIG_DEBUG_FS) += debugfs.o include $(src)/goya/Makefile habanalabs-y += $(HL_GOYA_FILES) + +include $(src)/gaudi/Makefile +habanalabs-y += $(HL_GAUDI_FILES) diff --git a/drivers/misc/habanalabs/command_buffer.c b/drivers/misc/habanalabs/command_buffer.c index 53fddbd8e693..02d13f71b1df 100644 --- a/drivers/misc/habanalabs/command_buffer.c +++ b/drivers/misc/habanalabs/command_buffer.c @@ -105,10 +105,9 @@ int hl_cb_create(struct hl_device *hdev, struct hl_cb_mgr *mgr, goto out_err; } - if (cb_size > HL_MAX_CB_SIZE) { - dev_err(hdev->dev, - "CB size %d must be less then %d\n", - cb_size, HL_MAX_CB_SIZE); + if (cb_size > SZ_2M) { + dev_err(hdev->dev, "CB size %d must be less than %d\n", + cb_size, SZ_2M); rc = -EINVAL; goto out_err; } @@ -211,7 +210,7 @@ int hl_cb_ioctl(struct hl_fpriv *hpriv, void *data) { union hl_cb_args *args = data; struct hl_device *hdev = hpriv->hdev; - u64 handle; + u64 handle = 0; int rc; if (hl_device_disabled_or_in_reset(hdev)) { @@ -223,15 +222,26 @@ int hl_cb_ioctl(struct hl_fpriv *hpriv, void *data) switch (args->in.op) { case HL_CB_OP_CREATE: - rc = hl_cb_create(hdev, &hpriv->cb_mgr, args->in.cb_size, - &handle, hpriv->ctx->asid); + if (args->in.cb_size > HL_MAX_CB_SIZE) { + dev_err(hdev->dev, + "User requested CB size %d must be less than %d\n", + args->in.cb_size, HL_MAX_CB_SIZE); + rc = -EINVAL; + } else { + rc = hl_cb_create(hdev, &hpriv->cb_mgr, + args->in.cb_size, &handle, + hpriv->ctx->asid); + } + memset(args, 0, sizeof(*args)); args->out.cb_handle = handle; break; + case HL_CB_OP_DESTROY: rc = hl_cb_destroy(hdev, &hpriv->cb_mgr, args->in.cb_handle); break; + default: rc = -ENOTTY; break; @@ -278,7 +288,7 @@ int hl_cb_mmap(struct hl_fpriv *hpriv, struct vm_area_struct *vma) cb = hl_cb_get(hdev, &hpriv->cb_mgr, handle); if (!cb) { dev_err(hdev->dev, - "CB mmap failed, no match to handle %d\n", handle); + "CB mmap failed, no match to handle 0x%x\n", handle); return -EINVAL; } @@ -347,7 +357,7 @@ struct hl_cb *hl_cb_get(struct hl_device *hdev, struct hl_cb_mgr *mgr, if (!cb) { spin_unlock(&mgr->cb_lock); dev_warn(hdev->dev, - "CB get failed, no match to handle %d\n", handle); + "CB get failed, no match to handle 0x%x\n", handle); return NULL; } diff --git a/drivers/misc/habanalabs/command_submission.c b/drivers/misc/habanalabs/command_submission.c index 409276b6374d..f82974a916c3 100644 --- a/drivers/misc/habanalabs/command_submission.c +++ b/drivers/misc/habanalabs/command_submission.c @@ -11,11 +11,33 @@ #include #include +#define HL_CS_FLAGS_SIG_WAIT (HL_CS_FLAGS_SIGNAL | HL_CS_FLAGS_WAIT) + static void job_wq_completion(struct work_struct *work); static long _hl_cs_wait_ioctl(struct hl_device *hdev, struct hl_ctx *ctx, u64 timeout_us, u64 seq); static void cs_do_release(struct kref *ref); +static void hl_sob_reset(struct kref *ref) +{ + struct hl_hw_sob *hw_sob = container_of(ref, struct hl_hw_sob, + kref); + struct hl_device *hdev = hw_sob->hdev; + + hdev->asic_funcs->reset_sob(hdev, hw_sob); +} + +void hl_sob_reset_error(struct kref *ref) +{ + struct hl_hw_sob *hw_sob = container_of(ref, struct hl_hw_sob, + kref); + struct hl_device *hdev = hw_sob->hdev; + + dev_crit(hdev->dev, + "SOB release shouldn't be called here, q_idx: %d, sob_id: %d\n", + hw_sob->q_idx, hw_sob->sob_id); +} + static const char *hl_fence_get_driver_name(struct dma_fence *fence) { return "HabanaLabs"; @@ -23,10 +45,10 @@ static const char *hl_fence_get_driver_name(struct dma_fence *fence) static const char *hl_fence_get_timeline_name(struct dma_fence *fence) { - struct hl_dma_fence *hl_fence = - container_of(fence, struct hl_dma_fence, base_fence); + struct hl_cs_compl *hl_cs_compl = + container_of(fence, struct hl_cs_compl, base_fence); - return dev_name(hl_fence->hdev->dev); + return dev_name(hl_cs_compl->hdev->dev); } static bool hl_fence_enable_signaling(struct dma_fence *fence) @@ -36,17 +58,47 @@ static bool hl_fence_enable_signaling(struct dma_fence *fence) static void hl_fence_release(struct dma_fence *fence) { - struct hl_dma_fence *hl_fence = - container_of(fence, struct hl_dma_fence, base_fence); + struct hl_cs_compl *hl_cs_cmpl = + container_of(fence, struct hl_cs_compl, base_fence); + struct hl_device *hdev = hl_cs_cmpl->hdev; - kfree_rcu(hl_fence, base_fence.rcu); + if ((hl_cs_cmpl->type == CS_TYPE_SIGNAL) || + (hl_cs_cmpl->type == CS_TYPE_WAIT)) { + + dev_dbg(hdev->dev, + "CS 0x%llx type %d finished, sob_id: %d, sob_val: 0x%x\n", + hl_cs_cmpl->cs_seq, + hl_cs_cmpl->type, + hl_cs_cmpl->hw_sob->sob_id, + hl_cs_cmpl->sob_val); + + /* + * A signal CS can get completion while the corresponding wait + * for signal CS is on its way to the PQ. The wait for signal CS + * will get stuck if the signal CS incremented the SOB to its + * max value and there are no pending (submitted) waits on this + * SOB. + * We do the following to void this situation: + * 1. The wait for signal CS must get a ref for the signal CS as + * soon as possible in cs_ioctl_signal_wait() and put it + * before being submitted to the PQ but after it incremented + * the SOB refcnt in init_signal_wait_cs(). + * 2. Signal/Wait for signal CS will decrement the SOB refcnt + * here. + * These two measures guarantee that the wait for signal CS will + * reset the SOB upon completion rather than the signal CS and + * hence the above scenario is avoided. + */ + kref_put(&hl_cs_cmpl->hw_sob->kref, hl_sob_reset); + } + + kfree_rcu(hl_cs_cmpl, base_fence.rcu); } static const struct dma_fence_ops hl_fence_ops = { .get_driver_name = hl_fence_get_driver_name, .get_timeline_name = hl_fence_get_timeline_name, .enable_signaling = hl_fence_enable_signaling, - .wait = dma_fence_default_wait, .release = hl_fence_release }; @@ -113,6 +165,7 @@ static int cs_parser(struct hl_fpriv *hpriv, struct hl_cs_job *job) if (!rc) { job->patched_cb = parser.patched_cb; job->job_cb_size = parser.patched_cb_size; + job->contains_dma_pkt = parser.contains_dma_pkt; spin_lock(&job->patched_cb->lock); job->patched_cb->cs_cnt++; @@ -259,6 +312,12 @@ static void cs_do_release(struct kref *ref) spin_unlock(&hdev->hw_queues_mirror_lock); } + } else if (cs->type == CS_TYPE_WAIT) { + /* + * In case the wait for signal CS was submitted, the put occurs + * in init_signal_wait_cs() right before hanging on the PQ. + */ + dma_fence_put(cs->signal_fence); } /* @@ -312,9 +371,9 @@ static void cs_timedout(struct work_struct *work) } static int allocate_cs(struct hl_device *hdev, struct hl_ctx *ctx, - struct hl_cs **cs_new) + enum hl_cs_type cs_type, struct hl_cs **cs_new) { - struct hl_dma_fence *fence; + struct hl_cs_compl *cs_cmpl; struct dma_fence *other = NULL; struct hl_cs *cs; int rc; @@ -326,25 +385,27 @@ static int allocate_cs(struct hl_device *hdev, struct hl_ctx *ctx, cs->ctx = ctx; cs->submitted = false; cs->completed = false; + cs->type = cs_type; INIT_LIST_HEAD(&cs->job_list); INIT_DELAYED_WORK(&cs->work_tdr, cs_timedout); kref_init(&cs->refcount); spin_lock_init(&cs->job_lock); - fence = kmalloc(sizeof(*fence), GFP_ATOMIC); - if (!fence) { + cs_cmpl = kmalloc(sizeof(*cs_cmpl), GFP_ATOMIC); + if (!cs_cmpl) { rc = -ENOMEM; goto free_cs; } - fence->hdev = hdev; - spin_lock_init(&fence->lock); - cs->fence = &fence->base_fence; + cs_cmpl->hdev = hdev; + cs_cmpl->type = cs->type; + spin_lock_init(&cs_cmpl->lock); + cs->fence = &cs_cmpl->base_fence; spin_lock(&ctx->cs_lock); - fence->cs_seq = ctx->cs_sequence; - other = ctx->cs_pending[fence->cs_seq & (HL_MAX_PENDING_CS - 1)]; + cs_cmpl->cs_seq = ctx->cs_sequence; + other = ctx->cs_pending[cs_cmpl->cs_seq & (HL_MAX_PENDING_CS - 1)]; if ((other) && (!dma_fence_is_signaled(other))) { spin_unlock(&ctx->cs_lock); dev_dbg(hdev->dev, @@ -353,16 +414,16 @@ static int allocate_cs(struct hl_device *hdev, struct hl_ctx *ctx, goto free_fence; } - dma_fence_init(&fence->base_fence, &hl_fence_ops, &fence->lock, + dma_fence_init(&cs_cmpl->base_fence, &hl_fence_ops, &cs_cmpl->lock, ctx->asid, ctx->cs_sequence); - cs->sequence = fence->cs_seq; + cs->sequence = cs_cmpl->cs_seq; - ctx->cs_pending[fence->cs_seq & (HL_MAX_PENDING_CS - 1)] = - &fence->base_fence; + ctx->cs_pending[cs_cmpl->cs_seq & (HL_MAX_PENDING_CS - 1)] = + &cs_cmpl->base_fence; ctx->cs_sequence++; - dma_fence_get(&fence->base_fence); + dma_fence_get(&cs_cmpl->base_fence); dma_fence_put(other); @@ -373,7 +434,7 @@ static int allocate_cs(struct hl_device *hdev, struct hl_ctx *ctx, return 0; free_fence: - kfree(fence); + kfree(cs_cmpl); free_cs: kfree(cs); return rc; @@ -499,8 +560,8 @@ struct hl_cs_job *hl_cs_allocate_job(struct hl_device *hdev, return job; } -static int _hl_cs_ioctl(struct hl_fpriv *hpriv, void __user *chunks, - u32 num_chunks, u64 *cs_seq) +static int cs_ioctl_default(struct hl_fpriv *hpriv, void __user *chunks, + u32 num_chunks, u64 *cs_seq) { struct hl_device *hdev = hpriv->hdev; struct hl_cs_chunk *cs_chunk_array; @@ -538,7 +599,7 @@ static int _hl_cs_ioctl(struct hl_fpriv *hpriv, void __user *chunks, /* increment refcnt for context */ hl_ctx_get(hdev, hpriv->ctx); - rc = allocate_cs(hdev, hpriv->ctx, &cs); + rc = allocate_cs(hdev, hpriv->ctx, CS_TYPE_DEFAULT, &cs); if (rc) { hl_ctx_put(hpriv->ctx); goto free_cs_chunk_array; @@ -652,13 +713,230 @@ out: return rc; } +static int cs_ioctl_signal_wait(struct hl_fpriv *hpriv, enum hl_cs_type cs_type, + void __user *chunks, u32 num_chunks, + u64 *cs_seq) +{ + struct hl_device *hdev = hpriv->hdev; + struct hl_ctx *ctx = hpriv->ctx; + struct hl_cs_chunk *cs_chunk_array, *chunk; + struct hw_queue_properties *hw_queue_prop; + struct dma_fence *sig_fence = NULL; + struct hl_cs_job *job; + struct hl_cs *cs; + struct hl_cb *cb; + u64 *signal_seq_arr = NULL, signal_seq; + u32 size_to_copy, q_idx, signal_seq_arr_len, cb_size; + int rc; + + *cs_seq = ULLONG_MAX; + + if (num_chunks > HL_MAX_JOBS_PER_CS) { + dev_err(hdev->dev, + "Number of chunks can NOT be larger than %d\n", + HL_MAX_JOBS_PER_CS); + rc = -EINVAL; + goto out; + } + + cs_chunk_array = kmalloc_array(num_chunks, sizeof(*cs_chunk_array), + GFP_ATOMIC); + if (!cs_chunk_array) { + rc = -ENOMEM; + goto out; + } + + size_to_copy = num_chunks * sizeof(struct hl_cs_chunk); + if (copy_from_user(cs_chunk_array, chunks, size_to_copy)) { + dev_err(hdev->dev, "Failed to copy cs chunk array from user\n"); + rc = -EFAULT; + goto free_cs_chunk_array; + } + + /* currently it is guaranteed to have only one chunk */ + chunk = &cs_chunk_array[0]; + q_idx = chunk->queue_index; + hw_queue_prop = &hdev->asic_prop.hw_queues_props[q_idx]; + + if ((q_idx >= HL_MAX_QUEUES) || + (hw_queue_prop->type != QUEUE_TYPE_EXT)) { + dev_err(hdev->dev, "Queue index %d is invalid\n", q_idx); + rc = -EINVAL; + goto free_cs_chunk_array; + } + + if (cs_type == CS_TYPE_WAIT) { + struct hl_cs_compl *sig_waitcs_cmpl; + + signal_seq_arr_len = chunk->num_signal_seq_arr; + + /* currently only one signal seq is supported */ + if (signal_seq_arr_len != 1) { + dev_err(hdev->dev, + "Wait for signal CS supports only one signal CS seq\n"); + rc = -EINVAL; + goto free_cs_chunk_array; + } + + signal_seq_arr = kmalloc_array(signal_seq_arr_len, + sizeof(*signal_seq_arr), + GFP_ATOMIC); + if (!signal_seq_arr) { + rc = -ENOMEM; + goto free_cs_chunk_array; + } + + size_to_copy = chunk->num_signal_seq_arr * + sizeof(*signal_seq_arr); + if (copy_from_user(signal_seq_arr, + u64_to_user_ptr(chunk->signal_seq_arr), + size_to_copy)) { + dev_err(hdev->dev, + "Failed to copy signal seq array from user\n"); + rc = -EFAULT; + goto free_signal_seq_array; + } + + /* currently it is guaranteed to have only one signal seq */ + signal_seq = signal_seq_arr[0]; + sig_fence = hl_ctx_get_fence(ctx, signal_seq); + if (IS_ERR(sig_fence)) { + dev_err(hdev->dev, + "Failed to get signal CS with seq 0x%llx\n", + signal_seq); + rc = PTR_ERR(sig_fence); + goto free_signal_seq_array; + } + + if (!sig_fence) { + /* signal CS already finished */ + rc = 0; + goto free_signal_seq_array; + } + + sig_waitcs_cmpl = + container_of(sig_fence, struct hl_cs_compl, base_fence); + + if (sig_waitcs_cmpl->type != CS_TYPE_SIGNAL) { + dev_err(hdev->dev, + "CS seq 0x%llx is not of a signal CS\n", + signal_seq); + dma_fence_put(sig_fence); + rc = -EINVAL; + goto free_signal_seq_array; + } + + if (dma_fence_is_signaled(sig_fence)) { + /* signal CS already finished */ + dma_fence_put(sig_fence); + rc = 0; + goto free_signal_seq_array; + } + } + + /* increment refcnt for context */ + hl_ctx_get(hdev, ctx); + + rc = allocate_cs(hdev, ctx, cs_type, &cs); + if (rc) { + if (cs_type == CS_TYPE_WAIT) + dma_fence_put(sig_fence); + hl_ctx_put(ctx); + goto free_signal_seq_array; + } + + /* + * Save the signal CS fence for later initialization right before + * hanging the wait CS on the queue. + */ + if (cs->type == CS_TYPE_WAIT) + cs->signal_fence = sig_fence; + + hl_debugfs_add_cs(cs); + + *cs_seq = cs->sequence; + + job = hl_cs_allocate_job(hdev, QUEUE_TYPE_EXT, true); + if (!job) { + dev_err(hdev->dev, "Failed to allocate a new job\n"); + rc = -ENOMEM; + goto put_cs; + } + + cb = hl_cb_kernel_create(hdev, PAGE_SIZE); + if (!cb) { + kfree(job); + rc = -EFAULT; + goto put_cs; + } + + if (cs->type == CS_TYPE_WAIT) + cb_size = hdev->asic_funcs->get_wait_cb_size(hdev); + else + cb_size = hdev->asic_funcs->get_signal_cb_size(hdev); + + job->id = 0; + job->cs = cs; + job->user_cb = cb; + job->user_cb->cs_cnt++; + job->user_cb_size = cb_size; + job->hw_queue_id = q_idx; + + /* + * No need in parsing, user CB is the patched CB. + * We call hl_cb_destroy() out of two reasons - we don't need the CB in + * the CB idr anymore and to decrement its refcount as it was + * incremented inside hl_cb_kernel_create(). + */ + job->patched_cb = job->user_cb; + job->job_cb_size = job->user_cb_size; + hl_cb_destroy(hdev, &hdev->kernel_cb_mgr, cb->id << PAGE_SHIFT); + + cs->jobs_in_queue_cnt[job->hw_queue_id]++; + + list_add_tail(&job->cs_node, &cs->job_list); + + /* increment refcount as for external queues we get completion */ + cs_get(cs); + + hl_debugfs_add_job(hdev, job); + + rc = hl_hw_queue_schedule_cs(cs); + if (rc) { + if (rc != -EAGAIN) + dev_err(hdev->dev, + "Failed to submit CS %d.%llu to H/W queues, error %d\n", + ctx->asid, cs->sequence, rc); + goto free_cs_object; + } + + rc = HL_CS_STATUS_SUCCESS; + goto put_cs; + +free_cs_object: + cs_rollback(hdev, cs); + *cs_seq = ULLONG_MAX; + /* The path below is both for good and erroneous exits */ +put_cs: + /* We finished with the CS in this function, so put the ref */ + cs_put(cs); +free_signal_seq_array: + if (cs_type == CS_TYPE_WAIT) + kfree(signal_seq_arr); +free_cs_chunk_array: + kfree(cs_chunk_array); +out: + return rc; +} + int hl_cs_ioctl(struct hl_fpriv *hpriv, void *data) { struct hl_device *hdev = hpriv->hdev; union hl_cs_args *args = data; struct hl_ctx *ctx = hpriv->ctx; void __user *chunks_execute, *chunks_restore; - u32 num_chunks_execute, num_chunks_restore; + enum hl_cs_type cs_type; + u32 num_chunks_execute, num_chunks_restore, sig_wait_flags; u64 cs_seq = ULONG_MAX; int rc, do_ctx_switch; bool need_soft_reset = false; @@ -671,12 +949,44 @@ int hl_cs_ioctl(struct hl_fpriv *hpriv, void *data) goto out; } + sig_wait_flags = args->in.cs_flags & HL_CS_FLAGS_SIG_WAIT; + + if (unlikely(sig_wait_flags == HL_CS_FLAGS_SIG_WAIT)) { + dev_err(hdev->dev, + "Signal and wait CS flags are mutually exclusive, context %d\n", + ctx->asid); + rc = -EINVAL; + goto out; + } + + if (unlikely((sig_wait_flags & HL_CS_FLAGS_SIG_WAIT) && + (!hdev->supports_sync_stream))) { + dev_err(hdev->dev, "Sync stream CS is not supported\n"); + rc = -EINVAL; + goto out; + } + + if (args->in.cs_flags & HL_CS_FLAGS_SIGNAL) + cs_type = CS_TYPE_SIGNAL; + else if (args->in.cs_flags & HL_CS_FLAGS_WAIT) + cs_type = CS_TYPE_WAIT; + else + cs_type = CS_TYPE_DEFAULT; + chunks_execute = (void __user *) (uintptr_t) args->in.chunks_execute; num_chunks_execute = args->in.num_chunks_execute; - if (!num_chunks_execute) { + if (cs_type == CS_TYPE_DEFAULT) { + if (!num_chunks_execute) { + dev_err(hdev->dev, + "Got execute CS with 0 chunks, context %d\n", + ctx->asid); + rc = -EINVAL; + goto out; + } + } else if (num_chunks_execute != 1) { dev_err(hdev->dev, - "Got execute CS with 0 chunks, context %d\n", + "Sync stream CS mandates one chunk only, context %d\n", ctx->asid); rc = -EINVAL; goto out; @@ -722,7 +1032,7 @@ int hl_cs_ioctl(struct hl_fpriv *hpriv, void *data) "Need to run restore phase but restore CS is empty\n"); rc = 0; } else { - rc = _hl_cs_ioctl(hpriv, chunks_restore, + rc = cs_ioctl_default(hpriv, chunks_restore, num_chunks_restore, &cs_seq); } @@ -764,7 +1074,12 @@ int hl_cs_ioctl(struct hl_fpriv *hpriv, void *data) } } - rc = _hl_cs_ioctl(hpriv, chunks_execute, num_chunks_execute, &cs_seq); + if (cs_type == CS_TYPE_DEFAULT) + rc = cs_ioctl_default(hpriv, chunks_execute, num_chunks_execute, + &cs_seq); + else + rc = cs_ioctl_signal_wait(hpriv, cs_type, chunks_execute, + num_chunks_execute, &cs_seq); out: if (rc != -EAGAIN) { @@ -796,6 +1111,10 @@ static long _hl_cs_wait_ioctl(struct hl_device *hdev, fence = hl_ctx_get_fence(ctx, seq); if (IS_ERR(fence)) { rc = PTR_ERR(fence); + if (rc == -EINVAL) + dev_notice_ratelimited(hdev->dev, + "Can't wait on seq %llu because current CS is at seq %llu\n", + seq, ctx->cs_sequence); } else if (fence) { rc = dma_fence_wait_timeout(fence, true, timeout); if (fence->error == -ETIMEDOUT) @@ -803,8 +1122,12 @@ static long _hl_cs_wait_ioctl(struct hl_device *hdev, else if (fence->error == -EIO) rc = -EIO; dma_fence_put(fence); - } else + } else { + dev_dbg(hdev->dev, + "Can't wait on seq %llu because current CS is at seq %llu (Fence is gone)\n", + seq, ctx->cs_sequence); rc = 1; + } hl_ctx_put(ctx); diff --git a/drivers/misc/habanalabs/context.c b/drivers/misc/habanalabs/context.c index 2df6fb87e7ff..ec92b3506b1f 100644 --- a/drivers/misc/habanalabs/context.c +++ b/drivers/misc/habanalabs/context.c @@ -170,24 +170,16 @@ int hl_ctx_put(struct hl_ctx *ctx) struct dma_fence *hl_ctx_get_fence(struct hl_ctx *ctx, u64 seq) { - struct hl_device *hdev = ctx->hdev; struct dma_fence *fence; spin_lock(&ctx->cs_lock); if (seq >= ctx->cs_sequence) { - dev_notice_ratelimited(hdev->dev, - "Can't wait on seq %llu because current CS is at seq %llu\n", - seq, ctx->cs_sequence); spin_unlock(&ctx->cs_lock); return ERR_PTR(-EINVAL); } - if (seq + HL_MAX_PENDING_CS < ctx->cs_sequence) { - dev_dbg(hdev->dev, - "Can't wait on seq %llu because current CS is at seq %llu (Fence is gone)\n", - seq, ctx->cs_sequence); spin_unlock(&ctx->cs_lock); return NULL; } diff --git a/drivers/misc/habanalabs/debugfs.c b/drivers/misc/habanalabs/debugfs.c index 756d36ed5d95..3c8dcdfba20c 100644 --- a/drivers/misc/habanalabs/debugfs.c +++ b/drivers/misc/habanalabs/debugfs.c @@ -970,6 +970,98 @@ static ssize_t hl_device_write(struct file *f, const char __user *buf, return count; } +static ssize_t hl_clk_gate_read(struct file *f, char __user *buf, + size_t count, loff_t *ppos) +{ + struct hl_dbg_device_entry *entry = file_inode(f)->i_private; + struct hl_device *hdev = entry->hdev; + char tmp_buf[200]; + ssize_t rc; + + if (*ppos) + return 0; + + sprintf(tmp_buf, "%d\n", hdev->clock_gating); + rc = simple_read_from_buffer(buf, strlen(tmp_buf) + 1, ppos, tmp_buf, + strlen(tmp_buf) + 1); + + return rc; +} + +static ssize_t hl_clk_gate_write(struct file *f, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct hl_dbg_device_entry *entry = file_inode(f)->i_private; + struct hl_device *hdev = entry->hdev; + u32 value; + ssize_t rc; + + if (atomic_read(&hdev->in_reset)) { + dev_warn_ratelimited(hdev->dev, + "Can't change clock gating during reset\n"); + return 0; + } + + rc = kstrtouint_from_user(buf, count, 10, &value); + if (rc) + return rc; + + if (value) { + hdev->clock_gating = 1; + if (hdev->asic_funcs->enable_clock_gating) + hdev->asic_funcs->enable_clock_gating(hdev); + } else { + if (hdev->asic_funcs->disable_clock_gating) + hdev->asic_funcs->disable_clock_gating(hdev); + hdev->clock_gating = 0; + } + + return count; +} + +static ssize_t hl_stop_on_err_read(struct file *f, char __user *buf, + size_t count, loff_t *ppos) +{ + struct hl_dbg_device_entry *entry = file_inode(f)->i_private; + struct hl_device *hdev = entry->hdev; + char tmp_buf[200]; + ssize_t rc; + + if (*ppos) + return 0; + + sprintf(tmp_buf, "%d\n", hdev->stop_on_err); + rc = simple_read_from_buffer(buf, strlen(tmp_buf) + 1, ppos, tmp_buf, + strlen(tmp_buf) + 1); + + return rc; +} + +static ssize_t hl_stop_on_err_write(struct file *f, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct hl_dbg_device_entry *entry = file_inode(f)->i_private; + struct hl_device *hdev = entry->hdev; + u32 value; + ssize_t rc; + + if (atomic_read(&hdev->in_reset)) { + dev_warn_ratelimited(hdev->dev, + "Can't change stop on error during reset\n"); + return 0; + } + + rc = kstrtouint_from_user(buf, count, 10, &value); + if (rc) + return rc; + + hdev->stop_on_err = value ? 1 : 0; + + hl_device_reset(hdev, false, false); + + return count; +} + static const struct file_operations hl_data32b_fops = { .owner = THIS_MODULE, .read = hl_data_read32, @@ -1015,6 +1107,18 @@ static const struct file_operations hl_device_fops = { .write = hl_device_write }; +static const struct file_operations hl_clk_gate_fops = { + .owner = THIS_MODULE, + .read = hl_clk_gate_read, + .write = hl_clk_gate_write +}; + +static const struct file_operations hl_stop_on_err_fops = { + .owner = THIS_MODULE, + .read = hl_stop_on_err_read, + .write = hl_stop_on_err_write +}; + static const struct hl_info_list hl_debugfs_list[] = { {"command_buffers", command_buffers_show, NULL}, {"command_submission", command_submission_show, NULL}, @@ -1152,6 +1256,18 @@ void hl_debugfs_add_device(struct hl_device *hdev) dev_entry, &hl_device_fops); + debugfs_create_file("clk_gate", + 0200, + dev_entry->root, + dev_entry, + &hl_clk_gate_fops); + + debugfs_create_file("stop_on_err", + 0644, + dev_entry->root, + dev_entry, + &hl_stop_on_err_fops); + for (i = 0, entry = dev_entry->entry_arr ; i < count ; i++, entry++) { ent = debugfs_create_file(hl_debugfs_list[i].name, diff --git a/drivers/misc/habanalabs/device.c b/drivers/misc/habanalabs/device.c index aef4de36b7aa..2b38a119704c 100644 --- a/drivers/misc/habanalabs/device.c +++ b/drivers/misc/habanalabs/device.c @@ -256,6 +256,10 @@ static int device_early_init(struct hl_device *hdev) goya_set_asic_funcs(hdev); strlcpy(hdev->asic_name, "GOYA", sizeof(hdev->asic_name)); break; + case ASIC_GAUDI: + gaudi_set_asic_funcs(hdev); + sprintf(hdev->asic_name, "GAUDI"); + break; default: dev_err(hdev->dev, "Unrecognized ASIC type %d\n", hdev->asic_type); @@ -603,6 +607,9 @@ int hl_device_set_debug_mode(struct hl_device *hdev, bool enable) hdev->in_debug = 0; + if (!hdev->hard_reset_pending) + hdev->asic_funcs->enable_clock_gating(hdev); + goto out; } @@ -613,6 +620,7 @@ int hl_device_set_debug_mode(struct hl_device *hdev, bool enable) goto out; } + hdev->asic_funcs->disable_clock_gating(hdev); hdev->in_debug = 1; out: @@ -718,7 +726,7 @@ disable_device: return rc; } -static void device_kill_open_processes(struct hl_device *hdev) +static int device_kill_open_processes(struct hl_device *hdev) { u16 pending_total, pending_cnt; struct hl_fpriv *hpriv; @@ -771,9 +779,7 @@ static void device_kill_open_processes(struct hl_device *hdev) ssleep(1); } - if (!list_empty(&hdev->fpriv_list)) - dev_crit(hdev->dev, - "Going to hard reset with open user contexts\n"); + return list_empty(&hdev->fpriv_list) ? 0 : -EBUSY; } static void device_hard_reset_pending(struct work_struct *work) @@ -793,6 +799,7 @@ static void device_hard_reset_pending(struct work_struct *work) * @hdev: pointer to habanalabs device structure * @hard_reset: should we do hard reset to all engines or just reset the * compute/dma engines + * @from_hard_reset_thread: is the caller the hard-reset thread * * Block future CS and wait for pending CS to be enqueued * Call ASIC H/W fini @@ -815,6 +822,11 @@ int hl_device_reset(struct hl_device *hdev, bool hard_reset, return 0; } + if ((!hard_reset) && (!hdev->supports_soft_reset)) { + dev_dbg(hdev->dev, "Doing hard-reset instead of soft-reset\n"); + hard_reset = true; + } + /* * Prevent concurrency in this function - only one reset should be * done at any given time. Only need to perform this if we didn't @@ -894,7 +906,12 @@ again: * process can't really exit until all its CSs are done, which * is what we do in cs rollback */ - device_kill_open_processes(hdev); + rc = device_kill_open_processes(hdev); + if (rc) { + dev_crit(hdev->dev, + "Failed to kill all open processes, stopping hard reset\n"); + goto out_err; + } /* Flush the Event queue workers to make sure no other thread is * reading or writing to registers during the reset @@ -1062,7 +1079,7 @@ out_err: */ int hl_device_init(struct hl_device *hdev, struct class *hclass) { - int i, rc, cq_ready_cnt; + int i, rc, cq_cnt, cq_ready_cnt; char *name; bool add_cdev_sysfs_on_err = false; @@ -1120,14 +1137,16 @@ int hl_device_init(struct hl_device *hdev, struct class *hclass) goto sw_fini; } + cq_cnt = hdev->asic_prop.completion_queues_count; + /* * Initialize the completion queues. Must be done before hw_init, * because there the addresses of the completion queues are being * passed as arguments to request_irq */ - hdev->completion_queue = - kcalloc(hdev->asic_prop.completion_queues_count, - sizeof(*hdev->completion_queue), GFP_KERNEL); + hdev->completion_queue = kcalloc(cq_cnt, + sizeof(*hdev->completion_queue), + GFP_KERNEL); if (!hdev->completion_queue) { dev_err(hdev->dev, "failed to allocate completion queues\n"); @@ -1135,10 +1154,9 @@ int hl_device_init(struct hl_device *hdev, struct class *hclass) goto hw_queues_destroy; } - for (i = 0, cq_ready_cnt = 0; - i < hdev->asic_prop.completion_queues_count; - i++, cq_ready_cnt++) { - rc = hl_cq_init(hdev, &hdev->completion_queue[i], i); + for (i = 0, cq_ready_cnt = 0 ; i < cq_cnt ; i++, cq_ready_cnt++) { + rc = hl_cq_init(hdev, &hdev->completion_queue[i], + hdev->asic_funcs->get_queue_id_for_cq(hdev, i)); if (rc) { dev_err(hdev->dev, "failed to initialize completion queue\n"); @@ -1325,11 +1343,12 @@ void hl_device_fini(struct hl_device *hdev) * This function is competing with the reset function, so try to * take the reset atomic and if we are already in middle of reset, * wait until reset function is finished. Reset function is designed - * to always finish (could take up to a few seconds in worst case). + * to always finish. However, in Gaudi, because of all the network + * ports, the hard reset could take between 10-30 seconds */ timeout = ktime_add_us(ktime_get(), - HL_PENDING_RESET_PER_SEC * 1000 * 1000 * 4); + HL_HARD_RESET_MAX_TIMEOUT * 1000 * 1000); rc = atomic_cmpxchg(&hdev->in_reset, 0, 1); while (rc) { usleep_range(50, 200); @@ -1375,7 +1394,9 @@ void hl_device_fini(struct hl_device *hdev) * can't really exit until all its CSs are done, which is what we * do in cs rollback */ - device_kill_open_processes(hdev); + rc = device_kill_open_processes(hdev); + if (rc) + dev_crit(hdev->dev, "Failed to kill all open processes\n"); hl_cb_pool_fini(hdev); diff --git a/drivers/misc/habanalabs/firmware_if.c b/drivers/misc/habanalabs/firmware_if.c index f5bd03171dac..baf790cf4b78 100644 --- a/drivers/misc/habanalabs/firmware_if.c +++ b/drivers/misc/habanalabs/firmware_if.c @@ -6,20 +6,22 @@ */ #include "habanalabs.h" +#include "include/hl_boot_if.h" #include #include #include +#include /** - * hl_fw_push_fw_to_device() - Push FW code to device. + * hl_fw_load_fw_to_device() - Load F/W code to device's memory. * @hdev: pointer to hl_device structure. * * Copy fw code from firmware file to device memory. * * Return: 0 on success, non-zero for failure. */ -int hl_fw_push_fw_to_device(struct hl_device *hdev, const char *fw_name, +int hl_fw_load_fw_to_device(struct hl_device *hdev, const char *fw_name, void __iomem *dst) { const struct firmware *fw; @@ -129,6 +131,68 @@ out: return rc; } +int hl_fw_unmask_irq(struct hl_device *hdev, u16 event_type) +{ + struct armcp_packet pkt; + long result; + int rc; + + memset(&pkt, 0, sizeof(pkt)); + + pkt.ctl = cpu_to_le32(ARMCP_PACKET_UNMASK_RAZWI_IRQ << + ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.value = cpu_to_le64(event_type); + + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), + HL_DEVICE_TIMEOUT_USEC, &result); + + if (rc) + dev_err(hdev->dev, "failed to unmask RAZWI IRQ %d", event_type); + + return rc; +} + +int hl_fw_unmask_irq_arr(struct hl_device *hdev, const u32 *irq_arr, + size_t irq_arr_size) +{ + struct armcp_unmask_irq_arr_packet *pkt; + size_t total_pkt_size; + long result; + int rc; + + total_pkt_size = sizeof(struct armcp_unmask_irq_arr_packet) + + irq_arr_size; + + /* data should be aligned to 8 bytes in order to ArmCP to copy it */ + total_pkt_size = (total_pkt_size + 0x7) & ~0x7; + + /* total_pkt_size is casted to u16 later on */ + if (total_pkt_size > USHRT_MAX) { + dev_err(hdev->dev, "too many elements in IRQ array\n"); + return -EINVAL; + } + + pkt = kzalloc(total_pkt_size, GFP_KERNEL); + if (!pkt) + return -ENOMEM; + + pkt->length = cpu_to_le32(irq_arr_size / sizeof(irq_arr[0])); + memcpy(&pkt->irqs, irq_arr, irq_arr_size); + + pkt->armcp_pkt.ctl = cpu_to_le32(ARMCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY << + ARMCP_PKT_CTL_OPCODE_SHIFT); + + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) pkt, + total_pkt_size, HL_DEVICE_TIMEOUT_USEC, &result); + + if (rc) + dev_err(hdev->dev, "failed to unmask IRQ array\n"); + + kfree(pkt); + + return rc; +} + int hl_fw_test_cpu_queue(struct hl_device *hdev) { struct armcp_packet test_pkt = {}; @@ -286,3 +350,232 @@ out: return rc; } + +static void fw_read_errors(struct hl_device *hdev, u32 boot_err0_reg) +{ + u32 err_val; + + /* Some of the firmware status codes are deprecated in newer f/w + * versions. In those versions, the errors are reported + * in different registers. Therefore, we need to check those + * registers and print the exact errors. Moreover, there + * may be multiple errors, so we need to report on each error + * separately. Some of the error codes might indicate a state + * that is not an error per-se, but it is an error in production + * environment + */ + err_val = RREG32(boot_err0_reg); + if (!(err_val & CPU_BOOT_ERR0_ENABLED)) + return; + + if (err_val & CPU_BOOT_ERR0_DRAM_INIT_FAIL) + dev_err(hdev->dev, + "Device boot error - DRAM initialization failed\n"); + if (err_val & CPU_BOOT_ERR0_FIT_CORRUPTED) + dev_err(hdev->dev, "Device boot error - FIT image corrupted\n"); + if (err_val & CPU_BOOT_ERR0_TS_INIT_FAIL) + dev_err(hdev->dev, + "Device boot error - Thermal Sensor initialization failed\n"); + if (err_val & CPU_BOOT_ERR0_DRAM_SKIPPED) + dev_warn(hdev->dev, + "Device boot warning - Skipped DRAM initialization\n"); + if (err_val & CPU_BOOT_ERR0_BMC_WAIT_SKIPPED) + dev_warn(hdev->dev, + "Device boot error - Skipped waiting for BMC\n"); + if (err_val & CPU_BOOT_ERR0_NIC_DATA_NOT_RDY) + dev_err(hdev->dev, + "Device boot error - Serdes data from BMC not available\n"); + if (err_val & CPU_BOOT_ERR0_NIC_FW_FAIL) + dev_err(hdev->dev, + "Device boot error - NIC F/W initialization failed\n"); +} + +int hl_fw_init_cpu(struct hl_device *hdev, u32 cpu_boot_status_reg, + u32 msg_to_cpu_reg, u32 cpu_msg_status_reg, + u32 boot_err0_reg, bool skip_bmc, + u32 cpu_timeout, u32 boot_fit_timeout) +{ + u32 status; + int rc; + + dev_info(hdev->dev, "Going to wait for device boot (up to %lds)\n", + cpu_timeout / USEC_PER_SEC); + + /* Wait for boot FIT request */ + rc = hl_poll_timeout( + hdev, + cpu_boot_status_reg, + status, + status == CPU_BOOT_STATUS_WAITING_FOR_BOOT_FIT, + 10000, + boot_fit_timeout); + + if (rc) { + dev_dbg(hdev->dev, + "No boot fit request received, resuming boot\n"); + } else { + rc = hdev->asic_funcs->load_boot_fit_to_device(hdev); + if (rc) + goto out; + + /* Clear device CPU message status */ + WREG32(cpu_msg_status_reg, CPU_MSG_CLR); + + /* Signal device CPU that boot loader is ready */ + WREG32(msg_to_cpu_reg, KMD_MSG_FIT_RDY); + + /* Poll for CPU device ack */ + rc = hl_poll_timeout( + hdev, + cpu_msg_status_reg, + status, + status == CPU_MSG_OK, + 10000, + boot_fit_timeout); + + if (rc) { + dev_err(hdev->dev, + "Timeout waiting for boot fit load ack\n"); + goto out; + } + + /* Clear message */ + WREG32(msg_to_cpu_reg, KMD_MSG_NA); + } + + /* Make sure CPU boot-loader is running */ + rc = hl_poll_timeout( + hdev, + cpu_boot_status_reg, + status, + (status == CPU_BOOT_STATUS_DRAM_RDY) || + (status == CPU_BOOT_STATUS_NIC_FW_RDY) || + (status == CPU_BOOT_STATUS_READY_TO_BOOT) || + (status == CPU_BOOT_STATUS_SRAM_AVAIL), + 10000, + cpu_timeout); + + /* Read U-Boot, preboot versions now in case we will later fail */ + hdev->asic_funcs->read_device_fw_version(hdev, FW_COMP_UBOOT); + hdev->asic_funcs->read_device_fw_version(hdev, FW_COMP_PREBOOT); + + /* Some of the status codes below are deprecated in newer f/w + * versions but we keep them here for backward compatibility + */ + if (rc) { + switch (status) { + case CPU_BOOT_STATUS_NA: + dev_err(hdev->dev, + "Device boot error - BTL did NOT run\n"); + break; + case CPU_BOOT_STATUS_IN_WFE: + dev_err(hdev->dev, + "Device boot error - Stuck inside WFE loop\n"); + break; + case CPU_BOOT_STATUS_IN_BTL: + dev_err(hdev->dev, + "Device boot error - Stuck in BTL\n"); + break; + case CPU_BOOT_STATUS_IN_PREBOOT: + dev_err(hdev->dev, + "Device boot error - Stuck in Preboot\n"); + break; + case CPU_BOOT_STATUS_IN_SPL: + dev_err(hdev->dev, + "Device boot error - Stuck in SPL\n"); + break; + case CPU_BOOT_STATUS_IN_UBOOT: + dev_err(hdev->dev, + "Device boot error - Stuck in u-boot\n"); + break; + case CPU_BOOT_STATUS_DRAM_INIT_FAIL: + dev_err(hdev->dev, + "Device boot error - DRAM initialization failed\n"); + break; + case CPU_BOOT_STATUS_UBOOT_NOT_READY: + dev_err(hdev->dev, + "Device boot error - u-boot stopped by user\n"); + break; + case CPU_BOOT_STATUS_TS_INIT_FAIL: + dev_err(hdev->dev, + "Device boot error - Thermal Sensor initialization failed\n"); + break; + default: + dev_err(hdev->dev, + "Device boot error - Invalid status code %d\n", + status); + break; + } + + rc = -EIO; + goto out; + } + + if (!hdev->fw_loading) { + dev_info(hdev->dev, "Skip loading FW\n"); + goto out; + } + + if (status == CPU_BOOT_STATUS_SRAM_AVAIL) + goto out; + + dev_info(hdev->dev, + "Loading firmware to device, may take some time...\n"); + + rc = hdev->asic_funcs->load_firmware_to_device(hdev); + if (rc) + goto out; + + if (skip_bmc) { + WREG32(msg_to_cpu_reg, KMD_MSG_SKIP_BMC); + + rc = hl_poll_timeout( + hdev, + cpu_boot_status_reg, + status, + (status == CPU_BOOT_STATUS_BMC_WAITING_SKIPPED), + 10000, + cpu_timeout); + + if (rc) { + dev_err(hdev->dev, + "Failed to get ACK on skipping BMC, %d\n", + status); + WREG32(msg_to_cpu_reg, KMD_MSG_NA); + rc = -EIO; + goto out; + } + } + + WREG32(msg_to_cpu_reg, KMD_MSG_FIT_RDY); + + rc = hl_poll_timeout( + hdev, + cpu_boot_status_reg, + status, + (status == CPU_BOOT_STATUS_SRAM_AVAIL), + 10000, + cpu_timeout); + + /* Clear message */ + WREG32(msg_to_cpu_reg, KMD_MSG_NA); + + if (rc) { + if (status == CPU_BOOT_STATUS_FIT_CORRUPTED) + dev_err(hdev->dev, + "Device reports FIT image is corrupted\n"); + else + dev_err(hdev->dev, + "Device failed to load, %d\n", status); + + rc = -EIO; + goto out; + } + + dev_info(hdev->dev, "Successfully loaded firmware to device\n"); + +out: + fw_read_errors(hdev, boot_err0_reg); + + return rc; +} diff --git a/drivers/misc/habanalabs/gaudi/Makefile b/drivers/misc/habanalabs/gaudi/Makefile new file mode 100644 index 000000000000..f802cdc980ca --- /dev/null +++ b/drivers/misc/habanalabs/gaudi/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only +subdir-ccflags-y += -I$(src) + +HL_GAUDI_FILES := gaudi/gaudi.o gaudi/gaudi_hwmgr.o gaudi/gaudi_security.o \ + gaudi/gaudi_coresight.o diff --git a/drivers/misc/habanalabs/gaudi/gaudi.c b/drivers/misc/habanalabs/gaudi/gaudi.c new file mode 100644 index 000000000000..61f88e9884ce --- /dev/null +++ b/drivers/misc/habanalabs/gaudi/gaudi.c @@ -0,0 +1,6748 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + */ + +#include "gaudiP.h" +#include "include/hw_ip/mmu/mmu_general.h" +#include "include/hw_ip/mmu/mmu_v1_1.h" +#include "include/gaudi/gaudi_masks.h" +#include "include/gaudi/gaudi_fw_if.h" +#include "include/gaudi/gaudi_reg_map.h" +#include "include/gaudi/gaudi_async_ids_map_extended.h" + +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Gaudi security scheme: + * + * 1. Host is protected by: + * - Range registers + * - MMU + * + * 2. DDR is protected by: + * - Range registers (protect the first 512MB) + * + * 3. Configuration is protected by: + * - Range registers + * - Protection bits + * + * MMU is always enabled. + * + * QMAN DMA channels 0,1,5 (PCI DMAN): + * - DMA is not secured. + * - PQ and CQ are secured. + * - CP is secured: The driver needs to parse CB but WREG should be allowed + * because of TDMA (tensor DMA). Hence, WREG is always not + * secured. + * + * When the driver needs to use DMA it will check that Gaudi is idle, set DMA + * channel 0 to be secured, execute the DMA and change it back to not secured. + * Currently, the driver doesn't use the DMA while there are compute jobs + * running. + * + * The current use cases for the driver to use the DMA are: + * - Clear SRAM on context switch (happens on context switch when device is + * idle) + * - MMU page tables area clear (happens on init) + * + * QMAN DMA 2-4,6,7, TPC, MME, NIC: + * PQ is secured and is located on the Host (HBM CON TPC3 bug) + * CQ, CP and the engine are not secured + * + */ + +#define GAUDI_BOOT_FIT_FILE "habanalabs/gaudi/gaudi-boot-fit.itb" +#define GAUDI_LINUX_FW_FILE "habanalabs/gaudi/gaudi-fit.itb" +#define GAUDI_TPC_FW_FILE "habanalabs/gaudi/gaudi_tpc.bin" + +#define GAUDI_DMA_POOL_BLK_SIZE 0x100 /* 256 bytes */ + +#define GAUDI_RESET_TIMEOUT_MSEC 1000 /* 1000ms */ +#define GAUDI_RESET_WAIT_MSEC 1 /* 1ms */ +#define GAUDI_CPU_RESET_WAIT_MSEC 200 /* 200ms */ +#define GAUDI_TEST_QUEUE_WAIT_USEC 100000 /* 100ms */ + +#define GAUDI_PLDM_RESET_WAIT_MSEC 1000 /* 1s */ +#define GAUDI_PLDM_HRESET_TIMEOUT_MSEC 20000 /* 20s */ +#define GAUDI_PLDM_SRESET_TIMEOUT_MSEC 14000 /* 14s */ +#define GAUDI_PLDM_TEST_QUEUE_WAIT_USEC 1000000 /* 1s */ +#define GAUDI_PLDM_MMU_TIMEOUT_USEC (MMU_CONFIG_TIMEOUT_USEC * 100) +#define GAUDI_PLDM_QMAN0_TIMEOUT_USEC (HL_DEVICE_TIMEOUT_USEC * 30) +#define GAUDI_PLDM_TPC_KERNEL_WAIT_USEC (HL_DEVICE_TIMEOUT_USEC * 30) +#define GAUDI_BOOT_FIT_REQ_TIMEOUT_USEC 1000000 /* 1s */ + +#define GAUDI_QMAN0_FENCE_VAL 0x72E91AB9 + +#define GAUDI_MAX_STRING_LEN 20 + +#define GAUDI_CB_POOL_CB_CNT 512 +#define GAUDI_CB_POOL_CB_SIZE 0x20000 /* 128KB */ + +#define GAUDI_ALLOC_CPU_MEM_RETRY_CNT 3 + +#define GAUDI_NUM_OF_TPC_INTR_CAUSE 20 + +#define GAUDI_NUM_OF_QM_ERR_CAUSE 16 + +#define GAUDI_NUM_OF_QM_ARB_ERR_CAUSE 3 + +#define GAUDI_ARB_WDT_TIMEOUT 0x400000 + +static const char gaudi_irq_name[GAUDI_MSI_ENTRIES][GAUDI_MAX_STRING_LEN] = { + "gaudi cq 0_0", "gaudi cq 0_1", "gaudi cq 0_2", "gaudi cq 0_3", + "gaudi cq 1_0", "gaudi cq 1_1", "gaudi cq 1_2", "gaudi cq 1_3", + "gaudi cq 5_0", "gaudi cq 5_1", "gaudi cq 5_2", "gaudi cq 5_3", + "gaudi cpu eq" +}; + +static const u8 gaudi_dma_assignment[GAUDI_DMA_MAX] = { + [GAUDI_PCI_DMA_1] = 0, + [GAUDI_PCI_DMA_2] = 1, + [GAUDI_PCI_DMA_3] = 5, + [GAUDI_HBM_DMA_1] = 2, + [GAUDI_HBM_DMA_2] = 3, + [GAUDI_HBM_DMA_3] = 4, + [GAUDI_HBM_DMA_4] = 6, + [GAUDI_HBM_DMA_5] = 7 +}; + +static const u8 gaudi_cq_assignment[NUMBER_OF_CMPLT_QUEUES] = { + [0] = GAUDI_QUEUE_ID_DMA_0_0, + [1] = GAUDI_QUEUE_ID_DMA_0_1, + [2] = GAUDI_QUEUE_ID_DMA_0_2, + [3] = GAUDI_QUEUE_ID_DMA_0_3, + [4] = GAUDI_QUEUE_ID_DMA_1_0, + [5] = GAUDI_QUEUE_ID_DMA_1_1, + [6] = GAUDI_QUEUE_ID_DMA_1_2, + [7] = GAUDI_QUEUE_ID_DMA_1_3, + [8] = GAUDI_QUEUE_ID_DMA_5_0, + [9] = GAUDI_QUEUE_ID_DMA_5_1, + [10] = GAUDI_QUEUE_ID_DMA_5_2, + [11] = GAUDI_QUEUE_ID_DMA_5_3 +}; + +static const u16 gaudi_packet_sizes[MAX_PACKET_ID] = { + [PACKET_WREG_32] = sizeof(struct packet_wreg32), + [PACKET_WREG_BULK] = sizeof(struct packet_wreg_bulk), + [PACKET_MSG_LONG] = sizeof(struct packet_msg_long), + [PACKET_MSG_SHORT] = sizeof(struct packet_msg_short), + [PACKET_CP_DMA] = sizeof(struct packet_cp_dma), + [PACKET_REPEAT] = sizeof(struct packet_repeat), + [PACKET_MSG_PROT] = sizeof(struct packet_msg_prot), + [PACKET_FENCE] = sizeof(struct packet_fence), + [PACKET_LIN_DMA] = sizeof(struct packet_lin_dma), + [PACKET_NOP] = sizeof(struct packet_nop), + [PACKET_STOP] = sizeof(struct packet_stop), + [PACKET_ARB_POINT] = sizeof(struct packet_arb_point), + [PACKET_WAIT] = sizeof(struct packet_wait), + [PACKET_LOAD_AND_EXE] = sizeof(struct packet_load_and_exe) +}; + +static const char * const +gaudi_tpc_interrupts_cause[GAUDI_NUM_OF_TPC_INTR_CAUSE] = { + "tpc_address_exceed_slm", + "tpc_div_by_0", + "tpc_spu_mac_overflow", + "tpc_spu_addsub_overflow", + "tpc_spu_abs_overflow", + "tpc_spu_fp_dst_nan_inf", + "tpc_spu_fp_dst_denorm", + "tpc_vpu_mac_overflow", + "tpc_vpu_addsub_overflow", + "tpc_vpu_abs_overflow", + "tpc_vpu_fp_dst_nan_inf", + "tpc_vpu_fp_dst_denorm", + "tpc_assertions", + "tpc_illegal_instruction", + "tpc_pc_wrap_around", + "tpc_qm_sw_err", + "tpc_hbw_rresp_err", + "tpc_hbw_bresp_err", + "tpc_lbw_rresp_err", + "tpc_lbw_bresp_err" +}; + +static const char * const +gaudi_qman_error_cause[GAUDI_NUM_OF_QM_ERR_CAUSE] = { + "PQ AXI HBW error", + "CQ AXI HBW error", + "CP AXI HBW error", + "CP error due to undefined OPCODE", + "CP encountered STOP OPCODE", + "CP AXI LBW error", + "CP WRREG32 or WRBULK returned error", + "N/A", + "FENCE 0 inc over max value and clipped", + "FENCE 1 inc over max value and clipped", + "FENCE 2 inc over max value and clipped", + "FENCE 3 inc over max value and clipped", + "FENCE 0 dec under min value and clipped", + "FENCE 1 dec under min value and clipped", + "FENCE 2 dec under min value and clipped", + "FENCE 3 dec under min value and clipped" +}; + +static const char * const +gaudi_qman_arb_error_cause[GAUDI_NUM_OF_QM_ARB_ERR_CAUSE] = { + "Choice push while full error", + "Choice Q watchdog error", + "MSG AXI LBW returned with error" +}; + +static enum hl_queue_type gaudi_queue_type[GAUDI_QUEUE_ID_SIZE] = { + QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_0_0 */ + QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_0_1 */ + QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_0_2 */ + QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_0_3 */ + QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_1_0 */ + QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_1_1 */ + QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_1_2 */ + QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_1_3 */ + QUEUE_TYPE_CPU, /* GAUDI_QUEUE_ID_CPU_PQ */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_2_0 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_2_1 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_2_2 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_2_3 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_3_0 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_3_1 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_3_2 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_3_3 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_4_0 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_4_1 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_4_2 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_4_3 */ + QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_5_0 */ + QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_5_1 */ + QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_5_2 */ + QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_5_3 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_6_0 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_6_1 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_6_2 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_6_3 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_7_0 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_7_1 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_7_2 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_7_3 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_0_0 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_0_1 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_0_2 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_0_3 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_1_0 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_1_1 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_1_2 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_1_3 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_0_0 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_0_1 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_0_2 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_0_3 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_1_0 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_1_1 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_1_2 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_1_3 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_2_0 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_2_1 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_2_2 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_2_3 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_3_0 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_3_1 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_3_2 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_3_3 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_4_0 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_4_1 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_4_2 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_4_3 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_5_0 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_5_1 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_5_2 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_5_3 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_6_0 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_6_1 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_6_2 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_6_3 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_7_0 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_7_1 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_7_2 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_7_3 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_0_0 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_0_1 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_0_2 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_0_3 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_1_0 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_1_1 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_1_2 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_1_3 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_2_0 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_2_1 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_2_2 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_2_3 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_3_0 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_3_1 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_3_2 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_3_3 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_4_0 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_4_1 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_4_2 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_4_3 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_5_0 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_5_1 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_5_2 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_5_3 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_6_0 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_6_1 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_6_2 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_6_3 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_7_0 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_7_1 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_7_2 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_7_3 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_8_0 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_8_1 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_8_2 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_8_3 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_9_0 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_9_1 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_9_2 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_9_3 */ +}; + +static int gaudi_mmu_update_asid_hop0_addr(struct hl_device *hdev, u32 asid, + u64 phys_addr); +static int gaudi_send_job_on_qman0(struct hl_device *hdev, + struct hl_cs_job *job); +static int gaudi_memset_device_memory(struct hl_device *hdev, u64 addr, + u32 size, u64 val); +static int gaudi_run_tpc_kernel(struct hl_device *hdev, u64 tpc_kernel, + u32 tpc_id); +static int gaudi_mmu_clear_pgt_range(struct hl_device *hdev); +static int gaudi_armcp_info_get(struct hl_device *hdev); +static void gaudi_disable_clock_gating(struct hl_device *hdev); +static void gaudi_mmu_prepare(struct hl_device *hdev, u32 asid); + +static int gaudi_get_fixed_properties(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + int i; + + if (GAUDI_QUEUE_ID_SIZE >= HL_MAX_QUEUES) { + dev_err(hdev->dev, + "Number of H/W queues must be smaller than %d\n", + HL_MAX_QUEUES); + return -EFAULT; + } + + for (i = 0 ; i < GAUDI_QUEUE_ID_SIZE ; i++) { + if (gaudi_queue_type[i] == QUEUE_TYPE_EXT) { + prop->hw_queues_props[i].type = QUEUE_TYPE_EXT; + prop->hw_queues_props[i].driver_only = 0; + prop->hw_queues_props[i].requires_kernel_cb = 1; + } else if (gaudi_queue_type[i] == QUEUE_TYPE_CPU) { + prop->hw_queues_props[i].type = QUEUE_TYPE_CPU; + prop->hw_queues_props[i].driver_only = 1; + prop->hw_queues_props[i].requires_kernel_cb = 0; + } else if (gaudi_queue_type[i] == QUEUE_TYPE_INT) { + prop->hw_queues_props[i].type = QUEUE_TYPE_INT; + prop->hw_queues_props[i].driver_only = 0; + prop->hw_queues_props[i].requires_kernel_cb = 0; + } else if (gaudi_queue_type[i] == QUEUE_TYPE_NA) { + prop->hw_queues_props[i].type = QUEUE_TYPE_NA; + prop->hw_queues_props[i].driver_only = 0; + prop->hw_queues_props[i].requires_kernel_cb = 0; + } + } + + for (; i < HL_MAX_QUEUES; i++) + prop->hw_queues_props[i].type = QUEUE_TYPE_NA; + + prop->completion_queues_count = NUMBER_OF_CMPLT_QUEUES; + + prop->dram_base_address = DRAM_PHYS_BASE; + prop->dram_size = GAUDI_HBM_SIZE_32GB; + prop->dram_end_address = prop->dram_base_address + + prop->dram_size; + prop->dram_user_base_address = DRAM_BASE_ADDR_USER; + + prop->sram_base_address = SRAM_BASE_ADDR; + prop->sram_size = SRAM_SIZE; + prop->sram_end_address = prop->sram_base_address + + prop->sram_size; + prop->sram_user_base_address = prop->sram_base_address + + SRAM_USER_BASE_OFFSET; + + prop->mmu_pgt_addr = MMU_PAGE_TABLES_ADDR; + if (hdev->pldm) + prop->mmu_pgt_size = 0x800000; /* 8MB */ + else + prop->mmu_pgt_size = MMU_PAGE_TABLES_SIZE; + prop->mmu_pte_size = HL_PTE_SIZE; + prop->mmu_hop_table_size = HOP_TABLE_SIZE; + prop->mmu_hop0_tables_total_size = HOP0_TABLES_TOTAL_SIZE; + prop->dram_page_size = PAGE_SIZE_2MB; + + prop->pmmu.hop0_shift = HOP0_SHIFT; + prop->pmmu.hop1_shift = HOP1_SHIFT; + prop->pmmu.hop2_shift = HOP2_SHIFT; + prop->pmmu.hop3_shift = HOP3_SHIFT; + prop->pmmu.hop4_shift = HOP4_SHIFT; + prop->pmmu.hop0_mask = HOP0_MASK; + prop->pmmu.hop1_mask = HOP1_MASK; + prop->pmmu.hop2_mask = HOP2_MASK; + prop->pmmu.hop3_mask = HOP3_MASK; + prop->pmmu.hop4_mask = HOP4_MASK; + prop->pmmu.start_addr = VA_HOST_SPACE_START; + prop->pmmu.end_addr = + (VA_HOST_SPACE_START + VA_HOST_SPACE_SIZE / 2) - 1; + prop->pmmu.page_size = PAGE_SIZE_4KB; + + /* PMMU and HPMMU are the same except of page size */ + memcpy(&prop->pmmu_huge, &prop->pmmu, sizeof(prop->pmmu)); + prop->pmmu_huge.page_size = PAGE_SIZE_2MB; + + /* shifts and masks are the same in PMMU and DMMU */ + memcpy(&prop->dmmu, &prop->pmmu, sizeof(prop->pmmu)); + prop->dmmu.start_addr = (VA_HOST_SPACE_START + VA_HOST_SPACE_SIZE / 2); + prop->dmmu.end_addr = VA_HOST_SPACE_END; + prop->dmmu.page_size = PAGE_SIZE_2MB; + + prop->cfg_size = CFG_SIZE; + prop->max_asid = MAX_ASID; + prop->num_of_events = GAUDI_EVENT_SIZE; + prop->tpc_enabled_mask = TPC_ENABLED_MASK; + + prop->max_power_default = MAX_POWER_DEFAULT; + + prop->cb_pool_cb_cnt = GAUDI_CB_POOL_CB_CNT; + prop->cb_pool_cb_size = GAUDI_CB_POOL_CB_SIZE; + + prop->pcie_dbi_base_address = mmPCIE_DBI_BASE; + prop->pcie_aux_dbi_reg_addr = CFG_BASE + mmPCIE_AUX_DBI; + + strncpy(prop->armcp_info.card_name, GAUDI_DEFAULT_CARD_NAME, + CARD_NAME_MAX_LEN); + + return 0; +} + +static int gaudi_pci_bars_map(struct hl_device *hdev) +{ + static const char * const name[] = {"SRAM", "CFG", "HBM"}; + bool is_wc[3] = {false, false, true}; + int rc; + + rc = hl_pci_bars_map(hdev, name, is_wc); + if (rc) + return rc; + + hdev->rmmio = hdev->pcie_bar[CFG_BAR_ID] + + (CFG_BASE - SPI_FLASH_BASE_ADDR); + + return 0; +} + +static u64 gaudi_set_hbm_bar_base(struct hl_device *hdev, u64 addr) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + u64 old_addr = addr; + int rc; + + if ((gaudi) && (gaudi->hbm_bar_cur_addr == addr)) + return old_addr; + + /* Inbound Region 2 - Bar 4 - Point to HBM */ + rc = hl_pci_set_dram_bar_base(hdev, 2, 4, addr); + if (rc) + return U64_MAX; + + if (gaudi) { + old_addr = gaudi->hbm_bar_cur_addr; + gaudi->hbm_bar_cur_addr = addr; + } + + return old_addr; +} + +static int gaudi_init_iatu(struct hl_device *hdev) +{ + int rc = 0; + + /* Inbound Region 1 - Bar 2 - Point to SPI FLASH */ + rc = hl_pci_iatu_write(hdev, 0x314, + lower_32_bits(SPI_FLASH_BASE_ADDR)); + rc |= hl_pci_iatu_write(hdev, 0x318, + upper_32_bits(SPI_FLASH_BASE_ADDR)); + rc |= hl_pci_iatu_write(hdev, 0x300, 0); + /* Enable + Bar match + match enable */ + rc |= hl_pci_iatu_write(hdev, 0x304, 0xC0080200); + + if (rc) + return -EIO; + + return hl_pci_init_iatu(hdev, SRAM_BASE_ADDR, DRAM_PHYS_BASE, + HOST_PHYS_BASE, HOST_PHYS_SIZE); +} + +static int gaudi_early_init(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct pci_dev *pdev = hdev->pdev; + int rc; + + rc = gaudi_get_fixed_properties(hdev); + if (rc) { + dev_err(hdev->dev, "Failed to get fixed properties\n"); + return rc; + } + + /* Check BAR sizes */ + if (pci_resource_len(pdev, SRAM_BAR_ID) != SRAM_BAR_SIZE) { + dev_err(hdev->dev, + "Not " HL_NAME "? BAR %d size %llu, expecting %llu\n", + SRAM_BAR_ID, + (unsigned long long) pci_resource_len(pdev, + SRAM_BAR_ID), + SRAM_BAR_SIZE); + return -ENODEV; + } + + if (pci_resource_len(pdev, CFG_BAR_ID) != CFG_BAR_SIZE) { + dev_err(hdev->dev, + "Not " HL_NAME "? BAR %d size %llu, expecting %llu\n", + CFG_BAR_ID, + (unsigned long long) pci_resource_len(pdev, + CFG_BAR_ID), + CFG_BAR_SIZE); + return -ENODEV; + } + + prop->dram_pci_bar_size = pci_resource_len(pdev, HBM_BAR_ID); + + rc = hl_pci_init(hdev); + if (rc) + return rc; + + return 0; +} + +static int gaudi_early_fini(struct hl_device *hdev) +{ + hl_pci_fini(hdev); + + return 0; +} + +/** + * gaudi_fetch_psoc_frequency - Fetch PSOC frequency values + * + * @hdev: pointer to hl_device structure + * + */ +static void gaudi_fetch_psoc_frequency(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + + prop->psoc_pci_pll_nr = RREG32(mmPSOC_PCI_PLL_NR); + prop->psoc_pci_pll_nf = RREG32(mmPSOC_PCI_PLL_NF); + prop->psoc_pci_pll_od = RREG32(mmPSOC_PCI_PLL_OD); + prop->psoc_pci_pll_div_factor = RREG32(mmPSOC_PCI_PLL_DIV_FACTOR_1); +} + +static int _gaudi_init_tpc_mem(struct hl_device *hdev, + dma_addr_t tpc_kernel_src_addr, u32 tpc_kernel_size) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct packet_lin_dma *init_tpc_mem_pkt; + struct hl_cs_job *job; + struct hl_cb *cb; + u64 dst_addr; + u32 cb_size, ctl; + u8 tpc_id; + int rc; + + cb = hl_cb_kernel_create(hdev, PAGE_SIZE); + if (!cb) + return -EFAULT; + + init_tpc_mem_pkt = (struct packet_lin_dma *) (uintptr_t) + cb->kernel_address; + cb_size = sizeof(*init_tpc_mem_pkt); + memset(init_tpc_mem_pkt, 0, cb_size); + + init_tpc_mem_pkt->tsize = cpu_to_le32(tpc_kernel_size); + + ctl = ((PACKET_LIN_DMA << GAUDI_PKT_CTL_OPCODE_SHIFT) | + (1 << GAUDI_PKT_LIN_DMA_CTL_LIN_SHIFT) | + (1 << GAUDI_PKT_CTL_RB_SHIFT) | + (1 << GAUDI_PKT_CTL_MB_SHIFT)); + + init_tpc_mem_pkt->ctl = cpu_to_le32(ctl); + + init_tpc_mem_pkt->src_addr = cpu_to_le64(tpc_kernel_src_addr); + dst_addr = (prop->sram_user_base_address & + GAUDI_PKT_LIN_DMA_DST_ADDR_MASK) >> + GAUDI_PKT_LIN_DMA_DST_ADDR_SHIFT; + init_tpc_mem_pkt->dst_addr |= cpu_to_le64(dst_addr); + + job = hl_cs_allocate_job(hdev, QUEUE_TYPE_EXT, true); + if (!job) { + dev_err(hdev->dev, "Failed to allocate a new job\n"); + rc = -ENOMEM; + goto release_cb; + } + + job->id = 0; + job->user_cb = cb; + job->user_cb->cs_cnt++; + job->user_cb_size = cb_size; + job->hw_queue_id = GAUDI_QUEUE_ID_DMA_0_0; + job->patched_cb = job->user_cb; + job->job_cb_size = job->user_cb_size + sizeof(struct packet_msg_prot); + + hl_debugfs_add_job(hdev, job); + + rc = gaudi_send_job_on_qman0(hdev, job); + + if (rc) + goto free_job; + + for (tpc_id = 0 ; tpc_id < TPC_NUMBER_OF_ENGINES ; tpc_id++) { + rc = gaudi_run_tpc_kernel(hdev, dst_addr, tpc_id); + if (rc) + break; + } + +free_job: + hl_userptr_delete_list(hdev, &job->userptr_list); + hl_debugfs_remove_job(hdev, job); + kfree(job); + cb->cs_cnt--; + +release_cb: + hl_cb_put(cb); + hl_cb_destroy(hdev, &hdev->kernel_cb_mgr, cb->id << PAGE_SHIFT); + + return rc; +} + +/* + * gaudi_init_tpc_mem() - Initialize TPC memories. + * @hdev: Pointer to hl_device structure. + * + * Copy TPC kernel fw from firmware file and run it to initialize TPC memories. + * + * Return: 0 for success, negative value for error. + */ +static int gaudi_init_tpc_mem(struct hl_device *hdev) +{ + const struct firmware *fw; + size_t fw_size; + void *cpu_addr; + dma_addr_t dma_handle; + int rc; + + rc = request_firmware(&fw, GAUDI_TPC_FW_FILE, hdev->dev); + if (rc) { + dev_err(hdev->dev, "Firmware file %s is not found!\n", + GAUDI_TPC_FW_FILE); + goto out; + } + + fw_size = fw->size; + cpu_addr = hdev->asic_funcs->asic_dma_alloc_coherent(hdev, fw_size, + &dma_handle, GFP_KERNEL | __GFP_ZERO); + if (!cpu_addr) { + dev_err(hdev->dev, + "Failed to allocate %zu of dma memory for TPC kernel\n", + fw_size); + rc = -ENOMEM; + goto out; + } + + memcpy(cpu_addr, fw->data, fw_size); + + rc = _gaudi_init_tpc_mem(hdev, dma_handle, fw_size); + + hdev->asic_funcs->asic_dma_free_coherent(hdev, fw->size, cpu_addr, + dma_handle); + +out: + release_firmware(fw); + return rc; +} + +static int gaudi_late_init(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + int rc; + + rc = gaudi->armcp_info_get(hdev); + if (rc) { + dev_err(hdev->dev, "Failed to get armcp info\n"); + return rc; + } + + rc = hl_fw_send_pci_access_msg(hdev, ARMCP_PACKET_ENABLE_PCI_ACCESS); + if (rc) { + dev_err(hdev->dev, "Failed to enable PCI access from CPU\n"); + return rc; + } + + WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, GAUDI_EVENT_INTS_REGISTER); + + gaudi_fetch_psoc_frequency(hdev); + + rc = gaudi_mmu_clear_pgt_range(hdev); + if (rc) { + dev_err(hdev->dev, "Failed to clear MMU page tables range\n"); + goto disable_pci_access; + } + + rc = gaudi_init_tpc_mem(hdev); + if (rc) { + dev_err(hdev->dev, "Failed to initialize TPC memories\n"); + goto disable_pci_access; + } + + return 0; + +disable_pci_access: + hl_fw_send_pci_access_msg(hdev, ARMCP_PACKET_DISABLE_PCI_ACCESS); + + return rc; +} + +static void gaudi_late_fini(struct hl_device *hdev) +{ + const struct hwmon_channel_info **channel_info_arr; + int i = 0; + + if (!hdev->hl_chip_info->info) + return; + + channel_info_arr = hdev->hl_chip_info->info; + + while (channel_info_arr[i]) { + kfree(channel_info_arr[i]->config); + kfree(channel_info_arr[i]); + i++; + } + + kfree(channel_info_arr); + + hdev->hl_chip_info->info = NULL; +} + +static int gaudi_alloc_cpu_accessible_dma_mem(struct hl_device *hdev) +{ + dma_addr_t dma_addr_arr[GAUDI_ALLOC_CPU_MEM_RETRY_CNT] = {}, end_addr; + void *virt_addr_arr[GAUDI_ALLOC_CPU_MEM_RETRY_CNT] = {}; + int i, j, rc = 0; + + /* + * The device CPU works with 40-bits addresses, while bit 39 must be set + * to '1' when accessing the host. + * Bits 49:39 of the full host address are saved for a later + * configuration of the HW to perform extension to 50 bits. + * Because there is a single HW register that holds the extension bits, + * these bits must be identical in all allocated range. + */ + + for (i = 0 ; i < GAUDI_ALLOC_CPU_MEM_RETRY_CNT ; i++) { + virt_addr_arr[i] = + hdev->asic_funcs->asic_dma_alloc_coherent(hdev, + HL_CPU_ACCESSIBLE_MEM_SIZE, + &dma_addr_arr[i], + GFP_KERNEL | __GFP_ZERO); + if (!virt_addr_arr[i]) { + rc = -ENOMEM; + goto free_dma_mem_arr; + } + + end_addr = dma_addr_arr[i] + HL_CPU_ACCESSIBLE_MEM_SIZE - 1; + if (GAUDI_CPU_PCI_MSB_ADDR(dma_addr_arr[i]) == + GAUDI_CPU_PCI_MSB_ADDR(end_addr)) + break; + } + + if (i == GAUDI_ALLOC_CPU_MEM_RETRY_CNT) { + dev_err(hdev->dev, + "MSB of CPU accessible DMA memory are not identical in all range\n"); + rc = -EFAULT; + goto free_dma_mem_arr; + } + + hdev->cpu_accessible_dma_mem = virt_addr_arr[i]; + hdev->cpu_accessible_dma_address = dma_addr_arr[i]; + hdev->cpu_pci_msb_addr = + GAUDI_CPU_PCI_MSB_ADDR(hdev->cpu_accessible_dma_address); + + GAUDI_PCI_TO_CPU_ADDR(hdev->cpu_accessible_dma_address); + +free_dma_mem_arr: + for (j = 0 ; j < i ; j++) + hdev->asic_funcs->asic_dma_free_coherent(hdev, + HL_CPU_ACCESSIBLE_MEM_SIZE, + virt_addr_arr[j], + dma_addr_arr[j]); + + return rc; +} + +static void gaudi_free_internal_qmans_pq_mem(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + struct gaudi_internal_qman_info *q; + u32 i; + + for (i = 0 ; i < GAUDI_QUEUE_ID_SIZE ; i++) { + q = &gaudi->internal_qmans[i]; + if (!q->pq_kernel_addr) + continue; + hdev->asic_funcs->asic_dma_free_coherent(hdev, q->pq_size, + q->pq_kernel_addr, + q->pq_dma_addr); + } +} + +static int gaudi_alloc_internal_qmans_pq_mem(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + struct gaudi_internal_qman_info *q; + int rc, i; + + for (i = 0 ; i < GAUDI_QUEUE_ID_SIZE ; i++) { + if (gaudi_queue_type[i] != QUEUE_TYPE_INT) + continue; + + q = &gaudi->internal_qmans[i]; + + switch (i) { + case GAUDI_QUEUE_ID_DMA_2_0 ... GAUDI_QUEUE_ID_DMA_4_3: + case GAUDI_QUEUE_ID_DMA_6_0 ... GAUDI_QUEUE_ID_DMA_7_3: + q->pq_size = HBM_DMA_QMAN_SIZE_IN_BYTES; + break; + case GAUDI_QUEUE_ID_MME_0_0 ... GAUDI_QUEUE_ID_MME_1_3: + q->pq_size = MME_QMAN_SIZE_IN_BYTES; + break; + case GAUDI_QUEUE_ID_TPC_0_0 ... GAUDI_QUEUE_ID_TPC_7_3: + q->pq_size = TPC_QMAN_SIZE_IN_BYTES; + break; + default: + dev_err(hdev->dev, "Bad internal queue index %d", i); + rc = -EINVAL; + goto free_internal_qmans_pq_mem; + } + + q->pq_kernel_addr = hdev->asic_funcs->asic_dma_alloc_coherent( + hdev, q->pq_size, + &q->pq_dma_addr, + GFP_KERNEL | __GFP_ZERO); + if (!q->pq_kernel_addr) { + rc = -ENOMEM; + goto free_internal_qmans_pq_mem; + } + } + + return 0; + +free_internal_qmans_pq_mem: + gaudi_free_internal_qmans_pq_mem(hdev); + return rc; +} + +static int gaudi_sw_init(struct hl_device *hdev) +{ + struct gaudi_device *gaudi; + u32 i, event_id = 0; + int rc; + + /* Allocate device structure */ + gaudi = kzalloc(sizeof(*gaudi), GFP_KERNEL); + if (!gaudi) + return -ENOMEM; + + for (i = 0 ; i < ARRAY_SIZE(gaudi_irq_map_table) ; i++) { + if (gaudi_irq_map_table[i].valid) { + if (event_id == GAUDI_EVENT_SIZE) { + dev_err(hdev->dev, + "Event array exceeds the limit of %u events\n", + GAUDI_EVENT_SIZE); + rc = -EINVAL; + goto free_gaudi_device; + } + + gaudi->events[event_id++] = + gaudi_irq_map_table[i].fc_id; + } + } + + gaudi->armcp_info_get = gaudi_armcp_info_get; + + gaudi->max_freq_value = GAUDI_MAX_CLK_FREQ; + + hdev->asic_specific = gaudi; + + /* Create DMA pool for small allocations */ + hdev->dma_pool = dma_pool_create(dev_name(hdev->dev), + &hdev->pdev->dev, GAUDI_DMA_POOL_BLK_SIZE, 8, 0); + if (!hdev->dma_pool) { + dev_err(hdev->dev, "failed to create DMA pool\n"); + rc = -ENOMEM; + goto free_gaudi_device; + } + + rc = gaudi_alloc_cpu_accessible_dma_mem(hdev); + if (rc) + goto free_dma_pool; + + hdev->cpu_accessible_dma_pool = gen_pool_create(ilog2(32), -1); + if (!hdev->cpu_accessible_dma_pool) { + dev_err(hdev->dev, + "Failed to create CPU accessible DMA pool\n"); + rc = -ENOMEM; + goto free_cpu_dma_mem; + } + + rc = gen_pool_add(hdev->cpu_accessible_dma_pool, + (uintptr_t) hdev->cpu_accessible_dma_mem, + HL_CPU_ACCESSIBLE_MEM_SIZE, -1); + if (rc) { + dev_err(hdev->dev, + "Failed to add memory to CPU accessible DMA pool\n"); + rc = -EFAULT; + goto free_cpu_accessible_dma_pool; + } + + rc = gaudi_alloc_internal_qmans_pq_mem(hdev); + if (rc) + goto free_cpu_accessible_dma_pool; + + spin_lock_init(&gaudi->hw_queues_lock); + mutex_init(&gaudi->clk_gate_mutex); + + hdev->supports_sync_stream = true; + hdev->supports_coresight = true; + + return 0; + +free_cpu_accessible_dma_pool: + gen_pool_destroy(hdev->cpu_accessible_dma_pool); +free_cpu_dma_mem: + GAUDI_CPU_TO_PCI_ADDR(hdev->cpu_accessible_dma_address, + hdev->cpu_pci_msb_addr); + hdev->asic_funcs->asic_dma_free_coherent(hdev, + HL_CPU_ACCESSIBLE_MEM_SIZE, + hdev->cpu_accessible_dma_mem, + hdev->cpu_accessible_dma_address); +free_dma_pool: + dma_pool_destroy(hdev->dma_pool); +free_gaudi_device: + kfree(gaudi); + return rc; +} + +static int gaudi_sw_fini(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + gaudi_free_internal_qmans_pq_mem(hdev); + + gen_pool_destroy(hdev->cpu_accessible_dma_pool); + + GAUDI_CPU_TO_PCI_ADDR(hdev->cpu_accessible_dma_address, + hdev->cpu_pci_msb_addr); + hdev->asic_funcs->asic_dma_free_coherent(hdev, + HL_CPU_ACCESSIBLE_MEM_SIZE, + hdev->cpu_accessible_dma_mem, + hdev->cpu_accessible_dma_address); + + dma_pool_destroy(hdev->dma_pool); + + mutex_destroy(&gaudi->clk_gate_mutex); + + kfree(gaudi); + + return 0; +} + +static irqreturn_t gaudi_irq_handler_single(int irq, void *arg) +{ + struct hl_device *hdev = arg; + int i; + + if (hdev->disabled) + return IRQ_HANDLED; + + for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) + hl_irq_handler_cq(irq, &hdev->completion_queue[i]); + + hl_irq_handler_eq(irq, &hdev->event_queue); + + return IRQ_HANDLED; +} + +/* + * For backward compatibility, new MSI interrupts should be set after the + * existing CPU and NIC interrupts. + */ +static int gaudi_pci_irq_vector(struct hl_device *hdev, unsigned int nr, + bool cpu_eq) +{ + int msi_vec; + + if ((nr != GAUDI_EVENT_QUEUE_MSI_IDX) && (cpu_eq)) + dev_crit(hdev->dev, "CPU EQ must use IRQ %d\n", + GAUDI_EVENT_QUEUE_MSI_IDX); + + msi_vec = ((nr < GAUDI_EVENT_QUEUE_MSI_IDX) || (cpu_eq)) ? nr : + (nr + NIC_NUMBER_OF_ENGINES + 1); + + return pci_irq_vector(hdev->pdev, msi_vec); +} + +static int gaudi_enable_msi_single(struct hl_device *hdev) +{ + int rc, irq; + + dev_info(hdev->dev, "Working in single MSI IRQ mode\n"); + + irq = gaudi_pci_irq_vector(hdev, 0, false); + rc = request_irq(irq, gaudi_irq_handler_single, 0, + "gaudi single msi", hdev); + if (rc) + dev_err(hdev->dev, + "Failed to request single MSI IRQ\n"); + + return rc; +} + +static int gaudi_enable_msi_multi(struct hl_device *hdev) +{ + int cq_cnt = hdev->asic_prop.completion_queues_count; + int rc, i, irq_cnt_init, irq; + + for (i = 0, irq_cnt_init = 0 ; i < cq_cnt ; i++, irq_cnt_init++) { + irq = gaudi_pci_irq_vector(hdev, i, false); + rc = request_irq(irq, hl_irq_handler_cq, 0, gaudi_irq_name[i], + &hdev->completion_queue[i]); + if (rc) { + dev_err(hdev->dev, "Failed to request IRQ %d", irq); + goto free_irqs; + } + } + + irq = gaudi_pci_irq_vector(hdev, GAUDI_EVENT_QUEUE_MSI_IDX, true); + rc = request_irq(irq, hl_irq_handler_eq, 0, gaudi_irq_name[cq_cnt], + &hdev->event_queue); + if (rc) { + dev_err(hdev->dev, "Failed to request IRQ %d", irq); + goto free_irqs; + } + + return 0; + +free_irqs: + for (i = 0 ; i < irq_cnt_init ; i++) + free_irq(gaudi_pci_irq_vector(hdev, i, false), + &hdev->completion_queue[i]); + return rc; +} + +static int gaudi_enable_msi(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + int rc; + + if (gaudi->hw_cap_initialized & HW_CAP_MSI) + return 0; + + rc = pci_alloc_irq_vectors(hdev->pdev, 1, GAUDI_MSI_ENTRIES, + PCI_IRQ_MSI); + if (rc < 0) { + dev_err(hdev->dev, "MSI: Failed to enable support %d\n", rc); + return rc; + } + + if (rc < NUMBER_OF_INTERRUPTS) { + gaudi->multi_msi_mode = false; + rc = gaudi_enable_msi_single(hdev); + } else { + gaudi->multi_msi_mode = true; + rc = gaudi_enable_msi_multi(hdev); + } + + if (rc) + goto free_pci_irq_vectors; + + gaudi->hw_cap_initialized |= HW_CAP_MSI; + + return 0; + +free_pci_irq_vectors: + pci_free_irq_vectors(hdev->pdev); + return rc; +} + +static void gaudi_sync_irqs(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + int i, cq_cnt = hdev->asic_prop.completion_queues_count; + + if (!(gaudi->hw_cap_initialized & HW_CAP_MSI)) + return; + + /* Wait for all pending IRQs to be finished */ + if (gaudi->multi_msi_mode) { + for (i = 0 ; i < cq_cnt ; i++) + synchronize_irq(gaudi_pci_irq_vector(hdev, i, false)); + + synchronize_irq(gaudi_pci_irq_vector(hdev, + GAUDI_EVENT_QUEUE_MSI_IDX, + true)); + } else { + synchronize_irq(gaudi_pci_irq_vector(hdev, 0, false)); + } +} + +static void gaudi_disable_msi(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + int i, irq, cq_cnt = hdev->asic_prop.completion_queues_count; + + if (!(gaudi->hw_cap_initialized & HW_CAP_MSI)) + return; + + gaudi_sync_irqs(hdev); + + if (gaudi->multi_msi_mode) { + irq = gaudi_pci_irq_vector(hdev, GAUDI_EVENT_QUEUE_MSI_IDX, + true); + free_irq(irq, &hdev->event_queue); + + for (i = 0 ; i < cq_cnt ; i++) { + irq = gaudi_pci_irq_vector(hdev, i, false); + free_irq(irq, &hdev->completion_queue[i]); + } + } else { + free_irq(gaudi_pci_irq_vector(hdev, 0, false), hdev); + } + + pci_free_irq_vectors(hdev->pdev); + + gaudi->hw_cap_initialized &= ~HW_CAP_MSI; +} + +static void gaudi_init_scrambler_sram(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (gaudi->hw_cap_initialized & HW_CAP_SRAM_SCRAMBLER) + return; + + if (!hdev->sram_scrambler_enable) + return; + + WREG32(mmNIF_RTR_CTRL_0_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_1_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_2_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_3_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_4_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_5_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_6_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_7_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + + WREG32(mmSIF_RTR_CTRL_0_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_1_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_2_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_3_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_4_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_5_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_6_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_7_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + + WREG32(mmDMA_IF_E_N_DOWN_CH0_SCRAM_SRAM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_E_N_DOWN_CH1_SCRAM_SRAM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_E_S_DOWN_CH0_SCRAM_SRAM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_E_S_DOWN_CH1_SCRAM_SRAM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_W_N_DOWN_CH0_SCRAM_SRAM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_W_N_DOWN_CH1_SCRAM_SRAM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_W_S_DOWN_CH0_SCRAM_SRAM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_W_S_DOWN_CH1_SCRAM_SRAM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT); + + gaudi->hw_cap_initialized |= HW_CAP_SRAM_SCRAMBLER; +} + +static void gaudi_init_scrambler_hbm(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (gaudi->hw_cap_initialized & HW_CAP_HBM_SCRAMBLER) + return; + + if (!hdev->dram_scrambler_enable) + return; + + WREG32(mmNIF_RTR_CTRL_0_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_1_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_2_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_3_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_4_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_5_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_6_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_7_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + + WREG32(mmSIF_RTR_CTRL_0_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_1_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_2_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_3_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_4_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_5_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_6_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_7_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + + WREG32(mmDMA_IF_E_N_DOWN_CH0_SCRAM_HBM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_E_N_DOWN_CH1_SCRAM_HBM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_E_S_DOWN_CH0_SCRAM_HBM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_E_S_DOWN_CH1_SCRAM_HBM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_W_N_DOWN_CH0_SCRAM_HBM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_W_N_DOWN_CH1_SCRAM_HBM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_W_S_DOWN_CH0_SCRAM_HBM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_W_S_DOWN_CH1_SCRAM_HBM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT); + + gaudi->hw_cap_initialized |= HW_CAP_HBM_SCRAMBLER; +} + +static void gaudi_init_e2e(struct hl_device *hdev) +{ + WREG32(mmSIF_RTR_CTRL_0_E2E_HBM_WR_SIZE, 247 >> 3); + WREG32(mmSIF_RTR_CTRL_0_E2E_HBM_RD_SIZE, 785 >> 3); + WREG32(mmSIF_RTR_CTRL_0_E2E_PCI_WR_SIZE, 49); + WREG32(mmSIF_RTR_CTRL_0_E2E_PCI_RD_SIZE, 101); + + WREG32(mmSIF_RTR_CTRL_1_E2E_HBM_WR_SIZE, 275 >> 3); + WREG32(mmSIF_RTR_CTRL_1_E2E_HBM_RD_SIZE, 614 >> 3); + WREG32(mmSIF_RTR_CTRL_1_E2E_PCI_WR_SIZE, 1); + WREG32(mmSIF_RTR_CTRL_1_E2E_PCI_RD_SIZE, 39); + + WREG32(mmSIF_RTR_CTRL_2_E2E_HBM_WR_SIZE, 1); + WREG32(mmSIF_RTR_CTRL_2_E2E_HBM_RD_SIZE, 1); + WREG32(mmSIF_RTR_CTRL_2_E2E_PCI_WR_SIZE, 1); + WREG32(mmSIF_RTR_CTRL_2_E2E_PCI_RD_SIZE, 32); + + WREG32(mmSIF_RTR_CTRL_3_E2E_HBM_WR_SIZE, 176 >> 3); + WREG32(mmSIF_RTR_CTRL_3_E2E_HBM_RD_SIZE, 32 >> 3); + WREG32(mmSIF_RTR_CTRL_3_E2E_PCI_WR_SIZE, 19); + WREG32(mmSIF_RTR_CTRL_3_E2E_PCI_RD_SIZE, 32); + + WREG32(mmSIF_RTR_CTRL_4_E2E_HBM_WR_SIZE, 176 >> 3); + WREG32(mmSIF_RTR_CTRL_4_E2E_HBM_RD_SIZE, 32 >> 3); + WREG32(mmSIF_RTR_CTRL_4_E2E_PCI_WR_SIZE, 19); + WREG32(mmSIF_RTR_CTRL_4_E2E_PCI_RD_SIZE, 32); + + WREG32(mmSIF_RTR_CTRL_5_E2E_HBM_WR_SIZE, 1); + WREG32(mmSIF_RTR_CTRL_5_E2E_HBM_RD_SIZE, 1); + WREG32(mmSIF_RTR_CTRL_5_E2E_PCI_WR_SIZE, 1); + WREG32(mmSIF_RTR_CTRL_5_E2E_PCI_RD_SIZE, 32); + + WREG32(mmSIF_RTR_CTRL_6_E2E_HBM_WR_SIZE, 275 >> 3); + WREG32(mmSIF_RTR_CTRL_6_E2E_HBM_RD_SIZE, 614 >> 3); + WREG32(mmSIF_RTR_CTRL_6_E2E_PCI_WR_SIZE, 1); + WREG32(mmSIF_RTR_CTRL_6_E2E_PCI_RD_SIZE, 39); + + WREG32(mmSIF_RTR_CTRL_7_E2E_HBM_WR_SIZE, 297 >> 3); + WREG32(mmSIF_RTR_CTRL_7_E2E_HBM_RD_SIZE, 908 >> 3); + WREG32(mmSIF_RTR_CTRL_7_E2E_PCI_WR_SIZE, 19); + WREG32(mmSIF_RTR_CTRL_7_E2E_PCI_RD_SIZE, 19); + + WREG32(mmNIF_RTR_CTRL_0_E2E_HBM_WR_SIZE, 318 >> 3); + WREG32(mmNIF_RTR_CTRL_0_E2E_HBM_RD_SIZE, 956 >> 3); + WREG32(mmNIF_RTR_CTRL_0_E2E_PCI_WR_SIZE, 79); + WREG32(mmNIF_RTR_CTRL_0_E2E_PCI_RD_SIZE, 163); + + WREG32(mmNIF_RTR_CTRL_1_E2E_HBM_WR_SIZE, 275 >> 3); + WREG32(mmNIF_RTR_CTRL_1_E2E_HBM_RD_SIZE, 614 >> 3); + WREG32(mmNIF_RTR_CTRL_1_E2E_PCI_WR_SIZE, 1); + WREG32(mmNIF_RTR_CTRL_1_E2E_PCI_RD_SIZE, 39); + + WREG32(mmNIF_RTR_CTRL_2_E2E_HBM_WR_SIZE, 1); + WREG32(mmNIF_RTR_CTRL_2_E2E_HBM_RD_SIZE, 1); + WREG32(mmNIF_RTR_CTRL_2_E2E_PCI_WR_SIZE, 1); + WREG32(mmNIF_RTR_CTRL_2_E2E_PCI_RD_SIZE, 32); + + WREG32(mmNIF_RTR_CTRL_3_E2E_HBM_WR_SIZE, 176 >> 3); + WREG32(mmNIF_RTR_CTRL_3_E2E_HBM_RD_SIZE, 32 >> 3); + WREG32(mmNIF_RTR_CTRL_3_E2E_PCI_WR_SIZE, 19); + WREG32(mmNIF_RTR_CTRL_3_E2E_PCI_RD_SIZE, 32); + + WREG32(mmNIF_RTR_CTRL_4_E2E_HBM_WR_SIZE, 176 >> 3); + WREG32(mmNIF_RTR_CTRL_4_E2E_HBM_RD_SIZE, 32 >> 3); + WREG32(mmNIF_RTR_CTRL_4_E2E_PCI_WR_SIZE, 19); + WREG32(mmNIF_RTR_CTRL_4_E2E_PCI_RD_SIZE, 32); + + WREG32(mmNIF_RTR_CTRL_5_E2E_HBM_WR_SIZE, 1); + WREG32(mmNIF_RTR_CTRL_5_E2E_HBM_RD_SIZE, 1); + WREG32(mmNIF_RTR_CTRL_5_E2E_PCI_WR_SIZE, 1); + WREG32(mmNIF_RTR_CTRL_5_E2E_PCI_RD_SIZE, 32); + + WREG32(mmNIF_RTR_CTRL_6_E2E_HBM_WR_SIZE, 275 >> 3); + WREG32(mmNIF_RTR_CTRL_6_E2E_HBM_RD_SIZE, 614 >> 3); + WREG32(mmNIF_RTR_CTRL_6_E2E_PCI_WR_SIZE, 1); + WREG32(mmNIF_RTR_CTRL_6_E2E_PCI_RD_SIZE, 39); + + WREG32(mmNIF_RTR_CTRL_7_E2E_HBM_WR_SIZE, 318 >> 3); + WREG32(mmNIF_RTR_CTRL_7_E2E_HBM_RD_SIZE, 956 >> 3); + WREG32(mmNIF_RTR_CTRL_7_E2E_PCI_WR_SIZE, 79); + WREG32(mmNIF_RTR_CTRL_7_E2E_PCI_RD_SIZE, 79); + + WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_WR_SIZE, 344 >> 3); + WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_RD_SIZE, 1000 >> 3); + WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_WR_SIZE, 162); + WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_RD_SIZE, 338); + + WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_WR_SIZE, 344 >> 3); + WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_RD_SIZE, 1000 >> 3); + WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_WR_SIZE, 162); + WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_RD_SIZE, 338); + + WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_WR_SIZE, 344 >> 3); + WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_RD_SIZE, 1000 >> 3); + WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_WR_SIZE, 162); + WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_RD_SIZE, 338); + + WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_WR_SIZE, 344 >> 3); + WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_RD_SIZE, 1000 >> 3); + WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_WR_SIZE, 162); + WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_RD_SIZE, 338); + + WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_WR_SIZE, 344 >> 3); + WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_RD_SIZE, 1000 >> 3); + WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_WR_SIZE, 162); + WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_RD_SIZE, 338); + + WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_WR_SIZE, 344 >> 3); + WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_RD_SIZE, 1000 >> 3); + WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_WR_SIZE, 162); + WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_RD_SIZE, 338); + + WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_WR_SIZE, 344 >> 3); + WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_RD_SIZE, 1000 >> 3); + WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_WR_SIZE, 162); + WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_RD_SIZE, 338); + + WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_WR_SIZE, 344 >> 3); + WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_RD_SIZE, 1000 >> 3); + WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_WR_SIZE, 162); + WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_RD_SIZE, 338); + + if (!hdev->dram_scrambler_enable) { + WREG32(mmSIF_RTR_CTRL_0_NL_HBM_SEL_0, 0x21); + WREG32(mmSIF_RTR_CTRL_0_NL_HBM_SEL_1, 0x22); + WREG32(mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmSIF_RTR_CTRL_0_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmSIF_RTR_CTRL_1_NL_HBM_SEL_0, 0x21); + WREG32(mmSIF_RTR_CTRL_1_NL_HBM_SEL_1, 0x22); + WREG32(mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmSIF_RTR_CTRL_1_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmSIF_RTR_CTRL_2_NL_HBM_SEL_0, 0x21); + WREG32(mmSIF_RTR_CTRL_2_NL_HBM_SEL_1, 0x22); + WREG32(mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmSIF_RTR_CTRL_2_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmSIF_RTR_CTRL_3_NL_HBM_SEL_0, 0x21); + WREG32(mmSIF_RTR_CTRL_3_NL_HBM_SEL_1, 0x22); + WREG32(mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmSIF_RTR_CTRL_3_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmSIF_RTR_CTRL_4_NL_HBM_SEL_0, 0x21); + WREG32(mmSIF_RTR_CTRL_4_NL_HBM_SEL_1, 0x22); + WREG32(mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmSIF_RTR_CTRL_4_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmSIF_RTR_CTRL_5_NL_HBM_SEL_0, 0x21); + WREG32(mmSIF_RTR_CTRL_5_NL_HBM_SEL_1, 0x22); + WREG32(mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmSIF_RTR_CTRL_5_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmSIF_RTR_CTRL_6_NL_HBM_SEL_0, 0x21); + WREG32(mmSIF_RTR_CTRL_6_NL_HBM_SEL_1, 0x22); + WREG32(mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmSIF_RTR_CTRL_6_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmSIF_RTR_CTRL_7_NL_HBM_SEL_0, 0x21); + WREG32(mmSIF_RTR_CTRL_7_NL_HBM_SEL_1, 0x22); + WREG32(mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmSIF_RTR_CTRL_7_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmNIF_RTR_CTRL_0_NL_HBM_SEL_0, 0x21); + WREG32(mmNIF_RTR_CTRL_0_NL_HBM_SEL_1, 0x22); + WREG32(mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmNIF_RTR_CTRL_0_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmNIF_RTR_CTRL_1_NL_HBM_SEL_0, 0x21); + WREG32(mmNIF_RTR_CTRL_1_NL_HBM_SEL_1, 0x22); + WREG32(mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmNIF_RTR_CTRL_1_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmNIF_RTR_CTRL_2_NL_HBM_SEL_0, 0x21); + WREG32(mmNIF_RTR_CTRL_2_NL_HBM_SEL_1, 0x22); + WREG32(mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmNIF_RTR_CTRL_2_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmNIF_RTR_CTRL_3_NL_HBM_SEL_0, 0x21); + WREG32(mmNIF_RTR_CTRL_3_NL_HBM_SEL_1, 0x22); + WREG32(mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmNIF_RTR_CTRL_3_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmNIF_RTR_CTRL_4_NL_HBM_SEL_0, 0x21); + WREG32(mmNIF_RTR_CTRL_4_NL_HBM_SEL_1, 0x22); + WREG32(mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmNIF_RTR_CTRL_4_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmNIF_RTR_CTRL_5_NL_HBM_SEL_0, 0x21); + WREG32(mmNIF_RTR_CTRL_5_NL_HBM_SEL_1, 0x22); + WREG32(mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmNIF_RTR_CTRL_5_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmNIF_RTR_CTRL_6_NL_HBM_SEL_0, 0x21); + WREG32(mmNIF_RTR_CTRL_6_NL_HBM_SEL_1, 0x22); + WREG32(mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmNIF_RTR_CTRL_6_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmNIF_RTR_CTRL_7_NL_HBM_SEL_0, 0x21); + WREG32(mmNIF_RTR_CTRL_7_NL_HBM_SEL_1, 0x22); + WREG32(mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmNIF_RTR_CTRL_7_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmDMA_IF_E_N_DOWN_CH0_NL_HBM_SEL_0, 0x21); + WREG32(mmDMA_IF_E_N_DOWN_CH0_NL_HBM_SEL_1, 0x22); + WREG32(mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmDMA_IF_E_N_DOWN_CH0_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmDMA_IF_E_N_DOWN_CH1_NL_HBM_SEL_0, 0x21); + WREG32(mmDMA_IF_E_N_DOWN_CH1_NL_HBM_SEL_1, 0x22); + WREG32(mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmDMA_IF_E_N_DOWN_CH1_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmDMA_IF_E_S_DOWN_CH0_NL_HBM_SEL_0, 0x21); + WREG32(mmDMA_IF_E_S_DOWN_CH0_NL_HBM_SEL_1, 0x22); + WREG32(mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmDMA_IF_E_S_DOWN_CH0_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmDMA_IF_E_S_DOWN_CH1_NL_HBM_SEL_0, 0x21); + WREG32(mmDMA_IF_E_S_DOWN_CH1_NL_HBM_SEL_1, 0x22); + WREG32(mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmDMA_IF_E_S_DOWN_CH1_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmDMA_IF_W_N_DOWN_CH0_NL_HBM_SEL_0, 0x21); + WREG32(mmDMA_IF_W_N_DOWN_CH0_NL_HBM_SEL_1, 0x22); + WREG32(mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmDMA_IF_W_N_DOWN_CH0_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmDMA_IF_W_N_DOWN_CH1_NL_HBM_SEL_0, 0x21); + WREG32(mmDMA_IF_W_N_DOWN_CH1_NL_HBM_SEL_1, 0x22); + WREG32(mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmDMA_IF_W_N_DOWN_CH1_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmDMA_IF_W_S_DOWN_CH0_NL_HBM_SEL_0, 0x21); + WREG32(mmDMA_IF_W_S_DOWN_CH0_NL_HBM_SEL_1, 0x22); + WREG32(mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmDMA_IF_W_S_DOWN_CH1_NL_HBM_SEL_0, 0x21); + WREG32(mmDMA_IF_W_S_DOWN_CH1_NL_HBM_SEL_1, 0x22); + WREG32(mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_3, 0x20); + } + + WREG32(mmSIF_RTR_CTRL_0_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_0_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmSIF_RTR_CTRL_1_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_1_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmSIF_RTR_CTRL_2_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_2_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmSIF_RTR_CTRL_3_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_3_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmSIF_RTR_CTRL_4_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_4_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmSIF_RTR_CTRL_5_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_5_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmSIF_RTR_CTRL_6_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_6_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmSIF_RTR_CTRL_7_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_7_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmNIF_RTR_CTRL_0_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_0_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmNIF_RTR_CTRL_1_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_1_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmNIF_RTR_CTRL_2_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_2_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmNIF_RTR_CTRL_3_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_3_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmNIF_RTR_CTRL_4_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_4_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmNIF_RTR_CTRL_5_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_5_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmNIF_RTR_CTRL_6_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_6_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmNIF_RTR_CTRL_7_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_7_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_EN, + 1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_EN, + 1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_EN, + 1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_EN, + 1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_EN, + 1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_EN, + 1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_EN, + 1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_EN, + 1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_EN, + 1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_EN, + 1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_EN, + 1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_EN, + 1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_EN, + 1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_EN, + 1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_EN, + 1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_EN, + 1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT); +} + +static void gaudi_init_hbm_cred(struct hl_device *hdev) +{ + uint32_t hbm0_wr, hbm1_wr, hbm0_rd, hbm1_rd; + + hbm0_wr = 0x33333333; + hbm1_wr = 0x33333333; + hbm0_rd = 0x77777777; + hbm1_rd = 0xDDDDDDDD; + + WREG32(mmDMA_IF_E_N_HBM0_WR_CRED_CNT, hbm0_wr); + WREG32(mmDMA_IF_E_N_HBM1_WR_CRED_CNT, hbm1_wr); + WREG32(mmDMA_IF_E_N_HBM0_RD_CRED_CNT, hbm0_rd); + WREG32(mmDMA_IF_E_N_HBM1_RD_CRED_CNT, hbm1_rd); + + WREG32(mmDMA_IF_E_S_HBM0_WR_CRED_CNT, hbm0_wr); + WREG32(mmDMA_IF_E_S_HBM1_WR_CRED_CNT, hbm1_wr); + WREG32(mmDMA_IF_E_S_HBM0_RD_CRED_CNT, hbm0_rd); + WREG32(mmDMA_IF_E_S_HBM1_RD_CRED_CNT, hbm1_rd); + + WREG32(mmDMA_IF_W_N_HBM0_WR_CRED_CNT, hbm0_wr); + WREG32(mmDMA_IF_W_N_HBM1_WR_CRED_CNT, hbm1_wr); + WREG32(mmDMA_IF_W_N_HBM0_RD_CRED_CNT, hbm0_rd); + WREG32(mmDMA_IF_W_N_HBM1_RD_CRED_CNT, hbm1_rd); + + WREG32(mmDMA_IF_W_S_HBM0_WR_CRED_CNT, hbm0_wr); + WREG32(mmDMA_IF_W_S_HBM1_WR_CRED_CNT, hbm1_wr); + WREG32(mmDMA_IF_W_S_HBM0_RD_CRED_CNT, hbm0_rd); + WREG32(mmDMA_IF_W_S_HBM1_RD_CRED_CNT, hbm1_rd); + + WREG32(mmDMA_IF_E_N_HBM_CRED_EN_0, + (1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) | + (1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT)); + WREG32(mmDMA_IF_E_S_HBM_CRED_EN_0, + (1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) | + (1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT)); + WREG32(mmDMA_IF_W_N_HBM_CRED_EN_0, + (1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) | + (1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT)); + WREG32(mmDMA_IF_W_S_HBM_CRED_EN_0, + (1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) | + (1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT)); + + WREG32(mmDMA_IF_E_N_HBM_CRED_EN_1, + (1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) | + (1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT)); + WREG32(mmDMA_IF_E_S_HBM_CRED_EN_1, + (1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) | + (1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT)); + WREG32(mmDMA_IF_W_N_HBM_CRED_EN_1, + (1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) | + (1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT)); + WREG32(mmDMA_IF_W_S_HBM_CRED_EN_1, + (1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) | + (1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT)); +} + +static void gaudi_init_rate_limiter(struct hl_device *hdev) +{ + u32 nr, nf, od, sat, rst, timeout; + u64 freq; + + nr = RREG32(mmPSOC_HBM_PLL_NR); + nf = RREG32(mmPSOC_HBM_PLL_NF); + od = RREG32(mmPSOC_HBM_PLL_OD); + freq = (50 * (nf + 1)) / ((nr + 1) * (od + 1)); + + dev_dbg(hdev->dev, "HBM frequency is %lluMHz\n", freq); + + /* Configuration is for five (5) DDMA channels */ + if (freq == 800) { + sat = 4; + rst = 11; + timeout = 15; + } else if (freq == 900) { + sat = 4; + rst = 15; + timeout = 16; + } else if (freq == 950) { + sat = 4; + rst = 15; + timeout = 15; + } else { + dev_warn(hdev->dev, + "unsupported HBM frequency %lluMHz, no rate-limiters\n", + freq); + return; + } + + WREG32(mmDMA_IF_W_S_DOWN_RSP_MID_WGHT_0, 0x111); + WREG32(mmDMA_IF_W_S_DOWN_RSP_MID_WGHT_1, 0x111); + WREG32(mmDMA_IF_E_S_DOWN_RSP_MID_WGHT_0, 0x111); + WREG32(mmDMA_IF_E_S_DOWN_RSP_MID_WGHT_1, 0x111); + WREG32(mmDMA_IF_W_N_DOWN_RSP_MID_WGHT_0, 0x111); + WREG32(mmDMA_IF_W_N_DOWN_RSP_MID_WGHT_1, 0x111); + WREG32(mmDMA_IF_E_N_DOWN_RSP_MID_WGHT_0, 0x111); + WREG32(mmDMA_IF_E_N_DOWN_RSP_MID_WGHT_1, 0x111); + + if (!hdev->rl_enable) { + dev_info(hdev->dev, "Rate limiters disabled\n"); + return; + } + + WREG32(mmDMA_IF_W_S_DOWN_CH0_RL_HBM_SAT, sat); + WREG32(mmDMA_IF_W_S_DOWN_CH1_RL_HBM_SAT, sat); + WREG32(mmDMA_IF_E_S_DOWN_CH0_RL_HBM_SAT, sat); + WREG32(mmDMA_IF_E_S_DOWN_CH1_RL_HBM_SAT, sat); + WREG32(mmDMA_IF_W_N_DOWN_CH0_RL_HBM_SAT, sat); + WREG32(mmDMA_IF_W_N_DOWN_CH1_RL_HBM_SAT, sat); + WREG32(mmDMA_IF_E_N_DOWN_CH0_RL_HBM_SAT, sat); + WREG32(mmDMA_IF_E_N_DOWN_CH1_RL_HBM_SAT, sat); + + WREG32(mmDMA_IF_W_S_DOWN_CH0_RL_HBM_RST, rst); + WREG32(mmDMA_IF_W_S_DOWN_CH1_RL_HBM_RST, rst); + WREG32(mmDMA_IF_E_S_DOWN_CH0_RL_HBM_RST, rst); + WREG32(mmDMA_IF_E_S_DOWN_CH1_RL_HBM_RST, rst); + WREG32(mmDMA_IF_W_N_DOWN_CH0_RL_HBM_RST, rst); + WREG32(mmDMA_IF_W_N_DOWN_CH1_RL_HBM_RST, rst); + WREG32(mmDMA_IF_E_N_DOWN_CH0_RL_HBM_RST, rst); + WREG32(mmDMA_IF_E_N_DOWN_CH1_RL_HBM_RST, rst); + + WREG32(mmDMA_IF_W_S_DOWN_CH0_RL_HBM_TIMEOUT, timeout); + WREG32(mmDMA_IF_W_S_DOWN_CH1_RL_HBM_TIMEOUT, timeout); + WREG32(mmDMA_IF_E_S_DOWN_CH0_RL_HBM_TIMEOUT, timeout); + WREG32(mmDMA_IF_E_S_DOWN_CH1_RL_HBM_TIMEOUT, timeout); + WREG32(mmDMA_IF_W_N_DOWN_CH0_RL_HBM_TIMEOUT, timeout); + WREG32(mmDMA_IF_W_N_DOWN_CH1_RL_HBM_TIMEOUT, timeout); + WREG32(mmDMA_IF_E_N_DOWN_CH0_RL_HBM_TIMEOUT, timeout); + WREG32(mmDMA_IF_E_N_DOWN_CH1_RL_HBM_TIMEOUT, timeout); + + WREG32(mmDMA_IF_W_S_DOWN_CH0_RL_HBM_EN, 1); + WREG32(mmDMA_IF_W_S_DOWN_CH1_RL_HBM_EN, 1); + WREG32(mmDMA_IF_E_S_DOWN_CH0_RL_HBM_EN, 1); + WREG32(mmDMA_IF_E_S_DOWN_CH1_RL_HBM_EN, 1); + WREG32(mmDMA_IF_W_N_DOWN_CH0_RL_HBM_EN, 1); + WREG32(mmDMA_IF_W_N_DOWN_CH1_RL_HBM_EN, 1); + WREG32(mmDMA_IF_E_N_DOWN_CH0_RL_HBM_EN, 1); + WREG32(mmDMA_IF_E_N_DOWN_CH1_RL_HBM_EN, 1); + + WREG32(mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_SAT, sat); + WREG32(mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_SAT, sat); + WREG32(mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_SAT, sat); + WREG32(mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_SAT, sat); + WREG32(mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_SAT, sat); + WREG32(mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_SAT, sat); + WREG32(mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_SAT, sat); + WREG32(mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_SAT, sat); + + WREG32(mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_RST, rst); + WREG32(mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_RST, rst); + WREG32(mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_RST, rst); + WREG32(mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_RST, rst); + WREG32(mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_RST, rst); + WREG32(mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_RST, rst); + WREG32(mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_RST, rst); + WREG32(mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_RST, rst); + + WREG32(mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_TIMEOUT, timeout); + WREG32(mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_TIMEOUT, timeout); + WREG32(mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_TIMEOUT, timeout); + WREG32(mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_TIMEOUT, timeout); + WREG32(mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_TIMEOUT, timeout); + WREG32(mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_TIMEOUT, timeout); + WREG32(mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_TIMEOUT, timeout); + WREG32(mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_TIMEOUT, timeout); + + WREG32(mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_EN, 1); + WREG32(mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_EN, 1); + WREG32(mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_EN, 1); + WREG32(mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_EN, 1); + WREG32(mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_EN, 1); + WREG32(mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_EN, 1); + WREG32(mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_EN, 1); + WREG32(mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_EN, 1); +} + +static void gaudi_init_golden_registers(struct hl_device *hdev) +{ + u32 tpc_offset; + int tpc_id, i; + + gaudi_init_e2e(hdev); + + gaudi_init_hbm_cred(hdev); + + gaudi_init_rate_limiter(hdev); + + gaudi_disable_clock_gating(hdev); + + for (tpc_id = 0, tpc_offset = 0; + tpc_id < TPC_NUMBER_OF_ENGINES; + tpc_id++, tpc_offset += TPC_CFG_OFFSET) { + /* Mask all arithmetic interrupts from TPC */ + WREG32(mmTPC0_CFG_TPC_INTR_MASK + tpc_offset, 0x8FFF); + /* Set 16 cache lines */ + WREG32_FIELD(TPC0_CFG_MSS_CONFIG, tpc_offset, + ICACHE_FETCH_LINE_NUM, 2); + } + + /* Make sure 1st 128 bytes in SRAM are 0 for Tensor DMA */ + for (i = 0 ; i < 128 ; i += 8) + writeq(0, hdev->pcie_bar[SRAM_BAR_ID] + i); + + WREG32(mmMME0_CTRL_EUS_ROLLUP_CNT_ADD, 3); + WREG32(mmMME1_CTRL_EUS_ROLLUP_CNT_ADD, 3); + WREG32(mmMME2_CTRL_EUS_ROLLUP_CNT_ADD, 3); + WREG32(mmMME3_CTRL_EUS_ROLLUP_CNT_ADD, 3); + + /* WA for H3-2081 */ + WREG32(mmPCIE_WRAP_MAX_OUTSTAND, 0x10ff); +} + +static void gaudi_init_pci_dma_qman(struct hl_device *hdev, int dma_id, + int qman_id, dma_addr_t qman_pq_addr) +{ + u32 mtr_base_en_lo, mtr_base_en_hi, mtr_base_ws_lo, mtr_base_ws_hi; + u32 so_base_en_lo, so_base_en_hi, so_base_ws_lo, so_base_ws_hi; + u32 q_off, dma_qm_offset; + u32 dma_qm_err_cfg; + + dma_qm_offset = dma_id * DMA_QMAN_OFFSET; + + mtr_base_en_lo = lower_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0); + mtr_base_en_hi = upper_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0); + so_base_en_lo = lower_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0); + so_base_en_hi = upper_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0); + mtr_base_ws_lo = lower_32_bits(CFG_BASE + + mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0); + mtr_base_ws_hi = upper_32_bits(CFG_BASE + + mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0); + so_base_ws_lo = lower_32_bits(CFG_BASE + + mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0); + so_base_ws_hi = upper_32_bits(CFG_BASE + + mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0); + + q_off = dma_qm_offset + qman_id * 4; + + WREG32(mmDMA0_QM_PQ_BASE_LO_0 + q_off, lower_32_bits(qman_pq_addr)); + WREG32(mmDMA0_QM_PQ_BASE_HI_0 + q_off, upper_32_bits(qman_pq_addr)); + + WREG32(mmDMA0_QM_PQ_SIZE_0 + q_off, ilog2(HL_QUEUE_LENGTH)); + WREG32(mmDMA0_QM_PQ_PI_0 + q_off, 0); + WREG32(mmDMA0_QM_PQ_CI_0 + q_off, 0); + + WREG32(mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off, 0x74); + WREG32(mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off, 0x14); + WREG32(mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off, 0x1C); + + WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_en_lo); + WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_en_hi); + WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_en_lo); + WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_en_hi); + WREG32(mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 + q_off, mtr_base_ws_lo); + WREG32(mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 + q_off, mtr_base_ws_hi); + WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 + q_off, so_base_ws_lo); + WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 + q_off, so_base_ws_hi); + + /* The following configuration is needed only once per QMAN */ + if (qman_id == 0) { + /* Configure RAZWI IRQ */ + dma_qm_err_cfg = PCI_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK; + if (hdev->stop_on_err) { + dma_qm_err_cfg |= + PCI_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK; + } + + WREG32(mmDMA0_QM_GLBL_ERR_CFG + dma_qm_offset, dma_qm_err_cfg); + WREG32(mmDMA0_QM_GLBL_ERR_ADDR_LO + dma_qm_offset, + lower_32_bits(CFG_BASE + + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); + WREG32(mmDMA0_QM_GLBL_ERR_ADDR_HI + dma_qm_offset, + upper_32_bits(CFG_BASE + + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); + WREG32(mmDMA0_QM_GLBL_ERR_WDATA + dma_qm_offset, + gaudi_irq_map_table[GAUDI_EVENT_DMA0_QM].cpu_id + + dma_id); + + WREG32(mmDMA0_QM_ARB_ERR_MSG_EN + dma_qm_offset, + QM_ARB_ERR_MSG_EN_MASK); + + /* Increase ARB WDT to support streams architecture */ + WREG32(mmDMA0_QM_ARB_SLV_CHOISE_WDT + dma_qm_offset, + GAUDI_ARB_WDT_TIMEOUT); + + WREG32(mmDMA0_QM_GLBL_PROT + dma_qm_offset, + QMAN_EXTERNAL_MAKE_TRUSTED); + + WREG32(mmDMA0_QM_GLBL_CFG1 + dma_qm_offset, 0); + } +} + +static void gaudi_init_dma_core(struct hl_device *hdev, int dma_id) +{ + u32 dma_offset = dma_id * DMA_CORE_OFFSET; + u32 dma_err_cfg = 1 << DMA0_CORE_ERR_CFG_ERR_MSG_EN_SHIFT; + + /* Set to maximum possible according to physical size */ + WREG32(mmDMA0_CORE_RD_MAX_OUTSTAND + dma_offset, 0); + WREG32(mmDMA0_CORE_RD_MAX_SIZE + dma_offset, 0); + + /* STOP_ON bit implies no completion to operation in case of RAZWI */ + if (hdev->stop_on_err) + dma_err_cfg |= 1 << DMA0_CORE_ERR_CFG_STOP_ON_ERR_SHIFT; + + WREG32(mmDMA0_CORE_ERR_CFG + dma_offset, dma_err_cfg); + WREG32(mmDMA0_CORE_ERRMSG_ADDR_LO + dma_offset, + lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); + WREG32(mmDMA0_CORE_ERRMSG_ADDR_HI + dma_offset, + upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); + WREG32(mmDMA0_CORE_ERRMSG_WDATA + dma_offset, + gaudi_irq_map_table[GAUDI_EVENT_DMA0_CORE].cpu_id + dma_id); + WREG32(mmDMA0_CORE_PROT + dma_offset, + 1 << DMA0_CORE_PROT_ERR_VAL_SHIFT); + /* If the channel is secured, it should be in MMU bypass mode */ + WREG32(mmDMA0_CORE_SECURE_PROPS + dma_offset, + 1 << DMA0_CORE_SECURE_PROPS_MMBP_SHIFT); + WREG32(mmDMA0_CORE_CFG_0 + dma_offset, 1 << DMA0_CORE_CFG_0_EN_SHIFT); +} + +static void gaudi_enable_qman(struct hl_device *hdev, int dma_id, + u32 enable_mask) +{ + u32 dma_qm_offset = dma_id * DMA_QMAN_OFFSET; + + WREG32(mmDMA0_QM_GLBL_CFG0 + dma_qm_offset, enable_mask); +} + +static void gaudi_init_pci_dma_qmans(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + struct hl_hw_queue *q; + int i, j, dma_id, cpu_skip, nic_skip, cq_id = 0, q_idx, msi_vec = 0; + + if (gaudi->hw_cap_initialized & HW_CAP_PCI_DMA) + return; + + for (i = 0 ; i < PCI_DMA_NUMBER_OF_CHNLS ; i++) { + dma_id = gaudi_dma_assignment[i]; + /* + * For queues after the CPU Q need to add 1 to get the correct + * queue. In addition, need to add the CPU EQ and NIC IRQs in + * order to get the correct MSI register. + */ + if (dma_id > 1) { + cpu_skip = 1; + nic_skip = NIC_NUMBER_OF_ENGINES; + } else { + cpu_skip = 0; + nic_skip = 0; + } + + for (j = 0 ; j < QMAN_STREAMS ; j++) { + q_idx = 4 * dma_id + j + cpu_skip; + q = &hdev->kernel_queues[q_idx]; + q->cq_id = cq_id++; + q->msi_vec = nic_skip + cpu_skip + msi_vec++; + gaudi_init_pci_dma_qman(hdev, dma_id, j, + q->bus_address); + } + + gaudi_init_dma_core(hdev, dma_id); + + gaudi_enable_qman(hdev, dma_id, PCI_DMA_QMAN_ENABLE); + } + + gaudi->hw_cap_initialized |= HW_CAP_PCI_DMA; +} + +static void gaudi_init_hbm_dma_qman(struct hl_device *hdev, int dma_id, + int qman_id, u64 qman_base_addr) +{ + u32 mtr_base_lo, mtr_base_hi; + u32 so_base_lo, so_base_hi; + u32 q_off, dma_qm_offset; + u32 dma_qm_err_cfg; + + dma_qm_offset = dma_id * DMA_QMAN_OFFSET; + + mtr_base_lo = lower_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0); + mtr_base_hi = upper_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0); + so_base_lo = lower_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0); + so_base_hi = upper_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0); + + q_off = dma_qm_offset + qman_id * 4; + + if (qman_id < 4) { + WREG32(mmDMA0_QM_PQ_BASE_LO_0 + q_off, + lower_32_bits(qman_base_addr)); + WREG32(mmDMA0_QM_PQ_BASE_HI_0 + q_off, + upper_32_bits(qman_base_addr)); + + WREG32(mmDMA0_QM_PQ_SIZE_0 + q_off, ilog2(HBM_DMA_QMAN_LENGTH)); + WREG32(mmDMA0_QM_PQ_PI_0 + q_off, 0); + WREG32(mmDMA0_QM_PQ_CI_0 + q_off, 0); + + WREG32(mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off, 0x81BC); + WREG32(mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off, 0x81B4); + WREG32(mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off, 0x1C); + } else { + WREG32(mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off, 0x74); + WREG32(mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off, 0x14); + WREG32(mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off, 0x1C); + + /* Configure RAZWI IRQ */ + dma_qm_err_cfg = HBM_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK; + if (hdev->stop_on_err) { + dma_qm_err_cfg |= + HBM_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK; + } + WREG32(mmDMA0_QM_GLBL_ERR_CFG + dma_qm_offset, dma_qm_err_cfg); + + WREG32(mmDMA0_QM_GLBL_ERR_ADDR_LO + dma_qm_offset, + lower_32_bits(CFG_BASE + + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); + WREG32(mmDMA0_QM_GLBL_ERR_ADDR_HI + dma_qm_offset, + upper_32_bits(CFG_BASE + + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); + WREG32(mmDMA0_QM_GLBL_ERR_WDATA + dma_qm_offset, + gaudi_irq_map_table[GAUDI_EVENT_DMA0_QM].cpu_id + + dma_id); + + WREG32(mmDMA0_QM_ARB_ERR_MSG_EN + dma_qm_offset, + QM_ARB_ERR_MSG_EN_MASK); + + /* Increase ARB WDT to support streams architecture */ + WREG32(mmDMA0_QM_ARB_SLV_CHOISE_WDT + dma_qm_offset, + GAUDI_ARB_WDT_TIMEOUT); + + WREG32(mmDMA0_QM_GLBL_CFG1 + dma_qm_offset, 0); + WREG32(mmDMA0_QM_GLBL_PROT + dma_qm_offset, + QMAN_INTERNAL_MAKE_TRUSTED); + } + + WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_lo); + WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_hi); + WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_lo); + WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_hi); +} + +static void gaudi_init_hbm_dma_qmans(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + struct gaudi_internal_qman_info *q; + u64 qman_base_addr; + int i, j, dma_id, internal_q_index; + + if (gaudi->hw_cap_initialized & HW_CAP_HBM_DMA) + return; + + for (i = 0 ; i < HBM_DMA_NUMBER_OF_CHNLS ; i++) { + dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_1 + i]; + + for (j = 0 ; j < QMAN_STREAMS ; j++) { + /* + * Add the CPU queue in order to get the correct queue + * number as all internal queue are placed after it + */ + internal_q_index = dma_id * QMAN_STREAMS + j + 1; + + q = &gaudi->internal_qmans[internal_q_index]; + qman_base_addr = (u64) q->pq_dma_addr; + gaudi_init_hbm_dma_qman(hdev, dma_id, j, + qman_base_addr); + } + + /* Initializing lower CP for HBM DMA QMAN */ + gaudi_init_hbm_dma_qman(hdev, dma_id, 4, 0); + + gaudi_init_dma_core(hdev, dma_id); + + gaudi_enable_qman(hdev, dma_id, HBM_DMA_QMAN_ENABLE); + } + + gaudi->hw_cap_initialized |= HW_CAP_HBM_DMA; +} + +static void gaudi_init_mme_qman(struct hl_device *hdev, u32 mme_offset, + int qman_id, u64 qman_base_addr) +{ + u32 mtr_base_lo, mtr_base_hi; + u32 so_base_lo, so_base_hi; + u32 q_off, mme_id; + u32 mme_qm_err_cfg; + + mtr_base_lo = lower_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0); + mtr_base_hi = upper_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0); + so_base_lo = lower_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0); + so_base_hi = upper_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0); + + q_off = mme_offset + qman_id * 4; + + if (qman_id < 4) { + WREG32(mmMME0_QM_PQ_BASE_LO_0 + q_off, + lower_32_bits(qman_base_addr)); + WREG32(mmMME0_QM_PQ_BASE_HI_0 + q_off, + upper_32_bits(qman_base_addr)); + + WREG32(mmMME0_QM_PQ_SIZE_0 + q_off, ilog2(MME_QMAN_LENGTH)); + WREG32(mmMME0_QM_PQ_PI_0 + q_off, 0); + WREG32(mmMME0_QM_PQ_CI_0 + q_off, 0); + + WREG32(mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off, 0x81BC); + WREG32(mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off, 0x81B4); + WREG32(mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off, 0x1C); + } else { + WREG32(mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off, 0x74); + WREG32(mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off, 0x14); + WREG32(mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off, 0x1C); + + /* Configure RAZWI IRQ */ + mme_id = mme_offset / + (mmMME1_QM_GLBL_CFG0 - mmMME0_QM_GLBL_CFG0); + + mme_qm_err_cfg = MME_QMAN_GLBL_ERR_CFG_MSG_EN_MASK; + if (hdev->stop_on_err) { + mme_qm_err_cfg |= + MME_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK; + } + WREG32(mmMME0_QM_GLBL_ERR_CFG + mme_offset, mme_qm_err_cfg); + WREG32(mmMME0_QM_GLBL_ERR_ADDR_LO + mme_offset, + lower_32_bits(CFG_BASE + + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); + WREG32(mmMME0_QM_GLBL_ERR_ADDR_HI + mme_offset, + upper_32_bits(CFG_BASE + + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); + WREG32(mmMME0_QM_GLBL_ERR_WDATA + mme_offset, + gaudi_irq_map_table[GAUDI_EVENT_MME0_QM].cpu_id + + mme_id); + + WREG32(mmMME0_QM_ARB_ERR_MSG_EN + mme_offset, + QM_ARB_ERR_MSG_EN_MASK); + + /* Increase ARB WDT to support streams architecture */ + WREG32(mmMME0_QM_ARB_SLV_CHOISE_WDT + mme_offset, + GAUDI_ARB_WDT_TIMEOUT); + + WREG32(mmMME0_QM_GLBL_CFG1 + mme_offset, 0); + WREG32(mmMME0_QM_GLBL_PROT + mme_offset, + QMAN_INTERNAL_MAKE_TRUSTED); + } + + WREG32(mmMME0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_lo); + WREG32(mmMME0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_hi); + WREG32(mmMME0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_lo); + WREG32(mmMME0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_hi); +} + +static void gaudi_init_mme_qmans(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + struct gaudi_internal_qman_info *q; + u64 qman_base_addr; + u32 mme_offset; + int i, internal_q_index; + + if (gaudi->hw_cap_initialized & HW_CAP_MME) + return; + + /* + * map GAUDI_QUEUE_ID_MME_0_X to the N_W_MME (mmMME2_QM_BASE) + * and GAUDI_QUEUE_ID_MME_1_X to the S_W_MME (mmMME0_QM_BASE) + */ + + mme_offset = mmMME2_QM_GLBL_CFG0 - mmMME0_QM_GLBL_CFG0; + + for (i = 0 ; i < MME_NUMBER_OF_QMANS ; i++) { + internal_q_index = GAUDI_QUEUE_ID_MME_0_0 + i; + q = &gaudi->internal_qmans[internal_q_index]; + qman_base_addr = (u64) q->pq_dma_addr; + gaudi_init_mme_qman(hdev, mme_offset, (i & 0x3), + qman_base_addr); + if (i == 3) + mme_offset = 0; + } + + /* Initializing lower CP for MME QMANs */ + mme_offset = mmMME2_QM_GLBL_CFG0 - mmMME0_QM_GLBL_CFG0; + gaudi_init_mme_qman(hdev, mme_offset, 4, 0); + gaudi_init_mme_qman(hdev, 0, 4, 0); + + WREG32(mmMME2_QM_GLBL_CFG0, QMAN_MME_ENABLE); + WREG32(mmMME0_QM_GLBL_CFG0, QMAN_MME_ENABLE); + + gaudi->hw_cap_initialized |= HW_CAP_MME; +} + +static void gaudi_init_tpc_qman(struct hl_device *hdev, u32 tpc_offset, + int qman_id, u64 qman_base_addr) +{ + u32 mtr_base_lo, mtr_base_hi; + u32 so_base_lo, so_base_hi; + u32 q_off, tpc_id; + u32 tpc_qm_err_cfg; + + mtr_base_lo = lower_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0); + mtr_base_hi = upper_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0); + so_base_lo = lower_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0); + so_base_hi = upper_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0); + + q_off = tpc_offset + qman_id * 4; + + if (qman_id < 4) { + WREG32(mmTPC0_QM_PQ_BASE_LO_0 + q_off, + lower_32_bits(qman_base_addr)); + WREG32(mmTPC0_QM_PQ_BASE_HI_0 + q_off, + upper_32_bits(qman_base_addr)); + + WREG32(mmTPC0_QM_PQ_SIZE_0 + q_off, ilog2(TPC_QMAN_LENGTH)); + WREG32(mmTPC0_QM_PQ_PI_0 + q_off, 0); + WREG32(mmTPC0_QM_PQ_CI_0 + q_off, 0); + + WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off, 0x81BC); + WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off, 0x81B4); + WREG32(mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off, 0x1C); + } else { + WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off, 0x74); + WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off, 0x14); + WREG32(mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off, 0x1C); + + /* Configure RAZWI IRQ */ + tpc_id = tpc_offset / + (mmTPC1_QM_GLBL_CFG0 - mmTPC0_QM_GLBL_CFG0); + + tpc_qm_err_cfg = TPC_QMAN_GLBL_ERR_CFG_MSG_EN_MASK; + if (hdev->stop_on_err) { + tpc_qm_err_cfg |= + TPC_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK; + } + + WREG32(mmTPC0_QM_GLBL_ERR_CFG + tpc_offset, tpc_qm_err_cfg); + WREG32(mmTPC0_QM_GLBL_ERR_ADDR_LO + tpc_offset, + lower_32_bits(CFG_BASE + + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); + WREG32(mmTPC0_QM_GLBL_ERR_ADDR_HI + tpc_offset, + upper_32_bits(CFG_BASE + + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); + WREG32(mmTPC0_QM_GLBL_ERR_WDATA + tpc_offset, + gaudi_irq_map_table[GAUDI_EVENT_TPC0_QM].cpu_id + + tpc_id); + + WREG32(mmTPC0_QM_ARB_ERR_MSG_EN + tpc_offset, + QM_ARB_ERR_MSG_EN_MASK); + + /* Increase ARB WDT to support streams architecture */ + WREG32(mmTPC0_QM_ARB_SLV_CHOISE_WDT + tpc_offset, + GAUDI_ARB_WDT_TIMEOUT); + + WREG32(mmTPC0_QM_GLBL_CFG1 + tpc_offset, 0); + WREG32(mmTPC0_QM_GLBL_PROT + tpc_offset, + QMAN_INTERNAL_MAKE_TRUSTED); + } + + WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_lo); + WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_hi); + WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_lo); + WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_hi); +} + +static void gaudi_init_tpc_qmans(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + struct gaudi_internal_qman_info *q; + u64 qman_base_addr; + u32 so_base_hi, tpc_offset = 0; + u32 tpc_delta = mmTPC1_CFG_SM_BASE_ADDRESS_HIGH - + mmTPC0_CFG_SM_BASE_ADDRESS_HIGH; + int i, tpc_id, internal_q_index; + + if (gaudi->hw_cap_initialized & HW_CAP_TPC_MASK) + return; + + so_base_hi = upper_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0); + + for (tpc_id = 0 ; tpc_id < TPC_NUMBER_OF_ENGINES ; tpc_id++) { + for (i = 0 ; i < QMAN_STREAMS ; i++) { + internal_q_index = GAUDI_QUEUE_ID_TPC_0_0 + + tpc_id * QMAN_STREAMS + i; + q = &gaudi->internal_qmans[internal_q_index]; + qman_base_addr = (u64) q->pq_dma_addr; + gaudi_init_tpc_qman(hdev, tpc_offset, i, + qman_base_addr); + + if (i == 3) { + /* Initializing lower CP for TPC QMAN */ + gaudi_init_tpc_qman(hdev, tpc_offset, 4, 0); + + /* Enable the QMAN and TPC channel */ + WREG32(mmTPC0_QM_GLBL_CFG0 + tpc_offset, + QMAN_TPC_ENABLE); + } + } + + WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_HIGH + tpc_id * tpc_delta, + so_base_hi); + + tpc_offset += mmTPC1_QM_GLBL_CFG0 - mmTPC0_QM_GLBL_CFG0; + + gaudi->hw_cap_initialized |= 1 << (HW_CAP_TPC_SHIFT + tpc_id); + } +} + +static void gaudi_disable_pci_dma_qmans(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_PCI_DMA)) + return; + + WREG32(mmDMA0_QM_GLBL_CFG0, 0); + WREG32(mmDMA1_QM_GLBL_CFG0, 0); + WREG32(mmDMA5_QM_GLBL_CFG0, 0); +} + +static void gaudi_disable_hbm_dma_qmans(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_HBM_DMA)) + return; + + WREG32(mmDMA2_QM_GLBL_CFG0, 0); + WREG32(mmDMA3_QM_GLBL_CFG0, 0); + WREG32(mmDMA4_QM_GLBL_CFG0, 0); + WREG32(mmDMA6_QM_GLBL_CFG0, 0); + WREG32(mmDMA7_QM_GLBL_CFG0, 0); +} + +static void gaudi_disable_mme_qmans(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_MME)) + return; + + WREG32(mmMME2_QM_GLBL_CFG0, 0); + WREG32(mmMME0_QM_GLBL_CFG0, 0); +} + +static void gaudi_disable_tpc_qmans(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + u32 tpc_offset = 0; + int tpc_id; + + if (!(gaudi->hw_cap_initialized & HW_CAP_TPC_MASK)) + return; + + for (tpc_id = 0 ; tpc_id < TPC_NUMBER_OF_ENGINES ; tpc_id++) { + WREG32(mmTPC0_QM_GLBL_CFG0 + tpc_offset, 0); + tpc_offset += mmTPC1_QM_GLBL_CFG0 - mmTPC0_QM_GLBL_CFG0; + } +} + +static void gaudi_stop_pci_dma_qmans(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_PCI_DMA)) + return; + + /* Stop upper CPs of QMANs 0.0 to 1.3 and 5.0 to 5.3 */ + WREG32(mmDMA0_QM_GLBL_CFG1, 0xF << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT); + WREG32(mmDMA1_QM_GLBL_CFG1, 0xF << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT); + WREG32(mmDMA5_QM_GLBL_CFG1, 0xF << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT); +} + +static void gaudi_stop_hbm_dma_qmans(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_HBM_DMA)) + return; + + /* Stop CPs of HBM DMA QMANs */ + + WREG32(mmDMA2_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT); + WREG32(mmDMA3_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT); + WREG32(mmDMA4_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT); + WREG32(mmDMA6_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT); + WREG32(mmDMA7_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT); +} + +static void gaudi_stop_mme_qmans(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_MME)) + return; + + /* Stop CPs of MME QMANs */ + WREG32(mmMME2_QM_GLBL_CFG1, 0x1F << MME0_QM_GLBL_CFG1_CP_STOP_SHIFT); + WREG32(mmMME0_QM_GLBL_CFG1, 0x1F << MME0_QM_GLBL_CFG1_CP_STOP_SHIFT); +} + +static void gaudi_stop_tpc_qmans(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_TPC_MASK)) + return; + + WREG32(mmTPC0_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT); + WREG32(mmTPC1_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT); + WREG32(mmTPC2_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT); + WREG32(mmTPC3_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT); + WREG32(mmTPC4_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT); + WREG32(mmTPC5_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT); + WREG32(mmTPC6_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT); + WREG32(mmTPC7_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT); +} + +static void gaudi_pci_dma_stall(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_PCI_DMA)) + return; + + WREG32(mmDMA0_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT); + WREG32(mmDMA1_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT); + WREG32(mmDMA5_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT); +} + +static void gaudi_hbm_dma_stall(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_HBM_DMA)) + return; + + WREG32(mmDMA2_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT); + WREG32(mmDMA3_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT); + WREG32(mmDMA4_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT); + WREG32(mmDMA6_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT); + WREG32(mmDMA7_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT); +} + +static void gaudi_mme_stall(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_MME)) + return; + + /* WA for H3-1800 bug: do ACC and SBAB writes twice */ + WREG32(mmMME0_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT); + WREG32(mmMME0_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT); + WREG32(mmMME0_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT); + WREG32(mmMME0_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT); + WREG32(mmMME1_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT); + WREG32(mmMME1_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT); + WREG32(mmMME1_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT); + WREG32(mmMME1_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT); + WREG32(mmMME2_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT); + WREG32(mmMME2_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT); + WREG32(mmMME2_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT); + WREG32(mmMME2_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT); + WREG32(mmMME3_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT); + WREG32(mmMME3_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT); + WREG32(mmMME3_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT); + WREG32(mmMME3_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT); +} + +static void gaudi_tpc_stall(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_TPC_MASK)) + return; + + WREG32(mmTPC0_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT); + WREG32(mmTPC1_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT); + WREG32(mmTPC2_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT); + WREG32(mmTPC3_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT); + WREG32(mmTPC4_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT); + WREG32(mmTPC5_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT); + WREG32(mmTPC6_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT); + WREG32(mmTPC7_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT); +} + +static void gaudi_enable_clock_gating(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + u32 qman_offset; + int i; + + if (!hdev->clock_gating) + return; + + if (gaudi->hw_cap_initialized & HW_CAP_CLK_GATE) + return; + + /* In case we are during debug session, don't enable the clock gate + * as it may interfere + */ + if (hdev->in_debug) + return; + + for (i = 0, qman_offset = 0 ; i < PCI_DMA_NUMBER_OF_CHNLS ; i++) { + qman_offset = gaudi_dma_assignment[i] * DMA_QMAN_OFFSET; + WREG32(mmDMA0_QM_CGM_CFG1 + qman_offset, QMAN_CGM1_PWR_GATE_EN); + WREG32(mmDMA0_QM_CGM_CFG + qman_offset, + QMAN_UPPER_CP_CGM_PWR_GATE_EN); + } + + for (; i < HBM_DMA_NUMBER_OF_CHNLS ; i++) { + qman_offset = gaudi_dma_assignment[i] * DMA_QMAN_OFFSET; + WREG32(mmDMA0_QM_CGM_CFG1 + qman_offset, QMAN_CGM1_PWR_GATE_EN); + WREG32(mmDMA0_QM_CGM_CFG + qman_offset, + QMAN_COMMON_CP_CGM_PWR_GATE_EN); + } + + WREG32(mmMME0_QM_CGM_CFG1, QMAN_CGM1_PWR_GATE_EN); + WREG32(mmMME0_QM_CGM_CFG, + QMAN_COMMON_CP_CGM_PWR_GATE_EN); + WREG32(mmMME2_QM_CGM_CFG1, QMAN_CGM1_PWR_GATE_EN); + WREG32(mmMME2_QM_CGM_CFG, + QMAN_COMMON_CP_CGM_PWR_GATE_EN); + + for (i = 0, qman_offset = 0 ; i < TPC_NUMBER_OF_ENGINES ; i++) { + WREG32(mmTPC0_QM_CGM_CFG1 + qman_offset, + QMAN_CGM1_PWR_GATE_EN); + WREG32(mmTPC0_QM_CGM_CFG + qman_offset, + QMAN_COMMON_CP_CGM_PWR_GATE_EN); + + qman_offset += TPC_QMAN_OFFSET; + } + + gaudi->hw_cap_initialized |= HW_CAP_CLK_GATE; +} + +static void gaudi_disable_clock_gating(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + u32 qman_offset; + int i; + + if (!(gaudi->hw_cap_initialized & HW_CAP_CLK_GATE)) + return; + + for (i = 0, qman_offset = 0 ; i < DMA_NUMBER_OF_CHANNELS ; i++) { + WREG32(mmDMA0_QM_CGM_CFG + qman_offset, 0); + WREG32(mmDMA0_QM_CGM_CFG1 + qman_offset, 0); + + qman_offset += (mmDMA1_QM_CGM_CFG - mmDMA0_QM_CGM_CFG); + } + + WREG32(mmMME0_QM_CGM_CFG, 0); + WREG32(mmMME0_QM_CGM_CFG1, 0); + WREG32(mmMME2_QM_CGM_CFG, 0); + WREG32(mmMME2_QM_CGM_CFG1, 0); + + for (i = 0, qman_offset = 0 ; i < TPC_NUMBER_OF_ENGINES ; i++) { + WREG32(mmTPC0_QM_CGM_CFG + qman_offset, 0); + WREG32(mmTPC0_QM_CGM_CFG1 + qman_offset, 0); + + qman_offset += (mmTPC1_QM_CGM_CFG - mmTPC0_QM_CGM_CFG); + } + + gaudi->hw_cap_initialized &= ~(HW_CAP_CLK_GATE); +} + +static void gaudi_enable_timestamp(struct hl_device *hdev) +{ + /* Disable the timestamp counter */ + WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0); + + /* Zero the lower/upper parts of the 64-bit counter */ + WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0xC, 0); + WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0x8, 0); + + /* Enable the counter */ + WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 1); +} + +static void gaudi_disable_timestamp(struct hl_device *hdev) +{ + /* Disable the timestamp counter */ + WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0); +} + +static void gaudi_halt_engines(struct hl_device *hdev, bool hard_reset) +{ + u32 wait_timeout_ms, cpu_timeout_ms; + + dev_info(hdev->dev, + "Halting compute engines and disabling interrupts\n"); + + if (hdev->pldm) { + wait_timeout_ms = GAUDI_PLDM_RESET_WAIT_MSEC; + cpu_timeout_ms = GAUDI_PLDM_RESET_WAIT_MSEC; + } else { + wait_timeout_ms = GAUDI_RESET_WAIT_MSEC; + cpu_timeout_ms = GAUDI_CPU_RESET_WAIT_MSEC; + } + + if (hard_reset) { + /* + * I don't know what is the state of the CPU so make sure it is + * stopped in any means necessary + */ + WREG32(mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU, KMD_MSG_GOTO_WFE); + WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, + GAUDI_EVENT_HALT_MACHINE); + msleep(cpu_timeout_ms); + } + + gaudi_stop_mme_qmans(hdev); + gaudi_stop_tpc_qmans(hdev); + gaudi_stop_hbm_dma_qmans(hdev); + gaudi_stop_pci_dma_qmans(hdev); + + gaudi_disable_clock_gating(hdev); + + msleep(wait_timeout_ms); + + gaudi_pci_dma_stall(hdev); + gaudi_hbm_dma_stall(hdev); + gaudi_tpc_stall(hdev); + gaudi_mme_stall(hdev); + + msleep(wait_timeout_ms); + + gaudi_disable_mme_qmans(hdev); + gaudi_disable_tpc_qmans(hdev); + gaudi_disable_hbm_dma_qmans(hdev); + gaudi_disable_pci_dma_qmans(hdev); + + gaudi_disable_timestamp(hdev); + + if (hard_reset) + gaudi_disable_msi(hdev); + else + gaudi_sync_irqs(hdev); +} + +static int gaudi_mmu_init(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct gaudi_device *gaudi = hdev->asic_specific; + u64 hop0_addr; + int rc, i; + + if (!hdev->mmu_enable) + return 0; + + if (gaudi->hw_cap_initialized & HW_CAP_MMU) + return 0; + + hdev->dram_supports_virtual_memory = false; + + for (i = 0 ; i < prop->max_asid ; i++) { + hop0_addr = prop->mmu_pgt_addr + + (i * prop->mmu_hop_table_size); + + rc = gaudi_mmu_update_asid_hop0_addr(hdev, i, hop0_addr); + if (rc) { + dev_err(hdev->dev, + "failed to set hop0 addr for asid %d\n", i); + goto err; + } + } + + /* init MMU cache manage page */ + WREG32(mmSTLB_CACHE_INV_BASE_39_8, MMU_CACHE_MNG_ADDR >> 8); + WREG32(mmSTLB_CACHE_INV_BASE_49_40, MMU_CACHE_MNG_ADDR >> 40); + + hdev->asic_funcs->mmu_invalidate_cache(hdev, true, + VM_TYPE_USERPTR | VM_TYPE_PHYS_PACK); + + WREG32(mmMMU_UP_MMU_ENABLE, 1); + WREG32(mmMMU_UP_SPI_MASK, 0xF); + + WREG32(mmSTLB_HOP_CONFIGURATION, + hdev->mmu_huge_page_opt ? 0x30440 : 0x40440); + + gaudi->hw_cap_initialized |= HW_CAP_MMU; + + return 0; + +err: + return rc; +} + +static int gaudi_load_firmware_to_device(struct hl_device *hdev) +{ + void __iomem *dst; + + /* HBM scrambler must be initialized before pushing F/W to HBM */ + gaudi_init_scrambler_hbm(hdev); + + dst = hdev->pcie_bar[HBM_BAR_ID] + LINUX_FW_OFFSET; + + return hl_fw_load_fw_to_device(hdev, GAUDI_LINUX_FW_FILE, dst); +} + +static int gaudi_load_boot_fit_to_device(struct hl_device *hdev) +{ + void __iomem *dst; + + dst = hdev->pcie_bar[SRAM_BAR_ID] + BOOT_FIT_SRAM_OFFSET; + + return hl_fw_load_fw_to_device(hdev, GAUDI_BOOT_FIT_FILE, dst); +} + +static void gaudi_read_device_fw_version(struct hl_device *hdev, + enum hl_fw_component fwc) +{ + const char *name; + u32 ver_off; + char *dest; + + switch (fwc) { + case FW_COMP_UBOOT: + ver_off = RREG32(mmUBOOT_VER_OFFSET); + dest = hdev->asic_prop.uboot_ver; + name = "U-Boot"; + break; + case FW_COMP_PREBOOT: + ver_off = RREG32(mmPREBOOT_VER_OFFSET); + dest = hdev->asic_prop.preboot_ver; + name = "Preboot"; + break; + default: + dev_warn(hdev->dev, "Undefined FW component: %d\n", fwc); + return; + } + + ver_off &= ~((u32)SRAM_BASE_ADDR); + + if (ver_off < SRAM_SIZE - VERSION_MAX_LEN) { + memcpy_fromio(dest, hdev->pcie_bar[SRAM_BAR_ID] + ver_off, + VERSION_MAX_LEN); + } else { + dev_err(hdev->dev, "%s version offset (0x%x) is above SRAM\n", + name, ver_off); + strcpy(dest, "unavailable"); + } +} + +static int gaudi_init_cpu(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + int rc; + + if (!hdev->cpu_enable) + return 0; + + if (gaudi->hw_cap_initialized & HW_CAP_CPU) + return 0; + + /* + * The device CPU works with 40 bits addresses. + * This register sets the extension to 50 bits. + */ + WREG32(mmCPU_IF_CPU_MSB_ADDR, hdev->cpu_pci_msb_addr); + + rc = hl_fw_init_cpu(hdev, mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS, + mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU, + mmCPU_CMD_STATUS_TO_HOST, + mmCPU_BOOT_ERR0, + !hdev->bmc_enable, GAUDI_CPU_TIMEOUT_USEC, + GAUDI_BOOT_FIT_REQ_TIMEOUT_USEC); + + if (rc) + return rc; + + gaudi->hw_cap_initialized |= HW_CAP_CPU; + + return 0; +} + +static int gaudi_init_cpu_queues(struct hl_device *hdev, u32 cpu_timeout) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + struct hl_eq *eq; + u32 status; + struct hl_hw_queue *cpu_pq = + &hdev->kernel_queues[GAUDI_QUEUE_ID_CPU_PQ]; + int err; + + if (!hdev->cpu_queues_enable) + return 0; + + if (gaudi->hw_cap_initialized & HW_CAP_CPU_Q) + return 0; + + eq = &hdev->event_queue; + + WREG32(mmCPU_IF_PQ_BASE_ADDR_LOW, lower_32_bits(cpu_pq->bus_address)); + WREG32(mmCPU_IF_PQ_BASE_ADDR_HIGH, upper_32_bits(cpu_pq->bus_address)); + + WREG32(mmCPU_IF_EQ_BASE_ADDR_LOW, lower_32_bits(eq->bus_address)); + WREG32(mmCPU_IF_EQ_BASE_ADDR_HIGH, upper_32_bits(eq->bus_address)); + + WREG32(mmCPU_IF_CQ_BASE_ADDR_LOW, + lower_32_bits(hdev->cpu_accessible_dma_address)); + WREG32(mmCPU_IF_CQ_BASE_ADDR_HIGH, + upper_32_bits(hdev->cpu_accessible_dma_address)); + + WREG32(mmCPU_IF_PQ_LENGTH, HL_QUEUE_SIZE_IN_BYTES); + WREG32(mmCPU_IF_EQ_LENGTH, HL_EQ_SIZE_IN_BYTES); + WREG32(mmCPU_IF_CQ_LENGTH, HL_CPU_ACCESSIBLE_MEM_SIZE); + + /* Used for EQ CI */ + WREG32(mmCPU_IF_EQ_RD_OFFS, 0); + + WREG32(mmCPU_IF_PF_PQ_PI, 0); + + if (gaudi->multi_msi_mode) + WREG32(mmCPU_IF_QUEUE_INIT, PQ_INIT_STATUS_READY_FOR_CP); + else + WREG32(mmCPU_IF_QUEUE_INIT, + PQ_INIT_STATUS_READY_FOR_CP_SINGLE_MSI); + + WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, GAUDI_EVENT_PI_UPDATE); + + err = hl_poll_timeout( + hdev, + mmCPU_IF_QUEUE_INIT, + status, + (status == PQ_INIT_STATUS_READY_FOR_HOST), + 1000, + cpu_timeout); + + if (err) { + dev_err(hdev->dev, + "Failed to communicate with ARM CPU (ArmCP timeout)\n"); + return -EIO; + } + + gaudi->hw_cap_initialized |= HW_CAP_CPU_Q; + return 0; +} + +static void gaudi_pre_hw_init(struct hl_device *hdev) +{ + /* Perform read from the device to make sure device is up */ + RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG); + + /* + * Let's mark in the H/W that we have reached this point. We check + * this value in the reset_before_init function to understand whether + * we need to reset the chip before doing H/W init. This register is + * cleared by the H/W upon H/W reset + */ + WREG32(mmHW_STATE, HL_DEVICE_HW_STATE_DIRTY); + + /* Set the access through PCI bars (Linux driver only) as secured */ + WREG32(mmPCIE_WRAP_LBW_PROT_OVR, (PCIE_WRAP_LBW_PROT_OVR_RD_EN_MASK | + PCIE_WRAP_LBW_PROT_OVR_WR_EN_MASK)); + + /* Perform read to flush the waiting writes to ensure configuration + * was set in the device + */ + RREG32(mmPCIE_WRAP_LBW_PROT_OVR); + + if (hdev->axi_drain) { + WREG32(mmPCIE_WRAP_LBW_DRAIN_CFG, + 1 << PCIE_WRAP_LBW_DRAIN_CFG_EN_SHIFT); + WREG32(mmPCIE_WRAP_HBW_DRAIN_CFG, + 1 << PCIE_WRAP_HBW_DRAIN_CFG_EN_SHIFT); + + /* Perform read to flush the DRAIN cfg */ + RREG32(mmPCIE_WRAP_HBW_DRAIN_CFG); + } else { + WREG32(mmPCIE_WRAP_LBW_DRAIN_CFG, 0); + WREG32(mmPCIE_WRAP_HBW_DRAIN_CFG, 0); + + /* Perform read to flush the DRAIN cfg */ + RREG32(mmPCIE_WRAP_HBW_DRAIN_CFG); + } + + /* Configure the reset registers. Must be done as early as possible + * in case we fail during H/W initialization + */ + WREG32(mmPSOC_GLOBAL_CONF_SOFT_RST_CFG_H, + (CFG_RST_H_DMA_MASK | + CFG_RST_H_MME_MASK | + CFG_RST_H_SM_MASK | + CFG_RST_H_TPC_MASK)); + + WREG32(mmPSOC_GLOBAL_CONF_SOFT_RST_CFG_L, CFG_RST_L_TPC_MASK); + + WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H, + (CFG_RST_H_HBM_MASK | + CFG_RST_H_TPC_MASK | + CFG_RST_H_NIC_MASK | + CFG_RST_H_SM_MASK | + CFG_RST_H_DMA_MASK | + CFG_RST_H_MME_MASK | + CFG_RST_H_CPU_MASK | + CFG_RST_H_MMU_MASK)); + + WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L, + (CFG_RST_L_IF_MASK | + CFG_RST_L_PSOC_MASK | + CFG_RST_L_TPC_MASK)); +} + +static int gaudi_hw_init(struct hl_device *hdev) +{ + int rc; + + dev_info(hdev->dev, "Starting initialization of H/W\n"); + + gaudi_pre_hw_init(hdev); + + gaudi_init_pci_dma_qmans(hdev); + + gaudi_init_hbm_dma_qmans(hdev); + + /* + * Before pushing u-boot/linux to device, need to set the hbm bar to + * base address of dram + */ + if (gaudi_set_hbm_bar_base(hdev, DRAM_PHYS_BASE) == U64_MAX) { + dev_err(hdev->dev, + "failed to map HBM bar to DRAM base address\n"); + return -EIO; + } + + rc = gaudi_init_cpu(hdev); + if (rc) { + dev_err(hdev->dev, "failed to initialize CPU\n"); + return rc; + } + + /* SRAM scrambler must be initialized after CPU is running from HBM */ + gaudi_init_scrambler_sram(hdev); + + /* This is here just in case we are working without CPU */ + gaudi_init_scrambler_hbm(hdev); + + gaudi_init_golden_registers(hdev); + + rc = gaudi_mmu_init(hdev); + if (rc) + return rc; + + gaudi_init_security(hdev); + + gaudi_init_mme_qmans(hdev); + + gaudi_init_tpc_qmans(hdev); + + gaudi_enable_clock_gating(hdev); + + gaudi_enable_timestamp(hdev); + + /* MSI must be enabled before CPU queues are initialized */ + rc = gaudi_enable_msi(hdev); + if (rc) + goto disable_queues; + + /* must be called after MSI was enabled */ + rc = gaudi_init_cpu_queues(hdev, GAUDI_CPU_TIMEOUT_USEC); + if (rc) { + dev_err(hdev->dev, "failed to initialize CPU H/W queues %d\n", + rc); + goto disable_msi; + } + + /* Perform read from the device to flush all configuration */ + RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG); + + return 0; + +disable_msi: + gaudi_disable_msi(hdev); +disable_queues: + gaudi_disable_mme_qmans(hdev); + gaudi_disable_pci_dma_qmans(hdev); + + return rc; +} + +static void gaudi_hw_fini(struct hl_device *hdev, bool hard_reset) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + u32 status, reset_timeout_ms, boot_strap = 0; + + if (hdev->pldm) { + if (hard_reset) + reset_timeout_ms = GAUDI_PLDM_HRESET_TIMEOUT_MSEC; + else + reset_timeout_ms = GAUDI_PLDM_SRESET_TIMEOUT_MSEC; + } else { + reset_timeout_ms = GAUDI_RESET_TIMEOUT_MSEC; + } + + if (hard_reset) { + /* Tell ASIC not to re-initialize PCIe */ + WREG32(mmPREBOOT_PCIE_EN, LKD_HARD_RESET_MAGIC); + + boot_strap = RREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS); + /* H/W bug WA: + * rdata[31:0] = strap_read_val; + * wdata[31:0] = rdata[30:21],1'b0,rdata[20:0] + */ + boot_strap = (((boot_strap & 0x7FE00000) << 1) | + (boot_strap & 0x001FFFFF)); + WREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS, boot_strap & ~0x2); + + /* Restart BTL/BLR upon hard-reset */ + WREG32(mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START, 1); + + WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST, + 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_IND_SHIFT); + dev_info(hdev->dev, + "Issued HARD reset command, going to wait %dms\n", + reset_timeout_ms); + } else { + /* Don't restart BTL/BLR upon soft-reset */ + WREG32(mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START, 0); + + WREG32(mmPSOC_GLOBAL_CONF_SOFT_RST, + 1 << PSOC_GLOBAL_CONF_SOFT_RST_IND_SHIFT); + dev_info(hdev->dev, + "Issued SOFT reset command, going to wait %dms\n", + reset_timeout_ms); + } + + /* + * After hard reset, we can't poll the BTM_FSM register because the PSOC + * itself is in reset. Need to wait until the reset is deasserted + */ + msleep(reset_timeout_ms); + + status = RREG32(mmPSOC_GLOBAL_CONF_BTM_FSM); + if (status & PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK) + dev_err(hdev->dev, + "Timeout while waiting for device to reset 0x%x\n", + status); + + if (!hard_reset) { + gaudi->hw_cap_initialized &= ~(HW_CAP_PCI_DMA | HW_CAP_MME | + HW_CAP_TPC_MASK | + HW_CAP_HBM_DMA); + + WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, + GAUDI_EVENT_SOFT_RESET); + return; + } + + /* We continue here only for hard-reset */ + + WREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS, boot_strap); + + gaudi->hw_cap_initialized &= ~(HW_CAP_CPU | HW_CAP_CPU_Q | + HW_CAP_HBM | HW_CAP_PCI_DMA | + HW_CAP_MME | HW_CAP_TPC_MASK | + HW_CAP_HBM_DMA | HW_CAP_PLL | + HW_CAP_MMU | + HW_CAP_SRAM_SCRAMBLER | + HW_CAP_HBM_SCRAMBLER); + memset(gaudi->events_stat, 0, sizeof(gaudi->events_stat)); +} + +static int gaudi_suspend(struct hl_device *hdev) +{ + int rc; + + rc = hl_fw_send_pci_access_msg(hdev, ARMCP_PACKET_DISABLE_PCI_ACCESS); + if (rc) + dev_err(hdev->dev, "Failed to disable PCI access from CPU\n"); + + return rc; +} + +static int gaudi_resume(struct hl_device *hdev) +{ + return gaudi_init_iatu(hdev); +} + +static int gaudi_cb_mmap(struct hl_device *hdev, struct vm_area_struct *vma, + u64 kaddress, phys_addr_t paddress, u32 size) +{ + int rc; + + vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP | + VM_DONTCOPY | VM_NORESERVE; + + rc = remap_pfn_range(vma, vma->vm_start, paddress >> PAGE_SHIFT, + size, vma->vm_page_prot); + if (rc) + dev_err(hdev->dev, "remap_pfn_range error %d", rc); + + return rc; +} + +static void gaudi_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + u32 db_reg_offset, db_value, dma_qm_offset, q_off; + int dma_id; + bool invalid_queue = false; + + switch (hw_queue_id) { + case GAUDI_QUEUE_ID_DMA_0_0...GAUDI_QUEUE_ID_DMA_0_3: + dma_id = gaudi_dma_assignment[GAUDI_PCI_DMA_1]; + dma_qm_offset = dma_id * DMA_QMAN_OFFSET; + q_off = dma_qm_offset + (hw_queue_id & 0x3) * 4; + db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off; + break; + + case GAUDI_QUEUE_ID_DMA_1_0...GAUDI_QUEUE_ID_DMA_1_3: + dma_id = gaudi_dma_assignment[GAUDI_PCI_DMA_2]; + dma_qm_offset = dma_id * DMA_QMAN_OFFSET; + q_off = dma_qm_offset + (hw_queue_id & 0x3) * 4; + db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off; + break; + + case GAUDI_QUEUE_ID_DMA_2_0...GAUDI_QUEUE_ID_DMA_2_3: + dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_1]; + dma_qm_offset = dma_id * DMA_QMAN_OFFSET; + q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4; + db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off; + break; + + case GAUDI_QUEUE_ID_DMA_3_0...GAUDI_QUEUE_ID_DMA_3_3: + dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_2]; + dma_qm_offset = dma_id * DMA_QMAN_OFFSET; + q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4; + db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off; + break; + + case GAUDI_QUEUE_ID_DMA_4_0...GAUDI_QUEUE_ID_DMA_4_3: + dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_3]; + dma_qm_offset = dma_id * DMA_QMAN_OFFSET; + q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4; + db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off; + break; + + case GAUDI_QUEUE_ID_DMA_5_0...GAUDI_QUEUE_ID_DMA_5_3: + dma_id = gaudi_dma_assignment[GAUDI_PCI_DMA_3]; + dma_qm_offset = dma_id * DMA_QMAN_OFFSET; + q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4; + db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off; + break; + + case GAUDI_QUEUE_ID_DMA_6_0...GAUDI_QUEUE_ID_DMA_6_3: + dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_4]; + dma_qm_offset = dma_id * DMA_QMAN_OFFSET; + q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4; + db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off; + break; + + case GAUDI_QUEUE_ID_DMA_7_0...GAUDI_QUEUE_ID_DMA_7_3: + dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_5]; + dma_qm_offset = dma_id * DMA_QMAN_OFFSET; + q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4; + db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off; + break; + + case GAUDI_QUEUE_ID_CPU_PQ: + if (gaudi->hw_cap_initialized & HW_CAP_CPU_Q) + db_reg_offset = mmCPU_IF_PF_PQ_PI; + else + invalid_queue = true; + break; + + case GAUDI_QUEUE_ID_MME_0_0: + db_reg_offset = mmMME2_QM_PQ_PI_0; + break; + + case GAUDI_QUEUE_ID_MME_0_1: + db_reg_offset = mmMME2_QM_PQ_PI_1; + break; + + case GAUDI_QUEUE_ID_MME_0_2: + db_reg_offset = mmMME2_QM_PQ_PI_2; + break; + + case GAUDI_QUEUE_ID_MME_0_3: + db_reg_offset = mmMME2_QM_PQ_PI_3; + break; + + case GAUDI_QUEUE_ID_MME_1_0: + db_reg_offset = mmMME0_QM_PQ_PI_0; + break; + + case GAUDI_QUEUE_ID_MME_1_1: + db_reg_offset = mmMME0_QM_PQ_PI_1; + break; + + case GAUDI_QUEUE_ID_MME_1_2: + db_reg_offset = mmMME0_QM_PQ_PI_2; + break; + + case GAUDI_QUEUE_ID_MME_1_3: + db_reg_offset = mmMME0_QM_PQ_PI_3; + break; + + case GAUDI_QUEUE_ID_TPC_0_0: + db_reg_offset = mmTPC0_QM_PQ_PI_0; + break; + + case GAUDI_QUEUE_ID_TPC_0_1: + db_reg_offset = mmTPC0_QM_PQ_PI_1; + break; + + case GAUDI_QUEUE_ID_TPC_0_2: + db_reg_offset = mmTPC0_QM_PQ_PI_2; + break; + + case GAUDI_QUEUE_ID_TPC_0_3: + db_reg_offset = mmTPC0_QM_PQ_PI_3; + break; + + case GAUDI_QUEUE_ID_TPC_1_0: + db_reg_offset = mmTPC1_QM_PQ_PI_0; + break; + + case GAUDI_QUEUE_ID_TPC_1_1: + db_reg_offset = mmTPC1_QM_PQ_PI_1; + break; + + case GAUDI_QUEUE_ID_TPC_1_2: + db_reg_offset = mmTPC1_QM_PQ_PI_2; + break; + + case GAUDI_QUEUE_ID_TPC_1_3: + db_reg_offset = mmTPC1_QM_PQ_PI_3; + break; + + case GAUDI_QUEUE_ID_TPC_2_0: + db_reg_offset = mmTPC2_QM_PQ_PI_0; + break; + + case GAUDI_QUEUE_ID_TPC_2_1: + db_reg_offset = mmTPC2_QM_PQ_PI_1; + break; + + case GAUDI_QUEUE_ID_TPC_2_2: + db_reg_offset = mmTPC2_QM_PQ_PI_2; + break; + + case GAUDI_QUEUE_ID_TPC_2_3: + db_reg_offset = mmTPC2_QM_PQ_PI_3; + break; + + case GAUDI_QUEUE_ID_TPC_3_0: + db_reg_offset = mmTPC3_QM_PQ_PI_0; + break; + + case GAUDI_QUEUE_ID_TPC_3_1: + db_reg_offset = mmTPC3_QM_PQ_PI_1; + break; + + case GAUDI_QUEUE_ID_TPC_3_2: + db_reg_offset = mmTPC3_QM_PQ_PI_2; + break; + + case GAUDI_QUEUE_ID_TPC_3_3: + db_reg_offset = mmTPC3_QM_PQ_PI_3; + break; + + case GAUDI_QUEUE_ID_TPC_4_0: + db_reg_offset = mmTPC4_QM_PQ_PI_0; + break; + + case GAUDI_QUEUE_ID_TPC_4_1: + db_reg_offset = mmTPC4_QM_PQ_PI_1; + break; + + case GAUDI_QUEUE_ID_TPC_4_2: + db_reg_offset = mmTPC4_QM_PQ_PI_2; + break; + + case GAUDI_QUEUE_ID_TPC_4_3: + db_reg_offset = mmTPC4_QM_PQ_PI_3; + break; + + case GAUDI_QUEUE_ID_TPC_5_0: + db_reg_offset = mmTPC5_QM_PQ_PI_0; + break; + + case GAUDI_QUEUE_ID_TPC_5_1: + db_reg_offset = mmTPC5_QM_PQ_PI_1; + break; + + case GAUDI_QUEUE_ID_TPC_5_2: + db_reg_offset = mmTPC5_QM_PQ_PI_2; + break; + + case GAUDI_QUEUE_ID_TPC_5_3: + db_reg_offset = mmTPC5_QM_PQ_PI_3; + break; + + case GAUDI_QUEUE_ID_TPC_6_0: + db_reg_offset = mmTPC6_QM_PQ_PI_0; + break; + + case GAUDI_QUEUE_ID_TPC_6_1: + db_reg_offset = mmTPC6_QM_PQ_PI_1; + break; + + case GAUDI_QUEUE_ID_TPC_6_2: + db_reg_offset = mmTPC6_QM_PQ_PI_2; + break; + + case GAUDI_QUEUE_ID_TPC_6_3: + db_reg_offset = mmTPC6_QM_PQ_PI_3; + break; + + case GAUDI_QUEUE_ID_TPC_7_0: + db_reg_offset = mmTPC7_QM_PQ_PI_0; + break; + + case GAUDI_QUEUE_ID_TPC_7_1: + db_reg_offset = mmTPC7_QM_PQ_PI_1; + break; + + case GAUDI_QUEUE_ID_TPC_7_2: + db_reg_offset = mmTPC7_QM_PQ_PI_2; + break; + + case GAUDI_QUEUE_ID_TPC_7_3: + db_reg_offset = mmTPC7_QM_PQ_PI_3; + break; + + default: + invalid_queue = true; + } + + if (invalid_queue) { + /* Should never get here */ + dev_err(hdev->dev, "h/w queue %d is invalid. Can't set pi\n", + hw_queue_id); + return; + } + + db_value = pi; + + /* ring the doorbell */ + WREG32(db_reg_offset, db_value); + + if (hw_queue_id == GAUDI_QUEUE_ID_CPU_PQ) + WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, + GAUDI_EVENT_PI_UPDATE); +} + +static void gaudi_pqe_write(struct hl_device *hdev, __le64 *pqe, + struct hl_bd *bd) +{ + __le64 *pbd = (__le64 *) bd; + + /* The QMANs are on the host memory so a simple copy suffice */ + pqe[0] = pbd[0]; + pqe[1] = pbd[1]; +} + +static void *gaudi_dma_alloc_coherent(struct hl_device *hdev, size_t size, + dma_addr_t *dma_handle, gfp_t flags) +{ + void *kernel_addr = dma_alloc_coherent(&hdev->pdev->dev, size, + dma_handle, flags); + + /* Shift to the device's base physical address of host memory */ + if (kernel_addr) + *dma_handle += HOST_PHYS_BASE; + + return kernel_addr; +} + +static void gaudi_dma_free_coherent(struct hl_device *hdev, size_t size, + void *cpu_addr, dma_addr_t dma_handle) +{ + /* Cancel the device's base physical address of host memory */ + dma_addr_t fixed_dma_handle = dma_handle - HOST_PHYS_BASE; + + dma_free_coherent(&hdev->pdev->dev, size, cpu_addr, fixed_dma_handle); +} + +static void *gaudi_get_int_queue_base(struct hl_device *hdev, + u32 queue_id, dma_addr_t *dma_handle, + u16 *queue_len) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + struct gaudi_internal_qman_info *q; + + if (queue_id >= GAUDI_QUEUE_ID_SIZE || + gaudi_queue_type[queue_id] != QUEUE_TYPE_INT) { + dev_err(hdev->dev, "Got invalid queue id %d\n", queue_id); + return NULL; + } + + q = &gaudi->internal_qmans[queue_id]; + *dma_handle = q->pq_dma_addr; + *queue_len = q->pq_size / QMAN_PQ_ENTRY_SIZE; + + return q->pq_kernel_addr; +} + +static int gaudi_send_cpu_message(struct hl_device *hdev, u32 *msg, + u16 len, u32 timeout, long *result) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_CPU_Q)) { + if (result) + *result = 0; + return 0; + } + + return hl_fw_send_cpu_message(hdev, GAUDI_QUEUE_ID_CPU_PQ, msg, len, + timeout, result); +} + +static int gaudi_test_queue(struct hl_device *hdev, u32 hw_queue_id) +{ + struct packet_msg_prot *fence_pkt; + dma_addr_t pkt_dma_addr; + u32 fence_val, tmp, timeout_usec; + dma_addr_t fence_dma_addr; + u32 *fence_ptr; + int rc; + + if (hdev->pldm) + timeout_usec = GAUDI_PLDM_TEST_QUEUE_WAIT_USEC; + else + timeout_usec = GAUDI_TEST_QUEUE_WAIT_USEC; + + fence_val = GAUDI_QMAN0_FENCE_VAL; + + fence_ptr = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL, + &fence_dma_addr); + if (!fence_ptr) { + dev_err(hdev->dev, + "Failed to allocate memory for queue testing\n"); + return -ENOMEM; + } + + *fence_ptr = 0; + + fence_pkt = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, + sizeof(struct packet_msg_prot), + GFP_KERNEL, &pkt_dma_addr); + if (!fence_pkt) { + dev_err(hdev->dev, + "Failed to allocate packet for queue testing\n"); + rc = -ENOMEM; + goto free_fence_ptr; + } + + tmp = (PACKET_MSG_PROT << GAUDI_PKT_CTL_OPCODE_SHIFT) | + (1 << GAUDI_PKT_CTL_EB_SHIFT) | + (1 << GAUDI_PKT_CTL_MB_SHIFT); + fence_pkt->ctl = cpu_to_le32(tmp); + fence_pkt->value = cpu_to_le32(fence_val); + fence_pkt->addr = cpu_to_le64(fence_dma_addr); + + rc = hl_hw_queue_send_cb_no_cmpl(hdev, hw_queue_id, + sizeof(struct packet_msg_prot), + pkt_dma_addr); + if (rc) { + dev_err(hdev->dev, + "Failed to send fence packet\n"); + goto free_pkt; + } + + rc = hl_poll_timeout_memory(hdev, fence_ptr, tmp, (tmp == fence_val), + 1000, timeout_usec, true); + + hl_hw_queue_inc_ci_kernel(hdev, hw_queue_id); + + if (rc == -ETIMEDOUT) { + dev_err(hdev->dev, + "H/W queue %d test failed (scratch(0x%08llX) == 0x%08X)\n", + hw_queue_id, (unsigned long long) fence_dma_addr, tmp); + rc = -EIO; + } + +free_pkt: + hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_pkt, + pkt_dma_addr); +free_fence_ptr: + hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_ptr, + fence_dma_addr); + return rc; +} + +static int gaudi_test_cpu_queue(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + /* + * check capability here as send_cpu_message() won't update the result + * value if no capability + */ + if (!(gaudi->hw_cap_initialized & HW_CAP_CPU_Q)) + return 0; + + return hl_fw_test_cpu_queue(hdev); +} + +static int gaudi_test_queues(struct hl_device *hdev) +{ + int i, rc, ret_val = 0; + + for (i = 0 ; i < HL_MAX_QUEUES ; i++) { + if (hdev->asic_prop.hw_queues_props[i].type == QUEUE_TYPE_EXT) { + rc = gaudi_test_queue(hdev, i); + if (rc) + ret_val = -EINVAL; + } + } + + rc = gaudi_test_cpu_queue(hdev); + if (rc) + ret_val = -EINVAL; + + return ret_val; +} + +static void *gaudi_dma_pool_zalloc(struct hl_device *hdev, size_t size, + gfp_t mem_flags, dma_addr_t *dma_handle) +{ + void *kernel_addr; + + if (size > GAUDI_DMA_POOL_BLK_SIZE) + return NULL; + + kernel_addr = dma_pool_zalloc(hdev->dma_pool, mem_flags, dma_handle); + + /* Shift to the device's base physical address of host memory */ + if (kernel_addr) + *dma_handle += HOST_PHYS_BASE; + + return kernel_addr; +} + +static void gaudi_dma_pool_free(struct hl_device *hdev, void *vaddr, + dma_addr_t dma_addr) +{ + /* Cancel the device's base physical address of host memory */ + dma_addr_t fixed_dma_addr = dma_addr - HOST_PHYS_BASE; + + dma_pool_free(hdev->dma_pool, vaddr, fixed_dma_addr); +} + +static void *gaudi_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, + size_t size, dma_addr_t *dma_handle) +{ + return hl_fw_cpu_accessible_dma_pool_alloc(hdev, size, dma_handle); +} + +static void gaudi_cpu_accessible_dma_pool_free(struct hl_device *hdev, + size_t size, void *vaddr) +{ + hl_fw_cpu_accessible_dma_pool_free(hdev, size, vaddr); +} + +static int gaudi_dma_map_sg(struct hl_device *hdev, struct scatterlist *sgl, + int nents, enum dma_data_direction dir) +{ + struct scatterlist *sg; + int i; + + if (!dma_map_sg(&hdev->pdev->dev, sgl, nents, dir)) + return -ENOMEM; + + /* Shift to the device's base physical address of host memory */ + for_each_sg(sgl, sg, nents, i) + sg->dma_address += HOST_PHYS_BASE; + + return 0; +} + +static void gaudi_dma_unmap_sg(struct hl_device *hdev, struct scatterlist *sgl, + int nents, enum dma_data_direction dir) +{ + struct scatterlist *sg; + int i; + + /* Cancel the device's base physical address of host memory */ + for_each_sg(sgl, sg, nents, i) + sg->dma_address -= HOST_PHYS_BASE; + + dma_unmap_sg(&hdev->pdev->dev, sgl, nents, dir); +} + +static u32 gaudi_get_dma_desc_list_size(struct hl_device *hdev, + struct sg_table *sgt) +{ + struct scatterlist *sg, *sg_next_iter; + u32 count, dma_desc_cnt; + u64 len, len_next; + dma_addr_t addr, addr_next; + + dma_desc_cnt = 0; + + for_each_sg(sgt->sgl, sg, sgt->nents, count) { + + len = sg_dma_len(sg); + addr = sg_dma_address(sg); + + if (len == 0) + break; + + while ((count + 1) < sgt->nents) { + sg_next_iter = sg_next(sg); + len_next = sg_dma_len(sg_next_iter); + addr_next = sg_dma_address(sg_next_iter); + + if (len_next == 0) + break; + + if ((addr + len == addr_next) && + (len + len_next <= DMA_MAX_TRANSFER_SIZE)) { + len += len_next; + count++; + sg = sg_next_iter; + } else { + break; + } + } + + dma_desc_cnt++; + } + + return dma_desc_cnt * sizeof(struct packet_lin_dma); +} + +static int gaudi_pin_memory_before_cs(struct hl_device *hdev, + struct hl_cs_parser *parser, + struct packet_lin_dma *user_dma_pkt, + u64 addr, enum dma_data_direction dir) +{ + struct hl_userptr *userptr; + int rc; + + if (hl_userptr_is_pinned(hdev, addr, le32_to_cpu(user_dma_pkt->tsize), + parser->job_userptr_list, &userptr)) + goto already_pinned; + + userptr = kzalloc(sizeof(*userptr), GFP_ATOMIC); + if (!userptr) + return -ENOMEM; + + rc = hl_pin_host_memory(hdev, addr, le32_to_cpu(user_dma_pkt->tsize), + userptr); + if (rc) + goto free_userptr; + + list_add_tail(&userptr->job_node, parser->job_userptr_list); + + rc = hdev->asic_funcs->asic_dma_map_sg(hdev, userptr->sgt->sgl, + userptr->sgt->nents, dir); + if (rc) { + dev_err(hdev->dev, "failed to map sgt with DMA region\n"); + goto unpin_memory; + } + + userptr->dma_mapped = true; + userptr->dir = dir; + +already_pinned: + parser->patched_cb_size += + gaudi_get_dma_desc_list_size(hdev, userptr->sgt); + + return 0; + +unpin_memory: + hl_unpin_host_memory(hdev, userptr); +free_userptr: + kfree(userptr); + return rc; +} + +static int gaudi_validate_dma_pkt_host(struct hl_device *hdev, + struct hl_cs_parser *parser, + struct packet_lin_dma *user_dma_pkt, + bool src_in_host) +{ + enum dma_data_direction dir; + bool skip_host_mem_pin = false, user_memset; + u64 addr; + int rc = 0; + + user_memset = (le32_to_cpu(user_dma_pkt->ctl) & + GAUDI_PKT_LIN_DMA_CTL_MEMSET_MASK) >> + GAUDI_PKT_LIN_DMA_CTL_MEMSET_SHIFT; + + if (src_in_host) { + if (user_memset) + skip_host_mem_pin = true; + + dev_dbg(hdev->dev, "DMA direction is HOST --> DEVICE\n"); + dir = DMA_TO_DEVICE; + addr = le64_to_cpu(user_dma_pkt->src_addr); + } else { + dev_dbg(hdev->dev, "DMA direction is DEVICE --> HOST\n"); + dir = DMA_FROM_DEVICE; + addr = (le64_to_cpu(user_dma_pkt->dst_addr) & + GAUDI_PKT_LIN_DMA_DST_ADDR_MASK) >> + GAUDI_PKT_LIN_DMA_DST_ADDR_SHIFT; + } + + if (skip_host_mem_pin) + parser->patched_cb_size += sizeof(*user_dma_pkt); + else + rc = gaudi_pin_memory_before_cs(hdev, parser, user_dma_pkt, + addr, dir); + + return rc; +} + +static int gaudi_validate_dma_pkt_no_mmu(struct hl_device *hdev, + struct hl_cs_parser *parser, + struct packet_lin_dma *user_dma_pkt) +{ + bool src_in_host = false; + u64 dst_addr = (le64_to_cpu(user_dma_pkt->dst_addr) & + GAUDI_PKT_LIN_DMA_DST_ADDR_MASK) >> + GAUDI_PKT_LIN_DMA_DST_ADDR_SHIFT; + + dev_dbg(hdev->dev, "DMA packet details:\n"); + dev_dbg(hdev->dev, "source == 0x%llx\n", + le64_to_cpu(user_dma_pkt->src_addr)); + dev_dbg(hdev->dev, "destination == 0x%llx\n", dst_addr); + dev_dbg(hdev->dev, "size == %u\n", le32_to_cpu(user_dma_pkt->tsize)); + + /* + * Special handling for DMA with size 0. Bypass all validations + * because no transactions will be done except for WR_COMP, which + * is not a security issue + */ + if (!le32_to_cpu(user_dma_pkt->tsize)) { + parser->patched_cb_size += sizeof(*user_dma_pkt); + return 0; + } + + if (parser->hw_queue_id <= GAUDI_QUEUE_ID_DMA_0_3) + src_in_host = true; + + return gaudi_validate_dma_pkt_host(hdev, parser, user_dma_pkt, + src_in_host); +} + +static int gaudi_validate_cb(struct hl_device *hdev, + struct hl_cs_parser *parser, bool is_mmu) +{ + u32 cb_parsed_length = 0; + int rc = 0; + + parser->patched_cb_size = 0; + + /* cb_user_size is more than 0 so loop will always be executed */ + while (cb_parsed_length < parser->user_cb_size) { + enum packet_id pkt_id; + u16 pkt_size; + struct gaudi_packet *user_pkt; + + user_pkt = (struct gaudi_packet *) (uintptr_t) + (parser->user_cb->kernel_address + cb_parsed_length); + + pkt_id = (enum packet_id) ( + (le64_to_cpu(user_pkt->header) & + PACKET_HEADER_PACKET_ID_MASK) >> + PACKET_HEADER_PACKET_ID_SHIFT); + + pkt_size = gaudi_packet_sizes[pkt_id]; + cb_parsed_length += pkt_size; + if (cb_parsed_length > parser->user_cb_size) { + dev_err(hdev->dev, + "packet 0x%x is out of CB boundary\n", pkt_id); + rc = -EINVAL; + break; + } + + switch (pkt_id) { + case PACKET_MSG_PROT: + dev_err(hdev->dev, + "User not allowed to use MSG_PROT\n"); + rc = -EPERM; + break; + + case PACKET_CP_DMA: + dev_err(hdev->dev, "User not allowed to use CP_DMA\n"); + rc = -EPERM; + break; + + case PACKET_STOP: + dev_err(hdev->dev, "User not allowed to use STOP\n"); + rc = -EPERM; + break; + + case PACKET_LIN_DMA: + parser->contains_dma_pkt = true; + if (is_mmu) + parser->patched_cb_size += pkt_size; + else + rc = gaudi_validate_dma_pkt_no_mmu(hdev, parser, + (struct packet_lin_dma *) user_pkt); + break; + + case PACKET_WREG_32: + case PACKET_WREG_BULK: + case PACKET_MSG_LONG: + case PACKET_MSG_SHORT: + case PACKET_REPEAT: + case PACKET_FENCE: + case PACKET_NOP: + case PACKET_ARB_POINT: + case PACKET_LOAD_AND_EXE: + parser->patched_cb_size += pkt_size; + break; + + default: + dev_err(hdev->dev, "Invalid packet header 0x%x\n", + pkt_id); + rc = -EINVAL; + break; + } + + if (rc) + break; + } + + /* + * The new CB should have space at the end for two MSG_PROT packets: + * 1. A packet that will act as a completion packet + * 2. A packet that will generate MSI-X interrupt + */ + parser->patched_cb_size += sizeof(struct packet_msg_prot) * 2; + + return rc; +} + +static int gaudi_patch_dma_packet(struct hl_device *hdev, + struct hl_cs_parser *parser, + struct packet_lin_dma *user_dma_pkt, + struct packet_lin_dma *new_dma_pkt, + u32 *new_dma_pkt_size) +{ + struct hl_userptr *userptr; + struct scatterlist *sg, *sg_next_iter; + u32 count, dma_desc_cnt, user_wrcomp_en_mask, ctl; + u64 len, len_next; + dma_addr_t dma_addr, dma_addr_next; + u64 device_memory_addr, addr; + enum dma_data_direction dir; + struct sg_table *sgt; + bool src_in_host = false; + bool skip_host_mem_pin = false; + bool user_memset; + + ctl = le32_to_cpu(user_dma_pkt->ctl); + + if (parser->hw_queue_id <= GAUDI_QUEUE_ID_DMA_0_3) + src_in_host = true; + + user_memset = (ctl & GAUDI_PKT_LIN_DMA_CTL_MEMSET_MASK) >> + GAUDI_PKT_LIN_DMA_CTL_MEMSET_SHIFT; + + if (src_in_host) { + addr = le64_to_cpu(user_dma_pkt->src_addr); + device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr); + dir = DMA_TO_DEVICE; + if (user_memset) + skip_host_mem_pin = true; + } else { + addr = le64_to_cpu(user_dma_pkt->dst_addr); + device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr); + dir = DMA_FROM_DEVICE; + } + + if ((!skip_host_mem_pin) && + (!hl_userptr_is_pinned(hdev, addr, + le32_to_cpu(user_dma_pkt->tsize), + parser->job_userptr_list, &userptr))) { + dev_err(hdev->dev, "Userptr 0x%llx + 0x%x NOT mapped\n", + addr, user_dma_pkt->tsize); + return -EFAULT; + } + + if ((user_memset) && (dir == DMA_TO_DEVICE)) { + memcpy(new_dma_pkt, user_dma_pkt, sizeof(*user_dma_pkt)); + *new_dma_pkt_size = sizeof(*user_dma_pkt); + return 0; + } + + user_wrcomp_en_mask = ctl & GAUDI_PKT_LIN_DMA_CTL_WRCOMP_EN_MASK; + + sgt = userptr->sgt; + dma_desc_cnt = 0; + + for_each_sg(sgt->sgl, sg, sgt->nents, count) { + len = sg_dma_len(sg); + dma_addr = sg_dma_address(sg); + + if (len == 0) + break; + + while ((count + 1) < sgt->nents) { + sg_next_iter = sg_next(sg); + len_next = sg_dma_len(sg_next_iter); + dma_addr_next = sg_dma_address(sg_next_iter); + + if (len_next == 0) + break; + + if ((dma_addr + len == dma_addr_next) && + (len + len_next <= DMA_MAX_TRANSFER_SIZE)) { + len += len_next; + count++; + sg = sg_next_iter; + } else { + break; + } + } + + new_dma_pkt->ctl = user_dma_pkt->ctl; + + ctl = le32_to_cpu(user_dma_pkt->ctl); + if (likely(dma_desc_cnt)) + ctl &= ~GAUDI_PKT_CTL_EB_MASK; + ctl &= ~GAUDI_PKT_LIN_DMA_CTL_WRCOMP_EN_MASK; + new_dma_pkt->ctl = cpu_to_le32(ctl); + new_dma_pkt->tsize = cpu_to_le32(len); + + if (dir == DMA_TO_DEVICE) { + new_dma_pkt->src_addr = cpu_to_le64(dma_addr); + new_dma_pkt->dst_addr = cpu_to_le64(device_memory_addr); + } else { + new_dma_pkt->src_addr = cpu_to_le64(device_memory_addr); + new_dma_pkt->dst_addr = cpu_to_le64(dma_addr); + } + + if (!user_memset) + device_memory_addr += len; + dma_desc_cnt++; + new_dma_pkt++; + } + + if (!dma_desc_cnt) { + dev_err(hdev->dev, + "Error of 0 SG entries when patching DMA packet\n"); + return -EFAULT; + } + + /* Fix the last dma packet - wrcomp must be as user set it */ + new_dma_pkt--; + new_dma_pkt->ctl |= cpu_to_le32(user_wrcomp_en_mask); + + *new_dma_pkt_size = dma_desc_cnt * sizeof(struct packet_lin_dma); + + return 0; +} + +static int gaudi_patch_cb(struct hl_device *hdev, + struct hl_cs_parser *parser) +{ + u32 cb_parsed_length = 0; + u32 cb_patched_cur_length = 0; + int rc = 0; + + /* cb_user_size is more than 0 so loop will always be executed */ + while (cb_parsed_length < parser->user_cb_size) { + enum packet_id pkt_id; + u16 pkt_size; + u32 new_pkt_size = 0; + struct gaudi_packet *user_pkt, *kernel_pkt; + + user_pkt = (struct gaudi_packet *) (uintptr_t) + (parser->user_cb->kernel_address + cb_parsed_length); + kernel_pkt = (struct gaudi_packet *) (uintptr_t) + (parser->patched_cb->kernel_address + + cb_patched_cur_length); + + pkt_id = (enum packet_id) ( + (le64_to_cpu(user_pkt->header) & + PACKET_HEADER_PACKET_ID_MASK) >> + PACKET_HEADER_PACKET_ID_SHIFT); + + pkt_size = gaudi_packet_sizes[pkt_id]; + cb_parsed_length += pkt_size; + if (cb_parsed_length > parser->user_cb_size) { + dev_err(hdev->dev, + "packet 0x%x is out of CB boundary\n", pkt_id); + rc = -EINVAL; + break; + } + + switch (pkt_id) { + case PACKET_LIN_DMA: + rc = gaudi_patch_dma_packet(hdev, parser, + (struct packet_lin_dma *) user_pkt, + (struct packet_lin_dma *) kernel_pkt, + &new_pkt_size); + cb_patched_cur_length += new_pkt_size; + break; + + case PACKET_MSG_PROT: + dev_err(hdev->dev, + "User not allowed to use MSG_PROT\n"); + rc = -EPERM; + break; + + case PACKET_CP_DMA: + dev_err(hdev->dev, "User not allowed to use CP_DMA\n"); + rc = -EPERM; + break; + + case PACKET_STOP: + dev_err(hdev->dev, "User not allowed to use STOP\n"); + rc = -EPERM; + break; + + case PACKET_WREG_32: + case PACKET_WREG_BULK: + case PACKET_MSG_LONG: + case PACKET_MSG_SHORT: + case PACKET_REPEAT: + case PACKET_FENCE: + case PACKET_NOP: + case PACKET_ARB_POINT: + case PACKET_LOAD_AND_EXE: + memcpy(kernel_pkt, user_pkt, pkt_size); + cb_patched_cur_length += pkt_size; + break; + + default: + dev_err(hdev->dev, "Invalid packet header 0x%x\n", + pkt_id); + rc = -EINVAL; + break; + } + + if (rc) + break; + } + + return rc; +} + +static int gaudi_parse_cb_mmu(struct hl_device *hdev, + struct hl_cs_parser *parser) +{ + u64 patched_cb_handle; + u32 patched_cb_size; + struct hl_cb *user_cb; + int rc; + + /* + * The new CB should have space at the end for two MSG_PROT pkt: + * 1. A packet that will act as a completion packet + * 2. A packet that will generate MSI interrupt + */ + parser->patched_cb_size = parser->user_cb_size + + sizeof(struct packet_msg_prot) * 2; + + rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, + parser->patched_cb_size, + &patched_cb_handle, HL_KERNEL_ASID_ID); + + if (rc) { + dev_err(hdev->dev, + "Failed to allocate patched CB for DMA CS %d\n", + rc); + return rc; + } + + patched_cb_handle >>= PAGE_SHIFT; + parser->patched_cb = hl_cb_get(hdev, &hdev->kernel_cb_mgr, + (u32) patched_cb_handle); + /* hl_cb_get should never fail here so use kernel WARN */ + WARN(!parser->patched_cb, "DMA CB handle invalid 0x%x\n", + (u32) patched_cb_handle); + if (!parser->patched_cb) { + rc = -EFAULT; + goto out; + } + + /* + * The check that parser->user_cb_size <= parser->user_cb->size was done + * in validate_queue_index(). + */ + memcpy((void *) (uintptr_t) parser->patched_cb->kernel_address, + (void *) (uintptr_t) parser->user_cb->kernel_address, + parser->user_cb_size); + + patched_cb_size = parser->patched_cb_size; + + /* Validate patched CB instead of user CB */ + user_cb = parser->user_cb; + parser->user_cb = parser->patched_cb; + rc = gaudi_validate_cb(hdev, parser, true); + parser->user_cb = user_cb; + + if (rc) { + hl_cb_put(parser->patched_cb); + goto out; + } + + if (patched_cb_size != parser->patched_cb_size) { + dev_err(hdev->dev, "user CB size mismatch\n"); + hl_cb_put(parser->patched_cb); + rc = -EINVAL; + goto out; + } + +out: + /* + * Always call cb destroy here because we still have 1 reference + * to it by calling cb_get earlier. After the job will be completed, + * cb_put will release it, but here we want to remove it from the + * idr + */ + hl_cb_destroy(hdev, &hdev->kernel_cb_mgr, + patched_cb_handle << PAGE_SHIFT); + + return rc; +} + +static int gaudi_parse_cb_no_mmu(struct hl_device *hdev, + struct hl_cs_parser *parser) +{ + u64 patched_cb_handle; + int rc; + + rc = gaudi_validate_cb(hdev, parser, false); + + if (rc) + goto free_userptr; + + rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, + parser->patched_cb_size, + &patched_cb_handle, HL_KERNEL_ASID_ID); + if (rc) { + dev_err(hdev->dev, + "Failed to allocate patched CB for DMA CS %d\n", rc); + goto free_userptr; + } + + patched_cb_handle >>= PAGE_SHIFT; + parser->patched_cb = hl_cb_get(hdev, &hdev->kernel_cb_mgr, + (u32) patched_cb_handle); + /* hl_cb_get should never fail here so use kernel WARN */ + WARN(!parser->patched_cb, "DMA CB handle invalid 0x%x\n", + (u32) patched_cb_handle); + if (!parser->patched_cb) { + rc = -EFAULT; + goto out; + } + + rc = gaudi_patch_cb(hdev, parser); + + if (rc) + hl_cb_put(parser->patched_cb); + +out: + /* + * Always call cb destroy here because we still have 1 reference + * to it by calling cb_get earlier. After the job will be completed, + * cb_put will release it, but here we want to remove it from the + * idr + */ + hl_cb_destroy(hdev, &hdev->kernel_cb_mgr, + patched_cb_handle << PAGE_SHIFT); + +free_userptr: + if (rc) + hl_userptr_delete_list(hdev, parser->job_userptr_list); + return rc; +} + +static int gaudi_parse_cb_no_ext_queue(struct hl_device *hdev, + struct hl_cs_parser *parser) +{ + struct asic_fixed_properties *asic_prop = &hdev->asic_prop; + + /* For internal queue jobs just check if CB address is valid */ + if (hl_mem_area_inside_range((u64) (uintptr_t) parser->user_cb, + parser->user_cb_size, + asic_prop->sram_user_base_address, + asic_prop->sram_end_address)) + return 0; + + if (hl_mem_area_inside_range((u64) (uintptr_t) parser->user_cb, + parser->user_cb_size, + asic_prop->dram_user_base_address, + asic_prop->dram_end_address)) + return 0; + + /* PMMU and HPMMU addresses are equal, check only one of them */ + if (hl_mem_area_inside_range((u64) (uintptr_t) parser->user_cb, + parser->user_cb_size, + asic_prop->pmmu.start_addr, + asic_prop->pmmu.end_addr)) + return 0; + + dev_err(hdev->dev, + "CB address 0x%px + 0x%x for internal QMAN is not valid\n", + parser->user_cb, parser->user_cb_size); + + return -EFAULT; +} + +static int gaudi_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (parser->queue_type == QUEUE_TYPE_INT) + return gaudi_parse_cb_no_ext_queue(hdev, parser); + + if (gaudi->hw_cap_initialized & HW_CAP_MMU) + return gaudi_parse_cb_mmu(hdev, parser); + else + return gaudi_parse_cb_no_mmu(hdev, parser); +} + +static void gaudi_add_end_of_cb_packets(struct hl_device *hdev, + u64 kernel_address, u32 len, + u64 cq_addr, u32 cq_val, u32 msi_vec, + bool eb) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + struct packet_msg_prot *cq_pkt; + u32 tmp; + + cq_pkt = (struct packet_msg_prot *) (uintptr_t) + (kernel_address + len - (sizeof(struct packet_msg_prot) * 2)); + + tmp = (PACKET_MSG_PROT << GAUDI_PKT_CTL_OPCODE_SHIFT) | + (1 << GAUDI_PKT_CTL_MB_SHIFT); + + if (eb) + tmp |= (1 << GAUDI_PKT_CTL_EB_SHIFT); + + cq_pkt->ctl = cpu_to_le32(tmp); + cq_pkt->value = cpu_to_le32(cq_val); + cq_pkt->addr = cpu_to_le64(cq_addr); + + cq_pkt++; + + tmp = (PACKET_MSG_PROT << GAUDI_PKT_CTL_OPCODE_SHIFT) | + (1 << GAUDI_PKT_CTL_MB_SHIFT); + cq_pkt->ctl = cpu_to_le32(tmp); + cq_pkt->value = cpu_to_le32(1); + + if (!gaudi->multi_msi_mode) + msi_vec = 0; + + cq_pkt->addr = cpu_to_le64(CFG_BASE + mmPCIE_MSI_INTR_0 + msi_vec * 4); +} + +static void gaudi_update_eq_ci(struct hl_device *hdev, u32 val) +{ + WREG32(mmCPU_IF_EQ_RD_OFFS, val); +} + +static int gaudi_memset_device_memory(struct hl_device *hdev, u64 addr, + u32 size, u64 val) +{ + struct packet_lin_dma *lin_dma_pkt; + struct hl_cs_job *job; + u32 cb_size, ctl; + struct hl_cb *cb; + int rc; + + cb = hl_cb_kernel_create(hdev, PAGE_SIZE); + if (!cb) + return -EFAULT; + + lin_dma_pkt = (struct packet_lin_dma *) (uintptr_t) cb->kernel_address; + memset(lin_dma_pkt, 0, sizeof(*lin_dma_pkt)); + cb_size = sizeof(*lin_dma_pkt); + + ctl = ((PACKET_LIN_DMA << GAUDI_PKT_CTL_OPCODE_SHIFT) | + (1 << GAUDI_PKT_LIN_DMA_CTL_MEMSET_SHIFT) | + (1 << GAUDI_PKT_LIN_DMA_CTL_LIN_SHIFT) | + (1 << GAUDI_PKT_CTL_RB_SHIFT) | + (1 << GAUDI_PKT_CTL_MB_SHIFT)); + lin_dma_pkt->ctl = cpu_to_le32(ctl); + lin_dma_pkt->src_addr = cpu_to_le64(val); + lin_dma_pkt->dst_addr |= cpu_to_le64(addr); + lin_dma_pkt->tsize = cpu_to_le32(size); + + job = hl_cs_allocate_job(hdev, QUEUE_TYPE_EXT, true); + if (!job) { + dev_err(hdev->dev, "Failed to allocate a new job\n"); + rc = -ENOMEM; + goto release_cb; + } + + job->id = 0; + job->user_cb = cb; + job->user_cb->cs_cnt++; + job->user_cb_size = cb_size; + job->hw_queue_id = GAUDI_QUEUE_ID_DMA_0_0; + job->patched_cb = job->user_cb; + job->job_cb_size = job->user_cb_size + sizeof(struct packet_msg_prot); + + hl_debugfs_add_job(hdev, job); + + rc = gaudi_send_job_on_qman0(hdev, job); + + hl_debugfs_remove_job(hdev, job); + kfree(job); + cb->cs_cnt--; + +release_cb: + hl_cb_put(cb); + hl_cb_destroy(hdev, &hdev->kernel_cb_mgr, cb->id << PAGE_SHIFT); + + return rc; +} + +static void gaudi_restore_sm_registers(struct hl_device *hdev) +{ + int i; + + for (i = 0 ; i < NUM_OF_SOB_IN_BLOCK << 2 ; i += 4) { + WREG32(mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0 + i, 0); + WREG32(mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_SOB_OBJ_0 + i, 0); + WREG32(mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_SOB_OBJ_0 + i, 0); + } + + for (i = 0 ; i < NUM_OF_MONITORS_IN_BLOCK << 2 ; i += 4) { + WREG32(mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_0 + i, 0); + WREG32(mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_MON_STATUS_0 + i, 0); + WREG32(mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_MON_STATUS_0 + i, 0); + } + + i = GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT * 4; + + for (; i < NUM_OF_SOB_IN_BLOCK << 2 ; i += 4) + WREG32(mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0 + i, 0); + + i = GAUDI_FIRST_AVAILABLE_W_S_MONITOR * 4; + + for (; i < NUM_OF_MONITORS_IN_BLOCK << 2 ; i += 4) + WREG32(mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0 + i, 0); +} + +static void gaudi_restore_dma_registers(struct hl_device *hdev) +{ + u32 sob_delta = mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_1 - + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0; + int i; + + for (i = 0 ; i < DMA_NUMBER_OF_CHANNELS ; i++) { + u64 sob_addr = CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0 + + (i * sob_delta); + u32 dma_offset = i * DMA_CORE_OFFSET; + + WREG32(mmDMA0_CORE_WR_COMP_ADDR_LO + dma_offset, + lower_32_bits(sob_addr)); + WREG32(mmDMA0_CORE_WR_COMP_ADDR_HI + dma_offset, + upper_32_bits(sob_addr)); + WREG32(mmDMA0_CORE_WR_COMP_WDATA + dma_offset, 0x80000001); + + /* For DMAs 2-7, need to restore WR_AWUSER_31_11 as it can be + * modified by the user for SRAM reduction + */ + if (i > 1) + WREG32(mmDMA0_CORE_WR_AWUSER_31_11 + dma_offset, + 0x00000001); + } +} + +static void gaudi_restore_qm_registers(struct hl_device *hdev) +{ + u32 qman_offset; + int i; + + for (i = 0 ; i < DMA_NUMBER_OF_CHANNELS ; i++) { + qman_offset = i * DMA_QMAN_OFFSET; + WREG32(mmDMA0_QM_ARB_CFG_0 + qman_offset, 0); + } + + for (i = 0 ; i < MME_NUMBER_OF_MASTER_ENGINES ; i++) { + qman_offset = i * (mmMME2_QM_BASE - mmMME0_QM_BASE); + WREG32(mmMME0_QM_ARB_CFG_0 + qman_offset, 0); + } + + for (i = 0 ; i < TPC_NUMBER_OF_ENGINES ; i++) { + qman_offset = i * TPC_QMAN_OFFSET; + WREG32(mmTPC0_QM_ARB_CFG_0 + qman_offset, 0); + } +} + +static void gaudi_restore_user_registers(struct hl_device *hdev) +{ + gaudi_restore_sm_registers(hdev); + gaudi_restore_dma_registers(hdev); + gaudi_restore_qm_registers(hdev); +} + +static int gaudi_context_switch(struct hl_device *hdev, u32 asid) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + u64 addr = prop->sram_user_base_address; + u32 size = hdev->pldm ? 0x10000 : + (prop->sram_size - SRAM_USER_BASE_OFFSET); + u64 val = 0x7777777777777777ull; + int rc; + + rc = gaudi_memset_device_memory(hdev, addr, size, val); + if (rc) { + dev_err(hdev->dev, "Failed to clear SRAM in context switch\n"); + return rc; + } + + gaudi_mmu_prepare(hdev, asid); + + gaudi_restore_user_registers(hdev); + + return 0; +} + +static int gaudi_mmu_clear_pgt_range(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct gaudi_device *gaudi = hdev->asic_specific; + u64 addr = prop->mmu_pgt_addr; + u32 size = prop->mmu_pgt_size + MMU_CACHE_MNG_SIZE; + + if (!(gaudi->hw_cap_initialized & HW_CAP_MMU)) + return 0; + + return gaudi_memset_device_memory(hdev, addr, size, 0); +} + +static void gaudi_restore_phase_topology(struct hl_device *hdev) +{ + +} + +static int gaudi_debugfs_read32(struct hl_device *hdev, u64 addr, u32 *val) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct gaudi_device *gaudi = hdev->asic_specific; + u64 hbm_bar_addr; + int rc = 0; + + if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) { + if (gaudi->hw_cap_initialized & HW_CAP_CLK_GATE) { + dev_err_ratelimited(hdev->dev, + "Can't read register - clock gating is enabled!\n"); + rc = -EFAULT; + } else { + *val = RREG32(addr - CFG_BASE); + } + } else if ((addr >= SRAM_BASE_ADDR) && + (addr < SRAM_BASE_ADDR + SRAM_BAR_SIZE)) { + *val = readl(hdev->pcie_bar[SRAM_BAR_ID] + + (addr - SRAM_BASE_ADDR)); + } else if (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size) { + u64 bar_base_addr = DRAM_PHYS_BASE + + (addr & ~(prop->dram_pci_bar_size - 0x1ull)); + + hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, bar_base_addr); + if (hbm_bar_addr != U64_MAX) { + *val = readl(hdev->pcie_bar[HBM_BAR_ID] + + (addr - bar_base_addr)); + + hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, + hbm_bar_addr); + } + if (hbm_bar_addr == U64_MAX) + rc = -EIO; + } else if (addr >= HOST_PHYS_BASE && !iommu_present(&pci_bus_type)) { + *val = *(u32 *) phys_to_virt(addr - HOST_PHYS_BASE); + } else { + rc = -EFAULT; + } + + return rc; +} + +static int gaudi_debugfs_write32(struct hl_device *hdev, u64 addr, u32 val) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct gaudi_device *gaudi = hdev->asic_specific; + u64 hbm_bar_addr; + int rc = 0; + + if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) { + if (gaudi->hw_cap_initialized & HW_CAP_CLK_GATE) { + dev_err_ratelimited(hdev->dev, + "Can't write register - clock gating is enabled!\n"); + rc = -EFAULT; + } else { + WREG32(addr - CFG_BASE, val); + } + } else if ((addr >= SRAM_BASE_ADDR) && + (addr < SRAM_BASE_ADDR + SRAM_BAR_SIZE)) { + writel(val, hdev->pcie_bar[SRAM_BAR_ID] + + (addr - SRAM_BASE_ADDR)); + } else if (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size) { + u64 bar_base_addr = DRAM_PHYS_BASE + + (addr & ~(prop->dram_pci_bar_size - 0x1ull)); + + hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, bar_base_addr); + if (hbm_bar_addr != U64_MAX) { + writel(val, hdev->pcie_bar[HBM_BAR_ID] + + (addr - bar_base_addr)); + + hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, + hbm_bar_addr); + } + if (hbm_bar_addr == U64_MAX) + rc = -EIO; + } else if (addr >= HOST_PHYS_BASE && !iommu_present(&pci_bus_type)) { + *(u32 *) phys_to_virt(addr - HOST_PHYS_BASE) = val; + } else { + rc = -EFAULT; + } + + return rc; +} + +static int gaudi_debugfs_read64(struct hl_device *hdev, u64 addr, u64 *val) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct gaudi_device *gaudi = hdev->asic_specific; + u64 hbm_bar_addr; + int rc = 0; + + if ((addr >= CFG_BASE) && (addr <= CFG_BASE + CFG_SIZE - sizeof(u64))) { + if (gaudi->hw_cap_initialized & HW_CAP_CLK_GATE) { + dev_err_ratelimited(hdev->dev, + "Can't read register - clock gating is enabled!\n"); + rc = -EFAULT; + } else { + u32 val_l = RREG32(addr - CFG_BASE); + u32 val_h = RREG32(addr + sizeof(u32) - CFG_BASE); + + *val = (((u64) val_h) << 32) | val_l; + } + } else if ((addr >= SRAM_BASE_ADDR) && + (addr <= SRAM_BASE_ADDR + SRAM_BAR_SIZE - sizeof(u64))) { + *val = readq(hdev->pcie_bar[SRAM_BAR_ID] + + (addr - SRAM_BASE_ADDR)); + } else if (addr <= + DRAM_PHYS_BASE + hdev->asic_prop.dram_size - sizeof(u64)) { + u64 bar_base_addr = DRAM_PHYS_BASE + + (addr & ~(prop->dram_pci_bar_size - 0x1ull)); + + hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, bar_base_addr); + if (hbm_bar_addr != U64_MAX) { + *val = readq(hdev->pcie_bar[HBM_BAR_ID] + + (addr - bar_base_addr)); + + hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, + hbm_bar_addr); + } + if (hbm_bar_addr == U64_MAX) + rc = -EIO; + } else if (addr >= HOST_PHYS_BASE && !iommu_present(&pci_bus_type)) { + *val = *(u64 *) phys_to_virt(addr - HOST_PHYS_BASE); + } else { + rc = -EFAULT; + } + + return rc; +} + +static int gaudi_debugfs_write64(struct hl_device *hdev, u64 addr, u64 val) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct gaudi_device *gaudi = hdev->asic_specific; + u64 hbm_bar_addr; + int rc = 0; + + if ((addr >= CFG_BASE) && (addr <= CFG_BASE + CFG_SIZE - sizeof(u64))) { + if (gaudi->hw_cap_initialized & HW_CAP_CLK_GATE) { + dev_err_ratelimited(hdev->dev, + "Can't write register - clock gating is enabled!\n"); + rc = -EFAULT; + } else { + WREG32(addr - CFG_BASE, lower_32_bits(val)); + WREG32(addr + sizeof(u32) - CFG_BASE, + upper_32_bits(val)); + } + } else if ((addr >= SRAM_BASE_ADDR) && + (addr <= SRAM_BASE_ADDR + SRAM_BAR_SIZE - sizeof(u64))) { + writeq(val, hdev->pcie_bar[SRAM_BAR_ID] + + (addr - SRAM_BASE_ADDR)); + } else if (addr <= + DRAM_PHYS_BASE + hdev->asic_prop.dram_size - sizeof(u64)) { + u64 bar_base_addr = DRAM_PHYS_BASE + + (addr & ~(prop->dram_pci_bar_size - 0x1ull)); + + hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, bar_base_addr); + if (hbm_bar_addr != U64_MAX) { + writeq(val, hdev->pcie_bar[HBM_BAR_ID] + + (addr - bar_base_addr)); + + hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, + hbm_bar_addr); + } + if (hbm_bar_addr == U64_MAX) + rc = -EIO; + } else if (addr >= HOST_PHYS_BASE && !iommu_present(&pci_bus_type)) { + *(u64 *) phys_to_virt(addr - HOST_PHYS_BASE) = val; + } else { + rc = -EFAULT; + } + + return rc; +} + +static u64 gaudi_read_pte(struct hl_device *hdev, u64 addr) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (hdev->hard_reset_pending) + return U64_MAX; + + return readq(hdev->pcie_bar[HBM_BAR_ID] + + (addr - gaudi->hbm_bar_cur_addr)); +} + +static void gaudi_write_pte(struct hl_device *hdev, u64 addr, u64 val) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (hdev->hard_reset_pending) + return; + + writeq(val, hdev->pcie_bar[HBM_BAR_ID] + + (addr - gaudi->hbm_bar_cur_addr)); +} + +static void gaudi_mmu_prepare_reg(struct hl_device *hdev, u64 reg, u32 asid) +{ + /* mask to zero the MMBP and ASID bits */ + WREG32_AND(reg, ~0x7FF); + WREG32_OR(reg, asid); +} + +static void gaudi_mmu_prepare(struct hl_device *hdev, u32 asid) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_MMU)) + return; + + if (asid & ~DMA0_QM_GLBL_NON_SECURE_PROPS_0_ASID_MASK) { + WARN(1, "asid %u is too big\n", asid); + return; + } + + mutex_lock(&gaudi->clk_gate_mutex); + + hdev->asic_funcs->disable_clock_gating(hdev); + + gaudi_mmu_prepare_reg(hdev, mmDMA0_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA0_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA0_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA0_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA0_QM_GLBL_NON_SECURE_PROPS_4, asid); + + gaudi_mmu_prepare_reg(hdev, mmDMA1_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA1_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA1_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA1_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA1_QM_GLBL_NON_SECURE_PROPS_4, asid); + + gaudi_mmu_prepare_reg(hdev, mmDMA2_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA2_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA2_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA2_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA2_QM_GLBL_NON_SECURE_PROPS_4, asid); + + gaudi_mmu_prepare_reg(hdev, mmDMA3_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA3_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA3_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA3_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA3_QM_GLBL_NON_SECURE_PROPS_4, asid); + + gaudi_mmu_prepare_reg(hdev, mmDMA4_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA4_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA4_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA4_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA4_QM_GLBL_NON_SECURE_PROPS_4, asid); + + gaudi_mmu_prepare_reg(hdev, mmDMA5_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA5_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA5_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA5_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA5_QM_GLBL_NON_SECURE_PROPS_4, asid); + + gaudi_mmu_prepare_reg(hdev, mmDMA6_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA6_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA6_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA6_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA6_QM_GLBL_NON_SECURE_PROPS_4, asid); + + gaudi_mmu_prepare_reg(hdev, mmDMA7_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA7_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA7_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA7_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA7_QM_GLBL_NON_SECURE_PROPS_4, asid); + + gaudi_mmu_prepare_reg(hdev, mmDMA0_CORE_NON_SECURE_PROPS, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA1_CORE_NON_SECURE_PROPS, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA2_CORE_NON_SECURE_PROPS, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA3_CORE_NON_SECURE_PROPS, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA4_CORE_NON_SECURE_PROPS, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA5_CORE_NON_SECURE_PROPS, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA6_CORE_NON_SECURE_PROPS, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA7_CORE_NON_SECURE_PROPS, asid); + + gaudi_mmu_prepare_reg(hdev, mmTPC0_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC0_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC0_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC0_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC0_QM_GLBL_NON_SECURE_PROPS_4, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC0_CFG_ARUSER_LO, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC0_CFG_AWUSER_LO, asid); + + gaudi_mmu_prepare_reg(hdev, mmTPC1_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC1_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC1_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC1_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC1_QM_GLBL_NON_SECURE_PROPS_4, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC1_CFG_ARUSER_LO, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC1_CFG_AWUSER_LO, asid); + + gaudi_mmu_prepare_reg(hdev, mmTPC2_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC2_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC2_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC2_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC2_QM_GLBL_NON_SECURE_PROPS_4, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC2_CFG_ARUSER_LO, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC2_CFG_AWUSER_LO, asid); + + gaudi_mmu_prepare_reg(hdev, mmTPC3_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC3_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC3_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC3_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC3_QM_GLBL_NON_SECURE_PROPS_4, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC3_CFG_ARUSER_LO, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC3_CFG_AWUSER_LO, asid); + + gaudi_mmu_prepare_reg(hdev, mmTPC4_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC4_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC4_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC4_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC4_QM_GLBL_NON_SECURE_PROPS_4, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC4_CFG_ARUSER_LO, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC4_CFG_AWUSER_LO, asid); + + gaudi_mmu_prepare_reg(hdev, mmTPC5_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC5_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC5_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC5_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC5_QM_GLBL_NON_SECURE_PROPS_4, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC5_CFG_ARUSER_LO, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC5_CFG_AWUSER_LO, asid); + + gaudi_mmu_prepare_reg(hdev, mmTPC6_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC6_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC6_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC6_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC6_QM_GLBL_NON_SECURE_PROPS_4, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC6_CFG_ARUSER_LO, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC6_CFG_AWUSER_LO, asid); + + gaudi_mmu_prepare_reg(hdev, mmTPC7_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC7_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC7_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC7_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC7_QM_GLBL_NON_SECURE_PROPS_4, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC7_CFG_ARUSER_LO, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC7_CFG_AWUSER_LO, asid); + + gaudi_mmu_prepare_reg(hdev, mmMME0_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmMME0_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmMME0_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmMME0_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmMME0_QM_GLBL_NON_SECURE_PROPS_4, asid); + gaudi_mmu_prepare_reg(hdev, mmMME2_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmMME2_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmMME2_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmMME2_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmMME2_QM_GLBL_NON_SECURE_PROPS_4, asid); + + gaudi_mmu_prepare_reg(hdev, mmMME0_SBAB_ARUSER0, asid); + gaudi_mmu_prepare_reg(hdev, mmMME0_SBAB_ARUSER1, asid); + gaudi_mmu_prepare_reg(hdev, mmMME1_SBAB_ARUSER0, asid); + gaudi_mmu_prepare_reg(hdev, mmMME1_SBAB_ARUSER1, asid); + gaudi_mmu_prepare_reg(hdev, mmMME2_SBAB_ARUSER0, asid); + gaudi_mmu_prepare_reg(hdev, mmMME2_SBAB_ARUSER1, asid); + gaudi_mmu_prepare_reg(hdev, mmMME3_SBAB_ARUSER0, asid); + gaudi_mmu_prepare_reg(hdev, mmMME3_SBAB_ARUSER1, asid); + gaudi_mmu_prepare_reg(hdev, mmMME0_ACC_WBC, asid); + gaudi_mmu_prepare_reg(hdev, mmMME1_ACC_WBC, asid); + gaudi_mmu_prepare_reg(hdev, mmMME2_ACC_WBC, asid); + gaudi_mmu_prepare_reg(hdev, mmMME3_ACC_WBC, asid); + + gaudi_mmu_prepare_reg(hdev, mmPSOC_GLOBAL_CONF_TRACE_ARUSER, asid); + gaudi_mmu_prepare_reg(hdev, mmPSOC_GLOBAL_CONF_TRACE_AWUSER, asid); + + hdev->asic_funcs->enable_clock_gating(hdev); + + mutex_unlock(&gaudi->clk_gate_mutex); +} + +static int gaudi_send_job_on_qman0(struct hl_device *hdev, + struct hl_cs_job *job) +{ + struct packet_msg_prot *fence_pkt; + u32 *fence_ptr; + dma_addr_t fence_dma_addr; + struct hl_cb *cb; + u32 tmp, timeout, dma_offset; + int rc; + + if (hdev->pldm) + timeout = GAUDI_PLDM_QMAN0_TIMEOUT_USEC; + else + timeout = HL_DEVICE_TIMEOUT_USEC; + + if (!hdev->asic_funcs->is_device_idle(hdev, NULL, NULL)) { + dev_err_ratelimited(hdev->dev, + "Can't send driver job on QMAN0 because the device is not idle\n"); + return -EBUSY; + } + + fence_ptr = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL, + &fence_dma_addr); + if (!fence_ptr) { + dev_err(hdev->dev, + "Failed to allocate fence memory for QMAN0\n"); + return -ENOMEM; + } + + cb = job->patched_cb; + + fence_pkt = (struct packet_msg_prot *) (uintptr_t) (cb->kernel_address + + job->job_cb_size - sizeof(struct packet_msg_prot)); + + tmp = (PACKET_MSG_PROT << GAUDI_PKT_CTL_OPCODE_SHIFT) | + (1 << GAUDI_PKT_CTL_EB_SHIFT) | + (1 << GAUDI_PKT_CTL_MB_SHIFT); + fence_pkt->ctl = cpu_to_le32(tmp); + fence_pkt->value = cpu_to_le32(GAUDI_QMAN0_FENCE_VAL); + fence_pkt->addr = cpu_to_le64(fence_dma_addr); + + dma_offset = gaudi_dma_assignment[GAUDI_PCI_DMA_1] * DMA_CORE_OFFSET; + + WREG32_OR(mmDMA0_CORE_PROT + dma_offset, BIT(DMA0_CORE_PROT_VAL_SHIFT)); + + rc = hl_hw_queue_send_cb_no_cmpl(hdev, GAUDI_QUEUE_ID_DMA_0_0, + job->job_cb_size, cb->bus_address); + if (rc) { + dev_err(hdev->dev, "Failed to send CB on QMAN0, %d\n", rc); + goto free_fence_ptr; + } + + rc = hl_poll_timeout_memory(hdev, fence_ptr, tmp, + (tmp == GAUDI_QMAN0_FENCE_VAL), 1000, + timeout, true); + + hl_hw_queue_inc_ci_kernel(hdev, GAUDI_QUEUE_ID_DMA_0_0); + + if (rc == -ETIMEDOUT) { + dev_err(hdev->dev, "QMAN0 Job timeout (0x%x)\n", tmp); + goto free_fence_ptr; + } + +free_fence_ptr: + WREG32_AND(mmDMA0_CORE_PROT + dma_offset, + ~BIT(DMA0_CORE_PROT_VAL_SHIFT)); + + hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_ptr, + fence_dma_addr); + return rc; +} + +static void gaudi_get_event_desc(u16 event_type, char *desc, size_t size) +{ + if (event_type >= GAUDI_EVENT_SIZE) + goto event_not_supported; + + if (!gaudi_irq_map_table[event_type].valid) + goto event_not_supported; + + snprintf(desc, size, gaudi_irq_map_table[event_type].name); + + return; + +event_not_supported: + snprintf(desc, size, "N/A"); +} + +static const char *gaudi_get_razwi_initiator_dma_name(struct hl_device *hdev, + u32 x_y, bool is_write) +{ + u32 dma_id[2], dma_offset, err_cause[2], mask, i; + + mask = is_write ? DMA0_CORE_ERR_CAUSE_HBW_WR_ERR_MASK : + DMA0_CORE_ERR_CAUSE_HBW_RD_ERR_MASK; + + switch (x_y) { + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_0: + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_1: + dma_id[0] = 0; + dma_id[1] = 2; + break; + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_0: + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_1: + dma_id[0] = 1; + dma_id[1] = 3; + break; + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_0: + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_1: + dma_id[0] = 4; + dma_id[1] = 6; + break; + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_0: + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_1: + dma_id[0] = 5; + dma_id[1] = 7; + break; + default: + goto unknown_initiator; + } + + for (i = 0 ; i < 2 ; i++) { + dma_offset = dma_id[i] * DMA_CORE_OFFSET; + err_cause[i] = RREG32(mmDMA0_CORE_ERR_CAUSE + dma_offset); + } + + switch (x_y) { + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_0: + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_1: + if ((err_cause[0] & mask) && !(err_cause[1] & mask)) + return "DMA0"; + else if (!(err_cause[0] & mask) && (err_cause[1] & mask)) + return "DMA2"; + else + return "DMA0 or DMA2"; + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_0: + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_1: + if ((err_cause[0] & mask) && !(err_cause[1] & mask)) + return "DMA1"; + else if (!(err_cause[0] & mask) && (err_cause[1] & mask)) + return "DMA3"; + else + return "DMA1 or DMA3"; + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_0: + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_1: + if ((err_cause[0] & mask) && !(err_cause[1] & mask)) + return "DMA4"; + else if (!(err_cause[0] & mask) && (err_cause[1] & mask)) + return "DMA6"; + else + return "DMA4 or DMA6"; + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_0: + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_1: + if ((err_cause[0] & mask) && !(err_cause[1] & mask)) + return "DMA5"; + else if (!(err_cause[0] & mask) && (err_cause[1] & mask)) + return "DMA7"; + else + return "DMA5 or DMA7"; + } + +unknown_initiator: + return "unknown initiator"; +} + +static const char *gaudi_get_razwi_initiator_name(struct hl_device *hdev, + bool is_write) +{ + u32 val, x_y, axi_id; + + val = is_write ? RREG32(mmMMU_UP_RAZWI_WRITE_ID) : + RREG32(mmMMU_UP_RAZWI_READ_ID); + x_y = val & ((RAZWI_INITIATOR_Y_MASK << RAZWI_INITIATOR_Y_SHIFT) | + (RAZWI_INITIATOR_X_MASK << RAZWI_INITIATOR_X_SHIFT)); + axi_id = val & (RAZWI_INITIATOR_AXI_ID_MASK << + RAZWI_INITIATOR_AXI_ID_SHIFT); + + switch (x_y) { + case RAZWI_INITIATOR_ID_X_Y_TPC0_NIC0: + if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_TPC)) + return "TPC0"; + if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_NIC)) + return "NIC0"; + break; + case RAZWI_INITIATOR_ID_X_Y_TPC1: + return "TPC1"; + case RAZWI_INITIATOR_ID_X_Y_MME0_0: + case RAZWI_INITIATOR_ID_X_Y_MME0_1: + return "MME0"; + case RAZWI_INITIATOR_ID_X_Y_MME1_0: + case RAZWI_INITIATOR_ID_X_Y_MME1_1: + return "MME1"; + case RAZWI_INITIATOR_ID_X_Y_TPC2: + return "TPC2"; + case RAZWI_INITIATOR_ID_X_Y_TPC3_PCI_CPU_PSOC: + if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_TPC)) + return "TPC3"; + if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_PCI)) + return "PCI"; + if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_CPU)) + return "CPU"; + if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_PSOC)) + return "PSOC"; + break; + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_0: + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_1: + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_0: + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_1: + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_0: + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_1: + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_0: + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_1: + return gaudi_get_razwi_initiator_dma_name(hdev, x_y, is_write); + case RAZWI_INITIATOR_ID_X_Y_TPC4_NIC1_NIC2: + if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_TPC)) + return "TPC4"; + if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_NIC)) + return "NIC1"; + if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_NIC_FT)) + return "NIC2"; + break; + case RAZWI_INITIATOR_ID_X_Y_TPC5: + return "TPC5"; + case RAZWI_INITIATOR_ID_X_Y_MME2_0: + case RAZWI_INITIATOR_ID_X_Y_MME2_1: + return "MME2"; + case RAZWI_INITIATOR_ID_X_Y_MME3_0: + case RAZWI_INITIATOR_ID_X_Y_MME3_1: + return "MME3"; + case RAZWI_INITIATOR_ID_X_Y_TPC6: + return "TPC6"; + case RAZWI_INITIATOR_ID_X_Y_TPC7_NIC4_NIC5: + if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_TPC)) + return "TPC7"; + if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_NIC)) + return "NIC4"; + if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_NIC_FT)) + return "NIC5"; + break; + default: + break; + } + + dev_err(hdev->dev, + "Unknown RAZWI initiator ID 0x%x [Y=%d, X=%d, AXI_ID=%d]\n", + val, + (val >> RAZWI_INITIATOR_Y_SHIFT) & RAZWI_INITIATOR_Y_MASK, + (val >> RAZWI_INITIATOR_X_SHIFT) & RAZWI_INITIATOR_X_MASK, + (val >> RAZWI_INITIATOR_AXI_ID_SHIFT) & + RAZWI_INITIATOR_AXI_ID_MASK); + + return "unknown initiator"; +} + +static void gaudi_print_razwi_info(struct hl_device *hdev) +{ + if (RREG32(mmMMU_UP_RAZWI_WRITE_VLD)) { + dev_err_ratelimited(hdev->dev, + "RAZWI event caused by illegal write of %s\n", + gaudi_get_razwi_initiator_name(hdev, true)); + WREG32(mmMMU_UP_RAZWI_WRITE_VLD, 0); + } + + if (RREG32(mmMMU_UP_RAZWI_READ_VLD)) { + dev_err_ratelimited(hdev->dev, + "RAZWI event caused by illegal read of %s\n", + gaudi_get_razwi_initiator_name(hdev, false)); + WREG32(mmMMU_UP_RAZWI_READ_VLD, 0); + } +} + +static void gaudi_print_mmu_error_info(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + u64 addr; + u32 val; + + if (!(gaudi->hw_cap_initialized & HW_CAP_MMU)) + return; + + val = RREG32(mmMMU_UP_PAGE_ERROR_CAPTURE); + if (val & MMU_UP_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK) { + addr = val & MMU_UP_PAGE_ERROR_CAPTURE_VA_49_32_MASK; + addr <<= 32; + addr |= RREG32(mmMMU_UP_PAGE_ERROR_CAPTURE_VA); + + dev_err_ratelimited(hdev->dev, "MMU page fault on va 0x%llx\n", + addr); + + WREG32(mmMMU_UP_PAGE_ERROR_CAPTURE, 0); + } + + val = RREG32(mmMMU_UP_ACCESS_ERROR_CAPTURE); + if (val & MMU_UP_ACCESS_ERROR_CAPTURE_ENTRY_VALID_MASK) { + addr = val & MMU_UP_ACCESS_ERROR_CAPTURE_VA_49_32_MASK; + addr <<= 32; + addr |= RREG32(mmMMU_UP_ACCESS_ERROR_CAPTURE_VA); + + dev_err_ratelimited(hdev->dev, + "MMU access error on va 0x%llx\n", addr); + + WREG32(mmMMU_UP_ACCESS_ERROR_CAPTURE, 0); + } +} + +/* + * +-------------------+------------------------------------------------------+ + * | Configuration Reg | Description | + * | Address | | + * +-------------------+------------------------------------------------------+ + * | 0xF30 - 0xF3F |ECC single error indication (1 bit per memory wrapper)| + * | |0xF30 memory wrappers 31:0 (MSB to LSB) | + * | |0xF34 memory wrappers 63:32 | + * | |0xF38 memory wrappers 95:64 | + * | |0xF3C memory wrappers 127:96 | + * +-------------------+------------------------------------------------------+ + * | 0xF40 - 0xF4F |ECC double error indication (1 bit per memory wrapper)| + * | |0xF40 memory wrappers 31:0 (MSB to LSB) | + * | |0xF44 memory wrappers 63:32 | + * | |0xF48 memory wrappers 95:64 | + * | |0xF4C memory wrappers 127:96 | + * +-------------------+------------------------------------------------------+ + */ +static void gaudi_print_ecc_info_generic(struct hl_device *hdev, + const char *block_name, + u64 block_address, int num_memories, + bool derr, bool disable_clock_gating) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + int num_mem_regs = num_memories / 32 + ((num_memories % 32) ? 1 : 0); + + if (block_address >= CFG_BASE) + block_address -= CFG_BASE; + + if (derr) + block_address += GAUDI_ECC_DERR0_OFFSET; + else + block_address += GAUDI_ECC_SERR0_OFFSET; + + if (disable_clock_gating) { + mutex_lock(&gaudi->clk_gate_mutex); + hdev->asic_funcs->disable_clock_gating(hdev); + } + + switch (num_mem_regs) { + case 1: + dev_err(hdev->dev, + "%s ECC indication: 0x%08x\n", + block_name, RREG32(block_address)); + break; + case 2: + dev_err(hdev->dev, + "%s ECC indication: 0x%08x 0x%08x\n", + block_name, + RREG32(block_address), RREG32(block_address + 4)); + break; + case 3: + dev_err(hdev->dev, + "%s ECC indication: 0x%08x 0x%08x 0x%08x\n", + block_name, + RREG32(block_address), RREG32(block_address + 4), + RREG32(block_address + 8)); + break; + case 4: + dev_err(hdev->dev, + "%s ECC indication: 0x%08x 0x%08x 0x%08x 0x%08x\n", + block_name, + RREG32(block_address), RREG32(block_address + 4), + RREG32(block_address + 8), RREG32(block_address + 0xc)); + break; + default: + break; + + } + + if (disable_clock_gating) { + hdev->asic_funcs->enable_clock_gating(hdev); + mutex_unlock(&gaudi->clk_gate_mutex); + } +} + +static void gaudi_handle_qman_err_generic(struct hl_device *hdev, + const char *qm_name, + u64 glbl_sts_addr, + u64 arb_err_addr) +{ + u32 i, j, glbl_sts_val, arb_err_val, glbl_sts_clr_val; + char reg_desc[32]; + + /* Iterate through all stream GLBL_STS1 registers + Lower CP */ + for (i = 0 ; i < QMAN_STREAMS + 1 ; i++) { + glbl_sts_clr_val = 0; + glbl_sts_val = RREG32(glbl_sts_addr + 4 * i); + + if (!glbl_sts_val) + continue; + + if (i == QMAN_STREAMS) + snprintf(reg_desc, ARRAY_SIZE(reg_desc), "LowerCP"); + else + snprintf(reg_desc, ARRAY_SIZE(reg_desc), "stream%u", i); + + for (j = 0 ; j < GAUDI_NUM_OF_QM_ERR_CAUSE ; j++) { + if (glbl_sts_val & BIT(j)) { + dev_err_ratelimited(hdev->dev, + "%s %s. err cause: %s\n", + qm_name, reg_desc, + gaudi_qman_error_cause[j]); + glbl_sts_clr_val |= BIT(j); + } + } + + /* Write 1 clear errors */ + WREG32(glbl_sts_addr + 4 * i, glbl_sts_clr_val); + } + + arb_err_val = RREG32(arb_err_addr); + + if (!arb_err_val) + return; + + for (j = 0 ; j < GAUDI_NUM_OF_QM_ARB_ERR_CAUSE ; j++) { + if (arb_err_val & BIT(j)) { + dev_err_ratelimited(hdev->dev, + "%s ARB_ERR. err cause: %s\n", + qm_name, + gaudi_qman_arb_error_cause[j]); + } + } +} + +static void gaudi_print_ecc_info(struct hl_device *hdev, u16 event_type) +{ + u64 block_address; + u8 index; + int num_memories; + char desc[32]; + bool derr; + bool disable_clock_gating; + + switch (event_type) { + case GAUDI_EVENT_PCIE_CORE_SERR: + snprintf(desc, ARRAY_SIZE(desc), "%s", "PCIE_CORE"); + block_address = mmPCIE_CORE_BASE; + num_memories = 51; + derr = false; + disable_clock_gating = false; + break; + case GAUDI_EVENT_PCIE_CORE_DERR: + snprintf(desc, ARRAY_SIZE(desc), "%s", "PCIE_CORE"); + block_address = mmPCIE_CORE_BASE; + num_memories = 51; + derr = true; + disable_clock_gating = false; + break; + case GAUDI_EVENT_PCIE_IF_SERR: + snprintf(desc, ARRAY_SIZE(desc), "%s", "PCIE_WRAP"); + block_address = mmPCIE_WRAP_BASE; + num_memories = 11; + derr = false; + disable_clock_gating = false; + break; + case GAUDI_EVENT_PCIE_IF_DERR: + snprintf(desc, ARRAY_SIZE(desc), "%s", "PCIE_WRAP"); + block_address = mmPCIE_WRAP_BASE; + num_memories = 11; + derr = true; + disable_clock_gating = false; + break; + case GAUDI_EVENT_PCIE_PHY_SERR: + snprintf(desc, ARRAY_SIZE(desc), "%s", "PCIE_PHY"); + block_address = mmPCIE_PHY_BASE; + num_memories = 4; + derr = false; + disable_clock_gating = false; + break; + case GAUDI_EVENT_PCIE_PHY_DERR: + snprintf(desc, ARRAY_SIZE(desc), "%s", "PCIE_PHY"); + block_address = mmPCIE_PHY_BASE; + num_memories = 4; + derr = true; + disable_clock_gating = false; + break; + case GAUDI_EVENT_TPC0_SERR ... GAUDI_EVENT_TPC7_SERR: + index = event_type - GAUDI_EVENT_TPC0_SERR; + block_address = mmTPC0_CFG_BASE + index * TPC_CFG_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "%s%d", "TPC", index); + num_memories = 90; + derr = false; + disable_clock_gating = true; + break; + case GAUDI_EVENT_TPC0_DERR ... GAUDI_EVENT_TPC7_DERR: + index = event_type - GAUDI_EVENT_TPC0_DERR; + block_address = + mmTPC0_CFG_BASE + index * TPC_CFG_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "%s%d", "TPC", index); + num_memories = 90; + derr = true; + disable_clock_gating = true; + break; + case GAUDI_EVENT_MME0_ACC_SERR: + case GAUDI_EVENT_MME1_ACC_SERR: + case GAUDI_EVENT_MME2_ACC_SERR: + case GAUDI_EVENT_MME3_ACC_SERR: + index = (event_type - GAUDI_EVENT_MME0_ACC_SERR) / 4; + block_address = mmMME0_ACC_BASE + index * MME_ACC_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "MME%d_ACC", index); + num_memories = 128; + derr = false; + disable_clock_gating = true; + break; + case GAUDI_EVENT_MME0_ACC_DERR: + case GAUDI_EVENT_MME1_ACC_DERR: + case GAUDI_EVENT_MME2_ACC_DERR: + case GAUDI_EVENT_MME3_ACC_DERR: + index = (event_type - GAUDI_EVENT_MME0_ACC_DERR) / 4; + block_address = mmMME0_ACC_BASE + index * MME_ACC_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "MME%d_ACC", index); + num_memories = 128; + derr = true; + disable_clock_gating = true; + break; + case GAUDI_EVENT_MME0_SBAB_SERR: + case GAUDI_EVENT_MME1_SBAB_SERR: + case GAUDI_EVENT_MME2_SBAB_SERR: + case GAUDI_EVENT_MME3_SBAB_SERR: + index = (event_type - GAUDI_EVENT_MME0_SBAB_SERR) / 4; + block_address = mmMME0_SBAB_BASE + index * MME_ACC_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "MME%d_SBAB", index); + num_memories = 33; + derr = false; + disable_clock_gating = true; + break; + case GAUDI_EVENT_MME0_SBAB_DERR: + case GAUDI_EVENT_MME1_SBAB_DERR: + case GAUDI_EVENT_MME2_SBAB_DERR: + case GAUDI_EVENT_MME3_SBAB_DERR: + index = (event_type - GAUDI_EVENT_MME0_SBAB_DERR) / 4; + block_address = mmMME0_SBAB_BASE + index * MME_ACC_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "MME%d_SBAB", index); + num_memories = 33; + derr = true; + disable_clock_gating = true; + break; + case GAUDI_EVENT_DMA0_SERR_ECC ... GAUDI_EVENT_DMA7_SERR_ECC: + index = event_type - GAUDI_EVENT_DMA0_SERR_ECC; + block_address = mmDMA0_CORE_BASE + index * DMA_CORE_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "DMA%d_CORE", index); + num_memories = 16; + derr = false; + disable_clock_gating = false; + break; + case GAUDI_EVENT_DMA0_DERR_ECC ... GAUDI_EVENT_DMA7_DERR_ECC: + index = event_type - GAUDI_EVENT_DMA0_DERR_ECC; + block_address = mmDMA0_CORE_BASE + index * DMA_CORE_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "DMA%d_CORE", index); + num_memories = 16; + derr = true; + disable_clock_gating = false; + break; + case GAUDI_EVENT_CPU_IF_ECC_SERR: + block_address = mmCPU_IF_BASE; + snprintf(desc, ARRAY_SIZE(desc), "%s", "CPU"); + num_memories = 4; + derr = false; + disable_clock_gating = false; + break; + case GAUDI_EVENT_CPU_IF_ECC_DERR: + block_address = mmCPU_IF_BASE; + snprintf(desc, ARRAY_SIZE(desc), "%s", "CPU"); + num_memories = 4; + derr = true; + disable_clock_gating = false; + break; + case GAUDI_EVENT_PSOC_MEM_SERR: + block_address = mmPSOC_GLOBAL_CONF_BASE; + snprintf(desc, ARRAY_SIZE(desc), "%s", "CPU"); + num_memories = 4; + derr = false; + disable_clock_gating = false; + break; + case GAUDI_EVENT_PSOC_MEM_DERR: + block_address = mmPSOC_GLOBAL_CONF_BASE; + snprintf(desc, ARRAY_SIZE(desc), "%s", "CPU"); + num_memories = 4; + derr = true; + disable_clock_gating = false; + break; + case GAUDI_EVENT_PSOC_CORESIGHT_SERR: + block_address = mmPSOC_CS_TRACE_BASE; + snprintf(desc, ARRAY_SIZE(desc), "%s", "CPU"); + num_memories = 2; + derr = false; + disable_clock_gating = false; + break; + case GAUDI_EVENT_PSOC_CORESIGHT_DERR: + block_address = mmPSOC_CS_TRACE_BASE; + snprintf(desc, ARRAY_SIZE(desc), "%s", "CPU"); + num_memories = 2; + derr = true; + disable_clock_gating = false; + break; + case GAUDI_EVENT_SRAM0_SERR ... GAUDI_EVENT_SRAM28_SERR: + index = event_type - GAUDI_EVENT_SRAM0_SERR; + block_address = + mmSRAM_Y0_X0_BANK_BASE + index * SRAM_BANK_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "SRAM%d", index); + num_memories = 2; + derr = false; + disable_clock_gating = false; + break; + case GAUDI_EVENT_SRAM0_DERR ... GAUDI_EVENT_SRAM28_DERR: + index = event_type - GAUDI_EVENT_SRAM0_DERR; + block_address = + mmSRAM_Y0_X0_BANK_BASE + index * SRAM_BANK_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "SRAM%d", index); + num_memories = 2; + derr = true; + disable_clock_gating = false; + break; + case GAUDI_EVENT_DMA_IF0_SERR ... GAUDI_EVENT_DMA_IF3_SERR: + index = event_type - GAUDI_EVENT_DMA_IF0_SERR; + block_address = mmDMA_IF_W_S_BASE + + index * (mmDMA_IF_E_S_BASE - mmDMA_IF_W_S_BASE); + snprintf(desc, ARRAY_SIZE(desc), "DMA_IF%d", index); + num_memories = 60; + derr = false; + disable_clock_gating = false; + break; + case GAUDI_EVENT_DMA_IF0_DERR ... GAUDI_EVENT_DMA_IF3_DERR: + index = event_type - GAUDI_EVENT_DMA_IF0_DERR; + block_address = mmDMA_IF_W_S_BASE + + index * (mmDMA_IF_E_S_BASE - mmDMA_IF_W_S_BASE); + snprintf(desc, ARRAY_SIZE(desc), "DMA_IF%d", index); + derr = true; + num_memories = 60; + disable_clock_gating = false; + break; + case GAUDI_EVENT_HBM_0_SERR ... GAUDI_EVENT_HBM_3_SERR: + index = event_type - GAUDI_EVENT_HBM_0_SERR; + /* HBM Registers are at different offsets */ + block_address = mmHBM0_BASE + 0x8000 + + index * (mmHBM1_BASE - mmHBM0_BASE); + snprintf(desc, ARRAY_SIZE(desc), "HBM%d", index); + derr = false; + num_memories = 64; + disable_clock_gating = false; + break; + case GAUDI_EVENT_HBM_0_DERR ... GAUDI_EVENT_HBM_3_DERR: + index = event_type - GAUDI_EVENT_HBM_0_SERR; + /* HBM Registers are at different offsets */ + block_address = mmHBM0_BASE + 0x8000 + + index * (mmHBM1_BASE - mmHBM0_BASE); + snprintf(desc, ARRAY_SIZE(desc), "HBM%d", index); + derr = true; + num_memories = 64; + disable_clock_gating = false; + break; + default: + return; + } + + gaudi_print_ecc_info_generic(hdev, desc, block_address, num_memories, + derr, disable_clock_gating); +} + +static void gaudi_handle_qman_err(struct hl_device *hdev, u16 event_type) +{ + u64 glbl_sts_addr, arb_err_addr; + u8 index; + char desc[32]; + + switch (event_type) { + case GAUDI_EVENT_TPC0_QM ... GAUDI_EVENT_TPC7_QM: + index = event_type - GAUDI_EVENT_TPC0_QM; + glbl_sts_addr = + mmTPC0_QM_GLBL_STS1_0 + index * TPC_QMAN_OFFSET; + arb_err_addr = + mmTPC0_QM_ARB_ERR_CAUSE + index * TPC_QMAN_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "%s%d", "TPC_QM", index); + break; + case GAUDI_EVENT_MME0_QM ... GAUDI_EVENT_MME2_QM: + index = event_type - GAUDI_EVENT_MME0_QM; + glbl_sts_addr = + mmMME0_QM_GLBL_STS1_0 + index * MME_QMAN_OFFSET; + arb_err_addr = + mmMME0_QM_ARB_ERR_CAUSE + index * MME_QMAN_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "%s%d", "MME_QM", index); + break; + case GAUDI_EVENT_DMA0_QM ... GAUDI_EVENT_DMA7_QM: + index = event_type - GAUDI_EVENT_DMA0_QM; + glbl_sts_addr = + mmDMA0_QM_GLBL_STS1_0 + index * DMA_QMAN_OFFSET; + arb_err_addr = + mmDMA0_QM_ARB_ERR_CAUSE + index * DMA_QMAN_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "%s%d", "DMA_QM", index); + break; + default: + return; + } + + gaudi_handle_qman_err_generic(hdev, desc, glbl_sts_addr, arb_err_addr); +} + +static void gaudi_print_irq_info(struct hl_device *hdev, u16 event_type, + bool razwi) +{ + char desc[64] = ""; + + gaudi_get_event_desc(event_type, desc, sizeof(desc)); + dev_err_ratelimited(hdev->dev, "Received H/W interrupt %d [\"%s\"]\n", + event_type, desc); + + gaudi_print_ecc_info(hdev, event_type); + + if (razwi) { + gaudi_print_razwi_info(hdev); + gaudi_print_mmu_error_info(hdev); + } +} + +static int gaudi_soft_reset_late_init(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + /* Unmask all IRQs since some could have been received + * during the soft reset + */ + return hl_fw_unmask_irq_arr(hdev, gaudi->events, sizeof(gaudi->events)); +} + +static int gaudi_hbm_read_interrupts(struct hl_device *hdev, int device) +{ + int ch, err = 0; + u32 base, val, val2; + + base = GAUDI_HBM_CFG_BASE + device * GAUDI_HBM_CFG_OFFSET; + for (ch = 0 ; ch < GAUDI_HBM_CHANNELS ; ch++) { + val = RREG32_MASK(base + ch * 0x1000 + 0x06C, 0x0000FFFF); + val = (val & 0xFF) | ((val >> 8) & 0xFF); + if (val) { + err = 1; + dev_err(hdev->dev, + "HBM%d pc%d interrupts info: WR_PAR=%d, RD_PAR=%d, CA_PAR=%d, SERR=%d, DERR=%d\n", + device, ch * 2, val & 0x1, (val >> 1) & 0x1, + (val >> 2) & 0x1, (val >> 3) & 0x1, + (val >> 4) & 0x1); + + val2 = RREG32(base + ch * 0x1000 + 0x060); + dev_err(hdev->dev, + "HBM%d pc%d ECC info: 1ST_ERR_ADDR=0x%x, 1ST_ERR_TYPE=%d, SEC_CONT_CNT=%d, SEC_CNT=%d, DED_CNT=%d\n", + device, ch * 2, + RREG32(base + ch * 0x1000 + 0x064), + (val2 & 0x200) >> 9, (val2 & 0xFC00) >> 10, + (val2 & 0xFF0000) >> 16, + (val2 & 0xFF000000) >> 24); + } + + val = RREG32_MASK(base + ch * 0x1000 + 0x07C, 0x0000FFFF); + val = (val & 0xFF) | ((val >> 8) & 0xFF); + if (val) { + err = 1; + dev_err(hdev->dev, + "HBM%d pc%d interrupts info: WR_PAR=%d, RD_PAR=%d, CA_PAR=%d, SERR=%d, DERR=%d\n", + device, ch * 2 + 1, val & 0x1, (val >> 1) & 0x1, + (val >> 2) & 0x1, (val >> 3) & 0x1, + (val >> 4) & 0x1); + + val2 = RREG32(base + ch * 0x1000 + 0x070); + dev_err(hdev->dev, + "HBM%d pc%d ECC info: 1ST_ERR_ADDR=0x%x, 1ST_ERR_TYPE=%d, SEC_CONT_CNT=%d, SEC_CNT=%d, DED_CNT=%d\n", + device, ch * 2 + 1, + RREG32(base + ch * 0x1000 + 0x074), + (val2 & 0x200) >> 9, (val2 & 0xFC00) >> 10, + (val2 & 0xFF0000) >> 16, + (val2 & 0xFF000000) >> 24); + } + + /* Clear interrupts */ + RMWREG32(base + (ch * 0x1000) + 0x060, 0x1C8, 0x1FF); + RMWREG32(base + (ch * 0x1000) + 0x070, 0x1C8, 0x1FF); + WREG32(base + (ch * 0x1000) + 0x06C, 0x1F1F); + WREG32(base + (ch * 0x1000) + 0x07C, 0x1F1F); + RMWREG32(base + (ch * 0x1000) + 0x060, 0x0, 0xF); + RMWREG32(base + (ch * 0x1000) + 0x070, 0x0, 0xF); + } + + val = RREG32(base + 0x8F30); + val2 = RREG32(base + 0x8F34); + if (val | val2) { + err = 1; + dev_err(hdev->dev, + "HBM %d MC SRAM SERR info: Reg 0x8F30=0x%x, Reg 0x8F34=0x%x\n", + device, val, val2); + } + val = RREG32(base + 0x8F40); + val2 = RREG32(base + 0x8F44); + if (val | val2) { + err = 1; + dev_err(hdev->dev, + "HBM %d MC SRAM DERR info: Reg 0x8F40=0x%x, Reg 0x8F44=0x%x\n", + device, val, val2); + } + + return err; +} + +static int gaudi_hbm_event_to_dev(u16 hbm_event_type) +{ + switch (hbm_event_type) { + case GAUDI_EVENT_HBM0_SPI_0: + case GAUDI_EVENT_HBM0_SPI_1: + return 0; + case GAUDI_EVENT_HBM1_SPI_0: + case GAUDI_EVENT_HBM1_SPI_1: + return 1; + case GAUDI_EVENT_HBM2_SPI_0: + case GAUDI_EVENT_HBM2_SPI_1: + return 2; + case GAUDI_EVENT_HBM3_SPI_0: + case GAUDI_EVENT_HBM3_SPI_1: + return 3; + default: + break; + } + + /* Should never happen */ + return 0; +} + +static bool gaudi_tpc_read_interrupts(struct hl_device *hdev, u8 tpc_id, + char *interrupt_name) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + u32 tpc_offset = tpc_id * TPC_CFG_OFFSET, tpc_interrupts_cause, i; + bool soft_reset_required = false; + + /* Accessing the TPC_INTR_CAUSE registers requires disabling the clock + * gating, and thus cannot be done in ArmCP and should be done instead + * by the driver. + */ + + mutex_lock(&gaudi->clk_gate_mutex); + + hdev->asic_funcs->disable_clock_gating(hdev); + + tpc_interrupts_cause = RREG32(mmTPC0_CFG_TPC_INTR_CAUSE + tpc_offset) & + TPC0_CFG_TPC_INTR_CAUSE_CAUSE_MASK; + + for (i = 0 ; i < GAUDI_NUM_OF_TPC_INTR_CAUSE ; i++) + if (tpc_interrupts_cause & BIT(i)) { + dev_err_ratelimited(hdev->dev, + "TPC%d_%s interrupt cause: %s\n", + tpc_id, interrupt_name, + gaudi_tpc_interrupts_cause[i]); + /* If this is QM error, we need to soft-reset */ + if (i == 15) + soft_reset_required = true; + } + + /* Clear interrupts */ + WREG32(mmTPC0_CFG_TPC_INTR_CAUSE + tpc_offset, 0); + + hdev->asic_funcs->enable_clock_gating(hdev); + + mutex_unlock(&gaudi->clk_gate_mutex); + + return soft_reset_required; +} + +static int tpc_dec_event_to_tpc_id(u16 tpc_dec_event_type) +{ + return (tpc_dec_event_type - GAUDI_EVENT_TPC0_DEC) >> 1; +} + +static int tpc_krn_event_to_tpc_id(u16 tpc_dec_event_type) +{ + return (tpc_dec_event_type - GAUDI_EVENT_TPC0_KRN_ERR) / 6; +} + +static void gaudi_print_clk_change_info(struct hl_device *hdev, + u16 event_type) +{ + switch (event_type) { + case GAUDI_EVENT_FIX_POWER_ENV_S: + dev_info_ratelimited(hdev->dev, + "Clock throttling due to power consumption\n"); + break; + + case GAUDI_EVENT_FIX_POWER_ENV_E: + dev_info_ratelimited(hdev->dev, + "Power envelop is safe, back to optimal clock\n"); + break; + + case GAUDI_EVENT_FIX_THERMAL_ENV_S: + dev_info_ratelimited(hdev->dev, + "Clock throttling due to overheating\n"); + break; + + case GAUDI_EVENT_FIX_THERMAL_ENV_E: + dev_info_ratelimited(hdev->dev, + "Thermal envelop is safe, back to optimal clock\n"); + break; + + default: + dev_err(hdev->dev, "Received invalid clock change event %d\n", + event_type); + break; + } +} + +static void gaudi_handle_eqe(struct hl_device *hdev, + struct hl_eq_entry *eq_entry) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + u32 ctl = le32_to_cpu(eq_entry->hdr.ctl); + u16 event_type = ((ctl & EQ_CTL_EVENT_TYPE_MASK) + >> EQ_CTL_EVENT_TYPE_SHIFT); + u8 cause; + bool reset_required; + + gaudi->events_stat[event_type]++; + gaudi->events_stat_aggregate[event_type]++; + + switch (event_type) { + case GAUDI_EVENT_PCIE_CORE_DERR: + case GAUDI_EVENT_PCIE_IF_DERR: + case GAUDI_EVENT_PCIE_PHY_DERR: + case GAUDI_EVENT_TPC0_DERR ... GAUDI_EVENT_TPC7_DERR: + case GAUDI_EVENT_MME0_ACC_DERR: + case GAUDI_EVENT_MME0_SBAB_DERR: + case GAUDI_EVENT_MME1_ACC_DERR: + case GAUDI_EVENT_MME1_SBAB_DERR: + case GAUDI_EVENT_MME2_ACC_DERR: + case GAUDI_EVENT_MME2_SBAB_DERR: + case GAUDI_EVENT_MME3_ACC_DERR: + case GAUDI_EVENT_MME3_SBAB_DERR: + case GAUDI_EVENT_DMA0_DERR_ECC ... GAUDI_EVENT_DMA7_DERR_ECC: + fallthrough; + case GAUDI_EVENT_CPU_IF_ECC_DERR: + case GAUDI_EVENT_PSOC_MEM_DERR: + case GAUDI_EVENT_PSOC_CORESIGHT_DERR: + case GAUDI_EVENT_SRAM0_DERR ... GAUDI_EVENT_SRAM28_DERR: + case GAUDI_EVENT_DMA_IF0_DERR ... GAUDI_EVENT_DMA_IF3_DERR: + fallthrough; + case GAUDI_EVENT_GIC500: + case GAUDI_EVENT_HBM_0_DERR ... GAUDI_EVENT_HBM_3_DERR: + case GAUDI_EVENT_MMU_DERR: + case GAUDI_EVENT_AXI_ECC: + case GAUDI_EVENT_L2_RAM_ECC: + case GAUDI_EVENT_PLL0 ... GAUDI_EVENT_PLL17: + gaudi_print_irq_info(hdev, event_type, false); + if (hdev->hard_reset_on_fw_events) + hl_device_reset(hdev, true, false); + break; + + case GAUDI_EVENT_HBM0_SPI_0: + case GAUDI_EVENT_HBM1_SPI_0: + case GAUDI_EVENT_HBM2_SPI_0: + case GAUDI_EVENT_HBM3_SPI_0: + gaudi_print_irq_info(hdev, event_type, false); + gaudi_hbm_read_interrupts(hdev, + gaudi_hbm_event_to_dev(event_type)); + if (hdev->hard_reset_on_fw_events) + hl_device_reset(hdev, true, false); + break; + + case GAUDI_EVENT_HBM0_SPI_1: + case GAUDI_EVENT_HBM1_SPI_1: + case GAUDI_EVENT_HBM2_SPI_1: + case GAUDI_EVENT_HBM3_SPI_1: + gaudi_print_irq_info(hdev, event_type, false); + gaudi_hbm_read_interrupts(hdev, + gaudi_hbm_event_to_dev(event_type)); + break; + + case GAUDI_EVENT_TPC0_DEC: + case GAUDI_EVENT_TPC1_DEC: + case GAUDI_EVENT_TPC2_DEC: + case GAUDI_EVENT_TPC3_DEC: + case GAUDI_EVENT_TPC4_DEC: + case GAUDI_EVENT_TPC5_DEC: + case GAUDI_EVENT_TPC6_DEC: + case GAUDI_EVENT_TPC7_DEC: + gaudi_print_irq_info(hdev, event_type, true); + reset_required = gaudi_tpc_read_interrupts(hdev, + tpc_dec_event_to_tpc_id(event_type), + "AXI_SLV_DEC_Error"); + if (reset_required) { + dev_err(hdev->dev, "hard reset required due to %s\n", + gaudi_irq_map_table[event_type].name); + + if (hdev->hard_reset_on_fw_events) + hl_device_reset(hdev, true, false); + } else { + hl_fw_unmask_irq(hdev, event_type); + } + break; + + case GAUDI_EVENT_TPC0_KRN_ERR: + case GAUDI_EVENT_TPC1_KRN_ERR: + case GAUDI_EVENT_TPC2_KRN_ERR: + case GAUDI_EVENT_TPC3_KRN_ERR: + case GAUDI_EVENT_TPC4_KRN_ERR: + case GAUDI_EVENT_TPC5_KRN_ERR: + case GAUDI_EVENT_TPC6_KRN_ERR: + case GAUDI_EVENT_TPC7_KRN_ERR: + gaudi_print_irq_info(hdev, event_type, true); + reset_required = gaudi_tpc_read_interrupts(hdev, + tpc_krn_event_to_tpc_id(event_type), + "KRN_ERR"); + if (reset_required) { + dev_err(hdev->dev, "hard reset required due to %s\n", + gaudi_irq_map_table[event_type].name); + + if (hdev->hard_reset_on_fw_events) + hl_device_reset(hdev, true, false); + } else { + hl_fw_unmask_irq(hdev, event_type); + } + break; + + case GAUDI_EVENT_PCIE_CORE_SERR: + case GAUDI_EVENT_PCIE_IF_SERR: + case GAUDI_EVENT_PCIE_PHY_SERR: + case GAUDI_EVENT_TPC0_SERR ... GAUDI_EVENT_TPC7_SERR: + case GAUDI_EVENT_MME0_ACC_SERR: + case GAUDI_EVENT_MME0_SBAB_SERR: + case GAUDI_EVENT_MME1_ACC_SERR: + case GAUDI_EVENT_MME1_SBAB_SERR: + case GAUDI_EVENT_MME2_ACC_SERR: + case GAUDI_EVENT_MME2_SBAB_SERR: + case GAUDI_EVENT_MME3_ACC_SERR: + case GAUDI_EVENT_MME3_SBAB_SERR: + case GAUDI_EVENT_DMA0_SERR_ECC ... GAUDI_EVENT_DMA7_SERR_ECC: + case GAUDI_EVENT_CPU_IF_ECC_SERR: + case GAUDI_EVENT_PSOC_MEM_SERR: + case GAUDI_EVENT_PSOC_CORESIGHT_SERR: + case GAUDI_EVENT_SRAM0_SERR ... GAUDI_EVENT_SRAM28_SERR: + case GAUDI_EVENT_DMA_IF0_SERR ... GAUDI_EVENT_DMA_IF3_SERR: + case GAUDI_EVENT_HBM_0_SERR ... GAUDI_EVENT_HBM_3_SERR: + fallthrough; + case GAUDI_EVENT_MMU_SERR: + case GAUDI_EVENT_PCIE_DEC: + case GAUDI_EVENT_MME0_WBC_RSP: + case GAUDI_EVENT_MME0_SBAB0_RSP: + case GAUDI_EVENT_MME1_WBC_RSP: + case GAUDI_EVENT_MME1_SBAB0_RSP: + case GAUDI_EVENT_MME2_WBC_RSP: + case GAUDI_EVENT_MME2_SBAB0_RSP: + case GAUDI_EVENT_MME3_WBC_RSP: + case GAUDI_EVENT_MME3_SBAB0_RSP: + case GAUDI_EVENT_CPU_AXI_SPLITTER: + case GAUDI_EVENT_PSOC_AXI_DEC: + case GAUDI_EVENT_PSOC_PRSTN_FALL: + case GAUDI_EVENT_MMU_PAGE_FAULT: + case GAUDI_EVENT_MMU_WR_PERM: + case GAUDI_EVENT_RAZWI_OR_ADC: + case GAUDI_EVENT_TPC0_QM ... GAUDI_EVENT_TPC7_QM: + case GAUDI_EVENT_MME0_QM ... GAUDI_EVENT_MME2_QM: + case GAUDI_EVENT_DMA0_QM ... GAUDI_EVENT_DMA7_QM: + fallthrough; + case GAUDI_EVENT_DMA0_CORE ... GAUDI_EVENT_DMA7_CORE: + gaudi_print_irq_info(hdev, event_type, true); + gaudi_handle_qman_err(hdev, event_type); + hl_fw_unmask_irq(hdev, event_type); + break; + + case GAUDI_EVENT_RAZWI_OR_ADC_SW: + gaudi_print_irq_info(hdev, event_type, true); + if (hdev->hard_reset_on_fw_events) + hl_device_reset(hdev, true, false); + break; + + case GAUDI_EVENT_TPC0_BMON_SPMU: + case GAUDI_EVENT_TPC1_BMON_SPMU: + case GAUDI_EVENT_TPC2_BMON_SPMU: + case GAUDI_EVENT_TPC3_BMON_SPMU: + case GAUDI_EVENT_TPC4_BMON_SPMU: + case GAUDI_EVENT_TPC5_BMON_SPMU: + case GAUDI_EVENT_TPC6_BMON_SPMU: + case GAUDI_EVENT_TPC7_BMON_SPMU: + case GAUDI_EVENT_DMA_BM_CH0 ... GAUDI_EVENT_DMA_BM_CH7: + gaudi_print_irq_info(hdev, event_type, false); + hl_fw_unmask_irq(hdev, event_type); + break; + + case GAUDI_EVENT_FIX_POWER_ENV_S ... GAUDI_EVENT_FIX_THERMAL_ENV_E: + gaudi_print_clk_change_info(hdev, event_type); + hl_fw_unmask_irq(hdev, event_type); + break; + + case GAUDI_EVENT_PSOC_GPIO_U16_0: + cause = le64_to_cpu(eq_entry->data[0]) & 0xFF; + dev_err(hdev->dev, + "Received high temp H/W interrupt %d (cause %d)\n", + event_type, cause); + break; + + default: + dev_err(hdev->dev, "Received invalid H/W interrupt %d\n", + event_type); + break; + } +} + +static void *gaudi_get_events_stat(struct hl_device *hdev, bool aggregate, + u32 *size) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (aggregate) { + *size = (u32) sizeof(gaudi->events_stat_aggregate); + return gaudi->events_stat_aggregate; + } + + *size = (u32) sizeof(gaudi->events_stat); + return gaudi->events_stat; +} + +static int gaudi_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard, + u32 flags) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + u32 status, timeout_usec; + int rc; + + if (!(gaudi->hw_cap_initialized & HW_CAP_MMU) || + hdev->hard_reset_pending) + return 0; + + if (hdev->pldm) + timeout_usec = GAUDI_PLDM_MMU_TIMEOUT_USEC; + else + timeout_usec = MMU_CONFIG_TIMEOUT_USEC; + + mutex_lock(&hdev->mmu_cache_lock); + + /* L0 & L1 invalidation */ + WREG32(mmSTLB_INV_PS, 2); + + rc = hl_poll_timeout( + hdev, + mmSTLB_INV_PS, + status, + !status, + 1000, + timeout_usec); + + WREG32(mmSTLB_INV_SET, 0); + + mutex_unlock(&hdev->mmu_cache_lock); + + if (rc) { + dev_err_ratelimited(hdev->dev, + "MMU cache invalidation timeout\n"); + hl_device_reset(hdev, true, false); + } + + return rc; +} + +static int gaudi_mmu_invalidate_cache_range(struct hl_device *hdev, + bool is_hard, u32 asid, u64 va, u64 size) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + u32 status, timeout_usec; + u32 inv_data; + u32 pi; + int rc; + + if (!(gaudi->hw_cap_initialized & HW_CAP_MMU) || + hdev->hard_reset_pending) + return 0; + + mutex_lock(&hdev->mmu_cache_lock); + + if (hdev->pldm) + timeout_usec = GAUDI_PLDM_MMU_TIMEOUT_USEC; + else + timeout_usec = MMU_CONFIG_TIMEOUT_USEC; + + /* + * TODO: currently invalidate entire L0 & L1 as in regular hard + * invalidation. Need to apply invalidation of specific cache + * lines with mask of ASID & VA & size. + * Note that L1 with be flushed entirely in any case. + */ + + /* L0 & L1 invalidation */ + inv_data = RREG32(mmSTLB_CACHE_INV); + /* PI is 8 bit */ + pi = ((inv_data & STLB_CACHE_INV_PRODUCER_INDEX_MASK) + 1) & 0xFF; + WREG32(mmSTLB_CACHE_INV, + (inv_data & STLB_CACHE_INV_INDEX_MASK_MASK) | pi); + + rc = hl_poll_timeout( + hdev, + mmSTLB_INV_CONSUMER_INDEX, + status, + status == pi, + 1000, + timeout_usec); + + mutex_unlock(&hdev->mmu_cache_lock); + + if (rc) { + dev_err_ratelimited(hdev->dev, + "MMU cache invalidation timeout\n"); + hl_device_reset(hdev, true, false); + } + + return rc; +} + +static int gaudi_mmu_update_asid_hop0_addr(struct hl_device *hdev, + u32 asid, u64 phys_addr) +{ + u32 status, timeout_usec; + int rc; + + if (hdev->pldm) + timeout_usec = GAUDI_PLDM_MMU_TIMEOUT_USEC; + else + timeout_usec = MMU_CONFIG_TIMEOUT_USEC; + + WREG32(MMU_ASID, asid); + WREG32(MMU_HOP0_PA43_12, phys_addr >> MMU_HOP0_PA43_12_SHIFT); + WREG32(MMU_HOP0_PA49_44, phys_addr >> MMU_HOP0_PA49_44_SHIFT); + WREG32(MMU_BUSY, 0x80000000); + + rc = hl_poll_timeout( + hdev, + MMU_BUSY, + status, + !(status & 0x80000000), + 1000, + timeout_usec); + + if (rc) { + dev_err(hdev->dev, + "Timeout during MMU hop0 config of asid %d\n", asid); + return rc; + } + + return 0; +} + +static int gaudi_send_heartbeat(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_CPU_Q)) + return 0; + + return hl_fw_send_heartbeat(hdev); +} + +static int gaudi_armcp_info_get(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + struct asic_fixed_properties *prop = &hdev->asic_prop; + int rc; + + if (!(gaudi->hw_cap_initialized & HW_CAP_CPU_Q)) + return 0; + + rc = hl_fw_armcp_info_get(hdev); + if (rc) + return rc; + + if (!strlen(prop->armcp_info.card_name)) + strncpy(prop->armcp_info.card_name, GAUDI_DEFAULT_CARD_NAME, + CARD_NAME_MAX_LEN); + + return 0; +} + +static bool gaudi_is_device_idle(struct hl_device *hdev, u32 *mask, + struct seq_file *s) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + const char *fmt = "%-5d%-9s%#-14x%#-12x%#x\n"; + const char *mme_slave_fmt = "%-5d%-9s%-14s%-12s%#x\n"; + u32 qm_glbl_sts0, qm_cgm_sts, dma_core_sts0, tpc_cfg_sts, mme_arch_sts; + bool is_idle = true, is_eng_idle, is_slave; + u64 offset; + int i, dma_id; + + mutex_lock(&gaudi->clk_gate_mutex); + + hdev->asic_funcs->disable_clock_gating(hdev); + + if (s) + seq_puts(s, + "\nDMA is_idle QM_GLBL_STS0 QM_CGM_STS DMA_CORE_STS0\n" + "--- ------- ------------ ---------- -------------\n"); + + for (i = 0 ; i < DMA_NUMBER_OF_CHNLS ; i++) { + dma_id = gaudi_dma_assignment[i]; + offset = dma_id * DMA_QMAN_OFFSET; + + qm_glbl_sts0 = RREG32(mmDMA0_QM_GLBL_STS0 + offset); + qm_cgm_sts = RREG32(mmDMA0_QM_CGM_STS + offset); + dma_core_sts0 = RREG32(mmDMA0_CORE_STS0 + offset); + is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_cgm_sts) && + IS_DMA_IDLE(dma_core_sts0); + is_idle &= is_eng_idle; + + if (mask) + *mask |= !is_eng_idle << + (GAUDI_ENGINE_ID_DMA_0 + dma_id); + if (s) + seq_printf(s, fmt, dma_id, + is_eng_idle ? "Y" : "N", qm_glbl_sts0, + qm_cgm_sts, dma_core_sts0); + } + + if (s) + seq_puts(s, + "\nTPC is_idle QM_GLBL_STS0 QM_CGM_STS CFG_STATUS\n" + "--- ------- ------------ ---------- ----------\n"); + + for (i = 0 ; i < TPC_NUMBER_OF_ENGINES ; i++) { + offset = i * TPC_QMAN_OFFSET; + qm_glbl_sts0 = RREG32(mmTPC0_QM_GLBL_STS0 + offset); + qm_cgm_sts = RREG32(mmTPC0_QM_CGM_STS + offset); + tpc_cfg_sts = RREG32(mmTPC0_CFG_STATUS + offset); + is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_cgm_sts) && + IS_TPC_IDLE(tpc_cfg_sts); + is_idle &= is_eng_idle; + + if (mask) + *mask |= !is_eng_idle << (GAUDI_ENGINE_ID_TPC_0 + i); + if (s) + seq_printf(s, fmt, i, + is_eng_idle ? "Y" : "N", + qm_glbl_sts0, qm_cgm_sts, tpc_cfg_sts); + } + + if (s) + seq_puts(s, + "\nMME is_idle QM_GLBL_STS0 QM_CGM_STS ARCH_STATUS\n" + "--- ------- ------------ ---------- -----------\n"); + + for (i = 0 ; i < MME_NUMBER_OF_ENGINES ; i++) { + offset = i * MME_QMAN_OFFSET; + mme_arch_sts = RREG32(mmMME0_CTRL_ARCH_STATUS + offset); + is_eng_idle = IS_MME_IDLE(mme_arch_sts); + + /* MME 1 & 3 are slaves, no need to check their QMANs */ + is_slave = i % 2; + if (!is_slave) { + qm_glbl_sts0 = RREG32(mmMME0_QM_GLBL_STS0 + offset); + qm_cgm_sts = RREG32(mmMME0_QM_CGM_STS + offset); + is_eng_idle &= IS_QM_IDLE(qm_glbl_sts0, qm_cgm_sts); + } + + is_idle &= is_eng_idle; + + if (mask) + *mask |= !is_eng_idle << (GAUDI_ENGINE_ID_MME_0 + i); + if (s) { + if (!is_slave) + seq_printf(s, fmt, i, + is_eng_idle ? "Y" : "N", + qm_glbl_sts0, qm_cgm_sts, mme_arch_sts); + else + seq_printf(s, mme_slave_fmt, i, + is_eng_idle ? "Y" : "N", "-", + "-", mme_arch_sts); + } + } + + if (s) + seq_puts(s, "\n"); + + hdev->asic_funcs->enable_clock_gating(hdev); + + mutex_unlock(&gaudi->clk_gate_mutex); + + return is_idle; +} + +static void gaudi_hw_queues_lock(struct hl_device *hdev) + __acquires(&gaudi->hw_queues_lock) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + spin_lock(&gaudi->hw_queues_lock); +} + +static void gaudi_hw_queues_unlock(struct hl_device *hdev) + __releases(&gaudi->hw_queues_lock) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + spin_unlock(&gaudi->hw_queues_lock); +} + +static u32 gaudi_get_pci_id(struct hl_device *hdev) +{ + return hdev->pdev->device; +} + +static int gaudi_get_eeprom_data(struct hl_device *hdev, void *data, + size_t max_size) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_CPU_Q)) + return 0; + + return hl_fw_get_eeprom_data(hdev, data, max_size); +} + +/* + * this function should be used only during initialization and/or after reset, + * when there are no active users. + */ +static int gaudi_run_tpc_kernel(struct hl_device *hdev, u64 tpc_kernel, + u32 tpc_id) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + u64 kernel_timeout; + u32 status, offset; + int rc; + + offset = tpc_id * (mmTPC1_CFG_STATUS - mmTPC0_CFG_STATUS); + + if (hdev->pldm) + kernel_timeout = GAUDI_PLDM_TPC_KERNEL_WAIT_USEC; + else + kernel_timeout = HL_DEVICE_TIMEOUT_USEC; + + mutex_lock(&gaudi->clk_gate_mutex); + + hdev->asic_funcs->disable_clock_gating(hdev); + + WREG32(mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW + offset, + lower_32_bits(tpc_kernel)); + WREG32(mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH + offset, + upper_32_bits(tpc_kernel)); + + WREG32(mmTPC0_CFG_ICACHE_BASE_ADDERESS_LOW + offset, + lower_32_bits(tpc_kernel)); + WREG32(mmTPC0_CFG_ICACHE_BASE_ADDERESS_HIGH + offset, + upper_32_bits(tpc_kernel)); + /* set a valid LUT pointer, content is of no significance */ + WREG32(mmTPC0_CFG_LUT_FUNC256_BASE_ADDR_LO + offset, + lower_32_bits(tpc_kernel)); + WREG32(mmTPC0_CFG_LUT_FUNC256_BASE_ADDR_HI + offset, + upper_32_bits(tpc_kernel)); + + WREG32(mmTPC0_CFG_QM_SYNC_OBJECT_ADDR + offset, + lower_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0)); + + WREG32(mmTPC0_CFG_TPC_CMD + offset, + (1 << TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_SHIFT | + 1 << TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_SHIFT)); + /* wait a bit for the engine to start executing */ + usleep_range(1000, 1500); + + /* wait until engine has finished executing */ + rc = hl_poll_timeout( + hdev, + mmTPC0_CFG_STATUS + offset, + status, + (status & TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK) == + TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK, + 1000, + kernel_timeout); + + if (rc) { + dev_err(hdev->dev, + "Timeout while waiting for TPC%d icache prefetch\n", + tpc_id); + hdev->asic_funcs->enable_clock_gating(hdev); + mutex_unlock(&gaudi->clk_gate_mutex); + return -EIO; + } + + WREG32(mmTPC0_CFG_TPC_EXECUTE + offset, + 1 << TPC0_CFG_TPC_EXECUTE_V_SHIFT); + + /* wait a bit for the engine to start executing */ + usleep_range(1000, 1500); + + /* wait until engine has finished executing */ + rc = hl_poll_timeout( + hdev, + mmTPC0_CFG_STATUS + offset, + status, + (status & TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK) == + TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK, + 1000, + kernel_timeout); + + rc = hl_poll_timeout( + hdev, + mmTPC0_CFG_WQ_INFLIGHT_CNTR + offset, + status, + (status == 0), + 1000, + kernel_timeout); + + hdev->asic_funcs->enable_clock_gating(hdev); + mutex_unlock(&gaudi->clk_gate_mutex); + + if (rc) { + dev_err(hdev->dev, + "Timeout while waiting for TPC%d kernel to execute\n", + tpc_id); + return -EIO; + } + + return 0; +} + +static enum hl_device_hw_state gaudi_get_hw_state(struct hl_device *hdev) +{ + return RREG32(mmHW_STATE); +} + +static u32 gaudi_get_queue_id_for_cq(struct hl_device *hdev, u32 cq_idx) +{ + return gaudi_cq_assignment[cq_idx]; +} + +static void gaudi_ext_queue_init(struct hl_device *hdev, u32 q_idx) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + struct hl_hw_queue *hw_queue = &hdev->kernel_queues[q_idx]; + struct hl_hw_sob *hw_sob; + int sob, ext_idx = gaudi->ext_queue_idx++; + + /* + * The external queues might not sit sequentially, hence use the + * real external queue index for the SOB/MON base id. + */ + hw_queue->base_sob_id = ext_idx * HL_RSVD_SOBS; + hw_queue->base_mon_id = ext_idx * HL_RSVD_MONS; + hw_queue->next_sob_val = 1; + hw_queue->curr_sob_offset = 0; + + for (sob = 0 ; sob < HL_RSVD_SOBS ; sob++) { + hw_sob = &hw_queue->hw_sob[sob]; + hw_sob->hdev = hdev; + hw_sob->sob_id = hw_queue->base_sob_id + sob; + hw_sob->q_idx = q_idx; + kref_init(&hw_sob->kref); + } +} + +static void gaudi_ext_queue_reset(struct hl_device *hdev, u32 q_idx) +{ + struct hl_hw_queue *hw_queue = &hdev->kernel_queues[q_idx]; + + /* + * In case we got here due to a stuck CS, the refcnt might be bigger + * than 1 and therefore we reset it. + */ + kref_init(&hw_queue->hw_sob[hw_queue->curr_sob_offset].kref); + hw_queue->curr_sob_offset = 0; + hw_queue->next_sob_val = 1; +} + +static u32 gaudi_get_signal_cb_size(struct hl_device *hdev) +{ + return sizeof(struct packet_msg_short) + + sizeof(struct packet_msg_prot) * 2; +} + +static u32 gaudi_get_wait_cb_size(struct hl_device *hdev) +{ + return sizeof(struct packet_msg_short) * 4 + + sizeof(struct packet_fence) + + sizeof(struct packet_msg_prot) * 2; +} + +static void gaudi_gen_signal_cb(struct hl_device *hdev, void *data, u16 sob_id) +{ + struct hl_cb *cb = (struct hl_cb *) data; + struct packet_msg_short *pkt; + u32 value, ctl; + + pkt = (struct packet_msg_short *) (uintptr_t) cb->kernel_address; + memset(pkt, 0, sizeof(*pkt)); + + value = 1 << GAUDI_PKT_SHORT_VAL_SOB_SYNC_VAL_SHIFT; /* inc by 1 */ + value |= 1 << GAUDI_PKT_SHORT_VAL_SOB_MOD_SHIFT; /* add mode */ + + ctl = (sob_id * 4) << GAUDI_PKT_SHORT_CTL_ADDR_SHIFT; /* SOB id */ + ctl |= 0 << GAUDI_PKT_SHORT_CTL_OP_SHIFT; /* write the value */ + ctl |= 3 << GAUDI_PKT_SHORT_CTL_BASE_SHIFT; /* W_S SOB base */ + ctl |= PACKET_MSG_SHORT << GAUDI_PKT_SHORT_CTL_OPCODE_SHIFT; + ctl |= 1 << GAUDI_PKT_SHORT_CTL_EB_SHIFT; + ctl |= 1 << GAUDI_PKT_SHORT_CTL_RB_SHIFT; + ctl |= 1 << GAUDI_PKT_SHORT_CTL_MB_SHIFT; + + pkt->value = cpu_to_le32(value); + pkt->ctl = cpu_to_le32(ctl); +} + +static u32 gaudi_add_mon_msg_short(struct packet_msg_short *pkt, u32 value, + u16 addr) +{ + u32 ctl, pkt_size = sizeof(*pkt); + + memset(pkt, 0, pkt_size); + + ctl = addr << GAUDI_PKT_SHORT_CTL_ADDR_SHIFT; + ctl |= 2 << GAUDI_PKT_SHORT_CTL_BASE_SHIFT; /* W_S MON base */ + ctl |= PACKET_MSG_SHORT << GAUDI_PKT_SHORT_CTL_OPCODE_SHIFT; + ctl |= 0 << GAUDI_PKT_SHORT_CTL_EB_SHIFT; + ctl |= 1 << GAUDI_PKT_SHORT_CTL_RB_SHIFT; + ctl |= 0 << GAUDI_PKT_SHORT_CTL_MB_SHIFT; /* only last pkt needs MB */ + + pkt->value = cpu_to_le32(value); + pkt->ctl = cpu_to_le32(ctl); + + return pkt_size; +} + +static u32 gaudi_add_arm_monitor_pkt(struct packet_msg_short *pkt, u16 sob_id, + u16 sob_val, u16 addr) +{ + u32 ctl, value, pkt_size = sizeof(*pkt); + u8 mask = ~(1 << (sob_id & 0x7)); + + memset(pkt, 0, pkt_size); + + value = (sob_id / 8) << GAUDI_PKT_SHORT_VAL_MON_SYNC_GID_SHIFT; + value |= sob_val << GAUDI_PKT_SHORT_VAL_MON_SYNC_VAL_SHIFT; + value |= 0 << GAUDI_PKT_SHORT_VAL_MON_MODE_SHIFT; /* GREATER_OR_EQUAL */ + value |= mask << GAUDI_PKT_SHORT_VAL_MON_MASK_SHIFT; + + ctl = addr << GAUDI_PKT_SHORT_CTL_ADDR_SHIFT; + ctl |= 0 << GAUDI_PKT_SHORT_CTL_OP_SHIFT; /* write the value */ + ctl |= 2 << GAUDI_PKT_SHORT_CTL_BASE_SHIFT; /* W_S MON base */ + ctl |= PACKET_MSG_SHORT << GAUDI_PKT_SHORT_CTL_OPCODE_SHIFT; + ctl |= 0 << GAUDI_PKT_SHORT_CTL_EB_SHIFT; + ctl |= 1 << GAUDI_PKT_SHORT_CTL_RB_SHIFT; + ctl |= 1 << GAUDI_PKT_SHORT_CTL_MB_SHIFT; + + pkt->value = cpu_to_le32(value); + pkt->ctl = cpu_to_le32(ctl); + + return pkt_size; +} + +static u32 gaudi_add_fence_pkt(struct packet_fence *pkt) +{ + u32 ctl, cfg, pkt_size = sizeof(*pkt); + + memset(pkt, 0, pkt_size); + + cfg = 1 << GAUDI_PKT_FENCE_CFG_DEC_VAL_SHIFT; + cfg |= 1 << GAUDI_PKT_FENCE_CFG_TARGET_VAL_SHIFT; + cfg |= 2 << GAUDI_PKT_FENCE_CFG_ID_SHIFT; + + ctl = 0 << GAUDI_PKT_FENCE_CTL_PRED_SHIFT; + ctl |= PACKET_FENCE << GAUDI_PKT_FENCE_CTL_OPCODE_SHIFT; + ctl |= 0 << GAUDI_PKT_FENCE_CTL_EB_SHIFT; + ctl |= 1 << GAUDI_PKT_FENCE_CTL_RB_SHIFT; + ctl |= 1 << GAUDI_PKT_FENCE_CTL_MB_SHIFT; + + pkt->cfg = cpu_to_le32(cfg); + pkt->ctl = cpu_to_le32(ctl); + + return pkt_size; +} + +static void gaudi_gen_wait_cb(struct hl_device *hdev, void *data, u16 sob_id, + u16 sob_val, u16 mon_id, u32 q_idx) +{ + struct hl_cb *cb = (struct hl_cb *) data; + void *buf = (void *) (uintptr_t) cb->kernel_address; + u64 monitor_base, fence_addr = 0; + u32 size = 0; + u16 msg_addr_offset; + + switch (q_idx) { + case GAUDI_QUEUE_ID_DMA_0_0: + fence_addr = mmDMA0_QM_CP_FENCE2_RDATA_0; + break; + case GAUDI_QUEUE_ID_DMA_0_1: + fence_addr = mmDMA0_QM_CP_FENCE2_RDATA_1; + break; + case GAUDI_QUEUE_ID_DMA_0_2: + fence_addr = mmDMA0_QM_CP_FENCE2_RDATA_2; + break; + case GAUDI_QUEUE_ID_DMA_0_3: + fence_addr = mmDMA0_QM_CP_FENCE2_RDATA_3; + break; + case GAUDI_QUEUE_ID_DMA_1_0: + fence_addr = mmDMA1_QM_CP_FENCE2_RDATA_0; + break; + case GAUDI_QUEUE_ID_DMA_1_1: + fence_addr = mmDMA1_QM_CP_FENCE2_RDATA_1; + break; + case GAUDI_QUEUE_ID_DMA_1_2: + fence_addr = mmDMA1_QM_CP_FENCE2_RDATA_2; + break; + case GAUDI_QUEUE_ID_DMA_1_3: + fence_addr = mmDMA1_QM_CP_FENCE2_RDATA_3; + break; + case GAUDI_QUEUE_ID_DMA_5_0: + fence_addr = mmDMA5_QM_CP_FENCE2_RDATA_0; + break; + case GAUDI_QUEUE_ID_DMA_5_1: + fence_addr = mmDMA5_QM_CP_FENCE2_RDATA_1; + break; + case GAUDI_QUEUE_ID_DMA_5_2: + fence_addr = mmDMA5_QM_CP_FENCE2_RDATA_2; + break; + case GAUDI_QUEUE_ID_DMA_5_3: + fence_addr = mmDMA5_QM_CP_FENCE2_RDATA_3; + break; + default: + /* queue index should be valid here */ + dev_crit(hdev->dev, "wrong queue id %d for wait packet\n", + q_idx); + return; + } + + fence_addr += CFG_BASE; + + /* + * monitor_base should be the content of the base0 address registers, + * so it will be added to the msg short offsets + */ + monitor_base = mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0; + + /* First monitor config packet: low address of the sync */ + msg_addr_offset = + (mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 + mon_id * 4) - + monitor_base; + + size += gaudi_add_mon_msg_short(buf + size, (u32) fence_addr, + msg_addr_offset); + + /* Second monitor config packet: high address of the sync */ + msg_addr_offset = + (mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 + mon_id * 4) - + monitor_base; + + size += gaudi_add_mon_msg_short(buf + size, (u32) (fence_addr >> 32), + msg_addr_offset); + + /* + * Third monitor config packet: the payload, i.e. what to write when the + * sync triggers + */ + msg_addr_offset = + (mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_DATA_0 + mon_id * 4) - + monitor_base; + + size += gaudi_add_mon_msg_short(buf + size, 1, msg_addr_offset); + + /* Fourth monitor config packet: bind the monitor to a sync object */ + msg_addr_offset = + (mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0 + mon_id * 4) - + monitor_base; + size += gaudi_add_arm_monitor_pkt(buf + size, sob_id, sob_val, + msg_addr_offset); + + /* Fence packet */ + size += gaudi_add_fence_pkt(buf + size); +} + +static void gaudi_reset_sob(struct hl_device *hdev, void *data) +{ + struct hl_hw_sob *hw_sob = (struct hl_hw_sob *) data; + + dev_dbg(hdev->dev, "reset SOB, q_idx: %d, sob_id: %d\n", hw_sob->q_idx, + hw_sob->sob_id); + + WREG32(mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0 + hw_sob->sob_id * 4, + 0); + + kref_init(&hw_sob->kref); +} + +static void gaudi_set_dma_mask_from_fw(struct hl_device *hdev) +{ + if (RREG32(mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_0) == + HL_POWER9_HOST_MAGIC) { + hdev->power9_64bit_dma_enable = 1; + hdev->dma_mask = 64; + } else { + hdev->power9_64bit_dma_enable = 0; + hdev->dma_mask = 48; + } +} + +static u64 gaudi_get_device_time(struct hl_device *hdev) +{ + u64 device_time = ((u64) RREG32(mmPSOC_TIMESTAMP_CNTCVU)) << 32; + + return device_time | RREG32(mmPSOC_TIMESTAMP_CNTCVL); +} + +static const struct hl_asic_funcs gaudi_funcs = { + .early_init = gaudi_early_init, + .early_fini = gaudi_early_fini, + .late_init = gaudi_late_init, + .late_fini = gaudi_late_fini, + .sw_init = gaudi_sw_init, + .sw_fini = gaudi_sw_fini, + .hw_init = gaudi_hw_init, + .hw_fini = gaudi_hw_fini, + .halt_engines = gaudi_halt_engines, + .suspend = gaudi_suspend, + .resume = gaudi_resume, + .cb_mmap = gaudi_cb_mmap, + .ring_doorbell = gaudi_ring_doorbell, + .pqe_write = gaudi_pqe_write, + .asic_dma_alloc_coherent = gaudi_dma_alloc_coherent, + .asic_dma_free_coherent = gaudi_dma_free_coherent, + .get_int_queue_base = gaudi_get_int_queue_base, + .test_queues = gaudi_test_queues, + .asic_dma_pool_zalloc = gaudi_dma_pool_zalloc, + .asic_dma_pool_free = gaudi_dma_pool_free, + .cpu_accessible_dma_pool_alloc = gaudi_cpu_accessible_dma_pool_alloc, + .cpu_accessible_dma_pool_free = gaudi_cpu_accessible_dma_pool_free, + .hl_dma_unmap_sg = gaudi_dma_unmap_sg, + .cs_parser = gaudi_cs_parser, + .asic_dma_map_sg = gaudi_dma_map_sg, + .get_dma_desc_list_size = gaudi_get_dma_desc_list_size, + .add_end_of_cb_packets = gaudi_add_end_of_cb_packets, + .update_eq_ci = gaudi_update_eq_ci, + .context_switch = gaudi_context_switch, + .restore_phase_topology = gaudi_restore_phase_topology, + .debugfs_read32 = gaudi_debugfs_read32, + .debugfs_write32 = gaudi_debugfs_write32, + .debugfs_read64 = gaudi_debugfs_read64, + .debugfs_write64 = gaudi_debugfs_write64, + .add_device_attr = gaudi_add_device_attr, + .handle_eqe = gaudi_handle_eqe, + .set_pll_profile = gaudi_set_pll_profile, + .get_events_stat = gaudi_get_events_stat, + .read_pte = gaudi_read_pte, + .write_pte = gaudi_write_pte, + .mmu_invalidate_cache = gaudi_mmu_invalidate_cache, + .mmu_invalidate_cache_range = gaudi_mmu_invalidate_cache_range, + .send_heartbeat = gaudi_send_heartbeat, + .enable_clock_gating = gaudi_enable_clock_gating, + .disable_clock_gating = gaudi_disable_clock_gating, + .debug_coresight = gaudi_debug_coresight, + .is_device_idle = gaudi_is_device_idle, + .soft_reset_late_init = gaudi_soft_reset_late_init, + .hw_queues_lock = gaudi_hw_queues_lock, + .hw_queues_unlock = gaudi_hw_queues_unlock, + .get_pci_id = gaudi_get_pci_id, + .get_eeprom_data = gaudi_get_eeprom_data, + .send_cpu_message = gaudi_send_cpu_message, + .get_hw_state = gaudi_get_hw_state, + .pci_bars_map = gaudi_pci_bars_map, + .set_dram_bar_base = gaudi_set_hbm_bar_base, + .init_iatu = gaudi_init_iatu, + .rreg = hl_rreg, + .wreg = hl_wreg, + .halt_coresight = gaudi_halt_coresight, + .get_clk_rate = gaudi_get_clk_rate, + .get_queue_id_for_cq = gaudi_get_queue_id_for_cq, + .read_device_fw_version = gaudi_read_device_fw_version, + .load_firmware_to_device = gaudi_load_firmware_to_device, + .load_boot_fit_to_device = gaudi_load_boot_fit_to_device, + .ext_queue_init = gaudi_ext_queue_init, + .ext_queue_reset = gaudi_ext_queue_reset, + .get_signal_cb_size = gaudi_get_signal_cb_size, + .get_wait_cb_size = gaudi_get_wait_cb_size, + .gen_signal_cb = gaudi_gen_signal_cb, + .gen_wait_cb = gaudi_gen_wait_cb, + .reset_sob = gaudi_reset_sob, + .set_dma_mask_from_fw = gaudi_set_dma_mask_from_fw, + .get_device_time = gaudi_get_device_time +}; + +/** + * gaudi_set_asic_funcs - set GAUDI function pointers + * + * @*hdev: pointer to hl_device structure + * + */ +void gaudi_set_asic_funcs(struct hl_device *hdev) +{ + hdev->asic_funcs = &gaudi_funcs; +} diff --git a/drivers/misc/habanalabs/gaudi/gaudiP.h b/drivers/misc/habanalabs/gaudi/gaudiP.h new file mode 100644 index 000000000000..a46530d375fa --- /dev/null +++ b/drivers/misc/habanalabs/gaudi/gaudiP.h @@ -0,0 +1,261 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2019-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDIP_H_ +#define GAUDIP_H_ + +#include +#include "habanalabs.h" +#include "include/hl_boot_if.h" +#include "include/gaudi/gaudi_packets.h" +#include "include/gaudi/gaudi.h" +#include "include/gaudi/gaudi_async_events.h" + +#define NUMBER_OF_EXT_HW_QUEUES 12 +#define NUMBER_OF_CMPLT_QUEUES NUMBER_OF_EXT_HW_QUEUES +#define NUMBER_OF_CPU_HW_QUEUES 1 +#define NUMBER_OF_INT_HW_QUEUES 100 +#define NUMBER_OF_HW_QUEUES (NUMBER_OF_EXT_HW_QUEUES + \ + NUMBER_OF_CPU_HW_QUEUES + \ + NUMBER_OF_INT_HW_QUEUES) + +/* + * Number of MSI interrupts IDS: + * Each completion queue has 1 ID + * The event queue has 1 ID + */ +#define NUMBER_OF_INTERRUPTS (NUMBER_OF_CMPLT_QUEUES + \ + NUMBER_OF_CPU_HW_QUEUES) + +#if (NUMBER_OF_INTERRUPTS > GAUDI_MSI_ENTRIES) +#error "Number of MSI interrupts must be smaller or equal to GAUDI_MSI_ENTRIES" +#endif + +#define QMAN_FENCE_TIMEOUT_USEC 10000 /* 10 ms */ + +#define CORESIGHT_TIMEOUT_USEC 100000 /* 100 ms */ + +#define GAUDI_MAX_CLK_FREQ 2200000000ull /* 2200 MHz */ + +#define MAX_POWER_DEFAULT 200000 /* 200W */ + +#define GAUDI_CPU_TIMEOUT_USEC 15000000 /* 15s */ + +#define TPC_ENABLED_MASK 0xFF + +#define GAUDI_HBM_SIZE_32GB 0x800000000ull +#define GAUDI_HBM_DEVICES 4 +#define GAUDI_HBM_CHANNELS 8 +#define GAUDI_HBM_CFG_BASE (mmHBM0_BASE - CFG_BASE) +#define GAUDI_HBM_CFG_OFFSET (mmHBM1_BASE - mmHBM0_BASE) + +#define DMA_MAX_TRANSFER_SIZE U32_MAX + +#define GAUDI_DEFAULT_CARD_NAME "HL2000" + +#define PCI_DMA_NUMBER_OF_CHNLS 3 +#define HBM_DMA_NUMBER_OF_CHNLS 5 +#define DMA_NUMBER_OF_CHNLS (PCI_DMA_NUMBER_OF_CHNLS + \ + HBM_DMA_NUMBER_OF_CHNLS) + +#define MME_NUMBER_OF_SLAVE_ENGINES 2 +#define MME_NUMBER_OF_ENGINES (MME_NUMBER_OF_MASTER_ENGINES + \ + MME_NUMBER_OF_SLAVE_ENGINES) +#define MME_NUMBER_OF_QMANS (MME_NUMBER_OF_MASTER_ENGINES * \ + QMAN_STREAMS) + +#define QMAN_STREAMS 4 + +#define DMA_QMAN_OFFSET (mmDMA1_QM_BASE - mmDMA0_QM_BASE) +#define TPC_QMAN_OFFSET (mmTPC1_QM_BASE - mmTPC0_QM_BASE) +#define MME_QMAN_OFFSET (mmMME1_QM_BASE - mmMME0_QM_BASE) +#define NIC_MACRO_QMAN_OFFSET (mmNIC1_QM0_BASE - mmNIC0_QM0_BASE) + +#define TPC_CFG_OFFSET (mmTPC1_CFG_BASE - mmTPC0_CFG_BASE) + +#define DMA_CORE_OFFSET (mmDMA1_CORE_BASE - mmDMA0_CORE_BASE) + +#define SIF_RTR_CTRL_OFFSET (mmSIF_RTR_CTRL_1_BASE - mmSIF_RTR_CTRL_0_BASE) + +#define NIF_RTR_CTRL_OFFSET (mmNIF_RTR_CTRL_1_BASE - mmNIF_RTR_CTRL_0_BASE) + +#define MME_ACC_OFFSET (mmMME1_ACC_BASE - mmMME0_ACC_BASE) +#define SRAM_BANK_OFFSET (mmSRAM_Y0_X1_RTR_BASE - mmSRAM_Y0_X0_RTR_BASE) + +#define NUM_OF_SOB_IN_BLOCK \ + (((mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_2047 - \ + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0) + 4) >> 2) + +#define NUM_OF_MONITORS_IN_BLOCK \ + (((mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_511 - \ + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_0) + 4) >> 2) + + +/* DRAM Memory Map */ + +#define CPU_FW_IMAGE_SIZE 0x10000000 /* 256MB */ +#define MMU_PAGE_TABLES_SIZE 0x0BF00000 /* 191MB */ +#define MMU_CACHE_MNG_SIZE 0x00100000 /* 1MB */ +#define RESERVED 0x04000000 /* 64MB */ + +#define CPU_FW_IMAGE_ADDR DRAM_PHYS_BASE +#define MMU_PAGE_TABLES_ADDR (CPU_FW_IMAGE_ADDR + CPU_FW_IMAGE_SIZE) +#define MMU_CACHE_MNG_ADDR (MMU_PAGE_TABLES_ADDR + MMU_PAGE_TABLES_SIZE) + +#define DRAM_DRIVER_END_ADDR (MMU_CACHE_MNG_ADDR + MMU_CACHE_MNG_SIZE +\ + RESERVED) + +#define DRAM_BASE_ADDR_USER 0x20000000 + +#if (DRAM_DRIVER_END_ADDR > DRAM_BASE_ADDR_USER) +#error "Driver must reserve no more than 512MB" +#endif + +/* Internal QMANs PQ sizes */ + +#define MME_QMAN_LENGTH 64 +#define MME_QMAN_SIZE_IN_BYTES (MME_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE) + +#define HBM_DMA_QMAN_LENGTH 64 +#define HBM_DMA_QMAN_SIZE_IN_BYTES \ + (HBM_DMA_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE) + +#define TPC_QMAN_LENGTH 64 +#define TPC_QMAN_SIZE_IN_BYTES (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE) + +#define SRAM_USER_BASE_OFFSET GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START + +/* Virtual address space */ +#define VA_HOST_SPACE_START 0x1000000000000ull /* 256TB */ +#define VA_HOST_SPACE_END 0x3FF8000000000ull /* 1PB - 1TB */ +#define VA_HOST_SPACE_SIZE (VA_HOST_SPACE_END - \ + VA_HOST_SPACE_START) /* 767TB */ + +#define HW_CAP_PLL 0x00000001 +#define HW_CAP_HBM 0x00000002 +#define HW_CAP_MMU 0x00000004 +#define HW_CAP_MME 0x00000008 +#define HW_CAP_CPU 0x00000010 +#define HW_CAP_PCI_DMA 0x00000020 +#define HW_CAP_MSI 0x00000040 +#define HW_CAP_CPU_Q 0x00000080 +#define HW_CAP_HBM_DMA 0x00000100 +#define HW_CAP_CLK_GATE 0x00000200 +#define HW_CAP_SRAM_SCRAMBLER 0x00000400 +#define HW_CAP_HBM_SCRAMBLER 0x00000800 + +#define HW_CAP_TPC0 0x01000000 +#define HW_CAP_TPC1 0x02000000 +#define HW_CAP_TPC2 0x04000000 +#define HW_CAP_TPC3 0x08000000 +#define HW_CAP_TPC4 0x10000000 +#define HW_CAP_TPC5 0x20000000 +#define HW_CAP_TPC6 0x40000000 +#define HW_CAP_TPC7 0x80000000 +#define HW_CAP_TPC_MASK 0xFF000000 +#define HW_CAP_TPC_SHIFT 24 + +#define GAUDI_CPU_PCI_MSB_ADDR(addr) (((addr) & GENMASK_ULL(49, 39)) >> 39) +#define GAUDI_PCI_TO_CPU_ADDR(addr) \ + do { \ + (addr) &= ~GENMASK_ULL(49, 39); \ + (addr) |= BIT_ULL(39); \ + } while (0) +#define GAUDI_CPU_TO_PCI_ADDR(addr, extension) \ + do { \ + (addr) &= ~GENMASK_ULL(49, 39); \ + (addr) |= (u64) (extension) << 39; \ + } while (0) + +enum gaudi_dma_channels { + GAUDI_PCI_DMA_1, + GAUDI_PCI_DMA_2, + GAUDI_PCI_DMA_3, + GAUDI_HBM_DMA_1, + GAUDI_HBM_DMA_2, + GAUDI_HBM_DMA_3, + GAUDI_HBM_DMA_4, + GAUDI_HBM_DMA_5, + GAUDI_DMA_MAX +}; + +enum gaudi_tpc_mask { + GAUDI_TPC_MASK_TPC0 = 0x01, + GAUDI_TPC_MASK_TPC1 = 0x02, + GAUDI_TPC_MASK_TPC2 = 0x04, + GAUDI_TPC_MASK_TPC3 = 0x08, + GAUDI_TPC_MASK_TPC4 = 0x10, + GAUDI_TPC_MASK_TPC5 = 0x20, + GAUDI_TPC_MASK_TPC6 = 0x40, + GAUDI_TPC_MASK_TPC7 = 0x80, + GAUDI_TPC_MASK_ALL = 0xFF +}; + +/** + * struct gaudi_internal_qman_info - Internal QMAN information. + * @pq_kernel_addr: Kernel address of the PQ memory area in the host. + * @pq_dma_addr: DMA address of the PQ memory area in the host. + * @pq_size: Size of allocated host memory for PQ. + */ +struct gaudi_internal_qman_info { + void *pq_kernel_addr; + dma_addr_t pq_dma_addr; + size_t pq_size; +}; + +/** + * struct gaudi_device - ASIC specific manage structure. + * @armcp_info_get: get information on device from ArmCP + * @hw_queues_lock: protects the H/W queues from concurrent access. + * @clk_gate_mutex: protects code areas that require clock gating to be disabled + * temporarily + * @internal_qmans: Internal QMANs information. The array size is larger than + * the actual number of internal queues because they are not in + * consecutive order. + * @hbm_bar_cur_addr: current address of HBM PCI bar. + * @max_freq_value: current max clk frequency. + * @events: array that holds all event id's + * @events_stat: array that holds histogram of all received events. + * @events_stat_aggregate: same as events_stat but doesn't get cleared on reset + * @hw_cap_initialized: This field contains a bit per H/W engine. When that + * engine is initialized, that bit is set by the driver to + * signal we can use this engine in later code paths. + * Each bit is cleared upon reset of its corresponding H/W + * engine. + * @multi_msi_mode: whether we are working in multi MSI single MSI mode. + * Multi MSI is possible only with IOMMU enabled. + * @ext_queue_idx: helper index for external queues initialization. + */ +struct gaudi_device { + int (*armcp_info_get)(struct hl_device *hdev); + + /* TODO: remove hw_queues_lock after moving to scheduler code */ + spinlock_t hw_queues_lock; + struct mutex clk_gate_mutex; + + struct gaudi_internal_qman_info internal_qmans[GAUDI_QUEUE_ID_SIZE]; + + u64 hbm_bar_cur_addr; + u64 max_freq_value; + + u32 events[GAUDI_EVENT_SIZE]; + u32 events_stat[GAUDI_EVENT_SIZE]; + u32 events_stat_aggregate[GAUDI_EVENT_SIZE]; + u32 hw_cap_initialized; + u8 multi_msi_mode; + u8 ext_queue_idx; +}; + +void gaudi_init_security(struct hl_device *hdev); +void gaudi_add_device_attr(struct hl_device *hdev, + struct attribute_group *dev_attr_grp); +void gaudi_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq); +int gaudi_debug_coresight(struct hl_device *hdev, void *data); +void gaudi_halt_coresight(struct hl_device *hdev); +int gaudi_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk); + +#endif /* GAUDIP_H_ */ diff --git a/drivers/misc/habanalabs/gaudi/gaudi_coresight.c b/drivers/misc/habanalabs/gaudi/gaudi_coresight.c new file mode 100644 index 000000000000..bf0e062d7b87 --- /dev/null +++ b/drivers/misc/habanalabs/gaudi/gaudi_coresight.c @@ -0,0 +1,884 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + */ + +#include "gaudiP.h" +#include "include/gaudi/gaudi_coresight.h" +#include "include/gaudi/asic_reg/gaudi_regs.h" +#include "include/gaudi/gaudi_masks.h" + +#include +#include + +#define SPMU_SECTION_SIZE MME0_ACC_SPMU_MAX_OFFSET +#define SPMU_EVENT_TYPES_OFFSET 0x400 +#define SPMU_MAX_COUNTERS 6 + +static u64 debug_stm_regs[GAUDI_STM_LAST + 1] = { + [GAUDI_STM_MME0_ACC] = mmMME0_ACC_STM_BASE, + [GAUDI_STM_MME0_SBAB] = mmMME0_SBAB_STM_BASE, + [GAUDI_STM_MME0_CTRL] = mmMME0_CTRL_STM_BASE, + [GAUDI_STM_MME1_ACC] = mmMME1_ACC_STM_BASE, + [GAUDI_STM_MME1_SBAB] = mmMME1_SBAB_STM_BASE, + [GAUDI_STM_MME1_CTRL] = mmMME1_CTRL_STM_BASE, + [GAUDI_STM_MME2_ACC] = mmMME2_ACC_STM_BASE, + [GAUDI_STM_MME2_SBAB] = mmMME2_SBAB_STM_BASE, + [GAUDI_STM_MME2_CTRL] = mmMME2_CTRL_STM_BASE, + [GAUDI_STM_MME3_ACC] = mmMME3_ACC_STM_BASE, + [GAUDI_STM_MME3_SBAB] = mmMME3_SBAB_STM_BASE, + [GAUDI_STM_MME3_CTRL] = mmMME3_CTRL_STM_BASE, + [GAUDI_STM_DMA_IF_W_S] = mmDMA_IF_W_S_STM_BASE, + [GAUDI_STM_DMA_IF_E_S] = mmDMA_IF_E_S_STM_BASE, + [GAUDI_STM_DMA_IF_W_N] = mmDMA_IF_W_N_STM_BASE, + [GAUDI_STM_DMA_IF_E_N] = mmDMA_IF_E_N_STM_BASE, + [GAUDI_STM_CPU] = mmCPU_STM_BASE, + [GAUDI_STM_DMA_CH_0_CS] = mmDMA_CH_0_CS_STM_BASE, + [GAUDI_STM_DMA_CH_1_CS] = mmDMA_CH_1_CS_STM_BASE, + [GAUDI_STM_DMA_CH_2_CS] = mmDMA_CH_2_CS_STM_BASE, + [GAUDI_STM_DMA_CH_3_CS] = mmDMA_CH_3_CS_STM_BASE, + [GAUDI_STM_DMA_CH_4_CS] = mmDMA_CH_4_CS_STM_BASE, + [GAUDI_STM_DMA_CH_5_CS] = mmDMA_CH_5_CS_STM_BASE, + [GAUDI_STM_DMA_CH_6_CS] = mmDMA_CH_6_CS_STM_BASE, + [GAUDI_STM_DMA_CH_7_CS] = mmDMA_CH_7_CS_STM_BASE, + [GAUDI_STM_PCIE] = mmPCIE_STM_BASE, + [GAUDI_STM_MMU_CS] = mmMMU_CS_STM_BASE, + [GAUDI_STM_PSOC] = mmPSOC_STM_BASE, + [GAUDI_STM_NIC0_0] = mmSTM_0_NIC0_DBG_BASE, + [GAUDI_STM_NIC0_1] = mmSTM_1_NIC0_DBG_BASE, + [GAUDI_STM_NIC1_0] = mmSTM_0_NIC1_DBG_BASE, + [GAUDI_STM_NIC1_1] = mmSTM_1_NIC1_DBG_BASE, + [GAUDI_STM_NIC2_0] = mmSTM_0_NIC2_DBG_BASE, + [GAUDI_STM_NIC2_1] = mmSTM_1_NIC2_DBG_BASE, + [GAUDI_STM_NIC3_0] = mmSTM_0_NIC3_DBG_BASE, + [GAUDI_STM_NIC3_1] = mmSTM_1_NIC3_DBG_BASE, + [GAUDI_STM_NIC4_0] = mmSTM_0_NIC4_DBG_BASE, + [GAUDI_STM_NIC4_1] = mmSTM_1_NIC4_DBG_BASE, + [GAUDI_STM_TPC0_EML] = mmTPC0_EML_STM_BASE, + [GAUDI_STM_TPC1_EML] = mmTPC1_EML_STM_BASE, + [GAUDI_STM_TPC2_EML] = mmTPC2_EML_STM_BASE, + [GAUDI_STM_TPC3_EML] = mmTPC3_EML_STM_BASE, + [GAUDI_STM_TPC4_EML] = mmTPC4_EML_STM_BASE, + [GAUDI_STM_TPC5_EML] = mmTPC5_EML_STM_BASE, + [GAUDI_STM_TPC6_EML] = mmTPC6_EML_STM_BASE, + [GAUDI_STM_TPC7_EML] = mmTPC7_EML_STM_BASE +}; + +static u64 debug_etf_regs[GAUDI_ETF_LAST + 1] = { + [GAUDI_ETF_MME0_ACC] = mmMME0_ACC_ETF_BASE, + [GAUDI_ETF_MME0_SBAB] = mmMME0_SBAB_ETF_BASE, + [GAUDI_ETF_MME0_CTRL] = mmMME0_CTRL_ETF_BASE, + [GAUDI_ETF_MME1_ACC] = mmMME1_ACC_ETF_BASE, + [GAUDI_ETF_MME1_SBAB] = mmMME1_SBAB_ETF_BASE, + [GAUDI_ETF_MME1_CTRL] = mmMME1_CTRL_ETF_BASE, + [GAUDI_ETF_MME2_ACC] = mmMME2_MME2_ACC_ETF_BASE, + [GAUDI_ETF_MME2_SBAB] = mmMME2_SBAB_ETF_BASE, + [GAUDI_ETF_MME2_CTRL] = mmMME2_CTRL_ETF_BASE, + [GAUDI_ETF_MME3_ACC] = mmMME3_ACC_ETF_BASE, + [GAUDI_ETF_MME3_SBAB] = mmMME3_SBAB_ETF_BASE, + [GAUDI_ETF_MME3_CTRL] = mmMME3_CTRL_ETF_BASE, + [GAUDI_ETF_DMA_IF_W_S] = mmDMA_IF_W_S_ETF_BASE, + [GAUDI_ETF_DMA_IF_E_S] = mmDMA_IF_E_S_ETF_BASE, + [GAUDI_ETF_DMA_IF_W_N] = mmDMA_IF_W_N_ETF_BASE, + [GAUDI_ETF_DMA_IF_E_N] = mmDMA_IF_E_N_ETF_BASE, + [GAUDI_ETF_CPU_0] = mmCPU_ETF_0_BASE, + [GAUDI_ETF_CPU_1] = mmCPU_ETF_1_BASE, + [GAUDI_ETF_CPU_TRACE] = mmCPU_ETF_TRACE_BASE, + [GAUDI_ETF_DMA_CH_0_CS] = mmDMA_CH_0_CS_ETF_BASE, + [GAUDI_ETF_DMA_CH_1_CS] = mmDMA_CH_1_CS_ETF_BASE, + [GAUDI_ETF_DMA_CH_2_CS] = mmDMA_CH_2_CS_ETF_BASE, + [GAUDI_ETF_DMA_CH_3_CS] = mmDMA_CH_3_CS_ETF_BASE, + [GAUDI_ETF_DMA_CH_4_CS] = mmDMA_CH_4_CS_ETF_BASE, + [GAUDI_ETF_DMA_CH_5_CS] = mmDMA_CH_5_CS_ETF_BASE, + [GAUDI_ETF_DMA_CH_6_CS] = mmDMA_CH_6_CS_ETF_BASE, + [GAUDI_ETF_DMA_CH_7_CS] = mmDMA_CH_7_CS_ETF_BASE, + [GAUDI_ETF_PCIE] = mmPCIE_ETF_BASE, + [GAUDI_ETF_MMU_CS] = mmMMU_CS_ETF_BASE, + [GAUDI_ETF_PSOC] = mmPSOC_ETF_BASE, + [GAUDI_ETF_NIC0_0] = mmETF_0_NIC0_DBG_BASE, + [GAUDI_ETF_NIC0_1] = mmETF_1_NIC0_DBG_BASE, + [GAUDI_ETF_NIC1_0] = mmETF_0_NIC1_DBG_BASE, + [GAUDI_ETF_NIC1_1] = mmETF_1_NIC1_DBG_BASE, + [GAUDI_ETF_NIC2_0] = mmETF_0_NIC2_DBG_BASE, + [GAUDI_ETF_NIC2_1] = mmETF_1_NIC2_DBG_BASE, + [GAUDI_ETF_NIC3_0] = mmETF_0_NIC3_DBG_BASE, + [GAUDI_ETF_NIC3_1] = mmETF_1_NIC3_DBG_BASE, + [GAUDI_ETF_NIC4_0] = mmETF_0_NIC4_DBG_BASE, + [GAUDI_ETF_NIC4_1] = mmETF_1_NIC4_DBG_BASE, + [GAUDI_ETF_TPC0_EML] = mmTPC0_EML_ETF_BASE, + [GAUDI_ETF_TPC1_EML] = mmTPC1_EML_ETF_BASE, + [GAUDI_ETF_TPC2_EML] = mmTPC2_EML_ETF_BASE, + [GAUDI_ETF_TPC3_EML] = mmTPC3_EML_ETF_BASE, + [GAUDI_ETF_TPC4_EML] = mmTPC4_EML_ETF_BASE, + [GAUDI_ETF_TPC5_EML] = mmTPC5_EML_ETF_BASE, + [GAUDI_ETF_TPC6_EML] = mmTPC6_EML_ETF_BASE, + [GAUDI_ETF_TPC7_EML] = mmTPC7_EML_ETF_BASE +}; + +static u64 debug_funnel_regs[GAUDI_FUNNEL_LAST + 1] = { + [GAUDI_FUNNEL_MME0_ACC] = mmMME0_ACC_FUNNEL_BASE, + [GAUDI_FUNNEL_MME1_ACC] = mmMME1_ACC_FUNNEL_BASE, + [GAUDI_FUNNEL_MME2_ACC] = mmMME2_ACC_FUNNEL_BASE, + [GAUDI_FUNNEL_MME3_ACC] = mmMME3_ACC_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y0_X0] = mmSRAM_Y0_X0_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y0_X1] = mmSRAM_Y0_X1_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y0_X2] = mmSRAM_Y0_X2_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y0_X3] = mmSRAM_Y0_X3_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y0_X4] = mmSRAM_Y0_X4_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y0_X5] = mmSRAM_Y0_X5_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y0_X6] = mmSRAM_Y0_X6_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y0_X7] = mmSRAM_Y0_X7_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y1_X0] = mmSRAM_Y1_X0_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y1_X1] = mmSRAM_Y1_X1_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y1_X2] = mmSRAM_Y1_X2_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y1_X3] = mmSRAM_Y1_X3_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y1_X4] = mmSRAM_Y1_X4_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y1_X5] = mmSRAM_Y1_X5_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y1_X6] = mmSRAM_Y1_X6_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y1_X7] = mmSRAM_Y1_X7_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y2_X0] = mmSRAM_Y2_X0_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y2_X1] = mmSRAM_Y2_X1_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y2_X2] = mmSRAM_Y2_X2_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y2_X3] = mmSRAM_Y2_X3_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y2_X4] = mmSRAM_Y2_X4_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y2_X5] = mmSRAM_Y2_X5_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y2_X6] = mmSRAM_Y2_X6_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y2_X7] = mmSRAM_Y2_X7_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y3_X0] = mmSRAM_Y3_X0_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y3_X1] = mmSRAM_Y3_X1_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y3_X2] = mmSRAM_Y3_X2_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y3_X4] = mmSRAM_Y3_X4_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y3_X3] = mmSRAM_Y3_X3_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y3_X5] = mmSRAM_Y3_X5_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y3_X6] = mmSRAM_Y3_X6_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y3_X7] = mmSRAM_Y3_X7_FUNNEL_BASE, + [GAUDI_FUNNEL_SIF_0] = mmSIF_FUNNEL_0_BASE, + [GAUDI_FUNNEL_SIF_1] = mmSIF_FUNNEL_1_BASE, + [GAUDI_FUNNEL_SIF_2] = mmSIF_FUNNEL_2_BASE, + [GAUDI_FUNNEL_SIF_3] = mmSIF_FUNNEL_3_BASE, + [GAUDI_FUNNEL_SIF_4] = mmSIF_FUNNEL_4_BASE, + [GAUDI_FUNNEL_SIF_5] = mmSIF_FUNNEL_5_BASE, + [GAUDI_FUNNEL_SIF_6] = mmSIF_FUNNEL_6_BASE, + [GAUDI_FUNNEL_SIF_7] = mmSIF_FUNNEL_7_BASE, + [GAUDI_FUNNEL_NIF_0] = mmNIF_FUNNEL_0_BASE, + [GAUDI_FUNNEL_NIF_1] = mmNIF_FUNNEL_1_BASE, + [GAUDI_FUNNEL_NIF_2] = mmNIF_FUNNEL_2_BASE, + [GAUDI_FUNNEL_NIF_3] = mmNIF_FUNNEL_3_BASE, + [GAUDI_FUNNEL_NIF_4] = mmNIF_FUNNEL_4_BASE, + [GAUDI_FUNNEL_NIF_5] = mmNIF_FUNNEL_5_BASE, + [GAUDI_FUNNEL_NIF_6] = mmNIF_FUNNEL_6_BASE, + [GAUDI_FUNNEL_NIF_7] = mmNIF_FUNNEL_7_BASE, + [GAUDI_FUNNEL_DMA_IF_W_S] = mmDMA_IF_W_S_FUNNEL_BASE, + [GAUDI_FUNNEL_DMA_IF_E_S] = mmDMA_IF_E_S_FUNNEL_BASE, + [GAUDI_FUNNEL_DMA_IF_W_N] = mmDMA_IF_W_N_FUNNEL_BASE, + [GAUDI_FUNNEL_DMA_IF_E_N] = mmDMA_IF_E_N_FUNNEL_BASE, + [GAUDI_FUNNEL_CPU] = mmCPU_FUNNEL_BASE, + [GAUDI_FUNNEL_NIC_TPC_W_S] = mmNIC_TPC_FUNNEL_W_S_BASE, + [GAUDI_FUNNEL_NIC_TPC_E_S] = mmNIC_TPC_FUNNEL_E_S_BASE, + [GAUDI_FUNNEL_NIC_TPC_W_N] = mmNIC_TPC_FUNNEL_W_N_BASE, + [GAUDI_FUNNEL_NIC_TPC_E_N] = mmNIC_TPC_FUNNEL_E_N_BASE, + [GAUDI_FUNNEL_PCIE] = mmPCIE_FUNNEL_BASE, + [GAUDI_FUNNEL_PSOC] = mmPSOC_FUNNEL_BASE, + [GAUDI_FUNNEL_NIC0] = mmFUNNEL_NIC0_DBG_BASE, + [GAUDI_FUNNEL_NIC1] = mmFUNNEL_NIC1_DBG_BASE, + [GAUDI_FUNNEL_NIC2] = mmFUNNEL_NIC2_DBG_BASE, + [GAUDI_FUNNEL_NIC3] = mmFUNNEL_NIC3_DBG_BASE, + [GAUDI_FUNNEL_NIC4] = mmFUNNEL_NIC4_DBG_BASE, + [GAUDI_FUNNEL_TPC0_EML] = mmTPC0_EML_FUNNEL_BASE, + [GAUDI_FUNNEL_TPC1_EML] = mmTPC1_EML_FUNNEL_BASE, + [GAUDI_FUNNEL_TPC2_EML] = mmTPC2_EML_FUNNEL_BASE, + [GAUDI_FUNNEL_TPC3_EML] = mmTPC3_EML_FUNNEL_BASE, + [GAUDI_FUNNEL_TPC4_EML] = mmTPC4_EML_FUNNEL_BASE, + [GAUDI_FUNNEL_TPC5_EML] = mmTPC5_EML_FUNNEL_BASE, + [GAUDI_FUNNEL_TPC6_EML] = mmTPC6_EML_FUNNEL_BASE, + [GAUDI_FUNNEL_TPC7_EML] = mmTPC7_EML_FUNNEL_BASE +}; + +static u64 debug_bmon_regs[GAUDI_BMON_LAST + 1] = { + [GAUDI_BMON_MME0_ACC_0] = mmMME0_ACC_BMON0_BASE, + [GAUDI_BMON_MME0_SBAB_0] = mmMME0_SBAB_BMON0_BASE, + [GAUDI_BMON_MME0_SBAB_1] = mmMME0_SBAB_BMON1_BASE, + [GAUDI_BMON_MME0_CTRL_0] = mmMME0_CTRL_BMON0_BASE, + [GAUDI_BMON_MME0_CTRL_1] = mmMME0_CTRL_BMON1_BASE, + [GAUDI_BMON_MME1_ACC_0] = mmMME1_ACC_BMON0_BASE, + [GAUDI_BMON_MME1_SBAB_0] = mmMME1_SBAB_BMON0_BASE, + [GAUDI_BMON_MME1_SBAB_1] = mmMME1_SBAB_BMON1_BASE, + [GAUDI_BMON_MME1_CTRL_0] = mmMME1_CTRL_BMON0_BASE, + [GAUDI_BMON_MME1_CTRL_1] = mmMME1_CTRL_BMON1_BASE, + [GAUDI_BMON_MME2_ACC_0] = mmMME2_ACC_BMON0_BASE, + [GAUDI_BMON_MME2_SBAB_0] = mmMME2_SBAB_BMON0_BASE, + [GAUDI_BMON_MME2_SBAB_1] = mmMME2_SBAB_BMON1_BASE, + [GAUDI_BMON_MME2_CTRL_0] = mmMME2_CTRL_BMON0_BASE, + [GAUDI_BMON_MME2_CTRL_1] = mmMME2_CTRL_BMON1_BASE, + [GAUDI_BMON_MME3_ACC_0] = mmMME3_ACC_BMON0_BASE, + [GAUDI_BMON_MME3_SBAB_0] = mmMME3_SBAB_BMON0_BASE, + [GAUDI_BMON_MME3_SBAB_1] = mmMME3_SBAB_BMON1_BASE, + [GAUDI_BMON_MME3_CTRL_0] = mmMME3_CTRL_BMON0_BASE, + [GAUDI_BMON_MME3_CTRL_1] = mmMME3_CTRL_BMON1_BASE, + [GAUDI_BMON_DMA_IF_W_S_SOB_WR] = mmDMA_IF_W_S_SOB_WR_BMON_BASE, + [GAUDI_BMON_DMA_IF_W_S_0_WR] = mmDMA_IF_W_S_HBM0_WR_BMON_BASE, + [GAUDI_BMON_DMA_IF_W_S_0_RD] = mmDMA_IF_W_S_HBM0_RD_BMON_BASE, + [GAUDI_BMON_DMA_IF_W_S_1_WR] = mmDMA_IF_W_S_HBM1_WR_BMON_BASE, + [GAUDI_BMON_DMA_IF_W_S_1_RD] = mmDMA_IF_W_S_HBM1_RD_BMON_BASE, + [GAUDI_BMON_DMA_IF_E_S_SOB_WR] = mmDMA_IF_E_S_SOB_WR_BMON_BASE, + [GAUDI_BMON_DMA_IF_E_S_0_WR] = mmDMA_IF_E_S_HBM0_WR_BMON_BASE, + [GAUDI_BMON_DMA_IF_E_S_0_RD] = mmDMA_IF_E_S_HBM0_RD_BMON_BASE, + [GAUDI_BMON_DMA_IF_E_S_1_WR] = mmDMA_IF_E_S_HBM1_WR_BMON_BASE, + [GAUDI_BMON_DMA_IF_E_S_1_RD] = mmDMA_IF_E_S_HBM1_RD_BMON_BASE, + [GAUDI_BMON_DMA_IF_W_N_SOB_WR] = mmDMA_IF_W_N_SOB_WR_BMON_BASE, + [GAUDI_BMON_DMA_IF_W_N_HBM0_WR] = mmDMA_IF_W_N_HBM0_WR_BMON_BASE, + [GAUDI_BMON_DMA_IF_W_N_HBM0_RD] = mmDMA_IF_W_N_HBM0_RD_BMON_BASE, + [GAUDI_BMON_DMA_IF_W_N_HBM1_WR] = mmDMA_IF_W_N_HBM1_WR_BMON_BASE, + [GAUDI_BMON_DMA_IF_W_N_HBM1_RD] = mmDMA_IF_W_N_HBM1_RD_BMON_BASE, + [GAUDI_BMON_DMA_IF_E_N_SOB_WR] = mmDMA_IF_E_N_SOB_WR_BMON_BASE, + [GAUDI_BMON_DMA_IF_E_N_HBM0_WR] = mmDMA_IF_E_N_HBM0_WR_BMON_BASE, + [GAUDI_BMON_DMA_IF_E_N_HBM0_RD] = mmDMA_IF_E_N_HBM0_RD_BMON_BASE, + [GAUDI_BMON_DMA_IF_E_N_HBM1_WR] = mmDMA_IF_E_N_HBM1_WR_BMON_BASE, + [GAUDI_BMON_DMA_IF_E_N_HBM1_RD] = mmDMA_IF_E_N_HBM1_RD_BMON_BASE, + [GAUDI_BMON_CPU_WR] = mmCPU_WR_BMON_BASE, + [GAUDI_BMON_CPU_RD] = mmCPU_RD_BMON_BASE, + [GAUDI_BMON_DMA_CH_0_0] = mmDMA_CH_0_BMON_0_BASE, + [GAUDI_BMON_DMA_CH_0_1] = mmDMA_CH_0_BMON_1_BASE, + [GAUDI_BMON_DMA_CH_1_0] = mmDMA_CH_1_BMON_0_BASE, + [GAUDI_BMON_DMA_CH_1_1] = mmDMA_CH_1_BMON_1_BASE, + [GAUDI_BMON_DMA_CH_2_0] = mmDMA_CH_2_BMON_0_BASE, + [GAUDI_BMON_DMA_CH_2_1] = mmDMA_CH_2_BMON_1_BASE, + [GAUDI_BMON_DMA_CH_3_0] = mmDMA_CH_3_BMON_0_BASE, + [GAUDI_BMON_DMA_CH_3_1] = mmDMA_CH_3_BMON_1_BASE, + [GAUDI_BMON_DMA_CH_4_0] = mmDMA_CH_4_BMON_0_BASE, + [GAUDI_BMON_DMA_CH_4_1] = mmDMA_CH_4_BMON_1_BASE, + [GAUDI_BMON_DMA_CH_5_0] = mmDMA_CH_5_BMON_0_BASE, + [GAUDI_BMON_DMA_CH_5_1] = mmDMA_CH_5_BMON_1_BASE, + [GAUDI_BMON_DMA_CH_6_0] = mmDMA_CH_6_BMON_0_BASE, + [GAUDI_BMON_DMA_CH_6_1] = mmDMA_CH_6_BMON_1_BASE, + [GAUDI_BMON_DMA_CH_7_0] = mmDMA_CH_7_BMON_0_BASE, + [GAUDI_BMON_DMA_CH_7_1] = mmDMA_CH_7_BMON_1_BASE, + [GAUDI_BMON_PCIE_MSTR_WR] = mmPCIE_BMON_MSTR_WR_BASE, + [GAUDI_BMON_PCIE_MSTR_RD] = mmPCIE_BMON_MSTR_RD_BASE, + [GAUDI_BMON_PCIE_SLV_WR] = mmPCIE_BMON_SLV_WR_BASE, + [GAUDI_BMON_PCIE_SLV_RD] = mmPCIE_BMON_SLV_RD_BASE, + [GAUDI_BMON_MMU_0] = mmMMU_BMON_0_BASE, + [GAUDI_BMON_MMU_1] = mmMMU_BMON_1_BASE, + [GAUDI_BMON_NIC0_0] = mmBMON0_NIC0_DBG_BASE, + [GAUDI_BMON_NIC0_1] = mmBMON1_NIC0_DBG_BASE, + [GAUDI_BMON_NIC0_2] = mmBMON2_NIC0_DBG_BASE, + [GAUDI_BMON_NIC0_3] = mmBMON3_NIC0_DBG_BASE, + [GAUDI_BMON_NIC0_4] = mmBMON4_NIC0_DBG_BASE, + [GAUDI_BMON_NIC1_0] = mmBMON0_NIC1_DBG_BASE, + [GAUDI_BMON_NIC1_1] = mmBMON1_NIC1_DBG_BASE, + [GAUDI_BMON_NIC1_2] = mmBMON2_NIC1_DBG_BASE, + [GAUDI_BMON_NIC1_3] = mmBMON3_NIC1_DBG_BASE, + [GAUDI_BMON_NIC1_4] = mmBMON4_NIC1_DBG_BASE, + [GAUDI_BMON_NIC2_0] = mmBMON0_NIC2_DBG_BASE, + [GAUDI_BMON_NIC2_1] = mmBMON1_NIC2_DBG_BASE, + [GAUDI_BMON_NIC2_2] = mmBMON2_NIC2_DBG_BASE, + [GAUDI_BMON_NIC2_3] = mmBMON3_NIC2_DBG_BASE, + [GAUDI_BMON_NIC2_4] = mmBMON4_NIC2_DBG_BASE, + [GAUDI_BMON_NIC3_0] = mmBMON0_NIC3_DBG_BASE, + [GAUDI_BMON_NIC3_1] = mmBMON1_NIC3_DBG_BASE, + [GAUDI_BMON_NIC3_2] = mmBMON2_NIC3_DBG_BASE, + [GAUDI_BMON_NIC3_3] = mmBMON3_NIC3_DBG_BASE, + [GAUDI_BMON_NIC3_4] = mmBMON4_NIC3_DBG_BASE, + [GAUDI_BMON_NIC4_0] = mmBMON0_NIC4_DBG_BASE, + [GAUDI_BMON_NIC4_1] = mmBMON1_NIC4_DBG_BASE, + [GAUDI_BMON_NIC4_2] = mmBMON2_NIC4_DBG_BASE, + [GAUDI_BMON_NIC4_3] = mmBMON3_NIC4_DBG_BASE, + [GAUDI_BMON_NIC4_4] = mmBMON4_NIC4_DBG_BASE, + [GAUDI_BMON_TPC0_EML_0] = mmTPC0_EML_BUSMON_0_BASE, + [GAUDI_BMON_TPC0_EML_1] = mmTPC0_EML_BUSMON_1_BASE, + [GAUDI_BMON_TPC0_EML_2] = mmTPC0_EML_BUSMON_2_BASE, + [GAUDI_BMON_TPC0_EML_3] = mmTPC0_EML_BUSMON_3_BASE, + [GAUDI_BMON_TPC1_EML_0] = mmTPC1_EML_BUSMON_0_BASE, + [GAUDI_BMON_TPC1_EML_1] = mmTPC1_EML_BUSMON_1_BASE, + [GAUDI_BMON_TPC1_EML_2] = mmTPC1_EML_BUSMON_2_BASE, + [GAUDI_BMON_TPC1_EML_3] = mmTPC1_EML_BUSMON_3_BASE, + [GAUDI_BMON_TPC2_EML_0] = mmTPC2_EML_BUSMON_0_BASE, + [GAUDI_BMON_TPC2_EML_1] = mmTPC2_EML_BUSMON_1_BASE, + [GAUDI_BMON_TPC2_EML_2] = mmTPC2_EML_BUSMON_2_BASE, + [GAUDI_BMON_TPC2_EML_3] = mmTPC2_EML_BUSMON_3_BASE, + [GAUDI_BMON_TPC3_EML_0] = mmTPC3_EML_BUSMON_0_BASE, + [GAUDI_BMON_TPC3_EML_1] = mmTPC3_EML_BUSMON_1_BASE, + [GAUDI_BMON_TPC3_EML_2] = mmTPC3_EML_BUSMON_2_BASE, + [GAUDI_BMON_TPC3_EML_3] = mmTPC3_EML_BUSMON_3_BASE, + [GAUDI_BMON_TPC4_EML_0] = mmTPC4_EML_BUSMON_0_BASE, + [GAUDI_BMON_TPC4_EML_1] = mmTPC4_EML_BUSMON_1_BASE, + [GAUDI_BMON_TPC4_EML_2] = mmTPC4_EML_BUSMON_2_BASE, + [GAUDI_BMON_TPC4_EML_3] = mmTPC4_EML_BUSMON_3_BASE, + [GAUDI_BMON_TPC5_EML_0] = mmTPC5_EML_BUSMON_0_BASE, + [GAUDI_BMON_TPC5_EML_1] = mmTPC5_EML_BUSMON_1_BASE, + [GAUDI_BMON_TPC5_EML_2] = mmTPC5_EML_BUSMON_2_BASE, + [GAUDI_BMON_TPC5_EML_3] = mmTPC5_EML_BUSMON_3_BASE, + [GAUDI_BMON_TPC6_EML_0] = mmTPC6_EML_BUSMON_0_BASE, + [GAUDI_BMON_TPC6_EML_1] = mmTPC6_EML_BUSMON_1_BASE, + [GAUDI_BMON_TPC6_EML_2] = mmTPC6_EML_BUSMON_2_BASE, + [GAUDI_BMON_TPC6_EML_3] = mmTPC6_EML_BUSMON_3_BASE, + [GAUDI_BMON_TPC7_EML_0] = mmTPC7_EML_BUSMON_0_BASE, + [GAUDI_BMON_TPC7_EML_1] = mmTPC7_EML_BUSMON_1_BASE, + [GAUDI_BMON_TPC7_EML_2] = mmTPC7_EML_BUSMON_2_BASE, + [GAUDI_BMON_TPC7_EML_3] = mmTPC7_EML_BUSMON_3_BASE +}; + +static u64 debug_spmu_regs[GAUDI_SPMU_LAST + 1] = { + [GAUDI_SPMU_MME0_ACC] = mmMME0_ACC_SPMU_BASE, + [GAUDI_SPMU_MME0_SBAB] = mmMME0_SBAB_SPMU_BASE, + [GAUDI_SPMU_MME0_CTRL] = mmMME0_CTRL_SPMU_BASE, + [GAUDI_SPMU_MME1_ACC] = mmMME1_ACC_SPMU_BASE, + [GAUDI_SPMU_MME1_SBAB] = mmMME1_SBAB_SPMU_BASE, + [GAUDI_SPMU_MME1_CTRL] = mmMME1_CTRL_SPMU_BASE, + [GAUDI_SPMU_MME2_MME2_ACC] = mmMME2_ACC_SPMU_BASE, + [GAUDI_SPMU_MME2_SBAB] = mmMME2_SBAB_SPMU_BASE, + [GAUDI_SPMU_MME2_CTRL] = mmMME2_CTRL_SPMU_BASE, + [GAUDI_SPMU_MME3_ACC] = mmMME3_ACC_SPMU_BASE, + [GAUDI_SPMU_MME3_SBAB] = mmMME3_SBAB_SPMU_BASE, + [GAUDI_SPMU_MME3_CTRL] = mmMME3_CTRL_SPMU_BASE, + [GAUDI_SPMU_DMA_CH_0_CS] = mmDMA_CH_0_CS_SPMU_BASE, + [GAUDI_SPMU_DMA_CH_1_CS] = mmDMA_CH_1_CS_SPMU_BASE, + [GAUDI_SPMU_DMA_CH_2_CS] = mmDMA_CH_2_CS_SPMU_BASE, + [GAUDI_SPMU_DMA_CH_3_CS] = mmDMA_CH_3_CS_SPMU_BASE, + [GAUDI_SPMU_DMA_CH_4_CS] = mmDMA_CH_4_CS_SPMU_BASE, + [GAUDI_SPMU_DMA_CH_5_CS] = mmDMA_CH_5_CS_SPMU_BASE, + [GAUDI_SPMU_DMA_CH_6_CS] = mmDMA_CH_6_CS_SPMU_BASE, + [GAUDI_SPMU_DMA_CH_7_CS] = mmDMA_CH_7_CS_SPMU_BASE, + [GAUDI_SPMU_PCIE] = mmPCIE_SPMU_BASE, + [GAUDI_SPMU_MMU_CS] = mmMMU_CS_SPMU_BASE, + [GAUDI_SPMU_NIC0_0] = mmSPMU_0_NIC0_DBG_BASE, + [GAUDI_SPMU_NIC0_1] = mmSPMU_1_NIC0_DBG_BASE, + [GAUDI_SPMU_NIC1_0] = mmSPMU_0_NIC1_DBG_BASE, + [GAUDI_SPMU_NIC1_1] = mmSPMU_1_NIC1_DBG_BASE, + [GAUDI_SPMU_NIC2_0] = mmSPMU_0_NIC2_DBG_BASE, + [GAUDI_SPMU_NIC2_1] = mmSPMU_1_NIC2_DBG_BASE, + [GAUDI_SPMU_NIC3_0] = mmSPMU_0_NIC3_DBG_BASE, + [GAUDI_SPMU_NIC3_1] = mmSPMU_1_NIC3_DBG_BASE, + [GAUDI_SPMU_NIC4_0] = mmSPMU_0_NIC4_DBG_BASE, + [GAUDI_SPMU_NIC4_1] = mmSPMU_1_NIC4_DBG_BASE, + [GAUDI_SPMU_TPC0_EML] = mmTPC0_EML_SPMU_BASE, + [GAUDI_SPMU_TPC1_EML] = mmTPC1_EML_SPMU_BASE, + [GAUDI_SPMU_TPC2_EML] = mmTPC2_EML_SPMU_BASE, + [GAUDI_SPMU_TPC3_EML] = mmTPC3_EML_SPMU_BASE, + [GAUDI_SPMU_TPC4_EML] = mmTPC4_EML_SPMU_BASE, + [GAUDI_SPMU_TPC5_EML] = mmTPC5_EML_SPMU_BASE, + [GAUDI_SPMU_TPC6_EML] = mmTPC6_EML_SPMU_BASE, + [GAUDI_SPMU_TPC7_EML] = mmTPC7_EML_SPMU_BASE +}; + +static int gaudi_coresight_timeout(struct hl_device *hdev, u64 addr, + int position, bool up) +{ + int rc; + u32 val; + + rc = hl_poll_timeout( + hdev, + addr, + val, + up ? val & BIT(position) : !(val & BIT(position)), + 1000, + CORESIGHT_TIMEOUT_USEC); + + if (rc) { + dev_err(hdev->dev, + "Timeout while waiting for coresight, addr: 0x%llx, position: %d, up: %d\n", + addr, position, up); + return -EFAULT; + } + + return 0; +} + +static int gaudi_config_stm(struct hl_device *hdev, + struct hl_debug_params *params) +{ + struct hl_debug_params_stm *input; + u64 base_reg; + int rc; + + if (params->reg_idx >= ARRAY_SIZE(debug_stm_regs)) { + dev_err(hdev->dev, "Invalid register index in STM\n"); + return -EINVAL; + } + + base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE; + + WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); + + if (params->enable) { + input = params->input; + + if (!input) + return -EINVAL; + + WREG32(base_reg + 0xE80, 0x80004); + WREG32(base_reg + 0xD64, 7); + WREG32(base_reg + 0xD60, 0); + WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask)); + WREG32(base_reg + 0xD60, 1); + WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask)); + WREG32(base_reg + 0xE70, 0x10); + WREG32(base_reg + 0xE60, 0); + WREG32(base_reg + 0xE00, lower_32_bits(input->sp_mask)); + WREG32(base_reg + 0xEF4, input->id); + WREG32(base_reg + 0xDF4, 0x80); + WREG32(base_reg + 0xE8C, input->frequency); + WREG32(base_reg + 0xE90, 0x7FF); + + /* SW-2176 - SW WA for HW bug */ + if ((CFG_BASE + base_reg) >= mmDMA_CH_0_CS_STM_BASE && + (CFG_BASE + base_reg) <= mmDMA_CH_7_CS_STM_BASE) { + + WREG32(base_reg + 0xE68, 0xffff8005); + WREG32(base_reg + 0xE6C, 0x0); + } + + WREG32(base_reg + 0xE80, 0x27 | (input->id << 16)); + } else { + WREG32(base_reg + 0xE80, 4); + WREG32(base_reg + 0xD64, 0); + WREG32(base_reg + 0xD60, 1); + WREG32(base_reg + 0xD00, 0); + WREG32(base_reg + 0xD20, 0); + WREG32(base_reg + 0xD60, 0); + WREG32(base_reg + 0xE20, 0); + WREG32(base_reg + 0xE00, 0); + WREG32(base_reg + 0xDF4, 0x80); + WREG32(base_reg + 0xE70, 0); + WREG32(base_reg + 0xE60, 0); + WREG32(base_reg + 0xE64, 0); + WREG32(base_reg + 0xE8C, 0); + + rc = gaudi_coresight_timeout(hdev, base_reg + 0xE80, 23, false); + if (rc) { + dev_err(hdev->dev, + "Failed to disable STM on timeout, error %d\n", + rc); + return rc; + } + + WREG32(base_reg + 0xE80, 4); + } + + return 0; +} + +static int gaudi_config_etf(struct hl_device *hdev, + struct hl_debug_params *params) +{ + struct hl_debug_params_etf *input; + u64 base_reg; + u32 val; + int rc; + + if (params->reg_idx >= ARRAY_SIZE(debug_etf_regs)) { + dev_err(hdev->dev, "Invalid register index in ETF\n"); + return -EINVAL; + } + + base_reg = debug_etf_regs[params->reg_idx] - CFG_BASE; + + WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); + + val = RREG32(base_reg + 0x304); + val |= 0x1000; + WREG32(base_reg + 0x304, val); + val |= 0x40; + WREG32(base_reg + 0x304, val); + + rc = gaudi_coresight_timeout(hdev, base_reg + 0x304, 6, false); + if (rc) { + dev_err(hdev->dev, + "Failed to %s ETF on timeout, error %d\n", + params->enable ? "enable" : "disable", rc); + return rc; + } + + rc = gaudi_coresight_timeout(hdev, base_reg + 0xC, 2, true); + if (rc) { + dev_err(hdev->dev, + "Failed to %s ETF on timeout, error %d\n", + params->enable ? "enable" : "disable", rc); + return rc; + } + + WREG32(base_reg + 0x20, 0); + + if (params->enable) { + input = params->input; + + if (!input) + return -EINVAL; + + WREG32(base_reg + 0x34, 0x3FFC); + WREG32(base_reg + 0x28, input->sink_mode); + WREG32(base_reg + 0x304, 0x4001); + WREG32(base_reg + 0x308, 0xA); + WREG32(base_reg + 0x20, 1); + } else { + WREG32(base_reg + 0x34, 0); + WREG32(base_reg + 0x28, 0); + WREG32(base_reg + 0x304, 0); + } + + return 0; +} + +static bool gaudi_etr_validate_address(struct hl_device *hdev, u64 addr, + u32 size, bool *is_host) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct gaudi_device *gaudi = hdev->asic_specific; + + /* maximum address length is 50 bits */ + if (addr >> 50) { + dev_err(hdev->dev, + "ETR buffer address shouldn't exceed 50 bits\n"); + return false; + } + + /* PMMU and HPMMU addresses are equal, check only one of them */ + if ((gaudi->hw_cap_initialized & HW_CAP_MMU) && + hl_mem_area_inside_range(addr, size, + prop->pmmu.start_addr, + prop->pmmu.end_addr)) { + *is_host = true; + return true; + } + + if (hl_mem_area_inside_range(addr, size, + prop->dram_user_base_address, + prop->dram_end_address)) + return true; + + if (hl_mem_area_inside_range(addr, size, + prop->sram_user_base_address, + prop->sram_end_address)) + return true; + + if (!(gaudi->hw_cap_initialized & HW_CAP_MMU)) + dev_err(hdev->dev, "ETR buffer should be in SRAM/DRAM\n"); + + return false; +} + +static int gaudi_config_etr(struct hl_device *hdev, + struct hl_debug_params *params) +{ + struct hl_debug_params_etr *input; + u64 msb; + u32 val; + int rc; + + WREG32(mmPSOC_ETR_LAR, CORESIGHT_UNLOCK); + + val = RREG32(mmPSOC_ETR_FFCR); + val |= 0x1000; + WREG32(mmPSOC_ETR_FFCR, val); + val |= 0x40; + WREG32(mmPSOC_ETR_FFCR, val); + + rc = gaudi_coresight_timeout(hdev, mmPSOC_ETR_FFCR, 6, false); + if (rc) { + dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n", + params->enable ? "enable" : "disable", rc); + return rc; + } + + rc = gaudi_coresight_timeout(hdev, mmPSOC_ETR_STS, 2, true); + if (rc) { + dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n", + params->enable ? "enable" : "disable", rc); + return rc; + } + + WREG32(mmPSOC_ETR_CTL, 0); + + if (params->enable) { + bool is_host = false; + + input = params->input; + + if (!input) + return -EINVAL; + + if (input->buffer_size == 0) { + dev_err(hdev->dev, + "ETR buffer size should be bigger than 0\n"); + return -EINVAL; + } + + if (!gaudi_etr_validate_address(hdev, + input->buffer_address, input->buffer_size, + &is_host)) { + dev_err(hdev->dev, "ETR buffer address is invalid\n"); + return -EINVAL; + } + + msb = upper_32_bits(input->buffer_address) >> 8; + msb &= PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_MASK; + WREG32(mmPSOC_GLOBAL_CONF_TRACE_ADDR, msb); + + WREG32(mmPSOC_ETR_BUFWM, 0x3FFC); + WREG32(mmPSOC_ETR_RSZ, input->buffer_size); + WREG32(mmPSOC_ETR_MODE, input->sink_mode); + /* Workaround for H3 #HW-2075 bug: use small data chunks */ + WREG32(mmPSOC_ETR_AXICTL, (is_host ? 0 : 0x700) | + PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT); + WREG32(mmPSOC_ETR_DBALO, + lower_32_bits(input->buffer_address)); + WREG32(mmPSOC_ETR_DBAHI, + upper_32_bits(input->buffer_address)); + WREG32(mmPSOC_ETR_FFCR, 3); + WREG32(mmPSOC_ETR_PSCR, 0xA); + WREG32(mmPSOC_ETR_CTL, 1); + } else { + WREG32(mmPSOC_ETR_BUFWM, 0); + WREG32(mmPSOC_ETR_RSZ, 0x400); + WREG32(mmPSOC_ETR_DBALO, 0); + WREG32(mmPSOC_ETR_DBAHI, 0); + WREG32(mmPSOC_ETR_PSCR, 0); + WREG32(mmPSOC_ETR_MODE, 0); + WREG32(mmPSOC_ETR_FFCR, 0); + + if (params->output_size >= sizeof(u64)) { + u32 rwp, rwphi; + + /* + * The trace buffer address is 50 bits wide. The end of + * the buffer is set in the RWP register (lower 32 + * bits), and in the RWPHI register (upper 8 bits). + * The 10 msb of the 50-bit address are stored in a + * global configuration register. + */ + rwp = RREG32(mmPSOC_ETR_RWP); + rwphi = RREG32(mmPSOC_ETR_RWPHI) & 0xff; + msb = RREG32(mmPSOC_GLOBAL_CONF_TRACE_ADDR) & + PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_MASK; + *(u64 *) params->output = ((u64) msb << 40) | + ((u64) rwphi << 32) | rwp; + } + } + + return 0; +} + +static int gaudi_config_funnel(struct hl_device *hdev, + struct hl_debug_params *params) +{ + u64 base_reg; + + if (params->reg_idx >= ARRAY_SIZE(debug_funnel_regs)) { + dev_err(hdev->dev, "Invalid register index in FUNNEL\n"); + return -EINVAL; + } + + base_reg = debug_funnel_regs[params->reg_idx] - CFG_BASE; + + WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); + + WREG32(base_reg, params->enable ? 0x33F : 0); + + return 0; +} + +static int gaudi_config_bmon(struct hl_device *hdev, + struct hl_debug_params *params) +{ + struct hl_debug_params_bmon *input; + u64 base_reg; + + if (params->reg_idx >= ARRAY_SIZE(debug_bmon_regs)) { + dev_err(hdev->dev, "Invalid register index in BMON\n"); + return -EINVAL; + } + + base_reg = debug_bmon_regs[params->reg_idx] - CFG_BASE; + + WREG32(base_reg + 0x104, 1); + + if (params->enable) { + input = params->input; + + if (!input) + return -EINVAL; + + WREG32(base_reg + 0x200, lower_32_bits(input->start_addr0)); + WREG32(base_reg + 0x204, upper_32_bits(input->start_addr0)); + WREG32(base_reg + 0x208, lower_32_bits(input->addr_mask0)); + WREG32(base_reg + 0x20C, upper_32_bits(input->addr_mask0)); + WREG32(base_reg + 0x240, lower_32_bits(input->start_addr1)); + WREG32(base_reg + 0x244, upper_32_bits(input->start_addr1)); + WREG32(base_reg + 0x248, lower_32_bits(input->addr_mask1)); + WREG32(base_reg + 0x24C, upper_32_bits(input->addr_mask1)); + WREG32(base_reg + 0x224, 0); + WREG32(base_reg + 0x234, 0); + WREG32(base_reg + 0x30C, input->bw_win); + WREG32(base_reg + 0x308, input->win_capture); + WREG32(base_reg + 0x700, 0xA000B00 | (input->id << 12)); + WREG32(base_reg + 0x708, 0xA000A00 | (input->id << 12)); + WREG32(base_reg + 0x70C, 0xA000C00 | (input->id << 12)); + WREG32(base_reg + 0x100, 0x11); + WREG32(base_reg + 0x304, 0x1); + } else { + WREG32(base_reg + 0x200, 0); + WREG32(base_reg + 0x204, 0); + WREG32(base_reg + 0x208, 0xFFFFFFFF); + WREG32(base_reg + 0x20C, 0xFFFFFFFF); + WREG32(base_reg + 0x240, 0); + WREG32(base_reg + 0x244, 0); + WREG32(base_reg + 0x248, 0xFFFFFFFF); + WREG32(base_reg + 0x24C, 0xFFFFFFFF); + WREG32(base_reg + 0x224, 0xFFFFFFFF); + WREG32(base_reg + 0x234, 0x1070F); + WREG32(base_reg + 0x30C, 0); + WREG32(base_reg + 0x308, 0xFFFF); + WREG32(base_reg + 0x700, 0xA000B00); + WREG32(base_reg + 0x708, 0xA000A00); + WREG32(base_reg + 0x70C, 0xA000C00); + WREG32(base_reg + 0x100, 1); + WREG32(base_reg + 0x304, 0); + WREG32(base_reg + 0x104, 0); + } + + return 0; +} + +static int gaudi_config_spmu(struct hl_device *hdev, + struct hl_debug_params *params) +{ + u64 base_reg; + struct hl_debug_params_spmu *input = params->input; + u64 *output; + u32 output_arr_len; + u32 events_num; + u32 overflow_idx; + u32 cycle_cnt_idx; + int i; + + if (params->reg_idx >= ARRAY_SIZE(debug_spmu_regs)) { + dev_err(hdev->dev, "Invalid register index in SPMU\n"); + return -EINVAL; + } + + base_reg = debug_spmu_regs[params->reg_idx] - CFG_BASE; + + if (params->enable) { + input = params->input; + + if (!input) + return -EINVAL; + + if (input->event_types_num < 3) { + dev_err(hdev->dev, + "not enough event types values for SPMU enable\n"); + return -EINVAL; + } + + if (input->event_types_num > SPMU_MAX_COUNTERS) { + dev_err(hdev->dev, + "too many event types values for SPMU enable\n"); + return -EINVAL; + } + + WREG32(base_reg + 0xE04, 0x41013046); + WREG32(base_reg + 0xE04, 0x41013040); + + for (i = 0 ; i < input->event_types_num ; i++) + WREG32(base_reg + SPMU_EVENT_TYPES_OFFSET + i * 4, + input->event_types[i]); + + WREG32(base_reg + 0xE04, 0x41013041); + WREG32(base_reg + 0xC00, 0x8000003F); + } else { + output = params->output; + output_arr_len = params->output_size / 8; + events_num = output_arr_len - 2; + overflow_idx = output_arr_len - 2; + cycle_cnt_idx = output_arr_len - 1; + + if (!output) + return -EINVAL; + + if (output_arr_len < 3) { + dev_err(hdev->dev, + "not enough values for SPMU disable\n"); + return -EINVAL; + } + + if (events_num > SPMU_MAX_COUNTERS) { + dev_err(hdev->dev, + "too many events values for SPMU disable\n"); + return -EINVAL; + } + + WREG32(base_reg + 0xE04, 0x41013040); + + for (i = 0 ; i < events_num ; i++) + output[i] = RREG32(base_reg + i * 8); + + output[overflow_idx] = RREG32(base_reg + 0xCC0); + + output[cycle_cnt_idx] = RREG32(base_reg + 0xFC); + output[cycle_cnt_idx] <<= 32; + output[cycle_cnt_idx] |= RREG32(base_reg + 0xF8); + + WREG32(base_reg + 0xCC0, 0); + } + + return 0; +} + +int gaudi_debug_coresight(struct hl_device *hdev, void *data) +{ + struct hl_debug_params *params = data; + int rc = 0; + + switch (params->op) { + case HL_DEBUG_OP_STM: + rc = gaudi_config_stm(hdev, params); + break; + case HL_DEBUG_OP_ETF: + rc = gaudi_config_etf(hdev, params); + break; + case HL_DEBUG_OP_ETR: + rc = gaudi_config_etr(hdev, params); + break; + case HL_DEBUG_OP_FUNNEL: + rc = gaudi_config_funnel(hdev, params); + break; + case HL_DEBUG_OP_BMON: + rc = gaudi_config_bmon(hdev, params); + break; + case HL_DEBUG_OP_SPMU: + rc = gaudi_config_spmu(hdev, params); + break; + case HL_DEBUG_OP_TIMESTAMP: + /* Do nothing as this opcode is deprecated */ + break; + + default: + dev_err(hdev->dev, "Unknown coresight id %d\n", params->op); + return -EINVAL; + } + + /* Perform read from the device to flush all configuration */ + RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG); + + return rc; +} + +void gaudi_halt_coresight(struct hl_device *hdev) +{ + struct hl_debug_params params = {}; + int i, rc; + + for (i = GAUDI_ETF_FIRST ; i <= GAUDI_ETF_LAST ; i++) { + params.reg_idx = i; + rc = gaudi_config_etf(hdev, ¶ms); + if (rc) + dev_err(hdev->dev, "halt ETF failed, %d/%d\n", rc, i); + } + + rc = gaudi_config_etr(hdev, ¶ms); + if (rc) + dev_err(hdev->dev, "halt ETR failed, %d\n", rc); +} diff --git a/drivers/misc/habanalabs/gaudi/gaudi_hwmgr.c b/drivers/misc/habanalabs/gaudi/gaudi_hwmgr.c new file mode 100644 index 000000000000..6dd2c2a1cd70 --- /dev/null +++ b/drivers/misc/habanalabs/gaudi/gaudi_hwmgr.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + */ + +#include "gaudiP.h" +#include "include/gaudi/gaudi_fw_if.h" + +void gaudi_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (freq == PLL_LAST) + hl_set_frequency(hdev, MME_PLL, gaudi->max_freq_value); +} + +int gaudi_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk) +{ + long value; + + if (hl_device_disabled_or_in_reset(hdev)) + return -ENODEV; + + value = hl_get_frequency(hdev, MME_PLL, false); + + if (value < 0) { + dev_err(hdev->dev, "Failed to retrieve device max clock %ld\n", + value); + return value; + } + + *max_clk = (value / 1000 / 1000); + + value = hl_get_frequency(hdev, MME_PLL, true); + + if (value < 0) { + dev_err(hdev->dev, + "Failed to retrieve device current clock %ld\n", + value); + return value; + } + + *cur_clk = (value / 1000 / 1000); + + return 0; +} + +static ssize_t clk_max_freq_mhz_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + struct gaudi_device *gaudi = hdev->asic_specific; + long value; + + if (hl_device_disabled_or_in_reset(hdev)) + return -ENODEV; + + value = hl_get_frequency(hdev, MME_PLL, false); + + gaudi->max_freq_value = value; + + return sprintf(buf, "%lu\n", (value / 1000 / 1000)); +} + +static ssize_t clk_max_freq_mhz_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + struct gaudi_device *gaudi = hdev->asic_specific; + int rc; + u64 value; + + if (hl_device_disabled_or_in_reset(hdev)) { + count = -ENODEV; + goto fail; + } + + rc = kstrtoull(buf, 0, &value); + if (rc) { + count = -EINVAL; + goto fail; + } + + gaudi->max_freq_value = value * 1000 * 1000; + + hl_set_frequency(hdev, MME_PLL, gaudi->max_freq_value); + +fail: + return count; +} + +static ssize_t clk_cur_freq_mhz_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + long value; + + if (hl_device_disabled_or_in_reset(hdev)) + return -ENODEV; + + value = hl_get_frequency(hdev, MME_PLL, true); + + return sprintf(buf, "%lu\n", (value / 1000 / 1000)); +} + +static DEVICE_ATTR_RW(clk_max_freq_mhz); +static DEVICE_ATTR_RO(clk_cur_freq_mhz); + +static struct attribute *gaudi_dev_attrs[] = { + &dev_attr_clk_max_freq_mhz.attr, + &dev_attr_clk_cur_freq_mhz.attr, + NULL, +}; + +void gaudi_add_device_attr(struct hl_device *hdev, + struct attribute_group *dev_attr_grp) +{ + dev_attr_grp->attrs = gaudi_dev_attrs; +} diff --git a/drivers/misc/habanalabs/gaudi/gaudi_security.c b/drivers/misc/habanalabs/gaudi/gaudi_security.c new file mode 100644 index 000000000000..6a351e31fa6a --- /dev/null +++ b/drivers/misc/habanalabs/gaudi/gaudi_security.c @@ -0,0 +1,9090 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + */ + +#include "gaudiP.h" +#include "include/gaudi/asic_reg/gaudi_regs.h" + +#define GAUDI_NUMBER_OF_RR_REGS 24 +#define GAUDI_NUMBER_OF_LBW_RANGES 12 + +static u64 gaudi_rr_lbw_hit_aw_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DMA0_HIT_WPROT, + mmDMA_IF_W_S_DMA1_HIT_WPROT, + mmDMA_IF_E_S_DMA0_HIT_WPROT, + mmDMA_IF_E_S_DMA1_HIT_WPROT, + mmDMA_IF_W_N_DMA0_HIT_WPROT, + mmDMA_IF_W_N_DMA1_HIT_WPROT, + mmDMA_IF_E_N_DMA0_HIT_WPROT, + mmDMA_IF_E_N_DMA1_HIT_WPROT, + mmSIF_RTR_0_LBW_RANGE_PROT_HIT_AW, + mmSIF_RTR_1_LBW_RANGE_PROT_HIT_AW, + mmSIF_RTR_2_LBW_RANGE_PROT_HIT_AW, + mmSIF_RTR_3_LBW_RANGE_PROT_HIT_AW, + mmSIF_RTR_4_LBW_RANGE_PROT_HIT_AW, + mmSIF_RTR_5_LBW_RANGE_PROT_HIT_AW, + mmSIF_RTR_6_LBW_RANGE_PROT_HIT_AW, + mmSIF_RTR_7_LBW_RANGE_PROT_HIT_AW, + mmNIF_RTR_0_LBW_RANGE_PROT_HIT_AW, + mmNIF_RTR_1_LBW_RANGE_PROT_HIT_AW, + mmNIF_RTR_2_LBW_RANGE_PROT_HIT_AW, + mmNIF_RTR_3_LBW_RANGE_PROT_HIT_AW, + mmNIF_RTR_4_LBW_RANGE_PROT_HIT_AW, + mmNIF_RTR_5_LBW_RANGE_PROT_HIT_AW, + mmNIF_RTR_6_LBW_RANGE_PROT_HIT_AW, + mmNIF_RTR_7_LBW_RANGE_PROT_HIT_AW, +}; + +static u64 gaudi_rr_lbw_hit_ar_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DMA0_HIT_RPROT, + mmDMA_IF_W_S_DMA1_HIT_RPROT, + mmDMA_IF_E_S_DMA0_HIT_RPROT, + mmDMA_IF_E_S_DMA1_HIT_RPROT, + mmDMA_IF_W_N_DMA0_HIT_RPROT, + mmDMA_IF_W_N_DMA1_HIT_RPROT, + mmDMA_IF_E_N_DMA0_HIT_RPROT, + mmDMA_IF_E_N_DMA1_HIT_RPROT, + mmSIF_RTR_0_LBW_RANGE_PROT_HIT_AR, + mmSIF_RTR_1_LBW_RANGE_PROT_HIT_AR, + mmSIF_RTR_2_LBW_RANGE_PROT_HIT_AR, + mmSIF_RTR_3_LBW_RANGE_PROT_HIT_AR, + mmSIF_RTR_4_LBW_RANGE_PROT_HIT_AR, + mmSIF_RTR_5_LBW_RANGE_PROT_HIT_AR, + mmSIF_RTR_6_LBW_RANGE_PROT_HIT_AR, + mmSIF_RTR_7_LBW_RANGE_PROT_HIT_AR, + mmNIF_RTR_0_LBW_RANGE_PROT_HIT_AR, + mmNIF_RTR_1_LBW_RANGE_PROT_HIT_AR, + mmNIF_RTR_2_LBW_RANGE_PROT_HIT_AR, + mmNIF_RTR_3_LBW_RANGE_PROT_HIT_AR, + mmNIF_RTR_4_LBW_RANGE_PROT_HIT_AR, + mmNIF_RTR_5_LBW_RANGE_PROT_HIT_AR, + mmNIF_RTR_6_LBW_RANGE_PROT_HIT_AR, + mmNIF_RTR_7_LBW_RANGE_PROT_HIT_AR, +}; + +static u64 gaudi_rr_lbw_min_aw_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DMA0_MIN_WPROT_0, + mmDMA_IF_W_S_DMA1_MIN_WPROT_0, + mmDMA_IF_E_S_DMA0_MIN_WPROT_0, + mmDMA_IF_E_S_DMA1_MIN_WPROT_0, + mmDMA_IF_W_N_DMA0_MIN_WPROT_0, + mmDMA_IF_W_N_DMA1_MIN_WPROT_0, + mmDMA_IF_E_N_DMA0_MIN_WPROT_0, + mmDMA_IF_E_N_DMA1_MIN_WPROT_0, + mmSIF_RTR_0_LBW_RANGE_PROT_MIN_AW_0, + mmSIF_RTR_1_LBW_RANGE_PROT_MIN_AW_0, + mmSIF_RTR_2_LBW_RANGE_PROT_MIN_AW_0, + mmSIF_RTR_3_LBW_RANGE_PROT_MIN_AW_0, + mmSIF_RTR_4_LBW_RANGE_PROT_MIN_AW_0, + mmSIF_RTR_5_LBW_RANGE_PROT_MIN_AW_0, + mmSIF_RTR_6_LBW_RANGE_PROT_MIN_AW_0, + mmSIF_RTR_7_LBW_RANGE_PROT_MIN_AW_0, + mmNIF_RTR_0_LBW_RANGE_PROT_MIN_AW_0, + mmNIF_RTR_1_LBW_RANGE_PROT_MIN_AW_0, + mmNIF_RTR_2_LBW_RANGE_PROT_MIN_AW_0, + mmNIF_RTR_3_LBW_RANGE_PROT_MIN_AW_0, + mmNIF_RTR_4_LBW_RANGE_PROT_MIN_AW_0, + mmNIF_RTR_5_LBW_RANGE_PROT_MIN_AW_0, + mmNIF_RTR_6_LBW_RANGE_PROT_MIN_AW_0, + mmNIF_RTR_7_LBW_RANGE_PROT_MIN_AW_0, +}; + +static u64 gaudi_rr_lbw_max_aw_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DMA0_MAX_WPROT_0, + mmDMA_IF_W_S_DMA1_MAX_WPROT_0, + mmDMA_IF_E_S_DMA0_MAX_WPROT_0, + mmDMA_IF_E_S_DMA1_MAX_WPROT_0, + mmDMA_IF_W_N_DMA0_MAX_WPROT_0, + mmDMA_IF_W_N_DMA1_MAX_WPROT_0, + mmDMA_IF_E_N_DMA0_MAX_WPROT_0, + mmDMA_IF_E_N_DMA1_MAX_WPROT_0, + mmSIF_RTR_0_LBW_RANGE_PROT_MAX_AW_0, + mmSIF_RTR_1_LBW_RANGE_PROT_MAX_AW_0, + mmSIF_RTR_2_LBW_RANGE_PROT_MAX_AW_0, + mmSIF_RTR_3_LBW_RANGE_PROT_MAX_AW_0, + mmSIF_RTR_4_LBW_RANGE_PROT_MAX_AW_0, + mmSIF_RTR_5_LBW_RANGE_PROT_MAX_AW_0, + mmSIF_RTR_6_LBW_RANGE_PROT_MAX_AW_0, + mmSIF_RTR_7_LBW_RANGE_PROT_MAX_AW_0, + mmNIF_RTR_0_LBW_RANGE_PROT_MAX_AW_0, + mmNIF_RTR_1_LBW_RANGE_PROT_MAX_AW_0, + mmNIF_RTR_2_LBW_RANGE_PROT_MAX_AW_0, + mmNIF_RTR_3_LBW_RANGE_PROT_MAX_AW_0, + mmNIF_RTR_4_LBW_RANGE_PROT_MAX_AW_0, + mmNIF_RTR_5_LBW_RANGE_PROT_MAX_AW_0, + mmNIF_RTR_6_LBW_RANGE_PROT_MAX_AW_0, + mmNIF_RTR_7_LBW_RANGE_PROT_MAX_AW_0, +}; + +static u64 gaudi_rr_lbw_min_ar_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DMA0_MIN_RPROT_0, + mmDMA_IF_W_S_DMA1_MIN_RPROT_0, + mmDMA_IF_E_S_DMA0_MIN_RPROT_0, + mmDMA_IF_E_S_DMA1_MIN_RPROT_0, + mmDMA_IF_W_N_DMA0_MIN_RPROT_0, + mmDMA_IF_W_N_DMA1_MIN_RPROT_0, + mmDMA_IF_E_N_DMA0_MIN_RPROT_0, + mmDMA_IF_E_N_DMA1_MIN_RPROT_0, + mmSIF_RTR_0_LBW_RANGE_PROT_MIN_AR_0, + mmSIF_RTR_1_LBW_RANGE_PROT_MIN_AR_0, + mmSIF_RTR_2_LBW_RANGE_PROT_MIN_AR_0, + mmSIF_RTR_3_LBW_RANGE_PROT_MIN_AR_0, + mmSIF_RTR_4_LBW_RANGE_PROT_MIN_AR_0, + mmSIF_RTR_5_LBW_RANGE_PROT_MIN_AR_0, + mmSIF_RTR_6_LBW_RANGE_PROT_MIN_AR_0, + mmSIF_RTR_7_LBW_RANGE_PROT_MIN_AR_0, + mmNIF_RTR_0_LBW_RANGE_PROT_MIN_AR_0, + mmNIF_RTR_1_LBW_RANGE_PROT_MIN_AR_0, + mmNIF_RTR_2_LBW_RANGE_PROT_MIN_AR_0, + mmNIF_RTR_3_LBW_RANGE_PROT_MIN_AR_0, + mmNIF_RTR_4_LBW_RANGE_PROT_MIN_AR_0, + mmNIF_RTR_5_LBW_RANGE_PROT_MIN_AR_0, + mmNIF_RTR_6_LBW_RANGE_PROT_MIN_AR_0, + mmNIF_RTR_7_LBW_RANGE_PROT_MIN_AR_0, +}; + +static u64 gaudi_rr_lbw_max_ar_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DMA0_MAX_RPROT_0, + mmDMA_IF_W_S_DMA1_MAX_RPROT_0, + mmDMA_IF_E_S_DMA0_MAX_RPROT_0, + mmDMA_IF_E_S_DMA1_MAX_RPROT_0, + mmDMA_IF_W_N_DMA0_MAX_RPROT_0, + mmDMA_IF_W_N_DMA1_MAX_RPROT_0, + mmDMA_IF_E_N_DMA0_MAX_RPROT_0, + mmDMA_IF_E_N_DMA1_MAX_RPROT_0, + mmSIF_RTR_0_LBW_RANGE_PROT_MAX_AR_0, + mmSIF_RTR_1_LBW_RANGE_PROT_MAX_AR_0, + mmSIF_RTR_2_LBW_RANGE_PROT_MAX_AR_0, + mmSIF_RTR_3_LBW_RANGE_PROT_MAX_AR_0, + mmSIF_RTR_4_LBW_RANGE_PROT_MAX_AR_0, + mmSIF_RTR_5_LBW_RANGE_PROT_MAX_AR_0, + mmSIF_RTR_6_LBW_RANGE_PROT_MAX_AR_0, + mmSIF_RTR_7_LBW_RANGE_PROT_MAX_AR_0, + mmNIF_RTR_0_LBW_RANGE_PROT_MAX_AR_0, + mmNIF_RTR_1_LBW_RANGE_PROT_MAX_AR_0, + mmNIF_RTR_2_LBW_RANGE_PROT_MAX_AR_0, + mmNIF_RTR_3_LBW_RANGE_PROT_MAX_AR_0, + mmNIF_RTR_4_LBW_RANGE_PROT_MAX_AR_0, + mmNIF_RTR_5_LBW_RANGE_PROT_MAX_AR_0, + mmNIF_RTR_6_LBW_RANGE_PROT_MAX_AR_0, + mmNIF_RTR_7_LBW_RANGE_PROT_MAX_AR_0, +}; + +static u64 gaudi_rr_hbw_hit_aw_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_HIT_AW, + mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_HIT_AW, + mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_HIT_AW, + mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_HIT_AW, + mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_HIT_AW, + mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_HIT_AW, + mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_HIT_AW, + mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_HIT_AW, + mmSIF_RTR_CTRL_0_RANGE_SEC_HIT_AW, + mmSIF_RTR_CTRL_1_RANGE_SEC_HIT_AW, + mmSIF_RTR_CTRL_2_RANGE_SEC_HIT_AW, + mmSIF_RTR_CTRL_3_RANGE_SEC_HIT_AW, + mmSIF_RTR_CTRL_4_RANGE_SEC_HIT_AW, + mmSIF_RTR_CTRL_5_RANGE_SEC_HIT_AW, + mmSIF_RTR_CTRL_6_RANGE_SEC_HIT_AW, + mmSIF_RTR_CTRL_7_RANGE_SEC_HIT_AW, + mmNIF_RTR_CTRL_0_RANGE_SEC_HIT_AW, + mmNIF_RTR_CTRL_1_RANGE_SEC_HIT_AW, + mmNIF_RTR_CTRL_2_RANGE_SEC_HIT_AW, + mmNIF_RTR_CTRL_3_RANGE_SEC_HIT_AW, + mmNIF_RTR_CTRL_4_RANGE_SEC_HIT_AW, + mmNIF_RTR_CTRL_5_RANGE_SEC_HIT_AW, + mmNIF_RTR_CTRL_6_RANGE_SEC_HIT_AW, + mmNIF_RTR_CTRL_7_RANGE_SEC_HIT_AW +}; + +static u64 gaudi_rr_hbw_hit_ar_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_HIT_AR, + mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_HIT_AR, + mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_HIT_AR, + mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_HIT_AR, + mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_HIT_AR, + mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_HIT_AR, + mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_HIT_AR, + mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_HIT_AR, + mmSIF_RTR_CTRL_0_RANGE_SEC_HIT_AR, + mmSIF_RTR_CTRL_1_RANGE_SEC_HIT_AR, + mmSIF_RTR_CTRL_2_RANGE_SEC_HIT_AR, + mmSIF_RTR_CTRL_3_RANGE_SEC_HIT_AR, + mmSIF_RTR_CTRL_4_RANGE_SEC_HIT_AR, + mmSIF_RTR_CTRL_5_RANGE_SEC_HIT_AR, + mmSIF_RTR_CTRL_6_RANGE_SEC_HIT_AR, + mmSIF_RTR_CTRL_7_RANGE_SEC_HIT_AR, + mmNIF_RTR_CTRL_0_RANGE_SEC_HIT_AR, + mmNIF_RTR_CTRL_1_RANGE_SEC_HIT_AR, + mmNIF_RTR_CTRL_2_RANGE_SEC_HIT_AR, + mmNIF_RTR_CTRL_3_RANGE_SEC_HIT_AR, + mmNIF_RTR_CTRL_4_RANGE_SEC_HIT_AR, + mmNIF_RTR_CTRL_5_RANGE_SEC_HIT_AR, + mmNIF_RTR_CTRL_6_RANGE_SEC_HIT_AR, + mmNIF_RTR_CTRL_7_RANGE_SEC_HIT_AR +}; + +static u64 gaudi_rr_hbw_base_low_aw_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0, + mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0, + mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0, + mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0, + mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0, + mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0, + mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0, + mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0, + mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_0, + mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_0, + mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_0, + mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_0, + mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_0, + mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_0, + mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_0, + mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_0, + mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_0, + mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_0, + mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_0, + mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_0, + mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_0, + mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_0, + mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_0, + mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_0 +}; + +static u64 gaudi_rr_hbw_base_high_aw_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0, + mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0, + mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0, + mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0, + mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0, + mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0, + mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0, + mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0, + mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_0, + mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_0, + mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_0, + mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_0, + mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_0, + mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_0, + mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_0, + mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_0, + mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_0, + mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_0, + mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_0, + mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_0, + mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_0, + mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_0, + mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_0, + mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_0 +}; + +static u64 gaudi_rr_hbw_mask_low_aw_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0, + mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0, + mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0, + mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0, + mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0, + mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0, + mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0, + mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0, + mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_0, + mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_0, + mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_0, + mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_0, + mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_0, + mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_0, + mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_0, + mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_0, + mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_0, + mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_0, + mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_0, + mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_0, + mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_0, + mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_0, + mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_0, + mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_0 +}; + +static u64 gaudi_rr_hbw_mask_high_aw_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0, + mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0, + mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0, + mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0, + mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0, + mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0, + mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0, + mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0, + mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_0, + mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_0, + mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_0, + mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_0, + mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_0, + mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_0, + mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_0, + mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_0, + mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_0, + mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_0, + mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_0, + mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_0, + mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_0, + mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_0, + mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_0, + mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_0 +}; + +static u64 gaudi_rr_hbw_base_low_ar_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0, + mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0, + mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0, + mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0, + mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0, + mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0, + mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0, + mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0, + mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_0, + mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_0, + mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_0, + mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_0, + mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_0, + mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_0, + mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_0, + mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_0, + mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_0, + mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_0, + mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_0, + mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_0, + mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_0, + mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_0, + mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_0, + mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_0 +}; + +static u64 gaudi_rr_hbw_base_high_ar_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0, + mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0, + mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0, + mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0, + mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0, + mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0, + mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0, + mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0, + mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_0, + mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_0, + mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_0, + mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_0, + mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_0, + mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_0, + mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_0, + mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_0, + mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_0, + mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_0, + mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_0, + mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_0, + mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_0, + mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_0, + mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_0, + mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_0 +}; + +static u64 gaudi_rr_hbw_mask_low_ar_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0, + mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0, + mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0, + mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0, + mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0, + mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0, + mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0, + mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0, + mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_0, + mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_0, + mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_0, + mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_0, + mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_0, + mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_0, + mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_0, + mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_0, + mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_0, + mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_0, + mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_0, + mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_0, + mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_0, + mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_0, + mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_0, + mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_0 +}; + +static u64 gaudi_rr_hbw_mask_high_ar_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0, + mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0, + mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0, + mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0, + mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0, + mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0, + mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0, + mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0, + mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_0, + mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_0, + mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_0, + mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_0, + mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_0, + mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_0, + mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_0, + mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_0, + mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_0, + mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_0, + mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_0, + mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_0, + mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_0, + mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_0, + mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_0, + mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_0 +}; + +/** + * gaudi_set_block_as_protected - set the given block as protected + * + * @hdev: pointer to hl_device structure + * @block: block base address + * + */ +static void gaudi_pb_set_block(struct hl_device *hdev, u64 base) +{ + u32 pb_addr = base - CFG_BASE + PROT_BITS_OFFS; + + while (pb_addr & 0xFFF) { + WREG32(pb_addr, 0); + pb_addr += 4; + } +} + +static void gaudi_init_mme_protection_bits(struct hl_device *hdev) +{ + u32 pb_addr, mask; + u8 word_offset; + + gaudi_pb_set_block(hdev, mmMME0_ACC_BASE); + gaudi_pb_set_block(hdev, mmMME0_SBAB_BASE); + gaudi_pb_set_block(hdev, mmMME0_PRTN_BASE); + gaudi_pb_set_block(hdev, mmMME1_ACC_BASE); + gaudi_pb_set_block(hdev, mmMME1_SBAB_BASE); + gaudi_pb_set_block(hdev, mmMME1_PRTN_BASE); + gaudi_pb_set_block(hdev, mmMME2_ACC_BASE); + gaudi_pb_set_block(hdev, mmMME2_SBAB_BASE); + gaudi_pb_set_block(hdev, mmMME2_PRTN_BASE); + gaudi_pb_set_block(hdev, mmMME3_ACC_BASE); + gaudi_pb_set_block(hdev, mmMME3_SBAB_BASE); + gaudi_pb_set_block(hdev, mmMME3_PRTN_BASE); + + WREG32(mmMME0_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmMME1_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmMME2_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmMME3_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + + WREG32(mmMME0_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmMME2_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + + pb_addr = (mmMME0_CTRL_RESET & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_CTRL_RESET & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME0_CTRL_RESET & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_QM_STALL & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_SYNC_OBJECT_FIFO_TH & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_EUS_ROLLUP_CNT_ADD & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_INTR_MASK & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_LOG_SHADOW & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_PCU_RL_DESC0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_PCU_RL_TOKEN_UPDATE & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_PCU_RL_TH & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_PCU_RL_MIN & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_PCU_RL_CTRL_EN & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_PCU_RL_HISTORY_LOG_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_PCU_DUMMY_A_BF16 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_PCU_DUMMY_B_BF16 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_PCU_DUMMY_A_FP32_ODD & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_PCU_DUMMY_A_FP32_EVEN & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_PCU_DUMMY_B_FP32_ODD & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_PCU_DUMMY_B_FP32_EVEN & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_EU_POWER_SAVE_DISABLE & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_CS_DBG_BLOCK_ID & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_CS_DBG_STATUS_DROP_CNT & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_TE_CLOSE_CGATE & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_AGU_SM_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_AGU_SM_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_EZSYNC_OUT_CREDIT & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_PCU_RL_SAT_SEC & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_AGU_SYNC_MSG_AXI_USER & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_QM_SLV_LBW_CLK_EN & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_CTRL_SHADOW_0_STATUS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_CTRL_SHADOW_0_STATUS & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmMME0_CTRL_SHADOW_0_STATUS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME0_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME0_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME0_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME0_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME0_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & + PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME0_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME0_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME0_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME0_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & + PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME0_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME0_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmMME0_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME0_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmMME0_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME1_CTRL_RESET & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME1_CTRL_RESET & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME1_CTRL_RESET & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_QM_STALL & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_SYNC_OBJECT_FIFO_TH & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_EUS_ROLLUP_CNT_ADD & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_INTR_MASK & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_LOG_SHADOW & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_PCU_RL_DESC0 & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_PCU_RL_TOKEN_UPDATE & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_PCU_RL_TH & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_PCU_RL_MIN & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_PCU_RL_CTRL_EN & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_PCU_RL_HISTORY_LOG_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_PCU_DUMMY_A_BF16 & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_PCU_DUMMY_B_BF16 & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_PCU_DUMMY_A_FP32_ODD & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_PCU_DUMMY_A_FP32_EVEN & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_PCU_DUMMY_B_FP32_ODD & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_PCU_DUMMY_B_FP32_EVEN & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_EU_POWER_SAVE_DISABLE & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_CS_DBG_BLOCK_ID & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_CS_DBG_STATUS_DROP_CNT & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_TE_CLOSE_CGATE & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_AGU_SM_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_AGU_SM_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_EZSYNC_OUT_CREDIT & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_PCU_RL_SAT_SEC & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_AGU_SYNC_MSG_AXI_USER & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_QM_SLV_LBW_CLK_EN & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME1_CTRL_SHADOW_0_STATUS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME1_CTRL_SHADOW_0_STATUS & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmMME1_CTRL_SHADOW_0_STATUS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + /* MME 1 is slave, hence its whole QM block is protected (with RR) */ + + pb_addr = (mmMME2_CTRL_RESET & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_CTRL_RESET & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME2_CTRL_RESET & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_QM_STALL & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_SYNC_OBJECT_FIFO_TH & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_EUS_ROLLUP_CNT_ADD & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_INTR_MASK & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_LOG_SHADOW & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_PCU_RL_DESC0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_PCU_RL_TOKEN_UPDATE & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_PCU_RL_TH & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_PCU_RL_MIN & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_PCU_RL_CTRL_EN & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_PCU_RL_HISTORY_LOG_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_PCU_DUMMY_A_BF16 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_PCU_DUMMY_B_BF16 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_PCU_DUMMY_A_FP32_ODD & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_PCU_DUMMY_A_FP32_EVEN & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_PCU_DUMMY_B_FP32_ODD & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_PCU_DUMMY_B_FP32_EVEN & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_EU_POWER_SAVE_DISABLE & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_CS_DBG_BLOCK_ID & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_CS_DBG_STATUS_DROP_CNT & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_TE_CLOSE_CGATE & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_AGU_SM_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_AGU_SM_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_EZSYNC_OUT_CREDIT & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_PCU_RL_SAT_SEC & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_AGU_SYNC_MSG_AXI_USER & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_QM_SLV_LBW_CLK_EN & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_CTRL_SHADOW_0_STATUS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_CTRL_SHADOW_0_STATUS & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmMME2_CTRL_SHADOW_0_STATUS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME2_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME2_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME2_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME2_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME2_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) + >> 7) << 2; + mask = 1 << ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME2_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME2_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME2_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME2_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_23 & + PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME2_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME2_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmMME2_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME2_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmMME2_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME3_CTRL_RESET & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME3_CTRL_RESET & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME3_CTRL_RESET & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_QM_STALL & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_SYNC_OBJECT_FIFO_TH & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_EUS_ROLLUP_CNT_ADD & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_INTR_MASK & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_LOG_SHADOW & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_PCU_RL_DESC0 & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_PCU_RL_TOKEN_UPDATE & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_PCU_RL_TH & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_PCU_RL_MIN & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_PCU_RL_CTRL_EN & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_PCU_RL_HISTORY_LOG_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_PCU_DUMMY_A_BF16 & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_PCU_DUMMY_B_BF16 & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_PCU_DUMMY_A_FP32_ODD & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_PCU_DUMMY_A_FP32_EVEN & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_PCU_DUMMY_B_FP32_ODD & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_PCU_DUMMY_B_FP32_EVEN & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_EU_POWER_SAVE_DISABLE & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_CS_DBG_BLOCK_ID & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_CS_DBG_STATUS_DROP_CNT & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_TE_CLOSE_CGATE & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_AGU_SM_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_AGU_SM_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_EZSYNC_OUT_CREDIT & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_PCU_RL_SAT_SEC & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_AGU_SYNC_MSG_AXI_USER & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_QM_SLV_LBW_CLK_EN & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME3_CTRL_SHADOW_0_STATUS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME3_CTRL_SHADOW_0_STATUS & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmMME3_CTRL_SHADOW_0_STATUS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + /* MME 3 is slave, hence its whole QM block is protected (with RR) */ +} + +static void gaudi_init_dma_protection_bits(struct hl_device *hdev) +{ + u32 pb_addr, mask; + u8 word_offset; + + gaudi_pb_set_block(hdev, mmDMA_IF_E_S_BASE); + gaudi_pb_set_block(hdev, mmDMA_IF_E_S_DOWN_CH0_BASE); + gaudi_pb_set_block(hdev, mmDMA_IF_E_S_DOWN_CH1_BASE); + gaudi_pb_set_block(hdev, mmDMA_E_PLL_BASE); + gaudi_pb_set_block(hdev, mmDMA_IF_E_S_DOWN_BASE); + + gaudi_pb_set_block(hdev, mmDMA_IF_W_N_BASE); + gaudi_pb_set_block(hdev, mmDMA_IF_W_N_DOWN_CH0_BASE); + gaudi_pb_set_block(hdev, mmDMA_IF_W_N_DOWN_CH1_BASE); + gaudi_pb_set_block(hdev, mmDMA_IF_W_N_DOWN_BASE); + + gaudi_pb_set_block(hdev, mmDMA_IF_E_N_BASE); + gaudi_pb_set_block(hdev, mmDMA_IF_E_N_DOWN_CH0_BASE); + gaudi_pb_set_block(hdev, mmDMA_IF_E_N_DOWN_CH1_BASE); + gaudi_pb_set_block(hdev, mmDMA_IF_E_N_DOWN_BASE); + + WREG32(mmDMA0_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmDMA1_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmDMA2_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmDMA3_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmDMA4_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmDMA5_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmDMA6_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmDMA7_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + + WREG32(mmDMA0_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmDMA1_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmDMA2_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmDMA3_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmDMA4_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmDMA5_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmDMA6_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmDMA7_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + + pb_addr = (mmDMA0_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA0_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA0_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA0_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA0_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA0_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA0_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA0_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA0_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA0_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA0_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA0_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA0_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA0_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA1_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA1_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA1_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA1_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA1_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA1_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA1_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA1_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA1_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA1_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA1_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA1_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA1_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA2_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA2_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA2_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA2_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA2_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA2_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA2_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA2_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA2_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA2_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA2_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA2_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA2_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA3_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA3_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA3_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA3_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA3_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA3_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA3_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA3_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA3_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA3_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA3_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA3_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA3_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA4_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA4_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA4_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA4_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA4_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA4_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA4_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA4_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA4_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA4_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA4_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA4_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA4_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA5_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA5_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA5_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA5_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA5_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA5_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA5_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA5_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA5_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA5_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA5_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA5_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA5_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA6_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA6_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA6_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA6_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA6_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA6_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA6_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA6_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA6_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA6_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA6_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA6_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA6_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA7_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA7_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA7_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA7_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA7_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA7_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA7_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA7_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA7_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA7_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA7_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA7_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA7_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA0_CORE_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA0_CORE_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_NON_SECURE_PROPS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA0_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_RD_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_RD_ARCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_RD_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_WR_MAX_AWID & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_WR_AWCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_WR_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_WR_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_ERRMSG_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA0_CORE_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_STS1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA0_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_RD_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_DBG_DESC_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_DBG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA1_CORE_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA1_CORE_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_NON_SECURE_PROPS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA1_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_RD_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_RD_ARCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_RD_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_WR_MAX_AWID & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_WR_AWCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_WR_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_WR_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_ERRMSG_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA1_CORE_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_STS1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA1_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_RD_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_DBG_DESC_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_DBG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA2_CORE_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA2_CORE_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_NON_SECURE_PROPS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA2_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_RD_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_RD_ARCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_RD_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_WR_MAX_AWID & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_WR_AWCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_WR_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_ERRMSG_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA2_CORE_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_STS1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA2_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_RD_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_DBG_DESC_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_DBG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA3_CORE_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA3_CORE_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_NON_SECURE_PROPS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA3_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_RD_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_RD_ARCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_RD_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_WR_MAX_AWID & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_WR_AWCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_WR_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_ERRMSG_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA3_CORE_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_STS1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA3_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_RD_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_DBG_DESC_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_DBG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA4_CORE_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA4_CORE_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_NON_SECURE_PROPS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA4_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_RD_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_RD_ARCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_RD_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_WR_MAX_AWID & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_WR_AWCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_WR_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_ERRMSG_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA4_CORE_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_STS1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA4_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_RD_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_DBG_DESC_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_DBG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA5_CORE_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA5_CORE_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_NON_SECURE_PROPS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA5_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_RD_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_RD_ARCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_RD_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_WR_MAX_AWID & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_WR_AWCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_WR_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_ERRMSG_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA5_CORE_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_STS1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA5_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_RD_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_DBG_DESC_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_DBG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA6_CORE_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA6_CORE_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_NON_SECURE_PROPS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA6_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_RD_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_RD_ARCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_RD_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_WR_MAX_AWID & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_WR_AWCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_WR_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_ERRMSG_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA6_CORE_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_STS1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA6_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_RD_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_DBG_DESC_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_DBG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA7_CORE_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA7_CORE_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_NON_SECURE_PROPS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA7_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_RD_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_RD_ARCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_RD_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_WR_MAX_AWID & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_WR_AWCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_WR_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_ERRMSG_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA7_CORE_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_STS1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA7_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_RD_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_DBG_DESC_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_DBG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); +} + +static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) +{ + u32 pb_addr, mask; + u8 word_offset; + + gaudi_pb_set_block(hdev, mmTPC0_E2E_CRED_BASE); + gaudi_pb_set_block(hdev, mmTPC1_E2E_CRED_BASE); + gaudi_pb_set_block(hdev, mmTPC2_E2E_CRED_BASE); + gaudi_pb_set_block(hdev, mmTPC3_E2E_CRED_BASE); + gaudi_pb_set_block(hdev, mmTPC4_E2E_CRED_BASE); + gaudi_pb_set_block(hdev, mmTPC5_E2E_CRED_BASE); + gaudi_pb_set_block(hdev, mmTPC6_E2E_CRED_BASE); + gaudi_pb_set_block(hdev, mmTPC7_E2E_CRED_BASE); + + WREG32(mmTPC0_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmTPC0_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + + pb_addr = (mmTPC0_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + + word_offset = ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) + >> 7) << 2; + + mask = 1 << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + + word_offset = ((mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) + >> 7) << 2; + mask = 1 << ((mmTPC0_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC0_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_CFG_ROUND_CSR & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_CFG_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_RD_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_WR_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_TPC_INTR_MASK & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_WQ_CREDITS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_ARUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_ARUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_AWUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_AWUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_OPCODE_EXEC & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC0_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + WREG32(mmTPC1_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmTPC1_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + + pb_addr = (mmTPC1_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) + >> 7) << 2; + mask = 1 << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + + word_offset = ((mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) + >> 7) << 2; + mask = 1 << ((mmTPC1_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC1_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_CFG_ROUND_CSR & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_CFG_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_RD_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_WR_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_TPC_INTR_MASK & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_WQ_CREDITS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_ARUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_ARUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_AWUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_AWUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_OPCODE_EXEC & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC1_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + WREG32(mmTPC2_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmTPC2_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + + pb_addr = (mmTPC2_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) + >> 7) << 2; + mask = 1 << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) + >> 7) << 2; + mask = 1 << ((mmTPC2_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC2_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_CFG_ROUND_CSR & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_CFG_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_RD_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_WR_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_TPC_INTR_MASK & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_WQ_CREDITS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_ARUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_ARUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_AWUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_AWUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_OPCODE_EXEC & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC2_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + WREG32(mmTPC3_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmTPC3_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + + pb_addr = (mmTPC3_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) + >> 7) << 2; + mask = 1 << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) + >> 7) << 2; + mask = 1 << ((mmTPC3_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC3_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_CFG_ROUND_CSR & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_CFG_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_RD_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_WR_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_TPC_INTR_MASK & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_WQ_CREDITS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_ARUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_ARUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_AWUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_AWUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_OPCODE_EXEC & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC3_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + WREG32(mmTPC4_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmTPC4_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + + pb_addr = (mmTPC4_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) + >> 7) << 2; + mask = 1 << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) + >> 7) << 2; + mask = 1 << ((mmTPC4_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC4_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_CFG_ROUND_CSR & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_CFG_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_RD_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_WR_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_TPC_INTR_MASK & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_WQ_CREDITS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_ARUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_ARUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_AWUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_AWUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_OPCODE_EXEC & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC4_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + WREG32(mmTPC5_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmTPC5_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + + pb_addr = (mmTPC5_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) + >> 7) << 2; + mask = 1 << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) + >> 7) << 2; + mask = 1 << ((mmTPC5_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC5_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_CFG_ROUND_CSR & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_CFG_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_RD_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_WR_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_TPC_INTR_MASK & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_WQ_CREDITS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_ARUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_ARUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_AWUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_AWUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_OPCODE_EXEC & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC5_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + WREG32(mmTPC6_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmTPC6_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + + pb_addr = (mmTPC6_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) + >> 7) << 2; + mask = 1 << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + + word_offset = ((mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) + >> 7) << 2; + mask = 1 << ((mmTPC6_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + + mask = 1 << ((mmTPC6_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_CFG_ROUND_CSR & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_CFG_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_RD_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_WR_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_TPC_INTR_MASK & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_WQ_CREDITS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_ARUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_ARUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_AWUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_AWUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_OPCODE_EXEC & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC6_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + WREG32(mmTPC7_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmTPC7_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + + pb_addr = (mmTPC7_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + + word_offset = ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) + >> 7) << 2; + + mask = 1 << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) + >> 7) << 2; + mask = 1 << ((mmTPC7_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC7_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_CFG_ROUND_CSR & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_CFG_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_RD_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_WR_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_TPC_INTR_MASK & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_WQ_CREDITS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_ARUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_ARUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_AWUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_AWUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_OPCODE_EXEC & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC7_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); +} + +/** + * gaudi_init_protection_bits - Initialize protection bits of specific registers + * + * @hdev: pointer to hl_device structure + * + * All protection bits are 1 by default, means not protected. Need to set to 0 + * each bit that belongs to a protected register. + * + */ +static void gaudi_init_protection_bits(struct hl_device *hdev) +{ + /* + * In each 4K block of registers, the last 128 bytes are protection + * bits - total of 1024 bits, one for each register. Each bit is related + * to a specific register, by the order of the registers. + * So in order to calculate the bit that is related to a given register, + * we need to calculate its word offset and then the exact bit inside + * the word (which is 4 bytes). + * + * Register address: + * + * 31 12 11 7 6 2 1 0 + * ----------------------------------------------------------------- + * | Don't | word | bit location | 0 | + * | care | offset | inside word | | + * ----------------------------------------------------------------- + * + * Bits 7-11 represents the word offset inside the 128 bytes. + * Bits 2-6 represents the bit location inside the word. + * + * When a bit is cleared, it means the register it represents can only + * be accessed by a secured entity. When the bit is set, any entity can + * access the register. + * + * The last 4 bytes in the block of the PBs control the security of + * the PBs themselves, so they always need to be configured to be + * secured + */ + + gaudi_pb_set_block(hdev, mmIF_E_PLL_BASE); + gaudi_pb_set_block(hdev, mmMESH_W_PLL_BASE); + gaudi_pb_set_block(hdev, mmSRAM_W_PLL_BASE); + gaudi_pb_set_block(hdev, mmMESH_E_PLL_BASE); + gaudi_pb_set_block(hdev, mmSRAM_E_PLL_BASE); + + gaudi_init_dma_protection_bits(hdev); + + gaudi_init_mme_protection_bits(hdev); + + gaudi_init_tpc_protection_bits(hdev); +} + +static void gaudi_init_range_registers_lbw(struct hl_device *hdev) +{ + u32 lbw_rng_start[GAUDI_NUMBER_OF_LBW_RANGES]; + u32 lbw_rng_end[GAUDI_NUMBER_OF_LBW_RANGES]; + int i, j; + + lbw_rng_start[0] = (0xFBFE0000 & 0x3FFFFFF) - 1; + lbw_rng_end[0] = (0xFBFFF000 & 0x3FFFFFF) + 1; + + lbw_rng_start[1] = (0xFC0E8000 & 0x3FFFFFF) - 1; + lbw_rng_end[1] = (0xFC120000 & 0x3FFFFFF) + 1; + + lbw_rng_start[2] = (0xFC1E8000 & 0x3FFFFFF) - 1; + lbw_rng_end[2] = (0xFC48FFFF & 0x3FFFFFF) + 1; + + lbw_rng_start[3] = (0xFC600000 & 0x3FFFFFF) - 1; + lbw_rng_end[3] = (0xFCC48FFF & 0x3FFFFFF) + 1; + + lbw_rng_start[4] = (0xFCC4A000 & 0x3FFFFFF) - 1; + lbw_rng_end[4] = (0xFCCDFFFF & 0x3FFFFFF) + 1; + + lbw_rng_start[5] = (0xFCCE4000 & 0x3FFFFFF) - 1; + lbw_rng_end[5] = (0xFCD1FFFF & 0x3FFFFFF) + 1; + + lbw_rng_start[6] = (0xFCD24000 & 0x3FFFFFF) - 1; + lbw_rng_end[6] = (0xFCD5FFFF & 0x3FFFFFF) + 1; + + lbw_rng_start[7] = (0xFCD64000 & 0x3FFFFFF) - 1; + lbw_rng_end[7] = (0xFCD9FFFF & 0x3FFFFFF) + 1; + + lbw_rng_start[8] = (0xFCDA4000 & 0x3FFFFFF) - 1; + lbw_rng_end[8] = (0xFCDDFFFF & 0x3FFFFFF) + 1; + + lbw_rng_start[9] = (0xFCDE4000 & 0x3FFFFFF) - 1; + lbw_rng_end[9] = (0xFCE05FFF & 0x3FFFFFF) + 1; + + lbw_rng_start[10] = (0xFEC43000 & 0x3FFFFFF) - 1; + lbw_rng_end[10] = (0xFEC43FFF & 0x3FFFFFF) + 1; + + lbw_rng_start[11] = (0xFE484000 & 0x3FFFFFF) - 1; + lbw_rng_end[11] = (0xFE484FFF & 0x3FFFFFF) + 1; + + for (i = 0 ; i < GAUDI_NUMBER_OF_RR_REGS ; i++) { + WREG32(gaudi_rr_lbw_hit_aw_regs[i], + (1 << GAUDI_NUMBER_OF_LBW_RANGES) - 1); + WREG32(gaudi_rr_lbw_hit_ar_regs[i], + (1 << GAUDI_NUMBER_OF_LBW_RANGES) - 1); + } + + for (i = 0 ; i < GAUDI_NUMBER_OF_RR_REGS ; i++) + for (j = 0 ; j < GAUDI_NUMBER_OF_LBW_RANGES ; j++) { + WREG32(gaudi_rr_lbw_min_aw_regs[i] + (j << 2), + lbw_rng_start[j]); + + WREG32(gaudi_rr_lbw_min_ar_regs[i] + (j << 2), + lbw_rng_start[j]); + + WREG32(gaudi_rr_lbw_max_aw_regs[i] + (j << 2), + lbw_rng_end[j]); + + WREG32(gaudi_rr_lbw_max_ar_regs[i] + (j << 2), + lbw_rng_end[j]); + } +} + +static void gaudi_init_range_registers_hbw(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + u32 dram_addr_lo = lower_32_bits(DRAM_PHYS_BASE); + u32 dram_addr_hi = upper_32_bits(DRAM_PHYS_BASE); + + u32 sram_addr_lo = lower_32_bits(SRAM_BASE_ADDR); + u32 sram_addr_hi = upper_32_bits(SRAM_BASE_ADDR); + + u32 scratch_addr_lo = lower_32_bits(PSOC_SCRATCHPAD_ADDR); + u32 scratch_addr_hi = upper_32_bits(PSOC_SCRATCHPAD_ADDR); + + u32 pcie_fw_addr_lo = lower_32_bits(PCIE_FW_SRAM_ADDR); + u32 pcie_fw_addr_hi = upper_32_bits(PCIE_FW_SRAM_ADDR); + + u32 spi_addr_lo = lower_32_bits(SPI_FLASH_BASE_ADDR); + u32 spi_addr_hi = upper_32_bits(SPI_FLASH_BASE_ADDR); + + int i; + + /* Configure HBW RR: + * 1st range is the DRAM (first 512MB) + * 2nd range is the 1st 128 bytes in SRAM (for tensor DMA). This area + * is defined as read-only for user + * 3rd range is the PSOC scratch-pad + * 4th range is the PCIe F/W SRAM area + * 5th range is the SPI FLASH area + * 6th range is the host + */ + + for (i = 0 ; i < GAUDI_NUMBER_OF_RR_REGS ; i++) { + WREG32(gaudi_rr_hbw_hit_aw_regs[i], 0x1F); + WREG32(gaudi_rr_hbw_hit_ar_regs[i], 0x1D); + } + + for (i = 0 ; i < GAUDI_NUMBER_OF_RR_REGS ; i++) { + WREG32(gaudi_rr_hbw_base_low_aw_regs[i], dram_addr_lo); + WREG32(gaudi_rr_hbw_base_low_ar_regs[i], dram_addr_lo); + + WREG32(gaudi_rr_hbw_base_high_aw_regs[i], dram_addr_hi); + WREG32(gaudi_rr_hbw_base_high_ar_regs[i], dram_addr_hi); + + WREG32(gaudi_rr_hbw_mask_low_aw_regs[i], 0xE0000000); + WREG32(gaudi_rr_hbw_mask_low_ar_regs[i], 0xE0000000); + + WREG32(gaudi_rr_hbw_mask_high_aw_regs[i], 0x3FFFF); + WREG32(gaudi_rr_hbw_mask_high_ar_regs[i], 0x3FFFF); + + WREG32(gaudi_rr_hbw_base_low_aw_regs[i] + 4, sram_addr_lo); + WREG32(gaudi_rr_hbw_base_high_aw_regs[i] + 4, sram_addr_hi); + WREG32(gaudi_rr_hbw_mask_low_aw_regs[i] + 4, 0xFFFFFF80); + WREG32(gaudi_rr_hbw_mask_high_aw_regs[i] + 4, 0x3FFFF); + + WREG32(gaudi_rr_hbw_base_low_aw_regs[i] + 8, scratch_addr_lo); + WREG32(gaudi_rr_hbw_base_low_ar_regs[i] + 8, scratch_addr_lo); + + WREG32(gaudi_rr_hbw_base_high_aw_regs[i] + 8, scratch_addr_hi); + WREG32(gaudi_rr_hbw_base_high_ar_regs[i] + 8, scratch_addr_hi); + + WREG32(gaudi_rr_hbw_mask_low_aw_regs[i] + 8, 0xFFFF0000); + WREG32(gaudi_rr_hbw_mask_low_ar_regs[i] + 8, 0xFFFF0000); + + WREG32(gaudi_rr_hbw_mask_high_aw_regs[i] + 8, 0x3FFFF); + WREG32(gaudi_rr_hbw_mask_high_ar_regs[i] + 8, 0x3FFFF); + + WREG32(gaudi_rr_hbw_base_low_aw_regs[i] + 12, pcie_fw_addr_lo); + WREG32(gaudi_rr_hbw_base_low_ar_regs[i] + 12, pcie_fw_addr_lo); + + WREG32(gaudi_rr_hbw_base_high_aw_regs[i] + 12, pcie_fw_addr_hi); + WREG32(gaudi_rr_hbw_base_high_ar_regs[i] + 12, pcie_fw_addr_hi); + + WREG32(gaudi_rr_hbw_mask_low_aw_regs[i] + 12, 0xFFFF8000); + WREG32(gaudi_rr_hbw_mask_low_ar_regs[i] + 12, 0xFFFF8000); + + WREG32(gaudi_rr_hbw_mask_high_aw_regs[i] + 12, 0x3FFFF); + WREG32(gaudi_rr_hbw_mask_high_ar_regs[i] + 12, 0x3FFFF); + + WREG32(gaudi_rr_hbw_base_low_aw_regs[i] + 16, spi_addr_lo); + WREG32(gaudi_rr_hbw_base_low_ar_regs[i] + 16, spi_addr_lo); + + WREG32(gaudi_rr_hbw_base_high_aw_regs[i] + 16, spi_addr_hi); + WREG32(gaudi_rr_hbw_base_high_ar_regs[i] + 16, spi_addr_hi); + + WREG32(gaudi_rr_hbw_mask_low_aw_regs[i] + 16, 0xFE000000); + WREG32(gaudi_rr_hbw_mask_low_ar_regs[i] + 16, 0xFE000000); + + WREG32(gaudi_rr_hbw_mask_high_aw_regs[i] + 16, 0x3FFFF); + WREG32(gaudi_rr_hbw_mask_high_ar_regs[i] + 16, 0x3FFFF); + + if (gaudi->hw_cap_initialized & HW_CAP_MMU) + continue; + + /* Protect HOST */ + WREG32(gaudi_rr_hbw_base_low_aw_regs[i] + 20, 0); + WREG32(gaudi_rr_hbw_base_low_ar_regs[i] + 20, 0); + + WREG32(gaudi_rr_hbw_base_high_aw_regs[i] + 20, 0); + WREG32(gaudi_rr_hbw_base_high_ar_regs[i] + 20, 0); + + WREG32(gaudi_rr_hbw_mask_low_aw_regs[i] + 20, 0); + WREG32(gaudi_rr_hbw_mask_low_ar_regs[i] + 20, 0); + + WREG32(gaudi_rr_hbw_mask_high_aw_regs[i] + 20, 0xFFF80); + WREG32(gaudi_rr_hbw_mask_high_ar_regs[i] + 20, 0xFFF80); + } +} + +/** + * gaudi_init_security - Initialize security model + * + * @hdev: pointer to hl_device structure + * + * Initialize the security model of the device + * That includes range registers and protection bit per register + * + */ +void gaudi_init_security(struct hl_device *hdev) +{ + /* Due to H/W errata GAUDI0500, need to override default security + * property configuration of MME SBAB and ACC to be non-privileged and + * non-secured + */ + WREG32(mmMME0_SBAB_PROT, 0x2); + WREG32(mmMME0_ACC_PROT, 0x2); + WREG32(mmMME1_SBAB_PROT, 0x2); + WREG32(mmMME1_ACC_PROT, 0x2); + WREG32(mmMME2_SBAB_PROT, 0x2); + WREG32(mmMME2_ACC_PROT, 0x2); + WREG32(mmMME3_SBAB_PROT, 0x2); + WREG32(mmMME3_ACC_PROT, 0x2); + + /* On RAZWI, 0 will be returned from RR and 0xBABA0BAD from PB */ + WREG32(0xC01B28, 0x1); + + gaudi_init_range_registers_lbw(hdev); + + gaudi_init_range_registers_hbw(hdev); + + gaudi_init_protection_bits(hdev); +} diff --git a/drivers/misc/habanalabs/goya/goya.c b/drivers/misc/habanalabs/goya/goya.c index 68f065607544..0d2952bb58df 100644 --- a/drivers/misc/habanalabs/goya/goya.c +++ b/drivers/misc/habanalabs/goya/goya.c @@ -72,7 +72,7 @@ * */ -#define GOYA_UBOOT_FW_FILE "habanalabs/goya/goya-u-boot.bin" +#define GOYA_BOOT_FIT_FILE "habanalabs/goya/goya-boot-fit.itb" #define GOYA_LINUX_FW_FILE "habanalabs/goya/goya-fit.itb" #define GOYA_MMU_REGS_NUM 63 @@ -87,6 +87,7 @@ #define GOYA_TEST_QUEUE_WAIT_USEC 100000 /* 100ms */ #define GOYA_PLDM_MMU_TIMEOUT_USEC (MMU_CONFIG_TIMEOUT_USEC * 100) #define GOYA_PLDM_QMAN0_TIMEOUT_USEC (HL_DEVICE_TIMEOUT_USEC * 30) +#define GOYA_BOOT_FIT_REQ_TIMEOUT_USEC 1000000 /* 1s */ #define GOYA_QMAN0_FENCE_VAL 0xD169B243 @@ -531,7 +532,7 @@ static int goya_early_init(struct hl_device *hdev) prop->dram_pci_bar_size = pci_resource_len(pdev, DDR_BAR_ID); - rc = hl_pci_init(hdev, 48); + rc = hl_pci_init(hdev); if (rc) return rc; @@ -750,6 +751,8 @@ static int goya_sw_init(struct hl_device *hdev) } spin_lock_init(&goya->hw_queues_lock); + hdev->supports_coresight = true; + hdev->supports_soft_reset = true; return 0; @@ -800,6 +803,7 @@ static void goya_init_dma_qman(struct hl_device *hdev, int dma_id, u32 so_base_lo, so_base_hi; u32 gic_base_lo, gic_base_hi; u32 reg_off = dma_id * (mmDMA_QM_1_PQ_PI - mmDMA_QM_0_PQ_PI); + u32 dma_err_cfg = QMAN_DMA_ERR_MSG_EN; mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); @@ -836,7 +840,10 @@ static void goya_init_dma_qman(struct hl_device *hdev, int dma_id, else WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_FULLY_TRUSTED); - WREG32(mmDMA_QM_0_GLBL_ERR_CFG + reg_off, QMAN_DMA_ERR_MSG_EN); + if (hdev->stop_on_err) + dma_err_cfg |= 1 << DMA_QM_0_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT; + + WREG32(mmDMA_QM_0_GLBL_ERR_CFG + reg_off, dma_err_cfg); WREG32(mmDMA_QM_0_GLBL_CFG0 + reg_off, QMAN_DMA_ENABLE); } @@ -886,6 +893,7 @@ void goya_init_dma_qmans(struct hl_device *hdev) q = &hdev->kernel_queues[0]; for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++, q++) { + q->cq_id = q->msi_vec = i; goya_init_dma_qman(hdev, i, q->bus_address); goya_init_dma_ch(hdev, i); } @@ -2205,80 +2213,37 @@ static void goya_halt_engines(struct hl_device *hdev, bool hard_reset) } /* - * goya_push_uboot_to_device() - Push u-boot FW code to device. - * @hdev: Pointer to hl_device structure. - * - * Copy u-boot fw code from firmware file to SRAM BAR. - * - * Return: 0 on success, non-zero for failure. - */ -static int goya_push_uboot_to_device(struct hl_device *hdev) -{ - void __iomem *dst; - - dst = hdev->pcie_bar[SRAM_CFG_BAR_ID] + UBOOT_FW_OFFSET; - - return hl_fw_push_fw_to_device(hdev, GOYA_UBOOT_FW_FILE, dst); -} - -/* - * goya_push_linux_to_device() - Push LINUX FW code to device. + * goya_load_firmware_to_device() - Load LINUX FW code to device. * @hdev: Pointer to hl_device structure. * * Copy LINUX fw code from firmware file to HBM BAR. * * Return: 0 on success, non-zero for failure. */ -static int goya_push_linux_to_device(struct hl_device *hdev) +static int goya_load_firmware_to_device(struct hl_device *hdev) { void __iomem *dst; dst = hdev->pcie_bar[DDR_BAR_ID] + LINUX_FW_OFFSET; - return hl_fw_push_fw_to_device(hdev, GOYA_LINUX_FW_FILE, dst); + return hl_fw_load_fw_to_device(hdev, GOYA_LINUX_FW_FILE, dst); } -static int goya_pldm_init_cpu(struct hl_device *hdev) +/* + * goya_load_boot_fit_to_device() - Load boot fit to device. + * @hdev: Pointer to hl_device structure. + * + * Copy boot fit file to SRAM BAR. + * + * Return: 0 on success, non-zero for failure. + */ +static int goya_load_boot_fit_to_device(struct hl_device *hdev) { - u32 unit_rst_val; - int rc; + void __iomem *dst; - /* Must initialize SRAM scrambler before pushing u-boot to SRAM */ - goya_init_golden_registers(hdev); + dst = hdev->pcie_bar[SRAM_CFG_BAR_ID] + BOOT_FIT_SRAM_OFFSET; - /* Put ARM cores into reset */ - WREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL, CPU_RESET_ASSERT); - RREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL); - - /* Reset the CA53 MACRO */ - unit_rst_val = RREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N); - WREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N, CA53_RESET); - RREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N); - WREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N, unit_rst_val); - RREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N); - - rc = goya_push_uboot_to_device(hdev); - if (rc) - return rc; - - rc = goya_push_linux_to_device(hdev); - if (rc) - return rc; - - WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_FIT_RDY); - WREG32(mmPSOC_GLOBAL_CONF_WARM_REBOOT, CPU_BOOT_STATUS_NA); - - WREG32(mmCPU_CA53_CFG_RST_ADDR_LSB_0, - lower_32_bits(SRAM_BASE_ADDR + UBOOT_FW_OFFSET)); - WREG32(mmCPU_CA53_CFG_RST_ADDR_MSB_0, - upper_32_bits(SRAM_BASE_ADDR + UBOOT_FW_OFFSET)); - - /* Release ARM core 0 from reset */ - WREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL, - CPU_RESET_CORE0_DEASSERT); - RREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL); - - return 0; + return hl_fw_load_fw_to_device(hdev, GOYA_BOOT_FIT_FILE, dst); } /* @@ -2286,7 +2251,7 @@ static int goya_pldm_init_cpu(struct hl_device *hdev) * The version string should be located by that offset. */ static void goya_read_device_fw_version(struct hl_device *hdev, - enum goya_fw_component fwc) + enum hl_fw_component fwc) { const char *name; u32 ver_off; @@ -2320,10 +2285,9 @@ static void goya_read_device_fw_version(struct hl_device *hdev, } } -static int goya_init_cpu(struct hl_device *hdev, u32 cpu_timeout) +static int goya_init_cpu(struct hl_device *hdev) { struct goya_device *goya = hdev->asic_specific; - u32 status; int rc; if (!hdev->cpu_enable) @@ -2342,115 +2306,15 @@ static int goya_init_cpu(struct hl_device *hdev, u32 cpu_timeout) return -EIO; } - if (hdev->pldm) { - rc = goya_pldm_init_cpu(hdev); - if (rc) - return rc; + rc = hl_fw_init_cpu(hdev, mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS, + mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, + mmCPU_CMD_STATUS_TO_HOST, mmCPU_BOOT_ERR0, + false, GOYA_CPU_TIMEOUT_USEC, + GOYA_BOOT_FIT_REQ_TIMEOUT_USEC); - goto out; - } - - /* Make sure CPU boot-loader is running */ - rc = hl_poll_timeout( - hdev, - mmPSOC_GLOBAL_CONF_WARM_REBOOT, - status, - (status == CPU_BOOT_STATUS_DRAM_RDY) || - (status == CPU_BOOT_STATUS_SRAM_AVAIL), - 10000, - cpu_timeout); - - /* Read U-Boot version now in case we will later fail */ - goya_read_device_fw_version(hdev, FW_COMP_UBOOT); - goya_read_device_fw_version(hdev, FW_COMP_PREBOOT); - - if (rc) { - dev_err(hdev->dev, "Error in ARM u-boot!"); - switch (status) { - case CPU_BOOT_STATUS_NA: - dev_err(hdev->dev, - "ARM status %d - BTL did NOT run\n", status); - break; - case CPU_BOOT_STATUS_IN_WFE: - dev_err(hdev->dev, - "ARM status %d - Inside WFE loop\n", status); - break; - case CPU_BOOT_STATUS_IN_BTL: - dev_err(hdev->dev, - "ARM status %d - Stuck in BTL\n", status); - break; - case CPU_BOOT_STATUS_IN_PREBOOT: - dev_err(hdev->dev, - "ARM status %d - Stuck in Preboot\n", status); - break; - case CPU_BOOT_STATUS_IN_SPL: - dev_err(hdev->dev, - "ARM status %d - Stuck in SPL\n", status); - break; - case CPU_BOOT_STATUS_IN_UBOOT: - dev_err(hdev->dev, - "ARM status %d - Stuck in u-boot\n", status); - break; - case CPU_BOOT_STATUS_DRAM_INIT_FAIL: - dev_err(hdev->dev, - "ARM status %d - DDR initialization failed\n", - status); - break; - case CPU_BOOT_STATUS_UBOOT_NOT_READY: - dev_err(hdev->dev, - "ARM status %d - u-boot stopped by user\n", - status); - break; - case CPU_BOOT_STATUS_TS_INIT_FAIL: - dev_err(hdev->dev, - "ARM status %d - Thermal Sensor initialization failed\n", - status); - break; - default: - dev_err(hdev->dev, - "ARM status %d - Invalid status code\n", - status); - break; - } - return -EIO; - } - - if (!hdev->fw_loading) { - dev_info(hdev->dev, "Skip loading FW\n"); - goto out; - } - - if (status == CPU_BOOT_STATUS_SRAM_AVAIL) - goto out; - - rc = goya_push_linux_to_device(hdev); if (rc) return rc; - WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_FIT_RDY); - - rc = hl_poll_timeout( - hdev, - mmPSOC_GLOBAL_CONF_WARM_REBOOT, - status, - (status == CPU_BOOT_STATUS_SRAM_AVAIL), - 10000, - cpu_timeout); - - if (rc) { - if (status == CPU_BOOT_STATUS_FIT_CORRUPTED) - dev_err(hdev->dev, - "ARM u-boot reports FIT image is corrupted\n"); - else - dev_err(hdev->dev, - "ARM Linux failed to load, %d\n", status); - WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_NA); - return -EIO; - } - - dev_info(hdev->dev, "Successfully loaded firmware to device\n"); - -out: goya->hw_cap_initialized |= HW_CAP_CPU; return 0; @@ -2565,7 +2429,7 @@ static int goya_hw_init(struct hl_device *hdev) */ WREG32(mmHW_STATE, HL_DEVICE_HW_STATE_DIRTY); - rc = goya_init_cpu(hdev, GOYA_CPU_TIMEOUT_USEC); + rc = goya_init_cpu(hdev); if (rc) { dev_err(hdev->dev, "failed to initialize CPU\n"); return rc; @@ -2684,30 +2548,6 @@ static void goya_hw_fini(struct hl_device *hdev, bool hard_reset) HW_CAP_MMU | HW_CAP_TPC_MBIST | HW_CAP_GOLDEN | HW_CAP_TPC); memset(goya->events_stat, 0, sizeof(goya->events_stat)); - - if (!hdev->pldm) { - int rc; - /* In case we are running inside VM and the VM is - * shutting down, we need to make sure CPU boot-loader - * is running before we can continue the VM shutdown. - * That is because the VM will send an FLR signal that - * we must answer - */ - dev_info(hdev->dev, - "Going to wait up to %ds for CPU boot loader\n", - GOYA_CPU_TIMEOUT_USEC / 1000 / 1000); - - rc = hl_poll_timeout( - hdev, - mmPSOC_GLOBAL_CONF_WARM_REBOOT, - status, - (status == CPU_BOOT_STATUS_DRAM_RDY), - 10000, - GOYA_CPU_TIMEOUT_USEC); - if (rc) - dev_err(hdev->dev, - "failed to wait for CPU boot loader\n"); - } } int goya_suspend(struct hl_device *hdev) @@ -3555,6 +3395,7 @@ static int goya_validate_cb(struct hl_device *hdev, */ rc = goya_validate_wreg32(hdev, parser, (struct packet_wreg32 *) user_pkt); + parser->patched_cb_size += pkt_size; break; case PACKET_WREG_BULK: @@ -4016,7 +3857,8 @@ int goya_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser) } void goya_add_end_of_cb_packets(struct hl_device *hdev, u64 kernel_address, - u32 len, u64 cq_addr, u32 cq_val, u32 msix_vec) + u32 len, u64 cq_addr, u32 cq_val, u32 msix_vec, + bool eb) { struct packet_msg_prot *cq_pkt; u32 tmp; @@ -5042,7 +4884,7 @@ static void goya_mmu_prepare(struct hl_device *hdev, u32 asid) goya_mmu_prepare_reg(hdev, goya_mmu_regs[i], asid); } -static void goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard, +static int goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard, u32 flags) { struct goya_device *goya = hdev->asic_specific; @@ -5051,11 +4893,11 @@ static void goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard, if (!(goya->hw_cap_initialized & HW_CAP_MMU) || hdev->hard_reset_pending) - return; + return 0; /* no need in L1 only invalidation in Goya */ if (!is_hard) - return; + return 0; if (hdev->pldm) timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC; @@ -5077,13 +4919,17 @@ static void goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard, mutex_unlock(&hdev->mmu_cache_lock); - if (rc) - dev_notice_ratelimited(hdev->dev, - "Timeout when waiting for MMU cache invalidation\n"); + if (rc) { + dev_err_ratelimited(hdev->dev, + "MMU cache invalidation timeout\n"); + hl_device_reset(hdev, true, false); + } + + return rc; } -static void goya_mmu_invalidate_cache_range(struct hl_device *hdev, - bool is_hard, u32 asid, u64 va, u64 size) +static int goya_mmu_invalidate_cache_range(struct hl_device *hdev, + bool is_hard, u32 asid, u64 va, u64 size) { struct goya_device *goya = hdev->asic_specific; u32 status, timeout_usec, inv_data, pi; @@ -5091,11 +4937,11 @@ static void goya_mmu_invalidate_cache_range(struct hl_device *hdev, if (!(goya->hw_cap_initialized & HW_CAP_MMU) || hdev->hard_reset_pending) - return; + return 0; /* no need in L1 only invalidation in Goya */ if (!is_hard) - return; + return 0; if (hdev->pldm) timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC; @@ -5128,9 +4974,13 @@ static void goya_mmu_invalidate_cache_range(struct hl_device *hdev, mutex_unlock(&hdev->mmu_cache_lock); - if (rc) - dev_notice_ratelimited(hdev->dev, - "Timeout when waiting for MMU cache invalidation\n"); + if (rc) { + dev_err_ratelimited(hdev->dev, + "MMU cache invalidation timeout\n"); + hl_device_reset(hdev, true, false); + } + + return rc; } int goya_send_heartbeat(struct hl_device *hdev) @@ -5178,6 +5028,16 @@ int goya_armcp_info_get(struct hl_device *hdev) return 0; } +static void goya_enable_clock_gating(struct hl_device *hdev) +{ + +} + +static void goya_disable_clock_gating(struct hl_device *hdev) +{ + +} + static bool goya_is_device_idle(struct hl_device *hdev, u32 *mask, struct seq_file *s) { @@ -5293,6 +5153,68 @@ static enum hl_device_hw_state goya_get_hw_state(struct hl_device *hdev) return RREG32(mmHW_STATE); } +u32 goya_get_queue_id_for_cq(struct hl_device *hdev, u32 cq_idx) +{ + return cq_idx; +} + +static void goya_ext_queue_init(struct hl_device *hdev, u32 q_idx) +{ + +} + +static void goya_ext_queue_reset(struct hl_device *hdev, u32 q_idx) +{ + +} + +static u32 goya_get_signal_cb_size(struct hl_device *hdev) +{ + return 0; +} + +static u32 goya_get_wait_cb_size(struct hl_device *hdev) +{ + return 0; +} + +static void goya_gen_signal_cb(struct hl_device *hdev, void *data, u16 sob_id) +{ + +} + +static void goya_gen_wait_cb(struct hl_device *hdev, void *data, u16 sob_id, + u16 sob_val, u16 mon_id, u32 q_idx) +{ + +} + +static void goya_reset_sob(struct hl_device *hdev, void *data) +{ + +} + +static void goya_set_dma_mask_from_fw(struct hl_device *hdev) +{ + if (RREG32(mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_0) == + HL_POWER9_HOST_MAGIC) { + dev_dbg(hdev->dev, "Working in 64-bit DMA mode\n"); + hdev->power9_64bit_dma_enable = 1; + hdev->dma_mask = 64; + } else { + dev_dbg(hdev->dev, "Working in 48-bit DMA mode\n"); + hdev->power9_64bit_dma_enable = 0; + hdev->dma_mask = 48; + } +} + +u64 goya_get_device_time(struct hl_device *hdev) +{ + u64 device_time = ((u64) RREG32(mmPSOC_TIMESTAMP_CNTCVU)) << 32; + + return device_time | RREG32(mmPSOC_TIMESTAMP_CNTCVL); +} + static const struct hl_asic_funcs goya_funcs = { .early_init = goya_early_init, .early_fini = goya_early_fini, @@ -5337,6 +5259,8 @@ static const struct hl_asic_funcs goya_funcs = { .mmu_invalidate_cache = goya_mmu_invalidate_cache, .mmu_invalidate_cache_range = goya_mmu_invalidate_cache_range, .send_heartbeat = goya_send_heartbeat, + .enable_clock_gating = goya_enable_clock_gating, + .disable_clock_gating = goya_disable_clock_gating, .debug_coresight = goya_debug_coresight, .is_device_idle = goya_is_device_idle, .soft_reset_late_init = goya_soft_reset_late_init, @@ -5352,7 +5276,20 @@ static const struct hl_asic_funcs goya_funcs = { .rreg = hl_rreg, .wreg = hl_wreg, .halt_coresight = goya_halt_coresight, - .get_clk_rate = goya_get_clk_rate + .get_clk_rate = goya_get_clk_rate, + .get_queue_id_for_cq = goya_get_queue_id_for_cq, + .read_device_fw_version = goya_read_device_fw_version, + .load_firmware_to_device = goya_load_firmware_to_device, + .load_boot_fit_to_device = goya_load_boot_fit_to_device, + .ext_queue_init = goya_ext_queue_init, + .ext_queue_reset = goya_ext_queue_reset, + .get_signal_cb_size = goya_get_signal_cb_size, + .get_wait_cb_size = goya_get_wait_cb_size, + .gen_signal_cb = goya_gen_signal_cb, + .gen_wait_cb = goya_gen_wait_cb, + .reset_sob = goya_reset_sob, + .set_dma_mask_from_fw = goya_set_dma_mask_from_fw, + .get_device_time = goya_get_device_time }; /* diff --git a/drivers/misc/habanalabs/goya/goyaP.h b/drivers/misc/habanalabs/goya/goyaP.h index c3230cb6e25c..d36f8d90c9c9 100644 --- a/drivers/misc/habanalabs/goya/goyaP.h +++ b/drivers/misc/habanalabs/goya/goyaP.h @@ -45,7 +45,7 @@ #define CORESIGHT_TIMEOUT_USEC 100000 /* 100 ms */ -#define GOYA_CPU_TIMEOUT_USEC 10000000 /* 10s */ +#define GOYA_CPU_TIMEOUT_USEC 15000000 /* 15s */ #define TPC_ENABLED_MASK 0xFF @@ -149,11 +149,6 @@ #define HW_CAP_GOLDEN 0x00000400 #define HW_CAP_TPC 0x00000800 -enum goya_fw_component { - FW_COMP_UBOOT, - FW_COMP_PREBOOT -}; - struct goya_device { /* TODO: remove hw_queues_lock after moving to scheduler code */ spinlock_t hw_queues_lock; @@ -221,7 +216,8 @@ void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry); void *goya_get_events_stat(struct hl_device *hdev, bool aggregate, u32 *size); void goya_add_end_of_cb_packets(struct hl_device *hdev, u64 kernel_address, - u32 len, u64 cq_addr, u32 cq_val, u32 msix_vec); + u32 len, u64 cq_addr, u32 cq_val, u32 msix_vec, + bool eb); int goya_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser); void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id, dma_addr_t *dma_handle, u16 *queue_len); @@ -234,5 +230,7 @@ void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size, void goya_mmu_remove_device_cpu_mappings(struct hl_device *hdev); int goya_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk); +u32 goya_get_queue_id_for_cq(struct hl_device *hdev, u32 cq_idx); +u64 goya_get_device_time(struct hl_device *hdev); #endif /* GOYAP_H_ */ diff --git a/drivers/misc/habanalabs/goya/goya_coresight.c b/drivers/misc/habanalabs/goya/goya_coresight.c index a1bc930d904f..1258724ea510 100644 --- a/drivers/misc/habanalabs/goya/goya_coresight.c +++ b/drivers/misc/habanalabs/goya/goya_coresight.c @@ -266,7 +266,7 @@ static int goya_config_stm(struct hl_device *hdev, WREG32(base_reg + 0xDF4, 0x80); WREG32(base_reg + 0xE8C, input->frequency); WREG32(base_reg + 0xE90, 0x7FF); - WREG32(base_reg + 0xE80, 0x7 | (input->id << 16)); + WREG32(base_reg + 0xE80, 0x27 | (input->id << 16)); } else { WREG32(base_reg + 0xE80, 4); WREG32(base_reg + 0xD64, 0); diff --git a/drivers/misc/habanalabs/goya/goya_security.c b/drivers/misc/habanalabs/goya/goya_security.c index d6ec12b3e692..de8297001fea 100644 --- a/drivers/misc/habanalabs/goya/goya_security.c +++ b/drivers/misc/habanalabs/goya/goya_security.c @@ -683,7 +683,6 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) mask = 1 << ((mmTPC0_CFG_SEMAPHORE & 0x7F) >> 2); mask |= 1 << ((mmTPC0_CFG_VFLAGS & 0x7F) >> 2); mask |= 1 << ((mmTPC0_CFG_SFLAGS & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_LFSR_POLYNOM & 0x7F) >> 2); mask |= 1 << ((mmTPC0_CFG_STATUS & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -695,7 +694,6 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) mask |= 1 << ((mmTPC0_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); mask |= 1 << ((mmTPC0_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); mask |= 1 << ((mmTPC0_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); mask |= 1 << ((mmTPC0_CFG_TPC_STALL & 0x7F) >> 2); mask |= 1 << ((mmTPC0_CFG_MSS_CONFIG & 0x7F) >> 2); mask |= 1 << ((mmTPC0_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); @@ -875,6 +873,16 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) goya_pb_set_block(hdev, mmTPC1_RD_REGULATOR_BASE); goya_pb_set_block(hdev, mmTPC1_WR_REGULATOR_BASE); + pb_addr = (mmTPC1_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2; + + mask = 1 << ((mmTPC1_CFG_SEMAPHORE & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_STATUS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + pb_addr = (mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH & PROT_BITS_OFFS) >> 7) << 2; @@ -882,6 +890,10 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) mask |= 1 << ((mmTPC1_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); mask |= 1 << ((mmTPC1_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); mask |= 1 << ((mmTPC1_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_TPC_INTR_MASK & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -1057,6 +1069,16 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) goya_pb_set_block(hdev, mmTPC2_RD_REGULATOR_BASE); goya_pb_set_block(hdev, mmTPC2_WR_REGULATOR_BASE); + pb_addr = (mmTPC2_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2; + + mask = 1 << ((mmTPC2_CFG_SEMAPHORE & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_STATUS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + pb_addr = (mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH & PROT_BITS_OFFS) >> 7) << 2; @@ -1064,6 +1086,10 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) mask |= 1 << ((mmTPC2_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); mask |= 1 << ((mmTPC2_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); mask |= 1 << ((mmTPC2_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_TPC_INTR_MASK & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -1239,6 +1265,16 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) goya_pb_set_block(hdev, mmTPC3_RD_REGULATOR_BASE); goya_pb_set_block(hdev, mmTPC3_WR_REGULATOR_BASE); + pb_addr = (mmTPC3_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2; + + mask = 1 << ((mmTPC3_CFG_SEMAPHORE & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_STATUS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + pb_addr = (mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH & PROT_BITS_OFFS) >> 7) << 2; @@ -1246,6 +1282,10 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) mask |= 1 << ((mmTPC3_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); mask |= 1 << ((mmTPC3_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); mask |= 1 << ((mmTPC3_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_TPC_INTR_MASK & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -1421,6 +1461,16 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) goya_pb_set_block(hdev, mmTPC4_RD_REGULATOR_BASE); goya_pb_set_block(hdev, mmTPC4_WR_REGULATOR_BASE); + pb_addr = (mmTPC4_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2; + + mask = 1 << ((mmTPC4_CFG_SEMAPHORE & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_STATUS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + pb_addr = (mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH & PROT_BITS_OFFS) >> 7) << 2; @@ -1428,6 +1478,10 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) mask |= 1 << ((mmTPC4_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); mask |= 1 << ((mmTPC4_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); mask |= 1 << ((mmTPC4_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_TPC_INTR_MASK & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -1603,6 +1657,16 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) goya_pb_set_block(hdev, mmTPC5_RD_REGULATOR_BASE); goya_pb_set_block(hdev, mmTPC5_WR_REGULATOR_BASE); + pb_addr = (mmTPC5_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2; + + mask = 1 << ((mmTPC5_CFG_SEMAPHORE & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_STATUS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + pb_addr = (mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH & PROT_BITS_OFFS) >> 7) << 2; @@ -1610,6 +1674,10 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) mask |= 1 << ((mmTPC5_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); mask |= 1 << ((mmTPC5_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); mask |= 1 << ((mmTPC5_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_TPC_INTR_MASK & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -1785,6 +1853,16 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) goya_pb_set_block(hdev, mmTPC6_RD_REGULATOR_BASE); goya_pb_set_block(hdev, mmTPC6_WR_REGULATOR_BASE); + pb_addr = (mmTPC6_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2; + + mask = 1 << ((mmTPC6_CFG_SEMAPHORE & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_STATUS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + pb_addr = (mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH & PROT_BITS_OFFS) >> 7) << 2; @@ -1792,6 +1870,10 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) mask |= 1 << ((mmTPC6_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); mask |= 1 << ((mmTPC6_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); mask |= 1 << ((mmTPC6_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_TPC_INTR_MASK & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -1967,6 +2049,16 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) goya_pb_set_block(hdev, mmTPC7_RD_REGULATOR_BASE); goya_pb_set_block(hdev, mmTPC7_WR_REGULATOR_BASE); + pb_addr = (mmTPC7_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2; + + mask = 1 << ((mmTPC7_CFG_SEMAPHORE & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_STATUS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + pb_addr = (mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH & PROT_BITS_OFFS) >> 7) << 2; @@ -1974,6 +2066,10 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) mask |= 1 << ((mmTPC7_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); mask |= 1 << ((mmTPC7_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); mask |= 1 << ((mmTPC7_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_TPC_INTR_MASK & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); diff --git a/drivers/misc/habanalabs/habanalabs.h b/drivers/misc/habanalabs/habanalabs.h index 31ebcf9458fe..1ecdcf8b763a 100644 --- a/drivers/misc/habanalabs/habanalabs.h +++ b/drivers/misc/habanalabs/habanalabs.h @@ -23,7 +23,9 @@ #define HL_MMAP_CB_MASK (0x8000000000000000ull >> PAGE_SHIFT) -#define HL_PENDING_RESET_PER_SEC 5 +#define HL_PENDING_RESET_PER_SEC 30 + +#define HL_HARD_RESET_MAX_TIMEOUT 120 #define HL_DEVICE_TIMEOUT_USEC 1000000 /* 1 s */ @@ -51,6 +53,14 @@ /* MMU */ #define MMU_HASH_TABLE_BITS 7 /* 1 << 7 buckets */ +#define HL_RSVD_SOBS 4 +#define HL_RSVD_MONS 2 + +#define HL_RSVD_SOBS_IN_USE 2 +#define HL_RSVD_MONS_IN_USE 1 + +#define HL_MAX_SOB_VAL (1 << 15) + /** * struct pgt_info - MMU hop page info. * @node: hash linked-list node for the pgts shadow hash of pgts. @@ -75,6 +85,16 @@ struct pgt_info { struct hl_device; struct hl_fpriv; +/** + * enum hl_fw_component - F/W components to read version through registers. + * @FW_COMP_UBOOT: u-boot. + * @FW_COMP_PREBOOT: preboot. + */ +enum hl_fw_component { + FW_COMP_UBOOT, + FW_COMP_PREBOOT +}; + /** * enum hl_queue_type - Supported QUEUE types. * @QUEUE_TYPE_NA: queue is not available. @@ -94,6 +114,26 @@ enum hl_queue_type { QUEUE_TYPE_HW }; +enum hl_cs_type { + CS_TYPE_DEFAULT, + CS_TYPE_SIGNAL, + CS_TYPE_WAIT +}; + +/* + * struct hl_hw_sob - H/W SOB info. + * @hdev: habanalabs device structure. + * @kref: refcount of this SOB. The SOB will reset once the refcount is zero. + * @sob_id: id of this SOB. + * @q_idx: the H/W queue that uses this SOB. + */ +struct hl_hw_sob { + struct hl_device *hdev; + struct kref kref; + u32 sob_id; + u32 q_idx; +}; + /** * struct hw_queue_properties - queue information. * @type: queue type. @@ -250,17 +290,23 @@ struct asic_fixed_properties { }; /** - * struct hl_dma_fence - wrapper for fence object used by command submissions. + * struct hl_cs_compl - command submission completion object. * @base_fence: kernel fence object. * @lock: spinlock to protect fence. * @hdev: habanalabs device structure. + * @hw_sob: the H/W SOB used in this signal/wait CS. * @cs_seq: command submission sequence number. + * @type: type of the CS - signal/wait. + * @sob_val: the SOB value that is used in this signal/wait CS. */ -struct hl_dma_fence { +struct hl_cs_compl { struct dma_fence base_fence; spinlock_t lock; struct hl_device *hdev; + struct hl_hw_sob *hw_sob; u64 cs_seq; + enum hl_cs_type type; + u16 sob_val; }; /* @@ -358,6 +404,7 @@ struct hl_cs_job; /** * struct hl_hw_queue - describes a H/W transport queue. + * @hw_sob: array of the used H/W SOBs by this H/W queue. * @shadow_queue: pointer to a shadow queue that holds pointers to jobs. * @queue_type: type of queue. * @kernel_address: holds the queue's kernel virtual address. @@ -365,11 +412,19 @@ struct hl_cs_job; * @pi: holds the queue's pi value. * @ci: holds the queue's ci value, AS CALCULATED BY THE DRIVER (not real ci). * @hw_queue_id: the id of the H/W queue. + * @cq_id: the id for the corresponding CQ for this H/W queue. + * @msi_vec: the IRQ number of the H/W queue. * @int_queue_len: length of internal queue (number of entries). + * @next_sob_val: the next value to use for the currently used SOB. + * @base_sob_id: the base SOB id of the SOBs used by this queue. + * @base_mon_id: the base MON id of the MONs used by this queue. * @valid: is the queue valid (we have array of 32 queues, not all of them - * exists). + * exist). + * @curr_sob_offset: the id offset to the currently used SOB from the + * HL_RSVD_SOBS that are being used by this queue. */ struct hl_hw_queue { + struct hl_hw_sob hw_sob[HL_RSVD_SOBS]; struct hl_cs_job **shadow_queue; enum hl_queue_type queue_type; u64 kernel_address; @@ -377,8 +432,14 @@ struct hl_hw_queue { u32 pi; u32 ci; u32 hw_queue_id; + u32 cq_id; + u32 msi_vec; u16 int_queue_len; + u16 next_sob_val; + u16 base_sob_id; + u16 base_mon_id; u8 valid; + u8 curr_sob_offset; }; /** @@ -517,6 +578,8 @@ enum hl_pll_frequency { * @mmu_invalidate_cache_range: flush specific MMU STLB cache lines with * ASID-VA-size mask. * @send_heartbeat: send is-alive packet to ArmCP and verify response. + * @enable_clock_gating: enable clock gating for reducing power consumption. + * @disable_clock_gating: disable clock for accessing registers on HBW. * @debug_coresight: perform certain actions on Coresight for debugging. * @is_device_idle: return true if device is idle, false otherwise. * @soft_reset_late_init: perform certain actions needed after soft reset. @@ -534,6 +597,21 @@ enum hl_pll_frequency { * @wreg: Write a register. Needed for simulator support. * @halt_coresight: stop the ETF and ETR traces. * @get_clk_rate: Retrieve the ASIC current and maximum clock rate in MHz + * @get_queue_id_for_cq: Get the H/W queue id related to the given CQ index. + * @read_device_fw_version: read the device's firmware versions that are + * contained in registers + * @load_firmware_to_device: load the firmware to the device's memory + * @load_boot_fit_to_device: load boot fit to device's memory + * @ext_queue_init: Initialize the given external queue. + * @ext_queue_reset: Reset the given external queue. + * @get_signal_cb_size: Get signal CB size. + * @get_wait_cb_size: Get wait CB size. + * @gen_signal_cb: Generate a signal CB. + * @gen_wait_cb: Generate a wait CB. + * @reset_sob: Reset a SOB. + * @set_dma_mask_from_fw: set the DMA mask in the driver according to the + * firmware configuration + * @get_device_time: Get the device time. */ struct hl_asic_funcs { int (*early_init)(struct hl_device *hdev); @@ -578,7 +656,8 @@ struct hl_asic_funcs { struct sg_table *sgt); void (*add_end_of_cb_packets)(struct hl_device *hdev, u64 kernel_address, u32 len, - u64 cq_addr, u32 cq_val, u32 msix_num); + u64 cq_addr, u32 cq_val, u32 msix_num, + bool eb); void (*update_eq_ci)(struct hl_device *hdev, u32 val); int (*context_switch)(struct hl_device *hdev, u32 asid); void (*restore_phase_topology)(struct hl_device *hdev); @@ -596,11 +675,13 @@ struct hl_asic_funcs { u32 *size); u64 (*read_pte)(struct hl_device *hdev, u64 addr); void (*write_pte)(struct hl_device *hdev, u64 addr, u64 val); - void (*mmu_invalidate_cache)(struct hl_device *hdev, bool is_hard, + int (*mmu_invalidate_cache)(struct hl_device *hdev, bool is_hard, u32 flags); - void (*mmu_invalidate_cache_range)(struct hl_device *hdev, bool is_hard, + int (*mmu_invalidate_cache_range)(struct hl_device *hdev, bool is_hard, u32 asid, u64 va, u64 size); int (*send_heartbeat)(struct hl_device *hdev); + void (*enable_clock_gating)(struct hl_device *hdev); + void (*disable_clock_gating)(struct hl_device *hdev); int (*debug_coresight)(struct hl_device *hdev, void *data); bool (*is_device_idle)(struct hl_device *hdev, u32 *mask, struct seq_file *s); @@ -620,6 +701,21 @@ struct hl_asic_funcs { void (*wreg)(struct hl_device *hdev, u32 reg, u32 val); void (*halt_coresight)(struct hl_device *hdev); int (*get_clk_rate)(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk); + u32 (*get_queue_id_for_cq)(struct hl_device *hdev, u32 cq_idx); + void (*read_device_fw_version)(struct hl_device *hdev, + enum hl_fw_component fwc); + int (*load_firmware_to_device)(struct hl_device *hdev); + int (*load_boot_fit_to_device)(struct hl_device *hdev); + void (*ext_queue_init)(struct hl_device *hdev, u32 hw_queue_id); + void (*ext_queue_reset)(struct hl_device *hdev, u32 hw_queue_id); + u32 (*get_signal_cb_size)(struct hl_device *hdev); + u32 (*get_wait_cb_size)(struct hl_device *hdev); + void (*gen_signal_cb)(struct hl_device *hdev, void *data, u16 sob_id); + void (*gen_wait_cb)(struct hl_device *hdev, void *data, u16 sob_id, + u16 sob_val, u16 mon_id, u32 q_idx); + void (*reset_sob)(struct hl_device *hdev, void *data); + void (*set_dma_mask_from_fw)(struct hl_device *hdev); + u64 (*get_device_time)(struct hl_device *hdev); }; @@ -659,8 +755,8 @@ struct hl_va_range { * with huge pages. * @dram_va_range: holds available virtual addresses for DRAM mappings. * @mem_hash_lock: protects the mem_hash. - * @mmu_lock: protects the MMU page tables. Any change to the PGT, modifing the - * MMU hash or walking the PGT requires talking this lock + * @mmu_lock: protects the MMU page tables. Any change to the PGT, modifying the + * MMU hash or walking the PGT requires talking this lock. * @debugfs_list: node in debugfs list of contexts. * @cs_sequence: sequence number for CS. Value is assigned to a CS and passed * to user so user could inquire about CS. It is used as @@ -751,10 +847,14 @@ struct hl_userptr { * @job_lock: spinlock for the CS's jobs list. Needed for free_job. * @refcount: reference counter for usage of the CS. * @fence: pointer to the fence object of this CS. + * @signal_fence: pointer to the fence object of the signal CS (used by wait + * CS only). + * @finish_work: workqueue object to run when CS is completed by H/W. * @work_tdr: delayed work node for TDR. * @mirror_node : node in device mirror list of command submissions. * @debugfs_list: node in debugfs list of command submissions. * @sequence: the sequence number of this CS. + * @type: CS_TYPE_*. * @submitted: true if CS was submitted to H/W. * @completed: true if CS was completed by device. * @timedout : true if CS was timedout. @@ -769,10 +869,13 @@ struct hl_cs { spinlock_t job_lock; struct kref refcount; struct dma_fence *fence; + struct dma_fence *signal_fence; + struct work_struct finish_work; struct delayed_work work_tdr; struct list_head mirror_node; struct list_head debugfs_list; u64 sequence; + enum hl_cs_type type; u8 submitted; u8 completed; u8 timedout; @@ -799,6 +902,12 @@ struct hl_cs { * @is_kernel_allocated_cb: true if the CB handle we got from the user holds a * handle to a kernel-allocated CB object, false * otherwise (SRAM/DRAM/host address). + * @contains_dma_pkt: whether the JOB contains at least one DMA packet. This + * info is needed later, when adding the 2xMSG_PROT at the + * end of the JOB, to know which barriers to put in the + * MSG_PROT packets. Relevant only for GAUDI as GOYA doesn't + * have streams so the engine can't be busy by another + * stream. */ struct hl_cs_job { struct list_head cs_node; @@ -814,6 +923,7 @@ struct hl_cs_job { u32 user_cb_size; u32 job_cb_size; u8 is_kernel_allocated_cb; + u8 contains_dma_pkt; }; /** @@ -833,6 +943,12 @@ struct hl_cs_job { * @is_kernel_allocated_cb: true if the CB handle we got from the user holds a * handle to a kernel-allocated CB object, false * otherwise (SRAM/DRAM/host address). + * @contains_dma_pkt: whether the JOB contains at least one DMA packet. This + * info is needed later, when adding the 2xMSG_PROT at the + * end of the JOB, to know which barriers to put in the + * MSG_PROT packets. Relevant only for GAUDI as GOYA doesn't + * have streams so the engine can't be busy by another + * stream. */ struct hl_cs_parser { struct hl_cb *user_cb; @@ -846,6 +962,7 @@ struct hl_cs_parser { u32 patched_cb_size; u8 job_id; u8 is_kernel_allocated_cb; + u8 contains_dma_pkt; }; @@ -1093,6 +1210,16 @@ void hl_wreg(struct hl_device *hdev, u32 reg, u32 val); #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) +#define RMWREG32(reg, val, mask) \ + do { \ + u32 tmp_ = RREG32(reg); \ + tmp_ &= ~(mask); \ + tmp_ |= ((val) << __ffs(mask)); \ + WREG32(reg, tmp_); \ + } while (0) + +#define RREG32_MASK(reg, mask) ((RREG32(reg) & mask) >> __ffs(mask)) + #define REG_FIELD_SHIFT(reg, field) reg##_##field##_SHIFT #define REG_FIELD_MASK(reg, field) reg##_##field##_MASK #define WREG32_FIELD(reg, offset, field, val) \ @@ -1282,6 +1409,8 @@ struct hl_device_idle_busy_ts { * @idle_busy_ts_idx: index of current entry in idle_busy_ts_arr * @id: device minor. * @id_control: minor of the control device + * @cpu_pci_msb_addr: 50-bit extension bits for the device CPU's 40-bit + * addresses. * @disabled: is device disabled. * @late_init_done: is late init stage was done during initialization. * @hwmon_initialized: is H/W monitor sensors was initialized. @@ -1295,11 +1424,19 @@ struct hl_device_idle_busy_ts { * huge pages. * @init_done: is the initialization of the device done. * @mmu_enable: is MMU enabled. + * @mmu_huge_page_opt: is MMU huge pages optimization enabled. + * @clock_gating: is clock gating enabled. * @device_cpu_disabled: is the device CPU disabled (due to timeouts) * @dma_mask: the dma mask that was set for this device * @in_debug: is device under debug. This, together with fpriv_list, enforces * that only a single user is configuring the debug infrastructure. + * @power9_64bit_dma_enable: true to enable 64-bit DMA mask support. Relevant + * only to POWER9 machines. * @cdev_sysfs_created: were char devices and sysfs nodes created. + * @stop_on_err: true if engines should stop on error. + * @supports_sync_stream: is sync stream supported. + * @supports_coresight: is CoreSight supported. + * @supports_soft_reset: is soft reset supported. */ struct hl_device { struct pci_dev *pdev; @@ -1366,6 +1503,7 @@ struct hl_device { u32 idle_busy_ts_idx; u16 id; u16 id_control; + u16 cpu_pci_msb_addr; u8 disabled; u8 late_init_done; u8 hwmon_initialized; @@ -1376,18 +1514,31 @@ struct hl_device { u8 dram_default_page_mapping; u8 pmmu_huge_range; u8 init_done; + u8 clock_gating; u8 device_cpu_disabled; u8 dma_mask; u8 in_debug; + u8 power9_64bit_dma_enable; u8 cdev_sysfs_created; + u8 stop_on_err; + u8 supports_sync_stream; + u8 supports_coresight; + u8 supports_soft_reset; /* Parameters for bring-up */ u8 mmu_enable; + u8 mmu_huge_page_opt; u8 cpu_enable; u8 reset_pcilink; u8 cpu_queues_enable; u8 fw_loading; u8 pldm; + u8 axi_drain; + u8 sram_scrambler_enable; + u8 dram_scrambler_enable; + u8 hard_reset_on_fw_events; + u8 bmc_enable; + u8 rl_enable; }; @@ -1554,8 +1705,10 @@ int hl_cb_pool_fini(struct hl_device *hdev); void hl_cs_rollback_all(struct hl_device *hdev); struct hl_cs_job *hl_cs_allocate_job(struct hl_device *hdev, enum hl_queue_type queue_type, bool is_kernel_allocated_cb); +void hl_sob_reset_error(struct kref *ref); void goya_set_asic_funcs(struct hl_device *hdev); +void gaudi_set_asic_funcs(struct hl_device *hdev); int hl_vm_ctx_init(struct hl_ctx *ctx); void hl_vm_ctx_fini(struct hl_ctx *ctx); @@ -1583,11 +1736,14 @@ int hl_mmu_unmap(struct hl_ctx *ctx, u64 virt_addr, u32 page_size, void hl_mmu_swap_out(struct hl_ctx *ctx); void hl_mmu_swap_in(struct hl_ctx *ctx); -int hl_fw_push_fw_to_device(struct hl_device *hdev, const char *fw_name, +int hl_fw_load_fw_to_device(struct hl_device *hdev, const char *fw_name, void __iomem *dst); int hl_fw_send_pci_access_msg(struct hl_device *hdev, u32 opcode); int hl_fw_send_cpu_message(struct hl_device *hdev, u32 hw_queue_id, u32 *msg, u16 len, u32 timeout, long *result); +int hl_fw_unmask_irq(struct hl_device *hdev, u16 event_type); +int hl_fw_unmask_irq_arr(struct hl_device *hdev, const u32 *irq_arr, + size_t irq_arr_size); int hl_fw_test_cpu_queue(struct hl_device *hdev); void *hl_fw_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size, dma_addr_t *dma_handle); @@ -1596,6 +1752,10 @@ void hl_fw_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size, int hl_fw_send_heartbeat(struct hl_device *hdev); int hl_fw_armcp_info_get(struct hl_device *hdev); int hl_fw_get_eeprom_data(struct hl_device *hdev, void *data, size_t max_size); +int hl_fw_init_cpu(struct hl_device *hdev, u32 cpu_boot_status_reg, + u32 msg_to_cpu_reg, u32 cpu_msg_status_reg, + u32 boot_err0_reg, bool skip_bmc, + u32 cpu_timeout, u32 boot_fit_timeout); int hl_pci_bars_map(struct hl_device *hdev, const char * const name[3], bool is_wc[3]); @@ -1605,9 +1765,8 @@ int hl_pci_set_dram_bar_base(struct hl_device *hdev, u8 inbound_region, u8 bar, int hl_pci_init_iatu(struct hl_device *hdev, u64 sram_base_address, u64 dram_base_address, u64 host_phys_base_address, u64 host_phys_size); -int hl_pci_init(struct hl_device *hdev, u8 dma_mask); +int hl_pci_init(struct hl_device *hdev); void hl_pci_fini(struct hl_device *hdev); -int hl_pci_set_dma_mask(struct hl_device *hdev, u8 dma_mask); long hl_get_frequency(struct hl_device *hdev, u32 pll_index, bool curr); void hl_set_frequency(struct hl_device *hdev, u32 pll_index, u64 freq); @@ -1627,6 +1786,10 @@ void hl_set_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr, long value); u64 hl_get_max_power(struct hl_device *hdev); void hl_set_max_power(struct hl_device *hdev, u64 value); +int hl_set_voltage(struct hl_device *hdev, + int sensor_index, u32 attr, long value); +int hl_set_current(struct hl_device *hdev, + int sensor_index, u32 attr, long value); #ifdef CONFIG_DEBUG_FS diff --git a/drivers/misc/habanalabs/habanalabs_drv.c b/drivers/misc/habanalabs/habanalabs_drv.c index b670859c677a..8652c7e5d7f1 100644 --- a/drivers/misc/habanalabs/habanalabs_drv.c +++ b/drivers/misc/habanalabs/habanalabs_drv.c @@ -47,6 +47,7 @@ static const struct pci_device_id ids[] = { { PCI_DEVICE(PCI_VENDOR_ID_HABANALABS, PCI_IDS_GAUDI), }, { 0, } }; +MODULE_DEVICE_TABLE(pci, ids); /* * get_asic_type - translate device id to asic type @@ -171,6 +172,7 @@ out_err: put_pid(hpriv->taskpid); kfree(hpriv); + return rc; } @@ -230,8 +232,15 @@ static void set_driver_behavior_per_device(struct hl_device *hdev) hdev->fw_loading = 1; hdev->cpu_queues_enable = 1; hdev->heartbeat = 1; + hdev->clock_gating = 1; hdev->reset_pcilink = 0; + hdev->axi_drain = 0; + hdev->sram_scrambler_enable = 1; + hdev->dram_scrambler_enable = 1; + hdev->rl_enable = 1; + hdev->bmc_enable = 1; + hdev->hard_reset_on_fw_events = 1; } /* @@ -267,11 +276,6 @@ int create_hdev(struct hl_device **dev, struct pci_dev *pdev, dev_err(&pdev->dev, "Unsupported ASIC\n"); rc = -ENODEV; goto free_hdev; - } else if (hdev->asic_type == ASIC_GAUDI) { - dev_err(&pdev->dev, - "GAUDI is not supported by the current kernel\n"); - rc = -ENODEV; - goto free_hdev; } } else { hdev->asic_type = asic_type; diff --git a/drivers/misc/habanalabs/habanalabs_ioctl.c b/drivers/misc/habanalabs/habanalabs_ioctl.c index 6474b868ef27..52eedd3a6c3a 100644 --- a/drivers/misc/habanalabs/habanalabs_ioctl.c +++ b/drivers/misc/habanalabs/habanalabs_ioctl.c @@ -71,6 +71,8 @@ static int hw_ip_info(struct hl_device *hdev, struct hl_info_args *args) min(CARD_NAME_MAX_LEN, HL_INFO_CARD_NAME_MAX_LEN)); hw_ip.armcp_cpld_version = le32_to_cpu(prop->armcp_info.cpld_version); + hw_ip.module_id = le32_to_cpu(prop->armcp_info.card_location); + hw_ip.psoc_pci_pll_nr = prop->psoc_pci_pll_nr; hw_ip.psoc_pci_pll_nf = prop->psoc_pci_pll_nf; hw_ip.psoc_pci_pll_od = prop->psoc_pci_pll_od; @@ -258,6 +260,22 @@ static int get_reset_count(struct hl_device *hdev, struct hl_info_args *args) min((size_t) max_size, sizeof(reset_count))) ? -EFAULT : 0; } +static int time_sync_info(struct hl_device *hdev, struct hl_info_args *args) +{ + struct hl_info_time_sync time_sync = {0}; + u32 max_size = args->return_size; + void __user *out = (void __user *) (uintptr_t) args->return_pointer; + + if ((!max_size) || (!out)) + return -EINVAL; + + time_sync.device_time = hdev->asic_funcs->get_device_time(hdev); + time_sync.host_time = ktime_get_raw_ns(); + + return copy_to_user(out, &time_sync, + min((size_t) max_size, sizeof(time_sync))) ? -EFAULT : 0; +} + static int _hl_info_ioctl(struct hl_fpriv *hpriv, void *data, struct device *dev) { @@ -315,6 +333,9 @@ static int _hl_info_ioctl(struct hl_fpriv *hpriv, void *data, rc = get_clk_rate(hdev, args); break; + case HL_INFO_TIME_SYNC: + return time_sync_info(hdev, args); + default: dev_err(dev, "Invalid request %d\n", args->op); rc = -ENOTTY; diff --git a/drivers/misc/habanalabs/hw_queue.c b/drivers/misc/habanalabs/hw_queue.c index 91579dde9262..f4434b39ef1b 100644 --- a/drivers/misc/habanalabs/hw_queue.c +++ b/drivers/misc/habanalabs/hw_queue.c @@ -111,7 +111,7 @@ static int ext_queue_sanity_checks(struct hl_device *hdev, bool reserve_cq_entry) { atomic_t *free_slots = - &hdev->completion_queue[q->hw_queue_id].free_slots_cnt; + &hdev->completion_queue[q->cq_id].free_slots_cnt; int free_slots_cnt; /* Check we have enough space in the queue */ @@ -194,7 +194,7 @@ static int hw_queue_sanity_checks(struct hl_device *hdev, struct hl_hw_queue *q, int num_of_entries) { atomic_t *free_slots = - &hdev->completion_queue[q->hw_queue_id].free_slots_cnt; + &hdev->completion_queue[q->cq_id].free_slots_cnt; /* * Check we have enough space in the completion queue. @@ -308,13 +308,14 @@ static void ext_queue_schedule_job(struct hl_cs_job *job) * No need to check if CQ is full because it was already * checked in ext_queue_sanity_checks */ - cq = &hdev->completion_queue[q->hw_queue_id]; + cq = &hdev->completion_queue[q->cq_id]; cq_addr = cq->bus_address + cq->pi * sizeof(struct hl_cq_entry); hdev->asic_funcs->add_end_of_cb_packets(hdev, cb->kernel_address, len, cq_addr, le32_to_cpu(cq_pkt.data), - q->hw_queue_id); + q->msi_vec, + job->contains_dma_pkt); q->shadow_queue[hl_pi_2_offset(q->pi)] = job; @@ -401,21 +402,111 @@ static void hw_queue_schedule_job(struct hl_cs_job *job) * No need to check if CQ is full because it was already * checked in hw_queue_sanity_checks */ - cq = &hdev->completion_queue[q->hw_queue_id]; + cq = &hdev->completion_queue[q->cq_id]; + cq->pi = hl_cq_inc_ptr(cq->pi); ext_and_hw_queue_submit_bd(hdev, q, ctl, len, ptr); } +/* + * init_signal_wait_cs - initialize a signal/wait CS + * @cs: pointer to the signal/wait CS + * + * H/W queues spinlock should be taken before calling this function + */ +static void init_signal_wait_cs(struct hl_cs *cs) +{ + struct hl_ctx *ctx = cs->ctx; + struct hl_device *hdev = ctx->hdev; + struct hl_hw_queue *hw_queue; + struct hl_cs_compl *cs_cmpl = + container_of(cs->fence, struct hl_cs_compl, base_fence); + + struct hl_hw_sob *hw_sob; + struct hl_cs_job *job; + u32 q_idx; + + /* There is only one job in a signal/wait CS */ + job = list_first_entry(&cs->job_list, struct hl_cs_job, + cs_node); + q_idx = job->hw_queue_id; + hw_queue = &hdev->kernel_queues[q_idx]; + + if (cs->type & CS_TYPE_SIGNAL) { + hw_sob = &hw_queue->hw_sob[hw_queue->curr_sob_offset]; + + cs_cmpl->hw_sob = hw_sob; + cs_cmpl->sob_val = hw_queue->next_sob_val++; + + dev_dbg(hdev->dev, + "generate signal CB, sob_id: %d, sob val: 0x%x, q_idx: %d\n", + cs_cmpl->hw_sob->sob_id, cs_cmpl->sob_val, q_idx); + + hdev->asic_funcs->gen_signal_cb(hdev, job->patched_cb, + cs_cmpl->hw_sob->sob_id); + + kref_get(&hw_sob->kref); + + /* check for wraparound */ + if (hw_queue->next_sob_val == HL_MAX_SOB_VAL) { + /* + * Decrement as we reached the max value. + * The release function won't be called here as we've + * just incremented the refcount. + */ + kref_put(&hw_sob->kref, hl_sob_reset_error); + hw_queue->next_sob_val = 1; + /* only two SOBs are currently in use */ + hw_queue->curr_sob_offset = + (hw_queue->curr_sob_offset + 1) % + HL_RSVD_SOBS_IN_USE; + + dev_dbg(hdev->dev, "switched to SOB %d, q_idx: %d\n", + hw_queue->curr_sob_offset, q_idx); + } + } else if (cs->type & CS_TYPE_WAIT) { + struct hl_cs_compl *signal_cs_cmpl; + + signal_cs_cmpl = container_of(cs->signal_fence, + struct hl_cs_compl, + base_fence); + + /* copy the the SOB id and value of the signal CS */ + cs_cmpl->hw_sob = signal_cs_cmpl->hw_sob; + cs_cmpl->sob_val = signal_cs_cmpl->sob_val; + + dev_dbg(hdev->dev, + "generate wait CB, sob_id: %d, sob_val: 0x%x, mon_id: %d, q_idx: %d\n", + cs_cmpl->hw_sob->sob_id, cs_cmpl->sob_val, + hw_queue->base_mon_id, q_idx); + + hdev->asic_funcs->gen_wait_cb(hdev, job->patched_cb, + cs_cmpl->hw_sob->sob_id, + cs_cmpl->sob_val, + hw_queue->base_mon_id, + q_idx); + + kref_get(&cs_cmpl->hw_sob->kref); + /* + * Must put the signal fence after the SOB refcnt increment so + * the SOB refcnt won't turn 0 and reset the SOB before the + * wait CS was submitted. + */ + mb(); + dma_fence_put(cs->signal_fence); + cs->signal_fence = NULL; + } +} + /* * hl_hw_queue_schedule_cs - schedule a command submission - * - * @job : pointer to the CS - * + * @cs: pointer to the CS */ int hl_hw_queue_schedule_cs(struct hl_cs *cs) { - struct hl_device *hdev = cs->ctx->hdev; + struct hl_ctx *ctx = cs->ctx; + struct hl_device *hdev = ctx->hdev; struct hl_cs_job *job, *tmp; struct hl_hw_queue *q; int rc = 0, i, cq_cnt; @@ -461,6 +552,9 @@ int hl_hw_queue_schedule_cs(struct hl_cs *cs) } } + if ((cs->type == CS_TYPE_SIGNAL) || (cs->type == CS_TYPE_WAIT)) + init_signal_wait_cs(cs); + spin_lock(&hdev->hw_queues_mirror_lock); list_add_tail(&cs->mirror_node, &hdev->hw_queues_mirror_list); @@ -569,6 +663,9 @@ static int ext_and_cpu_queue_init(struct hl_device *hdev, struct hl_hw_queue *q, q->ci = 0; q->pi = 0; + if (!is_cpu_queue) + hdev->asic_funcs->ext_queue_init(hdev, q->hw_queue_id); + return 0; free_queue: @@ -791,5 +888,8 @@ void hl_hw_queue_reset(struct hl_device *hdev, bool hard_reset) ((!hard_reset) && (q->queue_type == QUEUE_TYPE_CPU))) continue; q->pi = q->ci = 0; + + if (q->queue_type == QUEUE_TYPE_EXT) + hdev->asic_funcs->ext_queue_reset(hdev, q->hw_queue_id); } } diff --git a/drivers/misc/habanalabs/hwmon.c b/drivers/misc/habanalabs/hwmon.c index a21a26e07c3b..8c6cd77e6af6 100644 --- a/drivers/misc/habanalabs/hwmon.c +++ b/drivers/misc/habanalabs/hwmon.c @@ -200,6 +200,7 @@ static int hl_write(struct device *dev, enum hwmon_sensor_types type, case hwmon_temp: switch (attr) { case hwmon_temp_offset: + case hwmon_temp_reset_history: break; default: return -EINVAL; @@ -216,6 +217,24 @@ static int hl_write(struct device *dev, enum hwmon_sensor_types type, } hl_set_pwm_info(hdev, channel, attr, val); break; + case hwmon_in: + switch (attr) { + case hwmon_in_reset_history: + break; + default: + return -EINVAL; + } + hl_set_voltage(hdev, channel, attr, val); + break; + case hwmon_curr: + switch (attr) { + case hwmon_curr_reset_history: + break; + default: + return -EINVAL; + } + hl_set_current(hdev, channel, attr, val); + break; default: return -EINVAL; } @@ -237,6 +256,8 @@ static umode_t hl_is_visible(const void *data, enum hwmon_sensor_types type, return 0444; case hwmon_temp_offset: return 0644; + case hwmon_temp_reset_history: + return 0200; } break; case hwmon_in: @@ -246,6 +267,8 @@ static umode_t hl_is_visible(const void *data, enum hwmon_sensor_types type, case hwmon_in_max: case hwmon_in_highest: return 0444; + case hwmon_in_reset_history: + return 0200; } break; case hwmon_curr: @@ -255,6 +278,8 @@ static umode_t hl_is_visible(const void *data, enum hwmon_sensor_types type, case hwmon_curr_max: case hwmon_curr_highest: return 0444; + case hwmon_curr_reset_history: + return 0200; } break; case hwmon_fan: @@ -462,6 +487,56 @@ void hl_set_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr, sensor_index, rc); } +int hl_set_voltage(struct hl_device *hdev, + int sensor_index, u32 attr, long value) +{ + struct armcp_packet pkt; + int rc; + + memset(&pkt, 0, sizeof(pkt)); + + pkt.ctl = cpu_to_le32(ARMCP_PACKET_VOLTAGE_SET << + ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.sensor_index = __cpu_to_le16(sensor_index); + pkt.type = __cpu_to_le16(attr); + pkt.value = __cpu_to_le64(value); + + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), + SENSORS_PKT_TIMEOUT, NULL); + + if (rc) + dev_err(hdev->dev, + "Failed to set voltage of sensor %d, error %d\n", + sensor_index, rc); + + return rc; +} + +int hl_set_current(struct hl_device *hdev, + int sensor_index, u32 attr, long value) +{ + struct armcp_packet pkt; + int rc; + + memset(&pkt, 0, sizeof(pkt)); + + pkt.ctl = cpu_to_le32(ARMCP_PACKET_CURRENT_SET << + ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.sensor_index = __cpu_to_le16(sensor_index); + pkt.type = __cpu_to_le16(attr); + pkt.value = __cpu_to_le64(value); + + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), + SENSORS_PKT_TIMEOUT, NULL); + + if (rc) + dev_err(hdev->dev, + "Failed to set current of sensor %d, error %d\n", + sensor_index, rc); + + return rc; +} + int hl_hwmon_init(struct hl_device *hdev) { struct device *dev = hdev->pdev ? &hdev->pdev->dev : hdev->dev; diff --git a/drivers/misc/habanalabs/include/armcp_if.h b/drivers/misc/habanalabs/include/armcp_if.h index bdd0a4c3a9cf..a34fc39ad87e 100644 --- a/drivers/misc/habanalabs/include/armcp_if.h +++ b/drivers/misc/habanalabs/include/armcp_if.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright 2016-2019 HabanaLabs, Ltd. + * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ @@ -35,7 +35,8 @@ struct hl_eq_entry { enum pq_init_status { PQ_INIT_STATUS_NA = 0, PQ_INIT_STATUS_READY_FOR_CP, - PQ_INIT_STATUS_READY_FOR_HOST + PQ_INIT_STATUS_READY_FOR_HOST, + PQ_INIT_STATUS_READY_FOR_CP_SINGLE_MSI }; /* @@ -193,6 +194,16 @@ enum pq_init_status { * Set the value of the offset property of a specified thermal sensor. * The packet's arguments specify the desired sensor and the field to * set. + * + * ARMCP_PACKET_VOLTAGE_SET - + * Trigger the reset_history property of a specified voltage sensor. + * The packet's arguments specify the desired sensor and the field to + * set. + * + * ARMCP_PACKET_CURRENT_SET - + * Trigger the reset_history property of a specified current sensor. + * The packet's arguments specify the desired sensor and the field to + * set. */ enum armcp_packet_id { @@ -220,6 +231,8 @@ enum armcp_packet_id { ARMCP_PACKET_EEPROM_DATA_GET, /* sysfs */ ARMCP_RESERVED, ARMCP_PACKET_TEMPERATURE_SET, /* sysfs */ + ARMCP_PACKET_VOLTAGE_SET, /* sysfs */ + ARMCP_PACKET_CURRENT_SET, /* sysfs */ }; #define ARMCP_PACKET_FENCE_VAL 0xFE8CE7A5 @@ -288,21 +301,24 @@ enum armcp_temp_type { armcp_temp_crit, armcp_temp_crit_hyst, armcp_temp_offset = 19, - armcp_temp_highest = 22 + armcp_temp_highest = 22, + armcp_temp_reset_history = 23 }; enum armcp_in_attributes { armcp_in_input, armcp_in_min, armcp_in_max, - armcp_in_highest = 7 + armcp_in_highest = 7, + armcp_in_reset_history }; enum armcp_curr_attributes { armcp_curr_input, armcp_curr_min, armcp_curr_max, - armcp_curr_highest = 7 + armcp_curr_highest = 7, + armcp_curr_reset_history }; enum armcp_fan_attributes { @@ -335,11 +351,24 @@ struct armcp_sensor { __le32 flags; }; +/** + * struct armcp_card_types - ASIC card type. + * @armcp_card_type_pci: PCI card. + * @armcp_card_type_pmc: PCI Mezzanine Card. + */ +enum armcp_card_types { + armcp_card_type_pci, + armcp_card_type_pmc +}; + /** * struct armcp_info - Info from ArmCP that is necessary to the host's driver * @sensors: available sensors description. * @kernel_version: ArmCP linux kernel version. * @reserved: reserved field. + * @card_type: card configuration type. + * @card_location: in a server, each card has different connections topology + * depending on its location (relevant for PMC card type) * @cpld_version: CPLD programmed F/W version. * @infineon_version: Infineon main DC-DC version. * @fuse_version: silicon production FUSE information. @@ -351,7 +380,9 @@ struct armcp_sensor { struct armcp_info { struct armcp_sensor sensors[ARMCP_MAX_SENSORS]; __u8 kernel_version[VERSION_MAX_LEN]; - __le32 reserved[3]; + __le32 reserved; + __le32 card_type; + __le32 card_location; __le32 cpld_version; __le32 infineon_version; __u8 fuse_version[VERSION_MAX_LEN]; diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/cpu_if_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/cpu_if_regs.h new file mode 100644 index 000000000000..cf80e31317ad --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/cpu_if_regs.h @@ -0,0 +1,174 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_CPU_IF_REGS_H_ +#define ASIC_REG_CPU_IF_REGS_H_ + +/* + ***************************************** + * CPU_IF (Prototype: CPU_IF) + ***************************************** + */ + +#define mmCPU_IF_ARUSER_OVR 0x442104 + +#define mmCPU_IF_ARUSER_OVR_EN 0x442108 + +#define mmCPU_IF_AWUSER_OVR 0x44210C + +#define mmCPU_IF_AWUSER_OVR_EN 0x442110 + +#define mmCPU_IF_AXCACHE_OVR 0x442114 + +#define mmCPU_IF_LOCK_OVR 0x442118 + +#define mmCPU_IF_PROT_OVR 0x44211C + +#define mmCPU_IF_MAX_OUTSTANDING 0x442120 + +#define mmCPU_IF_EARLY_BRESP_EN 0x442124 + +#define mmCPU_IF_FORCE_RSP_OK 0x442128 + +#define mmCPU_IF_CPU_MSB_ADDR 0x44212C + +#define mmCPU_IF_AXI_SPLIT_INTR 0x442130 + +#define mmCPU_IF_TOTAL_WR_CNT 0x442140 + +#define mmCPU_IF_INFLIGHT_WR_CNT 0x442144 + +#define mmCPU_IF_TOTAL_RD_CNT 0x442150 + +#define mmCPU_IF_INFLIGHT_RD_CNT 0x442154 + +#define mmCPU_IF_PF_PQ_PI 0x442200 + +#define mmCPU_IF_PQ_BASE_ADDR_LOW 0x442204 + +#define mmCPU_IF_PQ_BASE_ADDR_HIGH 0x442208 + +#define mmCPU_IF_PQ_LENGTH 0x44220C + +#define mmCPU_IF_CQ_BASE_ADDR_LOW 0x442210 + +#define mmCPU_IF_CQ_BASE_ADDR_HIGH 0x442214 + +#define mmCPU_IF_CQ_LENGTH 0x442218 + +#define mmCPU_IF_EQ_BASE_ADDR_LOW 0x442220 + +#define mmCPU_IF_EQ_BASE_ADDR_HIGH 0x442224 + +#define mmCPU_IF_EQ_LENGTH 0x442228 + +#define mmCPU_IF_EQ_RD_OFFS 0x44222C + +#define mmCPU_IF_QUEUE_INIT 0x442230 + +#define mmCPU_IF_TPC_SERR_INTR_STS 0x442300 + +#define mmCPU_IF_TPC_SERR_INTR_CLR 0x442304 + +#define mmCPU_IF_TPC_SERR_INTR_MASK 0x442308 + +#define mmCPU_IF_TPC_DERR_INTR_STS 0x442310 + +#define mmCPU_IF_TPC_DERR_INTR_CLR 0x442314 + +#define mmCPU_IF_TPC_DERR_INTR_MASK 0x442318 + +#define mmCPU_IF_DMA_SERR_INTR_STS 0x442320 + +#define mmCPU_IF_DMA_SERR_INTR_CLR 0x442324 + +#define mmCPU_IF_DMA_SERR_INTR_MASK 0x442328 + +#define mmCPU_IF_DMA_DERR_INTR_STS 0x442330 + +#define mmCPU_IF_DMA_DERR_INTR_CLR 0x442334 + +#define mmCPU_IF_DMA_DERR_INTR_MASK 0x442338 + +#define mmCPU_IF_SRAM_SERR_INTR_STS 0x442340 + +#define mmCPU_IF_SRAM_SERR_INTR_CLR 0x442344 + +#define mmCPU_IF_SRAM_SERR_INTR_MASK 0x442348 + +#define mmCPU_IF_SRAM_DERR_INTR_STS 0x442350 + +#define mmCPU_IF_SRAM_DERR_INTR_CLR 0x442354 + +#define mmCPU_IF_SRAM_DERR_INTR_MASK 0x442358 + +#define mmCPU_IF_NIC_SERR_INTR_STS 0x442360 + +#define mmCPU_IF_NIC_SERR_INTR_CLR 0x442364 + +#define mmCPU_IF_NIC_SERR_INTR_MASK 0x442368 + +#define mmCPU_IF_NIC_DERR_INTR_STS 0x442370 + +#define mmCPU_IF_NIC_DERR_INTR_CLR 0x442374 + +#define mmCPU_IF_NIC_DERR_INTR_MASK 0x442378 + +#define mmCPU_IF_DMA_IF_SERR_INTR_STS 0x442380 + +#define mmCPU_IF_DMA_IF_SERR_INTR_CLR 0x442384 + +#define mmCPU_IF_DMA_IF_SERR_INTR_MASK 0x442388 + +#define mmCPU_IF_DMA_IF_DERR_INTR_STS 0x442390 + +#define mmCPU_IF_DMA_IF_DERR_INTR_CLR 0x442394 + +#define mmCPU_IF_DMA_IF_DERR_INTR_MASK 0x442398 + +#define mmCPU_IF_HBM_SERR_INTR_STS 0x4423A0 + +#define mmCPU_IF_HBM_SERR_INTR_CLR 0x4423A4 + +#define mmCPU_IF_HBM_SERR_INTR_MASK 0x4423A8 + +#define mmCPU_IF_HBM_DERR_INTR_STS 0x4423B0 + +#define mmCPU_IF_HBM_DERR_INTR_CLR 0x4423B4 + +#define mmCPU_IF_HBM_DERR_INTR_MASK 0x4423B8 + +#define mmCPU_IF_PLL_SEI_INTR_STS 0x442400 + +#define mmCPU_IF_PLL_SEI_INTR_CLR 0x442404 + +#define mmCPU_IF_PLL_SEI_INTR_MASK 0x442408 + +#define mmCPU_IF_NIC_SEI_INTR_STS 0x442410 + +#define mmCPU_IF_NIC_SEI_INTR_CLR 0x442414 + +#define mmCPU_IF_NIC_SEI_INTR_MASK 0x442418 + +#define mmCPU_IF_DMA_SEI_INTR_STS 0x442420 + +#define mmCPU_IF_DMA_SEI_INTR_CLR 0x442424 + +#define mmCPU_IF_DMA_SEI_INTR_MASK 0x442428 + +#define mmCPU_IF_DMA_IF_SEI_INTR_STS 0x442430 + +#define mmCPU_IF_DMA_IF_SEI_INTR_CLR 0x442434 + +#define mmCPU_IF_DMA_IF_SEI_INTR_MASK 0x442438 + +#endif /* ASIC_REG_CPU_IF_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_core_masks.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_core_masks.h new file mode 100644 index 000000000000..d079a37acab8 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_core_masks.h @@ -0,0 +1,348 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA0_CORE_MASKS_H_ +#define ASIC_REG_DMA0_CORE_MASKS_H_ + +/* + ***************************************** + * DMA0_CORE (Prototype: DMA_CORE) + ***************************************** + */ + +/* DMA0_CORE_CFG_0 */ +#define DMA0_CORE_CFG_0_EN_SHIFT 0 +#define DMA0_CORE_CFG_0_EN_MASK 0x1 + +/* DMA0_CORE_CFG_1 */ +#define DMA0_CORE_CFG_1_HALT_SHIFT 0 +#define DMA0_CORE_CFG_1_HALT_MASK 0x1 +#define DMA0_CORE_CFG_1_FLUSH_SHIFT 1 +#define DMA0_CORE_CFG_1_FLUSH_MASK 0x2 +#define DMA0_CORE_CFG_1_SB_FORCE_MISS_SHIFT 2 +#define DMA0_CORE_CFG_1_SB_FORCE_MISS_MASK 0x4 + +/* DMA0_CORE_LBW_MAX_OUTSTAND */ +#define DMA0_CORE_LBW_MAX_OUTSTAND_VAL_SHIFT 0 +#define DMA0_CORE_LBW_MAX_OUTSTAND_VAL_MASK 0x1F + +/* DMA0_CORE_SRC_BASE_LO */ +#define DMA0_CORE_SRC_BASE_LO_VAL_SHIFT 0 +#define DMA0_CORE_SRC_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_SRC_BASE_HI */ +#define DMA0_CORE_SRC_BASE_HI_VAL_SHIFT 0 +#define DMA0_CORE_SRC_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_BASE_LO */ +#define DMA0_CORE_DST_BASE_LO_VAL_SHIFT 0 +#define DMA0_CORE_DST_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_BASE_HI */ +#define DMA0_CORE_DST_BASE_HI_VAL_SHIFT 0 +#define DMA0_CORE_DST_BASE_HI_VAL_MASK 0xFFFFFF +#define DMA0_CORE_DST_BASE_HI_CTX_ID_HI_SHIFT 24 +#define DMA0_CORE_DST_BASE_HI_CTX_ID_HI_MASK 0xFF000000 + +/* DMA0_CORE_SRC_TSIZE_1 */ +#define DMA0_CORE_SRC_TSIZE_1_VAL_SHIFT 0 +#define DMA0_CORE_SRC_TSIZE_1_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_SRC_STRIDE_1 */ +#define DMA0_CORE_SRC_STRIDE_1_VAL_SHIFT 0 +#define DMA0_CORE_SRC_STRIDE_1_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_SRC_TSIZE_2 */ +#define DMA0_CORE_SRC_TSIZE_2_VAL_SHIFT 0 +#define DMA0_CORE_SRC_TSIZE_2_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_SRC_STRIDE_2 */ +#define DMA0_CORE_SRC_STRIDE_2_VAL_SHIFT 0 +#define DMA0_CORE_SRC_STRIDE_2_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_SRC_TSIZE_3 */ +#define DMA0_CORE_SRC_TSIZE_3_VAL_SHIFT 0 +#define DMA0_CORE_SRC_TSIZE_3_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_SRC_STRIDE_3 */ +#define DMA0_CORE_SRC_STRIDE_3_VAL_SHIFT 0 +#define DMA0_CORE_SRC_STRIDE_3_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_SRC_TSIZE_4 */ +#define DMA0_CORE_SRC_TSIZE_4_VAL_SHIFT 0 +#define DMA0_CORE_SRC_TSIZE_4_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_SRC_STRIDE_4 */ +#define DMA0_CORE_SRC_STRIDE_4_VAL_SHIFT 0 +#define DMA0_CORE_SRC_STRIDE_4_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_SRC_TSIZE_0 */ +#define DMA0_CORE_SRC_TSIZE_0_VAL_SHIFT 0 +#define DMA0_CORE_SRC_TSIZE_0_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_TSIZE_1 */ +#define DMA0_CORE_DST_TSIZE_1_VAL_SHIFT 0 +#define DMA0_CORE_DST_TSIZE_1_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_STRIDE_1 */ +#define DMA0_CORE_DST_STRIDE_1_VAL_SHIFT 0 +#define DMA0_CORE_DST_STRIDE_1_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_TSIZE_2 */ +#define DMA0_CORE_DST_TSIZE_2_VAL_SHIFT 0 +#define DMA0_CORE_DST_TSIZE_2_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_STRIDE_2 */ +#define DMA0_CORE_DST_STRIDE_2_VAL_SHIFT 0 +#define DMA0_CORE_DST_STRIDE_2_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_TSIZE_3 */ +#define DMA0_CORE_DST_TSIZE_3_VAL_SHIFT 0 +#define DMA0_CORE_DST_TSIZE_3_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_STRIDE_3 */ +#define DMA0_CORE_DST_STRIDE_3_VAL_SHIFT 0 +#define DMA0_CORE_DST_STRIDE_3_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_TSIZE_4 */ +#define DMA0_CORE_DST_TSIZE_4_VAL_SHIFT 0 +#define DMA0_CORE_DST_TSIZE_4_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_STRIDE_4 */ +#define DMA0_CORE_DST_STRIDE_4_VAL_SHIFT 0 +#define DMA0_CORE_DST_STRIDE_4_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_TSIZE_0 */ +#define DMA0_CORE_DST_TSIZE_0_VAL_SHIFT 0 +#define DMA0_CORE_DST_TSIZE_0_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_COMMIT */ +#define DMA0_CORE_COMMIT_WR_COMP_EN_SHIFT 0 +#define DMA0_CORE_COMMIT_WR_COMP_EN_MASK 0x1 +#define DMA0_CORE_COMMIT_TRANSPOSE_SHIFT 1 +#define DMA0_CORE_COMMIT_TRANSPOSE_MASK 0x2 +#define DMA0_CORE_COMMIT_DTYPE_SHIFT 2 +#define DMA0_CORE_COMMIT_DTYPE_MASK 0x4 +#define DMA0_CORE_COMMIT_LIN_SHIFT 3 +#define DMA0_CORE_COMMIT_LIN_MASK 0x8 +#define DMA0_CORE_COMMIT_MEM_SET_SHIFT 4 +#define DMA0_CORE_COMMIT_MEM_SET_MASK 0x10 +#define DMA0_CORE_COMMIT_COMPRESS_SHIFT 5 +#define DMA0_CORE_COMMIT_COMPRESS_MASK 0x20 +#define DMA0_CORE_COMMIT_DECOMPRESS_SHIFT 6 +#define DMA0_CORE_COMMIT_DECOMPRESS_MASK 0x40 +#define DMA0_CORE_COMMIT_CTX_ID_SHIFT 16 +#define DMA0_CORE_COMMIT_CTX_ID_MASK 0xFF0000 + +/* DMA0_CORE_WR_COMP_WDATA */ +#define DMA0_CORE_WR_COMP_WDATA_VAL_SHIFT 0 +#define DMA0_CORE_WR_COMP_WDATA_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_WR_COMP_ADDR_LO */ +#define DMA0_CORE_WR_COMP_ADDR_LO_VAL_SHIFT 0 +#define DMA0_CORE_WR_COMP_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_WR_COMP_ADDR_HI */ +#define DMA0_CORE_WR_COMP_ADDR_HI_VAL_SHIFT 0 +#define DMA0_CORE_WR_COMP_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_WR_COMP_AWUSER_31_11 */ +#define DMA0_CORE_WR_COMP_AWUSER_31_11_VAL_SHIFT 0 +#define DMA0_CORE_WR_COMP_AWUSER_31_11_VAL_MASK 0x1FFFFF + +/* DMA0_CORE_TE_NUMROWS */ +#define DMA0_CORE_TE_NUMROWS_VAL_SHIFT 0 +#define DMA0_CORE_TE_NUMROWS_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_PROT */ +#define DMA0_CORE_PROT_VAL_SHIFT 0 +#define DMA0_CORE_PROT_VAL_MASK 0x1 +#define DMA0_CORE_PROT_ERR_VAL_SHIFT 1 +#define DMA0_CORE_PROT_ERR_VAL_MASK 0x2 + +/* DMA0_CORE_SECURE_PROPS */ +#define DMA0_CORE_SECURE_PROPS_ASID_SHIFT 0 +#define DMA0_CORE_SECURE_PROPS_ASID_MASK 0x3FF +#define DMA0_CORE_SECURE_PROPS_MMBP_SHIFT 10 +#define DMA0_CORE_SECURE_PROPS_MMBP_MASK 0x400 + +/* DMA0_CORE_NON_SECURE_PROPS */ +#define DMA0_CORE_NON_SECURE_PROPS_ASID_SHIFT 0 +#define DMA0_CORE_NON_SECURE_PROPS_ASID_MASK 0x3FF +#define DMA0_CORE_NON_SECURE_PROPS_MMBP_SHIFT 10 +#define DMA0_CORE_NON_SECURE_PROPS_MMBP_MASK 0x400 + +/* DMA0_CORE_RD_MAX_OUTSTAND */ +#define DMA0_CORE_RD_MAX_OUTSTAND_VAL_SHIFT 0 +#define DMA0_CORE_RD_MAX_OUTSTAND_VAL_MASK 0xFFF + +/* DMA0_CORE_RD_MAX_SIZE */ +#define DMA0_CORE_RD_MAX_SIZE_DATA_SHIFT 0 +#define DMA0_CORE_RD_MAX_SIZE_DATA_MASK 0x7FF +#define DMA0_CORE_RD_MAX_SIZE_MD_SHIFT 16 +#define DMA0_CORE_RD_MAX_SIZE_MD_MASK 0x7FF0000 + +/* DMA0_CORE_RD_ARCACHE */ +#define DMA0_CORE_RD_ARCACHE_VAL_SHIFT 0 +#define DMA0_CORE_RD_ARCACHE_VAL_MASK 0xF + +/* DMA0_CORE_RD_ARUSER_31_11 */ +#define DMA0_CORE_RD_ARUSER_31_11_VAL_SHIFT 0 +#define DMA0_CORE_RD_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* DMA0_CORE_RD_INFLIGHTS */ +#define DMA0_CORE_RD_INFLIGHTS_VAL_SHIFT 0 +#define DMA0_CORE_RD_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_WR_MAX_OUTSTAND */ +#define DMA0_CORE_WR_MAX_OUTSTAND_VAL_SHIFT 0 +#define DMA0_CORE_WR_MAX_OUTSTAND_VAL_MASK 0xFFF + +/* DMA0_CORE_WR_MAX_AWID */ +#define DMA0_CORE_WR_MAX_AWID_VAL_SHIFT 0 +#define DMA0_CORE_WR_MAX_AWID_VAL_MASK 0xFFFF + +/* DMA0_CORE_WR_AWCACHE */ +#define DMA0_CORE_WR_AWCACHE_VAL_SHIFT 0 +#define DMA0_CORE_WR_AWCACHE_VAL_MASK 0xF + +/* DMA0_CORE_WR_AWUSER_31_11 */ +#define DMA0_CORE_WR_AWUSER_31_11_VAL_SHIFT 0 +#define DMA0_CORE_WR_AWUSER_31_11_VAL_MASK 0x1FFFFF + +/* DMA0_CORE_WR_INFLIGHTS */ +#define DMA0_CORE_WR_INFLIGHTS_VAL_SHIFT 0 +#define DMA0_CORE_WR_INFLIGHTS_VAL_MASK 0xFFFF + +/* DMA0_CORE_RD_RATE_LIM_CFG_0 */ +#define DMA0_CORE_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define DMA0_CORE_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define DMA0_CORE_RD_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define DMA0_CORE_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* DMA0_CORE_RD_RATE_LIM_CFG_1 */ +#define DMA0_CORE_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define DMA0_CORE_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define DMA0_CORE_RD_RATE_LIM_CFG_1_EN_SHIFT 31 +#define DMA0_CORE_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* DMA0_CORE_WR_RATE_LIM_CFG_0 */ +#define DMA0_CORE_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define DMA0_CORE_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define DMA0_CORE_WR_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define DMA0_CORE_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* DMA0_CORE_WR_RATE_LIM_CFG_1 */ +#define DMA0_CORE_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define DMA0_CORE_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define DMA0_CORE_WR_RATE_LIM_CFG_1_EN_SHIFT 31 +#define DMA0_CORE_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* DMA0_CORE_ERR_CFG */ +#define DMA0_CORE_ERR_CFG_ERR_MSG_EN_SHIFT 0 +#define DMA0_CORE_ERR_CFG_ERR_MSG_EN_MASK 0x1 +#define DMA0_CORE_ERR_CFG_STOP_ON_ERR_SHIFT 1 +#define DMA0_CORE_ERR_CFG_STOP_ON_ERR_MASK 0x2 + +/* DMA0_CORE_ERR_CAUSE */ +#define DMA0_CORE_ERR_CAUSE_HBW_RD_ERR_SHIFT 0 +#define DMA0_CORE_ERR_CAUSE_HBW_RD_ERR_MASK 0x1 +#define DMA0_CORE_ERR_CAUSE_HBW_WR_ERR_SHIFT 1 +#define DMA0_CORE_ERR_CAUSE_HBW_WR_ERR_MASK 0x2 +#define DMA0_CORE_ERR_CAUSE_LBW_WR_ERR_SHIFT 2 +#define DMA0_CORE_ERR_CAUSE_LBW_WR_ERR_MASK 0x4 +#define DMA0_CORE_ERR_CAUSE_DESC_OVF_SHIFT 3 +#define DMA0_CORE_ERR_CAUSE_DESC_OVF_MASK 0x8 + +/* DMA0_CORE_ERRMSG_ADDR_LO */ +#define DMA0_CORE_ERRMSG_ADDR_LO_VAL_SHIFT 0 +#define DMA0_CORE_ERRMSG_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_ERRMSG_ADDR_HI */ +#define DMA0_CORE_ERRMSG_ADDR_HI_VAL_SHIFT 0 +#define DMA0_CORE_ERRMSG_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_ERRMSG_WDATA */ +#define DMA0_CORE_ERRMSG_WDATA_VAL_SHIFT 0 +#define DMA0_CORE_ERRMSG_WDATA_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_STS0 */ +#define DMA0_CORE_STS0_RD_REQ_CNT_SHIFT 0 +#define DMA0_CORE_STS0_RD_REQ_CNT_MASK 0x7FFF +#define DMA0_CORE_STS0_WR_REQ_CNT_SHIFT 16 +#define DMA0_CORE_STS0_WR_REQ_CNT_MASK 0x7FFF0000 +#define DMA0_CORE_STS0_BUSY_SHIFT 31 +#define DMA0_CORE_STS0_BUSY_MASK 0x80000000 + +/* DMA0_CORE_STS1 */ +#define DMA0_CORE_STS1_IS_HALT_SHIFT 0 +#define DMA0_CORE_STS1_IS_HALT_MASK 0x1 + +/* DMA0_CORE_RD_DBGMEM_ADD */ +#define DMA0_CORE_RD_DBGMEM_ADD_VAL_SHIFT 0 +#define DMA0_CORE_RD_DBGMEM_ADD_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_RD_DBGMEM_DATA_WR */ +#define DMA0_CORE_RD_DBGMEM_DATA_WR_VAL_SHIFT 0 +#define DMA0_CORE_RD_DBGMEM_DATA_WR_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_RD_DBGMEM_DATA_RD */ +#define DMA0_CORE_RD_DBGMEM_DATA_RD_VAL_SHIFT 0 +#define DMA0_CORE_RD_DBGMEM_DATA_RD_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_RD_DBGMEM_CTRL */ +#define DMA0_CORE_RD_DBGMEM_CTRL_WR_NRD_SHIFT 0 +#define DMA0_CORE_RD_DBGMEM_CTRL_WR_NRD_MASK 0x1 + +/* DMA0_CORE_RD_DBGMEM_RC */ +#define DMA0_CORE_RD_DBGMEM_RC_VALID_SHIFT 0 +#define DMA0_CORE_RD_DBGMEM_RC_VALID_MASK 0x1 + +/* DMA0_CORE_DBG_HBW_AXI_AR_CNT */ + +/* DMA0_CORE_DBG_HBW_AXI_AW_CNT */ + +/* DMA0_CORE_DBG_LBW_AXI_AW_CNT */ + +/* DMA0_CORE_DBG_DESC_CNT */ +#define DMA0_CORE_DBG_DESC_CNT_RD_STS_CTX_CNT_SHIFT 0 +#define DMA0_CORE_DBG_DESC_CNT_RD_STS_CTX_CNT_MASK 0xFFFFFFFF + +/* DMA0_CORE_DBG_STS */ +#define DMA0_CORE_DBG_STS_RD_CTX_FULL_SHIFT 0 +#define DMA0_CORE_DBG_STS_RD_CTX_FULL_MASK 0x1 +#define DMA0_CORE_DBG_STS_WR_CTX_FULL_SHIFT 1 +#define DMA0_CORE_DBG_STS_WR_CTX_FULL_MASK 0x2 +#define DMA0_CORE_DBG_STS_WR_COMP_FULL_SHIFT 2 +#define DMA0_CORE_DBG_STS_WR_COMP_FULL_MASK 0x4 +#define DMA0_CORE_DBG_STS_RD_CTX_EMPTY_SHIFT 3 +#define DMA0_CORE_DBG_STS_RD_CTX_EMPTY_MASK 0x8 +#define DMA0_CORE_DBG_STS_WR_CTX_EMPTY_SHIFT 4 +#define DMA0_CORE_DBG_STS_WR_CTX_EMPTY_MASK 0x10 +#define DMA0_CORE_DBG_STS_WR_COMP_EMPTY_SHIFT 5 +#define DMA0_CORE_DBG_STS_WR_COMP_EMPTY_MASK 0x20 +#define DMA0_CORE_DBG_STS_TE_EMPTY_SHIFT 6 +#define DMA0_CORE_DBG_STS_TE_EMPTY_MASK 0x40 +#define DMA0_CORE_DBG_STS_TE_BUSY_SHIFT 7 +#define DMA0_CORE_DBG_STS_TE_BUSY_MASK 0x80 +#define DMA0_CORE_DBG_STS_GSKT_EMPTY_SHIFT 8 +#define DMA0_CORE_DBG_STS_GSKT_EMPTY_MASK 0x100 +#define DMA0_CORE_DBG_STS_GSKT_FULL_SHIFT 9 +#define DMA0_CORE_DBG_STS_GSKT_FULL_MASK 0x200 +#define DMA0_CORE_DBG_STS_RDBUF_FULLNESS_SHIFT 20 +#define DMA0_CORE_DBG_STS_RDBUF_FULLNESS_MASK 0x7FF00000 + +/* DMA0_CORE_DBG_RD_DESC_ID */ + +/* DMA0_CORE_DBG_WR_DESC_ID */ + +#endif /* ASIC_REG_DMA0_CORE_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_core_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_core_regs.h new file mode 100644 index 000000000000..1fdd5d5fc6d2 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_core_regs.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA0_CORE_REGS_H_ +#define ASIC_REG_DMA0_CORE_REGS_H_ + +/* + ***************************************** + * DMA0_CORE (Prototype: DMA_CORE) + ***************************************** + */ + +#define mmDMA0_CORE_CFG_0 0x500000 + +#define mmDMA0_CORE_CFG_1 0x500004 + +#define mmDMA0_CORE_LBW_MAX_OUTSTAND 0x500008 + +#define mmDMA0_CORE_SRC_BASE_LO 0x500014 + +#define mmDMA0_CORE_SRC_BASE_HI 0x500018 + +#define mmDMA0_CORE_DST_BASE_LO 0x50001C + +#define mmDMA0_CORE_DST_BASE_HI 0x500020 + +#define mmDMA0_CORE_SRC_TSIZE_1 0x50002C + +#define mmDMA0_CORE_SRC_STRIDE_1 0x500030 + +#define mmDMA0_CORE_SRC_TSIZE_2 0x500034 + +#define mmDMA0_CORE_SRC_STRIDE_2 0x500038 + +#define mmDMA0_CORE_SRC_TSIZE_3 0x50003C + +#define mmDMA0_CORE_SRC_STRIDE_3 0x500040 + +#define mmDMA0_CORE_SRC_TSIZE_4 0x500044 + +#define mmDMA0_CORE_SRC_STRIDE_4 0x500048 + +#define mmDMA0_CORE_SRC_TSIZE_0 0x50004C + +#define mmDMA0_CORE_DST_TSIZE_1 0x500054 + +#define mmDMA0_CORE_DST_STRIDE_1 0x500058 + +#define mmDMA0_CORE_DST_TSIZE_2 0x50005C + +#define mmDMA0_CORE_DST_STRIDE_2 0x500060 + +#define mmDMA0_CORE_DST_TSIZE_3 0x500064 + +#define mmDMA0_CORE_DST_STRIDE_3 0x500068 + +#define mmDMA0_CORE_DST_TSIZE_4 0x50006C + +#define mmDMA0_CORE_DST_STRIDE_4 0x500070 + +#define mmDMA0_CORE_DST_TSIZE_0 0x500074 + +#define mmDMA0_CORE_COMMIT 0x500078 + +#define mmDMA0_CORE_WR_COMP_WDATA 0x50007C + +#define mmDMA0_CORE_WR_COMP_ADDR_LO 0x500080 + +#define mmDMA0_CORE_WR_COMP_ADDR_HI 0x500084 + +#define mmDMA0_CORE_WR_COMP_AWUSER_31_11 0x500088 + +#define mmDMA0_CORE_TE_NUMROWS 0x500094 + +#define mmDMA0_CORE_PROT 0x5000B8 + +#define mmDMA0_CORE_SECURE_PROPS 0x5000F0 + +#define mmDMA0_CORE_NON_SECURE_PROPS 0x5000F4 + +#define mmDMA0_CORE_RD_MAX_OUTSTAND 0x500100 + +#define mmDMA0_CORE_RD_MAX_SIZE 0x500104 + +#define mmDMA0_CORE_RD_ARCACHE 0x500108 + +#define mmDMA0_CORE_RD_ARUSER_31_11 0x500110 + +#define mmDMA0_CORE_RD_INFLIGHTS 0x500114 + +#define mmDMA0_CORE_WR_MAX_OUTSTAND 0x500120 + +#define mmDMA0_CORE_WR_MAX_AWID 0x500124 + +#define mmDMA0_CORE_WR_AWCACHE 0x500128 + +#define mmDMA0_CORE_WR_AWUSER_31_11 0x500130 + +#define mmDMA0_CORE_WR_INFLIGHTS 0x500134 + +#define mmDMA0_CORE_RD_RATE_LIM_CFG_0 0x500150 + +#define mmDMA0_CORE_RD_RATE_LIM_CFG_1 0x500154 + +#define mmDMA0_CORE_WR_RATE_LIM_CFG_0 0x500158 + +#define mmDMA0_CORE_WR_RATE_LIM_CFG_1 0x50015C + +#define mmDMA0_CORE_ERR_CFG 0x500160 + +#define mmDMA0_CORE_ERR_CAUSE 0x500164 + +#define mmDMA0_CORE_ERRMSG_ADDR_LO 0x500170 + +#define mmDMA0_CORE_ERRMSG_ADDR_HI 0x500174 + +#define mmDMA0_CORE_ERRMSG_WDATA 0x500178 + +#define mmDMA0_CORE_STS0 0x500190 + +#define mmDMA0_CORE_STS1 0x500194 + +#define mmDMA0_CORE_RD_DBGMEM_ADD 0x500200 + +#define mmDMA0_CORE_RD_DBGMEM_DATA_WR 0x500204 + +#define mmDMA0_CORE_RD_DBGMEM_DATA_RD 0x500208 + +#define mmDMA0_CORE_RD_DBGMEM_CTRL 0x50020C + +#define mmDMA0_CORE_RD_DBGMEM_RC 0x500210 + +#define mmDMA0_CORE_DBG_HBW_AXI_AR_CNT 0x500220 + +#define mmDMA0_CORE_DBG_HBW_AXI_AW_CNT 0x500224 + +#define mmDMA0_CORE_DBG_LBW_AXI_AW_CNT 0x500228 + +#define mmDMA0_CORE_DBG_DESC_CNT 0x50022C + +#define mmDMA0_CORE_DBG_STS 0x500230 + +#define mmDMA0_CORE_DBG_RD_DESC_ID 0x500234 + +#define mmDMA0_CORE_DBG_WR_DESC_ID 0x500238 + +#endif /* ASIC_REG_DMA0_CORE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_qm_masks.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_qm_masks.h new file mode 100644 index 000000000000..48376aabc3ba --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_qm_masks.h @@ -0,0 +1,800 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA0_QM_MASKS_H_ +#define ASIC_REG_DMA0_QM_MASKS_H_ + +/* + ***************************************** + * DMA0_QM (Prototype: QMAN) + ***************************************** + */ + +/* DMA0_QM_GLBL_CFG0 */ +#define DMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0 +#define DMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF +#define DMA0_QM_GLBL_CFG0_CQF_EN_SHIFT 4 +#define DMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0 +#define DMA0_QM_GLBL_CFG0_CP_EN_SHIFT 9 +#define DMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00 + +/* DMA0_QM_GLBL_CFG1 */ +#define DMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0 +#define DMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF +#define DMA0_QM_GLBL_CFG1_CQF_STOP_SHIFT 4 +#define DMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0 +#define DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT 9 +#define DMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00 +#define DMA0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 16 +#define DMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000 +#define DMA0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 20 +#define DMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000 +#define DMA0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 25 +#define DMA0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x3E000000 + +/* DMA0_QM_GLBL_PROT */ +#define DMA0_QM_GLBL_PROT_PQF_SHIFT 0 +#define DMA0_QM_GLBL_PROT_PQF_MASK 0xF +#define DMA0_QM_GLBL_PROT_CQF_SHIFT 4 +#define DMA0_QM_GLBL_PROT_CQF_MASK 0x1F0 +#define DMA0_QM_GLBL_PROT_CP_SHIFT 9 +#define DMA0_QM_GLBL_PROT_CP_MASK 0x3E00 +#define DMA0_QM_GLBL_PROT_ERR_SHIFT 14 +#define DMA0_QM_GLBL_PROT_ERR_MASK 0x4000 +#define DMA0_QM_GLBL_PROT_ARB_SHIFT 15 +#define DMA0_QM_GLBL_PROT_ARB_MASK 0x8000 + +/* DMA0_QM_GLBL_ERR_CFG */ +#define DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 0 +#define DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0xF +#define DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 +#define DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1F0 +#define DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 9 +#define DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x3E00 +#define DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 16 +#define DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0xF0000 +#define DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 20 +#define DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x1F00000 +#define DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 25 +#define DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x3E000000 +#define DMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT 31 +#define DMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK 0x80000000 + +/* DMA0_QM_GLBL_SECURE_PROPS */ +#define DMA0_QM_GLBL_SECURE_PROPS_0_ASID_SHIFT 0 +#define DMA0_QM_GLBL_SECURE_PROPS_0_ASID_MASK 0x3FF +#define DMA0_QM_GLBL_SECURE_PROPS_1_ASID_SHIFT 0 +#define DMA0_QM_GLBL_SECURE_PROPS_1_ASID_MASK 0x3FF +#define DMA0_QM_GLBL_SECURE_PROPS_2_ASID_SHIFT 0 +#define DMA0_QM_GLBL_SECURE_PROPS_2_ASID_MASK 0x3FF +#define DMA0_QM_GLBL_SECURE_PROPS_3_ASID_SHIFT 0 +#define DMA0_QM_GLBL_SECURE_PROPS_3_ASID_MASK 0x3FF +#define DMA0_QM_GLBL_SECURE_PROPS_4_ASID_SHIFT 0 +#define DMA0_QM_GLBL_SECURE_PROPS_4_ASID_MASK 0x3FF +#define DMA0_QM_GLBL_SECURE_PROPS_0_MMBP_SHIFT 10 +#define DMA0_QM_GLBL_SECURE_PROPS_0_MMBP_MASK 0x400 +#define DMA0_QM_GLBL_SECURE_PROPS_1_MMBP_SHIFT 10 +#define DMA0_QM_GLBL_SECURE_PROPS_1_MMBP_MASK 0x400 +#define DMA0_QM_GLBL_SECURE_PROPS_2_MMBP_SHIFT 10 +#define DMA0_QM_GLBL_SECURE_PROPS_2_MMBP_MASK 0x400 +#define DMA0_QM_GLBL_SECURE_PROPS_3_MMBP_SHIFT 10 +#define DMA0_QM_GLBL_SECURE_PROPS_3_MMBP_MASK 0x400 +#define DMA0_QM_GLBL_SECURE_PROPS_4_MMBP_SHIFT 10 +#define DMA0_QM_GLBL_SECURE_PROPS_4_MMBP_MASK 0x400 + +/* DMA0_QM_GLBL_NON_SECURE_PROPS */ +#define DMA0_QM_GLBL_NON_SECURE_PROPS_0_ASID_SHIFT 0 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_0_ASID_MASK 0x3FF +#define DMA0_QM_GLBL_NON_SECURE_PROPS_1_ASID_SHIFT 0 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_1_ASID_MASK 0x3FF +#define DMA0_QM_GLBL_NON_SECURE_PROPS_2_ASID_SHIFT 0 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_2_ASID_MASK 0x3FF +#define DMA0_QM_GLBL_NON_SECURE_PROPS_3_ASID_SHIFT 0 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_3_ASID_MASK 0x3FF +#define DMA0_QM_GLBL_NON_SECURE_PROPS_4_ASID_SHIFT 0 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_4_ASID_MASK 0x3FF +#define DMA0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_SHIFT 10 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_MASK 0x400 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_SHIFT 10 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_MASK 0x400 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_SHIFT 10 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_MASK 0x400 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_SHIFT 10 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_MASK 0x400 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_SHIFT 10 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_MASK 0x400 + +/* DMA0_QM_GLBL_STS0 */ +#define DMA0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0 +#define DMA0_QM_GLBL_STS0_PQF_IDLE_MASK 0xF +#define DMA0_QM_GLBL_STS0_CQF_IDLE_SHIFT 4 +#define DMA0_QM_GLBL_STS0_CQF_IDLE_MASK 0x1F0 +#define DMA0_QM_GLBL_STS0_CP_IDLE_SHIFT 9 +#define DMA0_QM_GLBL_STS0_CP_IDLE_MASK 0x3E00 +#define DMA0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 16 +#define DMA0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0xF0000 +#define DMA0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 20 +#define DMA0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x1F00000 +#define DMA0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 25 +#define DMA0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x3E000000 +#define DMA0_QM_GLBL_STS0_ARB_IS_STOP_SHIFT 31 +#define DMA0_QM_GLBL_STS0_ARB_IS_STOP_MASK 0x80000000 + +/* DMA0_QM_GLBL_STS1 */ +#define DMA0_QM_GLBL_STS1_PQF_RD_ERR_SHIFT 0 +#define DMA0_QM_GLBL_STS1_PQF_RD_ERR_MASK 0x1 +#define DMA0_QM_GLBL_STS1_CQF_RD_ERR_SHIFT 1 +#define DMA0_QM_GLBL_STS1_CQF_RD_ERR_MASK 0x2 +#define DMA0_QM_GLBL_STS1_CP_RD_ERR_SHIFT 2 +#define DMA0_QM_GLBL_STS1_CP_RD_ERR_MASK 0x4 +#define DMA0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3 +#define DMA0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8 +#define DMA0_QM_GLBL_STS1_CP_STOP_OP_SHIFT 4 +#define DMA0_QM_GLBL_STS1_CP_STOP_OP_MASK 0x10 +#define DMA0_QM_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5 +#define DMA0_QM_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20 +#define DMA0_QM_GLBL_STS1_CP_WREG_ERR_SHIFT 6 +#define DMA0_QM_GLBL_STS1_CP_WREG_ERR_MASK 0x40 +#define DMA0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_SHIFT 8 +#define DMA0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_MASK 0x100 +#define DMA0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_SHIFT 9 +#define DMA0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_MASK 0x200 +#define DMA0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_SHIFT 10 +#define DMA0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_MASK 0x400 +#define DMA0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_SHIFT 11 +#define DMA0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_MASK 0x800 +#define DMA0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_SHIFT 12 +#define DMA0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define DMA0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_SHIFT 13 +#define DMA0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define DMA0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_SHIFT 14 +#define DMA0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define DMA0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_SHIFT 15 +#define DMA0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* DMA0_QM_GLBL_STS1_4 */ +#define DMA0_QM_GLBL_STS1_4_CQF_RD_ERR_SHIFT 1 +#define DMA0_QM_GLBL_STS1_4_CQF_RD_ERR_MASK 0x2 +#define DMA0_QM_GLBL_STS1_4_CP_RD_ERR_SHIFT 2 +#define DMA0_QM_GLBL_STS1_4_CP_RD_ERR_MASK 0x4 +#define DMA0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_SHIFT 3 +#define DMA0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_MASK 0x8 +#define DMA0_QM_GLBL_STS1_4_CP_STOP_OP_SHIFT 4 +#define DMA0_QM_GLBL_STS1_4_CP_STOP_OP_MASK 0x10 +#define DMA0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_SHIFT 5 +#define DMA0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_MASK 0x20 +#define DMA0_QM_GLBL_STS1_4_CP_WREG_ERR_SHIFT 6 +#define DMA0_QM_GLBL_STS1_4_CP_WREG_ERR_MASK 0x40 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_SHIFT 8 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_MASK 0x100 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_SHIFT 9 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_MASK 0x200 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_SHIFT 10 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_MASK 0x400 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_SHIFT 11 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_MASK 0x800 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_SHIFT 12 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_SHIFT 13 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_SHIFT 14 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_SHIFT 15 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* DMA0_QM_GLBL_MSG_EN */ +#define DMA0_QM_GLBL_MSG_EN_PQF_RD_ERR_SHIFT 0 +#define DMA0_QM_GLBL_MSG_EN_PQF_RD_ERR_MASK 0x1 +#define DMA0_QM_GLBL_MSG_EN_CQF_RD_ERR_SHIFT 1 +#define DMA0_QM_GLBL_MSG_EN_CQF_RD_ERR_MASK 0x2 +#define DMA0_QM_GLBL_MSG_EN_CP_RD_ERR_SHIFT 2 +#define DMA0_QM_GLBL_MSG_EN_CP_RD_ERR_MASK 0x4 +#define DMA0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT 3 +#define DMA0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_MASK 0x8 +#define DMA0_QM_GLBL_MSG_EN_CP_STOP_OP_SHIFT 4 +#define DMA0_QM_GLBL_MSG_EN_CP_STOP_OP_MASK 0x10 +#define DMA0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_SHIFT 5 +#define DMA0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_MASK 0x20 +#define DMA0_QM_GLBL_MSG_EN_CP_WREG_ERR_SHIFT 6 +#define DMA0_QM_GLBL_MSG_EN_CP_WREG_ERR_MASK 0x40 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT 8 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT 9 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT 10 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_MASK 0x400 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT 11 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT 12 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT 13 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT 14 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT 15 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* DMA0_QM_GLBL_MSG_EN_4 */ +#define DMA0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_SHIFT 1 +#define DMA0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_MASK 0x2 +#define DMA0_QM_GLBL_MSG_EN_4_CP_RD_ERR_SHIFT 2 +#define DMA0_QM_GLBL_MSG_EN_4_CP_RD_ERR_MASK 0x4 +#define DMA0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT 3 +#define DMA0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK 0x8 +#define DMA0_QM_GLBL_MSG_EN_4_CP_STOP_OP_SHIFT 4 +#define DMA0_QM_GLBL_MSG_EN_4_CP_STOP_OP_MASK 0x10 +#define DMA0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_SHIFT 5 +#define DMA0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_MASK 0x20 +#define DMA0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_SHIFT 6 +#define DMA0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_MASK 0x40 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT 8 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT 9 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT 10 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK 0x400 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT 11 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT 12 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT 13 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT 14 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT 15 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* DMA0_QM_PQ_BASE_LO */ +#define DMA0_QM_PQ_BASE_LO_VAL_SHIFT 0 +#define DMA0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_PQ_BASE_HI */ +#define DMA0_QM_PQ_BASE_HI_VAL_SHIFT 0 +#define DMA0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_PQ_SIZE */ +#define DMA0_QM_PQ_SIZE_VAL_SHIFT 0 +#define DMA0_QM_PQ_SIZE_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_PQ_PI */ +#define DMA0_QM_PQ_PI_VAL_SHIFT 0 +#define DMA0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_PQ_CI */ +#define DMA0_QM_PQ_CI_VAL_SHIFT 0 +#define DMA0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_PQ_CFG0 */ +#define DMA0_QM_PQ_CFG0_RESERVED_SHIFT 0 +#define DMA0_QM_PQ_CFG0_RESERVED_MASK 0x1 + +/* DMA0_QM_PQ_CFG1 */ +#define DMA0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0 +#define DMA0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define DMA0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define DMA0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* DMA0_QM_PQ_ARUSER_31_11 */ +#define DMA0_QM_PQ_ARUSER_31_11_VAL_SHIFT 0 +#define DMA0_QM_PQ_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* DMA0_QM_PQ_STS0 */ +#define DMA0_QM_PQ_STS0_PQ_CREDIT_CNT_SHIFT 0 +#define DMA0_QM_PQ_STS0_PQ_CREDIT_CNT_MASK 0xFFFF +#define DMA0_QM_PQ_STS0_PQ_FREE_CNT_SHIFT 16 +#define DMA0_QM_PQ_STS0_PQ_FREE_CNT_MASK 0xFFFF0000 + +/* DMA0_QM_PQ_STS1 */ +#define DMA0_QM_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT 0 +#define DMA0_QM_PQ_STS1_PQ_INFLIGHT_CNT_MASK 0xFFFF +#define DMA0_QM_PQ_STS1_PQ_BUF_EMPTY_SHIFT 30 +#define DMA0_QM_PQ_STS1_PQ_BUF_EMPTY_MASK 0x40000000 +#define DMA0_QM_PQ_STS1_PQ_BUSY_SHIFT 31 +#define DMA0_QM_PQ_STS1_PQ_BUSY_MASK 0x80000000 + +/* DMA0_QM_CQ_CFG0 */ +#define DMA0_QM_CQ_CFG0_RESERVED_SHIFT 0 +#define DMA0_QM_CQ_CFG0_RESERVED_MASK 0x1 + +/* DMA0_QM_CQ_CFG1 */ +#define DMA0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0 +#define DMA0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define DMA0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define DMA0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* DMA0_QM_CQ_ARUSER_31_11 */ +#define DMA0_QM_CQ_ARUSER_31_11_VAL_SHIFT 0 +#define DMA0_QM_CQ_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* DMA0_QM_CQ_STS0 */ +#define DMA0_QM_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0 +#define DMA0_QM_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF +#define DMA0_QM_CQ_STS0_CQ_FREE_CNT_SHIFT 16 +#define DMA0_QM_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000 + +/* DMA0_QM_CQ_STS1 */ +#define DMA0_QM_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0 +#define DMA0_QM_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF +#define DMA0_QM_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30 +#define DMA0_QM_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000 +#define DMA0_QM_CQ_STS1_CQ_BUSY_SHIFT 31 +#define DMA0_QM_CQ_STS1_CQ_BUSY_MASK 0x80000000 + +/* DMA0_QM_CQ_PTR_LO_0 */ +#define DMA0_QM_CQ_PTR_LO_0_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_LO_0_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_PTR_HI_0 */ +#define DMA0_QM_CQ_PTR_HI_0_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_HI_0_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_TSIZE_0 */ +#define DMA0_QM_CQ_TSIZE_0_VAL_SHIFT 0 +#define DMA0_QM_CQ_TSIZE_0_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_CTL_0 */ +#define DMA0_QM_CQ_CTL_0_RPT_SHIFT 0 +#define DMA0_QM_CQ_CTL_0_RPT_MASK 0xFFFF +#define DMA0_QM_CQ_CTL_0_CTL_SHIFT 16 +#define DMA0_QM_CQ_CTL_0_CTL_MASK 0xFFFF0000 + +/* DMA0_QM_CQ_PTR_LO_1 */ +#define DMA0_QM_CQ_PTR_LO_1_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_LO_1_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_PTR_HI_1 */ +#define DMA0_QM_CQ_PTR_HI_1_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_HI_1_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_TSIZE_1 */ +#define DMA0_QM_CQ_TSIZE_1_VAL_SHIFT 0 +#define DMA0_QM_CQ_TSIZE_1_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_CTL_1 */ +#define DMA0_QM_CQ_CTL_1_RPT_SHIFT 0 +#define DMA0_QM_CQ_CTL_1_RPT_MASK 0xFFFF +#define DMA0_QM_CQ_CTL_1_CTL_SHIFT 16 +#define DMA0_QM_CQ_CTL_1_CTL_MASK 0xFFFF0000 + +/* DMA0_QM_CQ_PTR_LO_2 */ +#define DMA0_QM_CQ_PTR_LO_2_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_LO_2_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_PTR_HI_2 */ +#define DMA0_QM_CQ_PTR_HI_2_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_HI_2_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_TSIZE_2 */ +#define DMA0_QM_CQ_TSIZE_2_VAL_SHIFT 0 +#define DMA0_QM_CQ_TSIZE_2_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_CTL_2 */ +#define DMA0_QM_CQ_CTL_2_RPT_SHIFT 0 +#define DMA0_QM_CQ_CTL_2_RPT_MASK 0xFFFF +#define DMA0_QM_CQ_CTL_2_CTL_SHIFT 16 +#define DMA0_QM_CQ_CTL_2_CTL_MASK 0xFFFF0000 + +/* DMA0_QM_CQ_PTR_LO_3 */ +#define DMA0_QM_CQ_PTR_LO_3_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_LO_3_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_PTR_HI_3 */ +#define DMA0_QM_CQ_PTR_HI_3_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_HI_3_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_TSIZE_3 */ +#define DMA0_QM_CQ_TSIZE_3_VAL_SHIFT 0 +#define DMA0_QM_CQ_TSIZE_3_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_CTL_3 */ +#define DMA0_QM_CQ_CTL_3_RPT_SHIFT 0 +#define DMA0_QM_CQ_CTL_3_RPT_MASK 0xFFFF +#define DMA0_QM_CQ_CTL_3_CTL_SHIFT 16 +#define DMA0_QM_CQ_CTL_3_CTL_MASK 0xFFFF0000 + +/* DMA0_QM_CQ_PTR_LO_4 */ +#define DMA0_QM_CQ_PTR_LO_4_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_LO_4_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_PTR_HI_4 */ +#define DMA0_QM_CQ_PTR_HI_4_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_HI_4_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_TSIZE_4 */ +#define DMA0_QM_CQ_TSIZE_4_VAL_SHIFT 0 +#define DMA0_QM_CQ_TSIZE_4_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_CTL_4 */ +#define DMA0_QM_CQ_CTL_4_RPT_SHIFT 0 +#define DMA0_QM_CQ_CTL_4_RPT_MASK 0xFFFF +#define DMA0_QM_CQ_CTL_4_CTL_SHIFT 16 +#define DMA0_QM_CQ_CTL_4_CTL_MASK 0xFFFF0000 + +/* DMA0_QM_CQ_PTR_LO_STS */ +#define DMA0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_PTR_HI_STS */ +#define DMA0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_TSIZE_STS */ +#define DMA0_QM_CQ_TSIZE_STS_VAL_SHIFT 0 +#define DMA0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_CTL_STS */ +#define DMA0_QM_CQ_CTL_STS_RPT_SHIFT 0 +#define DMA0_QM_CQ_CTL_STS_RPT_MASK 0xFFFF +#define DMA0_QM_CQ_CTL_STS_CTL_SHIFT 16 +#define DMA0_QM_CQ_CTL_STS_CTL_MASK 0xFFFF0000 + +/* DMA0_QM_CQ_IFIFO_CNT */ +#define DMA0_QM_CQ_IFIFO_CNT_VAL_SHIFT 0 +#define DMA0_QM_CQ_IFIFO_CNT_VAL_MASK 0x3 + +/* DMA0_QM_CP_MSG_BASE0_ADDR_LO */ +#define DMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 +#define DMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_MSG_BASE0_ADDR_HI */ +#define DMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 +#define DMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_MSG_BASE1_ADDR_LO */ +#define DMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 +#define DMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_MSG_BASE1_ADDR_HI */ +#define DMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 +#define DMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_MSG_BASE2_ADDR_LO */ +#define DMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 +#define DMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_MSG_BASE2_ADDR_HI */ +#define DMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 +#define DMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_MSG_BASE3_ADDR_LO */ +#define DMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 +#define DMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_MSG_BASE3_ADDR_HI */ +#define DMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 +#define DMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_LDMA_TSIZE_OFFSET */ +#define DMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 +#define DMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */ +#define DMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 +#define DMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET */ +#define DMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 +#define DMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_FENCE0_RDATA */ +#define DMA0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 +#define DMA0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF + +/* DMA0_QM_CP_FENCE1_RDATA */ +#define DMA0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 +#define DMA0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF + +/* DMA0_QM_CP_FENCE2_RDATA */ +#define DMA0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 +#define DMA0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF + +/* DMA0_QM_CP_FENCE3_RDATA */ +#define DMA0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 +#define DMA0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF + +/* DMA0_QM_CP_FENCE0_CNT */ +#define DMA0_QM_CP_FENCE0_CNT_VAL_SHIFT 0 +#define DMA0_QM_CP_FENCE0_CNT_VAL_MASK 0x3FFF + +/* DMA0_QM_CP_FENCE1_CNT */ +#define DMA0_QM_CP_FENCE1_CNT_VAL_SHIFT 0 +#define DMA0_QM_CP_FENCE1_CNT_VAL_MASK 0x3FFF + +/* DMA0_QM_CP_FENCE2_CNT */ +#define DMA0_QM_CP_FENCE2_CNT_VAL_SHIFT 0 +#define DMA0_QM_CP_FENCE2_CNT_VAL_MASK 0x3FFF + +/* DMA0_QM_CP_FENCE3_CNT */ +#define DMA0_QM_CP_FENCE3_CNT_VAL_SHIFT 0 +#define DMA0_QM_CP_FENCE3_CNT_VAL_MASK 0x3FFF + +/* DMA0_QM_CP_STS */ +#define DMA0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 +#define DMA0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF +#define DMA0_QM_CP_STS_ERDY_SHIFT 16 +#define DMA0_QM_CP_STS_ERDY_MASK 0x10000 +#define DMA0_QM_CP_STS_RRDY_SHIFT 17 +#define DMA0_QM_CP_STS_RRDY_MASK 0x20000 +#define DMA0_QM_CP_STS_MRDY_SHIFT 18 +#define DMA0_QM_CP_STS_MRDY_MASK 0x40000 +#define DMA0_QM_CP_STS_SW_STOP_SHIFT 19 +#define DMA0_QM_CP_STS_SW_STOP_MASK 0x80000 +#define DMA0_QM_CP_STS_FENCE_ID_SHIFT 20 +#define DMA0_QM_CP_STS_FENCE_ID_MASK 0x300000 +#define DMA0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 22 +#define DMA0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000 + +/* DMA0_QM_CP_CURRENT_INST_LO */ +#define DMA0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0 +#define DMA0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_CURRENT_INST_HI */ +#define DMA0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0 +#define DMA0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_BARRIER_CFG */ +#define DMA0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0 +#define DMA0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF +#define DMA0_QM_CP_BARRIER_CFG_RBGUARD_SHIFT 16 +#define DMA0_QM_CP_BARRIER_CFG_RBGUARD_MASK 0xF0000 + +/* DMA0_QM_CP_DBG_0 */ +#define DMA0_QM_CP_DBG_0_CS_SHIFT 0 +#define DMA0_QM_CP_DBG_0_CS_MASK 0xF +#define DMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT 4 +#define DMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_MASK 0x10 +#define DMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT 5 +#define DMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK 0x20 +#define DMA0_QM_CP_DBG_0_MREB_STALL_SHIFT 6 +#define DMA0_QM_CP_DBG_0_MREB_STALL_MASK 0x40 +#define DMA0_QM_CP_DBG_0_STALL_SHIFT 7 +#define DMA0_QM_CP_DBG_0_STALL_MASK 0x80 + +/* DMA0_QM_CP_ARUSER_31_11 */ +#define DMA0_QM_CP_ARUSER_31_11_VAL_SHIFT 0 +#define DMA0_QM_CP_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* DMA0_QM_CP_AWUSER_31_11 */ +#define DMA0_QM_CP_AWUSER_31_11_VAL_SHIFT 0 +#define DMA0_QM_CP_AWUSER_31_11_VAL_MASK 0x1FFFFF + +/* DMA0_QM_ARB_CFG_0 */ +#define DMA0_QM_ARB_CFG_0_TYPE_SHIFT 0 +#define DMA0_QM_ARB_CFG_0_TYPE_MASK 0x1 +#define DMA0_QM_ARB_CFG_0_IS_MASTER_SHIFT 4 +#define DMA0_QM_ARB_CFG_0_IS_MASTER_MASK 0x10 +#define DMA0_QM_ARB_CFG_0_EN_SHIFT 8 +#define DMA0_QM_ARB_CFG_0_EN_MASK 0x100 +#define DMA0_QM_ARB_CFG_0_MASK_SHIFT 12 +#define DMA0_QM_ARB_CFG_0_MASK_MASK 0xF000 +#define DMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT 16 +#define DMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_MASK 0x10000 + +/* DMA0_QM_ARB_CHOISE_Q_PUSH */ +#define DMA0_QM_ARB_CHOISE_Q_PUSH_VAL_SHIFT 0 +#define DMA0_QM_ARB_CHOISE_Q_PUSH_VAL_MASK 0x3 + +/* DMA0_QM_ARB_WRR_WEIGHT */ +#define DMA0_QM_ARB_WRR_WEIGHT_VAL_SHIFT 0 +#define DMA0_QM_ARB_WRR_WEIGHT_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_ARB_CFG_1 */ +#define DMA0_QM_ARB_CFG_1_CLR_SHIFT 0 +#define DMA0_QM_ARB_CFG_1_CLR_MASK 0x1 + +/* DMA0_QM_ARB_MST_AVAIL_CRED */ +#define DMA0_QM_ARB_MST_AVAIL_CRED_VAL_SHIFT 0 +#define DMA0_QM_ARB_MST_AVAIL_CRED_VAL_MASK 0x7F + +/* DMA0_QM_ARB_MST_CRED_INC */ +#define DMA0_QM_ARB_MST_CRED_INC_VAL_SHIFT 0 +#define DMA0_QM_ARB_MST_CRED_INC_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_ARB_MST_CHOISE_PUSH_OFST */ +#define DMA0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_SHIFT 0 +#define DMA0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST */ +#define DMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT 0 +#define DMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_ARB_MST_SLAVE_EN */ +#define DMA0_QM_ARB_MST_SLAVE_EN_VAL_SHIFT 0 +#define DMA0_QM_ARB_MST_SLAVE_EN_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_ARB_MST_QUIET_PER */ +#define DMA0_QM_ARB_MST_QUIET_PER_VAL_SHIFT 0 +#define DMA0_QM_ARB_MST_QUIET_PER_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_ARB_SLV_CHOISE_WDT */ +#define DMA0_QM_ARB_SLV_CHOISE_WDT_VAL_SHIFT 0 +#define DMA0_QM_ARB_SLV_CHOISE_WDT_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_ARB_SLV_ID */ +#define DMA0_QM_ARB_SLV_ID_VAL_SHIFT 0 +#define DMA0_QM_ARB_SLV_ID_VAL_MASK 0x1F + +/* DMA0_QM_ARB_MSG_MAX_INFLIGHT */ +#define DMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT 0 +#define DMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_MASK 0x3F + +/* DMA0_QM_ARB_MSG_AWUSER_31_11 */ +#define DMA0_QM_ARB_MSG_AWUSER_31_11_VAL_SHIFT 0 +#define DMA0_QM_ARB_MSG_AWUSER_31_11_VAL_MASK 0x1FFFFF + +/* DMA0_QM_ARB_MSG_AWUSER_SEC_PROP */ +#define DMA0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_SHIFT 0 +#define DMA0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_MASK 0x3FF +#define DMA0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_SHIFT 10 +#define DMA0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_MASK 0x400 + +/* DMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP */ +#define DMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_SHIFT 0 +#define DMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_MASK 0x3FF +#define DMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_SHIFT 10 +#define DMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_MASK 0x400 + +/* DMA0_QM_ARB_BASE_LO */ +#define DMA0_QM_ARB_BASE_LO_VAL_SHIFT 0 +#define DMA0_QM_ARB_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_ARB_BASE_HI */ +#define DMA0_QM_ARB_BASE_HI_VAL_SHIFT 0 +#define DMA0_QM_ARB_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_ARB_STATE_STS */ +#define DMA0_QM_ARB_STATE_STS_VAL_SHIFT 0 +#define DMA0_QM_ARB_STATE_STS_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_ARB_CHOISE_FULLNESS_STS */ +#define DMA0_QM_ARB_CHOISE_FULLNESS_STS_VAL_SHIFT 0 +#define DMA0_QM_ARB_CHOISE_FULLNESS_STS_VAL_MASK 0x7F + +/* DMA0_QM_ARB_MSG_STS */ +#define DMA0_QM_ARB_MSG_STS_FULL_SHIFT 0 +#define DMA0_QM_ARB_MSG_STS_FULL_MASK 0x1 +#define DMA0_QM_ARB_MSG_STS_NO_INFLIGHT_SHIFT 1 +#define DMA0_QM_ARB_MSG_STS_NO_INFLIGHT_MASK 0x2 + +/* DMA0_QM_ARB_SLV_CHOISE_Q_HEAD */ +#define DMA0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_SHIFT 0 +#define DMA0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_MASK 0x3 + +/* DMA0_QM_ARB_ERR_CAUSE */ +#define DMA0_QM_ARB_ERR_CAUSE_CHOISE_OVF_SHIFT 0 +#define DMA0_QM_ARB_ERR_CAUSE_CHOISE_OVF_MASK 0x1 +#define DMA0_QM_ARB_ERR_CAUSE_CHOISE_WDT_SHIFT 1 +#define DMA0_QM_ARB_ERR_CAUSE_CHOISE_WDT_MASK 0x2 +#define DMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT 2 +#define DMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK 0x4 + +/* DMA0_QM_ARB_ERR_MSG_EN */ +#define DMA0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_SHIFT 0 +#define DMA0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1 +#define DMA0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_SHIFT 1 +#define DMA0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2 +#define DMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT 2 +#define DMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4 + +/* DMA0_QM_ARB_ERR_STS_DRP */ +#define DMA0_QM_ARB_ERR_STS_DRP_VAL_SHIFT 0 +#define DMA0_QM_ARB_ERR_STS_DRP_VAL_MASK 0x3 + +/* DMA0_QM_ARB_MST_CRED_STS */ +#define DMA0_QM_ARB_MST_CRED_STS_VAL_SHIFT 0 +#define DMA0_QM_ARB_MST_CRED_STS_VAL_MASK 0x7F + +/* DMA0_QM_CGM_CFG */ +#define DMA0_QM_CGM_CFG_IDLE_TH_SHIFT 0 +#define DMA0_QM_CGM_CFG_IDLE_TH_MASK 0xFFF +#define DMA0_QM_CGM_CFG_G2F_TH_SHIFT 16 +#define DMA0_QM_CGM_CFG_G2F_TH_MASK 0xFF0000 +#define DMA0_QM_CGM_CFG_CP_IDLE_MASK_SHIFT 24 +#define DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK 0x1F000000 +#define DMA0_QM_CGM_CFG_EN_SHIFT 31 +#define DMA0_QM_CGM_CFG_EN_MASK 0x80000000 + +/* DMA0_QM_CGM_STS */ +#define DMA0_QM_CGM_STS_ST_SHIFT 0 +#define DMA0_QM_CGM_STS_ST_MASK 0x3 +#define DMA0_QM_CGM_STS_CG_SHIFT 4 +#define DMA0_QM_CGM_STS_CG_MASK 0x10 +#define DMA0_QM_CGM_STS_AGENT_IDLE_SHIFT 8 +#define DMA0_QM_CGM_STS_AGENT_IDLE_MASK 0x100 +#define DMA0_QM_CGM_STS_AXI_IDLE_SHIFT 9 +#define DMA0_QM_CGM_STS_AXI_IDLE_MASK 0x200 +#define DMA0_QM_CGM_STS_CP_IDLE_SHIFT 10 +#define DMA0_QM_CGM_STS_CP_IDLE_MASK 0x400 + +/* DMA0_QM_CGM_CFG1 */ +#define DMA0_QM_CGM_CFG1_MASK_TH_SHIFT 0 +#define DMA0_QM_CGM_CFG1_MASK_TH_MASK 0xFF + +/* DMA0_QM_LOCAL_RANGE_BASE */ +#define DMA0_QM_LOCAL_RANGE_BASE_VAL_SHIFT 0 +#define DMA0_QM_LOCAL_RANGE_BASE_VAL_MASK 0xFFFF + +/* DMA0_QM_LOCAL_RANGE_SIZE */ +#define DMA0_QM_LOCAL_RANGE_SIZE_VAL_SHIFT 0 +#define DMA0_QM_LOCAL_RANGE_SIZE_VAL_MASK 0xFFFF + +/* DMA0_QM_CSMR_STRICT_PRIO_CFG */ +#define DMA0_QM_CSMR_STRICT_PRIO_CFG_TYPE_SHIFT 0 +#define DMA0_QM_CSMR_STRICT_PRIO_CFG_TYPE_MASK 0x1 + +/* DMA0_QM_HBW_RD_RATE_LIM_CFG_1 */ +#define DMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define DMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define DMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT 31 +#define DMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* DMA0_QM_LBW_WR_RATE_LIM_CFG_0 */ +#define DMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define DMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define DMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define DMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* DMA0_QM_LBW_WR_RATE_LIM_CFG_1 */ +#define DMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define DMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define DMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT 31 +#define DMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* DMA0_QM_HBW_RD_RATE_LIM_CFG_0 */ +#define DMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define DMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define DMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define DMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* DMA0_QM_GLBL_AXCACHE */ +#define DMA0_QM_GLBL_AXCACHE_AR_SHIFT 0 +#define DMA0_QM_GLBL_AXCACHE_AR_MASK 0xF +#define DMA0_QM_GLBL_AXCACHE_AW_SHIFT 16 +#define DMA0_QM_GLBL_AXCACHE_AW_MASK 0xF0000 + +/* DMA0_QM_IND_GW_APB_CFG */ +#define DMA0_QM_IND_GW_APB_CFG_ADDR_SHIFT 0 +#define DMA0_QM_IND_GW_APB_CFG_ADDR_MASK 0x7FFFFFFF +#define DMA0_QM_IND_GW_APB_CFG_CMD_SHIFT 31 +#define DMA0_QM_IND_GW_APB_CFG_CMD_MASK 0x80000000 + +/* DMA0_QM_IND_GW_APB_WDATA */ +#define DMA0_QM_IND_GW_APB_WDATA_VAL_SHIFT 0 +#define DMA0_QM_IND_GW_APB_WDATA_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_IND_GW_APB_RDATA */ +#define DMA0_QM_IND_GW_APB_RDATA_VAL_SHIFT 0 +#define DMA0_QM_IND_GW_APB_RDATA_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_IND_GW_APB_STATUS */ +#define DMA0_QM_IND_GW_APB_STATUS_RDY_SHIFT 0 +#define DMA0_QM_IND_GW_APB_STATUS_RDY_MASK 0x1 +#define DMA0_QM_IND_GW_APB_STATUS_ERR_SHIFT 1 +#define DMA0_QM_IND_GW_APB_STATUS_ERR_MASK 0x2 + +/* DMA0_QM_GLBL_ERR_ADDR_LO */ +#define DMA0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 +#define DMA0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_GLBL_ERR_ADDR_HI */ +#define DMA0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 +#define DMA0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_GLBL_ERR_WDATA */ +#define DMA0_QM_GLBL_ERR_WDATA_VAL_SHIFT 0 +#define DMA0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_GLBL_MEM_INIT_BUSY */ +#define DMA0_QM_GLBL_MEM_INIT_BUSY_RBUF_SHIFT 0 +#define DMA0_QM_GLBL_MEM_INIT_BUSY_RBUF_MASK 0xF + +#endif /* ASIC_REG_DMA0_QM_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_qm_regs.h new file mode 100644 index 000000000000..8e56a93d88a1 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA0_QM_REGS_H_ +#define ASIC_REG_DMA0_QM_REGS_H_ + +/* + ***************************************** + * DMA0_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA0_QM_GLBL_CFG0 0x508000 + +#define mmDMA0_QM_GLBL_CFG1 0x508004 + +#define mmDMA0_QM_GLBL_PROT 0x508008 + +#define mmDMA0_QM_GLBL_ERR_CFG 0x50800C + +#define mmDMA0_QM_GLBL_SECURE_PROPS_0 0x508010 + +#define mmDMA0_QM_GLBL_SECURE_PROPS_1 0x508014 + +#define mmDMA0_QM_GLBL_SECURE_PROPS_2 0x508018 + +#define mmDMA0_QM_GLBL_SECURE_PROPS_3 0x50801C + +#define mmDMA0_QM_GLBL_SECURE_PROPS_4 0x508020 + +#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_0 0x508024 + +#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_1 0x508028 + +#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_2 0x50802C + +#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_3 0x508030 + +#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_4 0x508034 + +#define mmDMA0_QM_GLBL_STS0 0x508038 + +#define mmDMA0_QM_GLBL_STS1_0 0x508040 + +#define mmDMA0_QM_GLBL_STS1_1 0x508044 + +#define mmDMA0_QM_GLBL_STS1_2 0x508048 + +#define mmDMA0_QM_GLBL_STS1_3 0x50804C + +#define mmDMA0_QM_GLBL_STS1_4 0x508050 + +#define mmDMA0_QM_GLBL_MSG_EN_0 0x508054 + +#define mmDMA0_QM_GLBL_MSG_EN_1 0x508058 + +#define mmDMA0_QM_GLBL_MSG_EN_2 0x50805C + +#define mmDMA0_QM_GLBL_MSG_EN_3 0x508060 + +#define mmDMA0_QM_GLBL_MSG_EN_4 0x508068 + +#define mmDMA0_QM_PQ_BASE_LO_0 0x508070 + +#define mmDMA0_QM_PQ_BASE_LO_1 0x508074 + +#define mmDMA0_QM_PQ_BASE_LO_2 0x508078 + +#define mmDMA0_QM_PQ_BASE_LO_3 0x50807C + +#define mmDMA0_QM_PQ_BASE_HI_0 0x508080 + +#define mmDMA0_QM_PQ_BASE_HI_1 0x508084 + +#define mmDMA0_QM_PQ_BASE_HI_2 0x508088 + +#define mmDMA0_QM_PQ_BASE_HI_3 0x50808C + +#define mmDMA0_QM_PQ_SIZE_0 0x508090 + +#define mmDMA0_QM_PQ_SIZE_1 0x508094 + +#define mmDMA0_QM_PQ_SIZE_2 0x508098 + +#define mmDMA0_QM_PQ_SIZE_3 0x50809C + +#define mmDMA0_QM_PQ_PI_0 0x5080A0 + +#define mmDMA0_QM_PQ_PI_1 0x5080A4 + +#define mmDMA0_QM_PQ_PI_2 0x5080A8 + +#define mmDMA0_QM_PQ_PI_3 0x5080AC + +#define mmDMA0_QM_PQ_CI_0 0x5080B0 + +#define mmDMA0_QM_PQ_CI_1 0x5080B4 + +#define mmDMA0_QM_PQ_CI_2 0x5080B8 + +#define mmDMA0_QM_PQ_CI_3 0x5080BC + +#define mmDMA0_QM_PQ_CFG0_0 0x5080C0 + +#define mmDMA0_QM_PQ_CFG0_1 0x5080C4 + +#define mmDMA0_QM_PQ_CFG0_2 0x5080C8 + +#define mmDMA0_QM_PQ_CFG0_3 0x5080CC + +#define mmDMA0_QM_PQ_CFG1_0 0x5080D0 + +#define mmDMA0_QM_PQ_CFG1_1 0x5080D4 + +#define mmDMA0_QM_PQ_CFG1_2 0x5080D8 + +#define mmDMA0_QM_PQ_CFG1_3 0x5080DC + +#define mmDMA0_QM_PQ_ARUSER_31_11_0 0x5080E0 + +#define mmDMA0_QM_PQ_ARUSER_31_11_1 0x5080E4 + +#define mmDMA0_QM_PQ_ARUSER_31_11_2 0x5080E8 + +#define mmDMA0_QM_PQ_ARUSER_31_11_3 0x5080EC + +#define mmDMA0_QM_PQ_STS0_0 0x5080F0 + +#define mmDMA0_QM_PQ_STS0_1 0x5080F4 + +#define mmDMA0_QM_PQ_STS0_2 0x5080F8 + +#define mmDMA0_QM_PQ_STS0_3 0x5080FC + +#define mmDMA0_QM_PQ_STS1_0 0x508100 + +#define mmDMA0_QM_PQ_STS1_1 0x508104 + +#define mmDMA0_QM_PQ_STS1_2 0x508108 + +#define mmDMA0_QM_PQ_STS1_3 0x50810C + +#define mmDMA0_QM_CQ_CFG0_0 0x508110 + +#define mmDMA0_QM_CQ_CFG0_1 0x508114 + +#define mmDMA0_QM_CQ_CFG0_2 0x508118 + +#define mmDMA0_QM_CQ_CFG0_3 0x50811C + +#define mmDMA0_QM_CQ_CFG0_4 0x508120 + +#define mmDMA0_QM_CQ_CFG1_0 0x508124 + +#define mmDMA0_QM_CQ_CFG1_1 0x508128 + +#define mmDMA0_QM_CQ_CFG1_2 0x50812C + +#define mmDMA0_QM_CQ_CFG1_3 0x508130 + +#define mmDMA0_QM_CQ_CFG1_4 0x508134 + +#define mmDMA0_QM_CQ_ARUSER_31_11_0 0x508138 + +#define mmDMA0_QM_CQ_ARUSER_31_11_1 0x50813C + +#define mmDMA0_QM_CQ_ARUSER_31_11_2 0x508140 + +#define mmDMA0_QM_CQ_ARUSER_31_11_3 0x508144 + +#define mmDMA0_QM_CQ_ARUSER_31_11_4 0x508148 + +#define mmDMA0_QM_CQ_STS0_0 0x50814C + +#define mmDMA0_QM_CQ_STS0_1 0x508150 + +#define mmDMA0_QM_CQ_STS0_2 0x508154 + +#define mmDMA0_QM_CQ_STS0_3 0x508158 + +#define mmDMA0_QM_CQ_STS0_4 0x50815C + +#define mmDMA0_QM_CQ_STS1_0 0x508160 + +#define mmDMA0_QM_CQ_STS1_1 0x508164 + +#define mmDMA0_QM_CQ_STS1_2 0x508168 + +#define mmDMA0_QM_CQ_STS1_3 0x50816C + +#define mmDMA0_QM_CQ_STS1_4 0x508170 + +#define mmDMA0_QM_CQ_PTR_LO_0 0x508174 + +#define mmDMA0_QM_CQ_PTR_HI_0 0x508178 + +#define mmDMA0_QM_CQ_TSIZE_0 0x50817C + +#define mmDMA0_QM_CQ_CTL_0 0x508180 + +#define mmDMA0_QM_CQ_PTR_LO_1 0x508184 + +#define mmDMA0_QM_CQ_PTR_HI_1 0x508188 + +#define mmDMA0_QM_CQ_TSIZE_1 0x50818C + +#define mmDMA0_QM_CQ_CTL_1 0x508190 + +#define mmDMA0_QM_CQ_PTR_LO_2 0x508194 + +#define mmDMA0_QM_CQ_PTR_HI_2 0x508198 + +#define mmDMA0_QM_CQ_TSIZE_2 0x50819C + +#define mmDMA0_QM_CQ_CTL_2 0x5081A0 + +#define mmDMA0_QM_CQ_PTR_LO_3 0x5081A4 + +#define mmDMA0_QM_CQ_PTR_HI_3 0x5081A8 + +#define mmDMA0_QM_CQ_TSIZE_3 0x5081AC + +#define mmDMA0_QM_CQ_CTL_3 0x5081B0 + +#define mmDMA0_QM_CQ_PTR_LO_4 0x5081B4 + +#define mmDMA0_QM_CQ_PTR_HI_4 0x5081B8 + +#define mmDMA0_QM_CQ_TSIZE_4 0x5081BC + +#define mmDMA0_QM_CQ_CTL_4 0x5081C0 + +#define mmDMA0_QM_CQ_PTR_LO_STS_0 0x5081C4 + +#define mmDMA0_QM_CQ_PTR_LO_STS_1 0x5081C8 + +#define mmDMA0_QM_CQ_PTR_LO_STS_2 0x5081CC + +#define mmDMA0_QM_CQ_PTR_LO_STS_3 0x5081D0 + +#define mmDMA0_QM_CQ_PTR_LO_STS_4 0x5081D4 + +#define mmDMA0_QM_CQ_PTR_HI_STS_0 0x5081D8 + +#define mmDMA0_QM_CQ_PTR_HI_STS_1 0x5081DC + +#define mmDMA0_QM_CQ_PTR_HI_STS_2 0x5081E0 + +#define mmDMA0_QM_CQ_PTR_HI_STS_3 0x5081E4 + +#define mmDMA0_QM_CQ_PTR_HI_STS_4 0x5081E8 + +#define mmDMA0_QM_CQ_TSIZE_STS_0 0x5081EC + +#define mmDMA0_QM_CQ_TSIZE_STS_1 0x5081F0 + +#define mmDMA0_QM_CQ_TSIZE_STS_2 0x5081F4 + +#define mmDMA0_QM_CQ_TSIZE_STS_3 0x5081F8 + +#define mmDMA0_QM_CQ_TSIZE_STS_4 0x5081FC + +#define mmDMA0_QM_CQ_CTL_STS_0 0x508200 + +#define mmDMA0_QM_CQ_CTL_STS_1 0x508204 + +#define mmDMA0_QM_CQ_CTL_STS_2 0x508208 + +#define mmDMA0_QM_CQ_CTL_STS_3 0x50820C + +#define mmDMA0_QM_CQ_CTL_STS_4 0x508210 + +#define mmDMA0_QM_CQ_IFIFO_CNT_0 0x508214 + +#define mmDMA0_QM_CQ_IFIFO_CNT_1 0x508218 + +#define mmDMA0_QM_CQ_IFIFO_CNT_2 0x50821C + +#define mmDMA0_QM_CQ_IFIFO_CNT_3 0x508220 + +#define mmDMA0_QM_CQ_IFIFO_CNT_4 0x508224 + +#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 0x508228 + +#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_1 0x50822C + +#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_2 0x508230 + +#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_3 0x508234 + +#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_4 0x508238 + +#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 0x50823C + +#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_1 0x508240 + +#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_2 0x508244 + +#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_3 0x508248 + +#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_4 0x50824C + +#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 0x508250 + +#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_1 0x508254 + +#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_2 0x508258 + +#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_3 0x50825C + +#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_4 0x508260 + +#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 0x508264 + +#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_1 0x508268 + +#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_2 0x50826C + +#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_3 0x508270 + +#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_4 0x508274 + +#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 0x508278 + +#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_1 0x50827C + +#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 0x508280 + +#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_3 0x508284 + +#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_4 0x508288 + +#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 0x50828C + +#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_1 0x508290 + +#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_2 0x508294 + +#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_3 0x508298 + +#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_4 0x50829C + +#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 0x5082A0 + +#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_1 0x5082A4 + +#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_2 0x5082A8 + +#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_3 0x5082AC + +#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_4 0x5082B0 + +#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 0x5082B4 + +#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_1 0x5082B8 + +#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_2 0x5082BC + +#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_3 0x5082C0 + +#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_4 0x5082C4 + +#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 0x5082C8 + +#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_1 0x5082CC + +#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_2 0x5082D0 + +#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_3 0x5082D4 + +#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_4 0x5082D8 + +#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5082E0 + +#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5082E4 + +#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5082E8 + +#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5082EC + +#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5082F0 + +#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5082F4 + +#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5082F8 + +#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5082FC + +#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x508300 + +#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x508304 + +#define mmDMA0_QM_CP_FENCE0_RDATA_0 0x508308 + +#define mmDMA0_QM_CP_FENCE0_RDATA_1 0x50830C + +#define mmDMA0_QM_CP_FENCE0_RDATA_2 0x508310 + +#define mmDMA0_QM_CP_FENCE0_RDATA_3 0x508314 + +#define mmDMA0_QM_CP_FENCE0_RDATA_4 0x508318 + +#define mmDMA0_QM_CP_FENCE1_RDATA_0 0x50831C + +#define mmDMA0_QM_CP_FENCE1_RDATA_1 0x508320 + +#define mmDMA0_QM_CP_FENCE1_RDATA_2 0x508324 + +#define mmDMA0_QM_CP_FENCE1_RDATA_3 0x508328 + +#define mmDMA0_QM_CP_FENCE1_RDATA_4 0x50832C + +#define mmDMA0_QM_CP_FENCE2_RDATA_0 0x508330 + +#define mmDMA0_QM_CP_FENCE2_RDATA_1 0x508334 + +#define mmDMA0_QM_CP_FENCE2_RDATA_2 0x508338 + +#define mmDMA0_QM_CP_FENCE2_RDATA_3 0x50833C + +#define mmDMA0_QM_CP_FENCE2_RDATA_4 0x508340 + +#define mmDMA0_QM_CP_FENCE3_RDATA_0 0x508344 + +#define mmDMA0_QM_CP_FENCE3_RDATA_1 0x508348 + +#define mmDMA0_QM_CP_FENCE3_RDATA_2 0x50834C + +#define mmDMA0_QM_CP_FENCE3_RDATA_3 0x508350 + +#define mmDMA0_QM_CP_FENCE3_RDATA_4 0x508354 + +#define mmDMA0_QM_CP_FENCE0_CNT_0 0x508358 + +#define mmDMA0_QM_CP_FENCE0_CNT_1 0x50835C + +#define mmDMA0_QM_CP_FENCE0_CNT_2 0x508360 + +#define mmDMA0_QM_CP_FENCE0_CNT_3 0x508364 + +#define mmDMA0_QM_CP_FENCE0_CNT_4 0x508368 + +#define mmDMA0_QM_CP_FENCE1_CNT_0 0x50836C + +#define mmDMA0_QM_CP_FENCE1_CNT_1 0x508370 + +#define mmDMA0_QM_CP_FENCE1_CNT_2 0x508374 + +#define mmDMA0_QM_CP_FENCE1_CNT_3 0x508378 + +#define mmDMA0_QM_CP_FENCE1_CNT_4 0x50837C + +#define mmDMA0_QM_CP_FENCE2_CNT_0 0x508380 + +#define mmDMA0_QM_CP_FENCE2_CNT_1 0x508384 + +#define mmDMA0_QM_CP_FENCE2_CNT_2 0x508388 + +#define mmDMA0_QM_CP_FENCE2_CNT_3 0x50838C + +#define mmDMA0_QM_CP_FENCE2_CNT_4 0x508390 + +#define mmDMA0_QM_CP_FENCE3_CNT_0 0x508394 + +#define mmDMA0_QM_CP_FENCE3_CNT_1 0x508398 + +#define mmDMA0_QM_CP_FENCE3_CNT_2 0x50839C + +#define mmDMA0_QM_CP_FENCE3_CNT_3 0x5083A0 + +#define mmDMA0_QM_CP_FENCE3_CNT_4 0x5083A4 + +#define mmDMA0_QM_CP_STS_0 0x5083A8 + +#define mmDMA0_QM_CP_STS_1 0x5083AC + +#define mmDMA0_QM_CP_STS_2 0x5083B0 + +#define mmDMA0_QM_CP_STS_3 0x5083B4 + +#define mmDMA0_QM_CP_STS_4 0x5083B8 + +#define mmDMA0_QM_CP_CURRENT_INST_LO_0 0x5083BC + +#define mmDMA0_QM_CP_CURRENT_INST_LO_1 0x5083C0 + +#define mmDMA0_QM_CP_CURRENT_INST_LO_2 0x5083C4 + +#define mmDMA0_QM_CP_CURRENT_INST_LO_3 0x5083C8 + +#define mmDMA0_QM_CP_CURRENT_INST_LO_4 0x5083CC + +#define mmDMA0_QM_CP_CURRENT_INST_HI_0 0x5083D0 + +#define mmDMA0_QM_CP_CURRENT_INST_HI_1 0x5083D4 + +#define mmDMA0_QM_CP_CURRENT_INST_HI_2 0x5083D8 + +#define mmDMA0_QM_CP_CURRENT_INST_HI_3 0x5083DC + +#define mmDMA0_QM_CP_CURRENT_INST_HI_4 0x5083E0 + +#define mmDMA0_QM_CP_BARRIER_CFG_0 0x5083F4 + +#define mmDMA0_QM_CP_BARRIER_CFG_1 0x5083F8 + +#define mmDMA0_QM_CP_BARRIER_CFG_2 0x5083FC + +#define mmDMA0_QM_CP_BARRIER_CFG_3 0x508400 + +#define mmDMA0_QM_CP_BARRIER_CFG_4 0x508404 + +#define mmDMA0_QM_CP_DBG_0_0 0x508408 + +#define mmDMA0_QM_CP_DBG_0_1 0x50840C + +#define mmDMA0_QM_CP_DBG_0_2 0x508410 + +#define mmDMA0_QM_CP_DBG_0_3 0x508414 + +#define mmDMA0_QM_CP_DBG_0_4 0x508418 + +#define mmDMA0_QM_CP_ARUSER_31_11_0 0x50841C + +#define mmDMA0_QM_CP_ARUSER_31_11_1 0x508420 + +#define mmDMA0_QM_CP_ARUSER_31_11_2 0x508424 + +#define mmDMA0_QM_CP_ARUSER_31_11_3 0x508428 + +#define mmDMA0_QM_CP_ARUSER_31_11_4 0x50842C + +#define mmDMA0_QM_CP_AWUSER_31_11_0 0x508430 + +#define mmDMA0_QM_CP_AWUSER_31_11_1 0x508434 + +#define mmDMA0_QM_CP_AWUSER_31_11_2 0x508438 + +#define mmDMA0_QM_CP_AWUSER_31_11_3 0x50843C + +#define mmDMA0_QM_CP_AWUSER_31_11_4 0x508440 + +#define mmDMA0_QM_ARB_CFG_0 0x508A00 + +#define mmDMA0_QM_ARB_CHOISE_Q_PUSH 0x508A04 + +#define mmDMA0_QM_ARB_WRR_WEIGHT_0 0x508A08 + +#define mmDMA0_QM_ARB_WRR_WEIGHT_1 0x508A0C + +#define mmDMA0_QM_ARB_WRR_WEIGHT_2 0x508A10 + +#define mmDMA0_QM_ARB_WRR_WEIGHT_3 0x508A14 + +#define mmDMA0_QM_ARB_CFG_1 0x508A18 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_0 0x508A20 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_1 0x508A24 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_2 0x508A28 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_3 0x508A2C + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_4 0x508A30 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_5 0x508A34 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_6 0x508A38 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_7 0x508A3C + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_8 0x508A40 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_9 0x508A44 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_10 0x508A48 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_11 0x508A4C + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_12 0x508A50 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_13 0x508A54 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_14 0x508A58 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_15 0x508A5C + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_16 0x508A60 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_17 0x508A64 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_18 0x508A68 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_19 0x508A6C + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_20 0x508A70 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_21 0x508A74 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_22 0x508A78 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_23 0x508A7C + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_24 0x508A80 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_25 0x508A84 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_26 0x508A88 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_27 0x508A8C + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_28 0x508A90 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_29 0x508A94 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_30 0x508A98 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_31 0x508A9C + +#define mmDMA0_QM_ARB_MST_CRED_INC 0x508AA0 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x508AA4 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x508AA8 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x508AAC + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x508AB0 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x508AB4 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x508AB8 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x508ABC + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x508AC0 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x508AC4 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x508AC8 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x508ACC + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x508AD0 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x508AD4 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x508AD8 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x508ADC + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x508AE0 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x508AE4 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x508AE8 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x508AEC + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x508AF0 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x508AF4 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x508AF8 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x508AFC + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x508B00 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x508B04 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x508B08 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x508B0C + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x508B10 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x508B14 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x508B18 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x508B1C + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x508B20 + +#define mmDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x508B28 + +#define mmDMA0_QM_ARB_MST_SLAVE_EN 0x508B2C + +#define mmDMA0_QM_ARB_MST_QUIET_PER 0x508B34 + +#define mmDMA0_QM_ARB_SLV_CHOISE_WDT 0x508B38 + +#define mmDMA0_QM_ARB_SLV_ID 0x508B3C + +#define mmDMA0_QM_ARB_MSG_MAX_INFLIGHT 0x508B44 + +#define mmDMA0_QM_ARB_MSG_AWUSER_31_11 0x508B48 + +#define mmDMA0_QM_ARB_MSG_AWUSER_SEC_PROP 0x508B4C + +#define mmDMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x508B50 + +#define mmDMA0_QM_ARB_BASE_LO 0x508B54 + +#define mmDMA0_QM_ARB_BASE_HI 0x508B58 + +#define mmDMA0_QM_ARB_STATE_STS 0x508B80 + +#define mmDMA0_QM_ARB_CHOISE_FULLNESS_STS 0x508B84 + +#define mmDMA0_QM_ARB_MSG_STS 0x508B88 + +#define mmDMA0_QM_ARB_SLV_CHOISE_Q_HEAD 0x508B8C + +#define mmDMA0_QM_ARB_ERR_CAUSE 0x508B9C + +#define mmDMA0_QM_ARB_ERR_MSG_EN 0x508BA0 + +#define mmDMA0_QM_ARB_ERR_STS_DRP 0x508BA8 + +#define mmDMA0_QM_ARB_MST_CRED_STS_0 0x508BB0 + +#define mmDMA0_QM_ARB_MST_CRED_STS_1 0x508BB4 + +#define mmDMA0_QM_ARB_MST_CRED_STS_2 0x508BB8 + +#define mmDMA0_QM_ARB_MST_CRED_STS_3 0x508BBC + +#define mmDMA0_QM_ARB_MST_CRED_STS_4 0x508BC0 + +#define mmDMA0_QM_ARB_MST_CRED_STS_5 0x508BC4 + +#define mmDMA0_QM_ARB_MST_CRED_STS_6 0x508BC8 + +#define mmDMA0_QM_ARB_MST_CRED_STS_7 0x508BCC + +#define mmDMA0_QM_ARB_MST_CRED_STS_8 0x508BD0 + +#define mmDMA0_QM_ARB_MST_CRED_STS_9 0x508BD4 + +#define mmDMA0_QM_ARB_MST_CRED_STS_10 0x508BD8 + +#define mmDMA0_QM_ARB_MST_CRED_STS_11 0x508BDC + +#define mmDMA0_QM_ARB_MST_CRED_STS_12 0x508BE0 + +#define mmDMA0_QM_ARB_MST_CRED_STS_13 0x508BE4 + +#define mmDMA0_QM_ARB_MST_CRED_STS_14 0x508BE8 + +#define mmDMA0_QM_ARB_MST_CRED_STS_15 0x508BEC + +#define mmDMA0_QM_ARB_MST_CRED_STS_16 0x508BF0 + +#define mmDMA0_QM_ARB_MST_CRED_STS_17 0x508BF4 + +#define mmDMA0_QM_ARB_MST_CRED_STS_18 0x508BF8 + +#define mmDMA0_QM_ARB_MST_CRED_STS_19 0x508BFC + +#define mmDMA0_QM_ARB_MST_CRED_STS_20 0x508C00 + +#define mmDMA0_QM_ARB_MST_CRED_STS_21 0x508C04 + +#define mmDMA0_QM_ARB_MST_CRED_STS_22 0x508C08 + +#define mmDMA0_QM_ARB_MST_CRED_STS_23 0x508C0C + +#define mmDMA0_QM_ARB_MST_CRED_STS_24 0x508C10 + +#define mmDMA0_QM_ARB_MST_CRED_STS_25 0x508C14 + +#define mmDMA0_QM_ARB_MST_CRED_STS_26 0x508C18 + +#define mmDMA0_QM_ARB_MST_CRED_STS_27 0x508C1C + +#define mmDMA0_QM_ARB_MST_CRED_STS_28 0x508C20 + +#define mmDMA0_QM_ARB_MST_CRED_STS_29 0x508C24 + +#define mmDMA0_QM_ARB_MST_CRED_STS_30 0x508C28 + +#define mmDMA0_QM_ARB_MST_CRED_STS_31 0x508C2C + +#define mmDMA0_QM_CGM_CFG 0x508C70 + +#define mmDMA0_QM_CGM_STS 0x508C74 + +#define mmDMA0_QM_CGM_CFG1 0x508C78 + +#define mmDMA0_QM_LOCAL_RANGE_BASE 0x508C80 + +#define mmDMA0_QM_LOCAL_RANGE_SIZE 0x508C84 + +#define mmDMA0_QM_CSMR_STRICT_PRIO_CFG 0x508C90 + +#define mmDMA0_QM_HBW_RD_RATE_LIM_CFG_1 0x508C94 + +#define mmDMA0_QM_LBW_WR_RATE_LIM_CFG_0 0x508C98 + +#define mmDMA0_QM_LBW_WR_RATE_LIM_CFG_1 0x508C9C + +#define mmDMA0_QM_HBW_RD_RATE_LIM_CFG_0 0x508CA0 + +#define mmDMA0_QM_GLBL_AXCACHE 0x508CA4 + +#define mmDMA0_QM_IND_GW_APB_CFG 0x508CB0 + +#define mmDMA0_QM_IND_GW_APB_WDATA 0x508CB4 + +#define mmDMA0_QM_IND_GW_APB_RDATA 0x508CB8 + +#define mmDMA0_QM_IND_GW_APB_STATUS 0x508CBC + +#define mmDMA0_QM_GLBL_ERR_ADDR_LO 0x508CD0 + +#define mmDMA0_QM_GLBL_ERR_ADDR_HI 0x508CD4 + +#define mmDMA0_QM_GLBL_ERR_WDATA 0x508CD8 + +#define mmDMA0_QM_GLBL_MEM_INIT_BUSY 0x508D00 + +#endif /* ASIC_REG_DMA0_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma1_core_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma1_core_regs.h new file mode 100644 index 000000000000..4d8d8f26c5d4 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma1_core_regs.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA1_CORE_REGS_H_ +#define ASIC_REG_DMA1_CORE_REGS_H_ + +/* + ***************************************** + * DMA1_CORE (Prototype: DMA_CORE) + ***************************************** + */ + +#define mmDMA1_CORE_CFG_0 0x520000 + +#define mmDMA1_CORE_CFG_1 0x520004 + +#define mmDMA1_CORE_LBW_MAX_OUTSTAND 0x520008 + +#define mmDMA1_CORE_SRC_BASE_LO 0x520014 + +#define mmDMA1_CORE_SRC_BASE_HI 0x520018 + +#define mmDMA1_CORE_DST_BASE_LO 0x52001C + +#define mmDMA1_CORE_DST_BASE_HI 0x520020 + +#define mmDMA1_CORE_SRC_TSIZE_1 0x52002C + +#define mmDMA1_CORE_SRC_STRIDE_1 0x520030 + +#define mmDMA1_CORE_SRC_TSIZE_2 0x520034 + +#define mmDMA1_CORE_SRC_STRIDE_2 0x520038 + +#define mmDMA1_CORE_SRC_TSIZE_3 0x52003C + +#define mmDMA1_CORE_SRC_STRIDE_3 0x520040 + +#define mmDMA1_CORE_SRC_TSIZE_4 0x520044 + +#define mmDMA1_CORE_SRC_STRIDE_4 0x520048 + +#define mmDMA1_CORE_SRC_TSIZE_0 0x52004C + +#define mmDMA1_CORE_DST_TSIZE_1 0x520054 + +#define mmDMA1_CORE_DST_STRIDE_1 0x520058 + +#define mmDMA1_CORE_DST_TSIZE_2 0x52005C + +#define mmDMA1_CORE_DST_STRIDE_2 0x520060 + +#define mmDMA1_CORE_DST_TSIZE_3 0x520064 + +#define mmDMA1_CORE_DST_STRIDE_3 0x520068 + +#define mmDMA1_CORE_DST_TSIZE_4 0x52006C + +#define mmDMA1_CORE_DST_STRIDE_4 0x520070 + +#define mmDMA1_CORE_DST_TSIZE_0 0x520074 + +#define mmDMA1_CORE_COMMIT 0x520078 + +#define mmDMA1_CORE_WR_COMP_WDATA 0x52007C + +#define mmDMA1_CORE_WR_COMP_ADDR_LO 0x520080 + +#define mmDMA1_CORE_WR_COMP_ADDR_HI 0x520084 + +#define mmDMA1_CORE_WR_COMP_AWUSER_31_11 0x520088 + +#define mmDMA1_CORE_TE_NUMROWS 0x520094 + +#define mmDMA1_CORE_PROT 0x5200B8 + +#define mmDMA1_CORE_SECURE_PROPS 0x5200F0 + +#define mmDMA1_CORE_NON_SECURE_PROPS 0x5200F4 + +#define mmDMA1_CORE_RD_MAX_OUTSTAND 0x520100 + +#define mmDMA1_CORE_RD_MAX_SIZE 0x520104 + +#define mmDMA1_CORE_RD_ARCACHE 0x520108 + +#define mmDMA1_CORE_RD_ARUSER_31_11 0x520110 + +#define mmDMA1_CORE_RD_INFLIGHTS 0x520114 + +#define mmDMA1_CORE_WR_MAX_OUTSTAND 0x520120 + +#define mmDMA1_CORE_WR_MAX_AWID 0x520124 + +#define mmDMA1_CORE_WR_AWCACHE 0x520128 + +#define mmDMA1_CORE_WR_AWUSER_31_11 0x520130 + +#define mmDMA1_CORE_WR_INFLIGHTS 0x520134 + +#define mmDMA1_CORE_RD_RATE_LIM_CFG_0 0x520150 + +#define mmDMA1_CORE_RD_RATE_LIM_CFG_1 0x520154 + +#define mmDMA1_CORE_WR_RATE_LIM_CFG_0 0x520158 + +#define mmDMA1_CORE_WR_RATE_LIM_CFG_1 0x52015C + +#define mmDMA1_CORE_ERR_CFG 0x520160 + +#define mmDMA1_CORE_ERR_CAUSE 0x520164 + +#define mmDMA1_CORE_ERRMSG_ADDR_LO 0x520170 + +#define mmDMA1_CORE_ERRMSG_ADDR_HI 0x520174 + +#define mmDMA1_CORE_ERRMSG_WDATA 0x520178 + +#define mmDMA1_CORE_STS0 0x520190 + +#define mmDMA1_CORE_STS1 0x520194 + +#define mmDMA1_CORE_RD_DBGMEM_ADD 0x520200 + +#define mmDMA1_CORE_RD_DBGMEM_DATA_WR 0x520204 + +#define mmDMA1_CORE_RD_DBGMEM_DATA_RD 0x520208 + +#define mmDMA1_CORE_RD_DBGMEM_CTRL 0x52020C + +#define mmDMA1_CORE_RD_DBGMEM_RC 0x520210 + +#define mmDMA1_CORE_DBG_HBW_AXI_AR_CNT 0x520220 + +#define mmDMA1_CORE_DBG_HBW_AXI_AW_CNT 0x520224 + +#define mmDMA1_CORE_DBG_LBW_AXI_AW_CNT 0x520228 + +#define mmDMA1_CORE_DBG_DESC_CNT 0x52022C + +#define mmDMA1_CORE_DBG_STS 0x520230 + +#define mmDMA1_CORE_DBG_RD_DESC_ID 0x520234 + +#define mmDMA1_CORE_DBG_WR_DESC_ID 0x520238 + +#endif /* ASIC_REG_DMA1_CORE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma1_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma1_qm_regs.h new file mode 100644 index 000000000000..c3ef300849be --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma1_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA1_QM_REGS_H_ +#define ASIC_REG_DMA1_QM_REGS_H_ + +/* + ***************************************** + * DMA1_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA1_QM_GLBL_CFG0 0x528000 + +#define mmDMA1_QM_GLBL_CFG1 0x528004 + +#define mmDMA1_QM_GLBL_PROT 0x528008 + +#define mmDMA1_QM_GLBL_ERR_CFG 0x52800C + +#define mmDMA1_QM_GLBL_SECURE_PROPS_0 0x528010 + +#define mmDMA1_QM_GLBL_SECURE_PROPS_1 0x528014 + +#define mmDMA1_QM_GLBL_SECURE_PROPS_2 0x528018 + +#define mmDMA1_QM_GLBL_SECURE_PROPS_3 0x52801C + +#define mmDMA1_QM_GLBL_SECURE_PROPS_4 0x528020 + +#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_0 0x528024 + +#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_1 0x528028 + +#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_2 0x52802C + +#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_3 0x528030 + +#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_4 0x528034 + +#define mmDMA1_QM_GLBL_STS0 0x528038 + +#define mmDMA1_QM_GLBL_STS1_0 0x528040 + +#define mmDMA1_QM_GLBL_STS1_1 0x528044 + +#define mmDMA1_QM_GLBL_STS1_2 0x528048 + +#define mmDMA1_QM_GLBL_STS1_3 0x52804C + +#define mmDMA1_QM_GLBL_STS1_4 0x528050 + +#define mmDMA1_QM_GLBL_MSG_EN_0 0x528054 + +#define mmDMA1_QM_GLBL_MSG_EN_1 0x528058 + +#define mmDMA1_QM_GLBL_MSG_EN_2 0x52805C + +#define mmDMA1_QM_GLBL_MSG_EN_3 0x528060 + +#define mmDMA1_QM_GLBL_MSG_EN_4 0x528068 + +#define mmDMA1_QM_PQ_BASE_LO_0 0x528070 + +#define mmDMA1_QM_PQ_BASE_LO_1 0x528074 + +#define mmDMA1_QM_PQ_BASE_LO_2 0x528078 + +#define mmDMA1_QM_PQ_BASE_LO_3 0x52807C + +#define mmDMA1_QM_PQ_BASE_HI_0 0x528080 + +#define mmDMA1_QM_PQ_BASE_HI_1 0x528084 + +#define mmDMA1_QM_PQ_BASE_HI_2 0x528088 + +#define mmDMA1_QM_PQ_BASE_HI_3 0x52808C + +#define mmDMA1_QM_PQ_SIZE_0 0x528090 + +#define mmDMA1_QM_PQ_SIZE_1 0x528094 + +#define mmDMA1_QM_PQ_SIZE_2 0x528098 + +#define mmDMA1_QM_PQ_SIZE_3 0x52809C + +#define mmDMA1_QM_PQ_PI_0 0x5280A0 + +#define mmDMA1_QM_PQ_PI_1 0x5280A4 + +#define mmDMA1_QM_PQ_PI_2 0x5280A8 + +#define mmDMA1_QM_PQ_PI_3 0x5280AC + +#define mmDMA1_QM_PQ_CI_0 0x5280B0 + +#define mmDMA1_QM_PQ_CI_1 0x5280B4 + +#define mmDMA1_QM_PQ_CI_2 0x5280B8 + +#define mmDMA1_QM_PQ_CI_3 0x5280BC + +#define mmDMA1_QM_PQ_CFG0_0 0x5280C0 + +#define mmDMA1_QM_PQ_CFG0_1 0x5280C4 + +#define mmDMA1_QM_PQ_CFG0_2 0x5280C8 + +#define mmDMA1_QM_PQ_CFG0_3 0x5280CC + +#define mmDMA1_QM_PQ_CFG1_0 0x5280D0 + +#define mmDMA1_QM_PQ_CFG1_1 0x5280D4 + +#define mmDMA1_QM_PQ_CFG1_2 0x5280D8 + +#define mmDMA1_QM_PQ_CFG1_3 0x5280DC + +#define mmDMA1_QM_PQ_ARUSER_31_11_0 0x5280E0 + +#define mmDMA1_QM_PQ_ARUSER_31_11_1 0x5280E4 + +#define mmDMA1_QM_PQ_ARUSER_31_11_2 0x5280E8 + +#define mmDMA1_QM_PQ_ARUSER_31_11_3 0x5280EC + +#define mmDMA1_QM_PQ_STS0_0 0x5280F0 + +#define mmDMA1_QM_PQ_STS0_1 0x5280F4 + +#define mmDMA1_QM_PQ_STS0_2 0x5280F8 + +#define mmDMA1_QM_PQ_STS0_3 0x5280FC + +#define mmDMA1_QM_PQ_STS1_0 0x528100 + +#define mmDMA1_QM_PQ_STS1_1 0x528104 + +#define mmDMA1_QM_PQ_STS1_2 0x528108 + +#define mmDMA1_QM_PQ_STS1_3 0x52810C + +#define mmDMA1_QM_CQ_CFG0_0 0x528110 + +#define mmDMA1_QM_CQ_CFG0_1 0x528114 + +#define mmDMA1_QM_CQ_CFG0_2 0x528118 + +#define mmDMA1_QM_CQ_CFG0_3 0x52811C + +#define mmDMA1_QM_CQ_CFG0_4 0x528120 + +#define mmDMA1_QM_CQ_CFG1_0 0x528124 + +#define mmDMA1_QM_CQ_CFG1_1 0x528128 + +#define mmDMA1_QM_CQ_CFG1_2 0x52812C + +#define mmDMA1_QM_CQ_CFG1_3 0x528130 + +#define mmDMA1_QM_CQ_CFG1_4 0x528134 + +#define mmDMA1_QM_CQ_ARUSER_31_11_0 0x528138 + +#define mmDMA1_QM_CQ_ARUSER_31_11_1 0x52813C + +#define mmDMA1_QM_CQ_ARUSER_31_11_2 0x528140 + +#define mmDMA1_QM_CQ_ARUSER_31_11_3 0x528144 + +#define mmDMA1_QM_CQ_ARUSER_31_11_4 0x528148 + +#define mmDMA1_QM_CQ_STS0_0 0x52814C + +#define mmDMA1_QM_CQ_STS0_1 0x528150 + +#define mmDMA1_QM_CQ_STS0_2 0x528154 + +#define mmDMA1_QM_CQ_STS0_3 0x528158 + +#define mmDMA1_QM_CQ_STS0_4 0x52815C + +#define mmDMA1_QM_CQ_STS1_0 0x528160 + +#define mmDMA1_QM_CQ_STS1_1 0x528164 + +#define mmDMA1_QM_CQ_STS1_2 0x528168 + +#define mmDMA1_QM_CQ_STS1_3 0x52816C + +#define mmDMA1_QM_CQ_STS1_4 0x528170 + +#define mmDMA1_QM_CQ_PTR_LO_0 0x528174 + +#define mmDMA1_QM_CQ_PTR_HI_0 0x528178 + +#define mmDMA1_QM_CQ_TSIZE_0 0x52817C + +#define mmDMA1_QM_CQ_CTL_0 0x528180 + +#define mmDMA1_QM_CQ_PTR_LO_1 0x528184 + +#define mmDMA1_QM_CQ_PTR_HI_1 0x528188 + +#define mmDMA1_QM_CQ_TSIZE_1 0x52818C + +#define mmDMA1_QM_CQ_CTL_1 0x528190 + +#define mmDMA1_QM_CQ_PTR_LO_2 0x528194 + +#define mmDMA1_QM_CQ_PTR_HI_2 0x528198 + +#define mmDMA1_QM_CQ_TSIZE_2 0x52819C + +#define mmDMA1_QM_CQ_CTL_2 0x5281A0 + +#define mmDMA1_QM_CQ_PTR_LO_3 0x5281A4 + +#define mmDMA1_QM_CQ_PTR_HI_3 0x5281A8 + +#define mmDMA1_QM_CQ_TSIZE_3 0x5281AC + +#define mmDMA1_QM_CQ_CTL_3 0x5281B0 + +#define mmDMA1_QM_CQ_PTR_LO_4 0x5281B4 + +#define mmDMA1_QM_CQ_PTR_HI_4 0x5281B8 + +#define mmDMA1_QM_CQ_TSIZE_4 0x5281BC + +#define mmDMA1_QM_CQ_CTL_4 0x5281C0 + +#define mmDMA1_QM_CQ_PTR_LO_STS_0 0x5281C4 + +#define mmDMA1_QM_CQ_PTR_LO_STS_1 0x5281C8 + +#define mmDMA1_QM_CQ_PTR_LO_STS_2 0x5281CC + +#define mmDMA1_QM_CQ_PTR_LO_STS_3 0x5281D0 + +#define mmDMA1_QM_CQ_PTR_LO_STS_4 0x5281D4 + +#define mmDMA1_QM_CQ_PTR_HI_STS_0 0x5281D8 + +#define mmDMA1_QM_CQ_PTR_HI_STS_1 0x5281DC + +#define mmDMA1_QM_CQ_PTR_HI_STS_2 0x5281E0 + +#define mmDMA1_QM_CQ_PTR_HI_STS_3 0x5281E4 + +#define mmDMA1_QM_CQ_PTR_HI_STS_4 0x5281E8 + +#define mmDMA1_QM_CQ_TSIZE_STS_0 0x5281EC + +#define mmDMA1_QM_CQ_TSIZE_STS_1 0x5281F0 + +#define mmDMA1_QM_CQ_TSIZE_STS_2 0x5281F4 + +#define mmDMA1_QM_CQ_TSIZE_STS_3 0x5281F8 + +#define mmDMA1_QM_CQ_TSIZE_STS_4 0x5281FC + +#define mmDMA1_QM_CQ_CTL_STS_0 0x528200 + +#define mmDMA1_QM_CQ_CTL_STS_1 0x528204 + +#define mmDMA1_QM_CQ_CTL_STS_2 0x528208 + +#define mmDMA1_QM_CQ_CTL_STS_3 0x52820C + +#define mmDMA1_QM_CQ_CTL_STS_4 0x528210 + +#define mmDMA1_QM_CQ_IFIFO_CNT_0 0x528214 + +#define mmDMA1_QM_CQ_IFIFO_CNT_1 0x528218 + +#define mmDMA1_QM_CQ_IFIFO_CNT_2 0x52821C + +#define mmDMA1_QM_CQ_IFIFO_CNT_3 0x528220 + +#define mmDMA1_QM_CQ_IFIFO_CNT_4 0x528224 + +#define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_0 0x528228 + +#define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_1 0x52822C + +#define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_2 0x528230 + +#define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_3 0x528234 + +#define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_4 0x528238 + +#define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_0 0x52823C + +#define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_1 0x528240 + +#define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_2 0x528244 + +#define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_3 0x528248 + +#define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_4 0x52824C + +#define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_0 0x528250 + +#define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_1 0x528254 + +#define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_2 0x528258 + +#define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_3 0x52825C + +#define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_4 0x528260 + +#define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_0 0x528264 + +#define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_1 0x528268 + +#define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_2 0x52826C + +#define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_3 0x528270 + +#define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_4 0x528274 + +#define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_0 0x528278 + +#define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_1 0x52827C + +#define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_2 0x528280 + +#define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_3 0x528284 + +#define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_4 0x528288 + +#define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_0 0x52828C + +#define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_1 0x528290 + +#define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_2 0x528294 + +#define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_3 0x528298 + +#define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_4 0x52829C + +#define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_0 0x5282A0 + +#define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_1 0x5282A4 + +#define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_2 0x5282A8 + +#define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_3 0x5282AC + +#define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_4 0x5282B0 + +#define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_0 0x5282B4 + +#define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_1 0x5282B8 + +#define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_2 0x5282BC + +#define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_3 0x5282C0 + +#define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_4 0x5282C4 + +#define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_0 0x5282C8 + +#define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_1 0x5282CC + +#define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_2 0x5282D0 + +#define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_3 0x5282D4 + +#define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_4 0x5282D8 + +#define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5282E0 + +#define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5282E4 + +#define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5282E8 + +#define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5282EC + +#define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5282F0 + +#define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5282F4 + +#define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5282F8 + +#define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5282FC + +#define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x528300 + +#define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x528304 + +#define mmDMA1_QM_CP_FENCE0_RDATA_0 0x528308 + +#define mmDMA1_QM_CP_FENCE0_RDATA_1 0x52830C + +#define mmDMA1_QM_CP_FENCE0_RDATA_2 0x528310 + +#define mmDMA1_QM_CP_FENCE0_RDATA_3 0x528314 + +#define mmDMA1_QM_CP_FENCE0_RDATA_4 0x528318 + +#define mmDMA1_QM_CP_FENCE1_RDATA_0 0x52831C + +#define mmDMA1_QM_CP_FENCE1_RDATA_1 0x528320 + +#define mmDMA1_QM_CP_FENCE1_RDATA_2 0x528324 + +#define mmDMA1_QM_CP_FENCE1_RDATA_3 0x528328 + +#define mmDMA1_QM_CP_FENCE1_RDATA_4 0x52832C + +#define mmDMA1_QM_CP_FENCE2_RDATA_0 0x528330 + +#define mmDMA1_QM_CP_FENCE2_RDATA_1 0x528334 + +#define mmDMA1_QM_CP_FENCE2_RDATA_2 0x528338 + +#define mmDMA1_QM_CP_FENCE2_RDATA_3 0x52833C + +#define mmDMA1_QM_CP_FENCE2_RDATA_4 0x528340 + +#define mmDMA1_QM_CP_FENCE3_RDATA_0 0x528344 + +#define mmDMA1_QM_CP_FENCE3_RDATA_1 0x528348 + +#define mmDMA1_QM_CP_FENCE3_RDATA_2 0x52834C + +#define mmDMA1_QM_CP_FENCE3_RDATA_3 0x528350 + +#define mmDMA1_QM_CP_FENCE3_RDATA_4 0x528354 + +#define mmDMA1_QM_CP_FENCE0_CNT_0 0x528358 + +#define mmDMA1_QM_CP_FENCE0_CNT_1 0x52835C + +#define mmDMA1_QM_CP_FENCE0_CNT_2 0x528360 + +#define mmDMA1_QM_CP_FENCE0_CNT_3 0x528364 + +#define mmDMA1_QM_CP_FENCE0_CNT_4 0x528368 + +#define mmDMA1_QM_CP_FENCE1_CNT_0 0x52836C + +#define mmDMA1_QM_CP_FENCE1_CNT_1 0x528370 + +#define mmDMA1_QM_CP_FENCE1_CNT_2 0x528374 + +#define mmDMA1_QM_CP_FENCE1_CNT_3 0x528378 + +#define mmDMA1_QM_CP_FENCE1_CNT_4 0x52837C + +#define mmDMA1_QM_CP_FENCE2_CNT_0 0x528380 + +#define mmDMA1_QM_CP_FENCE2_CNT_1 0x528384 + +#define mmDMA1_QM_CP_FENCE2_CNT_2 0x528388 + +#define mmDMA1_QM_CP_FENCE2_CNT_3 0x52838C + +#define mmDMA1_QM_CP_FENCE2_CNT_4 0x528390 + +#define mmDMA1_QM_CP_FENCE3_CNT_0 0x528394 + +#define mmDMA1_QM_CP_FENCE3_CNT_1 0x528398 + +#define mmDMA1_QM_CP_FENCE3_CNT_2 0x52839C + +#define mmDMA1_QM_CP_FENCE3_CNT_3 0x5283A0 + +#define mmDMA1_QM_CP_FENCE3_CNT_4 0x5283A4 + +#define mmDMA1_QM_CP_STS_0 0x5283A8 + +#define mmDMA1_QM_CP_STS_1 0x5283AC + +#define mmDMA1_QM_CP_STS_2 0x5283B0 + +#define mmDMA1_QM_CP_STS_3 0x5283B4 + +#define mmDMA1_QM_CP_STS_4 0x5283B8 + +#define mmDMA1_QM_CP_CURRENT_INST_LO_0 0x5283BC + +#define mmDMA1_QM_CP_CURRENT_INST_LO_1 0x5283C0 + +#define mmDMA1_QM_CP_CURRENT_INST_LO_2 0x5283C4 + +#define mmDMA1_QM_CP_CURRENT_INST_LO_3 0x5283C8 + +#define mmDMA1_QM_CP_CURRENT_INST_LO_4 0x5283CC + +#define mmDMA1_QM_CP_CURRENT_INST_HI_0 0x5283D0 + +#define mmDMA1_QM_CP_CURRENT_INST_HI_1 0x5283D4 + +#define mmDMA1_QM_CP_CURRENT_INST_HI_2 0x5283D8 + +#define mmDMA1_QM_CP_CURRENT_INST_HI_3 0x5283DC + +#define mmDMA1_QM_CP_CURRENT_INST_HI_4 0x5283E0 + +#define mmDMA1_QM_CP_BARRIER_CFG_0 0x5283F4 + +#define mmDMA1_QM_CP_BARRIER_CFG_1 0x5283F8 + +#define mmDMA1_QM_CP_BARRIER_CFG_2 0x5283FC + +#define mmDMA1_QM_CP_BARRIER_CFG_3 0x528400 + +#define mmDMA1_QM_CP_BARRIER_CFG_4 0x528404 + +#define mmDMA1_QM_CP_DBG_0_0 0x528408 + +#define mmDMA1_QM_CP_DBG_0_1 0x52840C + +#define mmDMA1_QM_CP_DBG_0_2 0x528410 + +#define mmDMA1_QM_CP_DBG_0_3 0x528414 + +#define mmDMA1_QM_CP_DBG_0_4 0x528418 + +#define mmDMA1_QM_CP_ARUSER_31_11_0 0x52841C + +#define mmDMA1_QM_CP_ARUSER_31_11_1 0x528420 + +#define mmDMA1_QM_CP_ARUSER_31_11_2 0x528424 + +#define mmDMA1_QM_CP_ARUSER_31_11_3 0x528428 + +#define mmDMA1_QM_CP_ARUSER_31_11_4 0x52842C + +#define mmDMA1_QM_CP_AWUSER_31_11_0 0x528430 + +#define mmDMA1_QM_CP_AWUSER_31_11_1 0x528434 + +#define mmDMA1_QM_CP_AWUSER_31_11_2 0x528438 + +#define mmDMA1_QM_CP_AWUSER_31_11_3 0x52843C + +#define mmDMA1_QM_CP_AWUSER_31_11_4 0x528440 + +#define mmDMA1_QM_ARB_CFG_0 0x528A00 + +#define mmDMA1_QM_ARB_CHOISE_Q_PUSH 0x528A04 + +#define mmDMA1_QM_ARB_WRR_WEIGHT_0 0x528A08 + +#define mmDMA1_QM_ARB_WRR_WEIGHT_1 0x528A0C + +#define mmDMA1_QM_ARB_WRR_WEIGHT_2 0x528A10 + +#define mmDMA1_QM_ARB_WRR_WEIGHT_3 0x528A14 + +#define mmDMA1_QM_ARB_CFG_1 0x528A18 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_0 0x528A20 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_1 0x528A24 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_2 0x528A28 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_3 0x528A2C + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_4 0x528A30 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_5 0x528A34 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_6 0x528A38 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_7 0x528A3C + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_8 0x528A40 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_9 0x528A44 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_10 0x528A48 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_11 0x528A4C + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_12 0x528A50 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_13 0x528A54 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_14 0x528A58 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_15 0x528A5C + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_16 0x528A60 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_17 0x528A64 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_18 0x528A68 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_19 0x528A6C + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_20 0x528A70 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_21 0x528A74 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_22 0x528A78 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_23 0x528A7C + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_24 0x528A80 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_25 0x528A84 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_26 0x528A88 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_27 0x528A8C + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_28 0x528A90 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_29 0x528A94 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_30 0x528A98 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_31 0x528A9C + +#define mmDMA1_QM_ARB_MST_CRED_INC 0x528AA0 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x528AA4 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x528AA8 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x528AAC + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x528AB0 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x528AB4 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x528AB8 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x528ABC + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x528AC0 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x528AC4 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x528AC8 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x528ACC + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x528AD0 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x528AD4 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x528AD8 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x528ADC + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x528AE0 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x528AE4 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x528AE8 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x528AEC + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x528AF0 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x528AF4 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x528AF8 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x528AFC + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x528B00 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x528B04 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x528B08 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x528B0C + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x528B10 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x528B14 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x528B18 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x528B1C + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x528B20 + +#define mmDMA1_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x528B28 + +#define mmDMA1_QM_ARB_MST_SLAVE_EN 0x528B2C + +#define mmDMA1_QM_ARB_MST_QUIET_PER 0x528B34 + +#define mmDMA1_QM_ARB_SLV_CHOISE_WDT 0x528B38 + +#define mmDMA1_QM_ARB_SLV_ID 0x528B3C + +#define mmDMA1_QM_ARB_MSG_MAX_INFLIGHT 0x528B44 + +#define mmDMA1_QM_ARB_MSG_AWUSER_31_11 0x528B48 + +#define mmDMA1_QM_ARB_MSG_AWUSER_SEC_PROP 0x528B4C + +#define mmDMA1_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x528B50 + +#define mmDMA1_QM_ARB_BASE_LO 0x528B54 + +#define mmDMA1_QM_ARB_BASE_HI 0x528B58 + +#define mmDMA1_QM_ARB_STATE_STS 0x528B80 + +#define mmDMA1_QM_ARB_CHOISE_FULLNESS_STS 0x528B84 + +#define mmDMA1_QM_ARB_MSG_STS 0x528B88 + +#define mmDMA1_QM_ARB_SLV_CHOISE_Q_HEAD 0x528B8C + +#define mmDMA1_QM_ARB_ERR_CAUSE 0x528B9C + +#define mmDMA1_QM_ARB_ERR_MSG_EN 0x528BA0 + +#define mmDMA1_QM_ARB_ERR_STS_DRP 0x528BA8 + +#define mmDMA1_QM_ARB_MST_CRED_STS_0 0x528BB0 + +#define mmDMA1_QM_ARB_MST_CRED_STS_1 0x528BB4 + +#define mmDMA1_QM_ARB_MST_CRED_STS_2 0x528BB8 + +#define mmDMA1_QM_ARB_MST_CRED_STS_3 0x528BBC + +#define mmDMA1_QM_ARB_MST_CRED_STS_4 0x528BC0 + +#define mmDMA1_QM_ARB_MST_CRED_STS_5 0x528BC4 + +#define mmDMA1_QM_ARB_MST_CRED_STS_6 0x528BC8 + +#define mmDMA1_QM_ARB_MST_CRED_STS_7 0x528BCC + +#define mmDMA1_QM_ARB_MST_CRED_STS_8 0x528BD0 + +#define mmDMA1_QM_ARB_MST_CRED_STS_9 0x528BD4 + +#define mmDMA1_QM_ARB_MST_CRED_STS_10 0x528BD8 + +#define mmDMA1_QM_ARB_MST_CRED_STS_11 0x528BDC + +#define mmDMA1_QM_ARB_MST_CRED_STS_12 0x528BE0 + +#define mmDMA1_QM_ARB_MST_CRED_STS_13 0x528BE4 + +#define mmDMA1_QM_ARB_MST_CRED_STS_14 0x528BE8 + +#define mmDMA1_QM_ARB_MST_CRED_STS_15 0x528BEC + +#define mmDMA1_QM_ARB_MST_CRED_STS_16 0x528BF0 + +#define mmDMA1_QM_ARB_MST_CRED_STS_17 0x528BF4 + +#define mmDMA1_QM_ARB_MST_CRED_STS_18 0x528BF8 + +#define mmDMA1_QM_ARB_MST_CRED_STS_19 0x528BFC + +#define mmDMA1_QM_ARB_MST_CRED_STS_20 0x528C00 + +#define mmDMA1_QM_ARB_MST_CRED_STS_21 0x528C04 + +#define mmDMA1_QM_ARB_MST_CRED_STS_22 0x528C08 + +#define mmDMA1_QM_ARB_MST_CRED_STS_23 0x528C0C + +#define mmDMA1_QM_ARB_MST_CRED_STS_24 0x528C10 + +#define mmDMA1_QM_ARB_MST_CRED_STS_25 0x528C14 + +#define mmDMA1_QM_ARB_MST_CRED_STS_26 0x528C18 + +#define mmDMA1_QM_ARB_MST_CRED_STS_27 0x528C1C + +#define mmDMA1_QM_ARB_MST_CRED_STS_28 0x528C20 + +#define mmDMA1_QM_ARB_MST_CRED_STS_29 0x528C24 + +#define mmDMA1_QM_ARB_MST_CRED_STS_30 0x528C28 + +#define mmDMA1_QM_ARB_MST_CRED_STS_31 0x528C2C + +#define mmDMA1_QM_CGM_CFG 0x528C70 + +#define mmDMA1_QM_CGM_STS 0x528C74 + +#define mmDMA1_QM_CGM_CFG1 0x528C78 + +#define mmDMA1_QM_LOCAL_RANGE_BASE 0x528C80 + +#define mmDMA1_QM_LOCAL_RANGE_SIZE 0x528C84 + +#define mmDMA1_QM_CSMR_STRICT_PRIO_CFG 0x528C90 + +#define mmDMA1_QM_HBW_RD_RATE_LIM_CFG_1 0x528C94 + +#define mmDMA1_QM_LBW_WR_RATE_LIM_CFG_0 0x528C98 + +#define mmDMA1_QM_LBW_WR_RATE_LIM_CFG_1 0x528C9C + +#define mmDMA1_QM_HBW_RD_RATE_LIM_CFG_0 0x528CA0 + +#define mmDMA1_QM_GLBL_AXCACHE 0x528CA4 + +#define mmDMA1_QM_IND_GW_APB_CFG 0x528CB0 + +#define mmDMA1_QM_IND_GW_APB_WDATA 0x528CB4 + +#define mmDMA1_QM_IND_GW_APB_RDATA 0x528CB8 + +#define mmDMA1_QM_IND_GW_APB_STATUS 0x528CBC + +#define mmDMA1_QM_GLBL_ERR_ADDR_LO 0x528CD0 + +#define mmDMA1_QM_GLBL_ERR_ADDR_HI 0x528CD4 + +#define mmDMA1_QM_GLBL_ERR_WDATA 0x528CD8 + +#define mmDMA1_QM_GLBL_MEM_INIT_BUSY 0x528D00 + +#endif /* ASIC_REG_DMA1_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma2_core_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma2_core_regs.h new file mode 100644 index 000000000000..a42862cd5ae0 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma2_core_regs.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA2_CORE_REGS_H_ +#define ASIC_REG_DMA2_CORE_REGS_H_ + +/* + ***************************************** + * DMA2_CORE (Prototype: DMA_CORE) + ***************************************** + */ + +#define mmDMA2_CORE_CFG_0 0x540000 + +#define mmDMA2_CORE_CFG_1 0x540004 + +#define mmDMA2_CORE_LBW_MAX_OUTSTAND 0x540008 + +#define mmDMA2_CORE_SRC_BASE_LO 0x540014 + +#define mmDMA2_CORE_SRC_BASE_HI 0x540018 + +#define mmDMA2_CORE_DST_BASE_LO 0x54001C + +#define mmDMA2_CORE_DST_BASE_HI 0x540020 + +#define mmDMA2_CORE_SRC_TSIZE_1 0x54002C + +#define mmDMA2_CORE_SRC_STRIDE_1 0x540030 + +#define mmDMA2_CORE_SRC_TSIZE_2 0x540034 + +#define mmDMA2_CORE_SRC_STRIDE_2 0x540038 + +#define mmDMA2_CORE_SRC_TSIZE_3 0x54003C + +#define mmDMA2_CORE_SRC_STRIDE_3 0x540040 + +#define mmDMA2_CORE_SRC_TSIZE_4 0x540044 + +#define mmDMA2_CORE_SRC_STRIDE_4 0x540048 + +#define mmDMA2_CORE_SRC_TSIZE_0 0x54004C + +#define mmDMA2_CORE_DST_TSIZE_1 0x540054 + +#define mmDMA2_CORE_DST_STRIDE_1 0x540058 + +#define mmDMA2_CORE_DST_TSIZE_2 0x54005C + +#define mmDMA2_CORE_DST_STRIDE_2 0x540060 + +#define mmDMA2_CORE_DST_TSIZE_3 0x540064 + +#define mmDMA2_CORE_DST_STRIDE_3 0x540068 + +#define mmDMA2_CORE_DST_TSIZE_4 0x54006C + +#define mmDMA2_CORE_DST_STRIDE_4 0x540070 + +#define mmDMA2_CORE_DST_TSIZE_0 0x540074 + +#define mmDMA2_CORE_COMMIT 0x540078 + +#define mmDMA2_CORE_WR_COMP_WDATA 0x54007C + +#define mmDMA2_CORE_WR_COMP_ADDR_LO 0x540080 + +#define mmDMA2_CORE_WR_COMP_ADDR_HI 0x540084 + +#define mmDMA2_CORE_WR_COMP_AWUSER_31_11 0x540088 + +#define mmDMA2_CORE_TE_NUMROWS 0x540094 + +#define mmDMA2_CORE_PROT 0x5400B8 + +#define mmDMA2_CORE_SECURE_PROPS 0x5400F0 + +#define mmDMA2_CORE_NON_SECURE_PROPS 0x5400F4 + +#define mmDMA2_CORE_RD_MAX_OUTSTAND 0x540100 + +#define mmDMA2_CORE_RD_MAX_SIZE 0x540104 + +#define mmDMA2_CORE_RD_ARCACHE 0x540108 + +#define mmDMA2_CORE_RD_ARUSER_31_11 0x540110 + +#define mmDMA2_CORE_RD_INFLIGHTS 0x540114 + +#define mmDMA2_CORE_WR_MAX_OUTSTAND 0x540120 + +#define mmDMA2_CORE_WR_MAX_AWID 0x540124 + +#define mmDMA2_CORE_WR_AWCACHE 0x540128 + +#define mmDMA2_CORE_WR_AWUSER_31_11 0x540130 + +#define mmDMA2_CORE_WR_INFLIGHTS 0x540134 + +#define mmDMA2_CORE_RD_RATE_LIM_CFG_0 0x540150 + +#define mmDMA2_CORE_RD_RATE_LIM_CFG_1 0x540154 + +#define mmDMA2_CORE_WR_RATE_LIM_CFG_0 0x540158 + +#define mmDMA2_CORE_WR_RATE_LIM_CFG_1 0x54015C + +#define mmDMA2_CORE_ERR_CFG 0x540160 + +#define mmDMA2_CORE_ERR_CAUSE 0x540164 + +#define mmDMA2_CORE_ERRMSG_ADDR_LO 0x540170 + +#define mmDMA2_CORE_ERRMSG_ADDR_HI 0x540174 + +#define mmDMA2_CORE_ERRMSG_WDATA 0x540178 + +#define mmDMA2_CORE_STS0 0x540190 + +#define mmDMA2_CORE_STS1 0x540194 + +#define mmDMA2_CORE_RD_DBGMEM_ADD 0x540200 + +#define mmDMA2_CORE_RD_DBGMEM_DATA_WR 0x540204 + +#define mmDMA2_CORE_RD_DBGMEM_DATA_RD 0x540208 + +#define mmDMA2_CORE_RD_DBGMEM_CTRL 0x54020C + +#define mmDMA2_CORE_RD_DBGMEM_RC 0x540210 + +#define mmDMA2_CORE_DBG_HBW_AXI_AR_CNT 0x540220 + +#define mmDMA2_CORE_DBG_HBW_AXI_AW_CNT 0x540224 + +#define mmDMA2_CORE_DBG_LBW_AXI_AW_CNT 0x540228 + +#define mmDMA2_CORE_DBG_DESC_CNT 0x54022C + +#define mmDMA2_CORE_DBG_STS 0x540230 + +#define mmDMA2_CORE_DBG_RD_DESC_ID 0x540234 + +#define mmDMA2_CORE_DBG_WR_DESC_ID 0x540238 + +#endif /* ASIC_REG_DMA2_CORE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma2_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma2_qm_regs.h new file mode 100644 index 000000000000..8c4d4e016852 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma2_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA2_QM_REGS_H_ +#define ASIC_REG_DMA2_QM_REGS_H_ + +/* + ***************************************** + * DMA2_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA2_QM_GLBL_CFG0 0x548000 + +#define mmDMA2_QM_GLBL_CFG1 0x548004 + +#define mmDMA2_QM_GLBL_PROT 0x548008 + +#define mmDMA2_QM_GLBL_ERR_CFG 0x54800C + +#define mmDMA2_QM_GLBL_SECURE_PROPS_0 0x548010 + +#define mmDMA2_QM_GLBL_SECURE_PROPS_1 0x548014 + +#define mmDMA2_QM_GLBL_SECURE_PROPS_2 0x548018 + +#define mmDMA2_QM_GLBL_SECURE_PROPS_3 0x54801C + +#define mmDMA2_QM_GLBL_SECURE_PROPS_4 0x548020 + +#define mmDMA2_QM_GLBL_NON_SECURE_PROPS_0 0x548024 + +#define mmDMA2_QM_GLBL_NON_SECURE_PROPS_1 0x548028 + +#define mmDMA2_QM_GLBL_NON_SECURE_PROPS_2 0x54802C + +#define mmDMA2_QM_GLBL_NON_SECURE_PROPS_3 0x548030 + +#define mmDMA2_QM_GLBL_NON_SECURE_PROPS_4 0x548034 + +#define mmDMA2_QM_GLBL_STS0 0x548038 + +#define mmDMA2_QM_GLBL_STS1_0 0x548040 + +#define mmDMA2_QM_GLBL_STS1_1 0x548044 + +#define mmDMA2_QM_GLBL_STS1_2 0x548048 + +#define mmDMA2_QM_GLBL_STS1_3 0x54804C + +#define mmDMA2_QM_GLBL_STS1_4 0x548050 + +#define mmDMA2_QM_GLBL_MSG_EN_0 0x548054 + +#define mmDMA2_QM_GLBL_MSG_EN_1 0x548058 + +#define mmDMA2_QM_GLBL_MSG_EN_2 0x54805C + +#define mmDMA2_QM_GLBL_MSG_EN_3 0x548060 + +#define mmDMA2_QM_GLBL_MSG_EN_4 0x548068 + +#define mmDMA2_QM_PQ_BASE_LO_0 0x548070 + +#define mmDMA2_QM_PQ_BASE_LO_1 0x548074 + +#define mmDMA2_QM_PQ_BASE_LO_2 0x548078 + +#define mmDMA2_QM_PQ_BASE_LO_3 0x54807C + +#define mmDMA2_QM_PQ_BASE_HI_0 0x548080 + +#define mmDMA2_QM_PQ_BASE_HI_1 0x548084 + +#define mmDMA2_QM_PQ_BASE_HI_2 0x548088 + +#define mmDMA2_QM_PQ_BASE_HI_3 0x54808C + +#define mmDMA2_QM_PQ_SIZE_0 0x548090 + +#define mmDMA2_QM_PQ_SIZE_1 0x548094 + +#define mmDMA2_QM_PQ_SIZE_2 0x548098 + +#define mmDMA2_QM_PQ_SIZE_3 0x54809C + +#define mmDMA2_QM_PQ_PI_0 0x5480A0 + +#define mmDMA2_QM_PQ_PI_1 0x5480A4 + +#define mmDMA2_QM_PQ_PI_2 0x5480A8 + +#define mmDMA2_QM_PQ_PI_3 0x5480AC + +#define mmDMA2_QM_PQ_CI_0 0x5480B0 + +#define mmDMA2_QM_PQ_CI_1 0x5480B4 + +#define mmDMA2_QM_PQ_CI_2 0x5480B8 + +#define mmDMA2_QM_PQ_CI_3 0x5480BC + +#define mmDMA2_QM_PQ_CFG0_0 0x5480C0 + +#define mmDMA2_QM_PQ_CFG0_1 0x5480C4 + +#define mmDMA2_QM_PQ_CFG0_2 0x5480C8 + +#define mmDMA2_QM_PQ_CFG0_3 0x5480CC + +#define mmDMA2_QM_PQ_CFG1_0 0x5480D0 + +#define mmDMA2_QM_PQ_CFG1_1 0x5480D4 + +#define mmDMA2_QM_PQ_CFG1_2 0x5480D8 + +#define mmDMA2_QM_PQ_CFG1_3 0x5480DC + +#define mmDMA2_QM_PQ_ARUSER_31_11_0 0x5480E0 + +#define mmDMA2_QM_PQ_ARUSER_31_11_1 0x5480E4 + +#define mmDMA2_QM_PQ_ARUSER_31_11_2 0x5480E8 + +#define mmDMA2_QM_PQ_ARUSER_31_11_3 0x5480EC + +#define mmDMA2_QM_PQ_STS0_0 0x5480F0 + +#define mmDMA2_QM_PQ_STS0_1 0x5480F4 + +#define mmDMA2_QM_PQ_STS0_2 0x5480F8 + +#define mmDMA2_QM_PQ_STS0_3 0x5480FC + +#define mmDMA2_QM_PQ_STS1_0 0x548100 + +#define mmDMA2_QM_PQ_STS1_1 0x548104 + +#define mmDMA2_QM_PQ_STS1_2 0x548108 + +#define mmDMA2_QM_PQ_STS1_3 0x54810C + +#define mmDMA2_QM_CQ_CFG0_0 0x548110 + +#define mmDMA2_QM_CQ_CFG0_1 0x548114 + +#define mmDMA2_QM_CQ_CFG0_2 0x548118 + +#define mmDMA2_QM_CQ_CFG0_3 0x54811C + +#define mmDMA2_QM_CQ_CFG0_4 0x548120 + +#define mmDMA2_QM_CQ_CFG1_0 0x548124 + +#define mmDMA2_QM_CQ_CFG1_1 0x548128 + +#define mmDMA2_QM_CQ_CFG1_2 0x54812C + +#define mmDMA2_QM_CQ_CFG1_3 0x548130 + +#define mmDMA2_QM_CQ_CFG1_4 0x548134 + +#define mmDMA2_QM_CQ_ARUSER_31_11_0 0x548138 + +#define mmDMA2_QM_CQ_ARUSER_31_11_1 0x54813C + +#define mmDMA2_QM_CQ_ARUSER_31_11_2 0x548140 + +#define mmDMA2_QM_CQ_ARUSER_31_11_3 0x548144 + +#define mmDMA2_QM_CQ_ARUSER_31_11_4 0x548148 + +#define mmDMA2_QM_CQ_STS0_0 0x54814C + +#define mmDMA2_QM_CQ_STS0_1 0x548150 + +#define mmDMA2_QM_CQ_STS0_2 0x548154 + +#define mmDMA2_QM_CQ_STS0_3 0x548158 + +#define mmDMA2_QM_CQ_STS0_4 0x54815C + +#define mmDMA2_QM_CQ_STS1_0 0x548160 + +#define mmDMA2_QM_CQ_STS1_1 0x548164 + +#define mmDMA2_QM_CQ_STS1_2 0x548168 + +#define mmDMA2_QM_CQ_STS1_3 0x54816C + +#define mmDMA2_QM_CQ_STS1_4 0x548170 + +#define mmDMA2_QM_CQ_PTR_LO_0 0x548174 + +#define mmDMA2_QM_CQ_PTR_HI_0 0x548178 + +#define mmDMA2_QM_CQ_TSIZE_0 0x54817C + +#define mmDMA2_QM_CQ_CTL_0 0x548180 + +#define mmDMA2_QM_CQ_PTR_LO_1 0x548184 + +#define mmDMA2_QM_CQ_PTR_HI_1 0x548188 + +#define mmDMA2_QM_CQ_TSIZE_1 0x54818C + +#define mmDMA2_QM_CQ_CTL_1 0x548190 + +#define mmDMA2_QM_CQ_PTR_LO_2 0x548194 + +#define mmDMA2_QM_CQ_PTR_HI_2 0x548198 + +#define mmDMA2_QM_CQ_TSIZE_2 0x54819C + +#define mmDMA2_QM_CQ_CTL_2 0x5481A0 + +#define mmDMA2_QM_CQ_PTR_LO_3 0x5481A4 + +#define mmDMA2_QM_CQ_PTR_HI_3 0x5481A8 + +#define mmDMA2_QM_CQ_TSIZE_3 0x5481AC + +#define mmDMA2_QM_CQ_CTL_3 0x5481B0 + +#define mmDMA2_QM_CQ_PTR_LO_4 0x5481B4 + +#define mmDMA2_QM_CQ_PTR_HI_4 0x5481B8 + +#define mmDMA2_QM_CQ_TSIZE_4 0x5481BC + +#define mmDMA2_QM_CQ_CTL_4 0x5481C0 + +#define mmDMA2_QM_CQ_PTR_LO_STS_0 0x5481C4 + +#define mmDMA2_QM_CQ_PTR_LO_STS_1 0x5481C8 + +#define mmDMA2_QM_CQ_PTR_LO_STS_2 0x5481CC + +#define mmDMA2_QM_CQ_PTR_LO_STS_3 0x5481D0 + +#define mmDMA2_QM_CQ_PTR_LO_STS_4 0x5481D4 + +#define mmDMA2_QM_CQ_PTR_HI_STS_0 0x5481D8 + +#define mmDMA2_QM_CQ_PTR_HI_STS_1 0x5481DC + +#define mmDMA2_QM_CQ_PTR_HI_STS_2 0x5481E0 + +#define mmDMA2_QM_CQ_PTR_HI_STS_3 0x5481E4 + +#define mmDMA2_QM_CQ_PTR_HI_STS_4 0x5481E8 + +#define mmDMA2_QM_CQ_TSIZE_STS_0 0x5481EC + +#define mmDMA2_QM_CQ_TSIZE_STS_1 0x5481F0 + +#define mmDMA2_QM_CQ_TSIZE_STS_2 0x5481F4 + +#define mmDMA2_QM_CQ_TSIZE_STS_3 0x5481F8 + +#define mmDMA2_QM_CQ_TSIZE_STS_4 0x5481FC + +#define mmDMA2_QM_CQ_CTL_STS_0 0x548200 + +#define mmDMA2_QM_CQ_CTL_STS_1 0x548204 + +#define mmDMA2_QM_CQ_CTL_STS_2 0x548208 + +#define mmDMA2_QM_CQ_CTL_STS_3 0x54820C + +#define mmDMA2_QM_CQ_CTL_STS_4 0x548210 + +#define mmDMA2_QM_CQ_IFIFO_CNT_0 0x548214 + +#define mmDMA2_QM_CQ_IFIFO_CNT_1 0x548218 + +#define mmDMA2_QM_CQ_IFIFO_CNT_2 0x54821C + +#define mmDMA2_QM_CQ_IFIFO_CNT_3 0x548220 + +#define mmDMA2_QM_CQ_IFIFO_CNT_4 0x548224 + +#define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_0 0x548228 + +#define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_1 0x54822C + +#define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_2 0x548230 + +#define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_3 0x548234 + +#define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_4 0x548238 + +#define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_0 0x54823C + +#define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_1 0x548240 + +#define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_2 0x548244 + +#define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_3 0x548248 + +#define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_4 0x54824C + +#define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_0 0x548250 + +#define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_1 0x548254 + +#define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_2 0x548258 + +#define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_3 0x54825C + +#define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_4 0x548260 + +#define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_0 0x548264 + +#define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_1 0x548268 + +#define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_2 0x54826C + +#define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_3 0x548270 + +#define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_4 0x548274 + +#define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_0 0x548278 + +#define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_1 0x54827C + +#define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_2 0x548280 + +#define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_3 0x548284 + +#define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_4 0x548288 + +#define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_0 0x54828C + +#define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_1 0x548290 + +#define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_2 0x548294 + +#define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_3 0x548298 + +#define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_4 0x54829C + +#define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_0 0x5482A0 + +#define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_1 0x5482A4 + +#define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_2 0x5482A8 + +#define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_3 0x5482AC + +#define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_4 0x5482B0 + +#define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_0 0x5482B4 + +#define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_1 0x5482B8 + +#define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_2 0x5482BC + +#define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_3 0x5482C0 + +#define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_4 0x5482C4 + +#define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_0 0x5482C8 + +#define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_1 0x5482CC + +#define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_2 0x5482D0 + +#define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_3 0x5482D4 + +#define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_4 0x5482D8 + +#define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5482E0 + +#define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5482E4 + +#define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5482E8 + +#define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5482EC + +#define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5482F0 + +#define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5482F4 + +#define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5482F8 + +#define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5482FC + +#define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x548300 + +#define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x548304 + +#define mmDMA2_QM_CP_FENCE0_RDATA_0 0x548308 + +#define mmDMA2_QM_CP_FENCE0_RDATA_1 0x54830C + +#define mmDMA2_QM_CP_FENCE0_RDATA_2 0x548310 + +#define mmDMA2_QM_CP_FENCE0_RDATA_3 0x548314 + +#define mmDMA2_QM_CP_FENCE0_RDATA_4 0x548318 + +#define mmDMA2_QM_CP_FENCE1_RDATA_0 0x54831C + +#define mmDMA2_QM_CP_FENCE1_RDATA_1 0x548320 + +#define mmDMA2_QM_CP_FENCE1_RDATA_2 0x548324 + +#define mmDMA2_QM_CP_FENCE1_RDATA_3 0x548328 + +#define mmDMA2_QM_CP_FENCE1_RDATA_4 0x54832C + +#define mmDMA2_QM_CP_FENCE2_RDATA_0 0x548330 + +#define mmDMA2_QM_CP_FENCE2_RDATA_1 0x548334 + +#define mmDMA2_QM_CP_FENCE2_RDATA_2 0x548338 + +#define mmDMA2_QM_CP_FENCE2_RDATA_3 0x54833C + +#define mmDMA2_QM_CP_FENCE2_RDATA_4 0x548340 + +#define mmDMA2_QM_CP_FENCE3_RDATA_0 0x548344 + +#define mmDMA2_QM_CP_FENCE3_RDATA_1 0x548348 + +#define mmDMA2_QM_CP_FENCE3_RDATA_2 0x54834C + +#define mmDMA2_QM_CP_FENCE3_RDATA_3 0x548350 + +#define mmDMA2_QM_CP_FENCE3_RDATA_4 0x548354 + +#define mmDMA2_QM_CP_FENCE0_CNT_0 0x548358 + +#define mmDMA2_QM_CP_FENCE0_CNT_1 0x54835C + +#define mmDMA2_QM_CP_FENCE0_CNT_2 0x548360 + +#define mmDMA2_QM_CP_FENCE0_CNT_3 0x548364 + +#define mmDMA2_QM_CP_FENCE0_CNT_4 0x548368 + +#define mmDMA2_QM_CP_FENCE1_CNT_0 0x54836C + +#define mmDMA2_QM_CP_FENCE1_CNT_1 0x548370 + +#define mmDMA2_QM_CP_FENCE1_CNT_2 0x548374 + +#define mmDMA2_QM_CP_FENCE1_CNT_3 0x548378 + +#define mmDMA2_QM_CP_FENCE1_CNT_4 0x54837C + +#define mmDMA2_QM_CP_FENCE2_CNT_0 0x548380 + +#define mmDMA2_QM_CP_FENCE2_CNT_1 0x548384 + +#define mmDMA2_QM_CP_FENCE2_CNT_2 0x548388 + +#define mmDMA2_QM_CP_FENCE2_CNT_3 0x54838C + +#define mmDMA2_QM_CP_FENCE2_CNT_4 0x548390 + +#define mmDMA2_QM_CP_FENCE3_CNT_0 0x548394 + +#define mmDMA2_QM_CP_FENCE3_CNT_1 0x548398 + +#define mmDMA2_QM_CP_FENCE3_CNT_2 0x54839C + +#define mmDMA2_QM_CP_FENCE3_CNT_3 0x5483A0 + +#define mmDMA2_QM_CP_FENCE3_CNT_4 0x5483A4 + +#define mmDMA2_QM_CP_STS_0 0x5483A8 + +#define mmDMA2_QM_CP_STS_1 0x5483AC + +#define mmDMA2_QM_CP_STS_2 0x5483B0 + +#define mmDMA2_QM_CP_STS_3 0x5483B4 + +#define mmDMA2_QM_CP_STS_4 0x5483B8 + +#define mmDMA2_QM_CP_CURRENT_INST_LO_0 0x5483BC + +#define mmDMA2_QM_CP_CURRENT_INST_LO_1 0x5483C0 + +#define mmDMA2_QM_CP_CURRENT_INST_LO_2 0x5483C4 + +#define mmDMA2_QM_CP_CURRENT_INST_LO_3 0x5483C8 + +#define mmDMA2_QM_CP_CURRENT_INST_LO_4 0x5483CC + +#define mmDMA2_QM_CP_CURRENT_INST_HI_0 0x5483D0 + +#define mmDMA2_QM_CP_CURRENT_INST_HI_1 0x5483D4 + +#define mmDMA2_QM_CP_CURRENT_INST_HI_2 0x5483D8 + +#define mmDMA2_QM_CP_CURRENT_INST_HI_3 0x5483DC + +#define mmDMA2_QM_CP_CURRENT_INST_HI_4 0x5483E0 + +#define mmDMA2_QM_CP_BARRIER_CFG_0 0x5483F4 + +#define mmDMA2_QM_CP_BARRIER_CFG_1 0x5483F8 + +#define mmDMA2_QM_CP_BARRIER_CFG_2 0x5483FC + +#define mmDMA2_QM_CP_BARRIER_CFG_3 0x548400 + +#define mmDMA2_QM_CP_BARRIER_CFG_4 0x548404 + +#define mmDMA2_QM_CP_DBG_0_0 0x548408 + +#define mmDMA2_QM_CP_DBG_0_1 0x54840C + +#define mmDMA2_QM_CP_DBG_0_2 0x548410 + +#define mmDMA2_QM_CP_DBG_0_3 0x548414 + +#define mmDMA2_QM_CP_DBG_0_4 0x548418 + +#define mmDMA2_QM_CP_ARUSER_31_11_0 0x54841C + +#define mmDMA2_QM_CP_ARUSER_31_11_1 0x548420 + +#define mmDMA2_QM_CP_ARUSER_31_11_2 0x548424 + +#define mmDMA2_QM_CP_ARUSER_31_11_3 0x548428 + +#define mmDMA2_QM_CP_ARUSER_31_11_4 0x54842C + +#define mmDMA2_QM_CP_AWUSER_31_11_0 0x548430 + +#define mmDMA2_QM_CP_AWUSER_31_11_1 0x548434 + +#define mmDMA2_QM_CP_AWUSER_31_11_2 0x548438 + +#define mmDMA2_QM_CP_AWUSER_31_11_3 0x54843C + +#define mmDMA2_QM_CP_AWUSER_31_11_4 0x548440 + +#define mmDMA2_QM_ARB_CFG_0 0x548A00 + +#define mmDMA2_QM_ARB_CHOISE_Q_PUSH 0x548A04 + +#define mmDMA2_QM_ARB_WRR_WEIGHT_0 0x548A08 + +#define mmDMA2_QM_ARB_WRR_WEIGHT_1 0x548A0C + +#define mmDMA2_QM_ARB_WRR_WEIGHT_2 0x548A10 + +#define mmDMA2_QM_ARB_WRR_WEIGHT_3 0x548A14 + +#define mmDMA2_QM_ARB_CFG_1 0x548A18 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_0 0x548A20 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_1 0x548A24 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_2 0x548A28 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_3 0x548A2C + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_4 0x548A30 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_5 0x548A34 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_6 0x548A38 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_7 0x548A3C + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_8 0x548A40 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_9 0x548A44 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_10 0x548A48 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_11 0x548A4C + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_12 0x548A50 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_13 0x548A54 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_14 0x548A58 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_15 0x548A5C + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_16 0x548A60 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_17 0x548A64 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_18 0x548A68 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_19 0x548A6C + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_20 0x548A70 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_21 0x548A74 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_22 0x548A78 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_23 0x548A7C + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_24 0x548A80 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_25 0x548A84 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_26 0x548A88 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_27 0x548A8C + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_28 0x548A90 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_29 0x548A94 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_30 0x548A98 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_31 0x548A9C + +#define mmDMA2_QM_ARB_MST_CRED_INC 0x548AA0 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x548AA4 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x548AA8 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x548AAC + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x548AB0 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x548AB4 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x548AB8 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x548ABC + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x548AC0 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x548AC4 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x548AC8 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x548ACC + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x548AD0 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x548AD4 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x548AD8 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x548ADC + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x548AE0 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x548AE4 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x548AE8 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x548AEC + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x548AF0 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x548AF4 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x548AF8 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x548AFC + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x548B00 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x548B04 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x548B08 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x548B0C + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x548B10 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x548B14 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x548B18 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x548B1C + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x548B20 + +#define mmDMA2_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x548B28 + +#define mmDMA2_QM_ARB_MST_SLAVE_EN 0x548B2C + +#define mmDMA2_QM_ARB_MST_QUIET_PER 0x548B34 + +#define mmDMA2_QM_ARB_SLV_CHOISE_WDT 0x548B38 + +#define mmDMA2_QM_ARB_SLV_ID 0x548B3C + +#define mmDMA2_QM_ARB_MSG_MAX_INFLIGHT 0x548B44 + +#define mmDMA2_QM_ARB_MSG_AWUSER_31_11 0x548B48 + +#define mmDMA2_QM_ARB_MSG_AWUSER_SEC_PROP 0x548B4C + +#define mmDMA2_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x548B50 + +#define mmDMA2_QM_ARB_BASE_LO 0x548B54 + +#define mmDMA2_QM_ARB_BASE_HI 0x548B58 + +#define mmDMA2_QM_ARB_STATE_STS 0x548B80 + +#define mmDMA2_QM_ARB_CHOISE_FULLNESS_STS 0x548B84 + +#define mmDMA2_QM_ARB_MSG_STS 0x548B88 + +#define mmDMA2_QM_ARB_SLV_CHOISE_Q_HEAD 0x548B8C + +#define mmDMA2_QM_ARB_ERR_CAUSE 0x548B9C + +#define mmDMA2_QM_ARB_ERR_MSG_EN 0x548BA0 + +#define mmDMA2_QM_ARB_ERR_STS_DRP 0x548BA8 + +#define mmDMA2_QM_ARB_MST_CRED_STS_0 0x548BB0 + +#define mmDMA2_QM_ARB_MST_CRED_STS_1 0x548BB4 + +#define mmDMA2_QM_ARB_MST_CRED_STS_2 0x548BB8 + +#define mmDMA2_QM_ARB_MST_CRED_STS_3 0x548BBC + +#define mmDMA2_QM_ARB_MST_CRED_STS_4 0x548BC0 + +#define mmDMA2_QM_ARB_MST_CRED_STS_5 0x548BC4 + +#define mmDMA2_QM_ARB_MST_CRED_STS_6 0x548BC8 + +#define mmDMA2_QM_ARB_MST_CRED_STS_7 0x548BCC + +#define mmDMA2_QM_ARB_MST_CRED_STS_8 0x548BD0 + +#define mmDMA2_QM_ARB_MST_CRED_STS_9 0x548BD4 + +#define mmDMA2_QM_ARB_MST_CRED_STS_10 0x548BD8 + +#define mmDMA2_QM_ARB_MST_CRED_STS_11 0x548BDC + +#define mmDMA2_QM_ARB_MST_CRED_STS_12 0x548BE0 + +#define mmDMA2_QM_ARB_MST_CRED_STS_13 0x548BE4 + +#define mmDMA2_QM_ARB_MST_CRED_STS_14 0x548BE8 + +#define mmDMA2_QM_ARB_MST_CRED_STS_15 0x548BEC + +#define mmDMA2_QM_ARB_MST_CRED_STS_16 0x548BF0 + +#define mmDMA2_QM_ARB_MST_CRED_STS_17 0x548BF4 + +#define mmDMA2_QM_ARB_MST_CRED_STS_18 0x548BF8 + +#define mmDMA2_QM_ARB_MST_CRED_STS_19 0x548BFC + +#define mmDMA2_QM_ARB_MST_CRED_STS_20 0x548C00 + +#define mmDMA2_QM_ARB_MST_CRED_STS_21 0x548C04 + +#define mmDMA2_QM_ARB_MST_CRED_STS_22 0x548C08 + +#define mmDMA2_QM_ARB_MST_CRED_STS_23 0x548C0C + +#define mmDMA2_QM_ARB_MST_CRED_STS_24 0x548C10 + +#define mmDMA2_QM_ARB_MST_CRED_STS_25 0x548C14 + +#define mmDMA2_QM_ARB_MST_CRED_STS_26 0x548C18 + +#define mmDMA2_QM_ARB_MST_CRED_STS_27 0x548C1C + +#define mmDMA2_QM_ARB_MST_CRED_STS_28 0x548C20 + +#define mmDMA2_QM_ARB_MST_CRED_STS_29 0x548C24 + +#define mmDMA2_QM_ARB_MST_CRED_STS_30 0x548C28 + +#define mmDMA2_QM_ARB_MST_CRED_STS_31 0x548C2C + +#define mmDMA2_QM_CGM_CFG 0x548C70 + +#define mmDMA2_QM_CGM_STS 0x548C74 + +#define mmDMA2_QM_CGM_CFG1 0x548C78 + +#define mmDMA2_QM_LOCAL_RANGE_BASE 0x548C80 + +#define mmDMA2_QM_LOCAL_RANGE_SIZE 0x548C84 + +#define mmDMA2_QM_CSMR_STRICT_PRIO_CFG 0x548C90 + +#define mmDMA2_QM_HBW_RD_RATE_LIM_CFG_1 0x548C94 + +#define mmDMA2_QM_LBW_WR_RATE_LIM_CFG_0 0x548C98 + +#define mmDMA2_QM_LBW_WR_RATE_LIM_CFG_1 0x548C9C + +#define mmDMA2_QM_HBW_RD_RATE_LIM_CFG_0 0x548CA0 + +#define mmDMA2_QM_GLBL_AXCACHE 0x548CA4 + +#define mmDMA2_QM_IND_GW_APB_CFG 0x548CB0 + +#define mmDMA2_QM_IND_GW_APB_WDATA 0x548CB4 + +#define mmDMA2_QM_IND_GW_APB_RDATA 0x548CB8 + +#define mmDMA2_QM_IND_GW_APB_STATUS 0x548CBC + +#define mmDMA2_QM_GLBL_ERR_ADDR_LO 0x548CD0 + +#define mmDMA2_QM_GLBL_ERR_ADDR_HI 0x548CD4 + +#define mmDMA2_QM_GLBL_ERR_WDATA 0x548CD8 + +#define mmDMA2_QM_GLBL_MEM_INIT_BUSY 0x548D00 + +#endif /* ASIC_REG_DMA2_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma3_core_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma3_core_regs.h new file mode 100644 index 000000000000..fb145f416fe6 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma3_core_regs.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA3_CORE_REGS_H_ +#define ASIC_REG_DMA3_CORE_REGS_H_ + +/* + ***************************************** + * DMA3_CORE (Prototype: DMA_CORE) + ***************************************** + */ + +#define mmDMA3_CORE_CFG_0 0x560000 + +#define mmDMA3_CORE_CFG_1 0x560004 + +#define mmDMA3_CORE_LBW_MAX_OUTSTAND 0x560008 + +#define mmDMA3_CORE_SRC_BASE_LO 0x560014 + +#define mmDMA3_CORE_SRC_BASE_HI 0x560018 + +#define mmDMA3_CORE_DST_BASE_LO 0x56001C + +#define mmDMA3_CORE_DST_BASE_HI 0x560020 + +#define mmDMA3_CORE_SRC_TSIZE_1 0x56002C + +#define mmDMA3_CORE_SRC_STRIDE_1 0x560030 + +#define mmDMA3_CORE_SRC_TSIZE_2 0x560034 + +#define mmDMA3_CORE_SRC_STRIDE_2 0x560038 + +#define mmDMA3_CORE_SRC_TSIZE_3 0x56003C + +#define mmDMA3_CORE_SRC_STRIDE_3 0x560040 + +#define mmDMA3_CORE_SRC_TSIZE_4 0x560044 + +#define mmDMA3_CORE_SRC_STRIDE_4 0x560048 + +#define mmDMA3_CORE_SRC_TSIZE_0 0x56004C + +#define mmDMA3_CORE_DST_TSIZE_1 0x560054 + +#define mmDMA3_CORE_DST_STRIDE_1 0x560058 + +#define mmDMA3_CORE_DST_TSIZE_2 0x56005C + +#define mmDMA3_CORE_DST_STRIDE_2 0x560060 + +#define mmDMA3_CORE_DST_TSIZE_3 0x560064 + +#define mmDMA3_CORE_DST_STRIDE_3 0x560068 + +#define mmDMA3_CORE_DST_TSIZE_4 0x56006C + +#define mmDMA3_CORE_DST_STRIDE_4 0x560070 + +#define mmDMA3_CORE_DST_TSIZE_0 0x560074 + +#define mmDMA3_CORE_COMMIT 0x560078 + +#define mmDMA3_CORE_WR_COMP_WDATA 0x56007C + +#define mmDMA3_CORE_WR_COMP_ADDR_LO 0x560080 + +#define mmDMA3_CORE_WR_COMP_ADDR_HI 0x560084 + +#define mmDMA3_CORE_WR_COMP_AWUSER_31_11 0x560088 + +#define mmDMA3_CORE_TE_NUMROWS 0x560094 + +#define mmDMA3_CORE_PROT 0x5600B8 + +#define mmDMA3_CORE_SECURE_PROPS 0x5600F0 + +#define mmDMA3_CORE_NON_SECURE_PROPS 0x5600F4 + +#define mmDMA3_CORE_RD_MAX_OUTSTAND 0x560100 + +#define mmDMA3_CORE_RD_MAX_SIZE 0x560104 + +#define mmDMA3_CORE_RD_ARCACHE 0x560108 + +#define mmDMA3_CORE_RD_ARUSER_31_11 0x560110 + +#define mmDMA3_CORE_RD_INFLIGHTS 0x560114 + +#define mmDMA3_CORE_WR_MAX_OUTSTAND 0x560120 + +#define mmDMA3_CORE_WR_MAX_AWID 0x560124 + +#define mmDMA3_CORE_WR_AWCACHE 0x560128 + +#define mmDMA3_CORE_WR_AWUSER_31_11 0x560130 + +#define mmDMA3_CORE_WR_INFLIGHTS 0x560134 + +#define mmDMA3_CORE_RD_RATE_LIM_CFG_0 0x560150 + +#define mmDMA3_CORE_RD_RATE_LIM_CFG_1 0x560154 + +#define mmDMA3_CORE_WR_RATE_LIM_CFG_0 0x560158 + +#define mmDMA3_CORE_WR_RATE_LIM_CFG_1 0x56015C + +#define mmDMA3_CORE_ERR_CFG 0x560160 + +#define mmDMA3_CORE_ERR_CAUSE 0x560164 + +#define mmDMA3_CORE_ERRMSG_ADDR_LO 0x560170 + +#define mmDMA3_CORE_ERRMSG_ADDR_HI 0x560174 + +#define mmDMA3_CORE_ERRMSG_WDATA 0x560178 + +#define mmDMA3_CORE_STS0 0x560190 + +#define mmDMA3_CORE_STS1 0x560194 + +#define mmDMA3_CORE_RD_DBGMEM_ADD 0x560200 + +#define mmDMA3_CORE_RD_DBGMEM_DATA_WR 0x560204 + +#define mmDMA3_CORE_RD_DBGMEM_DATA_RD 0x560208 + +#define mmDMA3_CORE_RD_DBGMEM_CTRL 0x56020C + +#define mmDMA3_CORE_RD_DBGMEM_RC 0x560210 + +#define mmDMA3_CORE_DBG_HBW_AXI_AR_CNT 0x560220 + +#define mmDMA3_CORE_DBG_HBW_AXI_AW_CNT 0x560224 + +#define mmDMA3_CORE_DBG_LBW_AXI_AW_CNT 0x560228 + +#define mmDMA3_CORE_DBG_DESC_CNT 0x56022C + +#define mmDMA3_CORE_DBG_STS 0x560230 + +#define mmDMA3_CORE_DBG_RD_DESC_ID 0x560234 + +#define mmDMA3_CORE_DBG_WR_DESC_ID 0x560238 + +#endif /* ASIC_REG_DMA3_CORE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma3_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma3_qm_regs.h new file mode 100644 index 000000000000..a4b461ca3d94 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma3_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA3_QM_REGS_H_ +#define ASIC_REG_DMA3_QM_REGS_H_ + +/* + ***************************************** + * DMA3_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA3_QM_GLBL_CFG0 0x568000 + +#define mmDMA3_QM_GLBL_CFG1 0x568004 + +#define mmDMA3_QM_GLBL_PROT 0x568008 + +#define mmDMA3_QM_GLBL_ERR_CFG 0x56800C + +#define mmDMA3_QM_GLBL_SECURE_PROPS_0 0x568010 + +#define mmDMA3_QM_GLBL_SECURE_PROPS_1 0x568014 + +#define mmDMA3_QM_GLBL_SECURE_PROPS_2 0x568018 + +#define mmDMA3_QM_GLBL_SECURE_PROPS_3 0x56801C + +#define mmDMA3_QM_GLBL_SECURE_PROPS_4 0x568020 + +#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_0 0x568024 + +#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_1 0x568028 + +#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_2 0x56802C + +#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_3 0x568030 + +#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_4 0x568034 + +#define mmDMA3_QM_GLBL_STS0 0x568038 + +#define mmDMA3_QM_GLBL_STS1_0 0x568040 + +#define mmDMA3_QM_GLBL_STS1_1 0x568044 + +#define mmDMA3_QM_GLBL_STS1_2 0x568048 + +#define mmDMA3_QM_GLBL_STS1_3 0x56804C + +#define mmDMA3_QM_GLBL_STS1_4 0x568050 + +#define mmDMA3_QM_GLBL_MSG_EN_0 0x568054 + +#define mmDMA3_QM_GLBL_MSG_EN_1 0x568058 + +#define mmDMA3_QM_GLBL_MSG_EN_2 0x56805C + +#define mmDMA3_QM_GLBL_MSG_EN_3 0x568060 + +#define mmDMA3_QM_GLBL_MSG_EN_4 0x568068 + +#define mmDMA3_QM_PQ_BASE_LO_0 0x568070 + +#define mmDMA3_QM_PQ_BASE_LO_1 0x568074 + +#define mmDMA3_QM_PQ_BASE_LO_2 0x568078 + +#define mmDMA3_QM_PQ_BASE_LO_3 0x56807C + +#define mmDMA3_QM_PQ_BASE_HI_0 0x568080 + +#define mmDMA3_QM_PQ_BASE_HI_1 0x568084 + +#define mmDMA3_QM_PQ_BASE_HI_2 0x568088 + +#define mmDMA3_QM_PQ_BASE_HI_3 0x56808C + +#define mmDMA3_QM_PQ_SIZE_0 0x568090 + +#define mmDMA3_QM_PQ_SIZE_1 0x568094 + +#define mmDMA3_QM_PQ_SIZE_2 0x568098 + +#define mmDMA3_QM_PQ_SIZE_3 0x56809C + +#define mmDMA3_QM_PQ_PI_0 0x5680A0 + +#define mmDMA3_QM_PQ_PI_1 0x5680A4 + +#define mmDMA3_QM_PQ_PI_2 0x5680A8 + +#define mmDMA3_QM_PQ_PI_3 0x5680AC + +#define mmDMA3_QM_PQ_CI_0 0x5680B0 + +#define mmDMA3_QM_PQ_CI_1 0x5680B4 + +#define mmDMA3_QM_PQ_CI_2 0x5680B8 + +#define mmDMA3_QM_PQ_CI_3 0x5680BC + +#define mmDMA3_QM_PQ_CFG0_0 0x5680C0 + +#define mmDMA3_QM_PQ_CFG0_1 0x5680C4 + +#define mmDMA3_QM_PQ_CFG0_2 0x5680C8 + +#define mmDMA3_QM_PQ_CFG0_3 0x5680CC + +#define mmDMA3_QM_PQ_CFG1_0 0x5680D0 + +#define mmDMA3_QM_PQ_CFG1_1 0x5680D4 + +#define mmDMA3_QM_PQ_CFG1_2 0x5680D8 + +#define mmDMA3_QM_PQ_CFG1_3 0x5680DC + +#define mmDMA3_QM_PQ_ARUSER_31_11_0 0x5680E0 + +#define mmDMA3_QM_PQ_ARUSER_31_11_1 0x5680E4 + +#define mmDMA3_QM_PQ_ARUSER_31_11_2 0x5680E8 + +#define mmDMA3_QM_PQ_ARUSER_31_11_3 0x5680EC + +#define mmDMA3_QM_PQ_STS0_0 0x5680F0 + +#define mmDMA3_QM_PQ_STS0_1 0x5680F4 + +#define mmDMA3_QM_PQ_STS0_2 0x5680F8 + +#define mmDMA3_QM_PQ_STS0_3 0x5680FC + +#define mmDMA3_QM_PQ_STS1_0 0x568100 + +#define mmDMA3_QM_PQ_STS1_1 0x568104 + +#define mmDMA3_QM_PQ_STS1_2 0x568108 + +#define mmDMA3_QM_PQ_STS1_3 0x56810C + +#define mmDMA3_QM_CQ_CFG0_0 0x568110 + +#define mmDMA3_QM_CQ_CFG0_1 0x568114 + +#define mmDMA3_QM_CQ_CFG0_2 0x568118 + +#define mmDMA3_QM_CQ_CFG0_3 0x56811C + +#define mmDMA3_QM_CQ_CFG0_4 0x568120 + +#define mmDMA3_QM_CQ_CFG1_0 0x568124 + +#define mmDMA3_QM_CQ_CFG1_1 0x568128 + +#define mmDMA3_QM_CQ_CFG1_2 0x56812C + +#define mmDMA3_QM_CQ_CFG1_3 0x568130 + +#define mmDMA3_QM_CQ_CFG1_4 0x568134 + +#define mmDMA3_QM_CQ_ARUSER_31_11_0 0x568138 + +#define mmDMA3_QM_CQ_ARUSER_31_11_1 0x56813C + +#define mmDMA3_QM_CQ_ARUSER_31_11_2 0x568140 + +#define mmDMA3_QM_CQ_ARUSER_31_11_3 0x568144 + +#define mmDMA3_QM_CQ_ARUSER_31_11_4 0x568148 + +#define mmDMA3_QM_CQ_STS0_0 0x56814C + +#define mmDMA3_QM_CQ_STS0_1 0x568150 + +#define mmDMA3_QM_CQ_STS0_2 0x568154 + +#define mmDMA3_QM_CQ_STS0_3 0x568158 + +#define mmDMA3_QM_CQ_STS0_4 0x56815C + +#define mmDMA3_QM_CQ_STS1_0 0x568160 + +#define mmDMA3_QM_CQ_STS1_1 0x568164 + +#define mmDMA3_QM_CQ_STS1_2 0x568168 + +#define mmDMA3_QM_CQ_STS1_3 0x56816C + +#define mmDMA3_QM_CQ_STS1_4 0x568170 + +#define mmDMA3_QM_CQ_PTR_LO_0 0x568174 + +#define mmDMA3_QM_CQ_PTR_HI_0 0x568178 + +#define mmDMA3_QM_CQ_TSIZE_0 0x56817C + +#define mmDMA3_QM_CQ_CTL_0 0x568180 + +#define mmDMA3_QM_CQ_PTR_LO_1 0x568184 + +#define mmDMA3_QM_CQ_PTR_HI_1 0x568188 + +#define mmDMA3_QM_CQ_TSIZE_1 0x56818C + +#define mmDMA3_QM_CQ_CTL_1 0x568190 + +#define mmDMA3_QM_CQ_PTR_LO_2 0x568194 + +#define mmDMA3_QM_CQ_PTR_HI_2 0x568198 + +#define mmDMA3_QM_CQ_TSIZE_2 0x56819C + +#define mmDMA3_QM_CQ_CTL_2 0x5681A0 + +#define mmDMA3_QM_CQ_PTR_LO_3 0x5681A4 + +#define mmDMA3_QM_CQ_PTR_HI_3 0x5681A8 + +#define mmDMA3_QM_CQ_TSIZE_3 0x5681AC + +#define mmDMA3_QM_CQ_CTL_3 0x5681B0 + +#define mmDMA3_QM_CQ_PTR_LO_4 0x5681B4 + +#define mmDMA3_QM_CQ_PTR_HI_4 0x5681B8 + +#define mmDMA3_QM_CQ_TSIZE_4 0x5681BC + +#define mmDMA3_QM_CQ_CTL_4 0x5681C0 + +#define mmDMA3_QM_CQ_PTR_LO_STS_0 0x5681C4 + +#define mmDMA3_QM_CQ_PTR_LO_STS_1 0x5681C8 + +#define mmDMA3_QM_CQ_PTR_LO_STS_2 0x5681CC + +#define mmDMA3_QM_CQ_PTR_LO_STS_3 0x5681D0 + +#define mmDMA3_QM_CQ_PTR_LO_STS_4 0x5681D4 + +#define mmDMA3_QM_CQ_PTR_HI_STS_0 0x5681D8 + +#define mmDMA3_QM_CQ_PTR_HI_STS_1 0x5681DC + +#define mmDMA3_QM_CQ_PTR_HI_STS_2 0x5681E0 + +#define mmDMA3_QM_CQ_PTR_HI_STS_3 0x5681E4 + +#define mmDMA3_QM_CQ_PTR_HI_STS_4 0x5681E8 + +#define mmDMA3_QM_CQ_TSIZE_STS_0 0x5681EC + +#define mmDMA3_QM_CQ_TSIZE_STS_1 0x5681F0 + +#define mmDMA3_QM_CQ_TSIZE_STS_2 0x5681F4 + +#define mmDMA3_QM_CQ_TSIZE_STS_3 0x5681F8 + +#define mmDMA3_QM_CQ_TSIZE_STS_4 0x5681FC + +#define mmDMA3_QM_CQ_CTL_STS_0 0x568200 + +#define mmDMA3_QM_CQ_CTL_STS_1 0x568204 + +#define mmDMA3_QM_CQ_CTL_STS_2 0x568208 + +#define mmDMA3_QM_CQ_CTL_STS_3 0x56820C + +#define mmDMA3_QM_CQ_CTL_STS_4 0x568210 + +#define mmDMA3_QM_CQ_IFIFO_CNT_0 0x568214 + +#define mmDMA3_QM_CQ_IFIFO_CNT_1 0x568218 + +#define mmDMA3_QM_CQ_IFIFO_CNT_2 0x56821C + +#define mmDMA3_QM_CQ_IFIFO_CNT_3 0x568220 + +#define mmDMA3_QM_CQ_IFIFO_CNT_4 0x568224 + +#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_0 0x568228 + +#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_1 0x56822C + +#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_2 0x568230 + +#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_3 0x568234 + +#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_4 0x568238 + +#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_0 0x56823C + +#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_1 0x568240 + +#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_2 0x568244 + +#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_3 0x568248 + +#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_4 0x56824C + +#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_0 0x568250 + +#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_1 0x568254 + +#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_2 0x568258 + +#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_3 0x56825C + +#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_4 0x568260 + +#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_0 0x568264 + +#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_1 0x568268 + +#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_2 0x56826C + +#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_3 0x568270 + +#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_4 0x568274 + +#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_0 0x568278 + +#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_1 0x56827C + +#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_2 0x568280 + +#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_3 0x568284 + +#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_4 0x568288 + +#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_0 0x56828C + +#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_1 0x568290 + +#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_2 0x568294 + +#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_3 0x568298 + +#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_4 0x56829C + +#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_0 0x5682A0 + +#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_1 0x5682A4 + +#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_2 0x5682A8 + +#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_3 0x5682AC + +#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_4 0x5682B0 + +#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_0 0x5682B4 + +#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_1 0x5682B8 + +#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_2 0x5682BC + +#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_3 0x5682C0 + +#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_4 0x5682C4 + +#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_0 0x5682C8 + +#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_1 0x5682CC + +#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_2 0x5682D0 + +#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_3 0x5682D4 + +#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_4 0x5682D8 + +#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5682E0 + +#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5682E4 + +#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5682E8 + +#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5682EC + +#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5682F0 + +#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5682F4 + +#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5682F8 + +#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5682FC + +#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x568300 + +#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x568304 + +#define mmDMA3_QM_CP_FENCE0_RDATA_0 0x568308 + +#define mmDMA3_QM_CP_FENCE0_RDATA_1 0x56830C + +#define mmDMA3_QM_CP_FENCE0_RDATA_2 0x568310 + +#define mmDMA3_QM_CP_FENCE0_RDATA_3 0x568314 + +#define mmDMA3_QM_CP_FENCE0_RDATA_4 0x568318 + +#define mmDMA3_QM_CP_FENCE1_RDATA_0 0x56831C + +#define mmDMA3_QM_CP_FENCE1_RDATA_1 0x568320 + +#define mmDMA3_QM_CP_FENCE1_RDATA_2 0x568324 + +#define mmDMA3_QM_CP_FENCE1_RDATA_3 0x568328 + +#define mmDMA3_QM_CP_FENCE1_RDATA_4 0x56832C + +#define mmDMA3_QM_CP_FENCE2_RDATA_0 0x568330 + +#define mmDMA3_QM_CP_FENCE2_RDATA_1 0x568334 + +#define mmDMA3_QM_CP_FENCE2_RDATA_2 0x568338 + +#define mmDMA3_QM_CP_FENCE2_RDATA_3 0x56833C + +#define mmDMA3_QM_CP_FENCE2_RDATA_4 0x568340 + +#define mmDMA3_QM_CP_FENCE3_RDATA_0 0x568344 + +#define mmDMA3_QM_CP_FENCE3_RDATA_1 0x568348 + +#define mmDMA3_QM_CP_FENCE3_RDATA_2 0x56834C + +#define mmDMA3_QM_CP_FENCE3_RDATA_3 0x568350 + +#define mmDMA3_QM_CP_FENCE3_RDATA_4 0x568354 + +#define mmDMA3_QM_CP_FENCE0_CNT_0 0x568358 + +#define mmDMA3_QM_CP_FENCE0_CNT_1 0x56835C + +#define mmDMA3_QM_CP_FENCE0_CNT_2 0x568360 + +#define mmDMA3_QM_CP_FENCE0_CNT_3 0x568364 + +#define mmDMA3_QM_CP_FENCE0_CNT_4 0x568368 + +#define mmDMA3_QM_CP_FENCE1_CNT_0 0x56836C + +#define mmDMA3_QM_CP_FENCE1_CNT_1 0x568370 + +#define mmDMA3_QM_CP_FENCE1_CNT_2 0x568374 + +#define mmDMA3_QM_CP_FENCE1_CNT_3 0x568378 + +#define mmDMA3_QM_CP_FENCE1_CNT_4 0x56837C + +#define mmDMA3_QM_CP_FENCE2_CNT_0 0x568380 + +#define mmDMA3_QM_CP_FENCE2_CNT_1 0x568384 + +#define mmDMA3_QM_CP_FENCE2_CNT_2 0x568388 + +#define mmDMA3_QM_CP_FENCE2_CNT_3 0x56838C + +#define mmDMA3_QM_CP_FENCE2_CNT_4 0x568390 + +#define mmDMA3_QM_CP_FENCE3_CNT_0 0x568394 + +#define mmDMA3_QM_CP_FENCE3_CNT_1 0x568398 + +#define mmDMA3_QM_CP_FENCE3_CNT_2 0x56839C + +#define mmDMA3_QM_CP_FENCE3_CNT_3 0x5683A0 + +#define mmDMA3_QM_CP_FENCE3_CNT_4 0x5683A4 + +#define mmDMA3_QM_CP_STS_0 0x5683A8 + +#define mmDMA3_QM_CP_STS_1 0x5683AC + +#define mmDMA3_QM_CP_STS_2 0x5683B0 + +#define mmDMA3_QM_CP_STS_3 0x5683B4 + +#define mmDMA3_QM_CP_STS_4 0x5683B8 + +#define mmDMA3_QM_CP_CURRENT_INST_LO_0 0x5683BC + +#define mmDMA3_QM_CP_CURRENT_INST_LO_1 0x5683C0 + +#define mmDMA3_QM_CP_CURRENT_INST_LO_2 0x5683C4 + +#define mmDMA3_QM_CP_CURRENT_INST_LO_3 0x5683C8 + +#define mmDMA3_QM_CP_CURRENT_INST_LO_4 0x5683CC + +#define mmDMA3_QM_CP_CURRENT_INST_HI_0 0x5683D0 + +#define mmDMA3_QM_CP_CURRENT_INST_HI_1 0x5683D4 + +#define mmDMA3_QM_CP_CURRENT_INST_HI_2 0x5683D8 + +#define mmDMA3_QM_CP_CURRENT_INST_HI_3 0x5683DC + +#define mmDMA3_QM_CP_CURRENT_INST_HI_4 0x5683E0 + +#define mmDMA3_QM_CP_BARRIER_CFG_0 0x5683F4 + +#define mmDMA3_QM_CP_BARRIER_CFG_1 0x5683F8 + +#define mmDMA3_QM_CP_BARRIER_CFG_2 0x5683FC + +#define mmDMA3_QM_CP_BARRIER_CFG_3 0x568400 + +#define mmDMA3_QM_CP_BARRIER_CFG_4 0x568404 + +#define mmDMA3_QM_CP_DBG_0_0 0x568408 + +#define mmDMA3_QM_CP_DBG_0_1 0x56840C + +#define mmDMA3_QM_CP_DBG_0_2 0x568410 + +#define mmDMA3_QM_CP_DBG_0_3 0x568414 + +#define mmDMA3_QM_CP_DBG_0_4 0x568418 + +#define mmDMA3_QM_CP_ARUSER_31_11_0 0x56841C + +#define mmDMA3_QM_CP_ARUSER_31_11_1 0x568420 + +#define mmDMA3_QM_CP_ARUSER_31_11_2 0x568424 + +#define mmDMA3_QM_CP_ARUSER_31_11_3 0x568428 + +#define mmDMA3_QM_CP_ARUSER_31_11_4 0x56842C + +#define mmDMA3_QM_CP_AWUSER_31_11_0 0x568430 + +#define mmDMA3_QM_CP_AWUSER_31_11_1 0x568434 + +#define mmDMA3_QM_CP_AWUSER_31_11_2 0x568438 + +#define mmDMA3_QM_CP_AWUSER_31_11_3 0x56843C + +#define mmDMA3_QM_CP_AWUSER_31_11_4 0x568440 + +#define mmDMA3_QM_ARB_CFG_0 0x568A00 + +#define mmDMA3_QM_ARB_CHOISE_Q_PUSH 0x568A04 + +#define mmDMA3_QM_ARB_WRR_WEIGHT_0 0x568A08 + +#define mmDMA3_QM_ARB_WRR_WEIGHT_1 0x568A0C + +#define mmDMA3_QM_ARB_WRR_WEIGHT_2 0x568A10 + +#define mmDMA3_QM_ARB_WRR_WEIGHT_3 0x568A14 + +#define mmDMA3_QM_ARB_CFG_1 0x568A18 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_0 0x568A20 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_1 0x568A24 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_2 0x568A28 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_3 0x568A2C + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_4 0x568A30 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_5 0x568A34 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_6 0x568A38 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_7 0x568A3C + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_8 0x568A40 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_9 0x568A44 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_10 0x568A48 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_11 0x568A4C + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_12 0x568A50 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_13 0x568A54 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_14 0x568A58 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_15 0x568A5C + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_16 0x568A60 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_17 0x568A64 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_18 0x568A68 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_19 0x568A6C + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_20 0x568A70 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_21 0x568A74 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_22 0x568A78 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_23 0x568A7C + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_24 0x568A80 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_25 0x568A84 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_26 0x568A88 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_27 0x568A8C + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_28 0x568A90 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_29 0x568A94 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_30 0x568A98 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_31 0x568A9C + +#define mmDMA3_QM_ARB_MST_CRED_INC 0x568AA0 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x568AA4 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x568AA8 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x568AAC + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x568AB0 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x568AB4 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x568AB8 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x568ABC + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x568AC0 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x568AC4 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x568AC8 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x568ACC + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x568AD0 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x568AD4 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x568AD8 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x568ADC + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x568AE0 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x568AE4 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x568AE8 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x568AEC + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x568AF0 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x568AF4 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x568AF8 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x568AFC + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x568B00 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x568B04 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x568B08 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x568B0C + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x568B10 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x568B14 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x568B18 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x568B1C + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x568B20 + +#define mmDMA3_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x568B28 + +#define mmDMA3_QM_ARB_MST_SLAVE_EN 0x568B2C + +#define mmDMA3_QM_ARB_MST_QUIET_PER 0x568B34 + +#define mmDMA3_QM_ARB_SLV_CHOISE_WDT 0x568B38 + +#define mmDMA3_QM_ARB_SLV_ID 0x568B3C + +#define mmDMA3_QM_ARB_MSG_MAX_INFLIGHT 0x568B44 + +#define mmDMA3_QM_ARB_MSG_AWUSER_31_11 0x568B48 + +#define mmDMA3_QM_ARB_MSG_AWUSER_SEC_PROP 0x568B4C + +#define mmDMA3_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x568B50 + +#define mmDMA3_QM_ARB_BASE_LO 0x568B54 + +#define mmDMA3_QM_ARB_BASE_HI 0x568B58 + +#define mmDMA3_QM_ARB_STATE_STS 0x568B80 + +#define mmDMA3_QM_ARB_CHOISE_FULLNESS_STS 0x568B84 + +#define mmDMA3_QM_ARB_MSG_STS 0x568B88 + +#define mmDMA3_QM_ARB_SLV_CHOISE_Q_HEAD 0x568B8C + +#define mmDMA3_QM_ARB_ERR_CAUSE 0x568B9C + +#define mmDMA3_QM_ARB_ERR_MSG_EN 0x568BA0 + +#define mmDMA3_QM_ARB_ERR_STS_DRP 0x568BA8 + +#define mmDMA3_QM_ARB_MST_CRED_STS_0 0x568BB0 + +#define mmDMA3_QM_ARB_MST_CRED_STS_1 0x568BB4 + +#define mmDMA3_QM_ARB_MST_CRED_STS_2 0x568BB8 + +#define mmDMA3_QM_ARB_MST_CRED_STS_3 0x568BBC + +#define mmDMA3_QM_ARB_MST_CRED_STS_4 0x568BC0 + +#define mmDMA3_QM_ARB_MST_CRED_STS_5 0x568BC4 + +#define mmDMA3_QM_ARB_MST_CRED_STS_6 0x568BC8 + +#define mmDMA3_QM_ARB_MST_CRED_STS_7 0x568BCC + +#define mmDMA3_QM_ARB_MST_CRED_STS_8 0x568BD0 + +#define mmDMA3_QM_ARB_MST_CRED_STS_9 0x568BD4 + +#define mmDMA3_QM_ARB_MST_CRED_STS_10 0x568BD8 + +#define mmDMA3_QM_ARB_MST_CRED_STS_11 0x568BDC + +#define mmDMA3_QM_ARB_MST_CRED_STS_12 0x568BE0 + +#define mmDMA3_QM_ARB_MST_CRED_STS_13 0x568BE4 + +#define mmDMA3_QM_ARB_MST_CRED_STS_14 0x568BE8 + +#define mmDMA3_QM_ARB_MST_CRED_STS_15 0x568BEC + +#define mmDMA3_QM_ARB_MST_CRED_STS_16 0x568BF0 + +#define mmDMA3_QM_ARB_MST_CRED_STS_17 0x568BF4 + +#define mmDMA3_QM_ARB_MST_CRED_STS_18 0x568BF8 + +#define mmDMA3_QM_ARB_MST_CRED_STS_19 0x568BFC + +#define mmDMA3_QM_ARB_MST_CRED_STS_20 0x568C00 + +#define mmDMA3_QM_ARB_MST_CRED_STS_21 0x568C04 + +#define mmDMA3_QM_ARB_MST_CRED_STS_22 0x568C08 + +#define mmDMA3_QM_ARB_MST_CRED_STS_23 0x568C0C + +#define mmDMA3_QM_ARB_MST_CRED_STS_24 0x568C10 + +#define mmDMA3_QM_ARB_MST_CRED_STS_25 0x568C14 + +#define mmDMA3_QM_ARB_MST_CRED_STS_26 0x568C18 + +#define mmDMA3_QM_ARB_MST_CRED_STS_27 0x568C1C + +#define mmDMA3_QM_ARB_MST_CRED_STS_28 0x568C20 + +#define mmDMA3_QM_ARB_MST_CRED_STS_29 0x568C24 + +#define mmDMA3_QM_ARB_MST_CRED_STS_30 0x568C28 + +#define mmDMA3_QM_ARB_MST_CRED_STS_31 0x568C2C + +#define mmDMA3_QM_CGM_CFG 0x568C70 + +#define mmDMA3_QM_CGM_STS 0x568C74 + +#define mmDMA3_QM_CGM_CFG1 0x568C78 + +#define mmDMA3_QM_LOCAL_RANGE_BASE 0x568C80 + +#define mmDMA3_QM_LOCAL_RANGE_SIZE 0x568C84 + +#define mmDMA3_QM_CSMR_STRICT_PRIO_CFG 0x568C90 + +#define mmDMA3_QM_HBW_RD_RATE_LIM_CFG_1 0x568C94 + +#define mmDMA3_QM_LBW_WR_RATE_LIM_CFG_0 0x568C98 + +#define mmDMA3_QM_LBW_WR_RATE_LIM_CFG_1 0x568C9C + +#define mmDMA3_QM_HBW_RD_RATE_LIM_CFG_0 0x568CA0 + +#define mmDMA3_QM_GLBL_AXCACHE 0x568CA4 + +#define mmDMA3_QM_IND_GW_APB_CFG 0x568CB0 + +#define mmDMA3_QM_IND_GW_APB_WDATA 0x568CB4 + +#define mmDMA3_QM_IND_GW_APB_RDATA 0x568CB8 + +#define mmDMA3_QM_IND_GW_APB_STATUS 0x568CBC + +#define mmDMA3_QM_GLBL_ERR_ADDR_LO 0x568CD0 + +#define mmDMA3_QM_GLBL_ERR_ADDR_HI 0x568CD4 + +#define mmDMA3_QM_GLBL_ERR_WDATA 0x568CD8 + +#define mmDMA3_QM_GLBL_MEM_INIT_BUSY 0x568D00 + +#endif /* ASIC_REG_DMA3_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma4_core_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma4_core_regs.h new file mode 100644 index 000000000000..192d11404b1c --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma4_core_regs.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA4_CORE_REGS_H_ +#define ASIC_REG_DMA4_CORE_REGS_H_ + +/* + ***************************************** + * DMA4_CORE (Prototype: DMA_CORE) + ***************************************** + */ + +#define mmDMA4_CORE_CFG_0 0x580000 + +#define mmDMA4_CORE_CFG_1 0x580004 + +#define mmDMA4_CORE_LBW_MAX_OUTSTAND 0x580008 + +#define mmDMA4_CORE_SRC_BASE_LO 0x580014 + +#define mmDMA4_CORE_SRC_BASE_HI 0x580018 + +#define mmDMA4_CORE_DST_BASE_LO 0x58001C + +#define mmDMA4_CORE_DST_BASE_HI 0x580020 + +#define mmDMA4_CORE_SRC_TSIZE_1 0x58002C + +#define mmDMA4_CORE_SRC_STRIDE_1 0x580030 + +#define mmDMA4_CORE_SRC_TSIZE_2 0x580034 + +#define mmDMA4_CORE_SRC_STRIDE_2 0x580038 + +#define mmDMA4_CORE_SRC_TSIZE_3 0x58003C + +#define mmDMA4_CORE_SRC_STRIDE_3 0x580040 + +#define mmDMA4_CORE_SRC_TSIZE_4 0x580044 + +#define mmDMA4_CORE_SRC_STRIDE_4 0x580048 + +#define mmDMA4_CORE_SRC_TSIZE_0 0x58004C + +#define mmDMA4_CORE_DST_TSIZE_1 0x580054 + +#define mmDMA4_CORE_DST_STRIDE_1 0x580058 + +#define mmDMA4_CORE_DST_TSIZE_2 0x58005C + +#define mmDMA4_CORE_DST_STRIDE_2 0x580060 + +#define mmDMA4_CORE_DST_TSIZE_3 0x580064 + +#define mmDMA4_CORE_DST_STRIDE_3 0x580068 + +#define mmDMA4_CORE_DST_TSIZE_4 0x58006C + +#define mmDMA4_CORE_DST_STRIDE_4 0x580070 + +#define mmDMA4_CORE_DST_TSIZE_0 0x580074 + +#define mmDMA4_CORE_COMMIT 0x580078 + +#define mmDMA4_CORE_WR_COMP_WDATA 0x58007C + +#define mmDMA4_CORE_WR_COMP_ADDR_LO 0x580080 + +#define mmDMA4_CORE_WR_COMP_ADDR_HI 0x580084 + +#define mmDMA4_CORE_WR_COMP_AWUSER_31_11 0x580088 + +#define mmDMA4_CORE_TE_NUMROWS 0x580094 + +#define mmDMA4_CORE_PROT 0x5800B8 + +#define mmDMA4_CORE_SECURE_PROPS 0x5800F0 + +#define mmDMA4_CORE_NON_SECURE_PROPS 0x5800F4 + +#define mmDMA4_CORE_RD_MAX_OUTSTAND 0x580100 + +#define mmDMA4_CORE_RD_MAX_SIZE 0x580104 + +#define mmDMA4_CORE_RD_ARCACHE 0x580108 + +#define mmDMA4_CORE_RD_ARUSER_31_11 0x580110 + +#define mmDMA4_CORE_RD_INFLIGHTS 0x580114 + +#define mmDMA4_CORE_WR_MAX_OUTSTAND 0x580120 + +#define mmDMA4_CORE_WR_MAX_AWID 0x580124 + +#define mmDMA4_CORE_WR_AWCACHE 0x580128 + +#define mmDMA4_CORE_WR_AWUSER_31_11 0x580130 + +#define mmDMA4_CORE_WR_INFLIGHTS 0x580134 + +#define mmDMA4_CORE_RD_RATE_LIM_CFG_0 0x580150 + +#define mmDMA4_CORE_RD_RATE_LIM_CFG_1 0x580154 + +#define mmDMA4_CORE_WR_RATE_LIM_CFG_0 0x580158 + +#define mmDMA4_CORE_WR_RATE_LIM_CFG_1 0x58015C + +#define mmDMA4_CORE_ERR_CFG 0x580160 + +#define mmDMA4_CORE_ERR_CAUSE 0x580164 + +#define mmDMA4_CORE_ERRMSG_ADDR_LO 0x580170 + +#define mmDMA4_CORE_ERRMSG_ADDR_HI 0x580174 + +#define mmDMA4_CORE_ERRMSG_WDATA 0x580178 + +#define mmDMA4_CORE_STS0 0x580190 + +#define mmDMA4_CORE_STS1 0x580194 + +#define mmDMA4_CORE_RD_DBGMEM_ADD 0x580200 + +#define mmDMA4_CORE_RD_DBGMEM_DATA_WR 0x580204 + +#define mmDMA4_CORE_RD_DBGMEM_DATA_RD 0x580208 + +#define mmDMA4_CORE_RD_DBGMEM_CTRL 0x58020C + +#define mmDMA4_CORE_RD_DBGMEM_RC 0x580210 + +#define mmDMA4_CORE_DBG_HBW_AXI_AR_CNT 0x580220 + +#define mmDMA4_CORE_DBG_HBW_AXI_AW_CNT 0x580224 + +#define mmDMA4_CORE_DBG_LBW_AXI_AW_CNT 0x580228 + +#define mmDMA4_CORE_DBG_DESC_CNT 0x58022C + +#define mmDMA4_CORE_DBG_STS 0x580230 + +#define mmDMA4_CORE_DBG_RD_DESC_ID 0x580234 + +#define mmDMA4_CORE_DBG_WR_DESC_ID 0x580238 + +#endif /* ASIC_REG_DMA4_CORE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma4_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma4_qm_regs.h new file mode 100644 index 000000000000..f0cbda0d1e4d --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma4_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA4_QM_REGS_H_ +#define ASIC_REG_DMA4_QM_REGS_H_ + +/* + ***************************************** + * DMA4_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA4_QM_GLBL_CFG0 0x588000 + +#define mmDMA4_QM_GLBL_CFG1 0x588004 + +#define mmDMA4_QM_GLBL_PROT 0x588008 + +#define mmDMA4_QM_GLBL_ERR_CFG 0x58800C + +#define mmDMA4_QM_GLBL_SECURE_PROPS_0 0x588010 + +#define mmDMA4_QM_GLBL_SECURE_PROPS_1 0x588014 + +#define mmDMA4_QM_GLBL_SECURE_PROPS_2 0x588018 + +#define mmDMA4_QM_GLBL_SECURE_PROPS_3 0x58801C + +#define mmDMA4_QM_GLBL_SECURE_PROPS_4 0x588020 + +#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_0 0x588024 + +#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_1 0x588028 + +#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_2 0x58802C + +#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_3 0x588030 + +#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_4 0x588034 + +#define mmDMA4_QM_GLBL_STS0 0x588038 + +#define mmDMA4_QM_GLBL_STS1_0 0x588040 + +#define mmDMA4_QM_GLBL_STS1_1 0x588044 + +#define mmDMA4_QM_GLBL_STS1_2 0x588048 + +#define mmDMA4_QM_GLBL_STS1_3 0x58804C + +#define mmDMA4_QM_GLBL_STS1_4 0x588050 + +#define mmDMA4_QM_GLBL_MSG_EN_0 0x588054 + +#define mmDMA4_QM_GLBL_MSG_EN_1 0x588058 + +#define mmDMA4_QM_GLBL_MSG_EN_2 0x58805C + +#define mmDMA4_QM_GLBL_MSG_EN_3 0x588060 + +#define mmDMA4_QM_GLBL_MSG_EN_4 0x588068 + +#define mmDMA4_QM_PQ_BASE_LO_0 0x588070 + +#define mmDMA4_QM_PQ_BASE_LO_1 0x588074 + +#define mmDMA4_QM_PQ_BASE_LO_2 0x588078 + +#define mmDMA4_QM_PQ_BASE_LO_3 0x58807C + +#define mmDMA4_QM_PQ_BASE_HI_0 0x588080 + +#define mmDMA4_QM_PQ_BASE_HI_1 0x588084 + +#define mmDMA4_QM_PQ_BASE_HI_2 0x588088 + +#define mmDMA4_QM_PQ_BASE_HI_3 0x58808C + +#define mmDMA4_QM_PQ_SIZE_0 0x588090 + +#define mmDMA4_QM_PQ_SIZE_1 0x588094 + +#define mmDMA4_QM_PQ_SIZE_2 0x588098 + +#define mmDMA4_QM_PQ_SIZE_3 0x58809C + +#define mmDMA4_QM_PQ_PI_0 0x5880A0 + +#define mmDMA4_QM_PQ_PI_1 0x5880A4 + +#define mmDMA4_QM_PQ_PI_2 0x5880A8 + +#define mmDMA4_QM_PQ_PI_3 0x5880AC + +#define mmDMA4_QM_PQ_CI_0 0x5880B0 + +#define mmDMA4_QM_PQ_CI_1 0x5880B4 + +#define mmDMA4_QM_PQ_CI_2 0x5880B8 + +#define mmDMA4_QM_PQ_CI_3 0x5880BC + +#define mmDMA4_QM_PQ_CFG0_0 0x5880C0 + +#define mmDMA4_QM_PQ_CFG0_1 0x5880C4 + +#define mmDMA4_QM_PQ_CFG0_2 0x5880C8 + +#define mmDMA4_QM_PQ_CFG0_3 0x5880CC + +#define mmDMA4_QM_PQ_CFG1_0 0x5880D0 + +#define mmDMA4_QM_PQ_CFG1_1 0x5880D4 + +#define mmDMA4_QM_PQ_CFG1_2 0x5880D8 + +#define mmDMA4_QM_PQ_CFG1_3 0x5880DC + +#define mmDMA4_QM_PQ_ARUSER_31_11_0 0x5880E0 + +#define mmDMA4_QM_PQ_ARUSER_31_11_1 0x5880E4 + +#define mmDMA4_QM_PQ_ARUSER_31_11_2 0x5880E8 + +#define mmDMA4_QM_PQ_ARUSER_31_11_3 0x5880EC + +#define mmDMA4_QM_PQ_STS0_0 0x5880F0 + +#define mmDMA4_QM_PQ_STS0_1 0x5880F4 + +#define mmDMA4_QM_PQ_STS0_2 0x5880F8 + +#define mmDMA4_QM_PQ_STS0_3 0x5880FC + +#define mmDMA4_QM_PQ_STS1_0 0x588100 + +#define mmDMA4_QM_PQ_STS1_1 0x588104 + +#define mmDMA4_QM_PQ_STS1_2 0x588108 + +#define mmDMA4_QM_PQ_STS1_3 0x58810C + +#define mmDMA4_QM_CQ_CFG0_0 0x588110 + +#define mmDMA4_QM_CQ_CFG0_1 0x588114 + +#define mmDMA4_QM_CQ_CFG0_2 0x588118 + +#define mmDMA4_QM_CQ_CFG0_3 0x58811C + +#define mmDMA4_QM_CQ_CFG0_4 0x588120 + +#define mmDMA4_QM_CQ_CFG1_0 0x588124 + +#define mmDMA4_QM_CQ_CFG1_1 0x588128 + +#define mmDMA4_QM_CQ_CFG1_2 0x58812C + +#define mmDMA4_QM_CQ_CFG1_3 0x588130 + +#define mmDMA4_QM_CQ_CFG1_4 0x588134 + +#define mmDMA4_QM_CQ_ARUSER_31_11_0 0x588138 + +#define mmDMA4_QM_CQ_ARUSER_31_11_1 0x58813C + +#define mmDMA4_QM_CQ_ARUSER_31_11_2 0x588140 + +#define mmDMA4_QM_CQ_ARUSER_31_11_3 0x588144 + +#define mmDMA4_QM_CQ_ARUSER_31_11_4 0x588148 + +#define mmDMA4_QM_CQ_STS0_0 0x58814C + +#define mmDMA4_QM_CQ_STS0_1 0x588150 + +#define mmDMA4_QM_CQ_STS0_2 0x588154 + +#define mmDMA4_QM_CQ_STS0_3 0x588158 + +#define mmDMA4_QM_CQ_STS0_4 0x58815C + +#define mmDMA4_QM_CQ_STS1_0 0x588160 + +#define mmDMA4_QM_CQ_STS1_1 0x588164 + +#define mmDMA4_QM_CQ_STS1_2 0x588168 + +#define mmDMA4_QM_CQ_STS1_3 0x58816C + +#define mmDMA4_QM_CQ_STS1_4 0x588170 + +#define mmDMA4_QM_CQ_PTR_LO_0 0x588174 + +#define mmDMA4_QM_CQ_PTR_HI_0 0x588178 + +#define mmDMA4_QM_CQ_TSIZE_0 0x58817C + +#define mmDMA4_QM_CQ_CTL_0 0x588180 + +#define mmDMA4_QM_CQ_PTR_LO_1 0x588184 + +#define mmDMA4_QM_CQ_PTR_HI_1 0x588188 + +#define mmDMA4_QM_CQ_TSIZE_1 0x58818C + +#define mmDMA4_QM_CQ_CTL_1 0x588190 + +#define mmDMA4_QM_CQ_PTR_LO_2 0x588194 + +#define mmDMA4_QM_CQ_PTR_HI_2 0x588198 + +#define mmDMA4_QM_CQ_TSIZE_2 0x58819C + +#define mmDMA4_QM_CQ_CTL_2 0x5881A0 + +#define mmDMA4_QM_CQ_PTR_LO_3 0x5881A4 + +#define mmDMA4_QM_CQ_PTR_HI_3 0x5881A8 + +#define mmDMA4_QM_CQ_TSIZE_3 0x5881AC + +#define mmDMA4_QM_CQ_CTL_3 0x5881B0 + +#define mmDMA4_QM_CQ_PTR_LO_4 0x5881B4 + +#define mmDMA4_QM_CQ_PTR_HI_4 0x5881B8 + +#define mmDMA4_QM_CQ_TSIZE_4 0x5881BC + +#define mmDMA4_QM_CQ_CTL_4 0x5881C0 + +#define mmDMA4_QM_CQ_PTR_LO_STS_0 0x5881C4 + +#define mmDMA4_QM_CQ_PTR_LO_STS_1 0x5881C8 + +#define mmDMA4_QM_CQ_PTR_LO_STS_2 0x5881CC + +#define mmDMA4_QM_CQ_PTR_LO_STS_3 0x5881D0 + +#define mmDMA4_QM_CQ_PTR_LO_STS_4 0x5881D4 + +#define mmDMA4_QM_CQ_PTR_HI_STS_0 0x5881D8 + +#define mmDMA4_QM_CQ_PTR_HI_STS_1 0x5881DC + +#define mmDMA4_QM_CQ_PTR_HI_STS_2 0x5881E0 + +#define mmDMA4_QM_CQ_PTR_HI_STS_3 0x5881E4 + +#define mmDMA4_QM_CQ_PTR_HI_STS_4 0x5881E8 + +#define mmDMA4_QM_CQ_TSIZE_STS_0 0x5881EC + +#define mmDMA4_QM_CQ_TSIZE_STS_1 0x5881F0 + +#define mmDMA4_QM_CQ_TSIZE_STS_2 0x5881F4 + +#define mmDMA4_QM_CQ_TSIZE_STS_3 0x5881F8 + +#define mmDMA4_QM_CQ_TSIZE_STS_4 0x5881FC + +#define mmDMA4_QM_CQ_CTL_STS_0 0x588200 + +#define mmDMA4_QM_CQ_CTL_STS_1 0x588204 + +#define mmDMA4_QM_CQ_CTL_STS_2 0x588208 + +#define mmDMA4_QM_CQ_CTL_STS_3 0x58820C + +#define mmDMA4_QM_CQ_CTL_STS_4 0x588210 + +#define mmDMA4_QM_CQ_IFIFO_CNT_0 0x588214 + +#define mmDMA4_QM_CQ_IFIFO_CNT_1 0x588218 + +#define mmDMA4_QM_CQ_IFIFO_CNT_2 0x58821C + +#define mmDMA4_QM_CQ_IFIFO_CNT_3 0x588220 + +#define mmDMA4_QM_CQ_IFIFO_CNT_4 0x588224 + +#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_0 0x588228 + +#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_1 0x58822C + +#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_2 0x588230 + +#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_3 0x588234 + +#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_4 0x588238 + +#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_0 0x58823C + +#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_1 0x588240 + +#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_2 0x588244 + +#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_3 0x588248 + +#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_4 0x58824C + +#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_0 0x588250 + +#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_1 0x588254 + +#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_2 0x588258 + +#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_3 0x58825C + +#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_4 0x588260 + +#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_0 0x588264 + +#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_1 0x588268 + +#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_2 0x58826C + +#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_3 0x588270 + +#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_4 0x588274 + +#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_0 0x588278 + +#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_1 0x58827C + +#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_2 0x588280 + +#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_3 0x588284 + +#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_4 0x588288 + +#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_0 0x58828C + +#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_1 0x588290 + +#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_2 0x588294 + +#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_3 0x588298 + +#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_4 0x58829C + +#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_0 0x5882A0 + +#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_1 0x5882A4 + +#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_2 0x5882A8 + +#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_3 0x5882AC + +#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_4 0x5882B0 + +#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_0 0x5882B4 + +#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_1 0x5882B8 + +#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_2 0x5882BC + +#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_3 0x5882C0 + +#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_4 0x5882C4 + +#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_0 0x5882C8 + +#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_1 0x5882CC + +#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_2 0x5882D0 + +#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_3 0x5882D4 + +#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_4 0x5882D8 + +#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5882E0 + +#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5882E4 + +#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5882E8 + +#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5882EC + +#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5882F0 + +#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5882F4 + +#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5882F8 + +#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5882FC + +#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x588300 + +#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x588304 + +#define mmDMA4_QM_CP_FENCE0_RDATA_0 0x588308 + +#define mmDMA4_QM_CP_FENCE0_RDATA_1 0x58830C + +#define mmDMA4_QM_CP_FENCE0_RDATA_2 0x588310 + +#define mmDMA4_QM_CP_FENCE0_RDATA_3 0x588314 + +#define mmDMA4_QM_CP_FENCE0_RDATA_4 0x588318 + +#define mmDMA4_QM_CP_FENCE1_RDATA_0 0x58831C + +#define mmDMA4_QM_CP_FENCE1_RDATA_1 0x588320 + +#define mmDMA4_QM_CP_FENCE1_RDATA_2 0x588324 + +#define mmDMA4_QM_CP_FENCE1_RDATA_3 0x588328 + +#define mmDMA4_QM_CP_FENCE1_RDATA_4 0x58832C + +#define mmDMA4_QM_CP_FENCE2_RDATA_0 0x588330 + +#define mmDMA4_QM_CP_FENCE2_RDATA_1 0x588334 + +#define mmDMA4_QM_CP_FENCE2_RDATA_2 0x588338 + +#define mmDMA4_QM_CP_FENCE2_RDATA_3 0x58833C + +#define mmDMA4_QM_CP_FENCE2_RDATA_4 0x588340 + +#define mmDMA4_QM_CP_FENCE3_RDATA_0 0x588344 + +#define mmDMA4_QM_CP_FENCE3_RDATA_1 0x588348 + +#define mmDMA4_QM_CP_FENCE3_RDATA_2 0x58834C + +#define mmDMA4_QM_CP_FENCE3_RDATA_3 0x588350 + +#define mmDMA4_QM_CP_FENCE3_RDATA_4 0x588354 + +#define mmDMA4_QM_CP_FENCE0_CNT_0 0x588358 + +#define mmDMA4_QM_CP_FENCE0_CNT_1 0x58835C + +#define mmDMA4_QM_CP_FENCE0_CNT_2 0x588360 + +#define mmDMA4_QM_CP_FENCE0_CNT_3 0x588364 + +#define mmDMA4_QM_CP_FENCE0_CNT_4 0x588368 + +#define mmDMA4_QM_CP_FENCE1_CNT_0 0x58836C + +#define mmDMA4_QM_CP_FENCE1_CNT_1 0x588370 + +#define mmDMA4_QM_CP_FENCE1_CNT_2 0x588374 + +#define mmDMA4_QM_CP_FENCE1_CNT_3 0x588378 + +#define mmDMA4_QM_CP_FENCE1_CNT_4 0x58837C + +#define mmDMA4_QM_CP_FENCE2_CNT_0 0x588380 + +#define mmDMA4_QM_CP_FENCE2_CNT_1 0x588384 + +#define mmDMA4_QM_CP_FENCE2_CNT_2 0x588388 + +#define mmDMA4_QM_CP_FENCE2_CNT_3 0x58838C + +#define mmDMA4_QM_CP_FENCE2_CNT_4 0x588390 + +#define mmDMA4_QM_CP_FENCE3_CNT_0 0x588394 + +#define mmDMA4_QM_CP_FENCE3_CNT_1 0x588398 + +#define mmDMA4_QM_CP_FENCE3_CNT_2 0x58839C + +#define mmDMA4_QM_CP_FENCE3_CNT_3 0x5883A0 + +#define mmDMA4_QM_CP_FENCE3_CNT_4 0x5883A4 + +#define mmDMA4_QM_CP_STS_0 0x5883A8 + +#define mmDMA4_QM_CP_STS_1 0x5883AC + +#define mmDMA4_QM_CP_STS_2 0x5883B0 + +#define mmDMA4_QM_CP_STS_3 0x5883B4 + +#define mmDMA4_QM_CP_STS_4 0x5883B8 + +#define mmDMA4_QM_CP_CURRENT_INST_LO_0 0x5883BC + +#define mmDMA4_QM_CP_CURRENT_INST_LO_1 0x5883C0 + +#define mmDMA4_QM_CP_CURRENT_INST_LO_2 0x5883C4 + +#define mmDMA4_QM_CP_CURRENT_INST_LO_3 0x5883C8 + +#define mmDMA4_QM_CP_CURRENT_INST_LO_4 0x5883CC + +#define mmDMA4_QM_CP_CURRENT_INST_HI_0 0x5883D0 + +#define mmDMA4_QM_CP_CURRENT_INST_HI_1 0x5883D4 + +#define mmDMA4_QM_CP_CURRENT_INST_HI_2 0x5883D8 + +#define mmDMA4_QM_CP_CURRENT_INST_HI_3 0x5883DC + +#define mmDMA4_QM_CP_CURRENT_INST_HI_4 0x5883E0 + +#define mmDMA4_QM_CP_BARRIER_CFG_0 0x5883F4 + +#define mmDMA4_QM_CP_BARRIER_CFG_1 0x5883F8 + +#define mmDMA4_QM_CP_BARRIER_CFG_2 0x5883FC + +#define mmDMA4_QM_CP_BARRIER_CFG_3 0x588400 + +#define mmDMA4_QM_CP_BARRIER_CFG_4 0x588404 + +#define mmDMA4_QM_CP_DBG_0_0 0x588408 + +#define mmDMA4_QM_CP_DBG_0_1 0x58840C + +#define mmDMA4_QM_CP_DBG_0_2 0x588410 + +#define mmDMA4_QM_CP_DBG_0_3 0x588414 + +#define mmDMA4_QM_CP_DBG_0_4 0x588418 + +#define mmDMA4_QM_CP_ARUSER_31_11_0 0x58841C + +#define mmDMA4_QM_CP_ARUSER_31_11_1 0x588420 + +#define mmDMA4_QM_CP_ARUSER_31_11_2 0x588424 + +#define mmDMA4_QM_CP_ARUSER_31_11_3 0x588428 + +#define mmDMA4_QM_CP_ARUSER_31_11_4 0x58842C + +#define mmDMA4_QM_CP_AWUSER_31_11_0 0x588430 + +#define mmDMA4_QM_CP_AWUSER_31_11_1 0x588434 + +#define mmDMA4_QM_CP_AWUSER_31_11_2 0x588438 + +#define mmDMA4_QM_CP_AWUSER_31_11_3 0x58843C + +#define mmDMA4_QM_CP_AWUSER_31_11_4 0x588440 + +#define mmDMA4_QM_ARB_CFG_0 0x588A00 + +#define mmDMA4_QM_ARB_CHOISE_Q_PUSH 0x588A04 + +#define mmDMA4_QM_ARB_WRR_WEIGHT_0 0x588A08 + +#define mmDMA4_QM_ARB_WRR_WEIGHT_1 0x588A0C + +#define mmDMA4_QM_ARB_WRR_WEIGHT_2 0x588A10 + +#define mmDMA4_QM_ARB_WRR_WEIGHT_3 0x588A14 + +#define mmDMA4_QM_ARB_CFG_1 0x588A18 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_0 0x588A20 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_1 0x588A24 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_2 0x588A28 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_3 0x588A2C + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_4 0x588A30 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_5 0x588A34 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_6 0x588A38 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_7 0x588A3C + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_8 0x588A40 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_9 0x588A44 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_10 0x588A48 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_11 0x588A4C + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_12 0x588A50 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_13 0x588A54 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_14 0x588A58 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_15 0x588A5C + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_16 0x588A60 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_17 0x588A64 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_18 0x588A68 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_19 0x588A6C + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_20 0x588A70 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_21 0x588A74 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_22 0x588A78 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_23 0x588A7C + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_24 0x588A80 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_25 0x588A84 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_26 0x588A88 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_27 0x588A8C + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_28 0x588A90 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_29 0x588A94 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_30 0x588A98 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_31 0x588A9C + +#define mmDMA4_QM_ARB_MST_CRED_INC 0x588AA0 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x588AA4 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x588AA8 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x588AAC + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x588AB0 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x588AB4 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x588AB8 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x588ABC + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x588AC0 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x588AC4 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x588AC8 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x588ACC + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x588AD0 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x588AD4 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x588AD8 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x588ADC + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x588AE0 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x588AE4 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x588AE8 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x588AEC + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x588AF0 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x588AF4 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x588AF8 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x588AFC + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x588B00 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x588B04 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x588B08 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x588B0C + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x588B10 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x588B14 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x588B18 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x588B1C + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x588B20 + +#define mmDMA4_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x588B28 + +#define mmDMA4_QM_ARB_MST_SLAVE_EN 0x588B2C + +#define mmDMA4_QM_ARB_MST_QUIET_PER 0x588B34 + +#define mmDMA4_QM_ARB_SLV_CHOISE_WDT 0x588B38 + +#define mmDMA4_QM_ARB_SLV_ID 0x588B3C + +#define mmDMA4_QM_ARB_MSG_MAX_INFLIGHT 0x588B44 + +#define mmDMA4_QM_ARB_MSG_AWUSER_31_11 0x588B48 + +#define mmDMA4_QM_ARB_MSG_AWUSER_SEC_PROP 0x588B4C + +#define mmDMA4_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x588B50 + +#define mmDMA4_QM_ARB_BASE_LO 0x588B54 + +#define mmDMA4_QM_ARB_BASE_HI 0x588B58 + +#define mmDMA4_QM_ARB_STATE_STS 0x588B80 + +#define mmDMA4_QM_ARB_CHOISE_FULLNESS_STS 0x588B84 + +#define mmDMA4_QM_ARB_MSG_STS 0x588B88 + +#define mmDMA4_QM_ARB_SLV_CHOISE_Q_HEAD 0x588B8C + +#define mmDMA4_QM_ARB_ERR_CAUSE 0x588B9C + +#define mmDMA4_QM_ARB_ERR_MSG_EN 0x588BA0 + +#define mmDMA4_QM_ARB_ERR_STS_DRP 0x588BA8 + +#define mmDMA4_QM_ARB_MST_CRED_STS_0 0x588BB0 + +#define mmDMA4_QM_ARB_MST_CRED_STS_1 0x588BB4 + +#define mmDMA4_QM_ARB_MST_CRED_STS_2 0x588BB8 + +#define mmDMA4_QM_ARB_MST_CRED_STS_3 0x588BBC + +#define mmDMA4_QM_ARB_MST_CRED_STS_4 0x588BC0 + +#define mmDMA4_QM_ARB_MST_CRED_STS_5 0x588BC4 + +#define mmDMA4_QM_ARB_MST_CRED_STS_6 0x588BC8 + +#define mmDMA4_QM_ARB_MST_CRED_STS_7 0x588BCC + +#define mmDMA4_QM_ARB_MST_CRED_STS_8 0x588BD0 + +#define mmDMA4_QM_ARB_MST_CRED_STS_9 0x588BD4 + +#define mmDMA4_QM_ARB_MST_CRED_STS_10 0x588BD8 + +#define mmDMA4_QM_ARB_MST_CRED_STS_11 0x588BDC + +#define mmDMA4_QM_ARB_MST_CRED_STS_12 0x588BE0 + +#define mmDMA4_QM_ARB_MST_CRED_STS_13 0x588BE4 + +#define mmDMA4_QM_ARB_MST_CRED_STS_14 0x588BE8 + +#define mmDMA4_QM_ARB_MST_CRED_STS_15 0x588BEC + +#define mmDMA4_QM_ARB_MST_CRED_STS_16 0x588BF0 + +#define mmDMA4_QM_ARB_MST_CRED_STS_17 0x588BF4 + +#define mmDMA4_QM_ARB_MST_CRED_STS_18 0x588BF8 + +#define mmDMA4_QM_ARB_MST_CRED_STS_19 0x588BFC + +#define mmDMA4_QM_ARB_MST_CRED_STS_20 0x588C00 + +#define mmDMA4_QM_ARB_MST_CRED_STS_21 0x588C04 + +#define mmDMA4_QM_ARB_MST_CRED_STS_22 0x588C08 + +#define mmDMA4_QM_ARB_MST_CRED_STS_23 0x588C0C + +#define mmDMA4_QM_ARB_MST_CRED_STS_24 0x588C10 + +#define mmDMA4_QM_ARB_MST_CRED_STS_25 0x588C14 + +#define mmDMA4_QM_ARB_MST_CRED_STS_26 0x588C18 + +#define mmDMA4_QM_ARB_MST_CRED_STS_27 0x588C1C + +#define mmDMA4_QM_ARB_MST_CRED_STS_28 0x588C20 + +#define mmDMA4_QM_ARB_MST_CRED_STS_29 0x588C24 + +#define mmDMA4_QM_ARB_MST_CRED_STS_30 0x588C28 + +#define mmDMA4_QM_ARB_MST_CRED_STS_31 0x588C2C + +#define mmDMA4_QM_CGM_CFG 0x588C70 + +#define mmDMA4_QM_CGM_STS 0x588C74 + +#define mmDMA4_QM_CGM_CFG1 0x588C78 + +#define mmDMA4_QM_LOCAL_RANGE_BASE 0x588C80 + +#define mmDMA4_QM_LOCAL_RANGE_SIZE 0x588C84 + +#define mmDMA4_QM_CSMR_STRICT_PRIO_CFG 0x588C90 + +#define mmDMA4_QM_HBW_RD_RATE_LIM_CFG_1 0x588C94 + +#define mmDMA4_QM_LBW_WR_RATE_LIM_CFG_0 0x588C98 + +#define mmDMA4_QM_LBW_WR_RATE_LIM_CFG_1 0x588C9C + +#define mmDMA4_QM_HBW_RD_RATE_LIM_CFG_0 0x588CA0 + +#define mmDMA4_QM_GLBL_AXCACHE 0x588CA4 + +#define mmDMA4_QM_IND_GW_APB_CFG 0x588CB0 + +#define mmDMA4_QM_IND_GW_APB_WDATA 0x588CB4 + +#define mmDMA4_QM_IND_GW_APB_RDATA 0x588CB8 + +#define mmDMA4_QM_IND_GW_APB_STATUS 0x588CBC + +#define mmDMA4_QM_GLBL_ERR_ADDR_LO 0x588CD0 + +#define mmDMA4_QM_GLBL_ERR_ADDR_HI 0x588CD4 + +#define mmDMA4_QM_GLBL_ERR_WDATA 0x588CD8 + +#define mmDMA4_QM_GLBL_MEM_INIT_BUSY 0x588D00 + +#endif /* ASIC_REG_DMA4_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma5_core_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma5_core_regs.h new file mode 100644 index 000000000000..6e07c6fb6fc9 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma5_core_regs.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA5_CORE_REGS_H_ +#define ASIC_REG_DMA5_CORE_REGS_H_ + +/* + ***************************************** + * DMA5_CORE (Prototype: DMA_CORE) + ***************************************** + */ + +#define mmDMA5_CORE_CFG_0 0x5A0000 + +#define mmDMA5_CORE_CFG_1 0x5A0004 + +#define mmDMA5_CORE_LBW_MAX_OUTSTAND 0x5A0008 + +#define mmDMA5_CORE_SRC_BASE_LO 0x5A0014 + +#define mmDMA5_CORE_SRC_BASE_HI 0x5A0018 + +#define mmDMA5_CORE_DST_BASE_LO 0x5A001C + +#define mmDMA5_CORE_DST_BASE_HI 0x5A0020 + +#define mmDMA5_CORE_SRC_TSIZE_1 0x5A002C + +#define mmDMA5_CORE_SRC_STRIDE_1 0x5A0030 + +#define mmDMA5_CORE_SRC_TSIZE_2 0x5A0034 + +#define mmDMA5_CORE_SRC_STRIDE_2 0x5A0038 + +#define mmDMA5_CORE_SRC_TSIZE_3 0x5A003C + +#define mmDMA5_CORE_SRC_STRIDE_3 0x5A0040 + +#define mmDMA5_CORE_SRC_TSIZE_4 0x5A0044 + +#define mmDMA5_CORE_SRC_STRIDE_4 0x5A0048 + +#define mmDMA5_CORE_SRC_TSIZE_0 0x5A004C + +#define mmDMA5_CORE_DST_TSIZE_1 0x5A0054 + +#define mmDMA5_CORE_DST_STRIDE_1 0x5A0058 + +#define mmDMA5_CORE_DST_TSIZE_2 0x5A005C + +#define mmDMA5_CORE_DST_STRIDE_2 0x5A0060 + +#define mmDMA5_CORE_DST_TSIZE_3 0x5A0064 + +#define mmDMA5_CORE_DST_STRIDE_3 0x5A0068 + +#define mmDMA5_CORE_DST_TSIZE_4 0x5A006C + +#define mmDMA5_CORE_DST_STRIDE_4 0x5A0070 + +#define mmDMA5_CORE_DST_TSIZE_0 0x5A0074 + +#define mmDMA5_CORE_COMMIT 0x5A0078 + +#define mmDMA5_CORE_WR_COMP_WDATA 0x5A007C + +#define mmDMA5_CORE_WR_COMP_ADDR_LO 0x5A0080 + +#define mmDMA5_CORE_WR_COMP_ADDR_HI 0x5A0084 + +#define mmDMA5_CORE_WR_COMP_AWUSER_31_11 0x5A0088 + +#define mmDMA5_CORE_TE_NUMROWS 0x5A0094 + +#define mmDMA5_CORE_PROT 0x5A00B8 + +#define mmDMA5_CORE_SECURE_PROPS 0x5A00F0 + +#define mmDMA5_CORE_NON_SECURE_PROPS 0x5A00F4 + +#define mmDMA5_CORE_RD_MAX_OUTSTAND 0x5A0100 + +#define mmDMA5_CORE_RD_MAX_SIZE 0x5A0104 + +#define mmDMA5_CORE_RD_ARCACHE 0x5A0108 + +#define mmDMA5_CORE_RD_ARUSER_31_11 0x5A0110 + +#define mmDMA5_CORE_RD_INFLIGHTS 0x5A0114 + +#define mmDMA5_CORE_WR_MAX_OUTSTAND 0x5A0120 + +#define mmDMA5_CORE_WR_MAX_AWID 0x5A0124 + +#define mmDMA5_CORE_WR_AWCACHE 0x5A0128 + +#define mmDMA5_CORE_WR_AWUSER_31_11 0x5A0130 + +#define mmDMA5_CORE_WR_INFLIGHTS 0x5A0134 + +#define mmDMA5_CORE_RD_RATE_LIM_CFG_0 0x5A0150 + +#define mmDMA5_CORE_RD_RATE_LIM_CFG_1 0x5A0154 + +#define mmDMA5_CORE_WR_RATE_LIM_CFG_0 0x5A0158 + +#define mmDMA5_CORE_WR_RATE_LIM_CFG_1 0x5A015C + +#define mmDMA5_CORE_ERR_CFG 0x5A0160 + +#define mmDMA5_CORE_ERR_CAUSE 0x5A0164 + +#define mmDMA5_CORE_ERRMSG_ADDR_LO 0x5A0170 + +#define mmDMA5_CORE_ERRMSG_ADDR_HI 0x5A0174 + +#define mmDMA5_CORE_ERRMSG_WDATA 0x5A0178 + +#define mmDMA5_CORE_STS0 0x5A0190 + +#define mmDMA5_CORE_STS1 0x5A0194 + +#define mmDMA5_CORE_RD_DBGMEM_ADD 0x5A0200 + +#define mmDMA5_CORE_RD_DBGMEM_DATA_WR 0x5A0204 + +#define mmDMA5_CORE_RD_DBGMEM_DATA_RD 0x5A0208 + +#define mmDMA5_CORE_RD_DBGMEM_CTRL 0x5A020C + +#define mmDMA5_CORE_RD_DBGMEM_RC 0x5A0210 + +#define mmDMA5_CORE_DBG_HBW_AXI_AR_CNT 0x5A0220 + +#define mmDMA5_CORE_DBG_HBW_AXI_AW_CNT 0x5A0224 + +#define mmDMA5_CORE_DBG_LBW_AXI_AW_CNT 0x5A0228 + +#define mmDMA5_CORE_DBG_DESC_CNT 0x5A022C + +#define mmDMA5_CORE_DBG_STS 0x5A0230 + +#define mmDMA5_CORE_DBG_RD_DESC_ID 0x5A0234 + +#define mmDMA5_CORE_DBG_WR_DESC_ID 0x5A0238 + +#endif /* ASIC_REG_DMA5_CORE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma5_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma5_qm_regs.h new file mode 100644 index 000000000000..0faea21756c5 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma5_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA5_QM_REGS_H_ +#define ASIC_REG_DMA5_QM_REGS_H_ + +/* + ***************************************** + * DMA5_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA5_QM_GLBL_CFG0 0x5A8000 + +#define mmDMA5_QM_GLBL_CFG1 0x5A8004 + +#define mmDMA5_QM_GLBL_PROT 0x5A8008 + +#define mmDMA5_QM_GLBL_ERR_CFG 0x5A800C + +#define mmDMA5_QM_GLBL_SECURE_PROPS_0 0x5A8010 + +#define mmDMA5_QM_GLBL_SECURE_PROPS_1 0x5A8014 + +#define mmDMA5_QM_GLBL_SECURE_PROPS_2 0x5A8018 + +#define mmDMA5_QM_GLBL_SECURE_PROPS_3 0x5A801C + +#define mmDMA5_QM_GLBL_SECURE_PROPS_4 0x5A8020 + +#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_0 0x5A8024 + +#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_1 0x5A8028 + +#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_2 0x5A802C + +#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_3 0x5A8030 + +#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_4 0x5A8034 + +#define mmDMA5_QM_GLBL_STS0 0x5A8038 + +#define mmDMA5_QM_GLBL_STS1_0 0x5A8040 + +#define mmDMA5_QM_GLBL_STS1_1 0x5A8044 + +#define mmDMA5_QM_GLBL_STS1_2 0x5A8048 + +#define mmDMA5_QM_GLBL_STS1_3 0x5A804C + +#define mmDMA5_QM_GLBL_STS1_4 0x5A8050 + +#define mmDMA5_QM_GLBL_MSG_EN_0 0x5A8054 + +#define mmDMA5_QM_GLBL_MSG_EN_1 0x5A8058 + +#define mmDMA5_QM_GLBL_MSG_EN_2 0x5A805C + +#define mmDMA5_QM_GLBL_MSG_EN_3 0x5A8060 + +#define mmDMA5_QM_GLBL_MSG_EN_4 0x5A8068 + +#define mmDMA5_QM_PQ_BASE_LO_0 0x5A8070 + +#define mmDMA5_QM_PQ_BASE_LO_1 0x5A8074 + +#define mmDMA5_QM_PQ_BASE_LO_2 0x5A8078 + +#define mmDMA5_QM_PQ_BASE_LO_3 0x5A807C + +#define mmDMA5_QM_PQ_BASE_HI_0 0x5A8080 + +#define mmDMA5_QM_PQ_BASE_HI_1 0x5A8084 + +#define mmDMA5_QM_PQ_BASE_HI_2 0x5A8088 + +#define mmDMA5_QM_PQ_BASE_HI_3 0x5A808C + +#define mmDMA5_QM_PQ_SIZE_0 0x5A8090 + +#define mmDMA5_QM_PQ_SIZE_1 0x5A8094 + +#define mmDMA5_QM_PQ_SIZE_2 0x5A8098 + +#define mmDMA5_QM_PQ_SIZE_3 0x5A809C + +#define mmDMA5_QM_PQ_PI_0 0x5A80A0 + +#define mmDMA5_QM_PQ_PI_1 0x5A80A4 + +#define mmDMA5_QM_PQ_PI_2 0x5A80A8 + +#define mmDMA5_QM_PQ_PI_3 0x5A80AC + +#define mmDMA5_QM_PQ_CI_0 0x5A80B0 + +#define mmDMA5_QM_PQ_CI_1 0x5A80B4 + +#define mmDMA5_QM_PQ_CI_2 0x5A80B8 + +#define mmDMA5_QM_PQ_CI_3 0x5A80BC + +#define mmDMA5_QM_PQ_CFG0_0 0x5A80C0 + +#define mmDMA5_QM_PQ_CFG0_1 0x5A80C4 + +#define mmDMA5_QM_PQ_CFG0_2 0x5A80C8 + +#define mmDMA5_QM_PQ_CFG0_3 0x5A80CC + +#define mmDMA5_QM_PQ_CFG1_0 0x5A80D0 + +#define mmDMA5_QM_PQ_CFG1_1 0x5A80D4 + +#define mmDMA5_QM_PQ_CFG1_2 0x5A80D8 + +#define mmDMA5_QM_PQ_CFG1_3 0x5A80DC + +#define mmDMA5_QM_PQ_ARUSER_31_11_0 0x5A80E0 + +#define mmDMA5_QM_PQ_ARUSER_31_11_1 0x5A80E4 + +#define mmDMA5_QM_PQ_ARUSER_31_11_2 0x5A80E8 + +#define mmDMA5_QM_PQ_ARUSER_31_11_3 0x5A80EC + +#define mmDMA5_QM_PQ_STS0_0 0x5A80F0 + +#define mmDMA5_QM_PQ_STS0_1 0x5A80F4 + +#define mmDMA5_QM_PQ_STS0_2 0x5A80F8 + +#define mmDMA5_QM_PQ_STS0_3 0x5A80FC + +#define mmDMA5_QM_PQ_STS1_0 0x5A8100 + +#define mmDMA5_QM_PQ_STS1_1 0x5A8104 + +#define mmDMA5_QM_PQ_STS1_2 0x5A8108 + +#define mmDMA5_QM_PQ_STS1_3 0x5A810C + +#define mmDMA5_QM_CQ_CFG0_0 0x5A8110 + +#define mmDMA5_QM_CQ_CFG0_1 0x5A8114 + +#define mmDMA5_QM_CQ_CFG0_2 0x5A8118 + +#define mmDMA5_QM_CQ_CFG0_3 0x5A811C + +#define mmDMA5_QM_CQ_CFG0_4 0x5A8120 + +#define mmDMA5_QM_CQ_CFG1_0 0x5A8124 + +#define mmDMA5_QM_CQ_CFG1_1 0x5A8128 + +#define mmDMA5_QM_CQ_CFG1_2 0x5A812C + +#define mmDMA5_QM_CQ_CFG1_3 0x5A8130 + +#define mmDMA5_QM_CQ_CFG1_4 0x5A8134 + +#define mmDMA5_QM_CQ_ARUSER_31_11_0 0x5A8138 + +#define mmDMA5_QM_CQ_ARUSER_31_11_1 0x5A813C + +#define mmDMA5_QM_CQ_ARUSER_31_11_2 0x5A8140 + +#define mmDMA5_QM_CQ_ARUSER_31_11_3 0x5A8144 + +#define mmDMA5_QM_CQ_ARUSER_31_11_4 0x5A8148 + +#define mmDMA5_QM_CQ_STS0_0 0x5A814C + +#define mmDMA5_QM_CQ_STS0_1 0x5A8150 + +#define mmDMA5_QM_CQ_STS0_2 0x5A8154 + +#define mmDMA5_QM_CQ_STS0_3 0x5A8158 + +#define mmDMA5_QM_CQ_STS0_4 0x5A815C + +#define mmDMA5_QM_CQ_STS1_0 0x5A8160 + +#define mmDMA5_QM_CQ_STS1_1 0x5A8164 + +#define mmDMA5_QM_CQ_STS1_2 0x5A8168 + +#define mmDMA5_QM_CQ_STS1_3 0x5A816C + +#define mmDMA5_QM_CQ_STS1_4 0x5A8170 + +#define mmDMA5_QM_CQ_PTR_LO_0 0x5A8174 + +#define mmDMA5_QM_CQ_PTR_HI_0 0x5A8178 + +#define mmDMA5_QM_CQ_TSIZE_0 0x5A817C + +#define mmDMA5_QM_CQ_CTL_0 0x5A8180 + +#define mmDMA5_QM_CQ_PTR_LO_1 0x5A8184 + +#define mmDMA5_QM_CQ_PTR_HI_1 0x5A8188 + +#define mmDMA5_QM_CQ_TSIZE_1 0x5A818C + +#define mmDMA5_QM_CQ_CTL_1 0x5A8190 + +#define mmDMA5_QM_CQ_PTR_LO_2 0x5A8194 + +#define mmDMA5_QM_CQ_PTR_HI_2 0x5A8198 + +#define mmDMA5_QM_CQ_TSIZE_2 0x5A819C + +#define mmDMA5_QM_CQ_CTL_2 0x5A81A0 + +#define mmDMA5_QM_CQ_PTR_LO_3 0x5A81A4 + +#define mmDMA5_QM_CQ_PTR_HI_3 0x5A81A8 + +#define mmDMA5_QM_CQ_TSIZE_3 0x5A81AC + +#define mmDMA5_QM_CQ_CTL_3 0x5A81B0 + +#define mmDMA5_QM_CQ_PTR_LO_4 0x5A81B4 + +#define mmDMA5_QM_CQ_PTR_HI_4 0x5A81B8 + +#define mmDMA5_QM_CQ_TSIZE_4 0x5A81BC + +#define mmDMA5_QM_CQ_CTL_4 0x5A81C0 + +#define mmDMA5_QM_CQ_PTR_LO_STS_0 0x5A81C4 + +#define mmDMA5_QM_CQ_PTR_LO_STS_1 0x5A81C8 + +#define mmDMA5_QM_CQ_PTR_LO_STS_2 0x5A81CC + +#define mmDMA5_QM_CQ_PTR_LO_STS_3 0x5A81D0 + +#define mmDMA5_QM_CQ_PTR_LO_STS_4 0x5A81D4 + +#define mmDMA5_QM_CQ_PTR_HI_STS_0 0x5A81D8 + +#define mmDMA5_QM_CQ_PTR_HI_STS_1 0x5A81DC + +#define mmDMA5_QM_CQ_PTR_HI_STS_2 0x5A81E0 + +#define mmDMA5_QM_CQ_PTR_HI_STS_3 0x5A81E4 + +#define mmDMA5_QM_CQ_PTR_HI_STS_4 0x5A81E8 + +#define mmDMA5_QM_CQ_TSIZE_STS_0 0x5A81EC + +#define mmDMA5_QM_CQ_TSIZE_STS_1 0x5A81F0 + +#define mmDMA5_QM_CQ_TSIZE_STS_2 0x5A81F4 + +#define mmDMA5_QM_CQ_TSIZE_STS_3 0x5A81F8 + +#define mmDMA5_QM_CQ_TSIZE_STS_4 0x5A81FC + +#define mmDMA5_QM_CQ_CTL_STS_0 0x5A8200 + +#define mmDMA5_QM_CQ_CTL_STS_1 0x5A8204 + +#define mmDMA5_QM_CQ_CTL_STS_2 0x5A8208 + +#define mmDMA5_QM_CQ_CTL_STS_3 0x5A820C + +#define mmDMA5_QM_CQ_CTL_STS_4 0x5A8210 + +#define mmDMA5_QM_CQ_IFIFO_CNT_0 0x5A8214 + +#define mmDMA5_QM_CQ_IFIFO_CNT_1 0x5A8218 + +#define mmDMA5_QM_CQ_IFIFO_CNT_2 0x5A821C + +#define mmDMA5_QM_CQ_IFIFO_CNT_3 0x5A8220 + +#define mmDMA5_QM_CQ_IFIFO_CNT_4 0x5A8224 + +#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_0 0x5A8228 + +#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_1 0x5A822C + +#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_2 0x5A8230 + +#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_3 0x5A8234 + +#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_4 0x5A8238 + +#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_0 0x5A823C + +#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_1 0x5A8240 + +#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_2 0x5A8244 + +#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_3 0x5A8248 + +#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_4 0x5A824C + +#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_0 0x5A8250 + +#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_1 0x5A8254 + +#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_2 0x5A8258 + +#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_3 0x5A825C + +#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_4 0x5A8260 + +#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_0 0x5A8264 + +#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_1 0x5A8268 + +#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_2 0x5A826C + +#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_3 0x5A8270 + +#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_4 0x5A8274 + +#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_0 0x5A8278 + +#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_1 0x5A827C + +#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_2 0x5A8280 + +#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_3 0x5A8284 + +#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_4 0x5A8288 + +#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_0 0x5A828C + +#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_1 0x5A8290 + +#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_2 0x5A8294 + +#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_3 0x5A8298 + +#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_4 0x5A829C + +#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_0 0x5A82A0 + +#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_1 0x5A82A4 + +#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_2 0x5A82A8 + +#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_3 0x5A82AC + +#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_4 0x5A82B0 + +#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_0 0x5A82B4 + +#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_1 0x5A82B8 + +#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_2 0x5A82BC + +#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_3 0x5A82C0 + +#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_4 0x5A82C4 + +#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_0 0x5A82C8 + +#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_1 0x5A82CC + +#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_2 0x5A82D0 + +#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_3 0x5A82D4 + +#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_4 0x5A82D8 + +#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5A82E0 + +#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5A82E4 + +#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5A82E8 + +#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5A82EC + +#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5A82F0 + +#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5A82F4 + +#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5A82F8 + +#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5A82FC + +#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x5A8300 + +#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x5A8304 + +#define mmDMA5_QM_CP_FENCE0_RDATA_0 0x5A8308 + +#define mmDMA5_QM_CP_FENCE0_RDATA_1 0x5A830C + +#define mmDMA5_QM_CP_FENCE0_RDATA_2 0x5A8310 + +#define mmDMA5_QM_CP_FENCE0_RDATA_3 0x5A8314 + +#define mmDMA5_QM_CP_FENCE0_RDATA_4 0x5A8318 + +#define mmDMA5_QM_CP_FENCE1_RDATA_0 0x5A831C + +#define mmDMA5_QM_CP_FENCE1_RDATA_1 0x5A8320 + +#define mmDMA5_QM_CP_FENCE1_RDATA_2 0x5A8324 + +#define mmDMA5_QM_CP_FENCE1_RDATA_3 0x5A8328 + +#define mmDMA5_QM_CP_FENCE1_RDATA_4 0x5A832C + +#define mmDMA5_QM_CP_FENCE2_RDATA_0 0x5A8330 + +#define mmDMA5_QM_CP_FENCE2_RDATA_1 0x5A8334 + +#define mmDMA5_QM_CP_FENCE2_RDATA_2 0x5A8338 + +#define mmDMA5_QM_CP_FENCE2_RDATA_3 0x5A833C + +#define mmDMA5_QM_CP_FENCE2_RDATA_4 0x5A8340 + +#define mmDMA5_QM_CP_FENCE3_RDATA_0 0x5A8344 + +#define mmDMA5_QM_CP_FENCE3_RDATA_1 0x5A8348 + +#define mmDMA5_QM_CP_FENCE3_RDATA_2 0x5A834C + +#define mmDMA5_QM_CP_FENCE3_RDATA_3 0x5A8350 + +#define mmDMA5_QM_CP_FENCE3_RDATA_4 0x5A8354 + +#define mmDMA5_QM_CP_FENCE0_CNT_0 0x5A8358 + +#define mmDMA5_QM_CP_FENCE0_CNT_1 0x5A835C + +#define mmDMA5_QM_CP_FENCE0_CNT_2 0x5A8360 + +#define mmDMA5_QM_CP_FENCE0_CNT_3 0x5A8364 + +#define mmDMA5_QM_CP_FENCE0_CNT_4 0x5A8368 + +#define mmDMA5_QM_CP_FENCE1_CNT_0 0x5A836C + +#define mmDMA5_QM_CP_FENCE1_CNT_1 0x5A8370 + +#define mmDMA5_QM_CP_FENCE1_CNT_2 0x5A8374 + +#define mmDMA5_QM_CP_FENCE1_CNT_3 0x5A8378 + +#define mmDMA5_QM_CP_FENCE1_CNT_4 0x5A837C + +#define mmDMA5_QM_CP_FENCE2_CNT_0 0x5A8380 + +#define mmDMA5_QM_CP_FENCE2_CNT_1 0x5A8384 + +#define mmDMA5_QM_CP_FENCE2_CNT_2 0x5A8388 + +#define mmDMA5_QM_CP_FENCE2_CNT_3 0x5A838C + +#define mmDMA5_QM_CP_FENCE2_CNT_4 0x5A8390 + +#define mmDMA5_QM_CP_FENCE3_CNT_0 0x5A8394 + +#define mmDMA5_QM_CP_FENCE3_CNT_1 0x5A8398 + +#define mmDMA5_QM_CP_FENCE3_CNT_2 0x5A839C + +#define mmDMA5_QM_CP_FENCE3_CNT_3 0x5A83A0 + +#define mmDMA5_QM_CP_FENCE3_CNT_4 0x5A83A4 + +#define mmDMA5_QM_CP_STS_0 0x5A83A8 + +#define mmDMA5_QM_CP_STS_1 0x5A83AC + +#define mmDMA5_QM_CP_STS_2 0x5A83B0 + +#define mmDMA5_QM_CP_STS_3 0x5A83B4 + +#define mmDMA5_QM_CP_STS_4 0x5A83B8 + +#define mmDMA5_QM_CP_CURRENT_INST_LO_0 0x5A83BC + +#define mmDMA5_QM_CP_CURRENT_INST_LO_1 0x5A83C0 + +#define mmDMA5_QM_CP_CURRENT_INST_LO_2 0x5A83C4 + +#define mmDMA5_QM_CP_CURRENT_INST_LO_3 0x5A83C8 + +#define mmDMA5_QM_CP_CURRENT_INST_LO_4 0x5A83CC + +#define mmDMA5_QM_CP_CURRENT_INST_HI_0 0x5A83D0 + +#define mmDMA5_QM_CP_CURRENT_INST_HI_1 0x5A83D4 + +#define mmDMA5_QM_CP_CURRENT_INST_HI_2 0x5A83D8 + +#define mmDMA5_QM_CP_CURRENT_INST_HI_3 0x5A83DC + +#define mmDMA5_QM_CP_CURRENT_INST_HI_4 0x5A83E0 + +#define mmDMA5_QM_CP_BARRIER_CFG_0 0x5A83F4 + +#define mmDMA5_QM_CP_BARRIER_CFG_1 0x5A83F8 + +#define mmDMA5_QM_CP_BARRIER_CFG_2 0x5A83FC + +#define mmDMA5_QM_CP_BARRIER_CFG_3 0x5A8400 + +#define mmDMA5_QM_CP_BARRIER_CFG_4 0x5A8404 + +#define mmDMA5_QM_CP_DBG_0_0 0x5A8408 + +#define mmDMA5_QM_CP_DBG_0_1 0x5A840C + +#define mmDMA5_QM_CP_DBG_0_2 0x5A8410 + +#define mmDMA5_QM_CP_DBG_0_3 0x5A8414 + +#define mmDMA5_QM_CP_DBG_0_4 0x5A8418 + +#define mmDMA5_QM_CP_ARUSER_31_11_0 0x5A841C + +#define mmDMA5_QM_CP_ARUSER_31_11_1 0x5A8420 + +#define mmDMA5_QM_CP_ARUSER_31_11_2 0x5A8424 + +#define mmDMA5_QM_CP_ARUSER_31_11_3 0x5A8428 + +#define mmDMA5_QM_CP_ARUSER_31_11_4 0x5A842C + +#define mmDMA5_QM_CP_AWUSER_31_11_0 0x5A8430 + +#define mmDMA5_QM_CP_AWUSER_31_11_1 0x5A8434 + +#define mmDMA5_QM_CP_AWUSER_31_11_2 0x5A8438 + +#define mmDMA5_QM_CP_AWUSER_31_11_3 0x5A843C + +#define mmDMA5_QM_CP_AWUSER_31_11_4 0x5A8440 + +#define mmDMA5_QM_ARB_CFG_0 0x5A8A00 + +#define mmDMA5_QM_ARB_CHOISE_Q_PUSH 0x5A8A04 + +#define mmDMA5_QM_ARB_WRR_WEIGHT_0 0x5A8A08 + +#define mmDMA5_QM_ARB_WRR_WEIGHT_1 0x5A8A0C + +#define mmDMA5_QM_ARB_WRR_WEIGHT_2 0x5A8A10 + +#define mmDMA5_QM_ARB_WRR_WEIGHT_3 0x5A8A14 + +#define mmDMA5_QM_ARB_CFG_1 0x5A8A18 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_0 0x5A8A20 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_1 0x5A8A24 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_2 0x5A8A28 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_3 0x5A8A2C + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_4 0x5A8A30 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_5 0x5A8A34 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_6 0x5A8A38 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_7 0x5A8A3C + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_8 0x5A8A40 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_9 0x5A8A44 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_10 0x5A8A48 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_11 0x5A8A4C + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_12 0x5A8A50 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_13 0x5A8A54 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_14 0x5A8A58 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_15 0x5A8A5C + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_16 0x5A8A60 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_17 0x5A8A64 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_18 0x5A8A68 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_19 0x5A8A6C + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_20 0x5A8A70 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_21 0x5A8A74 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_22 0x5A8A78 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_23 0x5A8A7C + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_24 0x5A8A80 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_25 0x5A8A84 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_26 0x5A8A88 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_27 0x5A8A8C + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_28 0x5A8A90 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_29 0x5A8A94 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_30 0x5A8A98 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_31 0x5A8A9C + +#define mmDMA5_QM_ARB_MST_CRED_INC 0x5A8AA0 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x5A8AA4 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x5A8AA8 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x5A8AAC + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x5A8AB0 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x5A8AB4 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x5A8AB8 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x5A8ABC + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x5A8AC0 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x5A8AC4 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x5A8AC8 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x5A8ACC + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x5A8AD0 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x5A8AD4 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x5A8AD8 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x5A8ADC + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x5A8AE0 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x5A8AE4 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x5A8AE8 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x5A8AEC + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x5A8AF0 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x5A8AF4 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x5A8AF8 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x5A8AFC + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x5A8B00 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x5A8B04 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x5A8B08 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x5A8B0C + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x5A8B10 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x5A8B14 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x5A8B18 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x5A8B1C + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x5A8B20 + +#define mmDMA5_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x5A8B28 + +#define mmDMA5_QM_ARB_MST_SLAVE_EN 0x5A8B2C + +#define mmDMA5_QM_ARB_MST_QUIET_PER 0x5A8B34 + +#define mmDMA5_QM_ARB_SLV_CHOISE_WDT 0x5A8B38 + +#define mmDMA5_QM_ARB_SLV_ID 0x5A8B3C + +#define mmDMA5_QM_ARB_MSG_MAX_INFLIGHT 0x5A8B44 + +#define mmDMA5_QM_ARB_MSG_AWUSER_31_11 0x5A8B48 + +#define mmDMA5_QM_ARB_MSG_AWUSER_SEC_PROP 0x5A8B4C + +#define mmDMA5_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x5A8B50 + +#define mmDMA5_QM_ARB_BASE_LO 0x5A8B54 + +#define mmDMA5_QM_ARB_BASE_HI 0x5A8B58 + +#define mmDMA5_QM_ARB_STATE_STS 0x5A8B80 + +#define mmDMA5_QM_ARB_CHOISE_FULLNESS_STS 0x5A8B84 + +#define mmDMA5_QM_ARB_MSG_STS 0x5A8B88 + +#define mmDMA5_QM_ARB_SLV_CHOISE_Q_HEAD 0x5A8B8C + +#define mmDMA5_QM_ARB_ERR_CAUSE 0x5A8B9C + +#define mmDMA5_QM_ARB_ERR_MSG_EN 0x5A8BA0 + +#define mmDMA5_QM_ARB_ERR_STS_DRP 0x5A8BA8 + +#define mmDMA5_QM_ARB_MST_CRED_STS_0 0x5A8BB0 + +#define mmDMA5_QM_ARB_MST_CRED_STS_1 0x5A8BB4 + +#define mmDMA5_QM_ARB_MST_CRED_STS_2 0x5A8BB8 + +#define mmDMA5_QM_ARB_MST_CRED_STS_3 0x5A8BBC + +#define mmDMA5_QM_ARB_MST_CRED_STS_4 0x5A8BC0 + +#define mmDMA5_QM_ARB_MST_CRED_STS_5 0x5A8BC4 + +#define mmDMA5_QM_ARB_MST_CRED_STS_6 0x5A8BC8 + +#define mmDMA5_QM_ARB_MST_CRED_STS_7 0x5A8BCC + +#define mmDMA5_QM_ARB_MST_CRED_STS_8 0x5A8BD0 + +#define mmDMA5_QM_ARB_MST_CRED_STS_9 0x5A8BD4 + +#define mmDMA5_QM_ARB_MST_CRED_STS_10 0x5A8BD8 + +#define mmDMA5_QM_ARB_MST_CRED_STS_11 0x5A8BDC + +#define mmDMA5_QM_ARB_MST_CRED_STS_12 0x5A8BE0 + +#define mmDMA5_QM_ARB_MST_CRED_STS_13 0x5A8BE4 + +#define mmDMA5_QM_ARB_MST_CRED_STS_14 0x5A8BE8 + +#define mmDMA5_QM_ARB_MST_CRED_STS_15 0x5A8BEC + +#define mmDMA5_QM_ARB_MST_CRED_STS_16 0x5A8BF0 + +#define mmDMA5_QM_ARB_MST_CRED_STS_17 0x5A8BF4 + +#define mmDMA5_QM_ARB_MST_CRED_STS_18 0x5A8BF8 + +#define mmDMA5_QM_ARB_MST_CRED_STS_19 0x5A8BFC + +#define mmDMA5_QM_ARB_MST_CRED_STS_20 0x5A8C00 + +#define mmDMA5_QM_ARB_MST_CRED_STS_21 0x5A8C04 + +#define mmDMA5_QM_ARB_MST_CRED_STS_22 0x5A8C08 + +#define mmDMA5_QM_ARB_MST_CRED_STS_23 0x5A8C0C + +#define mmDMA5_QM_ARB_MST_CRED_STS_24 0x5A8C10 + +#define mmDMA5_QM_ARB_MST_CRED_STS_25 0x5A8C14 + +#define mmDMA5_QM_ARB_MST_CRED_STS_26 0x5A8C18 + +#define mmDMA5_QM_ARB_MST_CRED_STS_27 0x5A8C1C + +#define mmDMA5_QM_ARB_MST_CRED_STS_28 0x5A8C20 + +#define mmDMA5_QM_ARB_MST_CRED_STS_29 0x5A8C24 + +#define mmDMA5_QM_ARB_MST_CRED_STS_30 0x5A8C28 + +#define mmDMA5_QM_ARB_MST_CRED_STS_31 0x5A8C2C + +#define mmDMA5_QM_CGM_CFG 0x5A8C70 + +#define mmDMA5_QM_CGM_STS 0x5A8C74 + +#define mmDMA5_QM_CGM_CFG1 0x5A8C78 + +#define mmDMA5_QM_LOCAL_RANGE_BASE 0x5A8C80 + +#define mmDMA5_QM_LOCAL_RANGE_SIZE 0x5A8C84 + +#define mmDMA5_QM_CSMR_STRICT_PRIO_CFG 0x5A8C90 + +#define mmDMA5_QM_HBW_RD_RATE_LIM_CFG_1 0x5A8C94 + +#define mmDMA5_QM_LBW_WR_RATE_LIM_CFG_0 0x5A8C98 + +#define mmDMA5_QM_LBW_WR_RATE_LIM_CFG_1 0x5A8C9C + +#define mmDMA5_QM_HBW_RD_RATE_LIM_CFG_0 0x5A8CA0 + +#define mmDMA5_QM_GLBL_AXCACHE 0x5A8CA4 + +#define mmDMA5_QM_IND_GW_APB_CFG 0x5A8CB0 + +#define mmDMA5_QM_IND_GW_APB_WDATA 0x5A8CB4 + +#define mmDMA5_QM_IND_GW_APB_RDATA 0x5A8CB8 + +#define mmDMA5_QM_IND_GW_APB_STATUS 0x5A8CBC + +#define mmDMA5_QM_GLBL_ERR_ADDR_LO 0x5A8CD0 + +#define mmDMA5_QM_GLBL_ERR_ADDR_HI 0x5A8CD4 + +#define mmDMA5_QM_GLBL_ERR_WDATA 0x5A8CD8 + +#define mmDMA5_QM_GLBL_MEM_INIT_BUSY 0x5A8D00 + +#endif /* ASIC_REG_DMA5_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma6_core_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma6_core_regs.h new file mode 100644 index 000000000000..4962c13e2e2e --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma6_core_regs.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA6_CORE_REGS_H_ +#define ASIC_REG_DMA6_CORE_REGS_H_ + +/* + ***************************************** + * DMA6_CORE (Prototype: DMA_CORE) + ***************************************** + */ + +#define mmDMA6_CORE_CFG_0 0x5C0000 + +#define mmDMA6_CORE_CFG_1 0x5C0004 + +#define mmDMA6_CORE_LBW_MAX_OUTSTAND 0x5C0008 + +#define mmDMA6_CORE_SRC_BASE_LO 0x5C0014 + +#define mmDMA6_CORE_SRC_BASE_HI 0x5C0018 + +#define mmDMA6_CORE_DST_BASE_LO 0x5C001C + +#define mmDMA6_CORE_DST_BASE_HI 0x5C0020 + +#define mmDMA6_CORE_SRC_TSIZE_1 0x5C002C + +#define mmDMA6_CORE_SRC_STRIDE_1 0x5C0030 + +#define mmDMA6_CORE_SRC_TSIZE_2 0x5C0034 + +#define mmDMA6_CORE_SRC_STRIDE_2 0x5C0038 + +#define mmDMA6_CORE_SRC_TSIZE_3 0x5C003C + +#define mmDMA6_CORE_SRC_STRIDE_3 0x5C0040 + +#define mmDMA6_CORE_SRC_TSIZE_4 0x5C0044 + +#define mmDMA6_CORE_SRC_STRIDE_4 0x5C0048 + +#define mmDMA6_CORE_SRC_TSIZE_0 0x5C004C + +#define mmDMA6_CORE_DST_TSIZE_1 0x5C0054 + +#define mmDMA6_CORE_DST_STRIDE_1 0x5C0058 + +#define mmDMA6_CORE_DST_TSIZE_2 0x5C005C + +#define mmDMA6_CORE_DST_STRIDE_2 0x5C0060 + +#define mmDMA6_CORE_DST_TSIZE_3 0x5C0064 + +#define mmDMA6_CORE_DST_STRIDE_3 0x5C0068 + +#define mmDMA6_CORE_DST_TSIZE_4 0x5C006C + +#define mmDMA6_CORE_DST_STRIDE_4 0x5C0070 + +#define mmDMA6_CORE_DST_TSIZE_0 0x5C0074 + +#define mmDMA6_CORE_COMMIT 0x5C0078 + +#define mmDMA6_CORE_WR_COMP_WDATA 0x5C007C + +#define mmDMA6_CORE_WR_COMP_ADDR_LO 0x5C0080 + +#define mmDMA6_CORE_WR_COMP_ADDR_HI 0x5C0084 + +#define mmDMA6_CORE_WR_COMP_AWUSER_31_11 0x5C0088 + +#define mmDMA6_CORE_TE_NUMROWS 0x5C0094 + +#define mmDMA6_CORE_PROT 0x5C00B8 + +#define mmDMA6_CORE_SECURE_PROPS 0x5C00F0 + +#define mmDMA6_CORE_NON_SECURE_PROPS 0x5C00F4 + +#define mmDMA6_CORE_RD_MAX_OUTSTAND 0x5C0100 + +#define mmDMA6_CORE_RD_MAX_SIZE 0x5C0104 + +#define mmDMA6_CORE_RD_ARCACHE 0x5C0108 + +#define mmDMA6_CORE_RD_ARUSER_31_11 0x5C0110 + +#define mmDMA6_CORE_RD_INFLIGHTS 0x5C0114 + +#define mmDMA6_CORE_WR_MAX_OUTSTAND 0x5C0120 + +#define mmDMA6_CORE_WR_MAX_AWID 0x5C0124 + +#define mmDMA6_CORE_WR_AWCACHE 0x5C0128 + +#define mmDMA6_CORE_WR_AWUSER_31_11 0x5C0130 + +#define mmDMA6_CORE_WR_INFLIGHTS 0x5C0134 + +#define mmDMA6_CORE_RD_RATE_LIM_CFG_0 0x5C0150 + +#define mmDMA6_CORE_RD_RATE_LIM_CFG_1 0x5C0154 + +#define mmDMA6_CORE_WR_RATE_LIM_CFG_0 0x5C0158 + +#define mmDMA6_CORE_WR_RATE_LIM_CFG_1 0x5C015C + +#define mmDMA6_CORE_ERR_CFG 0x5C0160 + +#define mmDMA6_CORE_ERR_CAUSE 0x5C0164 + +#define mmDMA6_CORE_ERRMSG_ADDR_LO 0x5C0170 + +#define mmDMA6_CORE_ERRMSG_ADDR_HI 0x5C0174 + +#define mmDMA6_CORE_ERRMSG_WDATA 0x5C0178 + +#define mmDMA6_CORE_STS0 0x5C0190 + +#define mmDMA6_CORE_STS1 0x5C0194 + +#define mmDMA6_CORE_RD_DBGMEM_ADD 0x5C0200 + +#define mmDMA6_CORE_RD_DBGMEM_DATA_WR 0x5C0204 + +#define mmDMA6_CORE_RD_DBGMEM_DATA_RD 0x5C0208 + +#define mmDMA6_CORE_RD_DBGMEM_CTRL 0x5C020C + +#define mmDMA6_CORE_RD_DBGMEM_RC 0x5C0210 + +#define mmDMA6_CORE_DBG_HBW_AXI_AR_CNT 0x5C0220 + +#define mmDMA6_CORE_DBG_HBW_AXI_AW_CNT 0x5C0224 + +#define mmDMA6_CORE_DBG_LBW_AXI_AW_CNT 0x5C0228 + +#define mmDMA6_CORE_DBG_DESC_CNT 0x5C022C + +#define mmDMA6_CORE_DBG_STS 0x5C0230 + +#define mmDMA6_CORE_DBG_RD_DESC_ID 0x5C0234 + +#define mmDMA6_CORE_DBG_WR_DESC_ID 0x5C0238 + +#endif /* ASIC_REG_DMA6_CORE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma6_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma6_qm_regs.h new file mode 100644 index 000000000000..af87adb94c94 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma6_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA6_QM_REGS_H_ +#define ASIC_REG_DMA6_QM_REGS_H_ + +/* + ***************************************** + * DMA6_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA6_QM_GLBL_CFG0 0x5C8000 + +#define mmDMA6_QM_GLBL_CFG1 0x5C8004 + +#define mmDMA6_QM_GLBL_PROT 0x5C8008 + +#define mmDMA6_QM_GLBL_ERR_CFG 0x5C800C + +#define mmDMA6_QM_GLBL_SECURE_PROPS_0 0x5C8010 + +#define mmDMA6_QM_GLBL_SECURE_PROPS_1 0x5C8014 + +#define mmDMA6_QM_GLBL_SECURE_PROPS_2 0x5C8018 + +#define mmDMA6_QM_GLBL_SECURE_PROPS_3 0x5C801C + +#define mmDMA6_QM_GLBL_SECURE_PROPS_4 0x5C8020 + +#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_0 0x5C8024 + +#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_1 0x5C8028 + +#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_2 0x5C802C + +#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_3 0x5C8030 + +#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_4 0x5C8034 + +#define mmDMA6_QM_GLBL_STS0 0x5C8038 + +#define mmDMA6_QM_GLBL_STS1_0 0x5C8040 + +#define mmDMA6_QM_GLBL_STS1_1 0x5C8044 + +#define mmDMA6_QM_GLBL_STS1_2 0x5C8048 + +#define mmDMA6_QM_GLBL_STS1_3 0x5C804C + +#define mmDMA6_QM_GLBL_STS1_4 0x5C8050 + +#define mmDMA6_QM_GLBL_MSG_EN_0 0x5C8054 + +#define mmDMA6_QM_GLBL_MSG_EN_1 0x5C8058 + +#define mmDMA6_QM_GLBL_MSG_EN_2 0x5C805C + +#define mmDMA6_QM_GLBL_MSG_EN_3 0x5C8060 + +#define mmDMA6_QM_GLBL_MSG_EN_4 0x5C8068 + +#define mmDMA6_QM_PQ_BASE_LO_0 0x5C8070 + +#define mmDMA6_QM_PQ_BASE_LO_1 0x5C8074 + +#define mmDMA6_QM_PQ_BASE_LO_2 0x5C8078 + +#define mmDMA6_QM_PQ_BASE_LO_3 0x5C807C + +#define mmDMA6_QM_PQ_BASE_HI_0 0x5C8080 + +#define mmDMA6_QM_PQ_BASE_HI_1 0x5C8084 + +#define mmDMA6_QM_PQ_BASE_HI_2 0x5C8088 + +#define mmDMA6_QM_PQ_BASE_HI_3 0x5C808C + +#define mmDMA6_QM_PQ_SIZE_0 0x5C8090 + +#define mmDMA6_QM_PQ_SIZE_1 0x5C8094 + +#define mmDMA6_QM_PQ_SIZE_2 0x5C8098 + +#define mmDMA6_QM_PQ_SIZE_3 0x5C809C + +#define mmDMA6_QM_PQ_PI_0 0x5C80A0 + +#define mmDMA6_QM_PQ_PI_1 0x5C80A4 + +#define mmDMA6_QM_PQ_PI_2 0x5C80A8 + +#define mmDMA6_QM_PQ_PI_3 0x5C80AC + +#define mmDMA6_QM_PQ_CI_0 0x5C80B0 + +#define mmDMA6_QM_PQ_CI_1 0x5C80B4 + +#define mmDMA6_QM_PQ_CI_2 0x5C80B8 + +#define mmDMA6_QM_PQ_CI_3 0x5C80BC + +#define mmDMA6_QM_PQ_CFG0_0 0x5C80C0 + +#define mmDMA6_QM_PQ_CFG0_1 0x5C80C4 + +#define mmDMA6_QM_PQ_CFG0_2 0x5C80C8 + +#define mmDMA6_QM_PQ_CFG0_3 0x5C80CC + +#define mmDMA6_QM_PQ_CFG1_0 0x5C80D0 + +#define mmDMA6_QM_PQ_CFG1_1 0x5C80D4 + +#define mmDMA6_QM_PQ_CFG1_2 0x5C80D8 + +#define mmDMA6_QM_PQ_CFG1_3 0x5C80DC + +#define mmDMA6_QM_PQ_ARUSER_31_11_0 0x5C80E0 + +#define mmDMA6_QM_PQ_ARUSER_31_11_1 0x5C80E4 + +#define mmDMA6_QM_PQ_ARUSER_31_11_2 0x5C80E8 + +#define mmDMA6_QM_PQ_ARUSER_31_11_3 0x5C80EC + +#define mmDMA6_QM_PQ_STS0_0 0x5C80F0 + +#define mmDMA6_QM_PQ_STS0_1 0x5C80F4 + +#define mmDMA6_QM_PQ_STS0_2 0x5C80F8 + +#define mmDMA6_QM_PQ_STS0_3 0x5C80FC + +#define mmDMA6_QM_PQ_STS1_0 0x5C8100 + +#define mmDMA6_QM_PQ_STS1_1 0x5C8104 + +#define mmDMA6_QM_PQ_STS1_2 0x5C8108 + +#define mmDMA6_QM_PQ_STS1_3 0x5C810C + +#define mmDMA6_QM_CQ_CFG0_0 0x5C8110 + +#define mmDMA6_QM_CQ_CFG0_1 0x5C8114 + +#define mmDMA6_QM_CQ_CFG0_2 0x5C8118 + +#define mmDMA6_QM_CQ_CFG0_3 0x5C811C + +#define mmDMA6_QM_CQ_CFG0_4 0x5C8120 + +#define mmDMA6_QM_CQ_CFG1_0 0x5C8124 + +#define mmDMA6_QM_CQ_CFG1_1 0x5C8128 + +#define mmDMA6_QM_CQ_CFG1_2 0x5C812C + +#define mmDMA6_QM_CQ_CFG1_3 0x5C8130 + +#define mmDMA6_QM_CQ_CFG1_4 0x5C8134 + +#define mmDMA6_QM_CQ_ARUSER_31_11_0 0x5C8138 + +#define mmDMA6_QM_CQ_ARUSER_31_11_1 0x5C813C + +#define mmDMA6_QM_CQ_ARUSER_31_11_2 0x5C8140 + +#define mmDMA6_QM_CQ_ARUSER_31_11_3 0x5C8144 + +#define mmDMA6_QM_CQ_ARUSER_31_11_4 0x5C8148 + +#define mmDMA6_QM_CQ_STS0_0 0x5C814C + +#define mmDMA6_QM_CQ_STS0_1 0x5C8150 + +#define mmDMA6_QM_CQ_STS0_2 0x5C8154 + +#define mmDMA6_QM_CQ_STS0_3 0x5C8158 + +#define mmDMA6_QM_CQ_STS0_4 0x5C815C + +#define mmDMA6_QM_CQ_STS1_0 0x5C8160 + +#define mmDMA6_QM_CQ_STS1_1 0x5C8164 + +#define mmDMA6_QM_CQ_STS1_2 0x5C8168 + +#define mmDMA6_QM_CQ_STS1_3 0x5C816C + +#define mmDMA6_QM_CQ_STS1_4 0x5C8170 + +#define mmDMA6_QM_CQ_PTR_LO_0 0x5C8174 + +#define mmDMA6_QM_CQ_PTR_HI_0 0x5C8178 + +#define mmDMA6_QM_CQ_TSIZE_0 0x5C817C + +#define mmDMA6_QM_CQ_CTL_0 0x5C8180 + +#define mmDMA6_QM_CQ_PTR_LO_1 0x5C8184 + +#define mmDMA6_QM_CQ_PTR_HI_1 0x5C8188 + +#define mmDMA6_QM_CQ_TSIZE_1 0x5C818C + +#define mmDMA6_QM_CQ_CTL_1 0x5C8190 + +#define mmDMA6_QM_CQ_PTR_LO_2 0x5C8194 + +#define mmDMA6_QM_CQ_PTR_HI_2 0x5C8198 + +#define mmDMA6_QM_CQ_TSIZE_2 0x5C819C + +#define mmDMA6_QM_CQ_CTL_2 0x5C81A0 + +#define mmDMA6_QM_CQ_PTR_LO_3 0x5C81A4 + +#define mmDMA6_QM_CQ_PTR_HI_3 0x5C81A8 + +#define mmDMA6_QM_CQ_TSIZE_3 0x5C81AC + +#define mmDMA6_QM_CQ_CTL_3 0x5C81B0 + +#define mmDMA6_QM_CQ_PTR_LO_4 0x5C81B4 + +#define mmDMA6_QM_CQ_PTR_HI_4 0x5C81B8 + +#define mmDMA6_QM_CQ_TSIZE_4 0x5C81BC + +#define mmDMA6_QM_CQ_CTL_4 0x5C81C0 + +#define mmDMA6_QM_CQ_PTR_LO_STS_0 0x5C81C4 + +#define mmDMA6_QM_CQ_PTR_LO_STS_1 0x5C81C8 + +#define mmDMA6_QM_CQ_PTR_LO_STS_2 0x5C81CC + +#define mmDMA6_QM_CQ_PTR_LO_STS_3 0x5C81D0 + +#define mmDMA6_QM_CQ_PTR_LO_STS_4 0x5C81D4 + +#define mmDMA6_QM_CQ_PTR_HI_STS_0 0x5C81D8 + +#define mmDMA6_QM_CQ_PTR_HI_STS_1 0x5C81DC + +#define mmDMA6_QM_CQ_PTR_HI_STS_2 0x5C81E0 + +#define mmDMA6_QM_CQ_PTR_HI_STS_3 0x5C81E4 + +#define mmDMA6_QM_CQ_PTR_HI_STS_4 0x5C81E8 + +#define mmDMA6_QM_CQ_TSIZE_STS_0 0x5C81EC + +#define mmDMA6_QM_CQ_TSIZE_STS_1 0x5C81F0 + +#define mmDMA6_QM_CQ_TSIZE_STS_2 0x5C81F4 + +#define mmDMA6_QM_CQ_TSIZE_STS_3 0x5C81F8 + +#define mmDMA6_QM_CQ_TSIZE_STS_4 0x5C81FC + +#define mmDMA6_QM_CQ_CTL_STS_0 0x5C8200 + +#define mmDMA6_QM_CQ_CTL_STS_1 0x5C8204 + +#define mmDMA6_QM_CQ_CTL_STS_2 0x5C8208 + +#define mmDMA6_QM_CQ_CTL_STS_3 0x5C820C + +#define mmDMA6_QM_CQ_CTL_STS_4 0x5C8210 + +#define mmDMA6_QM_CQ_IFIFO_CNT_0 0x5C8214 + +#define mmDMA6_QM_CQ_IFIFO_CNT_1 0x5C8218 + +#define mmDMA6_QM_CQ_IFIFO_CNT_2 0x5C821C + +#define mmDMA6_QM_CQ_IFIFO_CNT_3 0x5C8220 + +#define mmDMA6_QM_CQ_IFIFO_CNT_4 0x5C8224 + +#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_0 0x5C8228 + +#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_1 0x5C822C + +#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_2 0x5C8230 + +#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_3 0x5C8234 + +#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_4 0x5C8238 + +#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_0 0x5C823C + +#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_1 0x5C8240 + +#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_2 0x5C8244 + +#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_3 0x5C8248 + +#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_4 0x5C824C + +#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_0 0x5C8250 + +#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_1 0x5C8254 + +#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_2 0x5C8258 + +#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_3 0x5C825C + +#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_4 0x5C8260 + +#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_0 0x5C8264 + +#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_1 0x5C8268 + +#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_2 0x5C826C + +#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_3 0x5C8270 + +#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_4 0x5C8274 + +#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_0 0x5C8278 + +#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_1 0x5C827C + +#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_2 0x5C8280 + +#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_3 0x5C8284 + +#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_4 0x5C8288 + +#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_0 0x5C828C + +#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_1 0x5C8290 + +#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_2 0x5C8294 + +#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_3 0x5C8298 + +#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_4 0x5C829C + +#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_0 0x5C82A0 + +#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_1 0x5C82A4 + +#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_2 0x5C82A8 + +#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_3 0x5C82AC + +#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_4 0x5C82B0 + +#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_0 0x5C82B4 + +#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_1 0x5C82B8 + +#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_2 0x5C82BC + +#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_3 0x5C82C0 + +#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_4 0x5C82C4 + +#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_0 0x5C82C8 + +#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_1 0x5C82CC + +#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_2 0x5C82D0 + +#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_3 0x5C82D4 + +#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_4 0x5C82D8 + +#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5C82E0 + +#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5C82E4 + +#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5C82E8 + +#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5C82EC + +#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5C82F0 + +#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5C82F4 + +#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5C82F8 + +#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5C82FC + +#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x5C8300 + +#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x5C8304 + +#define mmDMA6_QM_CP_FENCE0_RDATA_0 0x5C8308 + +#define mmDMA6_QM_CP_FENCE0_RDATA_1 0x5C830C + +#define mmDMA6_QM_CP_FENCE0_RDATA_2 0x5C8310 + +#define mmDMA6_QM_CP_FENCE0_RDATA_3 0x5C8314 + +#define mmDMA6_QM_CP_FENCE0_RDATA_4 0x5C8318 + +#define mmDMA6_QM_CP_FENCE1_RDATA_0 0x5C831C + +#define mmDMA6_QM_CP_FENCE1_RDATA_1 0x5C8320 + +#define mmDMA6_QM_CP_FENCE1_RDATA_2 0x5C8324 + +#define mmDMA6_QM_CP_FENCE1_RDATA_3 0x5C8328 + +#define mmDMA6_QM_CP_FENCE1_RDATA_4 0x5C832C + +#define mmDMA6_QM_CP_FENCE2_RDATA_0 0x5C8330 + +#define mmDMA6_QM_CP_FENCE2_RDATA_1 0x5C8334 + +#define mmDMA6_QM_CP_FENCE2_RDATA_2 0x5C8338 + +#define mmDMA6_QM_CP_FENCE2_RDATA_3 0x5C833C + +#define mmDMA6_QM_CP_FENCE2_RDATA_4 0x5C8340 + +#define mmDMA6_QM_CP_FENCE3_RDATA_0 0x5C8344 + +#define mmDMA6_QM_CP_FENCE3_RDATA_1 0x5C8348 + +#define mmDMA6_QM_CP_FENCE3_RDATA_2 0x5C834C + +#define mmDMA6_QM_CP_FENCE3_RDATA_3 0x5C8350 + +#define mmDMA6_QM_CP_FENCE3_RDATA_4 0x5C8354 + +#define mmDMA6_QM_CP_FENCE0_CNT_0 0x5C8358 + +#define mmDMA6_QM_CP_FENCE0_CNT_1 0x5C835C + +#define mmDMA6_QM_CP_FENCE0_CNT_2 0x5C8360 + +#define mmDMA6_QM_CP_FENCE0_CNT_3 0x5C8364 + +#define mmDMA6_QM_CP_FENCE0_CNT_4 0x5C8368 + +#define mmDMA6_QM_CP_FENCE1_CNT_0 0x5C836C + +#define mmDMA6_QM_CP_FENCE1_CNT_1 0x5C8370 + +#define mmDMA6_QM_CP_FENCE1_CNT_2 0x5C8374 + +#define mmDMA6_QM_CP_FENCE1_CNT_3 0x5C8378 + +#define mmDMA6_QM_CP_FENCE1_CNT_4 0x5C837C + +#define mmDMA6_QM_CP_FENCE2_CNT_0 0x5C8380 + +#define mmDMA6_QM_CP_FENCE2_CNT_1 0x5C8384 + +#define mmDMA6_QM_CP_FENCE2_CNT_2 0x5C8388 + +#define mmDMA6_QM_CP_FENCE2_CNT_3 0x5C838C + +#define mmDMA6_QM_CP_FENCE2_CNT_4 0x5C8390 + +#define mmDMA6_QM_CP_FENCE3_CNT_0 0x5C8394 + +#define mmDMA6_QM_CP_FENCE3_CNT_1 0x5C8398 + +#define mmDMA6_QM_CP_FENCE3_CNT_2 0x5C839C + +#define mmDMA6_QM_CP_FENCE3_CNT_3 0x5C83A0 + +#define mmDMA6_QM_CP_FENCE3_CNT_4 0x5C83A4 + +#define mmDMA6_QM_CP_STS_0 0x5C83A8 + +#define mmDMA6_QM_CP_STS_1 0x5C83AC + +#define mmDMA6_QM_CP_STS_2 0x5C83B0 + +#define mmDMA6_QM_CP_STS_3 0x5C83B4 + +#define mmDMA6_QM_CP_STS_4 0x5C83B8 + +#define mmDMA6_QM_CP_CURRENT_INST_LO_0 0x5C83BC + +#define mmDMA6_QM_CP_CURRENT_INST_LO_1 0x5C83C0 + +#define mmDMA6_QM_CP_CURRENT_INST_LO_2 0x5C83C4 + +#define mmDMA6_QM_CP_CURRENT_INST_LO_3 0x5C83C8 + +#define mmDMA6_QM_CP_CURRENT_INST_LO_4 0x5C83CC + +#define mmDMA6_QM_CP_CURRENT_INST_HI_0 0x5C83D0 + +#define mmDMA6_QM_CP_CURRENT_INST_HI_1 0x5C83D4 + +#define mmDMA6_QM_CP_CURRENT_INST_HI_2 0x5C83D8 + +#define mmDMA6_QM_CP_CURRENT_INST_HI_3 0x5C83DC + +#define mmDMA6_QM_CP_CURRENT_INST_HI_4 0x5C83E0 + +#define mmDMA6_QM_CP_BARRIER_CFG_0 0x5C83F4 + +#define mmDMA6_QM_CP_BARRIER_CFG_1 0x5C83F8 + +#define mmDMA6_QM_CP_BARRIER_CFG_2 0x5C83FC + +#define mmDMA6_QM_CP_BARRIER_CFG_3 0x5C8400 + +#define mmDMA6_QM_CP_BARRIER_CFG_4 0x5C8404 + +#define mmDMA6_QM_CP_DBG_0_0 0x5C8408 + +#define mmDMA6_QM_CP_DBG_0_1 0x5C840C + +#define mmDMA6_QM_CP_DBG_0_2 0x5C8410 + +#define mmDMA6_QM_CP_DBG_0_3 0x5C8414 + +#define mmDMA6_QM_CP_DBG_0_4 0x5C8418 + +#define mmDMA6_QM_CP_ARUSER_31_11_0 0x5C841C + +#define mmDMA6_QM_CP_ARUSER_31_11_1 0x5C8420 + +#define mmDMA6_QM_CP_ARUSER_31_11_2 0x5C8424 + +#define mmDMA6_QM_CP_ARUSER_31_11_3 0x5C8428 + +#define mmDMA6_QM_CP_ARUSER_31_11_4 0x5C842C + +#define mmDMA6_QM_CP_AWUSER_31_11_0 0x5C8430 + +#define mmDMA6_QM_CP_AWUSER_31_11_1 0x5C8434 + +#define mmDMA6_QM_CP_AWUSER_31_11_2 0x5C8438 + +#define mmDMA6_QM_CP_AWUSER_31_11_3 0x5C843C + +#define mmDMA6_QM_CP_AWUSER_31_11_4 0x5C8440 + +#define mmDMA6_QM_ARB_CFG_0 0x5C8A00 + +#define mmDMA6_QM_ARB_CHOISE_Q_PUSH 0x5C8A04 + +#define mmDMA6_QM_ARB_WRR_WEIGHT_0 0x5C8A08 + +#define mmDMA6_QM_ARB_WRR_WEIGHT_1 0x5C8A0C + +#define mmDMA6_QM_ARB_WRR_WEIGHT_2 0x5C8A10 + +#define mmDMA6_QM_ARB_WRR_WEIGHT_3 0x5C8A14 + +#define mmDMA6_QM_ARB_CFG_1 0x5C8A18 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_0 0x5C8A20 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_1 0x5C8A24 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_2 0x5C8A28 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_3 0x5C8A2C + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_4 0x5C8A30 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_5 0x5C8A34 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_6 0x5C8A38 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_7 0x5C8A3C + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_8 0x5C8A40 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_9 0x5C8A44 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_10 0x5C8A48 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_11 0x5C8A4C + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_12 0x5C8A50 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_13 0x5C8A54 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_14 0x5C8A58 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_15 0x5C8A5C + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_16 0x5C8A60 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_17 0x5C8A64 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_18 0x5C8A68 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_19 0x5C8A6C + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_20 0x5C8A70 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_21 0x5C8A74 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_22 0x5C8A78 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_23 0x5C8A7C + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_24 0x5C8A80 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_25 0x5C8A84 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_26 0x5C8A88 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_27 0x5C8A8C + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_28 0x5C8A90 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_29 0x5C8A94 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_30 0x5C8A98 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_31 0x5C8A9C + +#define mmDMA6_QM_ARB_MST_CRED_INC 0x5C8AA0 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x5C8AA4 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x5C8AA8 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x5C8AAC + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x5C8AB0 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x5C8AB4 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x5C8AB8 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x5C8ABC + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x5C8AC0 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x5C8AC4 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x5C8AC8 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x5C8ACC + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x5C8AD0 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x5C8AD4 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x5C8AD8 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x5C8ADC + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x5C8AE0 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x5C8AE4 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x5C8AE8 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x5C8AEC + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x5C8AF0 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x5C8AF4 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x5C8AF8 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x5C8AFC + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x5C8B00 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x5C8B04 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x5C8B08 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x5C8B0C + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x5C8B10 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x5C8B14 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x5C8B18 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x5C8B1C + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x5C8B20 + +#define mmDMA6_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x5C8B28 + +#define mmDMA6_QM_ARB_MST_SLAVE_EN 0x5C8B2C + +#define mmDMA6_QM_ARB_MST_QUIET_PER 0x5C8B34 + +#define mmDMA6_QM_ARB_SLV_CHOISE_WDT 0x5C8B38 + +#define mmDMA6_QM_ARB_SLV_ID 0x5C8B3C + +#define mmDMA6_QM_ARB_MSG_MAX_INFLIGHT 0x5C8B44 + +#define mmDMA6_QM_ARB_MSG_AWUSER_31_11 0x5C8B48 + +#define mmDMA6_QM_ARB_MSG_AWUSER_SEC_PROP 0x5C8B4C + +#define mmDMA6_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x5C8B50 + +#define mmDMA6_QM_ARB_BASE_LO 0x5C8B54 + +#define mmDMA6_QM_ARB_BASE_HI 0x5C8B58 + +#define mmDMA6_QM_ARB_STATE_STS 0x5C8B80 + +#define mmDMA6_QM_ARB_CHOISE_FULLNESS_STS 0x5C8B84 + +#define mmDMA6_QM_ARB_MSG_STS 0x5C8B88 + +#define mmDMA6_QM_ARB_SLV_CHOISE_Q_HEAD 0x5C8B8C + +#define mmDMA6_QM_ARB_ERR_CAUSE 0x5C8B9C + +#define mmDMA6_QM_ARB_ERR_MSG_EN 0x5C8BA0 + +#define mmDMA6_QM_ARB_ERR_STS_DRP 0x5C8BA8 + +#define mmDMA6_QM_ARB_MST_CRED_STS_0 0x5C8BB0 + +#define mmDMA6_QM_ARB_MST_CRED_STS_1 0x5C8BB4 + +#define mmDMA6_QM_ARB_MST_CRED_STS_2 0x5C8BB8 + +#define mmDMA6_QM_ARB_MST_CRED_STS_3 0x5C8BBC + +#define mmDMA6_QM_ARB_MST_CRED_STS_4 0x5C8BC0 + +#define mmDMA6_QM_ARB_MST_CRED_STS_5 0x5C8BC4 + +#define mmDMA6_QM_ARB_MST_CRED_STS_6 0x5C8BC8 + +#define mmDMA6_QM_ARB_MST_CRED_STS_7 0x5C8BCC + +#define mmDMA6_QM_ARB_MST_CRED_STS_8 0x5C8BD0 + +#define mmDMA6_QM_ARB_MST_CRED_STS_9 0x5C8BD4 + +#define mmDMA6_QM_ARB_MST_CRED_STS_10 0x5C8BD8 + +#define mmDMA6_QM_ARB_MST_CRED_STS_11 0x5C8BDC + +#define mmDMA6_QM_ARB_MST_CRED_STS_12 0x5C8BE0 + +#define mmDMA6_QM_ARB_MST_CRED_STS_13 0x5C8BE4 + +#define mmDMA6_QM_ARB_MST_CRED_STS_14 0x5C8BE8 + +#define mmDMA6_QM_ARB_MST_CRED_STS_15 0x5C8BEC + +#define mmDMA6_QM_ARB_MST_CRED_STS_16 0x5C8BF0 + +#define mmDMA6_QM_ARB_MST_CRED_STS_17 0x5C8BF4 + +#define mmDMA6_QM_ARB_MST_CRED_STS_18 0x5C8BF8 + +#define mmDMA6_QM_ARB_MST_CRED_STS_19 0x5C8BFC + +#define mmDMA6_QM_ARB_MST_CRED_STS_20 0x5C8C00 + +#define mmDMA6_QM_ARB_MST_CRED_STS_21 0x5C8C04 + +#define mmDMA6_QM_ARB_MST_CRED_STS_22 0x5C8C08 + +#define mmDMA6_QM_ARB_MST_CRED_STS_23 0x5C8C0C + +#define mmDMA6_QM_ARB_MST_CRED_STS_24 0x5C8C10 + +#define mmDMA6_QM_ARB_MST_CRED_STS_25 0x5C8C14 + +#define mmDMA6_QM_ARB_MST_CRED_STS_26 0x5C8C18 + +#define mmDMA6_QM_ARB_MST_CRED_STS_27 0x5C8C1C + +#define mmDMA6_QM_ARB_MST_CRED_STS_28 0x5C8C20 + +#define mmDMA6_QM_ARB_MST_CRED_STS_29 0x5C8C24 + +#define mmDMA6_QM_ARB_MST_CRED_STS_30 0x5C8C28 + +#define mmDMA6_QM_ARB_MST_CRED_STS_31 0x5C8C2C + +#define mmDMA6_QM_CGM_CFG 0x5C8C70 + +#define mmDMA6_QM_CGM_STS 0x5C8C74 + +#define mmDMA6_QM_CGM_CFG1 0x5C8C78 + +#define mmDMA6_QM_LOCAL_RANGE_BASE 0x5C8C80 + +#define mmDMA6_QM_LOCAL_RANGE_SIZE 0x5C8C84 + +#define mmDMA6_QM_CSMR_STRICT_PRIO_CFG 0x5C8C90 + +#define mmDMA6_QM_HBW_RD_RATE_LIM_CFG_1 0x5C8C94 + +#define mmDMA6_QM_LBW_WR_RATE_LIM_CFG_0 0x5C8C98 + +#define mmDMA6_QM_LBW_WR_RATE_LIM_CFG_1 0x5C8C9C + +#define mmDMA6_QM_HBW_RD_RATE_LIM_CFG_0 0x5C8CA0 + +#define mmDMA6_QM_GLBL_AXCACHE 0x5C8CA4 + +#define mmDMA6_QM_IND_GW_APB_CFG 0x5C8CB0 + +#define mmDMA6_QM_IND_GW_APB_WDATA 0x5C8CB4 + +#define mmDMA6_QM_IND_GW_APB_RDATA 0x5C8CB8 + +#define mmDMA6_QM_IND_GW_APB_STATUS 0x5C8CBC + +#define mmDMA6_QM_GLBL_ERR_ADDR_LO 0x5C8CD0 + +#define mmDMA6_QM_GLBL_ERR_ADDR_HI 0x5C8CD4 + +#define mmDMA6_QM_GLBL_ERR_WDATA 0x5C8CD8 + +#define mmDMA6_QM_GLBL_MEM_INIT_BUSY 0x5C8D00 + +#endif /* ASIC_REG_DMA6_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma7_core_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma7_core_regs.h new file mode 100644 index 000000000000..8dd705d20195 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma7_core_regs.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA7_CORE_REGS_H_ +#define ASIC_REG_DMA7_CORE_REGS_H_ + +/* + ***************************************** + * DMA7_CORE (Prototype: DMA_CORE) + ***************************************** + */ + +#define mmDMA7_CORE_CFG_0 0x5E0000 + +#define mmDMA7_CORE_CFG_1 0x5E0004 + +#define mmDMA7_CORE_LBW_MAX_OUTSTAND 0x5E0008 + +#define mmDMA7_CORE_SRC_BASE_LO 0x5E0014 + +#define mmDMA7_CORE_SRC_BASE_HI 0x5E0018 + +#define mmDMA7_CORE_DST_BASE_LO 0x5E001C + +#define mmDMA7_CORE_DST_BASE_HI 0x5E0020 + +#define mmDMA7_CORE_SRC_TSIZE_1 0x5E002C + +#define mmDMA7_CORE_SRC_STRIDE_1 0x5E0030 + +#define mmDMA7_CORE_SRC_TSIZE_2 0x5E0034 + +#define mmDMA7_CORE_SRC_STRIDE_2 0x5E0038 + +#define mmDMA7_CORE_SRC_TSIZE_3 0x5E003C + +#define mmDMA7_CORE_SRC_STRIDE_3 0x5E0040 + +#define mmDMA7_CORE_SRC_TSIZE_4 0x5E0044 + +#define mmDMA7_CORE_SRC_STRIDE_4 0x5E0048 + +#define mmDMA7_CORE_SRC_TSIZE_0 0x5E004C + +#define mmDMA7_CORE_DST_TSIZE_1 0x5E0054 + +#define mmDMA7_CORE_DST_STRIDE_1 0x5E0058 + +#define mmDMA7_CORE_DST_TSIZE_2 0x5E005C + +#define mmDMA7_CORE_DST_STRIDE_2 0x5E0060 + +#define mmDMA7_CORE_DST_TSIZE_3 0x5E0064 + +#define mmDMA7_CORE_DST_STRIDE_3 0x5E0068 + +#define mmDMA7_CORE_DST_TSIZE_4 0x5E006C + +#define mmDMA7_CORE_DST_STRIDE_4 0x5E0070 + +#define mmDMA7_CORE_DST_TSIZE_0 0x5E0074 + +#define mmDMA7_CORE_COMMIT 0x5E0078 + +#define mmDMA7_CORE_WR_COMP_WDATA 0x5E007C + +#define mmDMA7_CORE_WR_COMP_ADDR_LO 0x5E0080 + +#define mmDMA7_CORE_WR_COMP_ADDR_HI 0x5E0084 + +#define mmDMA7_CORE_WR_COMP_AWUSER_31_11 0x5E0088 + +#define mmDMA7_CORE_TE_NUMROWS 0x5E0094 + +#define mmDMA7_CORE_PROT 0x5E00B8 + +#define mmDMA7_CORE_SECURE_PROPS 0x5E00F0 + +#define mmDMA7_CORE_NON_SECURE_PROPS 0x5E00F4 + +#define mmDMA7_CORE_RD_MAX_OUTSTAND 0x5E0100 + +#define mmDMA7_CORE_RD_MAX_SIZE 0x5E0104 + +#define mmDMA7_CORE_RD_ARCACHE 0x5E0108 + +#define mmDMA7_CORE_RD_ARUSER_31_11 0x5E0110 + +#define mmDMA7_CORE_RD_INFLIGHTS 0x5E0114 + +#define mmDMA7_CORE_WR_MAX_OUTSTAND 0x5E0120 + +#define mmDMA7_CORE_WR_MAX_AWID 0x5E0124 + +#define mmDMA7_CORE_WR_AWCACHE 0x5E0128 + +#define mmDMA7_CORE_WR_AWUSER_31_11 0x5E0130 + +#define mmDMA7_CORE_WR_INFLIGHTS 0x5E0134 + +#define mmDMA7_CORE_RD_RATE_LIM_CFG_0 0x5E0150 + +#define mmDMA7_CORE_RD_RATE_LIM_CFG_1 0x5E0154 + +#define mmDMA7_CORE_WR_RATE_LIM_CFG_0 0x5E0158 + +#define mmDMA7_CORE_WR_RATE_LIM_CFG_1 0x5E015C + +#define mmDMA7_CORE_ERR_CFG 0x5E0160 + +#define mmDMA7_CORE_ERR_CAUSE 0x5E0164 + +#define mmDMA7_CORE_ERRMSG_ADDR_LO 0x5E0170 + +#define mmDMA7_CORE_ERRMSG_ADDR_HI 0x5E0174 + +#define mmDMA7_CORE_ERRMSG_WDATA 0x5E0178 + +#define mmDMA7_CORE_STS0 0x5E0190 + +#define mmDMA7_CORE_STS1 0x5E0194 + +#define mmDMA7_CORE_RD_DBGMEM_ADD 0x5E0200 + +#define mmDMA7_CORE_RD_DBGMEM_DATA_WR 0x5E0204 + +#define mmDMA7_CORE_RD_DBGMEM_DATA_RD 0x5E0208 + +#define mmDMA7_CORE_RD_DBGMEM_CTRL 0x5E020C + +#define mmDMA7_CORE_RD_DBGMEM_RC 0x5E0210 + +#define mmDMA7_CORE_DBG_HBW_AXI_AR_CNT 0x5E0220 + +#define mmDMA7_CORE_DBG_HBW_AXI_AW_CNT 0x5E0224 + +#define mmDMA7_CORE_DBG_LBW_AXI_AW_CNT 0x5E0228 + +#define mmDMA7_CORE_DBG_DESC_CNT 0x5E022C + +#define mmDMA7_CORE_DBG_STS 0x5E0230 + +#define mmDMA7_CORE_DBG_RD_DESC_ID 0x5E0234 + +#define mmDMA7_CORE_DBG_WR_DESC_ID 0x5E0238 + +#endif /* ASIC_REG_DMA7_CORE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma7_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma7_qm_regs.h new file mode 100644 index 000000000000..d6c631f63e3e --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma7_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA7_QM_REGS_H_ +#define ASIC_REG_DMA7_QM_REGS_H_ + +/* + ***************************************** + * DMA7_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA7_QM_GLBL_CFG0 0x5E8000 + +#define mmDMA7_QM_GLBL_CFG1 0x5E8004 + +#define mmDMA7_QM_GLBL_PROT 0x5E8008 + +#define mmDMA7_QM_GLBL_ERR_CFG 0x5E800C + +#define mmDMA7_QM_GLBL_SECURE_PROPS_0 0x5E8010 + +#define mmDMA7_QM_GLBL_SECURE_PROPS_1 0x5E8014 + +#define mmDMA7_QM_GLBL_SECURE_PROPS_2 0x5E8018 + +#define mmDMA7_QM_GLBL_SECURE_PROPS_3 0x5E801C + +#define mmDMA7_QM_GLBL_SECURE_PROPS_4 0x5E8020 + +#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_0 0x5E8024 + +#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_1 0x5E8028 + +#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_2 0x5E802C + +#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_3 0x5E8030 + +#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_4 0x5E8034 + +#define mmDMA7_QM_GLBL_STS0 0x5E8038 + +#define mmDMA7_QM_GLBL_STS1_0 0x5E8040 + +#define mmDMA7_QM_GLBL_STS1_1 0x5E8044 + +#define mmDMA7_QM_GLBL_STS1_2 0x5E8048 + +#define mmDMA7_QM_GLBL_STS1_3 0x5E804C + +#define mmDMA7_QM_GLBL_STS1_4 0x5E8050 + +#define mmDMA7_QM_GLBL_MSG_EN_0 0x5E8054 + +#define mmDMA7_QM_GLBL_MSG_EN_1 0x5E8058 + +#define mmDMA7_QM_GLBL_MSG_EN_2 0x5E805C + +#define mmDMA7_QM_GLBL_MSG_EN_3 0x5E8060 + +#define mmDMA7_QM_GLBL_MSG_EN_4 0x5E8068 + +#define mmDMA7_QM_PQ_BASE_LO_0 0x5E8070 + +#define mmDMA7_QM_PQ_BASE_LO_1 0x5E8074 + +#define mmDMA7_QM_PQ_BASE_LO_2 0x5E8078 + +#define mmDMA7_QM_PQ_BASE_LO_3 0x5E807C + +#define mmDMA7_QM_PQ_BASE_HI_0 0x5E8080 + +#define mmDMA7_QM_PQ_BASE_HI_1 0x5E8084 + +#define mmDMA7_QM_PQ_BASE_HI_2 0x5E8088 + +#define mmDMA7_QM_PQ_BASE_HI_3 0x5E808C + +#define mmDMA7_QM_PQ_SIZE_0 0x5E8090 + +#define mmDMA7_QM_PQ_SIZE_1 0x5E8094 + +#define mmDMA7_QM_PQ_SIZE_2 0x5E8098 + +#define mmDMA7_QM_PQ_SIZE_3 0x5E809C + +#define mmDMA7_QM_PQ_PI_0 0x5E80A0 + +#define mmDMA7_QM_PQ_PI_1 0x5E80A4 + +#define mmDMA7_QM_PQ_PI_2 0x5E80A8 + +#define mmDMA7_QM_PQ_PI_3 0x5E80AC + +#define mmDMA7_QM_PQ_CI_0 0x5E80B0 + +#define mmDMA7_QM_PQ_CI_1 0x5E80B4 + +#define mmDMA7_QM_PQ_CI_2 0x5E80B8 + +#define mmDMA7_QM_PQ_CI_3 0x5E80BC + +#define mmDMA7_QM_PQ_CFG0_0 0x5E80C0 + +#define mmDMA7_QM_PQ_CFG0_1 0x5E80C4 + +#define mmDMA7_QM_PQ_CFG0_2 0x5E80C8 + +#define mmDMA7_QM_PQ_CFG0_3 0x5E80CC + +#define mmDMA7_QM_PQ_CFG1_0 0x5E80D0 + +#define mmDMA7_QM_PQ_CFG1_1 0x5E80D4 + +#define mmDMA7_QM_PQ_CFG1_2 0x5E80D8 + +#define mmDMA7_QM_PQ_CFG1_3 0x5E80DC + +#define mmDMA7_QM_PQ_ARUSER_31_11_0 0x5E80E0 + +#define mmDMA7_QM_PQ_ARUSER_31_11_1 0x5E80E4 + +#define mmDMA7_QM_PQ_ARUSER_31_11_2 0x5E80E8 + +#define mmDMA7_QM_PQ_ARUSER_31_11_3 0x5E80EC + +#define mmDMA7_QM_PQ_STS0_0 0x5E80F0 + +#define mmDMA7_QM_PQ_STS0_1 0x5E80F4 + +#define mmDMA7_QM_PQ_STS0_2 0x5E80F8 + +#define mmDMA7_QM_PQ_STS0_3 0x5E80FC + +#define mmDMA7_QM_PQ_STS1_0 0x5E8100 + +#define mmDMA7_QM_PQ_STS1_1 0x5E8104 + +#define mmDMA7_QM_PQ_STS1_2 0x5E8108 + +#define mmDMA7_QM_PQ_STS1_3 0x5E810C + +#define mmDMA7_QM_CQ_CFG0_0 0x5E8110 + +#define mmDMA7_QM_CQ_CFG0_1 0x5E8114 + +#define mmDMA7_QM_CQ_CFG0_2 0x5E8118 + +#define mmDMA7_QM_CQ_CFG0_3 0x5E811C + +#define mmDMA7_QM_CQ_CFG0_4 0x5E8120 + +#define mmDMA7_QM_CQ_CFG1_0 0x5E8124 + +#define mmDMA7_QM_CQ_CFG1_1 0x5E8128 + +#define mmDMA7_QM_CQ_CFG1_2 0x5E812C + +#define mmDMA7_QM_CQ_CFG1_3 0x5E8130 + +#define mmDMA7_QM_CQ_CFG1_4 0x5E8134 + +#define mmDMA7_QM_CQ_ARUSER_31_11_0 0x5E8138 + +#define mmDMA7_QM_CQ_ARUSER_31_11_1 0x5E813C + +#define mmDMA7_QM_CQ_ARUSER_31_11_2 0x5E8140 + +#define mmDMA7_QM_CQ_ARUSER_31_11_3 0x5E8144 + +#define mmDMA7_QM_CQ_ARUSER_31_11_4 0x5E8148 + +#define mmDMA7_QM_CQ_STS0_0 0x5E814C + +#define mmDMA7_QM_CQ_STS0_1 0x5E8150 + +#define mmDMA7_QM_CQ_STS0_2 0x5E8154 + +#define mmDMA7_QM_CQ_STS0_3 0x5E8158 + +#define mmDMA7_QM_CQ_STS0_4 0x5E815C + +#define mmDMA7_QM_CQ_STS1_0 0x5E8160 + +#define mmDMA7_QM_CQ_STS1_1 0x5E8164 + +#define mmDMA7_QM_CQ_STS1_2 0x5E8168 + +#define mmDMA7_QM_CQ_STS1_3 0x5E816C + +#define mmDMA7_QM_CQ_STS1_4 0x5E8170 + +#define mmDMA7_QM_CQ_PTR_LO_0 0x5E8174 + +#define mmDMA7_QM_CQ_PTR_HI_0 0x5E8178 + +#define mmDMA7_QM_CQ_TSIZE_0 0x5E817C + +#define mmDMA7_QM_CQ_CTL_0 0x5E8180 + +#define mmDMA7_QM_CQ_PTR_LO_1 0x5E8184 + +#define mmDMA7_QM_CQ_PTR_HI_1 0x5E8188 + +#define mmDMA7_QM_CQ_TSIZE_1 0x5E818C + +#define mmDMA7_QM_CQ_CTL_1 0x5E8190 + +#define mmDMA7_QM_CQ_PTR_LO_2 0x5E8194 + +#define mmDMA7_QM_CQ_PTR_HI_2 0x5E8198 + +#define mmDMA7_QM_CQ_TSIZE_2 0x5E819C + +#define mmDMA7_QM_CQ_CTL_2 0x5E81A0 + +#define mmDMA7_QM_CQ_PTR_LO_3 0x5E81A4 + +#define mmDMA7_QM_CQ_PTR_HI_3 0x5E81A8 + +#define mmDMA7_QM_CQ_TSIZE_3 0x5E81AC + +#define mmDMA7_QM_CQ_CTL_3 0x5E81B0 + +#define mmDMA7_QM_CQ_PTR_LO_4 0x5E81B4 + +#define mmDMA7_QM_CQ_PTR_HI_4 0x5E81B8 + +#define mmDMA7_QM_CQ_TSIZE_4 0x5E81BC + +#define mmDMA7_QM_CQ_CTL_4 0x5E81C0 + +#define mmDMA7_QM_CQ_PTR_LO_STS_0 0x5E81C4 + +#define mmDMA7_QM_CQ_PTR_LO_STS_1 0x5E81C8 + +#define mmDMA7_QM_CQ_PTR_LO_STS_2 0x5E81CC + +#define mmDMA7_QM_CQ_PTR_LO_STS_3 0x5E81D0 + +#define mmDMA7_QM_CQ_PTR_LO_STS_4 0x5E81D4 + +#define mmDMA7_QM_CQ_PTR_HI_STS_0 0x5E81D8 + +#define mmDMA7_QM_CQ_PTR_HI_STS_1 0x5E81DC + +#define mmDMA7_QM_CQ_PTR_HI_STS_2 0x5E81E0 + +#define mmDMA7_QM_CQ_PTR_HI_STS_3 0x5E81E4 + +#define mmDMA7_QM_CQ_PTR_HI_STS_4 0x5E81E8 + +#define mmDMA7_QM_CQ_TSIZE_STS_0 0x5E81EC + +#define mmDMA7_QM_CQ_TSIZE_STS_1 0x5E81F0 + +#define mmDMA7_QM_CQ_TSIZE_STS_2 0x5E81F4 + +#define mmDMA7_QM_CQ_TSIZE_STS_3 0x5E81F8 + +#define mmDMA7_QM_CQ_TSIZE_STS_4 0x5E81FC + +#define mmDMA7_QM_CQ_CTL_STS_0 0x5E8200 + +#define mmDMA7_QM_CQ_CTL_STS_1 0x5E8204 + +#define mmDMA7_QM_CQ_CTL_STS_2 0x5E8208 + +#define mmDMA7_QM_CQ_CTL_STS_3 0x5E820C + +#define mmDMA7_QM_CQ_CTL_STS_4 0x5E8210 + +#define mmDMA7_QM_CQ_IFIFO_CNT_0 0x5E8214 + +#define mmDMA7_QM_CQ_IFIFO_CNT_1 0x5E8218 + +#define mmDMA7_QM_CQ_IFIFO_CNT_2 0x5E821C + +#define mmDMA7_QM_CQ_IFIFO_CNT_3 0x5E8220 + +#define mmDMA7_QM_CQ_IFIFO_CNT_4 0x5E8224 + +#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_0 0x5E8228 + +#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_1 0x5E822C + +#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_2 0x5E8230 + +#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_3 0x5E8234 + +#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_4 0x5E8238 + +#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_0 0x5E823C + +#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_1 0x5E8240 + +#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_2 0x5E8244 + +#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_3 0x5E8248 + +#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_4 0x5E824C + +#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_0 0x5E8250 + +#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_1 0x5E8254 + +#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_2 0x5E8258 + +#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_3 0x5E825C + +#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_4 0x5E8260 + +#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_0 0x5E8264 + +#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_1 0x5E8268 + +#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_2 0x5E826C + +#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_3 0x5E8270 + +#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_4 0x5E8274 + +#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_0 0x5E8278 + +#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_1 0x5E827C + +#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_2 0x5E8280 + +#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_3 0x5E8284 + +#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_4 0x5E8288 + +#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_0 0x5E828C + +#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_1 0x5E8290 + +#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_2 0x5E8294 + +#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_3 0x5E8298 + +#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_4 0x5E829C + +#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_0 0x5E82A0 + +#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_1 0x5E82A4 + +#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_2 0x5E82A8 + +#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_3 0x5E82AC + +#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_4 0x5E82B0 + +#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_0 0x5E82B4 + +#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_1 0x5E82B8 + +#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_2 0x5E82BC + +#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_3 0x5E82C0 + +#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_4 0x5E82C4 + +#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_0 0x5E82C8 + +#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_1 0x5E82CC + +#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_2 0x5E82D0 + +#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_3 0x5E82D4 + +#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_4 0x5E82D8 + +#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5E82E0 + +#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5E82E4 + +#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5E82E8 + +#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5E82EC + +#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5E82F0 + +#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5E82F4 + +#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5E82F8 + +#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5E82FC + +#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x5E8300 + +#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x5E8304 + +#define mmDMA7_QM_CP_FENCE0_RDATA_0 0x5E8308 + +#define mmDMA7_QM_CP_FENCE0_RDATA_1 0x5E830C + +#define mmDMA7_QM_CP_FENCE0_RDATA_2 0x5E8310 + +#define mmDMA7_QM_CP_FENCE0_RDATA_3 0x5E8314 + +#define mmDMA7_QM_CP_FENCE0_RDATA_4 0x5E8318 + +#define mmDMA7_QM_CP_FENCE1_RDATA_0 0x5E831C + +#define mmDMA7_QM_CP_FENCE1_RDATA_1 0x5E8320 + +#define mmDMA7_QM_CP_FENCE1_RDATA_2 0x5E8324 + +#define mmDMA7_QM_CP_FENCE1_RDATA_3 0x5E8328 + +#define mmDMA7_QM_CP_FENCE1_RDATA_4 0x5E832C + +#define mmDMA7_QM_CP_FENCE2_RDATA_0 0x5E8330 + +#define mmDMA7_QM_CP_FENCE2_RDATA_1 0x5E8334 + +#define mmDMA7_QM_CP_FENCE2_RDATA_2 0x5E8338 + +#define mmDMA7_QM_CP_FENCE2_RDATA_3 0x5E833C + +#define mmDMA7_QM_CP_FENCE2_RDATA_4 0x5E8340 + +#define mmDMA7_QM_CP_FENCE3_RDATA_0 0x5E8344 + +#define mmDMA7_QM_CP_FENCE3_RDATA_1 0x5E8348 + +#define mmDMA7_QM_CP_FENCE3_RDATA_2 0x5E834C + +#define mmDMA7_QM_CP_FENCE3_RDATA_3 0x5E8350 + +#define mmDMA7_QM_CP_FENCE3_RDATA_4 0x5E8354 + +#define mmDMA7_QM_CP_FENCE0_CNT_0 0x5E8358 + +#define mmDMA7_QM_CP_FENCE0_CNT_1 0x5E835C + +#define mmDMA7_QM_CP_FENCE0_CNT_2 0x5E8360 + +#define mmDMA7_QM_CP_FENCE0_CNT_3 0x5E8364 + +#define mmDMA7_QM_CP_FENCE0_CNT_4 0x5E8368 + +#define mmDMA7_QM_CP_FENCE1_CNT_0 0x5E836C + +#define mmDMA7_QM_CP_FENCE1_CNT_1 0x5E8370 + +#define mmDMA7_QM_CP_FENCE1_CNT_2 0x5E8374 + +#define mmDMA7_QM_CP_FENCE1_CNT_3 0x5E8378 + +#define mmDMA7_QM_CP_FENCE1_CNT_4 0x5E837C + +#define mmDMA7_QM_CP_FENCE2_CNT_0 0x5E8380 + +#define mmDMA7_QM_CP_FENCE2_CNT_1 0x5E8384 + +#define mmDMA7_QM_CP_FENCE2_CNT_2 0x5E8388 + +#define mmDMA7_QM_CP_FENCE2_CNT_3 0x5E838C + +#define mmDMA7_QM_CP_FENCE2_CNT_4 0x5E8390 + +#define mmDMA7_QM_CP_FENCE3_CNT_0 0x5E8394 + +#define mmDMA7_QM_CP_FENCE3_CNT_1 0x5E8398 + +#define mmDMA7_QM_CP_FENCE3_CNT_2 0x5E839C + +#define mmDMA7_QM_CP_FENCE3_CNT_3 0x5E83A0 + +#define mmDMA7_QM_CP_FENCE3_CNT_4 0x5E83A4 + +#define mmDMA7_QM_CP_STS_0 0x5E83A8 + +#define mmDMA7_QM_CP_STS_1 0x5E83AC + +#define mmDMA7_QM_CP_STS_2 0x5E83B0 + +#define mmDMA7_QM_CP_STS_3 0x5E83B4 + +#define mmDMA7_QM_CP_STS_4 0x5E83B8 + +#define mmDMA7_QM_CP_CURRENT_INST_LO_0 0x5E83BC + +#define mmDMA7_QM_CP_CURRENT_INST_LO_1 0x5E83C0 + +#define mmDMA7_QM_CP_CURRENT_INST_LO_2 0x5E83C4 + +#define mmDMA7_QM_CP_CURRENT_INST_LO_3 0x5E83C8 + +#define mmDMA7_QM_CP_CURRENT_INST_LO_4 0x5E83CC + +#define mmDMA7_QM_CP_CURRENT_INST_HI_0 0x5E83D0 + +#define mmDMA7_QM_CP_CURRENT_INST_HI_1 0x5E83D4 + +#define mmDMA7_QM_CP_CURRENT_INST_HI_2 0x5E83D8 + +#define mmDMA7_QM_CP_CURRENT_INST_HI_3 0x5E83DC + +#define mmDMA7_QM_CP_CURRENT_INST_HI_4 0x5E83E0 + +#define mmDMA7_QM_CP_BARRIER_CFG_0 0x5E83F4 + +#define mmDMA7_QM_CP_BARRIER_CFG_1 0x5E83F8 + +#define mmDMA7_QM_CP_BARRIER_CFG_2 0x5E83FC + +#define mmDMA7_QM_CP_BARRIER_CFG_3 0x5E8400 + +#define mmDMA7_QM_CP_BARRIER_CFG_4 0x5E8404 + +#define mmDMA7_QM_CP_DBG_0_0 0x5E8408 + +#define mmDMA7_QM_CP_DBG_0_1 0x5E840C + +#define mmDMA7_QM_CP_DBG_0_2 0x5E8410 + +#define mmDMA7_QM_CP_DBG_0_3 0x5E8414 + +#define mmDMA7_QM_CP_DBG_0_4 0x5E8418 + +#define mmDMA7_QM_CP_ARUSER_31_11_0 0x5E841C + +#define mmDMA7_QM_CP_ARUSER_31_11_1 0x5E8420 + +#define mmDMA7_QM_CP_ARUSER_31_11_2 0x5E8424 + +#define mmDMA7_QM_CP_ARUSER_31_11_3 0x5E8428 + +#define mmDMA7_QM_CP_ARUSER_31_11_4 0x5E842C + +#define mmDMA7_QM_CP_AWUSER_31_11_0 0x5E8430 + +#define mmDMA7_QM_CP_AWUSER_31_11_1 0x5E8434 + +#define mmDMA7_QM_CP_AWUSER_31_11_2 0x5E8438 + +#define mmDMA7_QM_CP_AWUSER_31_11_3 0x5E843C + +#define mmDMA7_QM_CP_AWUSER_31_11_4 0x5E8440 + +#define mmDMA7_QM_ARB_CFG_0 0x5E8A00 + +#define mmDMA7_QM_ARB_CHOISE_Q_PUSH 0x5E8A04 + +#define mmDMA7_QM_ARB_WRR_WEIGHT_0 0x5E8A08 + +#define mmDMA7_QM_ARB_WRR_WEIGHT_1 0x5E8A0C + +#define mmDMA7_QM_ARB_WRR_WEIGHT_2 0x5E8A10 + +#define mmDMA7_QM_ARB_WRR_WEIGHT_3 0x5E8A14 + +#define mmDMA7_QM_ARB_CFG_1 0x5E8A18 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_0 0x5E8A20 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_1 0x5E8A24 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_2 0x5E8A28 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_3 0x5E8A2C + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_4 0x5E8A30 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_5 0x5E8A34 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_6 0x5E8A38 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_7 0x5E8A3C + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_8 0x5E8A40 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_9 0x5E8A44 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_10 0x5E8A48 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_11 0x5E8A4C + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_12 0x5E8A50 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_13 0x5E8A54 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_14 0x5E8A58 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_15 0x5E8A5C + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_16 0x5E8A60 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_17 0x5E8A64 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_18 0x5E8A68 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_19 0x5E8A6C + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_20 0x5E8A70 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_21 0x5E8A74 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_22 0x5E8A78 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_23 0x5E8A7C + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_24 0x5E8A80 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_25 0x5E8A84 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_26 0x5E8A88 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_27 0x5E8A8C + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_28 0x5E8A90 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_29 0x5E8A94 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_30 0x5E8A98 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_31 0x5E8A9C + +#define mmDMA7_QM_ARB_MST_CRED_INC 0x5E8AA0 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x5E8AA4 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x5E8AA8 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x5E8AAC + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x5E8AB0 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x5E8AB4 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x5E8AB8 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x5E8ABC + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x5E8AC0 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x5E8AC4 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x5E8AC8 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x5E8ACC + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x5E8AD0 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x5E8AD4 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x5E8AD8 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x5E8ADC + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x5E8AE0 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x5E8AE4 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x5E8AE8 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x5E8AEC + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x5E8AF0 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x5E8AF4 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x5E8AF8 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x5E8AFC + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x5E8B00 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x5E8B04 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x5E8B08 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x5E8B0C + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x5E8B10 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x5E8B14 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x5E8B18 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x5E8B1C + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x5E8B20 + +#define mmDMA7_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x5E8B28 + +#define mmDMA7_QM_ARB_MST_SLAVE_EN 0x5E8B2C + +#define mmDMA7_QM_ARB_MST_QUIET_PER 0x5E8B34 + +#define mmDMA7_QM_ARB_SLV_CHOISE_WDT 0x5E8B38 + +#define mmDMA7_QM_ARB_SLV_ID 0x5E8B3C + +#define mmDMA7_QM_ARB_MSG_MAX_INFLIGHT 0x5E8B44 + +#define mmDMA7_QM_ARB_MSG_AWUSER_31_11 0x5E8B48 + +#define mmDMA7_QM_ARB_MSG_AWUSER_SEC_PROP 0x5E8B4C + +#define mmDMA7_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x5E8B50 + +#define mmDMA7_QM_ARB_BASE_LO 0x5E8B54 + +#define mmDMA7_QM_ARB_BASE_HI 0x5E8B58 + +#define mmDMA7_QM_ARB_STATE_STS 0x5E8B80 + +#define mmDMA7_QM_ARB_CHOISE_FULLNESS_STS 0x5E8B84 + +#define mmDMA7_QM_ARB_MSG_STS 0x5E8B88 + +#define mmDMA7_QM_ARB_SLV_CHOISE_Q_HEAD 0x5E8B8C + +#define mmDMA7_QM_ARB_ERR_CAUSE 0x5E8B9C + +#define mmDMA7_QM_ARB_ERR_MSG_EN 0x5E8BA0 + +#define mmDMA7_QM_ARB_ERR_STS_DRP 0x5E8BA8 + +#define mmDMA7_QM_ARB_MST_CRED_STS_0 0x5E8BB0 + +#define mmDMA7_QM_ARB_MST_CRED_STS_1 0x5E8BB4 + +#define mmDMA7_QM_ARB_MST_CRED_STS_2 0x5E8BB8 + +#define mmDMA7_QM_ARB_MST_CRED_STS_3 0x5E8BBC + +#define mmDMA7_QM_ARB_MST_CRED_STS_4 0x5E8BC0 + +#define mmDMA7_QM_ARB_MST_CRED_STS_5 0x5E8BC4 + +#define mmDMA7_QM_ARB_MST_CRED_STS_6 0x5E8BC8 + +#define mmDMA7_QM_ARB_MST_CRED_STS_7 0x5E8BCC + +#define mmDMA7_QM_ARB_MST_CRED_STS_8 0x5E8BD0 + +#define mmDMA7_QM_ARB_MST_CRED_STS_9 0x5E8BD4 + +#define mmDMA7_QM_ARB_MST_CRED_STS_10 0x5E8BD8 + +#define mmDMA7_QM_ARB_MST_CRED_STS_11 0x5E8BDC + +#define mmDMA7_QM_ARB_MST_CRED_STS_12 0x5E8BE0 + +#define mmDMA7_QM_ARB_MST_CRED_STS_13 0x5E8BE4 + +#define mmDMA7_QM_ARB_MST_CRED_STS_14 0x5E8BE8 + +#define mmDMA7_QM_ARB_MST_CRED_STS_15 0x5E8BEC + +#define mmDMA7_QM_ARB_MST_CRED_STS_16 0x5E8BF0 + +#define mmDMA7_QM_ARB_MST_CRED_STS_17 0x5E8BF4 + +#define mmDMA7_QM_ARB_MST_CRED_STS_18 0x5E8BF8 + +#define mmDMA7_QM_ARB_MST_CRED_STS_19 0x5E8BFC + +#define mmDMA7_QM_ARB_MST_CRED_STS_20 0x5E8C00 + +#define mmDMA7_QM_ARB_MST_CRED_STS_21 0x5E8C04 + +#define mmDMA7_QM_ARB_MST_CRED_STS_22 0x5E8C08 + +#define mmDMA7_QM_ARB_MST_CRED_STS_23 0x5E8C0C + +#define mmDMA7_QM_ARB_MST_CRED_STS_24 0x5E8C10 + +#define mmDMA7_QM_ARB_MST_CRED_STS_25 0x5E8C14 + +#define mmDMA7_QM_ARB_MST_CRED_STS_26 0x5E8C18 + +#define mmDMA7_QM_ARB_MST_CRED_STS_27 0x5E8C1C + +#define mmDMA7_QM_ARB_MST_CRED_STS_28 0x5E8C20 + +#define mmDMA7_QM_ARB_MST_CRED_STS_29 0x5E8C24 + +#define mmDMA7_QM_ARB_MST_CRED_STS_30 0x5E8C28 + +#define mmDMA7_QM_ARB_MST_CRED_STS_31 0x5E8C2C + +#define mmDMA7_QM_CGM_CFG 0x5E8C70 + +#define mmDMA7_QM_CGM_STS 0x5E8C74 + +#define mmDMA7_QM_CGM_CFG1 0x5E8C78 + +#define mmDMA7_QM_LOCAL_RANGE_BASE 0x5E8C80 + +#define mmDMA7_QM_LOCAL_RANGE_SIZE 0x5E8C84 + +#define mmDMA7_QM_CSMR_STRICT_PRIO_CFG 0x5E8C90 + +#define mmDMA7_QM_HBW_RD_RATE_LIM_CFG_1 0x5E8C94 + +#define mmDMA7_QM_LBW_WR_RATE_LIM_CFG_0 0x5E8C98 + +#define mmDMA7_QM_LBW_WR_RATE_LIM_CFG_1 0x5E8C9C + +#define mmDMA7_QM_HBW_RD_RATE_LIM_CFG_0 0x5E8CA0 + +#define mmDMA7_QM_GLBL_AXCACHE 0x5E8CA4 + +#define mmDMA7_QM_IND_GW_APB_CFG 0x5E8CB0 + +#define mmDMA7_QM_IND_GW_APB_WDATA 0x5E8CB4 + +#define mmDMA7_QM_IND_GW_APB_RDATA 0x5E8CB8 + +#define mmDMA7_QM_IND_GW_APB_STATUS 0x5E8CBC + +#define mmDMA7_QM_GLBL_ERR_ADDR_LO 0x5E8CD0 + +#define mmDMA7_QM_GLBL_ERR_ADDR_HI 0x5E8CD4 + +#define mmDMA7_QM_GLBL_ERR_WDATA 0x5E8CD8 + +#define mmDMA7_QM_GLBL_MEM_INIT_BUSY 0x5E8D00 + +#endif /* ASIC_REG_DMA7_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch0_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch0_regs.h new file mode 100644 index 000000000000..8c1c72df4469 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch0_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_E_N_DOWN_CH0_REGS_H_ +#define ASIC_REG_DMA_IF_E_N_DOWN_CH0_REGS_H_ + +/* + ***************************************** + * DMA_IF_E_N_DOWN_CH0 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmDMA_IF_E_N_DOWN_CH0_PERM_SEL 0x4E1108 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_0 0x4E1114 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_1 0x4E1118 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_2 0x4E111C + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_3 0x4E1120 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_4 0x4E1124 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_5 0x4E1128 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_6 0x4E112C + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_7 0x4E1130 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_8 0x4E1134 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_9 0x4E1138 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_10 0x4E113C + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_11 0x4E1140 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_12 0x4E1144 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_13 0x4E1148 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_14 0x4E114C + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_15 0x4E1150 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_16 0x4E1154 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_17 0x4E1158 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_18 0x4E115C + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_19 0x4E1160 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_20 0x4E1164 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_21 0x4E1168 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_22 0x4E116C + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_23 0x4E1170 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_24 0x4E1174 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_25 0x4E1178 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_26 0x4E117C + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_27 0x4E1180 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_0 0x4E1184 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_1 0x4E1188 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_2 0x4E118C + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_3 0x4E1190 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_4 0x4E1194 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_5 0x4E1198 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_6 0x4E119C + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_7 0x4E11A0 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_8 0x4E11A4 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_9 0x4E11A8 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_10 0x4E11AC + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_11 0x4E11B0 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_12 0x4E11B4 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_13 0x4E11B8 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_14 0x4E11BC + +#define mmDMA_IF_E_N_DOWN_CH0_SCRAM_SRAM_EN 0x4E126C + +#define mmDMA_IF_E_N_DOWN_CH0_RL_HBM_EN 0x4E1274 + +#define mmDMA_IF_E_N_DOWN_CH0_RL_HBM_SAT 0x4E1278 + +#define mmDMA_IF_E_N_DOWN_CH0_RL_HBM_RST 0x4E127C + +#define mmDMA_IF_E_N_DOWN_CH0_RL_HBM_TIMEOUT 0x4E1280 + +#define mmDMA_IF_E_N_DOWN_CH0_SCRAM_HBM_EN 0x4E1284 + +#define mmDMA_IF_E_N_DOWN_CH0_RL_PCI_EN 0x4E1288 + +#define mmDMA_IF_E_N_DOWN_CH0_RL_PCI_SAT 0x4E128C + +#define mmDMA_IF_E_N_DOWN_CH0_RL_PCI_RST 0x4E1290 + +#define mmDMA_IF_E_N_DOWN_CH0_RL_PCI_TIMEOUT 0x4E1294 + +#define mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_EN 0x4E129C + +#define mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_SAT 0x4E12A0 + +#define mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_RST 0x4E12A4 + +#define mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_TIMEOUT 0x4E12AC + +#define mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_RED 0x4E12B4 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_EN 0x4E12EC + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_EN 0x4E12F0 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_WR_SIZE 0x4E12F4 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_WR_SIZE 0x4E12F8 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_PCI_CTR_SET_EN 0x4E1404 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_PCI_CTR_SET 0x4E1408 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_PCI_CTR_WRAP 0x4E140C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_PCI_CTR_CNT 0x4E1410 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM_CTR_SET_EN 0x4E1414 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM_CTR_SET 0x4E1418 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_RD_SIZE 0x4E141C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_RD_SIZE 0x4E1420 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_PCI_CTR_SET_EN 0x4E1424 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_PCI_CTR_SET 0x4E1428 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_PCI_CTR_WRAP 0x4E142C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_PCI_CTR_CNT 0x4E1430 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM_CTR_SET_EN 0x4E1434 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM_CTR_SET 0x4E1438 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_SEL_0 0x4E1450 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_SEL_1 0x4E1454 + +#define mmDMA_IF_E_N_DOWN_CH0_NON_LIN_EN 0x4E1480 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_BANK_0 0x4E1500 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_BANK_1 0x4E1504 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_BANK_2 0x4E1508 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_BANK_3 0x4E150C + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_BANK_4 0x4E1510 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_0 0x4E1514 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_1 0x4E1520 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_2 0x4E1524 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_3 0x4E1528 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_4 0x4E152C + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_5 0x4E1530 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_6 0x4E1534 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_7 0x4E1538 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_8 0x4E153C + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_9 0x4E1540 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_0 0x4E1550 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_1 0x4E1554 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_2 0x4E1558 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_3 0x4E155C + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_4 0x4E1560 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_5 0x4E1564 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_6 0x4E1568 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_7 0x4E156C + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_8 0x4E1570 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_9 0x4E1574 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_10 0x4E1578 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_11 0x4E157C + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_12 0x4E1580 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_13 0x4E1584 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_14 0x4E1588 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_15 0x4E158C + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_16 0x4E1590 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_17 0x4E1594 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_18 0x4E1598 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0 0x4E15E4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_1 0x4E15E8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_2 0x4E15EC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_3 0x4E15F0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_4 0x4E15F4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_5 0x4E15F8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_6 0x4E15FC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_7 0x4E1600 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_8 0x4E1604 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_9 0x4E1608 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_10 0x4E160C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_11 0x4E1610 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_12 0x4E1614 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_13 0x4E1618 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_14 0x4E161C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_15 0x4E1620 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0 0x4E1624 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_1 0x4E1628 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_2 0x4E162C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_3 0x4E1630 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_4 0x4E1634 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_5 0x4E1638 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_6 0x4E163C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_7 0x4E1640 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_8 0x4E1644 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_9 0x4E1648 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_10 0x4E164C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_11 0x4E1650 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_12 0x4E1654 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_13 0x4E1658 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_14 0x4E165C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_15 0x4E1660 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0 0x4E1664 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_1 0x4E1668 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_2 0x4E166C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_3 0x4E1670 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_4 0x4E1674 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_5 0x4E1678 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_6 0x4E167C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_7 0x4E1680 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_8 0x4E1684 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_9 0x4E1688 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_10 0x4E168C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_11 0x4E1690 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_12 0x4E1694 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_13 0x4E1698 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_14 0x4E169C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_15 0x4E16A0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0 0x4E16A4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_1 0x4E16A8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_2 0x4E16AC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_3 0x4E16B0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_4 0x4E16B4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_5 0x4E16B8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_6 0x4E16BC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_7 0x4E16C0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_8 0x4E16C4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_9 0x4E16C8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_10 0x4E16CC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_11 0x4E16D0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_12 0x4E16D4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_13 0x4E16D8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_14 0x4E16DC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_15 0x4E16E0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_0 0x4E16E4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_1 0x4E16E8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_2 0x4E16EC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_3 0x4E16F0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_4 0x4E16F4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_5 0x4E16F8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_6 0x4E16FC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_7 0x4E1700 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_8 0x4E1704 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_9 0x4E1708 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_10 0x4E170C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_11 0x4E1710 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_12 0x4E1714 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_13 0x4E1718 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_14 0x4E171C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_15 0x4E1720 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_0 0x4E1724 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_1 0x4E1728 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_2 0x4E172C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_3 0x4E1730 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_4 0x4E1734 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_5 0x4E1738 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_6 0x4E173C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_7 0x4E1740 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_8 0x4E1744 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_9 0x4E1748 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_10 0x4E174C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_11 0x4E1750 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_12 0x4E1754 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_13 0x4E1758 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_14 0x4E175C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_15 0x4E1760 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_0 0x4E1764 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_1 0x4E1768 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_2 0x4E176C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_3 0x4E1770 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_4 0x4E1774 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_5 0x4E1778 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_6 0x4E177C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_7 0x4E1780 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_8 0x4E1784 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_9 0x4E1788 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_10 0x4E178C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_11 0x4E1790 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_12 0x4E1794 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_13 0x4E1798 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_14 0x4E179C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_15 0x4E17A0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_0 0x4E17A4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_1 0x4E17A8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_2 0x4E17AC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_3 0x4E17B0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_4 0x4E17B4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_5 0x4E17B8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_6 0x4E17BC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_7 0x4E17C0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_8 0x4E17C4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_9 0x4E17C8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_10 0x4E17CC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_11 0x4E17D0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_12 0x4E17D4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_13 0x4E17D8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_14 0x4E17DC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_15 0x4E17E0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0 0x4E1824 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_1 0x4E1828 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_2 0x4E182C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_3 0x4E1830 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_4 0x4E1834 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_5 0x4E1838 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_6 0x4E183C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_7 0x4E1840 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_8 0x4E1844 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_9 0x4E1848 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_10 0x4E184C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_11 0x4E1850 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_12 0x4E1854 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_13 0x4E1858 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_14 0x4E185C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_15 0x4E1860 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0 0x4E1864 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_1 0x4E1868 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_2 0x4E186C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_3 0x4E1870 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_4 0x4E1874 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_5 0x4E1878 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_6 0x4E187C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_7 0x4E1880 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_8 0x4E1884 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_9 0x4E1888 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_10 0x4E188C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_11 0x4E1890 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_12 0x4E1894 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_13 0x4E1898 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_14 0x4E189C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_15 0x4E18A0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0 0x4E18A4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_1 0x4E18A8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_2 0x4E18AC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_3 0x4E18B0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_4 0x4E18B4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_5 0x4E18B8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_6 0x4E18BC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_7 0x4E18C0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_8 0x4E18C4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_9 0x4E18C8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_10 0x4E18CC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_11 0x4E18D0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_12 0x4E18D4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_13 0x4E18D8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_14 0x4E18DC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_15 0x4E18E0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0 0x4E18E4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_1 0x4E18E8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_2 0x4E18EC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_3 0x4E18F0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_4 0x4E18F4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_5 0x4E18F8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_6 0x4E18FC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_7 0x4E1900 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_8 0x4E1904 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_9 0x4E1908 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_10 0x4E190C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_11 0x4E1910 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_12 0x4E1914 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_13 0x4E1918 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_14 0x4E191C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_15 0x4E1920 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_0 0x4E1924 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_1 0x4E1928 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_2 0x4E192C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_3 0x4E1930 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_4 0x4E1934 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_5 0x4E1938 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_6 0x4E193C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_7 0x4E1940 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_8 0x4E1944 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_9 0x4E1948 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_10 0x4E194C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_11 0x4E1950 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_12 0x4E1954 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_13 0x4E1958 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_14 0x4E195C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_15 0x4E1960 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_0 0x4E1964 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_1 0x4E1968 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_2 0x4E196C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_3 0x4E1970 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_4 0x4E1974 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_5 0x4E1978 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_6 0x4E197C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_7 0x4E1980 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_8 0x4E1984 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_9 0x4E1988 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_10 0x4E198C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_11 0x4E1990 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_12 0x4E1994 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_13 0x4E1998 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_14 0x4E199C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_15 0x4E19A0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_0 0x4E19A4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_1 0x4E19A8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_2 0x4E19AC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_3 0x4E19B0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_4 0x4E19B4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_5 0x4E19B8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_6 0x4E19BC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_7 0x4E19C0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_8 0x4E19C4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_9 0x4E19C8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_10 0x4E19CC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_11 0x4E19D0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_12 0x4E19D4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_13 0x4E19D8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_14 0x4E19DC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_15 0x4E19E0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_0 0x4E19E4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_1 0x4E19E8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_2 0x4E19EC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_3 0x4E19F0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_4 0x4E19F4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_5 0x4E19F8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_6 0x4E19FC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_7 0x4E1A00 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_8 0x4E1A04 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_9 0x4E1A08 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_10 0x4E1A0C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_11 0x4E1A10 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_12 0x4E1A14 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_13 0x4E1A18 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_14 0x4E1A1C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_15 0x4E1A20 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_HIT_AW 0x4E1A64 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_HIT_AR 0x4E1A68 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_HIT_AW 0x4E1A6C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_HIT_AR 0x4E1A70 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_CFG 0x4E1B64 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_SHIFT 0x4E1B68 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_0 0x4E1B6C + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_1 0x4E1B70 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_2 0x4E1B74 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_3 0x4E1B78 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_4 0x4E1B7C + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_5 0x4E1B80 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_6 0x4E1B84 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_7 0x4E1B88 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_0 0x4E1BAC + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_1 0x4E1BB0 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_2 0x4E1BB4 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_3 0x4E1BB8 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_4 0x4E1BBC + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_5 0x4E1BC0 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_6 0x4E1BC4 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_7 0x4E1BC8 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_0 0x4E1BEC + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_1 0x4E1BF0 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_2 0x4E1BF4 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_3 0x4E1BF8 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_4 0x4E1BFC + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_5 0x4E1C00 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_6 0x4E1C04 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_7 0x4E1C08 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_WDT 0x4E1C2C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_WRAP 0x4E1C30 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_WRAP 0x4E1C34 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_WRAP 0x4E1C38 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_WRAP 0x4E1C3C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_WRAP 0x4E1C40 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_WRAP 0x4E1C44 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_WRAP 0x4E1C48 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_WRAP 0x4E1C4C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_CNT 0x4E1C50 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_CNT 0x4E1C54 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_CNT 0x4E1C58 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_CNT 0x4E1C5C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_CNT 0x4E1C60 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_CNT 0x4E1C64 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_CNT 0x4E1C68 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_CNT 0x4E1C6C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_WRAP 0x4E1C70 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_WRAP 0x4E1C74 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_WRAP 0x4E1C78 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_WRAP 0x4E1C7C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_WRAP 0x4E1C80 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_WRAP 0x4E1C84 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_WRAP 0x4E1C88 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_WRAP 0x4E1C8C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_CNT 0x4E1C90 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_CNT 0x4E1C94 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_CNT 0x4E1C98 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_CNT 0x4E1C9C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_CNT 0x4E1CA0 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_CNT 0x4E1CA4 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_CNT 0x4E1CA8 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_CNT 0x4E1CAC + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_PC_SEL_0 0x4E1CB0 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_PC_SEL_1 0x4E1CB4 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_PC_SEL_2 0x4E1CB8 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_PC_SEL_3 0x4E1CBC + +#endif /* ASIC_REG_DMA_IF_E_N_DOWN_CH0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch1_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch1_regs.h new file mode 100644 index 000000000000..b2b593fcec30 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch1_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_E_N_DOWN_CH1_REGS_H_ +#define ASIC_REG_DMA_IF_E_N_DOWN_CH1_REGS_H_ + +/* + ***************************************** + * DMA_IF_E_N_DOWN_CH1 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmDMA_IF_E_N_DOWN_CH1_PERM_SEL 0x4E2108 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_0 0x4E2114 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_1 0x4E2118 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_2 0x4E211C + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_3 0x4E2120 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_4 0x4E2124 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_5 0x4E2128 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_6 0x4E212C + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_7 0x4E2130 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_8 0x4E2134 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_9 0x4E2138 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_10 0x4E213C + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_11 0x4E2140 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_12 0x4E2144 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_13 0x4E2148 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_14 0x4E214C + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_15 0x4E2150 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_16 0x4E2154 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_17 0x4E2158 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_18 0x4E215C + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_19 0x4E2160 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_20 0x4E2164 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_21 0x4E2168 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_22 0x4E216C + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_23 0x4E2170 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_24 0x4E2174 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_25 0x4E2178 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_26 0x4E217C + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_27 0x4E2180 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_0 0x4E2184 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_1 0x4E2188 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_2 0x4E218C + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_3 0x4E2190 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_4 0x4E2194 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_5 0x4E2198 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_6 0x4E219C + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_7 0x4E21A0 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_8 0x4E21A4 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_9 0x4E21A8 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_10 0x4E21AC + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_11 0x4E21B0 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_12 0x4E21B4 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_13 0x4E21B8 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_14 0x4E21BC + +#define mmDMA_IF_E_N_DOWN_CH1_SCRAM_SRAM_EN 0x4E226C + +#define mmDMA_IF_E_N_DOWN_CH1_RL_HBM_EN 0x4E2274 + +#define mmDMA_IF_E_N_DOWN_CH1_RL_HBM_SAT 0x4E2278 + +#define mmDMA_IF_E_N_DOWN_CH1_RL_HBM_RST 0x4E227C + +#define mmDMA_IF_E_N_DOWN_CH1_RL_HBM_TIMEOUT 0x4E2280 + +#define mmDMA_IF_E_N_DOWN_CH1_SCRAM_HBM_EN 0x4E2284 + +#define mmDMA_IF_E_N_DOWN_CH1_RL_PCI_EN 0x4E2288 + +#define mmDMA_IF_E_N_DOWN_CH1_RL_PCI_SAT 0x4E228C + +#define mmDMA_IF_E_N_DOWN_CH1_RL_PCI_RST 0x4E2290 + +#define mmDMA_IF_E_N_DOWN_CH1_RL_PCI_TIMEOUT 0x4E2294 + +#define mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_EN 0x4E229C + +#define mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_SAT 0x4E22A0 + +#define mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_RST 0x4E22A4 + +#define mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_TIMEOUT 0x4E22AC + +#define mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_RED 0x4E22B4 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_EN 0x4E22EC + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_EN 0x4E22F0 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_WR_SIZE 0x4E22F4 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_WR_SIZE 0x4E22F8 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_PCI_CTR_SET_EN 0x4E2404 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_PCI_CTR_SET 0x4E2408 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_PCI_CTR_WRAP 0x4E240C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_PCI_CTR_CNT 0x4E2410 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM_CTR_SET_EN 0x4E2414 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM_CTR_SET 0x4E2418 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_RD_SIZE 0x4E241C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_RD_SIZE 0x4E2420 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_PCI_CTR_SET_EN 0x4E2424 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_PCI_CTR_SET 0x4E2428 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_PCI_CTR_WRAP 0x4E242C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_PCI_CTR_CNT 0x4E2430 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM_CTR_SET_EN 0x4E2434 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM_CTR_SET 0x4E2438 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_SEL_0 0x4E2450 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_SEL_1 0x4E2454 + +#define mmDMA_IF_E_N_DOWN_CH1_NON_LIN_EN 0x4E2480 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_BANK_0 0x4E2500 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_BANK_1 0x4E2504 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_BANK_2 0x4E2508 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_BANK_3 0x4E250C + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_BANK_4 0x4E2510 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_0 0x4E2514 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_1 0x4E2520 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_2 0x4E2524 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_3 0x4E2528 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_4 0x4E252C + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_5 0x4E2530 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_6 0x4E2534 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_7 0x4E2538 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_8 0x4E253C + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_9 0x4E2540 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_0 0x4E2550 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_1 0x4E2554 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_2 0x4E2558 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_3 0x4E255C + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_4 0x4E2560 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_5 0x4E2564 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_6 0x4E2568 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_7 0x4E256C + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_8 0x4E2570 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_9 0x4E2574 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_10 0x4E2578 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_11 0x4E257C + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_12 0x4E2580 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_13 0x4E2584 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_14 0x4E2588 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_15 0x4E258C + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_16 0x4E2590 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_17 0x4E2594 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_18 0x4E2598 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0 0x4E25E4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_1 0x4E25E8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_2 0x4E25EC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_3 0x4E25F0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_4 0x4E25F4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_5 0x4E25F8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_6 0x4E25FC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_7 0x4E2600 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_8 0x4E2604 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_9 0x4E2608 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_10 0x4E260C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_11 0x4E2610 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_12 0x4E2614 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_13 0x4E2618 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_14 0x4E261C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_15 0x4E2620 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0 0x4E2624 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_1 0x4E2628 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_2 0x4E262C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_3 0x4E2630 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_4 0x4E2634 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_5 0x4E2638 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_6 0x4E263C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_7 0x4E2640 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_8 0x4E2644 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_9 0x4E2648 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_10 0x4E264C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_11 0x4E2650 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_12 0x4E2654 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_13 0x4E2658 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_14 0x4E265C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_15 0x4E2660 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0 0x4E2664 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_1 0x4E2668 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_2 0x4E266C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_3 0x4E2670 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_4 0x4E2674 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_5 0x4E2678 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_6 0x4E267C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_7 0x4E2680 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_8 0x4E2684 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_9 0x4E2688 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_10 0x4E268C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_11 0x4E2690 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_12 0x4E2694 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_13 0x4E2698 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_14 0x4E269C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_15 0x4E26A0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0 0x4E26A4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_1 0x4E26A8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_2 0x4E26AC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_3 0x4E26B0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_4 0x4E26B4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_5 0x4E26B8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_6 0x4E26BC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_7 0x4E26C0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_8 0x4E26C4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_9 0x4E26C8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_10 0x4E26CC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_11 0x4E26D0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_12 0x4E26D4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_13 0x4E26D8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_14 0x4E26DC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_15 0x4E26E0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_0 0x4E26E4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_1 0x4E26E8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_2 0x4E26EC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_3 0x4E26F0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_4 0x4E26F4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_5 0x4E26F8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_6 0x4E26FC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_7 0x4E2700 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_8 0x4E2704 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_9 0x4E2708 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_10 0x4E270C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_11 0x4E2710 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_12 0x4E2714 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_13 0x4E2718 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_14 0x4E271C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_15 0x4E2720 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_0 0x4E2724 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_1 0x4E2728 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_2 0x4E272C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_3 0x4E2730 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_4 0x4E2734 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_5 0x4E2738 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_6 0x4E273C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_7 0x4E2740 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_8 0x4E2744 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_9 0x4E2748 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_10 0x4E274C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_11 0x4E2750 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_12 0x4E2754 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_13 0x4E2758 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_14 0x4E275C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_15 0x4E2760 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_0 0x4E2764 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_1 0x4E2768 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_2 0x4E276C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_3 0x4E2770 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_4 0x4E2774 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_5 0x4E2778 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_6 0x4E277C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_7 0x4E2780 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_8 0x4E2784 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_9 0x4E2788 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_10 0x4E278C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_11 0x4E2790 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_12 0x4E2794 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_13 0x4E2798 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_14 0x4E279C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_15 0x4E27A0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_0 0x4E27A4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_1 0x4E27A8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_2 0x4E27AC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_3 0x4E27B0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_4 0x4E27B4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_5 0x4E27B8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_6 0x4E27BC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_7 0x4E27C0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_8 0x4E27C4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_9 0x4E27C8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_10 0x4E27CC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_11 0x4E27D0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_12 0x4E27D4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_13 0x4E27D8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_14 0x4E27DC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_15 0x4E27E0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0 0x4E2824 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_1 0x4E2828 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_2 0x4E282C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_3 0x4E2830 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_4 0x4E2834 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_5 0x4E2838 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_6 0x4E283C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_7 0x4E2840 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_8 0x4E2844 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_9 0x4E2848 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_10 0x4E284C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_11 0x4E2850 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_12 0x4E2854 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_13 0x4E2858 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_14 0x4E285C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_15 0x4E2860 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0 0x4E2864 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_1 0x4E2868 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_2 0x4E286C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_3 0x4E2870 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_4 0x4E2874 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_5 0x4E2878 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_6 0x4E287C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_7 0x4E2880 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_8 0x4E2884 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_9 0x4E2888 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_10 0x4E288C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_11 0x4E2890 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_12 0x4E2894 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_13 0x4E2898 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_14 0x4E289C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_15 0x4E28A0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0 0x4E28A4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_1 0x4E28A8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_2 0x4E28AC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_3 0x4E28B0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_4 0x4E28B4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_5 0x4E28B8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_6 0x4E28BC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_7 0x4E28C0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_8 0x4E28C4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_9 0x4E28C8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_10 0x4E28CC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_11 0x4E28D0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_12 0x4E28D4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_13 0x4E28D8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_14 0x4E28DC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_15 0x4E28E0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0 0x4E28E4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_1 0x4E28E8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_2 0x4E28EC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_3 0x4E28F0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_4 0x4E28F4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_5 0x4E28F8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_6 0x4E28FC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_7 0x4E2900 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_8 0x4E2904 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_9 0x4E2908 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_10 0x4E290C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_11 0x4E2910 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_12 0x4E2914 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_13 0x4E2918 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_14 0x4E291C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_15 0x4E2920 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_0 0x4E2924 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_1 0x4E2928 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_2 0x4E292C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_3 0x4E2930 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_4 0x4E2934 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_5 0x4E2938 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_6 0x4E293C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_7 0x4E2940 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_8 0x4E2944 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_9 0x4E2948 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_10 0x4E294C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_11 0x4E2950 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_12 0x4E2954 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_13 0x4E2958 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_14 0x4E295C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_15 0x4E2960 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_0 0x4E2964 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_1 0x4E2968 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_2 0x4E296C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_3 0x4E2970 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_4 0x4E2974 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_5 0x4E2978 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_6 0x4E297C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_7 0x4E2980 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_8 0x4E2984 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_9 0x4E2988 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_10 0x4E298C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_11 0x4E2990 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_12 0x4E2994 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_13 0x4E2998 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_14 0x4E299C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_15 0x4E29A0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_0 0x4E29A4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_1 0x4E29A8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_2 0x4E29AC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_3 0x4E29B0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_4 0x4E29B4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_5 0x4E29B8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_6 0x4E29BC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_7 0x4E29C0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_8 0x4E29C4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_9 0x4E29C8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_10 0x4E29CC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_11 0x4E29D0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_12 0x4E29D4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_13 0x4E29D8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_14 0x4E29DC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_15 0x4E29E0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_0 0x4E29E4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_1 0x4E29E8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_2 0x4E29EC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_3 0x4E29F0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_4 0x4E29F4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_5 0x4E29F8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_6 0x4E29FC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_7 0x4E2A00 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_8 0x4E2A04 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_9 0x4E2A08 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_10 0x4E2A0C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_11 0x4E2A10 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_12 0x4E2A14 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_13 0x4E2A18 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_14 0x4E2A1C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_15 0x4E2A20 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_HIT_AW 0x4E2A64 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_HIT_AR 0x4E2A68 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_HIT_AW 0x4E2A6C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_HIT_AR 0x4E2A70 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_CFG 0x4E2B64 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_SHIFT 0x4E2B68 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_0 0x4E2B6C + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_1 0x4E2B70 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_2 0x4E2B74 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_3 0x4E2B78 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_4 0x4E2B7C + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_5 0x4E2B80 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_6 0x4E2B84 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_7 0x4E2B88 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_0 0x4E2BAC + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_1 0x4E2BB0 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_2 0x4E2BB4 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_3 0x4E2BB8 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_4 0x4E2BBC + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_5 0x4E2BC0 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_6 0x4E2BC4 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_7 0x4E2BC8 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_0 0x4E2BEC + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_1 0x4E2BF0 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_2 0x4E2BF4 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_3 0x4E2BF8 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_4 0x4E2BFC + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_5 0x4E2C00 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_6 0x4E2C04 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_7 0x4E2C08 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_WDT 0x4E2C2C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_WRAP 0x4E2C30 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_WRAP 0x4E2C34 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_WRAP 0x4E2C38 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_WRAP 0x4E2C3C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_WRAP 0x4E2C40 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_WRAP 0x4E2C44 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_WRAP 0x4E2C48 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_WRAP 0x4E2C4C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_CNT 0x4E2C50 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_CNT 0x4E2C54 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_CNT 0x4E2C58 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_CNT 0x4E2C5C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_CNT 0x4E2C60 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_CNT 0x4E2C64 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_CNT 0x4E2C68 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_CNT 0x4E2C6C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_WRAP 0x4E2C70 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_WRAP 0x4E2C74 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_WRAP 0x4E2C78 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_WRAP 0x4E2C7C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_WRAP 0x4E2C80 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_WRAP 0x4E2C84 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_WRAP 0x4E2C88 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_WRAP 0x4E2C8C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_CNT 0x4E2C90 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_CNT 0x4E2C94 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_CNT 0x4E2C98 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_CNT 0x4E2C9C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_CNT 0x4E2CA0 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_CNT 0x4E2CA4 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_CNT 0x4E2CA8 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_CNT 0x4E2CAC + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_PC_SEL_0 0x4E2CB0 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_PC_SEL_1 0x4E2CB4 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_PC_SEL_2 0x4E2CB8 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_PC_SEL_3 0x4E2CBC + +#endif /* ASIC_REG_DMA_IF_E_N_DOWN_CH1_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_n_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_n_regs.h new file mode 100644 index 000000000000..8a10c6a76156 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_n_regs.h @@ -0,0 +1,860 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_E_N_REGS_H_ +#define ASIC_REG_DMA_IF_E_N_REGS_H_ + +/* + ***************************************** + * DMA_IF_E_N (Prototype: DMA_IF) + ***************************************** + */ + +#define mmDMA_IF_E_N_HBM0_WR_CRED_CNT 0x4E0000 + +#define mmDMA_IF_E_N_HBM1_WR_CRED_CNT 0x4E0004 + +#define mmDMA_IF_E_N_HBM0_RD_CRED_CNT 0x4E0008 + +#define mmDMA_IF_E_N_HBM1_RD_CRED_CNT 0x4E000C + +#define mmDMA_IF_E_N_HBM_LIMITER_0 0x4E0030 + +#define mmDMA_IF_E_N_HBM_LIMITER_1 0x4E0034 + +#define mmDMA_IF_E_N_HBM_LIMITER_2 0x4E0038 + +#define mmDMA_IF_E_N_HBM_LIMITER_3 0x4E003C + +#define mmDMA_IF_E_N_HBM_ALMOST_EN_0 0x4E0040 + +#define mmDMA_IF_E_N_HBM_ALMOST_EN_1 0x4E0044 + +#define mmDMA_IF_E_N_HBM_CRED_EN_0 0x4E0050 + +#define mmDMA_IF_E_N_HBM_CRED_EN_1 0x4E0054 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_0 0x4E0100 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_1 0x4E0104 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_2 0x4E0108 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_3 0x4E010C + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_4 0x4E0110 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_5 0x4E0114 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_6 0x4E0118 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_7 0x4E011C + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_8 0x4E0120 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_9 0x4E0124 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_10 0x4E0128 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_11 0x4E012C + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_12 0x4E0130 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_13 0x4E0134 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_14 0x4E0138 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_15 0x4E013C + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_0 0x4E0140 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_1 0x4E0144 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_2 0x4E0148 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_3 0x4E014C + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_4 0x4E0150 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_5 0x4E0154 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_6 0x4E0158 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_7 0x4E015C + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_8 0x4E0160 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_9 0x4E0164 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_10 0x4E0168 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_11 0x4E016C + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_12 0x4E0170 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_13 0x4E0174 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_14 0x4E0178 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_15 0x4E017C + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_0 0x4E0180 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_1 0x4E0184 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_2 0x4E0188 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_3 0x4E018C + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_4 0x4E0190 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_5 0x4E0194 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_6 0x4E0198 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_7 0x4E019C + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_8 0x4E01A0 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_9 0x4E01A4 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_10 0x4E01A8 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_11 0x4E01AC + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_12 0x4E01B0 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_13 0x4E01B4 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_14 0x4E01B8 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_15 0x4E01BC + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_0 0x4E01C0 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_1 0x4E01C4 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_2 0x4E01C8 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_3 0x4E01CC + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_4 0x4E01D0 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_5 0x4E01D4 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_6 0x4E01D8 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_7 0x4E01DC + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_8 0x4E01E0 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_9 0x4E01E4 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_10 0x4E01E8 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_11 0x4E01EC + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_12 0x4E01F0 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_13 0x4E01F4 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_14 0x4E01F8 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_15 0x4E01FC + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_0 0x4E0200 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_1 0x4E0204 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_2 0x4E0208 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_3 0x4E020C + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_4 0x4E0210 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_5 0x4E0214 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_6 0x4E0218 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_7 0x4E021C + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_8 0x4E0220 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_9 0x4E0224 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_10 0x4E0228 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_11 0x4E022C + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_12 0x4E0230 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_13 0x4E0234 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_14 0x4E0238 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_15 0x4E023C + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_0 0x4E0240 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_1 0x4E0244 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_2 0x4E0248 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_3 0x4E024C + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_4 0x4E0250 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_5 0x4E0254 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_6 0x4E0258 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_7 0x4E025C + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_8 0x4E0260 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_9 0x4E0264 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_10 0x4E0268 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_11 0x4E026C + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_12 0x4E0270 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_13 0x4E0274 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_14 0x4E0278 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_15 0x4E027C + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_0 0x4E0280 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_1 0x4E0284 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_2 0x4E0288 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_3 0x4E028C + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_4 0x4E0290 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_5 0x4E0294 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_6 0x4E0298 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_7 0x4E029C + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_8 0x4E02A0 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_9 0x4E02A4 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_10 0x4E02A8 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_11 0x4E02AC + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_12 0x4E02B0 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_13 0x4E02B4 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_14 0x4E02B8 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_15 0x4E02BC + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_0 0x4E02C0 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_1 0x4E02C4 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_2 0x4E02C8 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_3 0x4E02CC + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_4 0x4E02D0 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_5 0x4E02D4 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_6 0x4E02D8 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_7 0x4E02DC + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_8 0x4E02E0 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_9 0x4E02E4 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_10 0x4E02E8 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_11 0x4E02EC + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_12 0x4E02F0 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_13 0x4E02F4 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_14 0x4E02F8 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_15 0x4E02FC + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_0 0x4E0300 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_1 0x4E0304 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_2 0x4E0308 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_3 0x4E030C + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_4 0x4E0310 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_5 0x4E0314 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_6 0x4E0318 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_7 0x4E031C + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_8 0x4E0320 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_9 0x4E0324 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_10 0x4E0328 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_11 0x4E032C + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_12 0x4E0330 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_13 0x4E0334 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_14 0x4E0338 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_15 0x4E033C + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_0 0x4E0340 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_1 0x4E0344 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_2 0x4E0348 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_3 0x4E034C + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_4 0x4E0350 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_5 0x4E0354 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_6 0x4E0358 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_7 0x4E035C + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_8 0x4E0360 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_9 0x4E0364 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_10 0x4E0368 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_11 0x4E036C + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_12 0x4E0370 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_13 0x4E0374 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_14 0x4E0378 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_15 0x4E037C + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_0 0x4E0380 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_1 0x4E0384 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_2 0x4E0388 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_3 0x4E038C + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_4 0x4E0390 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_5 0x4E0394 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_6 0x4E0398 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_7 0x4E039C + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_8 0x4E03A0 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_9 0x4E03A4 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_10 0x4E03A8 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_11 0x4E03AC + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_12 0x4E03B0 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_13 0x4E03B4 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_14 0x4E03B8 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_15 0x4E03BC + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_0 0x4E03C0 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_1 0x4E03C4 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_2 0x4E03C8 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_3 0x4E03CC + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_4 0x4E03D0 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_5 0x4E03D4 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_6 0x4E03D8 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_7 0x4E03DC + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_8 0x4E03E0 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_9 0x4E03E4 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_10 0x4E03E8 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_11 0x4E03EC + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_12 0x4E03F0 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_13 0x4E03F4 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_14 0x4E03F8 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_15 0x4E03FC + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_0 0x4E0400 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_1 0x4E0404 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_2 0x4E0408 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_3 0x4E040C + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_4 0x4E0410 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_5 0x4E0414 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_6 0x4E0418 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_7 0x4E041C + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_8 0x4E0420 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_9 0x4E0424 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_10 0x4E0428 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_11 0x4E042C + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_12 0x4E0430 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_13 0x4E0434 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_14 0x4E0438 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_15 0x4E043C + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_0 0x4E0440 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_1 0x4E0444 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_2 0x4E0448 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_3 0x4E044C + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_4 0x4E0450 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_5 0x4E0454 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_6 0x4E0458 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_7 0x4E045C + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_8 0x4E0460 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_9 0x4E0464 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_10 0x4E0468 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_11 0x4E046C + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_12 0x4E0470 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_13 0x4E0474 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_14 0x4E0478 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_15 0x4E047C + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_0 0x4E0480 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_1 0x4E0484 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_2 0x4E0488 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_3 0x4E048C + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_4 0x4E0490 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_5 0x4E0494 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_6 0x4E0498 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_7 0x4E049C + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_8 0x4E04A0 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_9 0x4E04A4 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_10 0x4E04A8 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_11 0x4E04AC + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_12 0x4E04B0 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_13 0x4E04B4 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_14 0x4E04B8 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_15 0x4E04BC + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_0 0x4E04C0 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_1 0x4E04C4 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_2 0x4E04C8 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_3 0x4E04CC + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_4 0x4E04D0 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_5 0x4E04D4 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_6 0x4E04D8 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_7 0x4E04DC + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_8 0x4E04E0 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_9 0x4E04E4 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_10 0x4E04E8 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_11 0x4E04EC + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_12 0x4E04F0 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_13 0x4E04F4 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_14 0x4E04F8 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_15 0x4E04FC + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_0 0x4E0500 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_1 0x4E0504 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_2 0x4E0508 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_3 0x4E050C + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_4 0x4E0510 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_5 0x4E0514 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_6 0x4E0518 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_7 0x4E051C + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_8 0x4E0520 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_9 0x4E0524 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_10 0x4E0528 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_11 0x4E052C + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_12 0x4E0530 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_13 0x4E0534 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_14 0x4E0538 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_15 0x4E053C + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_0 0x4E0540 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_1 0x4E0544 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_2 0x4E0548 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_3 0x4E054C + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_4 0x4E0550 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_5 0x4E0554 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_6 0x4E0558 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_7 0x4E055C + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_8 0x4E0560 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_9 0x4E0564 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_10 0x4E0568 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_11 0x4E056C + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_12 0x4E0570 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_13 0x4E0574 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_14 0x4E0578 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_15 0x4E057C + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_0 0x4E0580 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_1 0x4E0584 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_2 0x4E0588 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_3 0x4E058C + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_4 0x4E0590 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_5 0x4E0594 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_6 0x4E0598 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_7 0x4E059C + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_8 0x4E05A0 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_9 0x4E05A4 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_10 0x4E05A8 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_11 0x4E05AC + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_12 0x4E05B0 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_13 0x4E05B4 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_14 0x4E05B8 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_15 0x4E05BC + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_0 0x4E05C0 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_1 0x4E05C4 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_2 0x4E05C8 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_3 0x4E05CC + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_4 0x4E05D0 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_5 0x4E05D4 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_6 0x4E05D8 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_7 0x4E05DC + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_8 0x4E05E0 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_9 0x4E05E4 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_10 0x4E05E8 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_11 0x4E05EC + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_12 0x4E05F0 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_13 0x4E05F4 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_14 0x4E05F8 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_15 0x4E05FC + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_0 0x4E0600 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_1 0x4E0604 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_2 0x4E0608 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_3 0x4E060C + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_4 0x4E0610 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_5 0x4E0614 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_6 0x4E0618 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_7 0x4E061C + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_8 0x4E0620 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_9 0x4E0624 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_10 0x4E0628 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_11 0x4E062C + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_12 0x4E0630 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_13 0x4E0634 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_14 0x4E0638 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_15 0x4E063C + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_0 0x4E0640 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_1 0x4E0644 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_2 0x4E0648 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_3 0x4E064C + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_4 0x4E0650 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_5 0x4E0654 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_6 0x4E0658 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_7 0x4E065C + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_8 0x4E0660 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_9 0x4E0664 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_10 0x4E0668 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_11 0x4E066C + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_12 0x4E0670 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_13 0x4E0674 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_14 0x4E0678 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_15 0x4E067C + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_0 0x4E0680 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_1 0x4E0684 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_2 0x4E0688 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_3 0x4E068C + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_4 0x4E0690 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_5 0x4E0694 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_6 0x4E0698 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_7 0x4E069C + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_8 0x4E06A0 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_9 0x4E06A4 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_10 0x4E06A8 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_11 0x4E06AC + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_12 0x4E06B0 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_13 0x4E06B4 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_14 0x4E06B8 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_15 0x4E06BC + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_0 0x4E06C0 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_1 0x4E06C4 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_2 0x4E06C8 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_3 0x4E06CC + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_4 0x4E06D0 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_5 0x4E06D4 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_6 0x4E06D8 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_7 0x4E06DC + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_8 0x4E06E0 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_9 0x4E06E4 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_10 0x4E06E8 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_11 0x4E06EC + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_12 0x4E06F0 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_13 0x4E06F4 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_14 0x4E06F8 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_15 0x4E06FC + +#define mmDMA_IF_E_N_SOB_HIT_RPROT 0x4E0700 + +#define mmDMA_IF_E_N_SOB_HIT_WPROT 0x4E0704 + +#define mmDMA_IF_E_N_SOB_HIT_RPRIV 0x4E070C + +#define mmDMA_IF_E_N_SOB_HIT_WPRIV 0x4E0710 + +#define mmDMA_IF_E_N_DMA0_HIT_RPROT 0x4E071C + +#define mmDMA_IF_E_N_DMA0_HIT_WPROT 0x4E0720 + +#define mmDMA_IF_E_N_DMA0_HIT_RPRIV 0x4E0724 + +#define mmDMA_IF_E_N_DMA0_HIT_WPRIV 0x4E0728 + +#define mmDMA_IF_E_N_DMA1_HIT_RPROT 0x4E0730 + +#define mmDMA_IF_E_N_DMA1_HIT_WPROT 0x4E0734 + +#define mmDMA_IF_E_N_DMA1_HIT_RPRIV 0x4E0738 + +#define mmDMA_IF_E_N_DMA1_HIT_WPRIV 0x4E073C + +#define mmDMA_IF_E_N_HBM_BIN 0x4E0800 + +#define mmDMA_IF_E_N_MME_BIN 0x4E0804 + +#define mmDMA_IF_E_N_TPC_BIN 0x4E0808 + +#define mmDMA_IF_E_N_DMA_BIN 0x4E080C + +#define mmDMA_IF_E_N_SOB_CG_EN 0x4E0810 + +#define mmDMA_IF_E_N_HBM_I2C_ADDR_0 0x4E0820 + +#define mmDMA_IF_E_N_HBM_I2C_ADDR_1 0x4E0824 + +#define mmDMA_IF_E_N_HBM_I2C_ADDR_2 0x4E0828 + +#define mmDMA_IF_E_N_HBM_I2C_ADDR_3 0x4E082C + +#define mmDMA_IF_E_N_HBM_I2C_ADDR_4 0x4E0830 + +#define mmDMA_IF_E_N_HBM_MISC 0x4E0834 + +#endif /* ASIC_REG_DMA_IF_E_N_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch0_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch0_regs.h new file mode 100644 index 000000000000..cd61289a1e8a --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch0_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_E_S_DOWN_CH0_REGS_H_ +#define ASIC_REG_DMA_IF_E_S_DOWN_CH0_REGS_H_ + +/* + ***************************************** + * DMA_IF_E_S_DOWN_CH0 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmDMA_IF_E_S_DOWN_CH0_PERM_SEL 0x4A1108 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_0 0x4A1114 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_1 0x4A1118 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_2 0x4A111C + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_3 0x4A1120 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_4 0x4A1124 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_5 0x4A1128 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_6 0x4A112C + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_7 0x4A1130 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_8 0x4A1134 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_9 0x4A1138 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_10 0x4A113C + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_11 0x4A1140 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_12 0x4A1144 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_13 0x4A1148 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_14 0x4A114C + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_15 0x4A1150 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_16 0x4A1154 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_17 0x4A1158 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_18 0x4A115C + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_19 0x4A1160 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_20 0x4A1164 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_21 0x4A1168 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_22 0x4A116C + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_23 0x4A1170 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_24 0x4A1174 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_25 0x4A1178 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_26 0x4A117C + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_27 0x4A1180 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_0 0x4A1184 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_1 0x4A1188 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_2 0x4A118C + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_3 0x4A1190 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_4 0x4A1194 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_5 0x4A1198 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_6 0x4A119C + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_7 0x4A11A0 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_8 0x4A11A4 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_9 0x4A11A8 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_10 0x4A11AC + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_11 0x4A11B0 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_12 0x4A11B4 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_13 0x4A11B8 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_14 0x4A11BC + +#define mmDMA_IF_E_S_DOWN_CH0_SCRAM_SRAM_EN 0x4A126C + +#define mmDMA_IF_E_S_DOWN_CH0_RL_HBM_EN 0x4A1274 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_HBM_SAT 0x4A1278 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_HBM_RST 0x4A127C + +#define mmDMA_IF_E_S_DOWN_CH0_RL_HBM_TIMEOUT 0x4A1280 + +#define mmDMA_IF_E_S_DOWN_CH0_SCRAM_HBM_EN 0x4A1284 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_PCI_EN 0x4A1288 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_PCI_SAT 0x4A128C + +#define mmDMA_IF_E_S_DOWN_CH0_RL_PCI_RST 0x4A1290 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_PCI_TIMEOUT 0x4A1294 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_EN 0x4A129C + +#define mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_SAT 0x4A12A0 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_RST 0x4A12A4 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_TIMEOUT 0x4A12AC + +#define mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_RED 0x4A12B4 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_EN 0x4A12EC + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_EN 0x4A12F0 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_WR_SIZE 0x4A12F4 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_WR_SIZE 0x4A12F8 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_PCI_CTR_SET_EN 0x4A1404 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_PCI_CTR_SET 0x4A1408 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_PCI_CTR_WRAP 0x4A140C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_PCI_CTR_CNT 0x4A1410 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM_CTR_SET_EN 0x4A1414 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM_CTR_SET 0x4A1418 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_RD_SIZE 0x4A141C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_RD_SIZE 0x4A1420 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_PCI_CTR_SET_EN 0x4A1424 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_PCI_CTR_SET 0x4A1428 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_PCI_CTR_WRAP 0x4A142C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_PCI_CTR_CNT 0x4A1430 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM_CTR_SET_EN 0x4A1434 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM_CTR_SET 0x4A1438 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_SEL_0 0x4A1450 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_SEL_1 0x4A1454 + +#define mmDMA_IF_E_S_DOWN_CH0_NON_LIN_EN 0x4A1480 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_BANK_0 0x4A1500 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_BANK_1 0x4A1504 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_BANK_2 0x4A1508 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_BANK_3 0x4A150C + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_BANK_4 0x4A1510 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_0 0x4A1514 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_1 0x4A1520 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_2 0x4A1524 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_3 0x4A1528 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_4 0x4A152C + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_5 0x4A1530 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_6 0x4A1534 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_7 0x4A1538 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_8 0x4A153C + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_9 0x4A1540 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_0 0x4A1550 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_1 0x4A1554 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_2 0x4A1558 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_3 0x4A155C + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_4 0x4A1560 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_5 0x4A1564 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_6 0x4A1568 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_7 0x4A156C + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_8 0x4A1570 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_9 0x4A1574 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_10 0x4A1578 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_11 0x4A157C + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_12 0x4A1580 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_13 0x4A1584 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_14 0x4A1588 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_15 0x4A158C + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_16 0x4A1590 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_17 0x4A1594 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_18 0x4A1598 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0 0x4A15E4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_1 0x4A15E8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_2 0x4A15EC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_3 0x4A15F0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_4 0x4A15F4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_5 0x4A15F8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_6 0x4A15FC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_7 0x4A1600 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_8 0x4A1604 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_9 0x4A1608 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_10 0x4A160C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_11 0x4A1610 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_12 0x4A1614 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_13 0x4A1618 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_14 0x4A161C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_15 0x4A1620 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0 0x4A1624 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_1 0x4A1628 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_2 0x4A162C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_3 0x4A1630 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_4 0x4A1634 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_5 0x4A1638 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_6 0x4A163C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_7 0x4A1640 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_8 0x4A1644 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_9 0x4A1648 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_10 0x4A164C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_11 0x4A1650 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_12 0x4A1654 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_13 0x4A1658 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_14 0x4A165C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_15 0x4A1660 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0 0x4A1664 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_1 0x4A1668 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_2 0x4A166C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_3 0x4A1670 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_4 0x4A1674 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_5 0x4A1678 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_6 0x4A167C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_7 0x4A1680 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_8 0x4A1684 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_9 0x4A1688 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_10 0x4A168C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_11 0x4A1690 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_12 0x4A1694 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_13 0x4A1698 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_14 0x4A169C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_15 0x4A16A0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0 0x4A16A4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_1 0x4A16A8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_2 0x4A16AC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_3 0x4A16B0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_4 0x4A16B4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_5 0x4A16B8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_6 0x4A16BC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_7 0x4A16C0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_8 0x4A16C4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_9 0x4A16C8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_10 0x4A16CC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_11 0x4A16D0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_12 0x4A16D4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_13 0x4A16D8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_14 0x4A16DC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_15 0x4A16E0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_0 0x4A16E4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_1 0x4A16E8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_2 0x4A16EC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_3 0x4A16F0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_4 0x4A16F4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_5 0x4A16F8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_6 0x4A16FC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_7 0x4A1700 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_8 0x4A1704 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_9 0x4A1708 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_10 0x4A170C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_11 0x4A1710 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_12 0x4A1714 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_13 0x4A1718 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_14 0x4A171C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_15 0x4A1720 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_0 0x4A1724 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_1 0x4A1728 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_2 0x4A172C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_3 0x4A1730 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_4 0x4A1734 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_5 0x4A1738 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_6 0x4A173C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_7 0x4A1740 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_8 0x4A1744 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_9 0x4A1748 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_10 0x4A174C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_11 0x4A1750 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_12 0x4A1754 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_13 0x4A1758 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_14 0x4A175C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_15 0x4A1760 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_0 0x4A1764 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_1 0x4A1768 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_2 0x4A176C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_3 0x4A1770 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_4 0x4A1774 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_5 0x4A1778 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_6 0x4A177C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_7 0x4A1780 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_8 0x4A1784 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_9 0x4A1788 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_10 0x4A178C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_11 0x4A1790 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_12 0x4A1794 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_13 0x4A1798 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_14 0x4A179C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_15 0x4A17A0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_0 0x4A17A4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_1 0x4A17A8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_2 0x4A17AC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_3 0x4A17B0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_4 0x4A17B4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_5 0x4A17B8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_6 0x4A17BC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_7 0x4A17C0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_8 0x4A17C4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_9 0x4A17C8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_10 0x4A17CC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_11 0x4A17D0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_12 0x4A17D4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_13 0x4A17D8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_14 0x4A17DC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_15 0x4A17E0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0 0x4A1824 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_1 0x4A1828 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_2 0x4A182C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_3 0x4A1830 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_4 0x4A1834 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_5 0x4A1838 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_6 0x4A183C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_7 0x4A1840 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_8 0x4A1844 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_9 0x4A1848 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_10 0x4A184C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_11 0x4A1850 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_12 0x4A1854 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_13 0x4A1858 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_14 0x4A185C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_15 0x4A1860 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0 0x4A1864 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_1 0x4A1868 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_2 0x4A186C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_3 0x4A1870 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_4 0x4A1874 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_5 0x4A1878 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_6 0x4A187C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_7 0x4A1880 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_8 0x4A1884 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_9 0x4A1888 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_10 0x4A188C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_11 0x4A1890 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_12 0x4A1894 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_13 0x4A1898 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_14 0x4A189C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_15 0x4A18A0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0 0x4A18A4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_1 0x4A18A8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_2 0x4A18AC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_3 0x4A18B0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_4 0x4A18B4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_5 0x4A18B8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_6 0x4A18BC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_7 0x4A18C0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_8 0x4A18C4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_9 0x4A18C8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_10 0x4A18CC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_11 0x4A18D0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_12 0x4A18D4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_13 0x4A18D8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_14 0x4A18DC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_15 0x4A18E0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0 0x4A18E4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_1 0x4A18E8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_2 0x4A18EC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_3 0x4A18F0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_4 0x4A18F4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_5 0x4A18F8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_6 0x4A18FC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_7 0x4A1900 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_8 0x4A1904 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_9 0x4A1908 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_10 0x4A190C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_11 0x4A1910 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_12 0x4A1914 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_13 0x4A1918 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_14 0x4A191C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_15 0x4A1920 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_0 0x4A1924 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_1 0x4A1928 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_2 0x4A192C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_3 0x4A1930 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_4 0x4A1934 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_5 0x4A1938 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_6 0x4A193C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_7 0x4A1940 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_8 0x4A1944 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_9 0x4A1948 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_10 0x4A194C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_11 0x4A1950 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_12 0x4A1954 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_13 0x4A1958 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_14 0x4A195C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_15 0x4A1960 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_0 0x4A1964 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_1 0x4A1968 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_2 0x4A196C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_3 0x4A1970 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_4 0x4A1974 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_5 0x4A1978 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_6 0x4A197C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_7 0x4A1980 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_8 0x4A1984 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_9 0x4A1988 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_10 0x4A198C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_11 0x4A1990 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_12 0x4A1994 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_13 0x4A1998 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_14 0x4A199C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_15 0x4A19A0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_0 0x4A19A4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_1 0x4A19A8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_2 0x4A19AC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_3 0x4A19B0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_4 0x4A19B4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_5 0x4A19B8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_6 0x4A19BC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_7 0x4A19C0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_8 0x4A19C4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_9 0x4A19C8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_10 0x4A19CC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_11 0x4A19D0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_12 0x4A19D4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_13 0x4A19D8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_14 0x4A19DC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_15 0x4A19E0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_0 0x4A19E4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_1 0x4A19E8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_2 0x4A19EC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_3 0x4A19F0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_4 0x4A19F4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_5 0x4A19F8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_6 0x4A19FC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_7 0x4A1A00 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_8 0x4A1A04 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_9 0x4A1A08 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_10 0x4A1A0C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_11 0x4A1A10 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_12 0x4A1A14 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_13 0x4A1A18 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_14 0x4A1A1C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_15 0x4A1A20 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_HIT_AW 0x4A1A64 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_HIT_AR 0x4A1A68 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_HIT_AW 0x4A1A6C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_HIT_AR 0x4A1A70 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_CFG 0x4A1B64 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_SHIFT 0x4A1B68 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_0 0x4A1B6C + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_1 0x4A1B70 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_2 0x4A1B74 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_3 0x4A1B78 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_4 0x4A1B7C + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_5 0x4A1B80 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_6 0x4A1B84 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_7 0x4A1B88 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_0 0x4A1BAC + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_1 0x4A1BB0 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_2 0x4A1BB4 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_3 0x4A1BB8 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_4 0x4A1BBC + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_5 0x4A1BC0 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_6 0x4A1BC4 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_7 0x4A1BC8 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_0 0x4A1BEC + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_1 0x4A1BF0 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_2 0x4A1BF4 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_3 0x4A1BF8 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_4 0x4A1BFC + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_5 0x4A1C00 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_6 0x4A1C04 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_7 0x4A1C08 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_WDT 0x4A1C2C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_WRAP 0x4A1C30 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_WRAP 0x4A1C34 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_WRAP 0x4A1C38 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_WRAP 0x4A1C3C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_WRAP 0x4A1C40 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_WRAP 0x4A1C44 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_WRAP 0x4A1C48 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_WRAP 0x4A1C4C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_CNT 0x4A1C50 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_CNT 0x4A1C54 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_CNT 0x4A1C58 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_CNT 0x4A1C5C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_CNT 0x4A1C60 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_CNT 0x4A1C64 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_CNT 0x4A1C68 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_CNT 0x4A1C6C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_WRAP 0x4A1C70 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_WRAP 0x4A1C74 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_WRAP 0x4A1C78 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_WRAP 0x4A1C7C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_WRAP 0x4A1C80 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_WRAP 0x4A1C84 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_WRAP 0x4A1C88 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_WRAP 0x4A1C8C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_CNT 0x4A1C90 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_CNT 0x4A1C94 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_CNT 0x4A1C98 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_CNT 0x4A1C9C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_CNT 0x4A1CA0 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_CNT 0x4A1CA4 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_CNT 0x4A1CA8 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_CNT 0x4A1CAC + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_PC_SEL_0 0x4A1CB0 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_PC_SEL_1 0x4A1CB4 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_PC_SEL_2 0x4A1CB8 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_PC_SEL_3 0x4A1CBC + +#endif /* ASIC_REG_DMA_IF_E_S_DOWN_CH0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch1_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch1_regs.h new file mode 100644 index 000000000000..3f32370a14c7 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch1_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_E_S_DOWN_CH1_REGS_H_ +#define ASIC_REG_DMA_IF_E_S_DOWN_CH1_REGS_H_ + +/* + ***************************************** + * DMA_IF_E_S_DOWN_CH1 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmDMA_IF_E_S_DOWN_CH1_PERM_SEL 0x4A2108 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_0 0x4A2114 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_1 0x4A2118 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_2 0x4A211C + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_3 0x4A2120 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_4 0x4A2124 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_5 0x4A2128 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_6 0x4A212C + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_7 0x4A2130 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_8 0x4A2134 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_9 0x4A2138 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_10 0x4A213C + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_11 0x4A2140 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_12 0x4A2144 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_13 0x4A2148 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_14 0x4A214C + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_15 0x4A2150 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_16 0x4A2154 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_17 0x4A2158 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_18 0x4A215C + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_19 0x4A2160 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_20 0x4A2164 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_21 0x4A2168 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_22 0x4A216C + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_23 0x4A2170 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_24 0x4A2174 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_25 0x4A2178 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_26 0x4A217C + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_27 0x4A2180 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_0 0x4A2184 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_1 0x4A2188 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_2 0x4A218C + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_3 0x4A2190 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_4 0x4A2194 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_5 0x4A2198 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_6 0x4A219C + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_7 0x4A21A0 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_8 0x4A21A4 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_9 0x4A21A8 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_10 0x4A21AC + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_11 0x4A21B0 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_12 0x4A21B4 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_13 0x4A21B8 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_14 0x4A21BC + +#define mmDMA_IF_E_S_DOWN_CH1_SCRAM_SRAM_EN 0x4A226C + +#define mmDMA_IF_E_S_DOWN_CH1_RL_HBM_EN 0x4A2274 + +#define mmDMA_IF_E_S_DOWN_CH1_RL_HBM_SAT 0x4A2278 + +#define mmDMA_IF_E_S_DOWN_CH1_RL_HBM_RST 0x4A227C + +#define mmDMA_IF_E_S_DOWN_CH1_RL_HBM_TIMEOUT 0x4A2280 + +#define mmDMA_IF_E_S_DOWN_CH1_SCRAM_HBM_EN 0x4A2284 + +#define mmDMA_IF_E_S_DOWN_CH1_RL_PCI_EN 0x4A2288 + +#define mmDMA_IF_E_S_DOWN_CH1_RL_PCI_SAT 0x4A228C + +#define mmDMA_IF_E_S_DOWN_CH1_RL_PCI_RST 0x4A2290 + +#define mmDMA_IF_E_S_DOWN_CH1_RL_PCI_TIMEOUT 0x4A2294 + +#define mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_EN 0x4A229C + +#define mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_SAT 0x4A22A0 + +#define mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_RST 0x4A22A4 + +#define mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_TIMEOUT 0x4A22AC + +#define mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_RED 0x4A22B4 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_EN 0x4A22EC + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_EN 0x4A22F0 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_WR_SIZE 0x4A22F4 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_WR_SIZE 0x4A22F8 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_PCI_CTR_SET_EN 0x4A2404 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_PCI_CTR_SET 0x4A2408 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_PCI_CTR_WRAP 0x4A240C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_PCI_CTR_CNT 0x4A2410 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM_CTR_SET_EN 0x4A2414 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM_CTR_SET 0x4A2418 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_RD_SIZE 0x4A241C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_RD_SIZE 0x4A2420 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_PCI_CTR_SET_EN 0x4A2424 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_PCI_CTR_SET 0x4A2428 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_PCI_CTR_WRAP 0x4A242C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_PCI_CTR_CNT 0x4A2430 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM_CTR_SET_EN 0x4A2434 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM_CTR_SET 0x4A2438 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_SEL_0 0x4A2450 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_SEL_1 0x4A2454 + +#define mmDMA_IF_E_S_DOWN_CH1_NON_LIN_EN 0x4A2480 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_BANK_0 0x4A2500 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_BANK_1 0x4A2504 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_BANK_2 0x4A2508 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_BANK_3 0x4A250C + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_BANK_4 0x4A2510 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_0 0x4A2514 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_1 0x4A2520 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_2 0x4A2524 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_3 0x4A2528 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_4 0x4A252C + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_5 0x4A2530 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_6 0x4A2534 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_7 0x4A2538 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_8 0x4A253C + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_9 0x4A2540 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_0 0x4A2550 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_1 0x4A2554 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_2 0x4A2558 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_3 0x4A255C + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_4 0x4A2560 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_5 0x4A2564 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_6 0x4A2568 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_7 0x4A256C + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_8 0x4A2570 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_9 0x4A2574 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_10 0x4A2578 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_11 0x4A257C + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_12 0x4A2580 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_13 0x4A2584 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_14 0x4A2588 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_15 0x4A258C + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_16 0x4A2590 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_17 0x4A2594 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_18 0x4A2598 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0 0x4A25E4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_1 0x4A25E8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_2 0x4A25EC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_3 0x4A25F0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_4 0x4A25F4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_5 0x4A25F8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_6 0x4A25FC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_7 0x4A2600 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_8 0x4A2604 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_9 0x4A2608 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_10 0x4A260C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_11 0x4A2610 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_12 0x4A2614 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_13 0x4A2618 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_14 0x4A261C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_15 0x4A2620 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0 0x4A2624 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_1 0x4A2628 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_2 0x4A262C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_3 0x4A2630 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_4 0x4A2634 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_5 0x4A2638 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_6 0x4A263C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_7 0x4A2640 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_8 0x4A2644 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_9 0x4A2648 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_10 0x4A264C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_11 0x4A2650 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_12 0x4A2654 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_13 0x4A2658 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_14 0x4A265C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_15 0x4A2660 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0 0x4A2664 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_1 0x4A2668 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_2 0x4A266C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_3 0x4A2670 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_4 0x4A2674 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_5 0x4A2678 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_6 0x4A267C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_7 0x4A2680 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_8 0x4A2684 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_9 0x4A2688 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_10 0x4A268C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_11 0x4A2690 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_12 0x4A2694 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_13 0x4A2698 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_14 0x4A269C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_15 0x4A26A0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0 0x4A26A4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_1 0x4A26A8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_2 0x4A26AC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_3 0x4A26B0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_4 0x4A26B4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_5 0x4A26B8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_6 0x4A26BC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_7 0x4A26C0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_8 0x4A26C4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_9 0x4A26C8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_10 0x4A26CC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_11 0x4A26D0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_12 0x4A26D4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_13 0x4A26D8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_14 0x4A26DC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_15 0x4A26E0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_0 0x4A26E4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_1 0x4A26E8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_2 0x4A26EC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_3 0x4A26F0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_4 0x4A26F4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_5 0x4A26F8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_6 0x4A26FC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_7 0x4A2700 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_8 0x4A2704 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_9 0x4A2708 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_10 0x4A270C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_11 0x4A2710 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_12 0x4A2714 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_13 0x4A2718 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_14 0x4A271C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_15 0x4A2720 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_0 0x4A2724 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_1 0x4A2728 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_2 0x4A272C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_3 0x4A2730 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_4 0x4A2734 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_5 0x4A2738 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_6 0x4A273C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_7 0x4A2740 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_8 0x4A2744 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_9 0x4A2748 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_10 0x4A274C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_11 0x4A2750 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_12 0x4A2754 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_13 0x4A2758 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_14 0x4A275C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_15 0x4A2760 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_0 0x4A2764 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_1 0x4A2768 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_2 0x4A276C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_3 0x4A2770 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_4 0x4A2774 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_5 0x4A2778 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_6 0x4A277C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_7 0x4A2780 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_8 0x4A2784 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_9 0x4A2788 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_10 0x4A278C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_11 0x4A2790 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_12 0x4A2794 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_13 0x4A2798 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_14 0x4A279C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_15 0x4A27A0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_0 0x4A27A4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_1 0x4A27A8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_2 0x4A27AC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_3 0x4A27B0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_4 0x4A27B4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_5 0x4A27B8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_6 0x4A27BC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_7 0x4A27C0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_8 0x4A27C4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_9 0x4A27C8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_10 0x4A27CC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_11 0x4A27D0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_12 0x4A27D4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_13 0x4A27D8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_14 0x4A27DC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_15 0x4A27E0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0 0x4A2824 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_1 0x4A2828 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_2 0x4A282C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_3 0x4A2830 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_4 0x4A2834 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_5 0x4A2838 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_6 0x4A283C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_7 0x4A2840 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_8 0x4A2844 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_9 0x4A2848 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_10 0x4A284C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_11 0x4A2850 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_12 0x4A2854 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_13 0x4A2858 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_14 0x4A285C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_15 0x4A2860 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0 0x4A2864 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_1 0x4A2868 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_2 0x4A286C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_3 0x4A2870 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_4 0x4A2874 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_5 0x4A2878 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_6 0x4A287C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_7 0x4A2880 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_8 0x4A2884 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_9 0x4A2888 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_10 0x4A288C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_11 0x4A2890 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_12 0x4A2894 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_13 0x4A2898 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_14 0x4A289C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_15 0x4A28A0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0 0x4A28A4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_1 0x4A28A8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_2 0x4A28AC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_3 0x4A28B0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_4 0x4A28B4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_5 0x4A28B8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_6 0x4A28BC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_7 0x4A28C0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_8 0x4A28C4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_9 0x4A28C8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_10 0x4A28CC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_11 0x4A28D0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_12 0x4A28D4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_13 0x4A28D8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_14 0x4A28DC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_15 0x4A28E0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0 0x4A28E4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_1 0x4A28E8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_2 0x4A28EC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_3 0x4A28F0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_4 0x4A28F4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_5 0x4A28F8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_6 0x4A28FC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_7 0x4A2900 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_8 0x4A2904 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_9 0x4A2908 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_10 0x4A290C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_11 0x4A2910 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_12 0x4A2914 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_13 0x4A2918 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_14 0x4A291C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_15 0x4A2920 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_0 0x4A2924 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_1 0x4A2928 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_2 0x4A292C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_3 0x4A2930 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_4 0x4A2934 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_5 0x4A2938 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_6 0x4A293C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_7 0x4A2940 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_8 0x4A2944 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_9 0x4A2948 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_10 0x4A294C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_11 0x4A2950 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_12 0x4A2954 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_13 0x4A2958 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_14 0x4A295C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_15 0x4A2960 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_0 0x4A2964 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_1 0x4A2968 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_2 0x4A296C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_3 0x4A2970 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_4 0x4A2974 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_5 0x4A2978 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_6 0x4A297C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_7 0x4A2980 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_8 0x4A2984 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_9 0x4A2988 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_10 0x4A298C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_11 0x4A2990 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_12 0x4A2994 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_13 0x4A2998 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_14 0x4A299C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_15 0x4A29A0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_0 0x4A29A4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_1 0x4A29A8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_2 0x4A29AC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_3 0x4A29B0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_4 0x4A29B4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_5 0x4A29B8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_6 0x4A29BC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_7 0x4A29C0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_8 0x4A29C4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_9 0x4A29C8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_10 0x4A29CC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_11 0x4A29D0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_12 0x4A29D4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_13 0x4A29D8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_14 0x4A29DC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_15 0x4A29E0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_0 0x4A29E4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_1 0x4A29E8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_2 0x4A29EC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_3 0x4A29F0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_4 0x4A29F4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_5 0x4A29F8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_6 0x4A29FC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_7 0x4A2A00 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_8 0x4A2A04 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_9 0x4A2A08 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_10 0x4A2A0C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_11 0x4A2A10 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_12 0x4A2A14 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_13 0x4A2A18 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_14 0x4A2A1C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_15 0x4A2A20 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_HIT_AW 0x4A2A64 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_HIT_AR 0x4A2A68 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_HIT_AW 0x4A2A6C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_HIT_AR 0x4A2A70 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_CFG 0x4A2B64 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_SHIFT 0x4A2B68 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_0 0x4A2B6C + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_1 0x4A2B70 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_2 0x4A2B74 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_3 0x4A2B78 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_4 0x4A2B7C + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_5 0x4A2B80 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_6 0x4A2B84 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_7 0x4A2B88 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_0 0x4A2BAC + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_1 0x4A2BB0 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_2 0x4A2BB4 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_3 0x4A2BB8 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_4 0x4A2BBC + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_5 0x4A2BC0 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_6 0x4A2BC4 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_7 0x4A2BC8 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_0 0x4A2BEC + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_1 0x4A2BF0 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_2 0x4A2BF4 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_3 0x4A2BF8 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_4 0x4A2BFC + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_5 0x4A2C00 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_6 0x4A2C04 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_7 0x4A2C08 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_WDT 0x4A2C2C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_WRAP 0x4A2C30 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_WRAP 0x4A2C34 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_WRAP 0x4A2C38 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_WRAP 0x4A2C3C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_WRAP 0x4A2C40 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_WRAP 0x4A2C44 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_WRAP 0x4A2C48 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_WRAP 0x4A2C4C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_CNT 0x4A2C50 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_CNT 0x4A2C54 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_CNT 0x4A2C58 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_CNT 0x4A2C5C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_CNT 0x4A2C60 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_CNT 0x4A2C64 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_CNT 0x4A2C68 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_CNT 0x4A2C6C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_WRAP 0x4A2C70 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_WRAP 0x4A2C74 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_WRAP 0x4A2C78 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_WRAP 0x4A2C7C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_WRAP 0x4A2C80 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_WRAP 0x4A2C84 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_WRAP 0x4A2C88 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_WRAP 0x4A2C8C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_CNT 0x4A2C90 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_CNT 0x4A2C94 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_CNT 0x4A2C98 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_CNT 0x4A2C9C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_CNT 0x4A2CA0 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_CNT 0x4A2CA4 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_CNT 0x4A2CA8 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_CNT 0x4A2CAC + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_PC_SEL_0 0x4A2CB0 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_PC_SEL_1 0x4A2CB4 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_PC_SEL_2 0x4A2CB8 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_PC_SEL_3 0x4A2CBC + +#endif /* ASIC_REG_DMA_IF_E_S_DOWN_CH1_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_s_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_s_regs.h new file mode 100644 index 000000000000..78c18da7154b --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_s_regs.h @@ -0,0 +1,860 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_E_S_REGS_H_ +#define ASIC_REG_DMA_IF_E_S_REGS_H_ + +/* + ***************************************** + * DMA_IF_E_S (Prototype: DMA_IF) + ***************************************** + */ + +#define mmDMA_IF_E_S_HBM0_WR_CRED_CNT 0x4A0000 + +#define mmDMA_IF_E_S_HBM1_WR_CRED_CNT 0x4A0004 + +#define mmDMA_IF_E_S_HBM0_RD_CRED_CNT 0x4A0008 + +#define mmDMA_IF_E_S_HBM1_RD_CRED_CNT 0x4A000C + +#define mmDMA_IF_E_S_HBM_LIMITER_0 0x4A0030 + +#define mmDMA_IF_E_S_HBM_LIMITER_1 0x4A0034 + +#define mmDMA_IF_E_S_HBM_LIMITER_2 0x4A0038 + +#define mmDMA_IF_E_S_HBM_LIMITER_3 0x4A003C + +#define mmDMA_IF_E_S_HBM_ALMOST_EN_0 0x4A0040 + +#define mmDMA_IF_E_S_HBM_ALMOST_EN_1 0x4A0044 + +#define mmDMA_IF_E_S_HBM_CRED_EN_0 0x4A0050 + +#define mmDMA_IF_E_S_HBM_CRED_EN_1 0x4A0054 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_0 0x4A0100 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_1 0x4A0104 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_2 0x4A0108 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_3 0x4A010C + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_4 0x4A0110 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_5 0x4A0114 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_6 0x4A0118 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_7 0x4A011C + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_8 0x4A0120 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_9 0x4A0124 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_10 0x4A0128 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_11 0x4A012C + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_12 0x4A0130 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_13 0x4A0134 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_14 0x4A0138 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_15 0x4A013C + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_0 0x4A0140 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_1 0x4A0144 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_2 0x4A0148 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_3 0x4A014C + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_4 0x4A0150 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_5 0x4A0154 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_6 0x4A0158 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_7 0x4A015C + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_8 0x4A0160 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_9 0x4A0164 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_10 0x4A0168 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_11 0x4A016C + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_12 0x4A0170 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_13 0x4A0174 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_14 0x4A0178 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_15 0x4A017C + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_0 0x4A0180 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_1 0x4A0184 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_2 0x4A0188 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_3 0x4A018C + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_4 0x4A0190 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_5 0x4A0194 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_6 0x4A0198 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_7 0x4A019C + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_8 0x4A01A0 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_9 0x4A01A4 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_10 0x4A01A8 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_11 0x4A01AC + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_12 0x4A01B0 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_13 0x4A01B4 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_14 0x4A01B8 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_15 0x4A01BC + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_0 0x4A01C0 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_1 0x4A01C4 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_2 0x4A01C8 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_3 0x4A01CC + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_4 0x4A01D0 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_5 0x4A01D4 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_6 0x4A01D8 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_7 0x4A01DC + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_8 0x4A01E0 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_9 0x4A01E4 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_10 0x4A01E8 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_11 0x4A01EC + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_12 0x4A01F0 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_13 0x4A01F4 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_14 0x4A01F8 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_15 0x4A01FC + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_0 0x4A0200 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_1 0x4A0204 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_2 0x4A0208 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_3 0x4A020C + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_4 0x4A0210 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_5 0x4A0214 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_6 0x4A0218 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_7 0x4A021C + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_8 0x4A0220 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_9 0x4A0224 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_10 0x4A0228 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_11 0x4A022C + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_12 0x4A0230 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_13 0x4A0234 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_14 0x4A0238 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_15 0x4A023C + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_0 0x4A0240 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_1 0x4A0244 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_2 0x4A0248 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_3 0x4A024C + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_4 0x4A0250 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_5 0x4A0254 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_6 0x4A0258 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_7 0x4A025C + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_8 0x4A0260 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_9 0x4A0264 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_10 0x4A0268 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_11 0x4A026C + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_12 0x4A0270 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_13 0x4A0274 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_14 0x4A0278 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_15 0x4A027C + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_0 0x4A0280 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_1 0x4A0284 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_2 0x4A0288 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_3 0x4A028C + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_4 0x4A0290 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_5 0x4A0294 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_6 0x4A0298 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_7 0x4A029C + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_8 0x4A02A0 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_9 0x4A02A4 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_10 0x4A02A8 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_11 0x4A02AC + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_12 0x4A02B0 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_13 0x4A02B4 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_14 0x4A02B8 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_15 0x4A02BC + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_0 0x4A02C0 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_1 0x4A02C4 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_2 0x4A02C8 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_3 0x4A02CC + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_4 0x4A02D0 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_5 0x4A02D4 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_6 0x4A02D8 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_7 0x4A02DC + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_8 0x4A02E0 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_9 0x4A02E4 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_10 0x4A02E8 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_11 0x4A02EC + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_12 0x4A02F0 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_13 0x4A02F4 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_14 0x4A02F8 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_15 0x4A02FC + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_0 0x4A0300 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_1 0x4A0304 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_2 0x4A0308 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_3 0x4A030C + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_4 0x4A0310 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_5 0x4A0314 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_6 0x4A0318 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_7 0x4A031C + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_8 0x4A0320 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_9 0x4A0324 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_10 0x4A0328 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_11 0x4A032C + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_12 0x4A0330 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_13 0x4A0334 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_14 0x4A0338 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_15 0x4A033C + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_0 0x4A0340 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_1 0x4A0344 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_2 0x4A0348 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_3 0x4A034C + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_4 0x4A0350 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_5 0x4A0354 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_6 0x4A0358 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_7 0x4A035C + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_8 0x4A0360 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_9 0x4A0364 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_10 0x4A0368 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_11 0x4A036C + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_12 0x4A0370 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_13 0x4A0374 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_14 0x4A0378 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_15 0x4A037C + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_0 0x4A0380 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_1 0x4A0384 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_2 0x4A0388 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_3 0x4A038C + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_4 0x4A0390 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_5 0x4A0394 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_6 0x4A0398 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_7 0x4A039C + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_8 0x4A03A0 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_9 0x4A03A4 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_10 0x4A03A8 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_11 0x4A03AC + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_12 0x4A03B0 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_13 0x4A03B4 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_14 0x4A03B8 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_15 0x4A03BC + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_0 0x4A03C0 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_1 0x4A03C4 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_2 0x4A03C8 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_3 0x4A03CC + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_4 0x4A03D0 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_5 0x4A03D4 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_6 0x4A03D8 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_7 0x4A03DC + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_8 0x4A03E0 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_9 0x4A03E4 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_10 0x4A03E8 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_11 0x4A03EC + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_12 0x4A03F0 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_13 0x4A03F4 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_14 0x4A03F8 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_15 0x4A03FC + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_0 0x4A0400 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_1 0x4A0404 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_2 0x4A0408 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_3 0x4A040C + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_4 0x4A0410 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_5 0x4A0414 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_6 0x4A0418 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_7 0x4A041C + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_8 0x4A0420 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_9 0x4A0424 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_10 0x4A0428 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_11 0x4A042C + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_12 0x4A0430 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_13 0x4A0434 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_14 0x4A0438 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_15 0x4A043C + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_0 0x4A0440 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_1 0x4A0444 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_2 0x4A0448 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_3 0x4A044C + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_4 0x4A0450 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_5 0x4A0454 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_6 0x4A0458 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_7 0x4A045C + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_8 0x4A0460 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_9 0x4A0464 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_10 0x4A0468 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_11 0x4A046C + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_12 0x4A0470 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_13 0x4A0474 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_14 0x4A0478 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_15 0x4A047C + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_0 0x4A0480 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_1 0x4A0484 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_2 0x4A0488 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_3 0x4A048C + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_4 0x4A0490 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_5 0x4A0494 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_6 0x4A0498 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_7 0x4A049C + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_8 0x4A04A0 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_9 0x4A04A4 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_10 0x4A04A8 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_11 0x4A04AC + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_12 0x4A04B0 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_13 0x4A04B4 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_14 0x4A04B8 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_15 0x4A04BC + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_0 0x4A04C0 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_1 0x4A04C4 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_2 0x4A04C8 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_3 0x4A04CC + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_4 0x4A04D0 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_5 0x4A04D4 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_6 0x4A04D8 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_7 0x4A04DC + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_8 0x4A04E0 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_9 0x4A04E4 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_10 0x4A04E8 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_11 0x4A04EC + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_12 0x4A04F0 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_13 0x4A04F4 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_14 0x4A04F8 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_15 0x4A04FC + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_0 0x4A0500 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_1 0x4A0504 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_2 0x4A0508 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_3 0x4A050C + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_4 0x4A0510 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_5 0x4A0514 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_6 0x4A0518 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_7 0x4A051C + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_8 0x4A0520 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_9 0x4A0524 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_10 0x4A0528 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_11 0x4A052C + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_12 0x4A0530 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_13 0x4A0534 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_14 0x4A0538 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_15 0x4A053C + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_0 0x4A0540 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_1 0x4A0544 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_2 0x4A0548 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_3 0x4A054C + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_4 0x4A0550 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_5 0x4A0554 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_6 0x4A0558 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_7 0x4A055C + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_8 0x4A0560 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_9 0x4A0564 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_10 0x4A0568 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_11 0x4A056C + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_12 0x4A0570 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_13 0x4A0574 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_14 0x4A0578 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_15 0x4A057C + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_0 0x4A0580 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_1 0x4A0584 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_2 0x4A0588 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_3 0x4A058C + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_4 0x4A0590 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_5 0x4A0594 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_6 0x4A0598 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_7 0x4A059C + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_8 0x4A05A0 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_9 0x4A05A4 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_10 0x4A05A8 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_11 0x4A05AC + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_12 0x4A05B0 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_13 0x4A05B4 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_14 0x4A05B8 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_15 0x4A05BC + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_0 0x4A05C0 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_1 0x4A05C4 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_2 0x4A05C8 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_3 0x4A05CC + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_4 0x4A05D0 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_5 0x4A05D4 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_6 0x4A05D8 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_7 0x4A05DC + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_8 0x4A05E0 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_9 0x4A05E4 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_10 0x4A05E8 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_11 0x4A05EC + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_12 0x4A05F0 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_13 0x4A05F4 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_14 0x4A05F8 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_15 0x4A05FC + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_0 0x4A0600 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_1 0x4A0604 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_2 0x4A0608 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_3 0x4A060C + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_4 0x4A0610 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_5 0x4A0614 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_6 0x4A0618 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_7 0x4A061C + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_8 0x4A0620 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_9 0x4A0624 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_10 0x4A0628 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_11 0x4A062C + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_12 0x4A0630 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_13 0x4A0634 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_14 0x4A0638 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_15 0x4A063C + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_0 0x4A0640 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_1 0x4A0644 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_2 0x4A0648 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_3 0x4A064C + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_4 0x4A0650 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_5 0x4A0654 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_6 0x4A0658 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_7 0x4A065C + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_8 0x4A0660 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_9 0x4A0664 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_10 0x4A0668 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_11 0x4A066C + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_12 0x4A0670 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_13 0x4A0674 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_14 0x4A0678 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_15 0x4A067C + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_0 0x4A0680 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_1 0x4A0684 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_2 0x4A0688 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_3 0x4A068C + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_4 0x4A0690 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_5 0x4A0694 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_6 0x4A0698 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_7 0x4A069C + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_8 0x4A06A0 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_9 0x4A06A4 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_10 0x4A06A8 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_11 0x4A06AC + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_12 0x4A06B0 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_13 0x4A06B4 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_14 0x4A06B8 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_15 0x4A06BC + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_0 0x4A06C0 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_1 0x4A06C4 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_2 0x4A06C8 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_3 0x4A06CC + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_4 0x4A06D0 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_5 0x4A06D4 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_6 0x4A06D8 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_7 0x4A06DC + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_8 0x4A06E0 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_9 0x4A06E4 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_10 0x4A06E8 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_11 0x4A06EC + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_12 0x4A06F0 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_13 0x4A06F4 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_14 0x4A06F8 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_15 0x4A06FC + +#define mmDMA_IF_E_S_SOB_HIT_RPROT 0x4A0700 + +#define mmDMA_IF_E_S_SOB_HIT_WPROT 0x4A0704 + +#define mmDMA_IF_E_S_SOB_HIT_RPRIV 0x4A070C + +#define mmDMA_IF_E_S_SOB_HIT_WPRIV 0x4A0710 + +#define mmDMA_IF_E_S_DMA0_HIT_RPROT 0x4A071C + +#define mmDMA_IF_E_S_DMA0_HIT_WPROT 0x4A0720 + +#define mmDMA_IF_E_S_DMA0_HIT_RPRIV 0x4A0724 + +#define mmDMA_IF_E_S_DMA0_HIT_WPRIV 0x4A0728 + +#define mmDMA_IF_E_S_DMA1_HIT_RPROT 0x4A0730 + +#define mmDMA_IF_E_S_DMA1_HIT_WPROT 0x4A0734 + +#define mmDMA_IF_E_S_DMA1_HIT_RPRIV 0x4A0738 + +#define mmDMA_IF_E_S_DMA1_HIT_WPRIV 0x4A073C + +#define mmDMA_IF_E_S_HBM_BIN 0x4A0800 + +#define mmDMA_IF_E_S_MME_BIN 0x4A0804 + +#define mmDMA_IF_E_S_TPC_BIN 0x4A0808 + +#define mmDMA_IF_E_S_DMA_BIN 0x4A080C + +#define mmDMA_IF_E_S_SOB_CG_EN 0x4A0810 + +#define mmDMA_IF_E_S_HBM_I2C_ADDR_0 0x4A0820 + +#define mmDMA_IF_E_S_HBM_I2C_ADDR_1 0x4A0824 + +#define mmDMA_IF_E_S_HBM_I2C_ADDR_2 0x4A0828 + +#define mmDMA_IF_E_S_HBM_I2C_ADDR_3 0x4A082C + +#define mmDMA_IF_E_S_HBM_I2C_ADDR_4 0x4A0830 + +#define mmDMA_IF_E_S_HBM_MISC 0x4A0834 + +#endif /* ASIC_REG_DMA_IF_E_S_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch0_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch0_regs.h new file mode 100644 index 000000000000..4ccaf8712948 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch0_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_W_N_DOWN_CH0_REGS_H_ +#define ASIC_REG_DMA_IF_W_N_DOWN_CH0_REGS_H_ + +/* + ***************************************** + * DMA_IF_W_N_DOWN_CH0 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmDMA_IF_W_N_DOWN_CH0_PERM_SEL 0x4C1108 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_0 0x4C1114 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_1 0x4C1118 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_2 0x4C111C + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_3 0x4C1120 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_4 0x4C1124 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_5 0x4C1128 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_6 0x4C112C + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_7 0x4C1130 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_8 0x4C1134 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_9 0x4C1138 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_10 0x4C113C + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_11 0x4C1140 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_12 0x4C1144 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_13 0x4C1148 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_14 0x4C114C + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_15 0x4C1150 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_16 0x4C1154 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_17 0x4C1158 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_18 0x4C115C + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_19 0x4C1160 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_20 0x4C1164 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_21 0x4C1168 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_22 0x4C116C + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_23 0x4C1170 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_24 0x4C1174 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_25 0x4C1178 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_26 0x4C117C + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_27 0x4C1180 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_0 0x4C1184 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_1 0x4C1188 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_2 0x4C118C + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_3 0x4C1190 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_4 0x4C1194 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_5 0x4C1198 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_6 0x4C119C + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_7 0x4C11A0 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_8 0x4C11A4 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_9 0x4C11A8 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_10 0x4C11AC + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_11 0x4C11B0 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_12 0x4C11B4 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_13 0x4C11B8 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_14 0x4C11BC + +#define mmDMA_IF_W_N_DOWN_CH0_SCRAM_SRAM_EN 0x4C126C + +#define mmDMA_IF_W_N_DOWN_CH0_RL_HBM_EN 0x4C1274 + +#define mmDMA_IF_W_N_DOWN_CH0_RL_HBM_SAT 0x4C1278 + +#define mmDMA_IF_W_N_DOWN_CH0_RL_HBM_RST 0x4C127C + +#define mmDMA_IF_W_N_DOWN_CH0_RL_HBM_TIMEOUT 0x4C1280 + +#define mmDMA_IF_W_N_DOWN_CH0_SCRAM_HBM_EN 0x4C1284 + +#define mmDMA_IF_W_N_DOWN_CH0_RL_PCI_EN 0x4C1288 + +#define mmDMA_IF_W_N_DOWN_CH0_RL_PCI_SAT 0x4C128C + +#define mmDMA_IF_W_N_DOWN_CH0_RL_PCI_RST 0x4C1290 + +#define mmDMA_IF_W_N_DOWN_CH0_RL_PCI_TIMEOUT 0x4C1294 + +#define mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_EN 0x4C129C + +#define mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_SAT 0x4C12A0 + +#define mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_RST 0x4C12A4 + +#define mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_TIMEOUT 0x4C12AC + +#define mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_RED 0x4C12B4 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_EN 0x4C12EC + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_EN 0x4C12F0 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_WR_SIZE 0x4C12F4 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_WR_SIZE 0x4C12F8 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_PCI_CTR_SET_EN 0x4C1404 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_PCI_CTR_SET 0x4C1408 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_PCI_CTR_WRAP 0x4C140C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_PCI_CTR_CNT 0x4C1410 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM_CTR_SET_EN 0x4C1414 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM_CTR_SET 0x4C1418 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_RD_SIZE 0x4C141C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_RD_SIZE 0x4C1420 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_PCI_CTR_SET_EN 0x4C1424 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_PCI_CTR_SET 0x4C1428 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_PCI_CTR_WRAP 0x4C142C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_PCI_CTR_CNT 0x4C1430 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM_CTR_SET_EN 0x4C1434 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM_CTR_SET 0x4C1438 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_SEL_0 0x4C1450 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_SEL_1 0x4C1454 + +#define mmDMA_IF_W_N_DOWN_CH0_NON_LIN_EN 0x4C1480 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_BANK_0 0x4C1500 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_BANK_1 0x4C1504 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_BANK_2 0x4C1508 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_BANK_3 0x4C150C + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_BANK_4 0x4C1510 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_0 0x4C1514 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_1 0x4C1520 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_2 0x4C1524 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_3 0x4C1528 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_4 0x4C152C + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_5 0x4C1530 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_6 0x4C1534 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_7 0x4C1538 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_8 0x4C153C + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_9 0x4C1540 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_0 0x4C1550 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_1 0x4C1554 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_2 0x4C1558 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_3 0x4C155C + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_4 0x4C1560 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_5 0x4C1564 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_6 0x4C1568 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_7 0x4C156C + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_8 0x4C1570 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_9 0x4C1574 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_10 0x4C1578 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_11 0x4C157C + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_12 0x4C1580 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_13 0x4C1584 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_14 0x4C1588 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_15 0x4C158C + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_16 0x4C1590 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_17 0x4C1594 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_18 0x4C1598 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0 0x4C15E4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_1 0x4C15E8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_2 0x4C15EC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_3 0x4C15F0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_4 0x4C15F4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_5 0x4C15F8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_6 0x4C15FC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_7 0x4C1600 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_8 0x4C1604 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_9 0x4C1608 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_10 0x4C160C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_11 0x4C1610 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_12 0x4C1614 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_13 0x4C1618 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_14 0x4C161C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_15 0x4C1620 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0 0x4C1624 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_1 0x4C1628 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_2 0x4C162C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_3 0x4C1630 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_4 0x4C1634 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_5 0x4C1638 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_6 0x4C163C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_7 0x4C1640 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_8 0x4C1644 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_9 0x4C1648 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_10 0x4C164C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_11 0x4C1650 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_12 0x4C1654 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_13 0x4C1658 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_14 0x4C165C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_15 0x4C1660 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0 0x4C1664 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_1 0x4C1668 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_2 0x4C166C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_3 0x4C1670 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_4 0x4C1674 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_5 0x4C1678 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_6 0x4C167C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_7 0x4C1680 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_8 0x4C1684 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_9 0x4C1688 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_10 0x4C168C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_11 0x4C1690 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_12 0x4C1694 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_13 0x4C1698 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_14 0x4C169C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_15 0x4C16A0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0 0x4C16A4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_1 0x4C16A8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_2 0x4C16AC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_3 0x4C16B0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_4 0x4C16B4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_5 0x4C16B8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_6 0x4C16BC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_7 0x4C16C0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_8 0x4C16C4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_9 0x4C16C8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_10 0x4C16CC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_11 0x4C16D0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_12 0x4C16D4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_13 0x4C16D8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_14 0x4C16DC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_15 0x4C16E0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_0 0x4C16E4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_1 0x4C16E8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_2 0x4C16EC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_3 0x4C16F0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_4 0x4C16F4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_5 0x4C16F8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_6 0x4C16FC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_7 0x4C1700 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_8 0x4C1704 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_9 0x4C1708 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_10 0x4C170C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_11 0x4C1710 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_12 0x4C1714 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_13 0x4C1718 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_14 0x4C171C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_15 0x4C1720 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_0 0x4C1724 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_1 0x4C1728 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_2 0x4C172C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_3 0x4C1730 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_4 0x4C1734 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_5 0x4C1738 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_6 0x4C173C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_7 0x4C1740 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_8 0x4C1744 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_9 0x4C1748 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_10 0x4C174C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_11 0x4C1750 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_12 0x4C1754 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_13 0x4C1758 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_14 0x4C175C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_15 0x4C1760 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_0 0x4C1764 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_1 0x4C1768 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_2 0x4C176C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_3 0x4C1770 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_4 0x4C1774 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_5 0x4C1778 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_6 0x4C177C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_7 0x4C1780 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_8 0x4C1784 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_9 0x4C1788 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_10 0x4C178C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_11 0x4C1790 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_12 0x4C1794 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_13 0x4C1798 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_14 0x4C179C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_15 0x4C17A0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_0 0x4C17A4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_1 0x4C17A8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_2 0x4C17AC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_3 0x4C17B0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_4 0x4C17B4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_5 0x4C17B8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_6 0x4C17BC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_7 0x4C17C0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_8 0x4C17C4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_9 0x4C17C8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_10 0x4C17CC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_11 0x4C17D0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_12 0x4C17D4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_13 0x4C17D8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_14 0x4C17DC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_15 0x4C17E0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0 0x4C1824 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_1 0x4C1828 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_2 0x4C182C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_3 0x4C1830 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_4 0x4C1834 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_5 0x4C1838 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_6 0x4C183C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_7 0x4C1840 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_8 0x4C1844 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_9 0x4C1848 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_10 0x4C184C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_11 0x4C1850 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_12 0x4C1854 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_13 0x4C1858 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_14 0x4C185C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_15 0x4C1860 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0 0x4C1864 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_1 0x4C1868 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_2 0x4C186C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_3 0x4C1870 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_4 0x4C1874 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_5 0x4C1878 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_6 0x4C187C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_7 0x4C1880 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_8 0x4C1884 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_9 0x4C1888 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_10 0x4C188C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_11 0x4C1890 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_12 0x4C1894 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_13 0x4C1898 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_14 0x4C189C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_15 0x4C18A0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0 0x4C18A4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_1 0x4C18A8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_2 0x4C18AC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_3 0x4C18B0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_4 0x4C18B4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_5 0x4C18B8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_6 0x4C18BC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_7 0x4C18C0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_8 0x4C18C4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_9 0x4C18C8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_10 0x4C18CC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_11 0x4C18D0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_12 0x4C18D4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_13 0x4C18D8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_14 0x4C18DC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_15 0x4C18E0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0 0x4C18E4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_1 0x4C18E8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_2 0x4C18EC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_3 0x4C18F0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_4 0x4C18F4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_5 0x4C18F8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_6 0x4C18FC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_7 0x4C1900 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_8 0x4C1904 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_9 0x4C1908 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_10 0x4C190C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_11 0x4C1910 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_12 0x4C1914 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_13 0x4C1918 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_14 0x4C191C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_15 0x4C1920 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_0 0x4C1924 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_1 0x4C1928 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_2 0x4C192C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_3 0x4C1930 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_4 0x4C1934 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_5 0x4C1938 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_6 0x4C193C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_7 0x4C1940 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_8 0x4C1944 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_9 0x4C1948 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_10 0x4C194C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_11 0x4C1950 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_12 0x4C1954 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_13 0x4C1958 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_14 0x4C195C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_15 0x4C1960 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_0 0x4C1964 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_1 0x4C1968 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_2 0x4C196C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_3 0x4C1970 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_4 0x4C1974 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_5 0x4C1978 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_6 0x4C197C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_7 0x4C1980 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_8 0x4C1984 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_9 0x4C1988 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_10 0x4C198C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_11 0x4C1990 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_12 0x4C1994 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_13 0x4C1998 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_14 0x4C199C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_15 0x4C19A0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_0 0x4C19A4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_1 0x4C19A8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_2 0x4C19AC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_3 0x4C19B0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_4 0x4C19B4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_5 0x4C19B8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_6 0x4C19BC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_7 0x4C19C0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_8 0x4C19C4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_9 0x4C19C8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_10 0x4C19CC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_11 0x4C19D0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_12 0x4C19D4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_13 0x4C19D8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_14 0x4C19DC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_15 0x4C19E0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_0 0x4C19E4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_1 0x4C19E8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_2 0x4C19EC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_3 0x4C19F0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_4 0x4C19F4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_5 0x4C19F8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_6 0x4C19FC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_7 0x4C1A00 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_8 0x4C1A04 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_9 0x4C1A08 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_10 0x4C1A0C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_11 0x4C1A10 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_12 0x4C1A14 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_13 0x4C1A18 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_14 0x4C1A1C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_15 0x4C1A20 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_HIT_AW 0x4C1A64 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_HIT_AR 0x4C1A68 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_HIT_AW 0x4C1A6C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_HIT_AR 0x4C1A70 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_CFG 0x4C1B64 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_SHIFT 0x4C1B68 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_0 0x4C1B6C + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_1 0x4C1B70 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_2 0x4C1B74 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_3 0x4C1B78 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_4 0x4C1B7C + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_5 0x4C1B80 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_6 0x4C1B84 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_7 0x4C1B88 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_0 0x4C1BAC + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_1 0x4C1BB0 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_2 0x4C1BB4 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_3 0x4C1BB8 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_4 0x4C1BBC + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_5 0x4C1BC0 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_6 0x4C1BC4 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_7 0x4C1BC8 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_0 0x4C1BEC + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_1 0x4C1BF0 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_2 0x4C1BF4 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_3 0x4C1BF8 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_4 0x4C1BFC + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_5 0x4C1C00 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_6 0x4C1C04 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_7 0x4C1C08 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_WDT 0x4C1C2C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_WRAP 0x4C1C30 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_WRAP 0x4C1C34 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_WRAP 0x4C1C38 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_WRAP 0x4C1C3C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_WRAP 0x4C1C40 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_WRAP 0x4C1C44 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_WRAP 0x4C1C48 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_WRAP 0x4C1C4C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_CNT 0x4C1C50 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_CNT 0x4C1C54 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_CNT 0x4C1C58 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_CNT 0x4C1C5C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_CNT 0x4C1C60 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_CNT 0x4C1C64 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_CNT 0x4C1C68 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_CNT 0x4C1C6C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_WRAP 0x4C1C70 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_WRAP 0x4C1C74 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_WRAP 0x4C1C78 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_WRAP 0x4C1C7C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_WRAP 0x4C1C80 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_WRAP 0x4C1C84 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_WRAP 0x4C1C88 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_WRAP 0x4C1C8C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_CNT 0x4C1C90 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_CNT 0x4C1C94 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_CNT 0x4C1C98 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_CNT 0x4C1C9C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_CNT 0x4C1CA0 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_CNT 0x4C1CA4 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_CNT 0x4C1CA8 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_CNT 0x4C1CAC + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_PC_SEL_0 0x4C1CB0 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_PC_SEL_1 0x4C1CB4 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_PC_SEL_2 0x4C1CB8 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_PC_SEL_3 0x4C1CBC + +#endif /* ASIC_REG_DMA_IF_W_N_DOWN_CH0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch1_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch1_regs.h new file mode 100644 index 000000000000..9236f4183084 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch1_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_W_N_DOWN_CH1_REGS_H_ +#define ASIC_REG_DMA_IF_W_N_DOWN_CH1_REGS_H_ + +/* + ***************************************** + * DMA_IF_W_N_DOWN_CH1 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmDMA_IF_W_N_DOWN_CH1_PERM_SEL 0x4C2108 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_0 0x4C2114 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_1 0x4C2118 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_2 0x4C211C + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_3 0x4C2120 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_4 0x4C2124 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_5 0x4C2128 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_6 0x4C212C + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_7 0x4C2130 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_8 0x4C2134 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_9 0x4C2138 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_10 0x4C213C + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_11 0x4C2140 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_12 0x4C2144 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_13 0x4C2148 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_14 0x4C214C + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_15 0x4C2150 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_16 0x4C2154 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_17 0x4C2158 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_18 0x4C215C + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_19 0x4C2160 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_20 0x4C2164 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_21 0x4C2168 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_22 0x4C216C + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_23 0x4C2170 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_24 0x4C2174 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_25 0x4C2178 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_26 0x4C217C + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_27 0x4C2180 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_0 0x4C2184 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_1 0x4C2188 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_2 0x4C218C + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_3 0x4C2190 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_4 0x4C2194 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_5 0x4C2198 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_6 0x4C219C + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_7 0x4C21A0 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_8 0x4C21A4 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_9 0x4C21A8 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_10 0x4C21AC + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_11 0x4C21B0 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_12 0x4C21B4 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_13 0x4C21B8 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_14 0x4C21BC + +#define mmDMA_IF_W_N_DOWN_CH1_SCRAM_SRAM_EN 0x4C226C + +#define mmDMA_IF_W_N_DOWN_CH1_RL_HBM_EN 0x4C2274 + +#define mmDMA_IF_W_N_DOWN_CH1_RL_HBM_SAT 0x4C2278 + +#define mmDMA_IF_W_N_DOWN_CH1_RL_HBM_RST 0x4C227C + +#define mmDMA_IF_W_N_DOWN_CH1_RL_HBM_TIMEOUT 0x4C2280 + +#define mmDMA_IF_W_N_DOWN_CH1_SCRAM_HBM_EN 0x4C2284 + +#define mmDMA_IF_W_N_DOWN_CH1_RL_PCI_EN 0x4C2288 + +#define mmDMA_IF_W_N_DOWN_CH1_RL_PCI_SAT 0x4C228C + +#define mmDMA_IF_W_N_DOWN_CH1_RL_PCI_RST 0x4C2290 + +#define mmDMA_IF_W_N_DOWN_CH1_RL_PCI_TIMEOUT 0x4C2294 + +#define mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_EN 0x4C229C + +#define mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_SAT 0x4C22A0 + +#define mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_RST 0x4C22A4 + +#define mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_TIMEOUT 0x4C22AC + +#define mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_RED 0x4C22B4 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_EN 0x4C22EC + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_EN 0x4C22F0 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_WR_SIZE 0x4C22F4 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_WR_SIZE 0x4C22F8 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_PCI_CTR_SET_EN 0x4C2404 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_PCI_CTR_SET 0x4C2408 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_PCI_CTR_WRAP 0x4C240C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_PCI_CTR_CNT 0x4C2410 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM_CTR_SET_EN 0x4C2414 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM_CTR_SET 0x4C2418 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_RD_SIZE 0x4C241C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_RD_SIZE 0x4C2420 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_PCI_CTR_SET_EN 0x4C2424 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_PCI_CTR_SET 0x4C2428 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_PCI_CTR_WRAP 0x4C242C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_PCI_CTR_CNT 0x4C2430 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM_CTR_SET_EN 0x4C2434 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM_CTR_SET 0x4C2438 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_SEL_0 0x4C2450 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_SEL_1 0x4C2454 + +#define mmDMA_IF_W_N_DOWN_CH1_NON_LIN_EN 0x4C2480 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_BANK_0 0x4C2500 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_BANK_1 0x4C2504 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_BANK_2 0x4C2508 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_BANK_3 0x4C250C + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_BANK_4 0x4C2510 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_0 0x4C2514 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_1 0x4C2520 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_2 0x4C2524 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_3 0x4C2528 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_4 0x4C252C + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_5 0x4C2530 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_6 0x4C2534 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_7 0x4C2538 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_8 0x4C253C + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_9 0x4C2540 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_0 0x4C2550 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_1 0x4C2554 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_2 0x4C2558 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_3 0x4C255C + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_4 0x4C2560 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_5 0x4C2564 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_6 0x4C2568 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_7 0x4C256C + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_8 0x4C2570 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_9 0x4C2574 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_10 0x4C2578 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_11 0x4C257C + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_12 0x4C2580 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_13 0x4C2584 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_14 0x4C2588 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_15 0x4C258C + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_16 0x4C2590 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_17 0x4C2594 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_18 0x4C2598 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0 0x4C25E4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_1 0x4C25E8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_2 0x4C25EC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_3 0x4C25F0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_4 0x4C25F4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_5 0x4C25F8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_6 0x4C25FC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_7 0x4C2600 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_8 0x4C2604 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_9 0x4C2608 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_10 0x4C260C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_11 0x4C2610 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_12 0x4C2614 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_13 0x4C2618 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_14 0x4C261C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_15 0x4C2620 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0 0x4C2624 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_1 0x4C2628 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_2 0x4C262C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_3 0x4C2630 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_4 0x4C2634 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_5 0x4C2638 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_6 0x4C263C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_7 0x4C2640 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_8 0x4C2644 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_9 0x4C2648 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_10 0x4C264C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_11 0x4C2650 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_12 0x4C2654 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_13 0x4C2658 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_14 0x4C265C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_15 0x4C2660 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0 0x4C2664 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_1 0x4C2668 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_2 0x4C266C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_3 0x4C2670 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_4 0x4C2674 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_5 0x4C2678 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_6 0x4C267C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_7 0x4C2680 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_8 0x4C2684 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_9 0x4C2688 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_10 0x4C268C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_11 0x4C2690 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_12 0x4C2694 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_13 0x4C2698 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_14 0x4C269C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_15 0x4C26A0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0 0x4C26A4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_1 0x4C26A8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_2 0x4C26AC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_3 0x4C26B0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_4 0x4C26B4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_5 0x4C26B8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_6 0x4C26BC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_7 0x4C26C0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_8 0x4C26C4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_9 0x4C26C8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_10 0x4C26CC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_11 0x4C26D0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_12 0x4C26D4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_13 0x4C26D8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_14 0x4C26DC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_15 0x4C26E0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_0 0x4C26E4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_1 0x4C26E8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_2 0x4C26EC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_3 0x4C26F0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_4 0x4C26F4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_5 0x4C26F8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_6 0x4C26FC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_7 0x4C2700 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_8 0x4C2704 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_9 0x4C2708 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_10 0x4C270C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_11 0x4C2710 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_12 0x4C2714 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_13 0x4C2718 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_14 0x4C271C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_15 0x4C2720 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_0 0x4C2724 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_1 0x4C2728 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_2 0x4C272C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_3 0x4C2730 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_4 0x4C2734 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_5 0x4C2738 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_6 0x4C273C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_7 0x4C2740 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_8 0x4C2744 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_9 0x4C2748 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_10 0x4C274C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_11 0x4C2750 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_12 0x4C2754 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_13 0x4C2758 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_14 0x4C275C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_15 0x4C2760 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_0 0x4C2764 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_1 0x4C2768 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_2 0x4C276C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_3 0x4C2770 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_4 0x4C2774 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_5 0x4C2778 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_6 0x4C277C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_7 0x4C2780 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_8 0x4C2784 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_9 0x4C2788 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_10 0x4C278C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_11 0x4C2790 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_12 0x4C2794 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_13 0x4C2798 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_14 0x4C279C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_15 0x4C27A0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_0 0x4C27A4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_1 0x4C27A8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_2 0x4C27AC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_3 0x4C27B0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_4 0x4C27B4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_5 0x4C27B8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_6 0x4C27BC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_7 0x4C27C0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_8 0x4C27C4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_9 0x4C27C8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_10 0x4C27CC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_11 0x4C27D0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_12 0x4C27D4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_13 0x4C27D8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_14 0x4C27DC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_15 0x4C27E0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0 0x4C2824 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_1 0x4C2828 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_2 0x4C282C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_3 0x4C2830 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_4 0x4C2834 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_5 0x4C2838 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_6 0x4C283C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_7 0x4C2840 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_8 0x4C2844 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_9 0x4C2848 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_10 0x4C284C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_11 0x4C2850 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_12 0x4C2854 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_13 0x4C2858 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_14 0x4C285C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_15 0x4C2860 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0 0x4C2864 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_1 0x4C2868 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_2 0x4C286C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_3 0x4C2870 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_4 0x4C2874 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_5 0x4C2878 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_6 0x4C287C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_7 0x4C2880 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_8 0x4C2884 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_9 0x4C2888 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_10 0x4C288C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_11 0x4C2890 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_12 0x4C2894 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_13 0x4C2898 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_14 0x4C289C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_15 0x4C28A0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0 0x4C28A4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_1 0x4C28A8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_2 0x4C28AC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_3 0x4C28B0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_4 0x4C28B4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_5 0x4C28B8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_6 0x4C28BC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_7 0x4C28C0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_8 0x4C28C4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_9 0x4C28C8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_10 0x4C28CC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_11 0x4C28D0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_12 0x4C28D4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_13 0x4C28D8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_14 0x4C28DC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_15 0x4C28E0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0 0x4C28E4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_1 0x4C28E8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_2 0x4C28EC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_3 0x4C28F0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_4 0x4C28F4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_5 0x4C28F8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_6 0x4C28FC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_7 0x4C2900 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_8 0x4C2904 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_9 0x4C2908 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_10 0x4C290C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_11 0x4C2910 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_12 0x4C2914 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_13 0x4C2918 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_14 0x4C291C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_15 0x4C2920 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_0 0x4C2924 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_1 0x4C2928 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_2 0x4C292C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_3 0x4C2930 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_4 0x4C2934 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_5 0x4C2938 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_6 0x4C293C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_7 0x4C2940 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_8 0x4C2944 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_9 0x4C2948 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_10 0x4C294C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_11 0x4C2950 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_12 0x4C2954 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_13 0x4C2958 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_14 0x4C295C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_15 0x4C2960 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_0 0x4C2964 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_1 0x4C2968 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_2 0x4C296C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_3 0x4C2970 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_4 0x4C2974 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_5 0x4C2978 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_6 0x4C297C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_7 0x4C2980 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_8 0x4C2984 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_9 0x4C2988 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_10 0x4C298C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_11 0x4C2990 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_12 0x4C2994 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_13 0x4C2998 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_14 0x4C299C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_15 0x4C29A0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_0 0x4C29A4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_1 0x4C29A8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_2 0x4C29AC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_3 0x4C29B0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_4 0x4C29B4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_5 0x4C29B8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_6 0x4C29BC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_7 0x4C29C0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_8 0x4C29C4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_9 0x4C29C8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_10 0x4C29CC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_11 0x4C29D0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_12 0x4C29D4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_13 0x4C29D8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_14 0x4C29DC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_15 0x4C29E0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_0 0x4C29E4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_1 0x4C29E8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_2 0x4C29EC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_3 0x4C29F0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_4 0x4C29F4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_5 0x4C29F8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_6 0x4C29FC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_7 0x4C2A00 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_8 0x4C2A04 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_9 0x4C2A08 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_10 0x4C2A0C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_11 0x4C2A10 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_12 0x4C2A14 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_13 0x4C2A18 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_14 0x4C2A1C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_15 0x4C2A20 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_HIT_AW 0x4C2A64 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_HIT_AR 0x4C2A68 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_HIT_AW 0x4C2A6C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_HIT_AR 0x4C2A70 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_CFG 0x4C2B64 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_SHIFT 0x4C2B68 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_0 0x4C2B6C + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_1 0x4C2B70 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_2 0x4C2B74 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_3 0x4C2B78 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_4 0x4C2B7C + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_5 0x4C2B80 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_6 0x4C2B84 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_7 0x4C2B88 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_0 0x4C2BAC + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_1 0x4C2BB0 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_2 0x4C2BB4 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_3 0x4C2BB8 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_4 0x4C2BBC + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_5 0x4C2BC0 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_6 0x4C2BC4 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_7 0x4C2BC8 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_0 0x4C2BEC + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_1 0x4C2BF0 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_2 0x4C2BF4 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_3 0x4C2BF8 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_4 0x4C2BFC + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_5 0x4C2C00 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_6 0x4C2C04 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_7 0x4C2C08 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_WDT 0x4C2C2C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_WRAP 0x4C2C30 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_WRAP 0x4C2C34 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_WRAP 0x4C2C38 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_WRAP 0x4C2C3C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_WRAP 0x4C2C40 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_WRAP 0x4C2C44 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_WRAP 0x4C2C48 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_WRAP 0x4C2C4C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_CNT 0x4C2C50 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_CNT 0x4C2C54 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_CNT 0x4C2C58 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_CNT 0x4C2C5C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_CNT 0x4C2C60 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_CNT 0x4C2C64 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_CNT 0x4C2C68 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_CNT 0x4C2C6C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_WRAP 0x4C2C70 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_WRAP 0x4C2C74 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_WRAP 0x4C2C78 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_WRAP 0x4C2C7C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_WRAP 0x4C2C80 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_WRAP 0x4C2C84 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_WRAP 0x4C2C88 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_WRAP 0x4C2C8C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_CNT 0x4C2C90 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_CNT 0x4C2C94 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_CNT 0x4C2C98 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_CNT 0x4C2C9C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_CNT 0x4C2CA0 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_CNT 0x4C2CA4 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_CNT 0x4C2CA8 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_CNT 0x4C2CAC + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_PC_SEL_0 0x4C2CB0 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_PC_SEL_1 0x4C2CB4 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_PC_SEL_2 0x4C2CB8 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_PC_SEL_3 0x4C2CBC + +#endif /* ASIC_REG_DMA_IF_W_N_DOWN_CH1_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_n_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_n_regs.h new file mode 100644 index 000000000000..da60893a5fab --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_n_regs.h @@ -0,0 +1,860 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_W_N_REGS_H_ +#define ASIC_REG_DMA_IF_W_N_REGS_H_ + +/* + ***************************************** + * DMA_IF_W_N (Prototype: DMA_IF) + ***************************************** + */ + +#define mmDMA_IF_W_N_HBM0_WR_CRED_CNT 0x4C0000 + +#define mmDMA_IF_W_N_HBM1_WR_CRED_CNT 0x4C0004 + +#define mmDMA_IF_W_N_HBM0_RD_CRED_CNT 0x4C0008 + +#define mmDMA_IF_W_N_HBM1_RD_CRED_CNT 0x4C000C + +#define mmDMA_IF_W_N_HBM_LIMITER_0 0x4C0030 + +#define mmDMA_IF_W_N_HBM_LIMITER_1 0x4C0034 + +#define mmDMA_IF_W_N_HBM_LIMITER_2 0x4C0038 + +#define mmDMA_IF_W_N_HBM_LIMITER_3 0x4C003C + +#define mmDMA_IF_W_N_HBM_ALMOST_EN_0 0x4C0040 + +#define mmDMA_IF_W_N_HBM_ALMOST_EN_1 0x4C0044 + +#define mmDMA_IF_W_N_HBM_CRED_EN_0 0x4C0050 + +#define mmDMA_IF_W_N_HBM_CRED_EN_1 0x4C0054 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_0 0x4C0100 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_1 0x4C0104 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_2 0x4C0108 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_3 0x4C010C + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_4 0x4C0110 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_5 0x4C0114 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_6 0x4C0118 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_7 0x4C011C + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_8 0x4C0120 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_9 0x4C0124 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_10 0x4C0128 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_11 0x4C012C + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_12 0x4C0130 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_13 0x4C0134 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_14 0x4C0138 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_15 0x4C013C + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_0 0x4C0140 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_1 0x4C0144 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_2 0x4C0148 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_3 0x4C014C + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_4 0x4C0150 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_5 0x4C0154 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_6 0x4C0158 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_7 0x4C015C + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_8 0x4C0160 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_9 0x4C0164 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_10 0x4C0168 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_11 0x4C016C + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_12 0x4C0170 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_13 0x4C0174 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_14 0x4C0178 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_15 0x4C017C + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_0 0x4C0180 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_1 0x4C0184 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_2 0x4C0188 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_3 0x4C018C + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_4 0x4C0190 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_5 0x4C0194 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_6 0x4C0198 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_7 0x4C019C + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_8 0x4C01A0 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_9 0x4C01A4 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_10 0x4C01A8 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_11 0x4C01AC + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_12 0x4C01B0 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_13 0x4C01B4 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_14 0x4C01B8 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_15 0x4C01BC + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_0 0x4C01C0 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_1 0x4C01C4 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_2 0x4C01C8 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_3 0x4C01CC + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_4 0x4C01D0 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_5 0x4C01D4 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_6 0x4C01D8 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_7 0x4C01DC + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_8 0x4C01E0 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_9 0x4C01E4 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_10 0x4C01E8 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_11 0x4C01EC + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_12 0x4C01F0 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_13 0x4C01F4 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_14 0x4C01F8 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_15 0x4C01FC + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_0 0x4C0200 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_1 0x4C0204 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_2 0x4C0208 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_3 0x4C020C + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_4 0x4C0210 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_5 0x4C0214 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_6 0x4C0218 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_7 0x4C021C + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_8 0x4C0220 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_9 0x4C0224 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_10 0x4C0228 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_11 0x4C022C + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_12 0x4C0230 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_13 0x4C0234 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_14 0x4C0238 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_15 0x4C023C + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_0 0x4C0240 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_1 0x4C0244 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_2 0x4C0248 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_3 0x4C024C + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_4 0x4C0250 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_5 0x4C0254 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_6 0x4C0258 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_7 0x4C025C + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_8 0x4C0260 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_9 0x4C0264 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_10 0x4C0268 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_11 0x4C026C + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_12 0x4C0270 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_13 0x4C0274 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_14 0x4C0278 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_15 0x4C027C + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_0 0x4C0280 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_1 0x4C0284 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_2 0x4C0288 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_3 0x4C028C + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_4 0x4C0290 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_5 0x4C0294 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_6 0x4C0298 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_7 0x4C029C + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_8 0x4C02A0 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_9 0x4C02A4 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_10 0x4C02A8 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_11 0x4C02AC + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_12 0x4C02B0 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_13 0x4C02B4 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_14 0x4C02B8 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_15 0x4C02BC + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_0 0x4C02C0 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_1 0x4C02C4 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_2 0x4C02C8 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_3 0x4C02CC + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_4 0x4C02D0 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_5 0x4C02D4 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_6 0x4C02D8 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_7 0x4C02DC + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_8 0x4C02E0 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_9 0x4C02E4 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_10 0x4C02E8 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_11 0x4C02EC + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_12 0x4C02F0 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_13 0x4C02F4 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_14 0x4C02F8 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_15 0x4C02FC + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_0 0x4C0300 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_1 0x4C0304 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_2 0x4C0308 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_3 0x4C030C + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_4 0x4C0310 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_5 0x4C0314 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_6 0x4C0318 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_7 0x4C031C + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_8 0x4C0320 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_9 0x4C0324 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_10 0x4C0328 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_11 0x4C032C + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_12 0x4C0330 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_13 0x4C0334 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_14 0x4C0338 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_15 0x4C033C + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_0 0x4C0340 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_1 0x4C0344 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_2 0x4C0348 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_3 0x4C034C + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_4 0x4C0350 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_5 0x4C0354 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_6 0x4C0358 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_7 0x4C035C + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_8 0x4C0360 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_9 0x4C0364 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_10 0x4C0368 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_11 0x4C036C + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_12 0x4C0370 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_13 0x4C0374 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_14 0x4C0378 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_15 0x4C037C + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_0 0x4C0380 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_1 0x4C0384 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_2 0x4C0388 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_3 0x4C038C + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_4 0x4C0390 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_5 0x4C0394 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_6 0x4C0398 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_7 0x4C039C + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_8 0x4C03A0 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_9 0x4C03A4 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_10 0x4C03A8 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_11 0x4C03AC + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_12 0x4C03B0 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_13 0x4C03B4 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_14 0x4C03B8 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_15 0x4C03BC + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_0 0x4C03C0 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_1 0x4C03C4 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_2 0x4C03C8 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_3 0x4C03CC + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_4 0x4C03D0 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_5 0x4C03D4 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_6 0x4C03D8 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_7 0x4C03DC + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_8 0x4C03E0 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_9 0x4C03E4 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_10 0x4C03E8 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_11 0x4C03EC + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_12 0x4C03F0 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_13 0x4C03F4 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_14 0x4C03F8 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_15 0x4C03FC + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_0 0x4C0400 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_1 0x4C0404 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_2 0x4C0408 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_3 0x4C040C + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_4 0x4C0410 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_5 0x4C0414 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_6 0x4C0418 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_7 0x4C041C + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_8 0x4C0420 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_9 0x4C0424 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_10 0x4C0428 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_11 0x4C042C + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_12 0x4C0430 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_13 0x4C0434 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_14 0x4C0438 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_15 0x4C043C + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_0 0x4C0440 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_1 0x4C0444 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_2 0x4C0448 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_3 0x4C044C + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_4 0x4C0450 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_5 0x4C0454 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_6 0x4C0458 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_7 0x4C045C + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_8 0x4C0460 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_9 0x4C0464 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_10 0x4C0468 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_11 0x4C046C + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_12 0x4C0470 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_13 0x4C0474 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_14 0x4C0478 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_15 0x4C047C + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_0 0x4C0480 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_1 0x4C0484 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_2 0x4C0488 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_3 0x4C048C + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_4 0x4C0490 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_5 0x4C0494 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_6 0x4C0498 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_7 0x4C049C + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_8 0x4C04A0 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_9 0x4C04A4 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_10 0x4C04A8 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_11 0x4C04AC + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_12 0x4C04B0 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_13 0x4C04B4 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_14 0x4C04B8 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_15 0x4C04BC + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_0 0x4C04C0 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_1 0x4C04C4 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_2 0x4C04C8 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_3 0x4C04CC + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_4 0x4C04D0 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_5 0x4C04D4 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_6 0x4C04D8 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_7 0x4C04DC + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_8 0x4C04E0 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_9 0x4C04E4 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_10 0x4C04E8 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_11 0x4C04EC + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_12 0x4C04F0 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_13 0x4C04F4 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_14 0x4C04F8 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_15 0x4C04FC + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_0 0x4C0500 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_1 0x4C0504 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_2 0x4C0508 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_3 0x4C050C + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_4 0x4C0510 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_5 0x4C0514 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_6 0x4C0518 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_7 0x4C051C + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_8 0x4C0520 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_9 0x4C0524 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_10 0x4C0528 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_11 0x4C052C + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_12 0x4C0530 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_13 0x4C0534 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_14 0x4C0538 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_15 0x4C053C + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_0 0x4C0540 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_1 0x4C0544 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_2 0x4C0548 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_3 0x4C054C + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_4 0x4C0550 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_5 0x4C0554 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_6 0x4C0558 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_7 0x4C055C + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_8 0x4C0560 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_9 0x4C0564 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_10 0x4C0568 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_11 0x4C056C + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_12 0x4C0570 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_13 0x4C0574 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_14 0x4C0578 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_15 0x4C057C + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_0 0x4C0580 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_1 0x4C0584 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_2 0x4C0588 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_3 0x4C058C + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_4 0x4C0590 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_5 0x4C0594 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_6 0x4C0598 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_7 0x4C059C + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_8 0x4C05A0 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_9 0x4C05A4 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_10 0x4C05A8 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_11 0x4C05AC + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_12 0x4C05B0 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_13 0x4C05B4 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_14 0x4C05B8 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_15 0x4C05BC + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_0 0x4C05C0 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_1 0x4C05C4 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_2 0x4C05C8 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_3 0x4C05CC + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_4 0x4C05D0 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_5 0x4C05D4 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_6 0x4C05D8 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_7 0x4C05DC + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_8 0x4C05E0 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_9 0x4C05E4 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_10 0x4C05E8 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_11 0x4C05EC + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_12 0x4C05F0 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_13 0x4C05F4 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_14 0x4C05F8 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_15 0x4C05FC + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_0 0x4C0600 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_1 0x4C0604 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_2 0x4C0608 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_3 0x4C060C + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_4 0x4C0610 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_5 0x4C0614 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_6 0x4C0618 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_7 0x4C061C + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_8 0x4C0620 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_9 0x4C0624 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_10 0x4C0628 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_11 0x4C062C + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_12 0x4C0630 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_13 0x4C0634 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_14 0x4C0638 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_15 0x4C063C + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_0 0x4C0640 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_1 0x4C0644 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_2 0x4C0648 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_3 0x4C064C + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_4 0x4C0650 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_5 0x4C0654 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_6 0x4C0658 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_7 0x4C065C + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_8 0x4C0660 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_9 0x4C0664 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_10 0x4C0668 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_11 0x4C066C + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_12 0x4C0670 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_13 0x4C0674 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_14 0x4C0678 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_15 0x4C067C + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_0 0x4C0680 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_1 0x4C0684 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_2 0x4C0688 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_3 0x4C068C + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_4 0x4C0690 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_5 0x4C0694 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_6 0x4C0698 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_7 0x4C069C + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_8 0x4C06A0 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_9 0x4C06A4 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_10 0x4C06A8 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_11 0x4C06AC + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_12 0x4C06B0 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_13 0x4C06B4 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_14 0x4C06B8 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_15 0x4C06BC + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_0 0x4C06C0 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_1 0x4C06C4 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_2 0x4C06C8 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_3 0x4C06CC + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_4 0x4C06D0 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_5 0x4C06D4 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_6 0x4C06D8 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_7 0x4C06DC + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_8 0x4C06E0 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_9 0x4C06E4 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_10 0x4C06E8 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_11 0x4C06EC + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_12 0x4C06F0 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_13 0x4C06F4 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_14 0x4C06F8 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_15 0x4C06FC + +#define mmDMA_IF_W_N_SOB_HIT_RPROT 0x4C0700 + +#define mmDMA_IF_W_N_SOB_HIT_WPROT 0x4C0704 + +#define mmDMA_IF_W_N_SOB_HIT_RPRIV 0x4C070C + +#define mmDMA_IF_W_N_SOB_HIT_WPRIV 0x4C0710 + +#define mmDMA_IF_W_N_DMA0_HIT_RPROT 0x4C071C + +#define mmDMA_IF_W_N_DMA0_HIT_WPROT 0x4C0720 + +#define mmDMA_IF_W_N_DMA0_HIT_RPRIV 0x4C0724 + +#define mmDMA_IF_W_N_DMA0_HIT_WPRIV 0x4C0728 + +#define mmDMA_IF_W_N_DMA1_HIT_RPROT 0x4C0730 + +#define mmDMA_IF_W_N_DMA1_HIT_WPROT 0x4C0734 + +#define mmDMA_IF_W_N_DMA1_HIT_RPRIV 0x4C0738 + +#define mmDMA_IF_W_N_DMA1_HIT_WPRIV 0x4C073C + +#define mmDMA_IF_W_N_HBM_BIN 0x4C0800 + +#define mmDMA_IF_W_N_MME_BIN 0x4C0804 + +#define mmDMA_IF_W_N_TPC_BIN 0x4C0808 + +#define mmDMA_IF_W_N_DMA_BIN 0x4C080C + +#define mmDMA_IF_W_N_SOB_CG_EN 0x4C0810 + +#define mmDMA_IF_W_N_HBM_I2C_ADDR_0 0x4C0820 + +#define mmDMA_IF_W_N_HBM_I2C_ADDR_1 0x4C0824 + +#define mmDMA_IF_W_N_HBM_I2C_ADDR_2 0x4C0828 + +#define mmDMA_IF_W_N_HBM_I2C_ADDR_3 0x4C082C + +#define mmDMA_IF_W_N_HBM_I2C_ADDR_4 0x4C0830 + +#define mmDMA_IF_W_N_HBM_MISC 0x4C0834 + +#endif /* ASIC_REG_DMA_IF_W_N_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch0_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch0_regs.h new file mode 100644 index 000000000000..56ffc920d58a --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch0_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_W_S_DOWN_CH0_REGS_H_ +#define ASIC_REG_DMA_IF_W_S_DOWN_CH0_REGS_H_ + +/* + ***************************************** + * DMA_IF_W_S_DOWN_CH0 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmDMA_IF_W_S_DOWN_CH0_PERM_SEL 0x481108 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_0 0x481114 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_1 0x481118 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_2 0x48111C + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_3 0x481120 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_4 0x481124 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_5 0x481128 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_6 0x48112C + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_7 0x481130 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_8 0x481134 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_9 0x481138 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_10 0x48113C + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_11 0x481140 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_12 0x481144 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_13 0x481148 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_14 0x48114C + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_15 0x481150 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_16 0x481154 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_17 0x481158 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_18 0x48115C + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_19 0x481160 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_20 0x481164 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_21 0x481168 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_22 0x48116C + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_23 0x481170 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_24 0x481174 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_25 0x481178 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_26 0x48117C + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_27 0x481180 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_0 0x481184 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_1 0x481188 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_2 0x48118C + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_3 0x481190 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_4 0x481194 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_5 0x481198 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_6 0x48119C + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_7 0x4811A0 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_8 0x4811A4 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_9 0x4811A8 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_10 0x4811AC + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_11 0x4811B0 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_12 0x4811B4 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_13 0x4811B8 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_14 0x4811BC + +#define mmDMA_IF_W_S_DOWN_CH0_SCRAM_SRAM_EN 0x48126C + +#define mmDMA_IF_W_S_DOWN_CH0_RL_HBM_EN 0x481274 + +#define mmDMA_IF_W_S_DOWN_CH0_RL_HBM_SAT 0x481278 + +#define mmDMA_IF_W_S_DOWN_CH0_RL_HBM_RST 0x48127C + +#define mmDMA_IF_W_S_DOWN_CH0_RL_HBM_TIMEOUT 0x481280 + +#define mmDMA_IF_W_S_DOWN_CH0_SCRAM_HBM_EN 0x481284 + +#define mmDMA_IF_W_S_DOWN_CH0_RL_PCI_EN 0x481288 + +#define mmDMA_IF_W_S_DOWN_CH0_RL_PCI_SAT 0x48128C + +#define mmDMA_IF_W_S_DOWN_CH0_RL_PCI_RST 0x481290 + +#define mmDMA_IF_W_S_DOWN_CH0_RL_PCI_TIMEOUT 0x481294 + +#define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_EN 0x48129C + +#define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_SAT 0x4812A0 + +#define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_RST 0x4812A4 + +#define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_TIMEOUT 0x4812AC + +#define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_RED 0x4812B4 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_EN 0x4812EC + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_EN 0x4812F0 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_WR_SIZE 0x4812F4 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_WR_SIZE 0x4812F8 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_PCI_CTR_SET_EN 0x481404 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_PCI_CTR_SET 0x481408 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_PCI_CTR_WRAP 0x48140C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_PCI_CTR_CNT 0x481410 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM_CTR_SET_EN 0x481414 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM_CTR_SET 0x481418 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_RD_SIZE 0x48141C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_RD_SIZE 0x481420 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_PCI_CTR_SET_EN 0x481424 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_PCI_CTR_SET 0x481428 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_PCI_CTR_WRAP 0x48142C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_PCI_CTR_CNT 0x481430 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM_CTR_SET_EN 0x481434 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM_CTR_SET 0x481438 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_SEL_0 0x481450 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_SEL_1 0x481454 + +#define mmDMA_IF_W_S_DOWN_CH0_NON_LIN_EN 0x481480 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_0 0x481500 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_1 0x481504 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_2 0x481508 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_3 0x48150C + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_4 0x481510 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_0 0x481514 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_1 0x481520 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_2 0x481524 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_3 0x481528 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_4 0x48152C + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_5 0x481530 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_6 0x481534 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_7 0x481538 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_8 0x48153C + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_9 0x481540 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_0 0x481550 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_1 0x481554 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_2 0x481558 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_3 0x48155C + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_4 0x481560 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_5 0x481564 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_6 0x481568 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_7 0x48156C + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_8 0x481570 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_9 0x481574 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_10 0x481578 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_11 0x48157C + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_12 0x481580 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_13 0x481584 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_14 0x481588 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_15 0x48158C + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_16 0x481590 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_17 0x481594 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_18 0x481598 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0 0x4815E4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_1 0x4815E8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_2 0x4815EC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_3 0x4815F0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_4 0x4815F4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_5 0x4815F8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_6 0x4815FC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_7 0x481600 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_8 0x481604 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_9 0x481608 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_10 0x48160C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_11 0x481610 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_12 0x481614 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_13 0x481618 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_14 0x48161C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_15 0x481620 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0 0x481624 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_1 0x481628 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_2 0x48162C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_3 0x481630 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_4 0x481634 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_5 0x481638 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_6 0x48163C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_7 0x481640 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_8 0x481644 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_9 0x481648 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_10 0x48164C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_11 0x481650 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_12 0x481654 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_13 0x481658 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_14 0x48165C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_15 0x481660 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0 0x481664 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_1 0x481668 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_2 0x48166C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_3 0x481670 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_4 0x481674 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_5 0x481678 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_6 0x48167C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_7 0x481680 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_8 0x481684 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_9 0x481688 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_10 0x48168C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_11 0x481690 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_12 0x481694 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_13 0x481698 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_14 0x48169C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_15 0x4816A0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0 0x4816A4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_1 0x4816A8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_2 0x4816AC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_3 0x4816B0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_4 0x4816B4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_5 0x4816B8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_6 0x4816BC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_7 0x4816C0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_8 0x4816C4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_9 0x4816C8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_10 0x4816CC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_11 0x4816D0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_12 0x4816D4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_13 0x4816D8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_14 0x4816DC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_15 0x4816E0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_0 0x4816E4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_1 0x4816E8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_2 0x4816EC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_3 0x4816F0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_4 0x4816F4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_5 0x4816F8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_6 0x4816FC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_7 0x481700 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_8 0x481704 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_9 0x481708 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_10 0x48170C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_11 0x481710 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_12 0x481714 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_13 0x481718 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_14 0x48171C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_15 0x481720 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_0 0x481724 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_1 0x481728 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_2 0x48172C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_3 0x481730 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_4 0x481734 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_5 0x481738 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_6 0x48173C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_7 0x481740 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_8 0x481744 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_9 0x481748 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_10 0x48174C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_11 0x481750 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_12 0x481754 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_13 0x481758 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_14 0x48175C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_15 0x481760 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_0 0x481764 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_1 0x481768 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_2 0x48176C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_3 0x481770 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_4 0x481774 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_5 0x481778 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_6 0x48177C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_7 0x481780 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_8 0x481784 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_9 0x481788 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_10 0x48178C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_11 0x481790 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_12 0x481794 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_13 0x481798 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_14 0x48179C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_15 0x4817A0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_0 0x4817A4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_1 0x4817A8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_2 0x4817AC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_3 0x4817B0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_4 0x4817B4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_5 0x4817B8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_6 0x4817BC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_7 0x4817C0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_8 0x4817C4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_9 0x4817C8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_10 0x4817CC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_11 0x4817D0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_12 0x4817D4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_13 0x4817D8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_14 0x4817DC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_15 0x4817E0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0 0x481824 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_1 0x481828 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_2 0x48182C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_3 0x481830 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_4 0x481834 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_5 0x481838 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_6 0x48183C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_7 0x481840 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_8 0x481844 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_9 0x481848 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_10 0x48184C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_11 0x481850 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_12 0x481854 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_13 0x481858 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_14 0x48185C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_15 0x481860 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0 0x481864 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_1 0x481868 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_2 0x48186C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_3 0x481870 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_4 0x481874 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_5 0x481878 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_6 0x48187C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_7 0x481880 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_8 0x481884 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_9 0x481888 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_10 0x48188C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_11 0x481890 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_12 0x481894 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_13 0x481898 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_14 0x48189C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_15 0x4818A0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0 0x4818A4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_1 0x4818A8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_2 0x4818AC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_3 0x4818B0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_4 0x4818B4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_5 0x4818B8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_6 0x4818BC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_7 0x4818C0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_8 0x4818C4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_9 0x4818C8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_10 0x4818CC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_11 0x4818D0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_12 0x4818D4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_13 0x4818D8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_14 0x4818DC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_15 0x4818E0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0 0x4818E4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_1 0x4818E8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_2 0x4818EC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_3 0x4818F0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_4 0x4818F4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_5 0x4818F8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_6 0x4818FC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_7 0x481900 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_8 0x481904 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_9 0x481908 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_10 0x48190C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_11 0x481910 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_12 0x481914 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_13 0x481918 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_14 0x48191C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_15 0x481920 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_0 0x481924 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_1 0x481928 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_2 0x48192C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_3 0x481930 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_4 0x481934 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_5 0x481938 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_6 0x48193C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_7 0x481940 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_8 0x481944 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_9 0x481948 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_10 0x48194C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_11 0x481950 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_12 0x481954 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_13 0x481958 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_14 0x48195C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_15 0x481960 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_0 0x481964 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_1 0x481968 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_2 0x48196C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_3 0x481970 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_4 0x481974 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_5 0x481978 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_6 0x48197C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_7 0x481980 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_8 0x481984 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_9 0x481988 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_10 0x48198C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_11 0x481990 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_12 0x481994 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_13 0x481998 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_14 0x48199C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_15 0x4819A0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_0 0x4819A4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_1 0x4819A8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_2 0x4819AC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_3 0x4819B0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_4 0x4819B4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_5 0x4819B8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_6 0x4819BC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_7 0x4819C0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_8 0x4819C4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_9 0x4819C8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_10 0x4819CC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_11 0x4819D0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_12 0x4819D4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_13 0x4819D8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_14 0x4819DC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_15 0x4819E0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_0 0x4819E4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_1 0x4819E8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_2 0x4819EC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_3 0x4819F0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_4 0x4819F4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_5 0x4819F8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_6 0x4819FC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_7 0x481A00 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_8 0x481A04 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_9 0x481A08 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_10 0x481A0C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_11 0x481A10 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_12 0x481A14 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_13 0x481A18 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_14 0x481A1C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_15 0x481A20 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_HIT_AW 0x481A64 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_HIT_AR 0x481A68 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_HIT_AW 0x481A6C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_HIT_AR 0x481A70 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_CFG 0x481B64 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_SHIFT 0x481B68 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_0 0x481B6C + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_1 0x481B70 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_2 0x481B74 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_3 0x481B78 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_4 0x481B7C + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_5 0x481B80 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_6 0x481B84 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_7 0x481B88 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_0 0x481BAC + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_1 0x481BB0 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_2 0x481BB4 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_3 0x481BB8 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_4 0x481BBC + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_5 0x481BC0 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_6 0x481BC4 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_7 0x481BC8 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_0 0x481BEC + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_1 0x481BF0 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_2 0x481BF4 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_3 0x481BF8 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_4 0x481BFC + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_5 0x481C00 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_6 0x481C04 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_7 0x481C08 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_WDT 0x481C2C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_WRAP 0x481C30 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_WRAP 0x481C34 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_WRAP 0x481C38 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_WRAP 0x481C3C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_WRAP 0x481C40 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_WRAP 0x481C44 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_WRAP 0x481C48 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_WRAP 0x481C4C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_CNT 0x481C50 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_CNT 0x481C54 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_CNT 0x481C58 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_CNT 0x481C5C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_CNT 0x481C60 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_CNT 0x481C64 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_CNT 0x481C68 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_CNT 0x481C6C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_WRAP 0x481C70 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_WRAP 0x481C74 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_WRAP 0x481C78 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_WRAP 0x481C7C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_WRAP 0x481C80 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_WRAP 0x481C84 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_WRAP 0x481C88 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_WRAP 0x481C8C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_CNT 0x481C90 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_CNT 0x481C94 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_CNT 0x481C98 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_CNT 0x481C9C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_CNT 0x481CA0 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_CNT 0x481CA4 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_CNT 0x481CA8 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_CNT 0x481CAC + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_0 0x481CB0 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_1 0x481CB4 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_2 0x481CB8 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_3 0x481CBC + +#endif /* ASIC_REG_DMA_IF_W_S_DOWN_CH0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch1_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch1_regs.h new file mode 100644 index 000000000000..cbc642918deb --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch1_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_W_S_DOWN_CH1_REGS_H_ +#define ASIC_REG_DMA_IF_W_S_DOWN_CH1_REGS_H_ + +/* + ***************************************** + * DMA_IF_W_S_DOWN_CH1 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmDMA_IF_W_S_DOWN_CH1_PERM_SEL 0x482108 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_0 0x482114 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_1 0x482118 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_2 0x48211C + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_3 0x482120 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_4 0x482124 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_5 0x482128 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_6 0x48212C + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_7 0x482130 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_8 0x482134 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_9 0x482138 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_10 0x48213C + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_11 0x482140 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_12 0x482144 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_13 0x482148 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_14 0x48214C + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_15 0x482150 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_16 0x482154 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_17 0x482158 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_18 0x48215C + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_19 0x482160 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_20 0x482164 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_21 0x482168 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_22 0x48216C + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_23 0x482170 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_24 0x482174 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_25 0x482178 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_26 0x48217C + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_27 0x482180 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_0 0x482184 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_1 0x482188 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_2 0x48218C + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_3 0x482190 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_4 0x482194 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_5 0x482198 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_6 0x48219C + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_7 0x4821A0 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_8 0x4821A4 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_9 0x4821A8 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_10 0x4821AC + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_11 0x4821B0 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_12 0x4821B4 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_13 0x4821B8 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_14 0x4821BC + +#define mmDMA_IF_W_S_DOWN_CH1_SCRAM_SRAM_EN 0x48226C + +#define mmDMA_IF_W_S_DOWN_CH1_RL_HBM_EN 0x482274 + +#define mmDMA_IF_W_S_DOWN_CH1_RL_HBM_SAT 0x482278 + +#define mmDMA_IF_W_S_DOWN_CH1_RL_HBM_RST 0x48227C + +#define mmDMA_IF_W_S_DOWN_CH1_RL_HBM_TIMEOUT 0x482280 + +#define mmDMA_IF_W_S_DOWN_CH1_SCRAM_HBM_EN 0x482284 + +#define mmDMA_IF_W_S_DOWN_CH1_RL_PCI_EN 0x482288 + +#define mmDMA_IF_W_S_DOWN_CH1_RL_PCI_SAT 0x48228C + +#define mmDMA_IF_W_S_DOWN_CH1_RL_PCI_RST 0x482290 + +#define mmDMA_IF_W_S_DOWN_CH1_RL_PCI_TIMEOUT 0x482294 + +#define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_EN 0x48229C + +#define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_SAT 0x4822A0 + +#define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_RST 0x4822A4 + +#define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_TIMEOUT 0x4822AC + +#define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_RED 0x4822B4 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_EN 0x4822EC + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_EN 0x4822F0 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_WR_SIZE 0x4822F4 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_WR_SIZE 0x4822F8 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_PCI_CTR_SET_EN 0x482404 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_PCI_CTR_SET 0x482408 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_PCI_CTR_WRAP 0x48240C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_PCI_CTR_CNT 0x482410 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM_CTR_SET_EN 0x482414 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM_CTR_SET 0x482418 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_RD_SIZE 0x48241C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_RD_SIZE 0x482420 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_PCI_CTR_SET_EN 0x482424 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_PCI_CTR_SET 0x482428 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_PCI_CTR_WRAP 0x48242C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_PCI_CTR_CNT 0x482430 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM_CTR_SET_EN 0x482434 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM_CTR_SET 0x482438 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_SEL_0 0x482450 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_SEL_1 0x482454 + +#define mmDMA_IF_W_S_DOWN_CH1_NON_LIN_EN 0x482480 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_0 0x482500 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_1 0x482504 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_2 0x482508 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_3 0x48250C + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_4 0x482510 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_0 0x482514 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_1 0x482520 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_2 0x482524 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_3 0x482528 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_4 0x48252C + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_5 0x482530 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_6 0x482534 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_7 0x482538 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_8 0x48253C + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_9 0x482540 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_0 0x482550 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_1 0x482554 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_2 0x482558 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_3 0x48255C + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_4 0x482560 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_5 0x482564 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_6 0x482568 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_7 0x48256C + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_8 0x482570 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_9 0x482574 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_10 0x482578 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_11 0x48257C + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_12 0x482580 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_13 0x482584 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_14 0x482588 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_15 0x48258C + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_16 0x482590 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_17 0x482594 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_18 0x482598 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0 0x4825E4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_1 0x4825E8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_2 0x4825EC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_3 0x4825F0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_4 0x4825F4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_5 0x4825F8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_6 0x4825FC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_7 0x482600 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_8 0x482604 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_9 0x482608 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_10 0x48260C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_11 0x482610 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_12 0x482614 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_13 0x482618 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_14 0x48261C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_15 0x482620 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0 0x482624 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_1 0x482628 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_2 0x48262C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_3 0x482630 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_4 0x482634 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_5 0x482638 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_6 0x48263C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_7 0x482640 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_8 0x482644 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_9 0x482648 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_10 0x48264C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_11 0x482650 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_12 0x482654 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_13 0x482658 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_14 0x48265C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_15 0x482660 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0 0x482664 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_1 0x482668 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_2 0x48266C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_3 0x482670 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_4 0x482674 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_5 0x482678 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_6 0x48267C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_7 0x482680 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_8 0x482684 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_9 0x482688 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_10 0x48268C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_11 0x482690 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_12 0x482694 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_13 0x482698 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_14 0x48269C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_15 0x4826A0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0 0x4826A4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_1 0x4826A8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_2 0x4826AC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_3 0x4826B0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_4 0x4826B4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_5 0x4826B8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_6 0x4826BC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_7 0x4826C0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_8 0x4826C4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_9 0x4826C8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_10 0x4826CC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_11 0x4826D0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_12 0x4826D4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_13 0x4826D8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_14 0x4826DC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_15 0x4826E0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_0 0x4826E4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_1 0x4826E8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_2 0x4826EC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_3 0x4826F0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_4 0x4826F4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_5 0x4826F8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_6 0x4826FC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_7 0x482700 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_8 0x482704 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_9 0x482708 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_10 0x48270C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_11 0x482710 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_12 0x482714 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_13 0x482718 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_14 0x48271C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_15 0x482720 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_0 0x482724 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_1 0x482728 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_2 0x48272C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_3 0x482730 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_4 0x482734 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_5 0x482738 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_6 0x48273C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_7 0x482740 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_8 0x482744 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_9 0x482748 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_10 0x48274C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_11 0x482750 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_12 0x482754 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_13 0x482758 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_14 0x48275C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_15 0x482760 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_0 0x482764 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_1 0x482768 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_2 0x48276C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_3 0x482770 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_4 0x482774 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_5 0x482778 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_6 0x48277C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_7 0x482780 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_8 0x482784 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_9 0x482788 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_10 0x48278C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_11 0x482790 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_12 0x482794 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_13 0x482798 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_14 0x48279C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_15 0x4827A0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_0 0x4827A4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_1 0x4827A8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_2 0x4827AC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_3 0x4827B0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_4 0x4827B4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_5 0x4827B8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_6 0x4827BC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_7 0x4827C0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_8 0x4827C4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_9 0x4827C8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_10 0x4827CC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_11 0x4827D0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_12 0x4827D4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_13 0x4827D8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_14 0x4827DC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_15 0x4827E0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0 0x482824 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_1 0x482828 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_2 0x48282C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_3 0x482830 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_4 0x482834 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_5 0x482838 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_6 0x48283C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_7 0x482840 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_8 0x482844 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_9 0x482848 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_10 0x48284C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_11 0x482850 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_12 0x482854 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_13 0x482858 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_14 0x48285C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_15 0x482860 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0 0x482864 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_1 0x482868 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_2 0x48286C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_3 0x482870 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_4 0x482874 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_5 0x482878 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_6 0x48287C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_7 0x482880 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_8 0x482884 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_9 0x482888 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_10 0x48288C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_11 0x482890 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_12 0x482894 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_13 0x482898 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_14 0x48289C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_15 0x4828A0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0 0x4828A4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_1 0x4828A8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_2 0x4828AC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_3 0x4828B0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_4 0x4828B4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_5 0x4828B8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_6 0x4828BC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_7 0x4828C0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_8 0x4828C4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_9 0x4828C8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_10 0x4828CC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_11 0x4828D0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_12 0x4828D4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_13 0x4828D8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_14 0x4828DC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_15 0x4828E0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0 0x4828E4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_1 0x4828E8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_2 0x4828EC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_3 0x4828F0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_4 0x4828F4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_5 0x4828F8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_6 0x4828FC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_7 0x482900 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_8 0x482904 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_9 0x482908 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_10 0x48290C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_11 0x482910 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_12 0x482914 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_13 0x482918 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_14 0x48291C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_15 0x482920 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_0 0x482924 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_1 0x482928 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_2 0x48292C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_3 0x482930 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_4 0x482934 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_5 0x482938 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_6 0x48293C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_7 0x482940 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_8 0x482944 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_9 0x482948 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_10 0x48294C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_11 0x482950 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_12 0x482954 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_13 0x482958 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_14 0x48295C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_15 0x482960 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_0 0x482964 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_1 0x482968 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_2 0x48296C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_3 0x482970 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_4 0x482974 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_5 0x482978 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_6 0x48297C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_7 0x482980 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_8 0x482984 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_9 0x482988 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_10 0x48298C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_11 0x482990 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_12 0x482994 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_13 0x482998 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_14 0x48299C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_15 0x4829A0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_0 0x4829A4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_1 0x4829A8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_2 0x4829AC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_3 0x4829B0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_4 0x4829B4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_5 0x4829B8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_6 0x4829BC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_7 0x4829C0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_8 0x4829C4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_9 0x4829C8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_10 0x4829CC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_11 0x4829D0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_12 0x4829D4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_13 0x4829D8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_14 0x4829DC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_15 0x4829E0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_0 0x4829E4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_1 0x4829E8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_2 0x4829EC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_3 0x4829F0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_4 0x4829F4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_5 0x4829F8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_6 0x4829FC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_7 0x482A00 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_8 0x482A04 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_9 0x482A08 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_10 0x482A0C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_11 0x482A10 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_12 0x482A14 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_13 0x482A18 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_14 0x482A1C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_15 0x482A20 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_HIT_AW 0x482A64 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_HIT_AR 0x482A68 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_HIT_AW 0x482A6C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_HIT_AR 0x482A70 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_CFG 0x482B64 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_SHIFT 0x482B68 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_0 0x482B6C + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_1 0x482B70 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_2 0x482B74 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_3 0x482B78 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_4 0x482B7C + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_5 0x482B80 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_6 0x482B84 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_7 0x482B88 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_0 0x482BAC + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_1 0x482BB0 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_2 0x482BB4 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_3 0x482BB8 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_4 0x482BBC + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_5 0x482BC0 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_6 0x482BC4 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_7 0x482BC8 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_0 0x482BEC + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_1 0x482BF0 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_2 0x482BF4 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_3 0x482BF8 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_4 0x482BFC + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_5 0x482C00 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_6 0x482C04 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_7 0x482C08 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_WDT 0x482C2C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_WRAP 0x482C30 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_WRAP 0x482C34 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_WRAP 0x482C38 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_WRAP 0x482C3C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_WRAP 0x482C40 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_WRAP 0x482C44 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_WRAP 0x482C48 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_WRAP 0x482C4C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_CNT 0x482C50 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_CNT 0x482C54 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_CNT 0x482C58 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_CNT 0x482C5C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_CNT 0x482C60 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_CNT 0x482C64 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_CNT 0x482C68 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_CNT 0x482C6C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_WRAP 0x482C70 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_WRAP 0x482C74 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_WRAP 0x482C78 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_WRAP 0x482C7C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_WRAP 0x482C80 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_WRAP 0x482C84 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_WRAP 0x482C88 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_WRAP 0x482C8C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_CNT 0x482C90 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_CNT 0x482C94 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_CNT 0x482C98 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_CNT 0x482C9C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_CNT 0x482CA0 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_CNT 0x482CA4 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_CNT 0x482CA8 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_CNT 0x482CAC + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_0 0x482CB0 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_1 0x482CB4 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_2 0x482CB8 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_3 0x482CBC + +#endif /* ASIC_REG_DMA_IF_W_S_DOWN_CH1_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_s_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_s_regs.h new file mode 100644 index 000000000000..2382bc41bea6 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_s_regs.h @@ -0,0 +1,860 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_W_S_REGS_H_ +#define ASIC_REG_DMA_IF_W_S_REGS_H_ + +/* + ***************************************** + * DMA_IF_W_S (Prototype: DMA_IF) + ***************************************** + */ + +#define mmDMA_IF_W_S_HBM0_WR_CRED_CNT 0x480000 + +#define mmDMA_IF_W_S_HBM1_WR_CRED_CNT 0x480004 + +#define mmDMA_IF_W_S_HBM0_RD_CRED_CNT 0x480008 + +#define mmDMA_IF_W_S_HBM1_RD_CRED_CNT 0x48000C + +#define mmDMA_IF_W_S_HBM_LIMITER_0 0x480030 + +#define mmDMA_IF_W_S_HBM_LIMITER_1 0x480034 + +#define mmDMA_IF_W_S_HBM_LIMITER_2 0x480038 + +#define mmDMA_IF_W_S_HBM_LIMITER_3 0x48003C + +#define mmDMA_IF_W_S_HBM_ALMOST_EN_0 0x480040 + +#define mmDMA_IF_W_S_HBM_ALMOST_EN_1 0x480044 + +#define mmDMA_IF_W_S_HBM_CRED_EN_0 0x480050 + +#define mmDMA_IF_W_S_HBM_CRED_EN_1 0x480054 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_0 0x480100 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_1 0x480104 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_2 0x480108 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_3 0x48010C + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_4 0x480110 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_5 0x480114 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_6 0x480118 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_7 0x48011C + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_8 0x480120 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_9 0x480124 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_10 0x480128 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_11 0x48012C + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_12 0x480130 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_13 0x480134 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_14 0x480138 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_15 0x48013C + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_0 0x480140 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_1 0x480144 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_2 0x480148 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_3 0x48014C + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_4 0x480150 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_5 0x480154 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_6 0x480158 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_7 0x48015C + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_8 0x480160 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_9 0x480164 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_10 0x480168 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_11 0x48016C + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_12 0x480170 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_13 0x480174 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_14 0x480178 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_15 0x48017C + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_0 0x480180 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_1 0x480184 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_2 0x480188 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_3 0x48018C + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_4 0x480190 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_5 0x480194 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_6 0x480198 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_7 0x48019C + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_8 0x4801A0 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_9 0x4801A4 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_10 0x4801A8 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_11 0x4801AC + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_12 0x4801B0 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_13 0x4801B4 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_14 0x4801B8 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_15 0x4801BC + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_0 0x4801C0 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_1 0x4801C4 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_2 0x4801C8 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_3 0x4801CC + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_4 0x4801D0 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_5 0x4801D4 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_6 0x4801D8 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_7 0x4801DC + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_8 0x4801E0 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_9 0x4801E4 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_10 0x4801E8 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_11 0x4801EC + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_12 0x4801F0 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_13 0x4801F4 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_14 0x4801F8 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_15 0x4801FC + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_0 0x480200 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_1 0x480204 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_2 0x480208 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_3 0x48020C + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_4 0x480210 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_5 0x480214 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_6 0x480218 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_7 0x48021C + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_8 0x480220 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_9 0x480224 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_10 0x480228 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_11 0x48022C + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_12 0x480230 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_13 0x480234 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_14 0x480238 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_15 0x48023C + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_0 0x480240 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_1 0x480244 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_2 0x480248 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_3 0x48024C + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_4 0x480250 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_5 0x480254 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_6 0x480258 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_7 0x48025C + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_8 0x480260 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_9 0x480264 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_10 0x480268 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_11 0x48026C + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_12 0x480270 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_13 0x480274 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_14 0x480278 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_15 0x48027C + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_0 0x480280 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_1 0x480284 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_2 0x480288 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_3 0x48028C + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_4 0x480290 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_5 0x480294 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_6 0x480298 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_7 0x48029C + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_8 0x4802A0 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_9 0x4802A4 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_10 0x4802A8 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_11 0x4802AC + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_12 0x4802B0 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_13 0x4802B4 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_14 0x4802B8 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_15 0x4802BC + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_0 0x4802C0 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_1 0x4802C4 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_2 0x4802C8 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_3 0x4802CC + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_4 0x4802D0 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_5 0x4802D4 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_6 0x4802D8 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_7 0x4802DC + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_8 0x4802E0 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_9 0x4802E4 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_10 0x4802E8 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_11 0x4802EC + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_12 0x4802F0 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_13 0x4802F4 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_14 0x4802F8 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_15 0x4802FC + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_0 0x480300 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_1 0x480304 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_2 0x480308 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_3 0x48030C + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_4 0x480310 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_5 0x480314 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_6 0x480318 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_7 0x48031C + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_8 0x480320 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_9 0x480324 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_10 0x480328 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_11 0x48032C + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_12 0x480330 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_13 0x480334 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_14 0x480338 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_15 0x48033C + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_0 0x480340 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_1 0x480344 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_2 0x480348 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_3 0x48034C + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_4 0x480350 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_5 0x480354 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_6 0x480358 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_7 0x48035C + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_8 0x480360 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_9 0x480364 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_10 0x480368 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_11 0x48036C + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_12 0x480370 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_13 0x480374 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_14 0x480378 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_15 0x48037C + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_0 0x480380 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_1 0x480384 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_2 0x480388 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_3 0x48038C + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_4 0x480390 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_5 0x480394 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_6 0x480398 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_7 0x48039C + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_8 0x4803A0 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_9 0x4803A4 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_10 0x4803A8 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_11 0x4803AC + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_12 0x4803B0 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_13 0x4803B4 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_14 0x4803B8 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_15 0x4803BC + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_0 0x4803C0 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_1 0x4803C4 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_2 0x4803C8 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_3 0x4803CC + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_4 0x4803D0 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_5 0x4803D4 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_6 0x4803D8 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_7 0x4803DC + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_8 0x4803E0 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_9 0x4803E4 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_10 0x4803E8 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_11 0x4803EC + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_12 0x4803F0 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_13 0x4803F4 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_14 0x4803F8 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_15 0x4803FC + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_0 0x480400 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_1 0x480404 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_2 0x480408 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_3 0x48040C + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_4 0x480410 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_5 0x480414 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_6 0x480418 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_7 0x48041C + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_8 0x480420 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_9 0x480424 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_10 0x480428 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_11 0x48042C + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_12 0x480430 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_13 0x480434 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_14 0x480438 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_15 0x48043C + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_0 0x480440 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_1 0x480444 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_2 0x480448 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_3 0x48044C + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_4 0x480450 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_5 0x480454 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_6 0x480458 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_7 0x48045C + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_8 0x480460 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_9 0x480464 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_10 0x480468 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_11 0x48046C + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_12 0x480470 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_13 0x480474 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_14 0x480478 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_15 0x48047C + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_0 0x480480 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_1 0x480484 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_2 0x480488 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_3 0x48048C + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_4 0x480490 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_5 0x480494 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_6 0x480498 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_7 0x48049C + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_8 0x4804A0 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_9 0x4804A4 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_10 0x4804A8 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_11 0x4804AC + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_12 0x4804B0 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_13 0x4804B4 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_14 0x4804B8 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_15 0x4804BC + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_0 0x4804C0 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_1 0x4804C4 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_2 0x4804C8 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_3 0x4804CC + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_4 0x4804D0 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_5 0x4804D4 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_6 0x4804D8 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_7 0x4804DC + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_8 0x4804E0 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_9 0x4804E4 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_10 0x4804E8 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_11 0x4804EC + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_12 0x4804F0 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_13 0x4804F4 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_14 0x4804F8 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_15 0x4804FC + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_0 0x480500 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_1 0x480504 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_2 0x480508 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_3 0x48050C + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_4 0x480510 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_5 0x480514 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_6 0x480518 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_7 0x48051C + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_8 0x480520 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_9 0x480524 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_10 0x480528 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_11 0x48052C + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_12 0x480530 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_13 0x480534 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_14 0x480538 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_15 0x48053C + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_0 0x480540 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_1 0x480544 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_2 0x480548 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_3 0x48054C + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_4 0x480550 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_5 0x480554 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_6 0x480558 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_7 0x48055C + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_8 0x480560 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_9 0x480564 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_10 0x480568 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_11 0x48056C + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_12 0x480570 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_13 0x480574 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_14 0x480578 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_15 0x48057C + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_0 0x480580 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_1 0x480584 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_2 0x480588 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_3 0x48058C + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_4 0x480590 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_5 0x480594 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_6 0x480598 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_7 0x48059C + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_8 0x4805A0 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_9 0x4805A4 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_10 0x4805A8 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_11 0x4805AC + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_12 0x4805B0 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_13 0x4805B4 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_14 0x4805B8 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_15 0x4805BC + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_0 0x4805C0 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_1 0x4805C4 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_2 0x4805C8 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_3 0x4805CC + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_4 0x4805D0 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_5 0x4805D4 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_6 0x4805D8 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_7 0x4805DC + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_8 0x4805E0 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_9 0x4805E4 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_10 0x4805E8 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_11 0x4805EC + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_12 0x4805F0 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_13 0x4805F4 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_14 0x4805F8 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_15 0x4805FC + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_0 0x480600 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_1 0x480604 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_2 0x480608 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_3 0x48060C + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_4 0x480610 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_5 0x480614 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_6 0x480618 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_7 0x48061C + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_8 0x480620 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_9 0x480624 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_10 0x480628 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_11 0x48062C + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_12 0x480630 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_13 0x480634 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_14 0x480638 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_15 0x48063C + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_0 0x480640 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_1 0x480644 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_2 0x480648 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_3 0x48064C + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_4 0x480650 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_5 0x480654 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_6 0x480658 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_7 0x48065C + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_8 0x480660 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_9 0x480664 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_10 0x480668 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_11 0x48066C + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_12 0x480670 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_13 0x480674 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_14 0x480678 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_15 0x48067C + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_0 0x480680 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_1 0x480684 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_2 0x480688 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_3 0x48068C + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_4 0x480690 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_5 0x480694 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_6 0x480698 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_7 0x48069C + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_8 0x4806A0 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_9 0x4806A4 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_10 0x4806A8 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_11 0x4806AC + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_12 0x4806B0 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_13 0x4806B4 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_14 0x4806B8 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_15 0x4806BC + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_0 0x4806C0 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_1 0x4806C4 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_2 0x4806C8 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_3 0x4806CC + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_4 0x4806D0 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_5 0x4806D4 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_6 0x4806D8 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_7 0x4806DC + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_8 0x4806E0 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_9 0x4806E4 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_10 0x4806E8 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_11 0x4806EC + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_12 0x4806F0 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_13 0x4806F4 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_14 0x4806F8 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_15 0x4806FC + +#define mmDMA_IF_W_S_SOB_HIT_RPROT 0x480700 + +#define mmDMA_IF_W_S_SOB_HIT_WPROT 0x480704 + +#define mmDMA_IF_W_S_SOB_HIT_RPRIV 0x48070C + +#define mmDMA_IF_W_S_SOB_HIT_WPRIV 0x480710 + +#define mmDMA_IF_W_S_DMA0_HIT_RPROT 0x48071C + +#define mmDMA_IF_W_S_DMA0_HIT_WPROT 0x480720 + +#define mmDMA_IF_W_S_DMA0_HIT_RPRIV 0x480724 + +#define mmDMA_IF_W_S_DMA0_HIT_WPRIV 0x480728 + +#define mmDMA_IF_W_S_DMA1_HIT_RPROT 0x480730 + +#define mmDMA_IF_W_S_DMA1_HIT_WPROT 0x480734 + +#define mmDMA_IF_W_S_DMA1_HIT_RPRIV 0x480738 + +#define mmDMA_IF_W_S_DMA1_HIT_WPRIV 0x48073C + +#define mmDMA_IF_W_S_HBM_BIN 0x480800 + +#define mmDMA_IF_W_S_MME_BIN 0x480804 + +#define mmDMA_IF_W_S_TPC_BIN 0x480808 + +#define mmDMA_IF_W_S_DMA_BIN 0x48080C + +#define mmDMA_IF_W_S_SOB_CG_EN 0x480810 + +#define mmDMA_IF_W_S_HBM_I2C_ADDR_0 0x480820 + +#define mmDMA_IF_W_S_HBM_I2C_ADDR_1 0x480824 + +#define mmDMA_IF_W_S_HBM_I2C_ADDR_2 0x480828 + +#define mmDMA_IF_W_S_HBM_I2C_ADDR_3 0x48082C + +#define mmDMA_IF_W_S_HBM_I2C_ADDR_4 0x480830 + +#define mmDMA_IF_W_S_HBM_MISC 0x480834 + +#endif /* ASIC_REG_DMA_IF_W_S_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/gaudi_blocks.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/gaudi_blocks.h new file mode 100644 index 000000000000..c7596aac7a5c --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/gaudi_blocks.h @@ -0,0 +1,4974 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef GAUDI_BLOCKS_H_ +#define GAUDI_BLOCKS_H_ + +#define mmNIC0_PHY0_BASE 0x0ull +#define NIC0_PHY0_MAX_OFFSET 0x9F13 +#define mmMME0_ACC_BASE 0x7FFC020000ull +#define MME0_ACC_MAX_OFFSET 0x5C00 +#define MME0_ACC_SECTION 0x20000 +#define mmMME0_SBAB_BASE 0x7FFC040000ull +#define MME0_SBAB_MAX_OFFSET 0x5800 +#define MME0_SBAB_SECTION 0x1000 +#define mmMME0_PRTN_BASE 0x7FFC041000ull +#define MME0_PRTN_MAX_OFFSET 0x5000 +#define MME0_PRTN_SECTION 0x1F000 +#define mmMME0_CTRL_BASE 0x7FFC060000ull +#define MME0_CTRL_MAX_OFFSET 0xDA80 +#define MME0_CTRL_SECTION 0x8000 +#define mmARCH_MME0_CTRL_BASE 0x7FFC060008ull +#define ARCH_MME0_CTRL_MAX_OFFSET 0x3400 +#define ARCH_MME0_CTRL_SECTION 0x3400 +#define mmARCH_TENSOR_S_MME0_CTRL_BASE 0x7FFC06003Cull +#define ARCH_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_S_MME0_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_S_MME0_CTRL_BASE 0x7FFC060088ull +#define ARCH_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_S_MME0_CTRL_SECTION 0x2400 +#define mmARCH_TENSOR_L_MME0_CTRL_BASE 0x7FFC0600ACull +#define ARCH_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_L_MME0_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC0600F8ull +#define ARCH_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400 +#define mmARCH_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC06011Cull +#define ARCH_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400 +#define mmARCH_TENSOR_O_MME0_CTRL_BASE 0x7FFC060140ull +#define ARCH_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_O_MME0_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC06018Cull +#define ARCH_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400 +#define mmARCH_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC0601B0ull +#define ARCH_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400 +#define mmARCH_DESC_MME0_CTRL_BASE 0x7FFC0601D4ull +#define ARCH_DESC_MME0_CTRL_MAX_OFFSET 0x5400 +#define ARCH_DESC_MME0_CTRL_SECTION 0x2340 +#define mmSHADOW_0_MME0_CTRL_BASE 0x7FFC060408ull +#define SHADOW_0_MME0_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_0_MME0_CTRL_SECTION 0x3400 +#define mmSHADOW_0_TENSOR_S_MME0_CTRL_BASE 0x7FFC06043Cull +#define SHADOW_0_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_S_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_S_MME0_CTRL_BASE 0x7FFC060488ull +#define SHADOW_0_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_S_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_0_TENSOR_L_MME0_CTRL_BASE 0x7FFC0604ACull +#define SHADOW_0_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_L_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC0604F8ull +#define SHADOW_0_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_0_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC06051Cull +#define SHADOW_0_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_0_TENSOR_O_MME0_CTRL_BASE 0x7FFC060540ull +#define SHADOW_0_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_O_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC06058Cull +#define SHADOW_0_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_0_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC0605B0ull +#define SHADOW_0_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_0_DESC_MME0_CTRL_BASE 0x7FFC0605D4ull +#define SHADOW_0_DESC_MME0_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_0_DESC_MME0_CTRL_SECTION 0xB400 +#define mmSHADOW_1_MME0_CTRL_BASE 0x7FFC060688ull +#define SHADOW_1_MME0_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_1_MME0_CTRL_SECTION 0x3400 +#define mmSHADOW_1_TENSOR_S_MME0_CTRL_BASE 0x7FFC0606BCull +#define SHADOW_1_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_S_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_S_MME0_CTRL_BASE 0x7FFC060708ull +#define SHADOW_1_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_S_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_1_TENSOR_L_MME0_CTRL_BASE 0x7FFC06072Cull +#define SHADOW_1_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_L_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC060778ull +#define SHADOW_1_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_1_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC06079Cull +#define SHADOW_1_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_1_TENSOR_O_MME0_CTRL_BASE 0x7FFC0607C0ull +#define SHADOW_1_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_O_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC06080Cull +#define SHADOW_1_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_1_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC060830ull +#define SHADOW_1_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_1_DESC_MME0_CTRL_BASE 0x7FFC060854ull +#define SHADOW_1_DESC_MME0_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_1_DESC_MME0_CTRL_SECTION 0xB400 +#define mmSHADOW_2_MME0_CTRL_BASE 0x7FFC060908ull +#define SHADOW_2_MME0_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_2_MME0_CTRL_SECTION 0x3400 +#define mmSHADOW_2_TENSOR_S_MME0_CTRL_BASE 0x7FFC06093Cull +#define SHADOW_2_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_S_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_S_MME0_CTRL_BASE 0x7FFC060988ull +#define SHADOW_2_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_S_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_2_TENSOR_L_MME0_CTRL_BASE 0x7FFC0609ACull +#define SHADOW_2_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_L_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC0609F8ull +#define SHADOW_2_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_2_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC060A1Cull +#define SHADOW_2_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_2_TENSOR_O_MME0_CTRL_BASE 0x7FFC060A40ull +#define SHADOW_2_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_O_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC060A8Cull +#define SHADOW_2_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_2_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC060AB0ull +#define SHADOW_2_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_2_DESC_MME0_CTRL_BASE 0x7FFC060AD4ull +#define SHADOW_2_DESC_MME0_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_2_DESC_MME0_CTRL_SECTION 0xB400 +#define mmSHADOW_3_MME0_CTRL_BASE 0x7FFC060B88ull +#define SHADOW_3_MME0_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_3_MME0_CTRL_SECTION 0x3400 +#define mmSHADOW_3_TENSOR_S_MME0_CTRL_BASE 0x7FFC060BBCull +#define SHADOW_3_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_S_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_S_MME0_CTRL_BASE 0x7FFC060C08ull +#define SHADOW_3_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_S_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_3_TENSOR_L_MME0_CTRL_BASE 0x7FFC060C2Cull +#define SHADOW_3_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_L_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC060C78ull +#define SHADOW_3_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_3_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC060C9Cull +#define SHADOW_3_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_3_TENSOR_O_MME0_CTRL_BASE 0x7FFC060CC0ull +#define SHADOW_3_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_O_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC060D0Cull +#define SHADOW_3_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_3_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC060D30ull +#define SHADOW_3_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_3_DESC_MME0_CTRL_BASE 0x7FFC060D54ull +#define SHADOW_3_DESC_MME0_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_3_DESC_MME0_CTRL_SECTION 0x72AC +#define mmMME0_QM_BASE 0x7FFC068000ull +#define MME0_QM_MAX_OFFSET 0xD040 +#define MME0_QM_SECTION 0x38000 +#define mmMME1_ACC_BASE 0x7FFC0A0000ull +#define MME1_ACC_MAX_OFFSET 0x5C00 +#define MME1_ACC_SECTION 0x20000 +#define mmMME1_SBAB_BASE 0x7FFC0C0000ull +#define MME1_SBAB_MAX_OFFSET 0x5800 +#define MME1_SBAB_SECTION 0x1000 +#define mmMME1_PRTN_BASE 0x7FFC0C1000ull +#define MME1_PRTN_MAX_OFFSET 0x5000 +#define MME1_PRTN_SECTION 0x1F000 +#define mmMME1_CTRL_BASE 0x7FFC0E0000ull +#define MME1_CTRL_MAX_OFFSET 0xDA80 +#define MME1_CTRL_SECTION 0x8000 +#define mmARCH_MME1_CTRL_BASE 0x7FFC0E0008ull +#define ARCH_MME1_CTRL_MAX_OFFSET 0x3400 +#define ARCH_MME1_CTRL_SECTION 0x3400 +#define mmARCH_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E003Cull +#define ARCH_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_S_MME1_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_S_MME1_CTRL_BASE 0x7FFC0E0088ull +#define ARCH_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_S_MME1_CTRL_SECTION 0x2400 +#define mmARCH_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E00ACull +#define ARCH_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_L_MME1_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E00F8ull +#define ARCH_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400 +#define mmARCH_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E011Cull +#define ARCH_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400 +#define mmARCH_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0140ull +#define ARCH_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_O_MME1_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E018Cull +#define ARCH_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400 +#define mmARCH_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E01B0ull +#define ARCH_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400 +#define mmARCH_DESC_MME1_CTRL_BASE 0x7FFC0E01D4ull +#define ARCH_DESC_MME1_CTRL_MAX_OFFSET 0x5400 +#define ARCH_DESC_MME1_CTRL_SECTION 0x2340 +#define mmSHADOW_0_MME1_CTRL_BASE 0x7FFC0E0408ull +#define SHADOW_0_MME1_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_0_MME1_CTRL_SECTION 0x3400 +#define mmSHADOW_0_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E043Cull +#define SHADOW_0_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_S_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_S_MME1_CTRL_BASE 0x7FFC0E0488ull +#define SHADOW_0_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_S_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_0_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E04ACull +#define SHADOW_0_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_L_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E04F8ull +#define SHADOW_0_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_0_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E051Cull +#define SHADOW_0_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_0_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0540ull +#define SHADOW_0_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_O_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E058Cull +#define SHADOW_0_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_0_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E05B0ull +#define SHADOW_0_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_0_DESC_MME1_CTRL_BASE 0x7FFC0E05D4ull +#define SHADOW_0_DESC_MME1_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_0_DESC_MME1_CTRL_SECTION 0xB400 +#define mmSHADOW_1_MME1_CTRL_BASE 0x7FFC0E0688ull +#define SHADOW_1_MME1_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_1_MME1_CTRL_SECTION 0x3400 +#define mmSHADOW_1_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E06BCull +#define SHADOW_1_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_S_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_S_MME1_CTRL_BASE 0x7FFC0E0708ull +#define SHADOW_1_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_S_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_1_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E072Cull +#define SHADOW_1_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_L_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E0778ull +#define SHADOW_1_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_1_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E079Cull +#define SHADOW_1_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_1_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E07C0ull +#define SHADOW_1_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_O_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E080Cull +#define SHADOW_1_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_1_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E0830ull +#define SHADOW_1_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_1_DESC_MME1_CTRL_BASE 0x7FFC0E0854ull +#define SHADOW_1_DESC_MME1_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_1_DESC_MME1_CTRL_SECTION 0xB400 +#define mmSHADOW_2_MME1_CTRL_BASE 0x7FFC0E0908ull +#define SHADOW_2_MME1_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_2_MME1_CTRL_SECTION 0x3400 +#define mmSHADOW_2_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E093Cull +#define SHADOW_2_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_S_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_S_MME1_CTRL_BASE 0x7FFC0E0988ull +#define SHADOW_2_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_S_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_2_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E09ACull +#define SHADOW_2_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_L_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E09F8ull +#define SHADOW_2_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_2_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E0A1Cull +#define SHADOW_2_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_2_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0A40ull +#define SHADOW_2_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_O_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E0A8Cull +#define SHADOW_2_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_2_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E0AB0ull +#define SHADOW_2_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_2_DESC_MME1_CTRL_BASE 0x7FFC0E0AD4ull +#define SHADOW_2_DESC_MME1_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_2_DESC_MME1_CTRL_SECTION 0xB400 +#define mmSHADOW_3_MME1_CTRL_BASE 0x7FFC0E0B88ull +#define SHADOW_3_MME1_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_3_MME1_CTRL_SECTION 0x3400 +#define mmSHADOW_3_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E0BBCull +#define SHADOW_3_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_S_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_S_MME1_CTRL_BASE 0x7FFC0E0C08ull +#define SHADOW_3_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_S_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_3_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E0C2Cull +#define SHADOW_3_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_L_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E0C78ull +#define SHADOW_3_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_3_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E0C9Cull +#define SHADOW_3_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_3_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0CC0ull +#define SHADOW_3_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_O_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E0D0Cull +#define SHADOW_3_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_3_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E0D30ull +#define SHADOW_3_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_3_DESC_MME1_CTRL_BASE 0x7FFC0E0D54ull +#define SHADOW_3_DESC_MME1_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_3_DESC_MME1_CTRL_SECTION 0x72AC +#define mmMME1_QM_BASE 0x7FFC0E8000ull +#define MME1_QM_MAX_OFFSET 0xD040 +#define MME1_QM_SECTION 0x38000 +#define mmMME2_ACC_BASE 0x7FFC120000ull +#define MME2_ACC_MAX_OFFSET 0x5C00 +#define MME2_ACC_SECTION 0x20000 +#define mmMME2_SBAB_BASE 0x7FFC140000ull +#define MME2_SBAB_MAX_OFFSET 0x5800 +#define MME2_SBAB_SECTION 0x1000 +#define mmMME2_PRTN_BASE 0x7FFC141000ull +#define MME2_PRTN_MAX_OFFSET 0x5000 +#define MME2_PRTN_SECTION 0x1F000 +#define mmMME2_CTRL_BASE 0x7FFC160000ull +#define MME2_CTRL_MAX_OFFSET 0xDA80 +#define MME2_CTRL_SECTION 0x8000 +#define mmARCH_MME2_CTRL_BASE 0x7FFC160008ull +#define ARCH_MME2_CTRL_MAX_OFFSET 0x3400 +#define ARCH_MME2_CTRL_SECTION 0x3400 +#define mmARCH_TENSOR_S_MME2_CTRL_BASE 0x7FFC16003Cull +#define ARCH_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_S_MME2_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_S_MME2_CTRL_BASE 0x7FFC160088ull +#define ARCH_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_S_MME2_CTRL_SECTION 0x2400 +#define mmARCH_TENSOR_L_MME2_CTRL_BASE 0x7FFC1600ACull +#define ARCH_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_L_MME2_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC1600F8ull +#define ARCH_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400 +#define mmARCH_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC16011Cull +#define ARCH_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400 +#define mmARCH_TENSOR_O_MME2_CTRL_BASE 0x7FFC160140ull +#define ARCH_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_O_MME2_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC16018Cull +#define ARCH_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400 +#define mmARCH_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC1601B0ull +#define ARCH_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400 +#define mmARCH_DESC_MME2_CTRL_BASE 0x7FFC1601D4ull +#define ARCH_DESC_MME2_CTRL_MAX_OFFSET 0x5400 +#define ARCH_DESC_MME2_CTRL_SECTION 0x2340 +#define mmSHADOW_0_MME2_CTRL_BASE 0x7FFC160408ull +#define SHADOW_0_MME2_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_0_MME2_CTRL_SECTION 0x3400 +#define mmSHADOW_0_TENSOR_S_MME2_CTRL_BASE 0x7FFC16043Cull +#define SHADOW_0_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_S_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_S_MME2_CTRL_BASE 0x7FFC160488ull +#define SHADOW_0_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_S_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_0_TENSOR_L_MME2_CTRL_BASE 0x7FFC1604ACull +#define SHADOW_0_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_L_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC1604F8ull +#define SHADOW_0_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_0_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC16051Cull +#define SHADOW_0_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_0_TENSOR_O_MME2_CTRL_BASE 0x7FFC160540ull +#define SHADOW_0_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_O_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC16058Cull +#define SHADOW_0_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_0_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC1605B0ull +#define SHADOW_0_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_0_DESC_MME2_CTRL_BASE 0x7FFC1605D4ull +#define SHADOW_0_DESC_MME2_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_0_DESC_MME2_CTRL_SECTION 0xB400 +#define mmSHADOW_1_MME2_CTRL_BASE 0x7FFC160688ull +#define SHADOW_1_MME2_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_1_MME2_CTRL_SECTION 0x3400 +#define mmSHADOW_1_TENSOR_S_MME2_CTRL_BASE 0x7FFC1606BCull +#define SHADOW_1_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_S_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_S_MME2_CTRL_BASE 0x7FFC160708ull +#define SHADOW_1_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_S_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_1_TENSOR_L_MME2_CTRL_BASE 0x7FFC16072Cull +#define SHADOW_1_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_L_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC160778ull +#define SHADOW_1_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_1_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC16079Cull +#define SHADOW_1_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_1_TENSOR_O_MME2_CTRL_BASE 0x7FFC1607C0ull +#define SHADOW_1_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_O_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC16080Cull +#define SHADOW_1_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_1_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC160830ull +#define SHADOW_1_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_1_DESC_MME2_CTRL_BASE 0x7FFC160854ull +#define SHADOW_1_DESC_MME2_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_1_DESC_MME2_CTRL_SECTION 0xB400 +#define mmSHADOW_2_MME2_CTRL_BASE 0x7FFC160908ull +#define SHADOW_2_MME2_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_2_MME2_CTRL_SECTION 0x3400 +#define mmSHADOW_2_TENSOR_S_MME2_CTRL_BASE 0x7FFC16093Cull +#define SHADOW_2_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_S_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_S_MME2_CTRL_BASE 0x7FFC160988ull +#define SHADOW_2_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_S_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_2_TENSOR_L_MME2_CTRL_BASE 0x7FFC1609ACull +#define SHADOW_2_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_L_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC1609F8ull +#define SHADOW_2_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_2_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC160A1Cull +#define SHADOW_2_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_2_TENSOR_O_MME2_CTRL_BASE 0x7FFC160A40ull +#define SHADOW_2_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_O_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC160A8Cull +#define SHADOW_2_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_2_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC160AB0ull +#define SHADOW_2_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_2_DESC_MME2_CTRL_BASE 0x7FFC160AD4ull +#define SHADOW_2_DESC_MME2_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_2_DESC_MME2_CTRL_SECTION 0xB400 +#define mmSHADOW_3_MME2_CTRL_BASE 0x7FFC160B88ull +#define SHADOW_3_MME2_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_3_MME2_CTRL_SECTION 0x3400 +#define mmSHADOW_3_TENSOR_S_MME2_CTRL_BASE 0x7FFC160BBCull +#define SHADOW_3_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_S_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_S_MME2_CTRL_BASE 0x7FFC160C08ull +#define SHADOW_3_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_S_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_3_TENSOR_L_MME2_CTRL_BASE 0x7FFC160C2Cull +#define SHADOW_3_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_L_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC160C78ull +#define SHADOW_3_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_3_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC160C9Cull +#define SHADOW_3_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_3_TENSOR_O_MME2_CTRL_BASE 0x7FFC160CC0ull +#define SHADOW_3_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_O_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC160D0Cull +#define SHADOW_3_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_3_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC160D30ull +#define SHADOW_3_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_3_DESC_MME2_CTRL_BASE 0x7FFC160D54ull +#define SHADOW_3_DESC_MME2_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_3_DESC_MME2_CTRL_SECTION 0x72AC +#define mmMME2_QM_BASE 0x7FFC168000ull +#define MME2_QM_MAX_OFFSET 0xD040 +#define MME2_QM_SECTION 0x38000 +#define mmMME3_ACC_BASE 0x7FFC1A0000ull +#define MME3_ACC_MAX_OFFSET 0x5C00 +#define MME3_ACC_SECTION 0x20000 +#define mmMME3_SBAB_BASE 0x7FFC1C0000ull +#define MME3_SBAB_MAX_OFFSET 0x5800 +#define MME3_SBAB_SECTION 0x1000 +#define mmMME3_PRTN_BASE 0x7FFC1C1000ull +#define MME3_PRTN_MAX_OFFSET 0x5000 +#define MME3_PRTN_SECTION 0x1F000 +#define mmMME3_CTRL_BASE 0x7FFC1E0000ull +#define MME3_CTRL_MAX_OFFSET 0xDA80 +#define MME3_CTRL_SECTION 0x8000 +#define mmARCH_MME3_CTRL_BASE 0x7FFC1E0008ull +#define ARCH_MME3_CTRL_MAX_OFFSET 0x3400 +#define ARCH_MME3_CTRL_SECTION 0x3400 +#define mmARCH_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E003Cull +#define ARCH_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_S_MME3_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_S_MME3_CTRL_BASE 0x7FFC1E0088ull +#define ARCH_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_S_MME3_CTRL_SECTION 0x2400 +#define mmARCH_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E00ACull +#define ARCH_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_L_MME3_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E00F8ull +#define ARCH_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400 +#define mmARCH_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E011Cull +#define ARCH_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400 +#define mmARCH_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0140ull +#define ARCH_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_O_MME3_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E018Cull +#define ARCH_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400 +#define mmARCH_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E01B0ull +#define ARCH_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400 +#define mmARCH_DESC_MME3_CTRL_BASE 0x7FFC1E01D4ull +#define ARCH_DESC_MME3_CTRL_MAX_OFFSET 0x5400 +#define ARCH_DESC_MME3_CTRL_SECTION 0x2340 +#define mmSHADOW_0_MME3_CTRL_BASE 0x7FFC1E0408ull +#define SHADOW_0_MME3_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_0_MME3_CTRL_SECTION 0x3400 +#define mmSHADOW_0_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E043Cull +#define SHADOW_0_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_S_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_S_MME3_CTRL_BASE 0x7FFC1E0488ull +#define SHADOW_0_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_S_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_0_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E04ACull +#define SHADOW_0_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_L_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E04F8ull +#define SHADOW_0_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_0_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E051Cull +#define SHADOW_0_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_0_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0540ull +#define SHADOW_0_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_O_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E058Cull +#define SHADOW_0_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_0_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E05B0ull +#define SHADOW_0_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_0_DESC_MME3_CTRL_BASE 0x7FFC1E05D4ull +#define SHADOW_0_DESC_MME3_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_0_DESC_MME3_CTRL_SECTION 0xB400 +#define mmSHADOW_1_MME3_CTRL_BASE 0x7FFC1E0688ull +#define SHADOW_1_MME3_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_1_MME3_CTRL_SECTION 0x3400 +#define mmSHADOW_1_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E06BCull +#define SHADOW_1_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_S_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_S_MME3_CTRL_BASE 0x7FFC1E0708ull +#define SHADOW_1_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_S_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_1_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E072Cull +#define SHADOW_1_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_L_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E0778ull +#define SHADOW_1_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_1_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E079Cull +#define SHADOW_1_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_1_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E07C0ull +#define SHADOW_1_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_O_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E080Cull +#define SHADOW_1_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_1_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E0830ull +#define SHADOW_1_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_1_DESC_MME3_CTRL_BASE 0x7FFC1E0854ull +#define SHADOW_1_DESC_MME3_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_1_DESC_MME3_CTRL_SECTION 0xB400 +#define mmSHADOW_2_MME3_CTRL_BASE 0x7FFC1E0908ull +#define SHADOW_2_MME3_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_2_MME3_CTRL_SECTION 0x3400 +#define mmSHADOW_2_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E093Cull +#define SHADOW_2_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_S_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_S_MME3_CTRL_BASE 0x7FFC1E0988ull +#define SHADOW_2_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_S_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_2_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E09ACull +#define SHADOW_2_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_L_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E09F8ull +#define SHADOW_2_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_2_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E0A1Cull +#define SHADOW_2_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_2_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0A40ull +#define SHADOW_2_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_O_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E0A8Cull +#define SHADOW_2_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_2_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E0AB0ull +#define SHADOW_2_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_2_DESC_MME3_CTRL_BASE 0x7FFC1E0AD4ull +#define SHADOW_2_DESC_MME3_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_2_DESC_MME3_CTRL_SECTION 0xB400 +#define mmSHADOW_3_MME3_CTRL_BASE 0x7FFC1E0B88ull +#define SHADOW_3_MME3_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_3_MME3_CTRL_SECTION 0x3400 +#define mmSHADOW_3_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E0BBCull +#define SHADOW_3_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_S_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_S_MME3_CTRL_BASE 0x7FFC1E0C08ull +#define SHADOW_3_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_S_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_3_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E0C2Cull +#define SHADOW_3_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_L_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E0C78ull +#define SHADOW_3_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_3_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E0C9Cull +#define SHADOW_3_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_3_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0CC0ull +#define SHADOW_3_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_O_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E0D0Cull +#define SHADOW_3_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_3_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E0D30ull +#define SHADOW_3_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_3_DESC_MME3_CTRL_BASE 0x7FFC1E0D54ull +#define SHADOW_3_DESC_MME3_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_3_DESC_MME3_CTRL_SECTION 0x72AC +#define mmMME3_QM_BASE 0x7FFC1E8000ull +#define MME3_QM_MAX_OFFSET 0xD040 +#define MME3_QM_SECTION 0x18000 +#define mmSRAM_Y0_X0_BANK_BASE 0x7FFC200000ull +#define SRAM_Y0_X0_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y0_X0_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X0_RTR_BASE 0x7FFC201000ull +#define SRAM_Y0_X0_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y0_X0_RTR_SECTION 0x7000 +#define mmSRAM_Y0_X1_BANK_BASE 0x7FFC208000ull +#define SRAM_Y0_X1_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y0_X1_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X1_RTR_BASE 0x7FFC209000ull +#define SRAM_Y0_X1_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y0_X1_RTR_SECTION 0x7000 +#define mmSRAM_Y0_X2_BANK_BASE 0x7FFC210000ull +#define SRAM_Y0_X2_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y0_X2_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X2_RTR_BASE 0x7FFC211000ull +#define SRAM_Y0_X2_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y0_X2_RTR_SECTION 0x7000 +#define mmSRAM_Y0_X3_BANK_BASE 0x7FFC218000ull +#define SRAM_Y0_X3_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y0_X3_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X3_RTR_BASE 0x7FFC219000ull +#define SRAM_Y0_X3_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y0_X3_RTR_SECTION 0x7000 +#define mmSRAM_Y0_X4_BANK_BASE 0x7FFC220000ull +#define SRAM_Y0_X4_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y0_X4_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X4_RTR_BASE 0x7FFC221000ull +#define SRAM_Y0_X4_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y0_X4_RTR_SECTION 0x7000 +#define mmSRAM_Y0_X5_BANK_BASE 0x7FFC228000ull +#define SRAM_Y0_X5_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y0_X5_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X5_RTR_BASE 0x7FFC229000ull +#define SRAM_Y0_X5_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y0_X5_RTR_SECTION 0x7000 +#define mmSRAM_Y0_X6_BANK_BASE 0x7FFC230000ull +#define SRAM_Y0_X6_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y0_X6_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X6_RTR_BASE 0x7FFC231000ull +#define SRAM_Y0_X6_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y0_X6_RTR_SECTION 0x7000 +#define mmSRAM_Y0_X7_BANK_BASE 0x7FFC238000ull +#define SRAM_Y0_X7_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y0_X7_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X7_RTR_BASE 0x7FFC239000ull +#define SRAM_Y0_X7_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y0_X7_RTR_SECTION 0x7000 +#define mmSRAM_Y1_X0_BANK_BASE 0x7FFC240000ull +#define SRAM_Y1_X0_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y1_X0_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X0_RTR_BASE 0x7FFC241000ull +#define SRAM_Y1_X0_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y1_X0_RTR_SECTION 0x7000 +#define mmSRAM_Y1_X1_BANK_BASE 0x7FFC248000ull +#define SRAM_Y1_X1_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y1_X1_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X1_RTR_BASE 0x7FFC249000ull +#define SRAM_Y1_X1_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y1_X1_RTR_SECTION 0x7000 +#define mmSRAM_Y1_X2_BANK_BASE 0x7FFC250000ull +#define SRAM_Y1_X2_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y1_X2_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X2_RTR_BASE 0x7FFC251000ull +#define SRAM_Y1_X2_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y1_X2_RTR_SECTION 0x7000 +#define mmSRAM_Y1_X3_BANK_BASE 0x7FFC258000ull +#define SRAM_Y1_X3_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y1_X3_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X3_RTR_BASE 0x7FFC259000ull +#define SRAM_Y1_X3_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y1_X3_RTR_SECTION 0x7000 +#define mmSRAM_Y1_X4_BANK_BASE 0x7FFC260000ull +#define SRAM_Y1_X4_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y1_X4_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X4_RTR_BASE 0x7FFC261000ull +#define SRAM_Y1_X4_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y1_X4_RTR_SECTION 0x7000 +#define mmSRAM_Y1_X5_BANK_BASE 0x7FFC268000ull +#define SRAM_Y1_X5_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y1_X5_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X5_RTR_BASE 0x7FFC269000ull +#define SRAM_Y1_X5_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y1_X5_RTR_SECTION 0x7000 +#define mmSRAM_Y1_X6_BANK_BASE 0x7FFC270000ull +#define SRAM_Y1_X6_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y1_X6_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X6_RTR_BASE 0x7FFC271000ull +#define SRAM_Y1_X6_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y1_X6_RTR_SECTION 0x7000 +#define mmSRAM_Y1_X7_BANK_BASE 0x7FFC278000ull +#define SRAM_Y1_X7_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y1_X7_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X7_RTR_BASE 0x7FFC279000ull +#define SRAM_Y1_X7_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y1_X7_RTR_SECTION 0x7000 +#define mmSRAM_Y2_X0_BANK_BASE 0x7FFC280000ull +#define SRAM_Y2_X0_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y2_X0_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X0_RTR_BASE 0x7FFC281000ull +#define SRAM_Y2_X0_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y2_X0_RTR_SECTION 0x7000 +#define mmSRAM_Y2_X1_BANK_BASE 0x7FFC288000ull +#define SRAM_Y2_X1_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y2_X1_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X1_RTR_BASE 0x7FFC289000ull +#define SRAM_Y2_X1_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y2_X1_RTR_SECTION 0x7000 +#define mmSRAM_Y2_X2_BANK_BASE 0x7FFC290000ull +#define SRAM_Y2_X2_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y2_X2_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X2_RTR_BASE 0x7FFC291000ull +#define SRAM_Y2_X2_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y2_X2_RTR_SECTION 0x7000 +#define mmSRAM_Y2_X3_BANK_BASE 0x7FFC298000ull +#define SRAM_Y2_X3_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y2_X3_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X3_RTR_BASE 0x7FFC299000ull +#define SRAM_Y2_X3_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y2_X3_RTR_SECTION 0x7000 +#define mmSRAM_Y2_X4_BANK_BASE 0x7FFC2A0000ull +#define SRAM_Y2_X4_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y2_X4_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X4_RTR_BASE 0x7FFC2A1000ull +#define SRAM_Y2_X4_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y2_X4_RTR_SECTION 0x7000 +#define mmSRAM_Y2_X5_BANK_BASE 0x7FFC2A8000ull +#define SRAM_Y2_X5_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y2_X5_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X5_RTR_BASE 0x7FFC2A9000ull +#define SRAM_Y2_X5_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y2_X5_RTR_SECTION 0x7000 +#define mmSRAM_Y2_X6_BANK_BASE 0x7FFC2B0000ull +#define SRAM_Y2_X6_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y2_X6_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X6_RTR_BASE 0x7FFC2B1000ull +#define SRAM_Y2_X6_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y2_X6_RTR_SECTION 0x7000 +#define mmSRAM_Y2_X7_BANK_BASE 0x7FFC2B8000ull +#define SRAM_Y2_X7_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y2_X7_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X7_RTR_BASE 0x7FFC2B9000ull +#define SRAM_Y2_X7_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y2_X7_RTR_SECTION 0x7000 +#define mmSRAM_Y3_X0_BANK_BASE 0x7FFC2C0000ull +#define SRAM_Y3_X0_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y3_X0_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X0_RTR_BASE 0x7FFC2C1000ull +#define SRAM_Y3_X0_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y3_X0_RTR_SECTION 0x7000 +#define mmSRAM_Y3_X1_BANK_BASE 0x7FFC2C8000ull +#define SRAM_Y3_X1_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y3_X1_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X1_RTR_BASE 0x7FFC2C9000ull +#define SRAM_Y3_X1_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y3_X1_RTR_SECTION 0x7000 +#define mmSRAM_Y3_X2_BANK_BASE 0x7FFC2D0000ull +#define SRAM_Y3_X2_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y3_X2_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X2_RTR_BASE 0x7FFC2D1000ull +#define SRAM_Y3_X2_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y3_X2_RTR_SECTION 0x7000 +#define mmSRAM_Y3_X3_BANK_BASE 0x7FFC2D8000ull +#define SRAM_Y3_X3_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y3_X3_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X3_RTR_BASE 0x7FFC2D9000ull +#define SRAM_Y3_X3_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y3_X3_RTR_SECTION 0x7000 +#define mmSRAM_Y3_X4_BANK_BASE 0x7FFC2E0000ull +#define SRAM_Y3_X4_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y3_X4_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X4_RTR_BASE 0x7FFC2E1000ull +#define SRAM_Y3_X4_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y3_X4_RTR_SECTION 0x7000 +#define mmSRAM_Y3_X5_BANK_BASE 0x7FFC2E8000ull +#define SRAM_Y3_X5_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y3_X5_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X5_RTR_BASE 0x7FFC2E9000ull +#define SRAM_Y3_X5_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y3_X5_RTR_SECTION 0x7000 +#define mmSRAM_Y3_X6_BANK_BASE 0x7FFC2F0000ull +#define SRAM_Y3_X6_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y3_X6_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X6_RTR_BASE 0x7FFC2F1000ull +#define SRAM_Y3_X6_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y3_X6_RTR_SECTION 0x7000 +#define mmSRAM_Y3_X7_BANK_BASE 0x7FFC2F8000ull +#define SRAM_Y3_X7_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y3_X7_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X7_RTR_BASE 0x7FFC2F9000ull +#define SRAM_Y3_X7_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y3_X7_RTR_SECTION 0x7000 +#define mmSIF_RTR_0_BASE 0x7FFC300000ull +#define SIF_RTR_0_MAX_OFFSET 0x6500 +#define SIF_RTR_0_SECTION 0x6000 +#define mmSIF_RTR_CTRL_0_BASE 0x7FFC306000ull +#define SIF_RTR_CTRL_0_MAX_OFFSET 0xCC00 +#define SIF_RTR_CTRL_0_SECTION 0xA000 +#define mmSIF_RTR_1_BASE 0x7FFC310000ull +#define SIF_RTR_1_MAX_OFFSET 0x6500 +#define SIF_RTR_1_SECTION 0x6000 +#define mmSIF_RTR_CTRL_1_BASE 0x7FFC316000ull +#define SIF_RTR_CTRL_1_MAX_OFFSET 0xCC00 +#define SIF_RTR_CTRL_1_SECTION 0xA000 +#define mmSIF_RTR_2_BASE 0x7FFC320000ull +#define SIF_RTR_2_MAX_OFFSET 0x6500 +#define SIF_RTR_2_SECTION 0x6000 +#define mmSIF_RTR_CTRL_2_BASE 0x7FFC326000ull +#define SIF_RTR_CTRL_2_MAX_OFFSET 0xCC00 +#define SIF_RTR_CTRL_2_SECTION 0xA000 +#define mmSIF_RTR_3_BASE 0x7FFC330000ull +#define SIF_RTR_3_MAX_OFFSET 0x6500 +#define SIF_RTR_3_SECTION 0x6000 +#define mmSIF_RTR_CTRL_3_BASE 0x7FFC336000ull +#define SIF_RTR_CTRL_3_MAX_OFFSET 0xCC00 +#define SIF_RTR_CTRL_3_SECTION 0xA000 +#define mmSIF_RTR_4_BASE 0x7FFC340000ull +#define SIF_RTR_4_MAX_OFFSET 0x6500 +#define SIF_RTR_4_SECTION 0x6000 +#define mmSIF_RTR_CTRL_4_BASE 0x7FFC346000ull +#define SIF_RTR_CTRL_4_MAX_OFFSET 0xCC00 +#define SIF_RTR_CTRL_4_SECTION 0xA000 +#define mmSIF_RTR_5_BASE 0x7FFC350000ull +#define SIF_RTR_5_MAX_OFFSET 0x6500 +#define SIF_RTR_5_SECTION 0x6000 +#define mmSIF_RTR_CTRL_5_BASE 0x7FFC356000ull +#define SIF_RTR_CTRL_5_MAX_OFFSET 0xCC00 +#define SIF_RTR_CTRL_5_SECTION 0xA000 +#define mmSIF_RTR_6_BASE 0x7FFC360000ull +#define SIF_RTR_6_MAX_OFFSET 0x6500 +#define SIF_RTR_6_SECTION 0x6000 +#define mmSIF_RTR_CTRL_6_BASE 0x7FFC366000ull +#define SIF_RTR_CTRL_6_MAX_OFFSET 0xCC00 +#define SIF_RTR_CTRL_6_SECTION 0xA000 +#define mmSIF_RTR_7_BASE 0x7FFC370000ull +#define SIF_RTR_7_MAX_OFFSET 0x6500 +#define SIF_RTR_7_SECTION 0x6000 +#define mmSIF_RTR_CTRL_7_BASE 0x7FFC376000ull +#define SIF_RTR_CTRL_7_MAX_OFFSET 0xCC00 +#define SIF_RTR_CTRL_7_SECTION 0xA000 +#define mmNIF_RTR_0_BASE 0x7FFC380000ull +#define NIF_RTR_0_MAX_OFFSET 0x6500 +#define NIF_RTR_0_SECTION 0x6000 +#define mmNIF_RTR_CTRL_0_BASE 0x7FFC386000ull +#define NIF_RTR_CTRL_0_MAX_OFFSET 0xCC00 +#define NIF_RTR_CTRL_0_SECTION 0xA000 +#define mmNIF_RTR_1_BASE 0x7FFC390000ull +#define NIF_RTR_1_MAX_OFFSET 0x6500 +#define NIF_RTR_1_SECTION 0x6000 +#define mmNIF_RTR_CTRL_1_BASE 0x7FFC396000ull +#define NIF_RTR_CTRL_1_MAX_OFFSET 0xCC00 +#define NIF_RTR_CTRL_1_SECTION 0xA000 +#define mmNIF_RTR_2_BASE 0x7FFC3A0000ull +#define NIF_RTR_2_MAX_OFFSET 0x6500 +#define NIF_RTR_2_SECTION 0x6000 +#define mmNIF_RTR_CTRL_2_BASE 0x7FFC3A6000ull +#define NIF_RTR_CTRL_2_MAX_OFFSET 0xCC00 +#define NIF_RTR_CTRL_2_SECTION 0xA000 +#define mmNIF_RTR_3_BASE 0x7FFC3B0000ull +#define NIF_RTR_3_MAX_OFFSET 0x6500 +#define NIF_RTR_3_SECTION 0x6000 +#define mmNIF_RTR_CTRL_3_BASE 0x7FFC3B6000ull +#define NIF_RTR_CTRL_3_MAX_OFFSET 0xCC00 +#define NIF_RTR_CTRL_3_SECTION 0xA000 +#define mmNIF_RTR_4_BASE 0x7FFC3C0000ull +#define NIF_RTR_4_MAX_OFFSET 0x6500 +#define NIF_RTR_4_SECTION 0x6000 +#define mmNIF_RTR_CTRL_4_BASE 0x7FFC3C6000ull +#define NIF_RTR_CTRL_4_MAX_OFFSET 0xCC00 +#define NIF_RTR_CTRL_4_SECTION 0xA000 +#define mmNIF_RTR_5_BASE 0x7FFC3D0000ull +#define NIF_RTR_5_MAX_OFFSET 0x6500 +#define NIF_RTR_5_SECTION 0x6000 +#define mmNIF_RTR_CTRL_5_BASE 0x7FFC3D6000ull +#define NIF_RTR_CTRL_5_MAX_OFFSET 0xCC00 +#define NIF_RTR_CTRL_5_SECTION 0xA000 +#define mmNIF_RTR_6_BASE 0x7FFC3E0000ull +#define NIF_RTR_6_MAX_OFFSET 0x6500 +#define NIF_RTR_6_SECTION 0x6000 +#define mmNIF_RTR_CTRL_6_BASE 0x7FFC3E6000ull +#define NIF_RTR_CTRL_6_MAX_OFFSET 0xCC00 +#define NIF_RTR_CTRL_6_SECTION 0xA000 +#define mmNIF_RTR_7_BASE 0x7FFC3F0000ull +#define NIF_RTR_7_MAX_OFFSET 0x6500 +#define NIF_RTR_7_SECTION 0x6000 +#define mmNIF_RTR_CTRL_7_BASE 0x7FFC3F6000ull +#define NIF_RTR_CTRL_7_MAX_OFFSET 0xCC00 +#define NIF_RTR_CTRL_7_SECTION 0x4B000 +#define mmCPU_CA53_CFG_BASE 0x7FFC441000ull +#define CPU_CA53_CFG_MAX_OFFSET 0x2180 +#define CPU_CA53_CFG_SECTION 0x1000 +#define mmCPU_IF_BASE 0x7FFC442000ull +#define CPU_IF_MAX_OFFSET 0x43C0 +#define CPU_IF_SECTION 0x2000 +#define mmCPU_TIMESTAMP_BASE 0x7FFC444000ull +#define CPU_TIMESTAMP_MAX_OFFSET 0x1000 +#define CPU_TIMESTAMP_SECTION 0x3C000 +#define mmDMA_IF_W_S_BASE 0x7FFC480000ull +#define DMA_IF_W_S_MAX_OFFSET 0x8380 +#define DMA_IF_W_S_SECTION 0x1000 +#define mmDMA_IF_W_S_DOWN_CH0_BASE 0x7FFC481000ull +#define DMA_IF_W_S_DOWN_CH0_MAX_OFFSET 0xCC00 +#define DMA_IF_W_S_DOWN_CH0_SECTION 0x1000 +#define mmDMA_IF_W_S_DOWN_CH1_BASE 0x7FFC482000ull +#define DMA_IF_W_S_DOWN_CH1_MAX_OFFSET 0xCC00 +#define DMA_IF_W_S_DOWN_CH1_SECTION 0x5000 +#define mmDMA_W_PLL_BASE 0x7FFC487000ull +#define DMA_W_PLL_MAX_OFFSET 0x5200 +#define DMA_W_PLL_SECTION 0x1000 +#define mmIF_W_PLL_BASE 0x7FFC488000ull +#define IF_W_PLL_MAX_OFFSET 0x5200 +#define IF_W_PLL_SECTION 0x1000 +#define mmDMA_IF_W_S_DOWN_BASE 0x7FFC489000ull +#define DMA_IF_W_S_DOWN_MAX_OFFSET 0x1500 +#define DMA_IF_W_S_DOWN_SECTION 0x7000 +#define mmSYNC_MNGR_GLBL_W_S_BASE 0x7FFC490000ull +#define SYNC_MNGR_GLBL_W_S_MAX_OFFSET 0x6C00 +#define SYNC_MNGR_GLBL_W_S_SECTION 0x1000 +#define mmSYNC_MNGR_OBJS_W_S_BASE 0x7FFC491000ull +#define SYNC_MNGR_OBJS_W_S_MAX_OFFSET 0x5C00 +#define SYNC_MNGR_OBJS_W_S_SECTION 0xF000 +#define mmDMA_IF_E_S_BASE 0x7FFC4A0000ull +#define DMA_IF_E_S_MAX_OFFSET 0x8380 +#define DMA_IF_E_S_SECTION 0x1000 +#define mmDMA_IF_E_S_DOWN_CH0_BASE 0x7FFC4A1000ull +#define DMA_IF_E_S_DOWN_CH0_MAX_OFFSET 0xCC00 +#define DMA_IF_E_S_DOWN_CH0_SECTION 0x1000 +#define mmDMA_IF_E_S_DOWN_CH1_BASE 0x7FFC4A2000ull +#define DMA_IF_E_S_DOWN_CH1_MAX_OFFSET 0xCC00 +#define DMA_IF_E_S_DOWN_CH1_SECTION 0x5000 +#define mmIF_E_PLL_BASE 0x7FFC4A7000ull +#define IF_E_PLL_MAX_OFFSET 0x5200 +#define IF_E_PLL_SECTION 0x1000 +#define mmDMA_E_PLL_BASE 0x7FFC4A8000ull +#define DMA_E_PLL_MAX_OFFSET 0x5200 +#define DMA_E_PLL_SECTION 0x1000 +#define mmDMA_IF_E_S_DOWN_BASE 0x7FFC4A9000ull +#define DMA_IF_E_S_DOWN_MAX_OFFSET 0x1500 +#define DMA_IF_E_S_DOWN_SECTION 0x7000 +#define mmSYNC_MNGR_GLBL_E_S_BASE 0x7FFC4B0000ull +#define SYNC_MNGR_GLBL_E_S_MAX_OFFSET 0x6C00 +#define SYNC_MNGR_GLBL_E_S_SECTION 0x1000 +#define mmSYNC_MNGR_OBJS_E_S_BASE 0x7FFC4B1000ull +#define SYNC_MNGR_OBJS_E_S_MAX_OFFSET 0x5C00 +#define SYNC_MNGR_OBJS_E_S_SECTION 0xF000 +#define mmDMA_IF_W_N_BASE 0x7FFC4C0000ull +#define DMA_IF_W_N_MAX_OFFSET 0x8380 +#define DMA_IF_W_N_SECTION 0x1000 +#define mmDMA_IF_W_N_DOWN_CH0_BASE 0x7FFC4C1000ull +#define DMA_IF_W_N_DOWN_CH0_MAX_OFFSET 0xCC00 +#define DMA_IF_W_N_DOWN_CH0_SECTION 0x1000 +#define mmDMA_IF_W_N_DOWN_CH1_BASE 0x7FFC4C2000ull +#define DMA_IF_W_N_DOWN_CH1_MAX_OFFSET 0xCC00 +#define DMA_IF_W_N_DOWN_CH1_SECTION 0x5000 +#define mmMESH_W_PLL_BASE 0x7FFC4C7000ull +#define MESH_W_PLL_MAX_OFFSET 0x5200 +#define MESH_W_PLL_SECTION 0x1000 +#define mmSRAM_W_PLL_BASE 0x7FFC4C8000ull +#define SRAM_W_PLL_MAX_OFFSET 0x5200 +#define SRAM_W_PLL_SECTION 0x1000 +#define mmDMA_IF_W_N_DOWN_BASE 0x7FFC4C9000ull +#define DMA_IF_W_N_DOWN_MAX_OFFSET 0x1500 +#define DMA_IF_W_N_DOWN_SECTION 0x7000 +#define mmSYNC_MNGR_GLBL_W_N_BASE 0x7FFC4D0000ull +#define SYNC_MNGR_GLBL_W_N_MAX_OFFSET 0x6C00 +#define SYNC_MNGR_GLBL_W_N_SECTION 0x1000 +#define mmSYNC_MNGR_OBJS_W_N_BASE 0x7FFC4D1000ull +#define SYNC_MNGR_OBJS_W_N_MAX_OFFSET 0x5C00 +#define SYNC_MNGR_OBJS_W_N_SECTION 0xF000 +#define mmDMA_IF_E_N_BASE 0x7FFC4E0000ull +#define DMA_IF_E_N_MAX_OFFSET 0x8380 +#define DMA_IF_E_N_SECTION 0x1000 +#define mmDMA_IF_E_N_DOWN_CH0_BASE 0x7FFC4E1000ull +#define DMA_IF_E_N_DOWN_CH0_MAX_OFFSET 0xCC00 +#define DMA_IF_E_N_DOWN_CH0_SECTION 0x1000 +#define mmDMA_IF_E_N_DOWN_CH1_BASE 0x7FFC4E2000ull +#define DMA_IF_E_N_DOWN_CH1_MAX_OFFSET 0xCC00 +#define DMA_IF_E_N_DOWN_CH1_SECTION 0x5000 +#define mmMESH_E_PLL_BASE 0x7FFC4E7000ull +#define MESH_E_PLL_MAX_OFFSET 0x5200 +#define MESH_E_PLL_SECTION 0x1000 +#define mmSRAM_E_PLL_BASE 0x7FFC4E8000ull +#define SRAM_E_PLL_MAX_OFFSET 0x5200 +#define SRAM_E_PLL_SECTION 0x1000 +#define mmDMA_IF_E_N_DOWN_BASE 0x7FFC4E9000ull +#define DMA_IF_E_N_DOWN_MAX_OFFSET 0x1500 +#define DMA_IF_E_N_DOWN_SECTION 0x7000 +#define mmSYNC_MNGR_GLBL_E_N_BASE 0x7FFC4F0000ull +#define SYNC_MNGR_GLBL_E_N_MAX_OFFSET 0x6C00 +#define SYNC_MNGR_GLBL_E_N_SECTION 0x1000 +#define mmSYNC_MNGR_OBJS_E_N_BASE 0x7FFC4F1000ull +#define SYNC_MNGR_OBJS_E_N_MAX_OFFSET 0x5C00 +#define SYNC_MNGR_OBJS_E_N_SECTION 0xF000 +#define mmDMA0_CORE_BASE 0x7FFC500000ull +#define DMA0_CORE_MAX_OFFSET 0x23C0 +#define DMA0_CORE_SECTION 0x8000 +#define mmDMA0_QM_BASE 0x7FFC508000ull +#define DMA0_QM_MAX_OFFSET 0xD040 +#define DMA0_QM_SECTION 0x18000 +#define mmDMA1_CORE_BASE 0x7FFC520000ull +#define DMA1_CORE_MAX_OFFSET 0x23C0 +#define DMA1_CORE_SECTION 0x8000 +#define mmDMA1_QM_BASE 0x7FFC528000ull +#define DMA1_QM_MAX_OFFSET 0xD040 +#define DMA1_QM_SECTION 0x18000 +#define mmDMA2_CORE_BASE 0x7FFC540000ull +#define DMA2_CORE_MAX_OFFSET 0x23C0 +#define DMA2_CORE_SECTION 0x8000 +#define mmDMA2_QM_BASE 0x7FFC548000ull +#define DMA2_QM_MAX_OFFSET 0xD040 +#define DMA2_QM_SECTION 0x18000 +#define mmDMA3_CORE_BASE 0x7FFC560000ull +#define DMA3_CORE_MAX_OFFSET 0x23C0 +#define DMA3_CORE_SECTION 0x8000 +#define mmDMA3_QM_BASE 0x7FFC568000ull +#define DMA3_QM_MAX_OFFSET 0xD040 +#define DMA3_QM_SECTION 0x18000 +#define mmDMA4_CORE_BASE 0x7FFC580000ull +#define DMA4_CORE_MAX_OFFSET 0x23C0 +#define DMA4_CORE_SECTION 0x8000 +#define mmDMA4_QM_BASE 0x7FFC588000ull +#define DMA4_QM_MAX_OFFSET 0xD040 +#define DMA4_QM_SECTION 0x18000 +#define mmDMA5_CORE_BASE 0x7FFC5A0000ull +#define DMA5_CORE_MAX_OFFSET 0x23C0 +#define DMA5_CORE_SECTION 0x8000 +#define mmDMA5_QM_BASE 0x7FFC5A8000ull +#define DMA5_QM_MAX_OFFSET 0xD040 +#define DMA5_QM_SECTION 0x18000 +#define mmDMA6_CORE_BASE 0x7FFC5C0000ull +#define DMA6_CORE_MAX_OFFSET 0x23C0 +#define DMA6_CORE_SECTION 0x8000 +#define mmDMA6_QM_BASE 0x7FFC5C8000ull +#define DMA6_QM_MAX_OFFSET 0xD040 +#define DMA6_QM_SECTION 0x18000 +#define mmDMA7_CORE_BASE 0x7FFC5E0000ull +#define DMA7_CORE_MAX_OFFSET 0x23C0 +#define DMA7_CORE_SECTION 0x8000 +#define mmDMA7_QM_BASE 0x7FFC5E8000ull +#define DMA7_QM_MAX_OFFSET 0xD040 +#define DMA7_QM_SECTION 0x18000 +#define mmHBM0_BASE 0x7FFC600000ull +#define HBM0_MAX_OFFSET 0x8F58 +#define HBM0_SECTION 0x80000 +#define mmHBM1_BASE 0x7FFC680000ull +#define HBM1_MAX_OFFSET 0x8F58 +#define HBM1_SECTION 0x80000 +#define mmHBM2_BASE 0x7FFC700000ull +#define HBM2_MAX_OFFSET 0x8F58 +#define HBM2_SECTION 0x80000 +#define mmHBM3_BASE 0x7FFC780000ull +#define HBM3_MAX_OFFSET 0x8F58 +#define HBM3_SECTION 0x80000 +#define mmGIC_BASE 0x7FFC800000ull +#define GIC_MAX_OFFSET 0x10000 +#define GIC_SECTION 0x401000 +#define mmPCIE_WRAP_BASE 0x7FFCC01000ull +#define PCIE_WRAP_MAX_OFFSET 0xDF00 +#define PCIE_WRAP_SECTION 0x1000 +#define mmPCIE_DBI_BASE 0x7FFCC02000ull +#define PCIE_DBI_MAX_OFFSET 0xC040 +#define PCIE_DBI_SECTION 0x2000 +#define mmPCIE_CORE_BASE 0x7FFCC04000ull +#define PCIE_CORE_MAX_OFFSET 0x9BC0 +#define PCIE_CORE_SECTION 0x3000 +#define mmPCIE_AUX_BASE 0x7FFCC07000ull +#define PCIE_AUX_MAX_OFFSET 0x9C40 +#define PCIE_AUX_SECTION 0x9000 +#define mmPCIE_PHY_BASE 0x7FFCC10000ull +#define PCIE_PHY_MAX_OFFSET 0x9640 +#define PCIE_PHY_SECTION 0x1000 +#define mmMMU_UP_BASE 0x7FFCC11000ull +#define MMU_UP_MAX_OFFSET 0x7000 +#define MMU_UP_SECTION 0x1000 +#define mmSTLB_BASE 0x7FFCC12000ull +#define STLB_MAX_OFFSET 0x8800 +#define STLB_SECTION 0x1000 +#define mmPCIE_MSI_BASE 0x7FFCC13000ull +#define PCIE_MSI_MAX_OFFSET 0x8000 +#define PCIE_MSI_SECTION 0x2D000 +#define mmPSOC_I2C_M0_BASE 0x7FFCC40000ull +#define PSOC_I2C_M0_MAX_OFFSET 0x1000 +#define PSOC_I2C_M0_SECTION 0x1000 +#define mmPSOC_I2C_M1_BASE 0x7FFCC41000ull +#define PSOC_I2C_M1_MAX_OFFSET 0x1000 +#define PSOC_I2C_M1_SECTION 0x1000 +#define mmPSOC_I2C_S_BASE 0x7FFCC42000ull +#define PSOC_I2C_S_MAX_OFFSET 0x1000 +#define PSOC_I2C_S_SECTION 0x1000 +#define mmPSOC_SPI_BASE 0x7FFCC43000ull +#define PSOC_SPI_MAX_OFFSET 0x1000 +#define PSOC_SPI_SECTION 0x2000 +#define mmPSOC_UART_0_BASE 0x7FFCC45000ull +#define PSOC_UART_0_MAX_OFFSET 0x1000 +#define PSOC_UART_0_SECTION 0x1000 +#define mmPSOC_UART_1_BASE 0x7FFCC46000ull +#define PSOC_UART_1_MAX_OFFSET 0x1000 +#define PSOC_UART_1_SECTION 0x1000 +#define mmPSOC_TIMER_BASE 0x7FFCC47000ull +#define PSOC_TIMER_MAX_OFFSET 0x1000 +#define PSOC_TIMER_SECTION 0x1000 +#define mmPSOC_WDOG_BASE 0x7FFCC48000ull +#define PSOC_WDOG_MAX_OFFSET 0x1000 +#define PSOC_WDOG_SECTION 0x1000 +#define mmPSOC_TIMESTAMP_BASE 0x7FFCC49000ull +#define PSOC_TIMESTAMP_MAX_OFFSET 0x1000 +#define PSOC_TIMESTAMP_SECTION 0x1000 +#define mmPSOC_EFUSE_BASE 0x7FFCC4A000ull +#define PSOC_EFUSE_MAX_OFFSET 0x3040 +#define PSOC_EFUSE_SECTION 0x1000 +#define mmPSOC_GLOBAL_CONF_BASE 0x7FFCC4B000ull +#define PSOC_GLOBAL_CONF_MAX_OFFSET 0xCD80 +#define PSOC_GLOBAL_CONF_SECTION 0x1000 +#define mmPSOC_GPIO0_BASE 0x7FFCC4C000ull +#define PSOC_GPIO0_MAX_OFFSET 0x1000 +#define PSOC_GPIO0_SECTION 0x1000 +#define mmPSOC_GPIO1_BASE 0x7FFCC4D000ull +#define PSOC_GPIO1_MAX_OFFSET 0x1000 +#define PSOC_GPIO1_SECTION 0x1000 +#define mmPSOC_BTL_BASE 0x7FFCC4E000ull +#define PSOC_BTL_MAX_OFFSET 0x1480 +#define PSOC_BTL_SECTION 0x1000 +#define mmPSOC_CS_TRACE_BASE 0x7FFCC4F000ull +#define PSOC_CS_TRACE_MAX_OFFSET 0x1680 +#define PSOC_CS_TRACE_SECTION 0x1000 +#define mmPSOC_GPIO2_BASE 0x7FFCC50000ull +#define PSOC_GPIO2_MAX_OFFSET 0x1000 +#define PSOC_GPIO2_SECTION 0x1000 +#define mmPSOC_GPIO3_BASE 0x7FFCC51000ull +#define PSOC_GPIO3_MAX_OFFSET 0x1000 +#define PSOC_GPIO3_SECTION 0x1000 +#define mmPSOC_GPIO4_BASE 0x7FFCC52000ull +#define PSOC_GPIO4_MAX_OFFSET 0x1000 +#define PSOC_GPIO4_SECTION 0x1000 +#define mmPSOC_DFT_EFUSE_BASE 0x7FFCC53000ull +#define PSOC_DFT_EFUSE_MAX_OFFSET 0x3040 +#define PSOC_DFT_EFUSE_SECTION 0x1000 +#define mmPSOC_RPM_0_BASE 0x7FFCC54000ull +#define PSOC_RPM_0_MAX_OFFSET 0x8800 +#define PSOC_RPM_0_SECTION 0x1000 +#define mmPSOC_RPM_1_BASE 0x7FFCC55000ull +#define PSOC_RPM_1_MAX_OFFSET 0x8800 +#define PSOC_RPM_1_SECTION 0x1000 +#define mmPSOC_RPM_2_BASE 0x7FFCC56000ull +#define PSOC_RPM_2_MAX_OFFSET 0x8800 +#define PSOC_RPM_2_SECTION 0x1000 +#define mmPSOC_RPM_3_BASE 0x7FFCC57000ull +#define PSOC_RPM_3_MAX_OFFSET 0x8800 +#define PSOC_RPM_3_SECTION 0x19000 +#define mmPSOC_CPU_PLL_BASE 0x7FFCC70000ull +#define PSOC_CPU_PLL_MAX_OFFSET 0x5200 +#define PSOC_CPU_PLL_SECTION 0x1000 +#define mmPSOC_MME_PLL_BASE 0x7FFCC71000ull +#define PSOC_MME_PLL_MAX_OFFSET 0x5200 +#define PSOC_MME_PLL_SECTION 0x1000 +#define mmPSOC_PCI_PLL_BASE 0x7FFCC72000ull +#define PSOC_PCI_PLL_MAX_OFFSET 0x5200 +#define PSOC_PCI_PLL_SECTION 0x1000 +#define mmPSOC_TPC_PLL_BASE 0x7FFCC73000ull +#define PSOC_TPC_PLL_MAX_OFFSET 0x5200 +#define PSOC_TPC_PLL_SECTION 0x1000 +#define mmPSOC_HBM_PLL_BASE 0x7FFCC74000ull +#define PSOC_HBM_PLL_MAX_OFFSET 0x5200 +#define PSOC_HBM_PLL_SECTION 0x1000 +#define mmPSOC_PM_BASE 0x7FFCC75000ull +#define PSOC_PM_MAX_OFFSET 0x1F00 +#define PSOC_PM_SECTION 0x1000 +#define mmPSOC_TS_BASE 0x7FFCC76000ull +#define PSOC_TS_MAX_OFFSET 0xE640 +#define PSOC_TS_SECTION 0x2000 +#define mmPSOC_PWM0_BASE 0x7FFCC78000ull +#define PSOC_PWM0_MAX_OFFSET 0x5800 +#define PSOC_PWM0_SECTION 0x1000 +#define mmPSOC_PWM1_BASE 0x7FFCC79000ull +#define PSOC_PWM1_MAX_OFFSET 0x5800 +#define PSOC_PWM1_SECTION 0x1000 +#define mmPSOC_PWM2_BASE 0x7FFCC7A000ull +#define PSOC_PWM2_MAX_OFFSET 0x5800 +#define PSOC_PWM2_SECTION 0x1000 +#define mmPSOC_PWM3_BASE 0x7FFCC7B000ull +#define PSOC_PWM3_MAX_OFFSET 0x5800 +#define PSOC_PWM3_SECTION 0x1000 +#define mmPSOC_GPIO5_BASE 0x7FFCC7C000ull +#define PSOC_GPIO5_MAX_OFFSET 0x1000 +#define PSOC_GPIO5_SECTION 0x1000 +#define mmPSOC_GPIO6_BASE 0x7FFCC7D000ull +#define PSOC_GPIO6_MAX_OFFSET 0x1000 +#define PSOC_GPIO6_SECTION 0x3000 +#define mmPCIE_PMA_0_BASE 0x7FFCC80000ull +#define PCIE_PMA_0_MAX_OFFSET 0x10003 +#define PCIE_PMA_0_SECTION 0x10000 +#define mmPCIE_PMA_1_BASE 0x7FFCC90000ull +#define PCIE_PMA_1_MAX_OFFSET 0x10003 +#define PCIE_PMA_1_SECTION 0x10000 +#define mmPCIE_PMA_2_BASE 0x7FFCCA0000ull +#define PCIE_PMA_2_MAX_OFFSET 0x10003 +#define PCIE_PMA_2_SECTION 0x10000 +#define mmPCIE_PMA_3_BASE 0x7FFCCB0000ull +#define PCIE_PMA_3_MAX_OFFSET 0x10003 +#define PCIE_PMA_3_SECTION 0x10000 +#define mmNIC0_MAC_CH0_BASE 0x7FFCCC0000ull +#define NIC0_MAC_CH0_MAX_OFFSET 0x8400 +#define NIC0_MAC_CH0_SECTION 0x1000 +#define mmNIC0_MAC_CH1_BASE 0x7FFCCC1000ull +#define NIC0_MAC_CH1_MAX_OFFSET 0x8400 +#define NIC0_MAC_CH1_SECTION 0x1000 +#define mmNIC0_MAC_CH2_BASE 0x7FFCCC2000ull +#define NIC0_MAC_CH2_MAX_OFFSET 0x8400 +#define NIC0_MAC_CH2_SECTION 0x1000 +#define mmNIC0_MAC_CH3_BASE 0x7FFCCC3000ull +#define NIC0_MAC_CH3_MAX_OFFSET 0x8400 +#define NIC0_MAC_CH3_SECTION 0x1000 +#define mmNIC0_STAT_BASE 0x7FFCCC4000ull +#define NIC0_STAT_MAX_OFFSET 0x4D00 +#define NIC0_STAT_SECTION 0x1000 +#define mmNIC0_MAC_XPCS91_BASE 0x7FFCCC5000ull +#define NIC0_MAC_XPCS91_MAX_OFFSET 0x2380 +#define NIC0_MAC_XPCS91_SECTION 0x3000 +#define mmNIC0_MAC_CORE_BASE 0x7FFCCC8000ull +#define NIC0_MAC_CORE_MAX_OFFSET 0x5400 +#define NIC0_MAC_CORE_SECTION 0x1000 +#define mmNIC0_MAC_AUX_BASE 0x7FFCCC9000ull +#define NIC0_MAC_AUX_MAX_OFFSET 0x3000 +#define NIC0_MAC_AUX_SECTION 0xF000 +#define mmNIC0_PHY_BASE 0x7FFCCD8000ull +#define NIC0_PHY_MAX_OFFSET 0x3400 +#define NIC0_PHY_SECTION 0x8000 +#define mmNIC0_QM0_BASE 0x7FFCCE0000ull +#define NIC0_QM0_MAX_OFFSET 0xD040 +#define NIC0_QM0_SECTION 0x2000 +#define mmNIC0_QM1_BASE 0x7FFCCE2000ull +#define NIC0_QM1_MAX_OFFSET 0xD040 +#define NIC0_QM1_SECTION 0x2000 +#define mmNIC0_QPC0_BASE 0x7FFCCE4000ull +#define NIC0_QPC0_MAX_OFFSET 0x7140 +#define NIC0_QPC0_SECTION 0x1000 +#define mmNIC0_QPC1_BASE 0x7FFCCE5000ull +#define NIC0_QPC1_MAX_OFFSET 0x7140 +#define NIC0_QPC1_SECTION 0x3000 +#define mmNIC0_RXB_BASE 0x7FFCCE8000ull +#define NIC0_RXB_MAX_OFFSET 0x6040 +#define NIC0_RXB_SECTION 0x1000 +#define mmNIC0_RXE0_BASE 0x7FFCCE9000ull +#define NIC0_RXE0_MAX_OFFSET 0x2FC0 +#define NIC0_RXE0_SECTION 0x1000 +#define mmNIC0_RXE1_BASE 0x7FFCCEA000ull +#define NIC0_RXE1_MAX_OFFSET 0x2FC0 +#define NIC0_RXE1_SECTION 0x1000 +#define mmNIC0_RX_GW_BASE 0x7FFCCEB000ull +#define NIC0_RX_GW_MAX_OFFSET 0x4540 +#define NIC0_RX_GW_SECTION 0x5000 +#define mmNIC0_TXS0_BASE 0x7FFCCF0000ull +#define NIC0_TXS0_MAX_OFFSET 0x19C0 +#define NIC0_TXS0_SECTION 0x1000 +#define mmNIC0_TXS1_BASE 0x7FFCCF1000ull +#define NIC0_TXS1_MAX_OFFSET 0x19C0 +#define NIC0_TXS1_SECTION 0x1000 +#define mmNIC0_TXE0_BASE 0x7FFCCF2000ull +#define NIC0_TXE0_MAX_OFFSET 0x2040 +#define NIC0_TXE0_SECTION 0x1000 +#define mmNIC0_TXE1_BASE 0x7FFCCF3000ull +#define NIC0_TXE1_MAX_OFFSET 0x2040 +#define NIC0_TXE1_SECTION 0x1000 +#define mmNIC0_TXB_BASE 0x7FFCCF4000ull +#define NIC0_TXB_MAX_OFFSET 0xD400 +#define NIC0_TXB_SECTION 0x1000 +#define mmNIC0_TMR_BASE 0x7FFCCF5000ull +#define NIC0_TMR_MAX_OFFSET 0x1600 +#define NIC0_TMR_SECTION 0x1000 +#define mmNIC0_TX_GW_BASE 0x7FFCCF6000ull +#define NIC0_TX_GW_MAX_OFFSET 0x1400 +#define NIC0_TX_GW_SECTION 0x2000 +#define mmNIC0_TS_BASE 0x7FFCCF8000ull +#define NIC0_TS_MAX_OFFSET 0xE640 +#define NIC0_TS_SECTION 0x1000 +#define mmNIC0_PLL_BASE 0x7FFCCF9000ull +#define NIC0_PLL_MAX_OFFSET 0x5200 +#define NIC0_PLL_SECTION 0x1000 +#define mmNIC0_PM_BASE 0x7FFCCFA000ull +#define NIC0_PM_MAX_OFFSET 0x1F00 +#define NIC0_PM_SECTION 0x6000 +#define mmNIC1_MAC_CH0_BASE 0x7FFCD00000ull +#define NIC1_MAC_CH0_MAX_OFFSET 0x8400 +#define NIC1_MAC_CH0_SECTION 0x1000 +#define mmNIC1_MAC_CH1_BASE 0x7FFCD01000ull +#define NIC1_MAC_CH1_MAX_OFFSET 0x8400 +#define NIC1_MAC_CH1_SECTION 0x1000 +#define mmNIC1_MAC_CH2_BASE 0x7FFCD02000ull +#define NIC1_MAC_CH2_MAX_OFFSET 0x8400 +#define NIC1_MAC_CH2_SECTION 0x1000 +#define mmNIC1_MAC_CH3_BASE 0x7FFCD03000ull +#define NIC1_MAC_CH3_MAX_OFFSET 0x8400 +#define NIC1_MAC_CH3_SECTION 0x1000 +#define mmNIC1_STAT_BASE 0x7FFCD04000ull +#define NIC1_STAT_MAX_OFFSET 0x4D00 +#define NIC1_STAT_SECTION 0x1000 +#define mmNIC1_MAC_XPCS91_BASE 0x7FFCD05000ull +#define NIC1_MAC_XPCS91_MAX_OFFSET 0x2380 +#define NIC1_MAC_XPCS91_SECTION 0x3000 +#define mmNIC1_MAC_CORE_BASE 0x7FFCD08000ull +#define NIC1_MAC_CORE_MAX_OFFSET 0x5400 +#define NIC1_MAC_CORE_SECTION 0x1000 +#define mmNIC1_MAC_AUX_BASE 0x7FFCD09000ull +#define NIC1_MAC_AUX_MAX_OFFSET 0x3000 +#define NIC1_MAC_AUX_SECTION 0xF000 +#define mmNIC1_PHY_BASE 0x7FFCD18000ull +#define NIC1_PHY_MAX_OFFSET 0x3400 +#define NIC1_PHY_SECTION 0x8000 +#define mmNIC1_QM0_BASE 0x7FFCD20000ull +#define NIC1_QM0_MAX_OFFSET 0xD040 +#define NIC1_QM0_SECTION 0x2000 +#define mmNIC1_QM1_BASE 0x7FFCD22000ull +#define NIC1_QM1_MAX_OFFSET 0xD040 +#define NIC1_QM1_SECTION 0x2000 +#define mmNIC1_QPC0_BASE 0x7FFCD24000ull +#define NIC1_QPC0_MAX_OFFSET 0x7140 +#define NIC1_QPC0_SECTION 0x1000 +#define mmNIC1_QPC1_BASE 0x7FFCD25000ull +#define NIC1_QPC1_MAX_OFFSET 0x7140 +#define NIC1_QPC1_SECTION 0x3000 +#define mmNIC1_RXB_BASE 0x7FFCD28000ull +#define NIC1_RXB_MAX_OFFSET 0x6040 +#define NIC1_RXB_SECTION 0x1000 +#define mmNIC1_RXE0_BASE 0x7FFCD29000ull +#define NIC1_RXE0_MAX_OFFSET 0x2FC0 +#define NIC1_RXE0_SECTION 0x1000 +#define mmNIC1_RXE1_BASE 0x7FFCD2A000ull +#define NIC1_RXE1_MAX_OFFSET 0x2FC0 +#define NIC1_RXE1_SECTION 0x1000 +#define mmNIC1_RX_GW_BASE 0x7FFCD2B000ull +#define NIC1_RX_GW_MAX_OFFSET 0x4540 +#define NIC1_RX_GW_SECTION 0x5000 +#define mmNIC1_TXS0_BASE 0x7FFCD30000ull +#define NIC1_TXS0_MAX_OFFSET 0x19C0 +#define NIC1_TXS0_SECTION 0x1000 +#define mmNIC1_TXS1_BASE 0x7FFCD31000ull +#define NIC1_TXS1_MAX_OFFSET 0x19C0 +#define NIC1_TXS1_SECTION 0x1000 +#define mmNIC1_TXE0_BASE 0x7FFCD32000ull +#define NIC1_TXE0_MAX_OFFSET 0x2040 +#define NIC1_TXE0_SECTION 0x1000 +#define mmNIC1_TXE1_BASE 0x7FFCD33000ull +#define NIC1_TXE1_MAX_OFFSET 0x2040 +#define NIC1_TXE1_SECTION 0x1000 +#define mmNIC1_TXB_BASE 0x7FFCD34000ull +#define NIC1_TXB_MAX_OFFSET 0xD400 +#define NIC1_TXB_SECTION 0x1000 +#define mmNIC1_TMR_BASE 0x7FFCD35000ull +#define NIC1_TMR_MAX_OFFSET 0x1600 +#define NIC1_TMR_SECTION 0x1000 +#define mmNIC1_TX_GW_BASE 0x7FFCD36000ull +#define NIC1_TX_GW_MAX_OFFSET 0x1400 +#define NIC1_TX_GW_SECTION 0x2000 +#define mmNIC1_TS_BASE 0x7FFCD38000ull +#define NIC1_TS_MAX_OFFSET 0xE640 +#define NIC1_TS_SECTION 0x1000 +#define mmNIC1_PLL_BASE 0x7FFCD39000ull +#define NIC1_PLL_MAX_OFFSET 0x5200 +#define NIC1_PLL_SECTION 0x1000 +#define mmNIC1_PM_BASE 0x7FFCD3A000ull +#define NIC1_PM_MAX_OFFSET 0x1F00 +#define NIC1_PM_SECTION 0x6000 +#define mmNIC2_MAC_CH0_BASE 0x7FFCD40000ull +#define NIC2_MAC_CH0_MAX_OFFSET 0x8400 +#define NIC2_MAC_CH0_SECTION 0x1000 +#define mmNIC2_MAC_CH1_BASE 0x7FFCD41000ull +#define NIC2_MAC_CH1_MAX_OFFSET 0x8400 +#define NIC2_MAC_CH1_SECTION 0x1000 +#define mmNIC2_MAC_CH2_BASE 0x7FFCD42000ull +#define NIC2_MAC_CH2_MAX_OFFSET 0x8400 +#define NIC2_MAC_CH2_SECTION 0x1000 +#define mmNIC2_MAC_CH3_BASE 0x7FFCD43000ull +#define NIC2_MAC_CH3_MAX_OFFSET 0x8400 +#define NIC2_MAC_CH3_SECTION 0x1000 +#define mmNIC2_STAT_BASE 0x7FFCD44000ull +#define NIC2_STAT_MAX_OFFSET 0x4D00 +#define NIC2_STAT_SECTION 0x1000 +#define mmNIC2_MAC_XPCS91_BASE 0x7FFCD45000ull +#define NIC2_MAC_XPCS91_MAX_OFFSET 0x2380 +#define NIC2_MAC_XPCS91_SECTION 0x3000 +#define mmNIC2_MAC_CORE_BASE 0x7FFCD48000ull +#define NIC2_MAC_CORE_MAX_OFFSET 0x5400 +#define NIC2_MAC_CORE_SECTION 0x1000 +#define mmNIC2_MAC_AUX_BASE 0x7FFCD49000ull +#define NIC2_MAC_AUX_MAX_OFFSET 0x3000 +#define NIC2_MAC_AUX_SECTION 0xF000 +#define mmNIC2_PHY_BASE 0x7FFCD58000ull +#define NIC2_PHY_MAX_OFFSET 0x3400 +#define NIC2_PHY_SECTION 0x8000 +#define mmNIC2_QM0_BASE 0x7FFCD60000ull +#define NIC2_QM0_MAX_OFFSET 0xD040 +#define NIC2_QM0_SECTION 0x2000 +#define mmNIC2_QM1_BASE 0x7FFCD62000ull +#define NIC2_QM1_MAX_OFFSET 0xD040 +#define NIC2_QM1_SECTION 0x2000 +#define mmNIC2_QPC0_BASE 0x7FFCD64000ull +#define NIC2_QPC0_MAX_OFFSET 0x7140 +#define NIC2_QPC0_SECTION 0x1000 +#define mmNIC2_QPC1_BASE 0x7FFCD65000ull +#define NIC2_QPC1_MAX_OFFSET 0x7140 +#define NIC2_QPC1_SECTION 0x3000 +#define mmNIC2_RXB_BASE 0x7FFCD68000ull +#define NIC2_RXB_MAX_OFFSET 0x6040 +#define NIC2_RXB_SECTION 0x1000 +#define mmNIC2_RXE0_BASE 0x7FFCD69000ull +#define NIC2_RXE0_MAX_OFFSET 0x2FC0 +#define NIC2_RXE0_SECTION 0x1000 +#define mmNIC2_RXE1_BASE 0x7FFCD6A000ull +#define NIC2_RXE1_MAX_OFFSET 0x2FC0 +#define NIC2_RXE1_SECTION 0x1000 +#define mmNIC2_RX_GW_BASE 0x7FFCD6B000ull +#define NIC2_RX_GW_MAX_OFFSET 0x4540 +#define NIC2_RX_GW_SECTION 0x5000 +#define mmNIC2_TXS0_BASE 0x7FFCD70000ull +#define NIC2_TXS0_MAX_OFFSET 0x19C0 +#define NIC2_TXS0_SECTION 0x1000 +#define mmNIC2_TXS1_BASE 0x7FFCD71000ull +#define NIC2_TXS1_MAX_OFFSET 0x19C0 +#define NIC2_TXS1_SECTION 0x1000 +#define mmNIC2_TXE0_BASE 0x7FFCD72000ull +#define NIC2_TXE0_MAX_OFFSET 0x2040 +#define NIC2_TXE0_SECTION 0x1000 +#define mmNIC2_TXE1_BASE 0x7FFCD73000ull +#define NIC2_TXE1_MAX_OFFSET 0x2040 +#define NIC2_TXE1_SECTION 0x1000 +#define mmNIC2_TXB_BASE 0x7FFCD74000ull +#define NIC2_TXB_MAX_OFFSET 0xD400 +#define NIC2_TXB_SECTION 0x1000 +#define mmNIC2_TMR_BASE 0x7FFCD75000ull +#define NIC2_TMR_MAX_OFFSET 0x1600 +#define NIC2_TMR_SECTION 0x1000 +#define mmNIC2_TX_GW_BASE 0x7FFCD76000ull +#define NIC2_TX_GW_MAX_OFFSET 0x1400 +#define NIC2_TX_GW_SECTION 0x2000 +#define mmNIC2_HBM_PLL_BASE 0x7FFCD78000ull +#define NIC2_HBM_PLL_MAX_OFFSET 0x5200 +#define NIC2_HBM_PLL_SECTION 0x1000 +#define mmNIC2_MME_PLL_BASE 0x7FFCD79000ull +#define NIC2_MME_PLL_MAX_OFFSET 0x5200 +#define NIC2_MME_PLL_SECTION 0x1000 +#define mmNIC2_TPC_PLL_BASE 0x7FFCD7A000ull +#define NIC2_TPC_PLL_MAX_OFFSET 0x5200 +#define NIC2_TPC_PLL_SECTION 0x6000 +#define mmNIC3_MAC_CH0_BASE 0x7FFCD80000ull +#define NIC3_MAC_CH0_MAX_OFFSET 0x8400 +#define NIC3_MAC_CH0_SECTION 0x1000 +#define mmNIC3_MAC_CH1_BASE 0x7FFCD81000ull +#define NIC3_MAC_CH1_MAX_OFFSET 0x8400 +#define NIC3_MAC_CH1_SECTION 0x1000 +#define mmNIC3_MAC_CH2_BASE 0x7FFCD82000ull +#define NIC3_MAC_CH2_MAX_OFFSET 0x8400 +#define NIC3_MAC_CH2_SECTION 0x1000 +#define mmNIC3_MAC_CH3_BASE 0x7FFCD83000ull +#define NIC3_MAC_CH3_MAX_OFFSET 0x8400 +#define NIC3_MAC_CH3_SECTION 0x1000 +#define mmNIC3_STAT_BASE 0x7FFCD84000ull +#define NIC3_STAT_MAX_OFFSET 0x4D00 +#define NIC3_STAT_SECTION 0x1000 +#define mmNIC3_MAC_XPCS91_BASE 0x7FFCD85000ull +#define NIC3_MAC_XPCS91_MAX_OFFSET 0x2380 +#define NIC3_MAC_XPCS91_SECTION 0x3000 +#define mmNIC3_MAC_CORE_BASE 0x7FFCD88000ull +#define NIC3_MAC_CORE_MAX_OFFSET 0x5400 +#define NIC3_MAC_CORE_SECTION 0x1000 +#define mmNIC3_MAC_AUX_BASE 0x7FFCD89000ull +#define NIC3_MAC_AUX_MAX_OFFSET 0x3000 +#define NIC3_MAC_AUX_SECTION 0xF000 +#define mmNIC3_PHY_BASE 0x7FFCD98000ull +#define NIC3_PHY_MAX_OFFSET 0x3400 +#define NIC3_PHY_SECTION 0x8000 +#define mmNIC3_QM0_BASE 0x7FFCDA0000ull +#define NIC3_QM0_MAX_OFFSET 0xD040 +#define NIC3_QM0_SECTION 0x2000 +#define mmNIC3_QM1_BASE 0x7FFCDA2000ull +#define NIC3_QM1_MAX_OFFSET 0xD040 +#define NIC3_QM1_SECTION 0x2000 +#define mmNIC3_QPC0_BASE 0x7FFCDA4000ull +#define NIC3_QPC0_MAX_OFFSET 0x7140 +#define NIC3_QPC0_SECTION 0x1000 +#define mmNIC3_QPC1_BASE 0x7FFCDA5000ull +#define NIC3_QPC1_MAX_OFFSET 0x7140 +#define NIC3_QPC1_SECTION 0x3000 +#define mmNIC3_RXB_BASE 0x7FFCDA8000ull +#define NIC3_RXB_MAX_OFFSET 0x6040 +#define NIC3_RXB_SECTION 0x1000 +#define mmNIC3_RXE0_BASE 0x7FFCDA9000ull +#define NIC3_RXE0_MAX_OFFSET 0x2FC0 +#define NIC3_RXE0_SECTION 0x1000 +#define mmNIC3_RXE1_BASE 0x7FFCDAA000ull +#define NIC3_RXE1_MAX_OFFSET 0x2FC0 +#define NIC3_RXE1_SECTION 0x1000 +#define mmNIC3_RX_GW_BASE 0x7FFCDAB000ull +#define NIC3_RX_GW_MAX_OFFSET 0x4540 +#define NIC3_RX_GW_SECTION 0x5000 +#define mmNIC3_TXS0_BASE 0x7FFCDB0000ull +#define NIC3_TXS0_MAX_OFFSET 0x19C0 +#define NIC3_TXS0_SECTION 0x1000 +#define mmNIC3_TXS1_BASE 0x7FFCDB1000ull +#define NIC3_TXS1_MAX_OFFSET 0x19C0 +#define NIC3_TXS1_SECTION 0x1000 +#define mmNIC3_TXE0_BASE 0x7FFCDB2000ull +#define NIC3_TXE0_MAX_OFFSET 0x2040 +#define NIC3_TXE0_SECTION 0x1000 +#define mmNIC3_TXE1_BASE 0x7FFCDB3000ull +#define NIC3_TXE1_MAX_OFFSET 0x2040 +#define NIC3_TXE1_SECTION 0x1000 +#define mmNIC3_TXB_BASE 0x7FFCDB4000ull +#define NIC3_TXB_MAX_OFFSET 0xD400 +#define NIC3_TXB_SECTION 0x1000 +#define mmNIC3_TMR_BASE 0x7FFCDB5000ull +#define NIC3_TMR_MAX_OFFSET 0x1600 +#define NIC3_TMR_SECTION 0x1000 +#define mmNIC3_TX_GW_BASE 0x7FFCDB6000ull +#define NIC3_TX_GW_MAX_OFFSET 0x1400 +#define NIC3_TX_GW_SECTION 0x2000 +#define mmNIC3_TS_BASE 0x7FFCDB8000ull +#define NIC3_TS_MAX_OFFSET 0xE640 +#define NIC3_TS_SECTION 0x2000 +#define mmNIC3_PM_BASE 0x7FFCDBA000ull +#define NIC3_PM_MAX_OFFSET 0x1F00 +#define NIC3_PM_SECTION 0x6000 +#define mmNIC4_MAC_CH0_BASE 0x7FFCDC0000ull +#define NIC4_MAC_CH0_MAX_OFFSET 0x8400 +#define NIC4_MAC_CH0_SECTION 0x1000 +#define mmNIC4_MAC_CH1_BASE 0x7FFCDC1000ull +#define NIC4_MAC_CH1_MAX_OFFSET 0x8400 +#define NIC4_MAC_CH1_SECTION 0x1000 +#define mmNIC4_MAC_CH2_BASE 0x7FFCDC2000ull +#define NIC4_MAC_CH2_MAX_OFFSET 0x8400 +#define NIC4_MAC_CH2_SECTION 0x1000 +#define mmNIC4_MAC_CH3_BASE 0x7FFCDC3000ull +#define NIC4_MAC_CH3_MAX_OFFSET 0x8400 +#define NIC4_MAC_CH3_SECTION 0x1000 +#define mmNIC4_STAT_BASE 0x7FFCDC4000ull +#define NIC4_STAT_MAX_OFFSET 0x4D00 +#define NIC4_STAT_SECTION 0x1000 +#define mmNIC4_MAC_XPCS91_BASE 0x7FFCDC5000ull +#define NIC4_MAC_XPCS91_MAX_OFFSET 0x2380 +#define NIC4_MAC_XPCS91_SECTION 0x3000 +#define mmNIC4_MAC_CORE_BASE 0x7FFCDC8000ull +#define NIC4_MAC_CORE_MAX_OFFSET 0x5400 +#define NIC4_MAC_CORE_SECTION 0x1000 +#define mmNIC4_MAC_AUX_BASE 0x7FFCDC9000ull +#define NIC4_MAC_AUX_MAX_OFFSET 0x3000 +#define NIC4_MAC_AUX_SECTION 0xF000 +#define mmNIC4_PHY_BASE 0x7FFCDD8000ull +#define NIC4_PHY_MAX_OFFSET 0x3400 +#define NIC4_PHY_SECTION 0x8000 +#define mmNIC4_QM0_BASE 0x7FFCDE0000ull +#define NIC4_QM0_MAX_OFFSET 0xD040 +#define NIC4_QM0_SECTION 0x2000 +#define mmNIC4_QM1_BASE 0x7FFCDE2000ull +#define NIC4_QM1_MAX_OFFSET 0xD040 +#define NIC4_QM1_SECTION 0x2000 +#define mmNIC4_QPC0_BASE 0x7FFCDE4000ull +#define NIC4_QPC0_MAX_OFFSET 0x7140 +#define NIC4_QPC0_SECTION 0x1000 +#define mmNIC4_QPC1_BASE 0x7FFCDE5000ull +#define NIC4_QPC1_MAX_OFFSET 0x7140 +#define NIC4_QPC1_SECTION 0x3000 +#define mmNIC4_RXB_BASE 0x7FFCDE8000ull +#define NIC4_RXB_MAX_OFFSET 0x6040 +#define NIC4_RXB_SECTION 0x1000 +#define mmNIC4_RXE0_BASE 0x7FFCDE9000ull +#define NIC4_RXE0_MAX_OFFSET 0x2FC0 +#define NIC4_RXE0_SECTION 0x1000 +#define mmNIC4_RXE1_BASE 0x7FFCDEA000ull +#define NIC4_RXE1_MAX_OFFSET 0x2FC0 +#define NIC4_RXE1_SECTION 0x1000 +#define mmNIC4_RX_GW_BASE 0x7FFCDEB000ull +#define NIC4_RX_GW_MAX_OFFSET 0x4540 +#define NIC4_RX_GW_SECTION 0x5000 +#define mmNIC4_TXS0_BASE 0x7FFCDF0000ull +#define NIC4_TXS0_MAX_OFFSET 0x19C0 +#define NIC4_TXS0_SECTION 0x1000 +#define mmNIC4_TXS1_BASE 0x7FFCDF1000ull +#define NIC4_TXS1_MAX_OFFSET 0x19C0 +#define NIC4_TXS1_SECTION 0x1000 +#define mmNIC4_TXE0_BASE 0x7FFCDF2000ull +#define NIC4_TXE0_MAX_OFFSET 0x2040 +#define NIC4_TXE0_SECTION 0x1000 +#define mmNIC4_TXE1_BASE 0x7FFCDF3000ull +#define NIC4_TXE1_MAX_OFFSET 0x2040 +#define NIC4_TXE1_SECTION 0x1000 +#define mmNIC4_TXB_BASE 0x7FFCDF4000ull +#define NIC4_TXB_MAX_OFFSET 0xD400 +#define NIC4_TXB_SECTION 0x1000 +#define mmNIC4_TMR_BASE 0x7FFCDF5000ull +#define NIC4_TMR_MAX_OFFSET 0x1600 +#define NIC4_TMR_SECTION 0x1000 +#define mmNIC4_TX_GW_BASE 0x7FFCDF6000ull +#define NIC4_TX_GW_MAX_OFFSET 0x1400 +#define NIC4_TX_GW_SECTION 0x10000 +#define mmTPC0_CFG_BASE 0x7FFCE06000ull +#define TPC0_CFG_MAX_OFFSET 0xE400 +#define TPC0_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC0_CFG_BASE 0x7FFCE06400ull +#define KERNEL_TENSOR_0_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC0_CFG_BASE 0x7FFCE06438ull +#define KERNEL_TENSOR_1_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC0_CFG_BASE 0x7FFCE06470ull +#define KERNEL_TENSOR_2_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC0_CFG_BASE 0x7FFCE064A8ull +#define KERNEL_TENSOR_3_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC0_CFG_BASE 0x7FFCE064E0ull +#define KERNEL_TENSOR_4_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC0_CFG_BASE 0x7FFCE06518ull +#define KERNEL_TENSOR_5_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC0_CFG_BASE 0x7FFCE06550ull +#define KERNEL_TENSOR_6_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC0_CFG_BASE 0x7FFCE06588ull +#define KERNEL_TENSOR_7_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC0_CFG_BASE 0x7FFCE065C0ull +#define KERNEL_TENSOR_8_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC0_CFG_BASE 0x7FFCE065F8ull +#define KERNEL_TENSOR_9_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC0_CFG_BASE 0x7FFCE06630ull +#define KERNEL_TENSOR_10_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC0_CFG_BASE 0x7FFCE06668ull +#define KERNEL_TENSOR_11_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC0_CFG_BASE 0x7FFCE066A0ull +#define KERNEL_TENSOR_12_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC0_CFG_BASE 0x7FFCE066D8ull +#define KERNEL_TENSOR_13_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC0_CFG_BASE 0x7FFCE06710ull +#define KERNEL_TENSOR_14_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC0_CFG_BASE 0x7FFCE06748ull +#define KERNEL_TENSOR_15_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC0_CFG_BASE 0x7FFCE06780ull +#define KERNEL_SYNC_OBJECT_TPC0_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC0_CFG_SECTION 0x8000 +#define mmKERNEL_TPC0_CFG_BASE 0x7FFCE06788ull +#define KERNEL_TPC0_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC0_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC0_CFG_BASE 0x7FFCE06A00ull +#define QM_TENSOR_0_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC0_CFG_BASE 0x7FFCE06A38ull +#define QM_TENSOR_1_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC0_CFG_BASE 0x7FFCE06A70ull +#define QM_TENSOR_2_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC0_CFG_BASE 0x7FFCE06AA8ull +#define QM_TENSOR_3_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC0_CFG_BASE 0x7FFCE06AE0ull +#define QM_TENSOR_4_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC0_CFG_BASE 0x7FFCE06B18ull +#define QM_TENSOR_5_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC0_CFG_BASE 0x7FFCE06B50ull +#define QM_TENSOR_6_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC0_CFG_BASE 0x7FFCE06B88ull +#define QM_TENSOR_7_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC0_CFG_BASE 0x7FFCE06BC0ull +#define QM_TENSOR_8_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC0_CFG_BASE 0x7FFCE06BF8ull +#define QM_TENSOR_9_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC0_CFG_BASE 0x7FFCE06C30ull +#define QM_TENSOR_10_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC0_CFG_BASE 0x7FFCE06C68ull +#define QM_TENSOR_11_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC0_CFG_BASE 0x7FFCE06CA0ull +#define QM_TENSOR_12_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC0_CFG_BASE 0x7FFCE06CD8ull +#define QM_TENSOR_13_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC0_CFG_BASE 0x7FFCE06D10ull +#define QM_TENSOR_14_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC0_CFG_BASE 0x7FFCE06D48ull +#define QM_TENSOR_15_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC0_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC0_CFG_BASE 0x7FFCE06D80ull +#define QM_SYNC_OBJECT_TPC0_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC0_CFG_SECTION 0x8000 +#define mmQM_TPC0_CFG_BASE 0x7FFCE06D88ull +#define QM_TPC0_CFG_MAX_OFFSET 0xB800 +#define QM_TPC0_CFG_SECTION 0x2780 +#define mmTPC0_E2E_CRED_BASE 0x7FFCE07000ull +#define TPC0_E2E_CRED_MAX_OFFSET 0x1680 +#define TPC0_E2E_CRED_SECTION 0x1000 +#define mmTPC0_QM_BASE 0x7FFCE08000ull +#define TPC0_QM_MAX_OFFSET 0xD040 +#define TPC0_QM_SECTION 0x3E000 +#define mmTPC1_CFG_BASE 0x7FFCE46000ull +#define TPC1_CFG_MAX_OFFSET 0xE400 +#define TPC1_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC1_CFG_BASE 0x7FFCE46400ull +#define KERNEL_TENSOR_0_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC1_CFG_BASE 0x7FFCE46438ull +#define KERNEL_TENSOR_1_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC1_CFG_BASE 0x7FFCE46470ull +#define KERNEL_TENSOR_2_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC1_CFG_BASE 0x7FFCE464A8ull +#define KERNEL_TENSOR_3_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC1_CFG_BASE 0x7FFCE464E0ull +#define KERNEL_TENSOR_4_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC1_CFG_BASE 0x7FFCE46518ull +#define KERNEL_TENSOR_5_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC1_CFG_BASE 0x7FFCE46550ull +#define KERNEL_TENSOR_6_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC1_CFG_BASE 0x7FFCE46588ull +#define KERNEL_TENSOR_7_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC1_CFG_BASE 0x7FFCE465C0ull +#define KERNEL_TENSOR_8_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC1_CFG_BASE 0x7FFCE465F8ull +#define KERNEL_TENSOR_9_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC1_CFG_BASE 0x7FFCE46630ull +#define KERNEL_TENSOR_10_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC1_CFG_BASE 0x7FFCE46668ull +#define KERNEL_TENSOR_11_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC1_CFG_BASE 0x7FFCE466A0ull +#define KERNEL_TENSOR_12_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC1_CFG_BASE 0x7FFCE466D8ull +#define KERNEL_TENSOR_13_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC1_CFG_BASE 0x7FFCE46710ull +#define KERNEL_TENSOR_14_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC1_CFG_BASE 0x7FFCE46748ull +#define KERNEL_TENSOR_15_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC1_CFG_BASE 0x7FFCE46780ull +#define KERNEL_SYNC_OBJECT_TPC1_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC1_CFG_SECTION 0x8000 +#define mmKERNEL_TPC1_CFG_BASE 0x7FFCE46788ull +#define KERNEL_TPC1_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC1_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC1_CFG_BASE 0x7FFCE46A00ull +#define QM_TENSOR_0_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC1_CFG_BASE 0x7FFCE46A38ull +#define QM_TENSOR_1_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC1_CFG_BASE 0x7FFCE46A70ull +#define QM_TENSOR_2_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC1_CFG_BASE 0x7FFCE46AA8ull +#define QM_TENSOR_3_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC1_CFG_BASE 0x7FFCE46AE0ull +#define QM_TENSOR_4_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC1_CFG_BASE 0x7FFCE46B18ull +#define QM_TENSOR_5_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC1_CFG_BASE 0x7FFCE46B50ull +#define QM_TENSOR_6_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC1_CFG_BASE 0x7FFCE46B88ull +#define QM_TENSOR_7_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC1_CFG_BASE 0x7FFCE46BC0ull +#define QM_TENSOR_8_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC1_CFG_BASE 0x7FFCE46BF8ull +#define QM_TENSOR_9_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC1_CFG_BASE 0x7FFCE46C30ull +#define QM_TENSOR_10_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC1_CFG_BASE 0x7FFCE46C68ull +#define QM_TENSOR_11_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC1_CFG_BASE 0x7FFCE46CA0ull +#define QM_TENSOR_12_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC1_CFG_BASE 0x7FFCE46CD8ull +#define QM_TENSOR_13_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC1_CFG_BASE 0x7FFCE46D10ull +#define QM_TENSOR_14_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC1_CFG_BASE 0x7FFCE46D48ull +#define QM_TENSOR_15_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC1_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC1_CFG_BASE 0x7FFCE46D80ull +#define QM_SYNC_OBJECT_TPC1_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC1_CFG_SECTION 0x8000 +#define mmQM_TPC1_CFG_BASE 0x7FFCE46D88ull +#define QM_TPC1_CFG_MAX_OFFSET 0xB800 +#define QM_TPC1_CFG_SECTION 0x2780 +#define mmTPC1_E2E_CRED_BASE 0x7FFCE47000ull +#define TPC1_E2E_CRED_MAX_OFFSET 0x1680 +#define TPC1_E2E_CRED_SECTION 0x1000 +#define mmTPC1_QM_BASE 0x7FFCE48000ull +#define TPC1_QM_MAX_OFFSET 0xD040 +#define TPC1_QM_SECTION 0x3E000 +#define mmTPC2_CFG_BASE 0x7FFCE86000ull +#define TPC2_CFG_MAX_OFFSET 0xE400 +#define TPC2_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC2_CFG_BASE 0x7FFCE86400ull +#define KERNEL_TENSOR_0_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC2_CFG_BASE 0x7FFCE86438ull +#define KERNEL_TENSOR_1_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC2_CFG_BASE 0x7FFCE86470ull +#define KERNEL_TENSOR_2_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC2_CFG_BASE 0x7FFCE864A8ull +#define KERNEL_TENSOR_3_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC2_CFG_BASE 0x7FFCE864E0ull +#define KERNEL_TENSOR_4_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC2_CFG_BASE 0x7FFCE86518ull +#define KERNEL_TENSOR_5_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC2_CFG_BASE 0x7FFCE86550ull +#define KERNEL_TENSOR_6_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC2_CFG_BASE 0x7FFCE86588ull +#define KERNEL_TENSOR_7_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC2_CFG_BASE 0x7FFCE865C0ull +#define KERNEL_TENSOR_8_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC2_CFG_BASE 0x7FFCE865F8ull +#define KERNEL_TENSOR_9_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC2_CFG_BASE 0x7FFCE86630ull +#define KERNEL_TENSOR_10_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC2_CFG_BASE 0x7FFCE86668ull +#define KERNEL_TENSOR_11_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC2_CFG_BASE 0x7FFCE866A0ull +#define KERNEL_TENSOR_12_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC2_CFG_BASE 0x7FFCE866D8ull +#define KERNEL_TENSOR_13_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC2_CFG_BASE 0x7FFCE86710ull +#define KERNEL_TENSOR_14_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC2_CFG_BASE 0x7FFCE86748ull +#define KERNEL_TENSOR_15_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC2_CFG_BASE 0x7FFCE86780ull +#define KERNEL_SYNC_OBJECT_TPC2_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC2_CFG_SECTION 0x8000 +#define mmKERNEL_TPC2_CFG_BASE 0x7FFCE86788ull +#define KERNEL_TPC2_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC2_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC2_CFG_BASE 0x7FFCE86A00ull +#define QM_TENSOR_0_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC2_CFG_BASE 0x7FFCE86A38ull +#define QM_TENSOR_1_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC2_CFG_BASE 0x7FFCE86A70ull +#define QM_TENSOR_2_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC2_CFG_BASE 0x7FFCE86AA8ull +#define QM_TENSOR_3_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC2_CFG_BASE 0x7FFCE86AE0ull +#define QM_TENSOR_4_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC2_CFG_BASE 0x7FFCE86B18ull +#define QM_TENSOR_5_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC2_CFG_BASE 0x7FFCE86B50ull +#define QM_TENSOR_6_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC2_CFG_BASE 0x7FFCE86B88ull +#define QM_TENSOR_7_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC2_CFG_BASE 0x7FFCE86BC0ull +#define QM_TENSOR_8_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC2_CFG_BASE 0x7FFCE86BF8ull +#define QM_TENSOR_9_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC2_CFG_BASE 0x7FFCE86C30ull +#define QM_TENSOR_10_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC2_CFG_BASE 0x7FFCE86C68ull +#define QM_TENSOR_11_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC2_CFG_BASE 0x7FFCE86CA0ull +#define QM_TENSOR_12_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC2_CFG_BASE 0x7FFCE86CD8ull +#define QM_TENSOR_13_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC2_CFG_BASE 0x7FFCE86D10ull +#define QM_TENSOR_14_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC2_CFG_BASE 0x7FFCE86D48ull +#define QM_TENSOR_15_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC2_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC2_CFG_BASE 0x7FFCE86D80ull +#define QM_SYNC_OBJECT_TPC2_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC2_CFG_SECTION 0x8000 +#define mmQM_TPC2_CFG_BASE 0x7FFCE86D88ull +#define QM_TPC2_CFG_MAX_OFFSET 0xB800 +#define QM_TPC2_CFG_SECTION 0x2780 +#define mmTPC2_E2E_CRED_BASE 0x7FFCE87000ull +#define TPC2_E2E_CRED_MAX_OFFSET 0x1680 +#define TPC2_E2E_CRED_SECTION 0x1000 +#define mmTPC2_QM_BASE 0x7FFCE88000ull +#define TPC2_QM_MAX_OFFSET 0xD040 +#define TPC2_QM_SECTION 0x3E000 +#define mmTPC3_CFG_BASE 0x7FFCEC6000ull +#define TPC3_CFG_MAX_OFFSET 0xE400 +#define TPC3_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC3_CFG_BASE 0x7FFCEC6400ull +#define KERNEL_TENSOR_0_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC3_CFG_BASE 0x7FFCEC6438ull +#define KERNEL_TENSOR_1_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC3_CFG_BASE 0x7FFCEC6470ull +#define KERNEL_TENSOR_2_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC3_CFG_BASE 0x7FFCEC64A8ull +#define KERNEL_TENSOR_3_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC3_CFG_BASE 0x7FFCEC64E0ull +#define KERNEL_TENSOR_4_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC3_CFG_BASE 0x7FFCEC6518ull +#define KERNEL_TENSOR_5_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC3_CFG_BASE 0x7FFCEC6550ull +#define KERNEL_TENSOR_6_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC3_CFG_BASE 0x7FFCEC6588ull +#define KERNEL_TENSOR_7_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC3_CFG_BASE 0x7FFCEC65C0ull +#define KERNEL_TENSOR_8_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC3_CFG_BASE 0x7FFCEC65F8ull +#define KERNEL_TENSOR_9_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC3_CFG_BASE 0x7FFCEC6630ull +#define KERNEL_TENSOR_10_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC3_CFG_BASE 0x7FFCEC6668ull +#define KERNEL_TENSOR_11_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC3_CFG_BASE 0x7FFCEC66A0ull +#define KERNEL_TENSOR_12_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC3_CFG_BASE 0x7FFCEC66D8ull +#define KERNEL_TENSOR_13_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC3_CFG_BASE 0x7FFCEC6710ull +#define KERNEL_TENSOR_14_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC3_CFG_BASE 0x7FFCEC6748ull +#define KERNEL_TENSOR_15_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC3_CFG_BASE 0x7FFCEC6780ull +#define KERNEL_SYNC_OBJECT_TPC3_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC3_CFG_SECTION 0x8000 +#define mmKERNEL_TPC3_CFG_BASE 0x7FFCEC6788ull +#define KERNEL_TPC3_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC3_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC3_CFG_BASE 0x7FFCEC6A00ull +#define QM_TENSOR_0_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC3_CFG_BASE 0x7FFCEC6A38ull +#define QM_TENSOR_1_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC3_CFG_BASE 0x7FFCEC6A70ull +#define QM_TENSOR_2_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC3_CFG_BASE 0x7FFCEC6AA8ull +#define QM_TENSOR_3_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC3_CFG_BASE 0x7FFCEC6AE0ull +#define QM_TENSOR_4_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC3_CFG_BASE 0x7FFCEC6B18ull +#define QM_TENSOR_5_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC3_CFG_BASE 0x7FFCEC6B50ull +#define QM_TENSOR_6_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC3_CFG_BASE 0x7FFCEC6B88ull +#define QM_TENSOR_7_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC3_CFG_BASE 0x7FFCEC6BC0ull +#define QM_TENSOR_8_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC3_CFG_BASE 0x7FFCEC6BF8ull +#define QM_TENSOR_9_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC3_CFG_BASE 0x7FFCEC6C30ull +#define QM_TENSOR_10_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC3_CFG_BASE 0x7FFCEC6C68ull +#define QM_TENSOR_11_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC3_CFG_BASE 0x7FFCEC6CA0ull +#define QM_TENSOR_12_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC3_CFG_BASE 0x7FFCEC6CD8ull +#define QM_TENSOR_13_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC3_CFG_BASE 0x7FFCEC6D10ull +#define QM_TENSOR_14_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC3_CFG_BASE 0x7FFCEC6D48ull +#define QM_TENSOR_15_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC3_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC3_CFG_BASE 0x7FFCEC6D80ull +#define QM_SYNC_OBJECT_TPC3_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC3_CFG_SECTION 0x8000 +#define mmQM_TPC3_CFG_BASE 0x7FFCEC6D88ull +#define QM_TPC3_CFG_MAX_OFFSET 0xB800 +#define QM_TPC3_CFG_SECTION 0x2780 +#define mmTPC3_E2E_CRED_BASE 0x7FFCEC7000ull +#define TPC3_E2E_CRED_MAX_OFFSET 0x1680 +#define TPC3_E2E_CRED_SECTION 0x1000 +#define mmTPC3_QM_BASE 0x7FFCEC8000ull +#define TPC3_QM_MAX_OFFSET 0xD040 +#define TPC3_QM_SECTION 0x3E000 +#define mmTPC4_CFG_BASE 0x7FFCF06000ull +#define TPC4_CFG_MAX_OFFSET 0xE400 +#define TPC4_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC4_CFG_BASE 0x7FFCF06400ull +#define KERNEL_TENSOR_0_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC4_CFG_BASE 0x7FFCF06438ull +#define KERNEL_TENSOR_1_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC4_CFG_BASE 0x7FFCF06470ull +#define KERNEL_TENSOR_2_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC4_CFG_BASE 0x7FFCF064A8ull +#define KERNEL_TENSOR_3_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC4_CFG_BASE 0x7FFCF064E0ull +#define KERNEL_TENSOR_4_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC4_CFG_BASE 0x7FFCF06518ull +#define KERNEL_TENSOR_5_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC4_CFG_BASE 0x7FFCF06550ull +#define KERNEL_TENSOR_6_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC4_CFG_BASE 0x7FFCF06588ull +#define KERNEL_TENSOR_7_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC4_CFG_BASE 0x7FFCF065C0ull +#define KERNEL_TENSOR_8_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC4_CFG_BASE 0x7FFCF065F8ull +#define KERNEL_TENSOR_9_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC4_CFG_BASE 0x7FFCF06630ull +#define KERNEL_TENSOR_10_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC4_CFG_BASE 0x7FFCF06668ull +#define KERNEL_TENSOR_11_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC4_CFG_BASE 0x7FFCF066A0ull +#define KERNEL_TENSOR_12_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC4_CFG_BASE 0x7FFCF066D8ull +#define KERNEL_TENSOR_13_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC4_CFG_BASE 0x7FFCF06710ull +#define KERNEL_TENSOR_14_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC4_CFG_BASE 0x7FFCF06748ull +#define KERNEL_TENSOR_15_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC4_CFG_BASE 0x7FFCF06780ull +#define KERNEL_SYNC_OBJECT_TPC4_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC4_CFG_SECTION 0x8000 +#define mmKERNEL_TPC4_CFG_BASE 0x7FFCF06788ull +#define KERNEL_TPC4_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC4_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC4_CFG_BASE 0x7FFCF06A00ull +#define QM_TENSOR_0_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC4_CFG_BASE 0x7FFCF06A38ull +#define QM_TENSOR_1_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC4_CFG_BASE 0x7FFCF06A70ull +#define QM_TENSOR_2_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC4_CFG_BASE 0x7FFCF06AA8ull +#define QM_TENSOR_3_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC4_CFG_BASE 0x7FFCF06AE0ull +#define QM_TENSOR_4_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC4_CFG_BASE 0x7FFCF06B18ull +#define QM_TENSOR_5_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC4_CFG_BASE 0x7FFCF06B50ull +#define QM_TENSOR_6_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC4_CFG_BASE 0x7FFCF06B88ull +#define QM_TENSOR_7_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC4_CFG_BASE 0x7FFCF06BC0ull +#define QM_TENSOR_8_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC4_CFG_BASE 0x7FFCF06BF8ull +#define QM_TENSOR_9_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC4_CFG_BASE 0x7FFCF06C30ull +#define QM_TENSOR_10_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC4_CFG_BASE 0x7FFCF06C68ull +#define QM_TENSOR_11_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC4_CFG_BASE 0x7FFCF06CA0ull +#define QM_TENSOR_12_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC4_CFG_BASE 0x7FFCF06CD8ull +#define QM_TENSOR_13_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC4_CFG_BASE 0x7FFCF06D10ull +#define QM_TENSOR_14_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC4_CFG_BASE 0x7FFCF06D48ull +#define QM_TENSOR_15_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC4_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC4_CFG_BASE 0x7FFCF06D80ull +#define QM_SYNC_OBJECT_TPC4_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC4_CFG_SECTION 0x8000 +#define mmQM_TPC4_CFG_BASE 0x7FFCF06D88ull +#define QM_TPC4_CFG_MAX_OFFSET 0xB800 +#define QM_TPC4_CFG_SECTION 0x2780 +#define mmTPC4_E2E_CRED_BASE 0x7FFCF07000ull +#define TPC4_E2E_CRED_MAX_OFFSET 0x1680 +#define TPC4_E2E_CRED_SECTION 0x1000 +#define mmTPC4_QM_BASE 0x7FFCF08000ull +#define TPC4_QM_MAX_OFFSET 0xD040 +#define TPC4_QM_SECTION 0x3E000 +#define mmTPC5_CFG_BASE 0x7FFCF46000ull +#define TPC5_CFG_MAX_OFFSET 0xE400 +#define TPC5_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC5_CFG_BASE 0x7FFCF46400ull +#define KERNEL_TENSOR_0_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC5_CFG_BASE 0x7FFCF46438ull +#define KERNEL_TENSOR_1_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC5_CFG_BASE 0x7FFCF46470ull +#define KERNEL_TENSOR_2_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC5_CFG_BASE 0x7FFCF464A8ull +#define KERNEL_TENSOR_3_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC5_CFG_BASE 0x7FFCF464E0ull +#define KERNEL_TENSOR_4_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC5_CFG_BASE 0x7FFCF46518ull +#define KERNEL_TENSOR_5_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC5_CFG_BASE 0x7FFCF46550ull +#define KERNEL_TENSOR_6_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC5_CFG_BASE 0x7FFCF46588ull +#define KERNEL_TENSOR_7_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC5_CFG_BASE 0x7FFCF465C0ull +#define KERNEL_TENSOR_8_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC5_CFG_BASE 0x7FFCF465F8ull +#define KERNEL_TENSOR_9_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC5_CFG_BASE 0x7FFCF46630ull +#define KERNEL_TENSOR_10_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC5_CFG_BASE 0x7FFCF46668ull +#define KERNEL_TENSOR_11_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC5_CFG_BASE 0x7FFCF466A0ull +#define KERNEL_TENSOR_12_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC5_CFG_BASE 0x7FFCF466D8ull +#define KERNEL_TENSOR_13_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC5_CFG_BASE 0x7FFCF46710ull +#define KERNEL_TENSOR_14_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC5_CFG_BASE 0x7FFCF46748ull +#define KERNEL_TENSOR_15_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC5_CFG_BASE 0x7FFCF46780ull +#define KERNEL_SYNC_OBJECT_TPC5_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC5_CFG_SECTION 0x8000 +#define mmKERNEL_TPC5_CFG_BASE 0x7FFCF46788ull +#define KERNEL_TPC5_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC5_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC5_CFG_BASE 0x7FFCF46A00ull +#define QM_TENSOR_0_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC5_CFG_BASE 0x7FFCF46A38ull +#define QM_TENSOR_1_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC5_CFG_BASE 0x7FFCF46A70ull +#define QM_TENSOR_2_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC5_CFG_BASE 0x7FFCF46AA8ull +#define QM_TENSOR_3_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC5_CFG_BASE 0x7FFCF46AE0ull +#define QM_TENSOR_4_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC5_CFG_BASE 0x7FFCF46B18ull +#define QM_TENSOR_5_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC5_CFG_BASE 0x7FFCF46B50ull +#define QM_TENSOR_6_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC5_CFG_BASE 0x7FFCF46B88ull +#define QM_TENSOR_7_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC5_CFG_BASE 0x7FFCF46BC0ull +#define QM_TENSOR_8_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC5_CFG_BASE 0x7FFCF46BF8ull +#define QM_TENSOR_9_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC5_CFG_BASE 0x7FFCF46C30ull +#define QM_TENSOR_10_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC5_CFG_BASE 0x7FFCF46C68ull +#define QM_TENSOR_11_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC5_CFG_BASE 0x7FFCF46CA0ull +#define QM_TENSOR_12_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC5_CFG_BASE 0x7FFCF46CD8ull +#define QM_TENSOR_13_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC5_CFG_BASE 0x7FFCF46D10ull +#define QM_TENSOR_14_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC5_CFG_BASE 0x7FFCF46D48ull +#define QM_TENSOR_15_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC5_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC5_CFG_BASE 0x7FFCF46D80ull +#define QM_SYNC_OBJECT_TPC5_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC5_CFG_SECTION 0x8000 +#define mmQM_TPC5_CFG_BASE 0x7FFCF46D88ull +#define QM_TPC5_CFG_MAX_OFFSET 0xB800 +#define QM_TPC5_CFG_SECTION 0x2780 +#define mmTPC5_E2E_CRED_BASE 0x7FFCF47000ull +#define TPC5_E2E_CRED_MAX_OFFSET 0x1680 +#define TPC5_E2E_CRED_SECTION 0x1000 +#define mmTPC5_QM_BASE 0x7FFCF48000ull +#define TPC5_QM_MAX_OFFSET 0xD040 +#define TPC5_QM_SECTION 0x3E000 +#define mmTPC6_CFG_BASE 0x7FFCF86000ull +#define TPC6_CFG_MAX_OFFSET 0xE400 +#define TPC6_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC6_CFG_BASE 0x7FFCF86400ull +#define KERNEL_TENSOR_0_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC6_CFG_BASE 0x7FFCF86438ull +#define KERNEL_TENSOR_1_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC6_CFG_BASE 0x7FFCF86470ull +#define KERNEL_TENSOR_2_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC6_CFG_BASE 0x7FFCF864A8ull +#define KERNEL_TENSOR_3_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC6_CFG_BASE 0x7FFCF864E0ull +#define KERNEL_TENSOR_4_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC6_CFG_BASE 0x7FFCF86518ull +#define KERNEL_TENSOR_5_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC6_CFG_BASE 0x7FFCF86550ull +#define KERNEL_TENSOR_6_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC6_CFG_BASE 0x7FFCF86588ull +#define KERNEL_TENSOR_7_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC6_CFG_BASE 0x7FFCF865C0ull +#define KERNEL_TENSOR_8_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC6_CFG_BASE 0x7FFCF865F8ull +#define KERNEL_TENSOR_9_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC6_CFG_BASE 0x7FFCF86630ull +#define KERNEL_TENSOR_10_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC6_CFG_BASE 0x7FFCF86668ull +#define KERNEL_TENSOR_11_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC6_CFG_BASE 0x7FFCF866A0ull +#define KERNEL_TENSOR_12_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC6_CFG_BASE 0x7FFCF866D8ull +#define KERNEL_TENSOR_13_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC6_CFG_BASE 0x7FFCF86710ull +#define KERNEL_TENSOR_14_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC6_CFG_BASE 0x7FFCF86748ull +#define KERNEL_TENSOR_15_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC6_CFG_BASE 0x7FFCF86780ull +#define KERNEL_SYNC_OBJECT_TPC6_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC6_CFG_SECTION 0x8000 +#define mmKERNEL_TPC6_CFG_BASE 0x7FFCF86788ull +#define KERNEL_TPC6_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC6_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC6_CFG_BASE 0x7FFCF86A00ull +#define QM_TENSOR_0_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC6_CFG_BASE 0x7FFCF86A38ull +#define QM_TENSOR_1_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC6_CFG_BASE 0x7FFCF86A70ull +#define QM_TENSOR_2_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC6_CFG_BASE 0x7FFCF86AA8ull +#define QM_TENSOR_3_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC6_CFG_BASE 0x7FFCF86AE0ull +#define QM_TENSOR_4_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC6_CFG_BASE 0x7FFCF86B18ull +#define QM_TENSOR_5_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC6_CFG_BASE 0x7FFCF86B50ull +#define QM_TENSOR_6_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC6_CFG_BASE 0x7FFCF86B88ull +#define QM_TENSOR_7_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC6_CFG_BASE 0x7FFCF86BC0ull +#define QM_TENSOR_8_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC6_CFG_BASE 0x7FFCF86BF8ull +#define QM_TENSOR_9_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC6_CFG_BASE 0x7FFCF86C30ull +#define QM_TENSOR_10_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC6_CFG_BASE 0x7FFCF86C68ull +#define QM_TENSOR_11_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC6_CFG_BASE 0x7FFCF86CA0ull +#define QM_TENSOR_12_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC6_CFG_BASE 0x7FFCF86CD8ull +#define QM_TENSOR_13_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC6_CFG_BASE 0x7FFCF86D10ull +#define QM_TENSOR_14_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC6_CFG_BASE 0x7FFCF86D48ull +#define QM_TENSOR_15_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC6_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC6_CFG_BASE 0x7FFCF86D80ull +#define QM_SYNC_OBJECT_TPC6_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC6_CFG_SECTION 0x8000 +#define mmQM_TPC6_CFG_BASE 0x7FFCF86D88ull +#define QM_TPC6_CFG_MAX_OFFSET 0xB800 +#define QM_TPC6_CFG_SECTION 0x2780 +#define mmTPC6_E2E_CRED_BASE 0x7FFCF87000ull +#define TPC6_E2E_CRED_MAX_OFFSET 0x1680 +#define TPC6_E2E_CRED_SECTION 0x1000 +#define mmTPC6_QM_BASE 0x7FFCF88000ull +#define TPC6_QM_MAX_OFFSET 0xD040 +#define TPC6_QM_SECTION 0x3E000 +#define mmTPC7_CFG_BASE 0x7FFCFC6000ull +#define TPC7_CFG_MAX_OFFSET 0xE400 +#define TPC7_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC7_CFG_BASE 0x7FFCFC6400ull +#define KERNEL_TENSOR_0_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC7_CFG_BASE 0x7FFCFC6438ull +#define KERNEL_TENSOR_1_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC7_CFG_BASE 0x7FFCFC6470ull +#define KERNEL_TENSOR_2_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC7_CFG_BASE 0x7FFCFC64A8ull +#define KERNEL_TENSOR_3_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC7_CFG_BASE 0x7FFCFC64E0ull +#define KERNEL_TENSOR_4_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC7_CFG_BASE 0x7FFCFC6518ull +#define KERNEL_TENSOR_5_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC7_CFG_BASE 0x7FFCFC6550ull +#define KERNEL_TENSOR_6_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC7_CFG_BASE 0x7FFCFC6588ull +#define KERNEL_TENSOR_7_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC7_CFG_BASE 0x7FFCFC65C0ull +#define KERNEL_TENSOR_8_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC7_CFG_BASE 0x7FFCFC65F8ull +#define KERNEL_TENSOR_9_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC7_CFG_BASE 0x7FFCFC6630ull +#define KERNEL_TENSOR_10_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC7_CFG_BASE 0x7FFCFC6668ull +#define KERNEL_TENSOR_11_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC7_CFG_BASE 0x7FFCFC66A0ull +#define KERNEL_TENSOR_12_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC7_CFG_BASE 0x7FFCFC66D8ull +#define KERNEL_TENSOR_13_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC7_CFG_BASE 0x7FFCFC6710ull +#define KERNEL_TENSOR_14_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC7_CFG_BASE 0x7FFCFC6748ull +#define KERNEL_TENSOR_15_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC7_CFG_BASE 0x7FFCFC6780ull +#define KERNEL_SYNC_OBJECT_TPC7_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC7_CFG_SECTION 0x8000 +#define mmKERNEL_TPC7_CFG_BASE 0x7FFCFC6788ull +#define KERNEL_TPC7_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC7_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC7_CFG_BASE 0x7FFCFC6A00ull +#define QM_TENSOR_0_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC7_CFG_BASE 0x7FFCFC6A38ull +#define QM_TENSOR_1_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC7_CFG_BASE 0x7FFCFC6A70ull +#define QM_TENSOR_2_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC7_CFG_BASE 0x7FFCFC6AA8ull +#define QM_TENSOR_3_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC7_CFG_BASE 0x7FFCFC6AE0ull +#define QM_TENSOR_4_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC7_CFG_BASE 0x7FFCFC6B18ull +#define QM_TENSOR_5_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC7_CFG_BASE 0x7FFCFC6B50ull +#define QM_TENSOR_6_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC7_CFG_BASE 0x7FFCFC6B88ull +#define QM_TENSOR_7_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC7_CFG_BASE 0x7FFCFC6BC0ull +#define QM_TENSOR_8_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC7_CFG_BASE 0x7FFCFC6BF8ull +#define QM_TENSOR_9_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC7_CFG_BASE 0x7FFCFC6C30ull +#define QM_TENSOR_10_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC7_CFG_BASE 0x7FFCFC6C68ull +#define QM_TENSOR_11_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC7_CFG_BASE 0x7FFCFC6CA0ull +#define QM_TENSOR_12_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC7_CFG_BASE 0x7FFCFC6CD8ull +#define QM_TENSOR_13_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC7_CFG_BASE 0x7FFCFC6D10ull +#define QM_TENSOR_14_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC7_CFG_BASE 0x7FFCFC6D48ull +#define QM_TENSOR_15_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC7_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC7_CFG_BASE 0x7FFCFC6D80ull +#define QM_SYNC_OBJECT_TPC7_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC7_CFG_SECTION 0x8000 +#define mmQM_TPC7_CFG_BASE 0x7FFCFC6D88ull +#define QM_TPC7_CFG_MAX_OFFSET 0xB800 +#define QM_TPC7_CFG_SECTION 0x2780 +#define mmTPC7_E2E_CRED_BASE 0x7FFCFC7000ull +#define TPC7_E2E_CRED_MAX_OFFSET 0x1680 +#define TPC7_E2E_CRED_SECTION 0x1000 +#define mmTPC7_QM_BASE 0x7FFCFC8000ull +#define TPC7_QM_MAX_OFFSET 0xD040 +#define TPC7_QM_SECTION 0x1038000 +#define mmMME_S_ROM_TABLE_BASE 0x7FFE000000ull +#define MME_S_ROM_TABLE_MAX_OFFSET 0x1000 +#define MME_S_ROM_TABLE_SECTION 0x21000 +#define mmMME0_ACC_STM_BASE 0x7FFE021000ull +#define MME0_ACC_STM_MAX_OFFSET 0x1000 +#define MME0_ACC_STM_SECTION 0x1000 +#define mmMME0_ACC_CTI_BASE 0x7FFE022000ull +#define MME0_ACC_CTI_MAX_OFFSET 0x1000 +#define MME0_ACC_CTI_SECTION 0x1000 +#define mmMME0_ACC_ETF_BASE 0x7FFE023000ull +#define MME0_ACC_ETF_MAX_OFFSET 0x1000 +#define MME0_ACC_ETF_SECTION 0x1000 +#define mmMME0_ACC_SPMU_BASE 0x7FFE024000ull +#define MME0_ACC_SPMU_MAX_OFFSET 0x1000 +#define MME0_ACC_SPMU_SECTION 0x1000 +#define mmMME0_ACC_CTI0_BASE 0x7FFE025000ull +#define MME0_ACC_CTI0_MAX_OFFSET 0x1000 +#define MME0_ACC_CTI0_SECTION 0x1000 +#define mmMME0_ACC_CTI1_BASE 0x7FFE026000ull +#define MME0_ACC_CTI1_MAX_OFFSET 0x1000 +#define MME0_ACC_CTI1_SECTION 0x1000 +#define mmMME0_ACC_BMON0_BASE 0x7FFE027000ull +#define MME0_ACC_BMON0_MAX_OFFSET 0x1000 +#define MME0_ACC_BMON0_SECTION 0x9000 +#define mmMME0_ACC_FUNNEL_BASE 0x7FFE030000ull +#define MME0_ACC_FUNNEL_MAX_OFFSET 0x1000 +#define MME0_ACC_FUNNEL_SECTION 0x11000 +#define mmMME0_SBAB_STM_BASE 0x7FFE041000ull +#define MME0_SBAB_STM_MAX_OFFSET 0x1000 +#define MME0_SBAB_STM_SECTION 0x1000 +#define mmMME0_SBAB_CTI_BASE 0x7FFE042000ull +#define MME0_SBAB_CTI_MAX_OFFSET 0x1000 +#define MME0_SBAB_CTI_SECTION 0x1000 +#define mmMME0_SBAB_ETF_BASE 0x7FFE043000ull +#define MME0_SBAB_ETF_MAX_OFFSET 0x1000 +#define MME0_SBAB_ETF_SECTION 0x1000 +#define mmMME0_SBAB_SPMU_BASE 0x7FFE044000ull +#define MME0_SBAB_SPMU_MAX_OFFSET 0x1000 +#define MME0_SBAB_SPMU_SECTION 0x1000 +#define mmMME0_SBAB_CTI0_BASE 0x7FFE045000ull +#define MME0_SBAB_CTI0_MAX_OFFSET 0x1000 +#define MME0_SBAB_CTI0_SECTION 0x1000 +#define mmMME0_SBAB_CTI1_BASE 0x7FFE046000ull +#define MME0_SBAB_CTI1_MAX_OFFSET 0x1000 +#define MME0_SBAB_CTI1_SECTION 0x1000 +#define mmMME0_SBAB_BMON0_BASE 0x7FFE047000ull +#define MME0_SBAB_BMON0_MAX_OFFSET 0x1000 +#define MME0_SBAB_BMON0_SECTION 0x1000 +#define mmMME0_SBAB_BMON1_BASE 0x7FFE048000ull +#define MME0_SBAB_BMON1_MAX_OFFSET 0x1000 +#define MME0_SBAB_BMON1_SECTION 0x19000 +#define mmMME0_CTRL_STM_BASE 0x7FFE061000ull +#define MME0_CTRL_STM_MAX_OFFSET 0x1000 +#define MME0_CTRL_STM_SECTION 0x1000 +#define mmMME0_CTRL_CTI_BASE 0x7FFE062000ull +#define MME0_CTRL_CTI_MAX_OFFSET 0x1000 +#define MME0_CTRL_CTI_SECTION 0x1000 +#define mmMME0_CTRL_ETF_BASE 0x7FFE063000ull +#define MME0_CTRL_ETF_MAX_OFFSET 0x1000 +#define MME0_CTRL_ETF_SECTION 0x1000 +#define mmMME0_CTRL_SPMU_BASE 0x7FFE064000ull +#define MME0_CTRL_SPMU_MAX_OFFSET 0x1000 +#define MME0_CTRL_SPMU_SECTION 0x1000 +#define mmMME0_CTRL_CTI0_BASE 0x7FFE065000ull +#define MME0_CTRL_CTI0_MAX_OFFSET 0x1000 +#define MME0_CTRL_CTI0_SECTION 0x1000 +#define mmMME0_CTRL_CTI1_BASE 0x7FFE066000ull +#define MME0_CTRL_CTI1_MAX_OFFSET 0x1000 +#define MME0_CTRL_CTI1_SECTION 0x1000 +#define mmMME0_CTRL_BMON0_BASE 0x7FFE067000ull +#define MME0_CTRL_BMON0_MAX_OFFSET 0x1000 +#define MME0_CTRL_BMON0_SECTION 0x1000 +#define mmMME0_CTRL_BMON1_BASE 0x7FFE068000ull +#define MME0_CTRL_BMON1_MAX_OFFSET 0x1000 +#define MME0_CTRL_BMON1_SECTION 0x39000 +#define mmMME1_ACC_STM_BASE 0x7FFE0A1000ull +#define MME1_ACC_STM_MAX_OFFSET 0x1000 +#define MME1_ACC_STM_SECTION 0x1000 +#define mmMME1_ACC_CTI_BASE 0x7FFE0A2000ull +#define MME1_ACC_CTI_MAX_OFFSET 0x1000 +#define MME1_ACC_CTI_SECTION 0x1000 +#define mmMME1_ACC_ETF_BASE 0x7FFE0A3000ull +#define MME1_ACC_ETF_MAX_OFFSET 0x1000 +#define MME1_ACC_ETF_SECTION 0x1000 +#define mmMME1_ACC_SPMU_BASE 0x7FFE0A4000ull +#define MME1_ACC_SPMU_MAX_OFFSET 0x1000 +#define MME1_ACC_SPMU_SECTION 0x1000 +#define mmMME1_ACC_CTI0_BASE 0x7FFE0A5000ull +#define MME1_ACC_CTI0_MAX_OFFSET 0x1000 +#define MME1_ACC_CTI0_SECTION 0x1000 +#define mmMME1_ACC_CTI1_BASE 0x7FFE0A6000ull +#define MME1_ACC_CTI1_MAX_OFFSET 0x1000 +#define MME1_ACC_CTI1_SECTION 0x1000 +#define mmMME1_ACC_BMON0_BASE 0x7FFE0A7000ull +#define MME1_ACC_BMON0_MAX_OFFSET 0x1000 +#define MME1_ACC_BMON0_SECTION 0x9000 +#define mmMME1_ACC_FUNNEL_BASE 0x7FFE0B0000ull +#define MME1_ACC_FUNNEL_MAX_OFFSET 0x1000 +#define MME1_ACC_FUNNEL_SECTION 0x11000 +#define mmMME1_SBAB_STM_BASE 0x7FFE0C1000ull +#define MME1_SBAB_STM_MAX_OFFSET 0x1000 +#define MME1_SBAB_STM_SECTION 0x1000 +#define mmMME1_SBAB_CTI_BASE 0x7FFE0C2000ull +#define MME1_SBAB_CTI_MAX_OFFSET 0x1000 +#define MME1_SBAB_CTI_SECTION 0x1000 +#define mmMME1_SBAB_ETF_BASE 0x7FFE0C3000ull +#define MME1_SBAB_ETF_MAX_OFFSET 0x1000 +#define MME1_SBAB_ETF_SECTION 0x1000 +#define mmMME1_SBAB_SPMU_BASE 0x7FFE0C4000ull +#define MME1_SBAB_SPMU_MAX_OFFSET 0x1000 +#define MME1_SBAB_SPMU_SECTION 0x1000 +#define mmMME1_SBAB_CTI0_BASE 0x7FFE0C5000ull +#define MME1_SBAB_CTI0_MAX_OFFSET 0x1000 +#define MME1_SBAB_CTI0_SECTION 0x1000 +#define mmMME1_SBAB_CTI1_BASE 0x7FFE0C6000ull +#define MME1_SBAB_CTI1_MAX_OFFSET 0x1000 +#define MME1_SBAB_CTI1_SECTION 0x1000 +#define mmMME1_SBAB_BMON0_BASE 0x7FFE0C7000ull +#define MME1_SBAB_BMON0_MAX_OFFSET 0x1000 +#define MME1_SBAB_BMON0_SECTION 0x1000 +#define mmMME1_SBAB_BMON1_BASE 0x7FFE0C8000ull +#define MME1_SBAB_BMON1_MAX_OFFSET 0x1000 +#define MME1_SBAB_BMON1_SECTION 0x19000 +#define mmMME1_CTRL_STM_BASE 0x7FFE0E1000ull +#define MME1_CTRL_STM_MAX_OFFSET 0x1000 +#define MME1_CTRL_STM_SECTION 0x1000 +#define mmMME1_CTRL_CTI_BASE 0x7FFE0E2000ull +#define MME1_CTRL_CTI_MAX_OFFSET 0x1000 +#define MME1_CTRL_CTI_SECTION 0x1000 +#define mmMME1_CTRL_ETF_BASE 0x7FFE0E3000ull +#define MME1_CTRL_ETF_MAX_OFFSET 0x1000 +#define MME1_CTRL_ETF_SECTION 0x1000 +#define mmMME1_CTRL_SPMU_BASE 0x7FFE0E4000ull +#define MME1_CTRL_SPMU_MAX_OFFSET 0x1000 +#define MME1_CTRL_SPMU_SECTION 0x1000 +#define mmMME1_CTRL_CTI0_BASE 0x7FFE0E5000ull +#define MME1_CTRL_CTI0_MAX_OFFSET 0x1000 +#define MME1_CTRL_CTI0_SECTION 0x1000 +#define mmMME1_CTRL_CTI1_BASE 0x7FFE0E6000ull +#define MME1_CTRL_CTI1_MAX_OFFSET 0x1000 +#define MME1_CTRL_CTI1_SECTION 0x1000 +#define mmMME1_CTRL_BMON0_BASE 0x7FFE0E7000ull +#define MME1_CTRL_BMON0_MAX_OFFSET 0x1000 +#define MME1_CTRL_BMON0_SECTION 0x1000 +#define mmMME1_CTRL_BMON1_BASE 0x7FFE0E8000ull +#define MME1_CTRL_BMON1_MAX_OFFSET 0x1000 +#define MME1_CTRL_BMON1_SECTION 0x18000 +#define mmMME_N_ROM_TABLE_BASE 0x7FFE100000ull +#define MME_N_ROM_TABLE_MAX_OFFSET 0x1000 +#define MME_N_ROM_TABLE_SECTION 0x21000 +#define mmMME2_ACC_STM_BASE 0x7FFE121000ull +#define MME2_ACC_STM_MAX_OFFSET 0x1000 +#define MME2_ACC_STM_SECTION 0x1000 +#define mmMME2_ACC_CTI_BASE 0x7FFE122000ull +#define MME2_ACC_CTI_MAX_OFFSET 0x1000 +#define MME2_ACC_CTI_SECTION 0x1000 +#define mmMME2_MME2_ACC_ETF_BASE 0x7FFE123000ull +#define MME2_MME2_ACC_ETF_MAX_OFFSET 0x1000 +#define MME2_MME2_ACC_ETF_SECTION 0x1000 +#define mmMME2_ACC_SPMU_BASE 0x7FFE124000ull +#define MME2_ACC_SPMU_MAX_OFFSET 0x1000 +#define MME2_ACC_SPMU_SECTION 0x1000 +#define mmMME2_ACC_CTI0_BASE 0x7FFE125000ull +#define MME2_ACC_CTI0_MAX_OFFSET 0x1000 +#define MME2_ACC_CTI0_SECTION 0x1000 +#define mmMME2_ACC_CTI1_BASE 0x7FFE126000ull +#define MME2_ACC_CTI1_MAX_OFFSET 0x1000 +#define MME2_ACC_CTI1_SECTION 0x1000 +#define mmMME2_ACC_BMON0_BASE 0x7FFE127000ull +#define MME2_ACC_BMON0_MAX_OFFSET 0x1000 +#define MME2_ACC_BMON0_SECTION 0x9000 +#define mmMME2_ACC_FUNNEL_BASE 0x7FFE130000ull +#define MME2_ACC_FUNNEL_MAX_OFFSET 0x1000 +#define MME2_ACC_FUNNEL_SECTION 0x11000 +#define mmMME2_SBAB_STM_BASE 0x7FFE141000ull +#define MME2_SBAB_STM_MAX_OFFSET 0x1000 +#define MME2_SBAB_STM_SECTION 0x1000 +#define mmMME2_SBAB_CTI_BASE 0x7FFE142000ull +#define MME2_SBAB_CTI_MAX_OFFSET 0x1000 +#define MME2_SBAB_CTI_SECTION 0x1000 +#define mmMME2_SBAB_ETF_BASE 0x7FFE143000ull +#define MME2_SBAB_ETF_MAX_OFFSET 0x1000 +#define MME2_SBAB_ETF_SECTION 0x1000 +#define mmMME2_SBAB_SPMU_BASE 0x7FFE144000ull +#define MME2_SBAB_SPMU_MAX_OFFSET 0x1000 +#define MME2_SBAB_SPMU_SECTION 0x1000 +#define mmMME2_SBAB_CTI0_BASE 0x7FFE145000ull +#define MME2_SBAB_CTI0_MAX_OFFSET 0x1000 +#define MME2_SBAB_CTI0_SECTION 0x1000 +#define mmMME2_SBAB_CTI1_BASE 0x7FFE146000ull +#define MME2_SBAB_CTI1_MAX_OFFSET 0x1000 +#define MME2_SBAB_CTI1_SECTION 0x1000 +#define mmMME2_SBAB_BMON0_BASE 0x7FFE147000ull +#define MME2_SBAB_BMON0_MAX_OFFSET 0x1000 +#define MME2_SBAB_BMON0_SECTION 0x1000 +#define mmMME2_SBAB_BMON1_BASE 0x7FFE148000ull +#define MME2_SBAB_BMON1_MAX_OFFSET 0x1000 +#define MME2_SBAB_BMON1_SECTION 0x19000 +#define mmMME2_CTRL_STM_BASE 0x7FFE161000ull +#define MME2_CTRL_STM_MAX_OFFSET 0x1000 +#define MME2_CTRL_STM_SECTION 0x1000 +#define mmMME2_CTRL_CTI_BASE 0x7FFE162000ull +#define MME2_CTRL_CTI_MAX_OFFSET 0x1000 +#define MME2_CTRL_CTI_SECTION 0x1000 +#define mmMME2_CTRL_ETF_BASE 0x7FFE163000ull +#define MME2_CTRL_ETF_MAX_OFFSET 0x1000 +#define MME2_CTRL_ETF_SECTION 0x1000 +#define mmMME2_CTRL_SPMU_BASE 0x7FFE164000ull +#define MME2_CTRL_SPMU_MAX_OFFSET 0x1000 +#define MME2_CTRL_SPMU_SECTION 0x1000 +#define mmMME2_CTRL_CTI0_BASE 0x7FFE165000ull +#define MME2_CTRL_CTI0_MAX_OFFSET 0x1000 +#define MME2_CTRL_CTI0_SECTION 0x1000 +#define mmMME2_CTRL_CTI1_BASE 0x7FFE166000ull +#define MME2_CTRL_CTI1_MAX_OFFSET 0x1000 +#define MME2_CTRL_CTI1_SECTION 0x1000 +#define mmMME2_CTRL_BMON0_BASE 0x7FFE167000ull +#define MME2_CTRL_BMON0_MAX_OFFSET 0x1000 +#define MME2_CTRL_BMON0_SECTION 0x1000 +#define mmMME2_CTRL_BMON1_BASE 0x7FFE168000ull +#define MME2_CTRL_BMON1_MAX_OFFSET 0x1000 +#define MME2_CTRL_BMON1_SECTION 0x39000 +#define mmMME3_ACC_STM_BASE 0x7FFE1A1000ull +#define MME3_ACC_STM_MAX_OFFSET 0x1000 +#define MME3_ACC_STM_SECTION 0x1000 +#define mmMME3_ACC_CTI_BASE 0x7FFE1A2000ull +#define MME3_ACC_CTI_MAX_OFFSET 0x1000 +#define MME3_ACC_CTI_SECTION 0x1000 +#define mmMME3_ACC_ETF_BASE 0x7FFE1A3000ull +#define MME3_ACC_ETF_MAX_OFFSET 0x1000 +#define MME3_ACC_ETF_SECTION 0x1000 +#define mmMME3_ACC_SPMU_BASE 0x7FFE1A4000ull +#define MME3_ACC_SPMU_MAX_OFFSET 0x1000 +#define MME3_ACC_SPMU_SECTION 0x1000 +#define mmMME3_ACC_CTI0_BASE 0x7FFE1A5000ull +#define MME3_ACC_CTI0_MAX_OFFSET 0x1000 +#define MME3_ACC_CTI0_SECTION 0x1000 +#define mmMME3_ACC_CTI1_BASE 0x7FFE1A6000ull +#define MME3_ACC_CTI1_MAX_OFFSET 0x1000 +#define MME3_ACC_CTI1_SECTION 0x1000 +#define mmMME3_ACC_BMON0_BASE 0x7FFE1A7000ull +#define MME3_ACC_BMON0_MAX_OFFSET 0x1000 +#define MME3_ACC_BMON0_SECTION 0x9000 +#define mmMME3_ACC_FUNNEL_BASE 0x7FFE1B0000ull +#define MME3_ACC_FUNNEL_MAX_OFFSET 0x1000 +#define MME3_ACC_FUNNEL_SECTION 0x11000 +#define mmMME3_SBAB_STM_BASE 0x7FFE1C1000ull +#define MME3_SBAB_STM_MAX_OFFSET 0x1000 +#define MME3_SBAB_STM_SECTION 0x1000 +#define mmMME3_SBAB_CTI_BASE 0x7FFE1C2000ull +#define MME3_SBAB_CTI_MAX_OFFSET 0x1000 +#define MME3_SBAB_CTI_SECTION 0x1000 +#define mmMME3_SBAB_ETF_BASE 0x7FFE1C3000ull +#define MME3_SBAB_ETF_MAX_OFFSET 0x1000 +#define MME3_SBAB_ETF_SECTION 0x1000 +#define mmMME3_SBAB_SPMU_BASE 0x7FFE1C4000ull +#define MME3_SBAB_SPMU_MAX_OFFSET 0x1000 +#define MME3_SBAB_SPMU_SECTION 0x1000 +#define mmMME3_SBAB_CTI0_BASE 0x7FFE1C5000ull +#define MME3_SBAB_CTI0_MAX_OFFSET 0x1000 +#define MME3_SBAB_CTI0_SECTION 0x1000 +#define mmMME3_SBAB_CTI1_BASE 0x7FFE1C6000ull +#define MME3_SBAB_CTI1_MAX_OFFSET 0x1000 +#define MME3_SBAB_CTI1_SECTION 0x1000 +#define mmMME3_SBAB_BMON0_BASE 0x7FFE1C7000ull +#define MME3_SBAB_BMON0_MAX_OFFSET 0x1000 +#define MME3_SBAB_BMON0_SECTION 0x1000 +#define mmMME3_SBAB_BMON1_BASE 0x7FFE1C8000ull +#define MME3_SBAB_BMON1_MAX_OFFSET 0x1000 +#define MME3_SBAB_BMON1_SECTION 0x19000 +#define mmMME3_CTRL_STM_BASE 0x7FFE1E1000ull +#define MME3_CTRL_STM_MAX_OFFSET 0x1000 +#define MME3_CTRL_STM_SECTION 0x1000 +#define mmMME3_CTRL_CTI_BASE 0x7FFE1E2000ull +#define MME3_CTRL_CTI_MAX_OFFSET 0x1000 +#define MME3_CTRL_CTI_SECTION 0x1000 +#define mmMME3_CTRL_ETF_BASE 0x7FFE1E3000ull +#define MME3_CTRL_ETF_MAX_OFFSET 0x1000 +#define MME3_CTRL_ETF_SECTION 0x1000 +#define mmMME3_CTRL_SPMU_BASE 0x7FFE1E4000ull +#define MME3_CTRL_SPMU_MAX_OFFSET 0x1000 +#define MME3_CTRL_SPMU_SECTION 0x1000 +#define mmMME3_CTRL_CTI0_BASE 0x7FFE1E5000ull +#define MME3_CTRL_CTI0_MAX_OFFSET 0x1000 +#define MME3_CTRL_CTI0_SECTION 0x1000 +#define mmMME3_CTRL_CTI1_BASE 0x7FFE1E6000ull +#define MME3_CTRL_CTI1_MAX_OFFSET 0x1000 +#define MME3_CTRL_CTI1_SECTION 0x1000 +#define mmMME3_CTRL_BMON0_BASE 0x7FFE1E7000ull +#define MME3_CTRL_BMON0_MAX_OFFSET 0x1000 +#define MME3_CTRL_BMON0_SECTION 0x1000 +#define mmMME3_CTRL_BMON1_BASE 0x7FFE1E8000ull +#define MME3_CTRL_BMON1_MAX_OFFSET 0x1000 +#define MME3_CTRL_BMON1_SECTION 0x18000 +#define mmIC_ROM_TABLE_BASE 0x7FFE200000ull +#define IC_ROM_TABLE_MAX_OFFSET 0x1000 +#define IC_ROM_TABLE_SECTION 0x1000 +#define mmSRAM_Y0_X0_FUNNEL_BASE 0x7FFE201000ull +#define SRAM_Y0_X0_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y0_X0_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y0_X1_FUNNEL_BASE 0x7FFE209000ull +#define SRAM_Y0_X1_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y0_X1_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y0_X2_FUNNEL_BASE 0x7FFE211000ull +#define SRAM_Y0_X2_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y0_X2_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y0_X3_FUNNEL_BASE 0x7FFE219000ull +#define SRAM_Y0_X3_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y0_X3_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y0_X4_FUNNEL_BASE 0x7FFE221000ull +#define SRAM_Y0_X4_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y0_X4_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y0_X5_FUNNEL_BASE 0x7FFE229000ull +#define SRAM_Y0_X5_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y0_X5_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y0_X6_FUNNEL_BASE 0x7FFE231000ull +#define SRAM_Y0_X6_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y0_X6_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y0_X7_FUNNEL_BASE 0x7FFE239000ull +#define SRAM_Y0_X7_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y0_X7_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y1_X0_FUNNEL_BASE 0x7FFE241000ull +#define SRAM_Y1_X0_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y1_X0_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y1_X1_FUNNEL_BASE 0x7FFE249000ull +#define SRAM_Y1_X1_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y1_X1_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y1_X2_FUNNEL_BASE 0x7FFE251000ull +#define SRAM_Y1_X2_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y1_X2_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y1_X3_FUNNEL_BASE 0x7FFE259000ull +#define SRAM_Y1_X3_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y1_X3_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y1_X4_FUNNEL_BASE 0x7FFE261000ull +#define SRAM_Y1_X4_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y1_X4_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y1_X5_FUNNEL_BASE 0x7FFE269000ull +#define SRAM_Y1_X5_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y1_X5_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y1_X6_FUNNEL_BASE 0x7FFE271000ull +#define SRAM_Y1_X6_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y1_X6_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y1_X7_FUNNEL_BASE 0x7FFE279000ull +#define SRAM_Y1_X7_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y1_X7_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y2_X0_FUNNEL_BASE 0x7FFE281000ull +#define SRAM_Y2_X0_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y2_X0_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y2_X1_FUNNEL_BASE 0x7FFE289000ull +#define SRAM_Y2_X1_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y2_X1_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y2_X2_FUNNEL_BASE 0x7FFE291000ull +#define SRAM_Y2_X2_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y2_X2_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y2_X3_FUNNEL_BASE 0x7FFE299000ull +#define SRAM_Y2_X3_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y2_X3_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y2_X4_FUNNEL_BASE 0x7FFE2A1000ull +#define SRAM_Y2_X4_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y2_X4_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y2_X5_FUNNEL_BASE 0x7FFE2A9000ull +#define SRAM_Y2_X5_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y2_X5_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y2_X6_FUNNEL_BASE 0x7FFE2B1000ull +#define SRAM_Y2_X6_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y2_X6_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y2_X7_FUNNEL_BASE 0x7FFE2B9000ull +#define SRAM_Y2_X7_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y2_X7_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y3_X0_FUNNEL_BASE 0x7FFE2C1000ull +#define SRAM_Y3_X0_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y3_X0_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y3_X1_FUNNEL_BASE 0x7FFE2C9000ull +#define SRAM_Y3_X1_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y3_X1_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y3_X2_FUNNEL_BASE 0x7FFE2D1000ull +#define SRAM_Y3_X2_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y3_X2_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y3_X4_FUNNEL_BASE 0x7FFE2D9000ull +#define SRAM_Y3_X4_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y3_X4_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y3_X3_FUNNEL_BASE 0x7FFE2E1000ull +#define SRAM_Y3_X3_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y3_X3_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y3_X5_FUNNEL_BASE 0x7FFE2E9000ull +#define SRAM_Y3_X5_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y3_X5_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y3_X6_FUNNEL_BASE 0x7FFE2F1000ull +#define SRAM_Y3_X6_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y3_X6_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y3_X7_FUNNEL_BASE 0x7FFE2F9000ull +#define SRAM_Y3_X7_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y3_X7_FUNNEL_SECTION 0x7000 +#define mmIF_ROM_TABLE_BASE 0x7FFE300000ull +#define IF_ROM_TABLE_MAX_OFFSET 0x1000 +#define IF_ROM_TABLE_SECTION 0x1000 +#define mmSIF_FUNNEL_0_BASE 0x7FFE301000ull +#define SIF_FUNNEL_0_MAX_OFFSET 0x1000 +#define SIF_FUNNEL_0_SECTION 0x10000 +#define mmSIF_FUNNEL_1_BASE 0x7FFE311000ull +#define SIF_FUNNEL_1_MAX_OFFSET 0x1000 +#define SIF_FUNNEL_1_SECTION 0x10000 +#define mmSIF_FUNNEL_2_BASE 0x7FFE321000ull +#define SIF_FUNNEL_2_MAX_OFFSET 0x1000 +#define SIF_FUNNEL_2_SECTION 0x10000 +#define mmSIF_FUNNEL_3_BASE 0x7FFE331000ull +#define SIF_FUNNEL_3_MAX_OFFSET 0x1000 +#define SIF_FUNNEL_3_SECTION 0x10000 +#define mmSIF_FUNNEL_4_BASE 0x7FFE341000ull +#define SIF_FUNNEL_4_MAX_OFFSET 0x1000 +#define SIF_FUNNEL_4_SECTION 0x10000 +#define mmSIF_FUNNEL_5_BASE 0x7FFE351000ull +#define SIF_FUNNEL_5_MAX_OFFSET 0x1000 +#define SIF_FUNNEL_5_SECTION 0x10000 +#define mmSIF_FUNNEL_6_BASE 0x7FFE361000ull +#define SIF_FUNNEL_6_MAX_OFFSET 0x1000 +#define SIF_FUNNEL_6_SECTION 0x10000 +#define mmSIF_FUNNEL_7_BASE 0x7FFE371000ull +#define SIF_FUNNEL_7_MAX_OFFSET 0x1000 +#define SIF_FUNNEL_7_SECTION 0x10000 +#define mmNIF_FUNNEL_0_BASE 0x7FFE381000ull +#define NIF_FUNNEL_0_MAX_OFFSET 0x1000 +#define NIF_FUNNEL_0_SECTION 0x10000 +#define mmNIF_FUNNEL_1_BASE 0x7FFE391000ull +#define NIF_FUNNEL_1_MAX_OFFSET 0x1000 +#define NIF_FUNNEL_1_SECTION 0x10000 +#define mmNIF_FUNNEL_2_BASE 0x7FFE3A1000ull +#define NIF_FUNNEL_2_MAX_OFFSET 0x1000 +#define NIF_FUNNEL_2_SECTION 0x10000 +#define mmNIF_FUNNEL_3_BASE 0x7FFE3B1000ull +#define NIF_FUNNEL_3_MAX_OFFSET 0x1000 +#define NIF_FUNNEL_3_SECTION 0x10000 +#define mmNIF_FUNNEL_4_BASE 0x7FFE3C1000ull +#define NIF_FUNNEL_4_MAX_OFFSET 0x1000 +#define NIF_FUNNEL_4_SECTION 0x10000 +#define mmNIF_FUNNEL_5_BASE 0x7FFE3D1000ull +#define NIF_FUNNEL_5_MAX_OFFSET 0x1000 +#define NIF_FUNNEL_5_SECTION 0x10000 +#define mmNIF_FUNNEL_6_BASE 0x7FFE3E1000ull +#define NIF_FUNNEL_6_MAX_OFFSET 0x1000 +#define NIF_FUNNEL_6_SECTION 0x10000 +#define mmNIF_FUNNEL_7_BASE 0x7FFE3F1000ull +#define NIF_FUNNEL_7_MAX_OFFSET 0x1000 +#define NIF_FUNNEL_7_SECTION 0xF000 +#define mmDMA_IF_ROM_TABLE_BASE 0x7FFE400000ull +#define DMA_IF_ROM_TABLE_MAX_OFFSET 0x1000 +#define DMA_IF_ROM_TABLE_SECTION 0x1000 +#define mmDMA_IF_W_S_STM_BASE 0x7FFE401000ull +#define DMA_IF_W_S_STM_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_STM_SECTION 0x1000 +#define mmDMA_IF_W_S_CTI_BASE 0x7FFE402000ull +#define DMA_IF_W_S_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_CTI_SECTION 0x1000 +#define mmDMA_IF_W_S_ETF_BASE 0x7FFE403000ull +#define DMA_IF_W_S_ETF_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_ETF_SECTION 0x2000 +#define mmDMA_IF_W_S_BMON0_CTI_BASE 0x7FFE405000ull +#define DMA_IF_W_S_BMON0_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_BMON0_CTI_SECTION 0x1000 +#define mmDMA_IF_W_S_BMON1_CTI_BASE 0x7FFE406000ull +#define DMA_IF_W_S_BMON1_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_BMON1_CTI_SECTION 0x1000 +#define mmDMA_IF_W_S_HBM0_WR_BMON_BASE 0x7FFE407000ull +#define DMA_IF_W_S_HBM0_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_HBM0_WR_BMON_SECTION 0x1000 +#define mmDMA_IF_W_S_HBM0_RD_BMON_BASE 0x7FFE408000ull +#define DMA_IF_W_S_HBM0_RD_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_HBM0_RD_BMON_SECTION 0x1000 +#define mmDMA_IF_W_S_HBM1_WR_BMON_BASE 0x7FFE409000ull +#define DMA_IF_W_S_HBM1_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_HBM1_WR_BMON_SECTION 0x1000 +#define mmDMA_IF_W_S_HBM1_RD_BMON_BASE 0x7FFE40A000ull +#define DMA_IF_W_S_HBM1_RD_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_HBM1_RD_BMON_SECTION 0x1000 +#define mmDMA_IF_W_S_SOB_WR_BMON_BASE 0x7FFE40B000ull +#define DMA_IF_W_S_SOB_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_SOB_WR_BMON_SECTION 0x4000 +#define mmDMA_IF_W_S_FUNNEL_BASE 0x7FFE40F000ull +#define DMA_IF_W_S_FUNNEL_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_FUNNEL_SECTION 0x12000 +#define mmDMA_IF_E_S_STM_BASE 0x7FFE421000ull +#define DMA_IF_E_S_STM_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_STM_SECTION 0x1000 +#define mmDMA_IF_E_S_CTI_BASE 0x7FFE422000ull +#define DMA_IF_E_S_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_CTI_SECTION 0x1000 +#define mmDMA_IF_E_S_ETF_BASE 0x7FFE423000ull +#define DMA_IF_E_S_ETF_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_ETF_SECTION 0x2000 +#define mmDMA_IF_E_S_BMON0_CTI_BASE 0x7FFE425000ull +#define DMA_IF_E_S_BMON0_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_BMON0_CTI_SECTION 0x1000 +#define mmDMA_IF_E_S_BMON1_CTI_BASE 0x7FFE426000ull +#define DMA_IF_E_S_BMON1_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_BMON1_CTI_SECTION 0x1000 +#define mmDMA_IF_E_S_HBM0_WR_BMON_BASE 0x7FFE427000ull +#define DMA_IF_E_S_HBM0_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_HBM0_WR_BMON_SECTION 0x1000 +#define mmDMA_IF_E_S_HBM0_RD_BMON_BASE 0x7FFE428000ull +#define DMA_IF_E_S_HBM0_RD_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_HBM0_RD_BMON_SECTION 0x1000 +#define mmDMA_IF_E_S_HBM1_WR_BMON_BASE 0x7FFE429000ull +#define DMA_IF_E_S_HBM1_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_HBM1_WR_BMON_SECTION 0x1000 +#define mmDMA_IF_E_S_HBM1_RD_BMON_BASE 0x7FFE42A000ull +#define DMA_IF_E_S_HBM1_RD_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_HBM1_RD_BMON_SECTION 0x1000 +#define mmDMA_IF_E_S_SOB_WR_BMON_BASE 0x7FFE42B000ull +#define DMA_IF_E_S_SOB_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_SOB_WR_BMON_SECTION 0x4000 +#define mmDMA_IF_E_S_FUNNEL_BASE 0x7FFE42F000ull +#define DMA_IF_E_S_FUNNEL_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_FUNNEL_SECTION 0x12000 +#define mmDMA_IF_W_N_STM_BASE 0x7FFE441000ull +#define DMA_IF_W_N_STM_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_STM_SECTION 0x1000 +#define mmDMA_IF_W_N_CTI_BASE 0x7FFE442000ull +#define DMA_IF_W_N_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_CTI_SECTION 0x1000 +#define mmDMA_IF_W_N_ETF_BASE 0x7FFE443000ull +#define DMA_IF_W_N_ETF_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_ETF_SECTION 0x2000 +#define mmDMA_IF_W_N_BMON0_CTI_BASE 0x7FFE445000ull +#define DMA_IF_W_N_BMON0_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_BMON0_CTI_SECTION 0x1000 +#define mmDMA_IF_W_N_BMON1_CTI_BASE 0x7FFE446000ull +#define DMA_IF_W_N_BMON1_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_BMON1_CTI_SECTION 0x1000 +#define mmDMA_IF_W_N_HBM0_WR_BMON_BASE 0x7FFE447000ull +#define DMA_IF_W_N_HBM0_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_HBM0_WR_BMON_SECTION 0x1000 +#define mmDMA_IF_W_N_HBM0_RD_BMON_BASE 0x7FFE448000ull +#define DMA_IF_W_N_HBM0_RD_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_HBM0_RD_BMON_SECTION 0x1000 +#define mmDMA_IF_W_N_HBM1_WR_BMON_BASE 0x7FFE449000ull +#define DMA_IF_W_N_HBM1_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_HBM1_WR_BMON_SECTION 0x1000 +#define mmDMA_IF_W_N_HBM1_RD_BMON_BASE 0x7FFE44A000ull +#define DMA_IF_W_N_HBM1_RD_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_HBM1_RD_BMON_SECTION 0x1000 +#define mmDMA_IF_W_N_SOB_WR_BMON_BASE 0x7FFE44B000ull +#define DMA_IF_W_N_SOB_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_SOB_WR_BMON_SECTION 0x4000 +#define mmDMA_IF_W_N_FUNNEL_BASE 0x7FFE44F000ull +#define DMA_IF_W_N_FUNNEL_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_FUNNEL_SECTION 0x12000 +#define mmDMA_IF_E_N_STM_BASE 0x7FFE461000ull +#define DMA_IF_E_N_STM_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_STM_SECTION 0x1000 +#define mmDMA_IF_E_N_CTI_BASE 0x7FFE462000ull +#define DMA_IF_E_N_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_CTI_SECTION 0x1000 +#define mmDMA_IF_E_N_ETF_BASE 0x7FFE463000ull +#define DMA_IF_E_N_ETF_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_ETF_SECTION 0x2000 +#define mmDMA_IF_E_N_BMON0_CTI_BASE 0x7FFE465000ull +#define DMA_IF_E_N_BMON0_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_BMON0_CTI_SECTION 0x1000 +#define mmDMA_IF_E_N_BMON1_CTI_BASE 0x7FFE466000ull +#define DMA_IF_E_N_BMON1_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_BMON1_CTI_SECTION 0x1000 +#define mmDMA_IF_E_N_HBM0_WR_BMON_BASE 0x7FFE467000ull +#define DMA_IF_E_N_HBM0_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_HBM0_WR_BMON_SECTION 0x1000 +#define mmDMA_IF_E_N_HBM0_RD_BMON_BASE 0x7FFE468000ull +#define DMA_IF_E_N_HBM0_RD_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_HBM0_RD_BMON_SECTION 0x1000 +#define mmDMA_IF_E_N_HBM1_WR_BMON_BASE 0x7FFE469000ull +#define DMA_IF_E_N_HBM1_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_HBM1_WR_BMON_SECTION 0x1000 +#define mmDMA_IF_E_N_HBM1_RD_BMON_BASE 0x7FFE46A000ull +#define DMA_IF_E_N_HBM1_RD_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_HBM1_RD_BMON_SECTION 0x1000 +#define mmDMA_IF_E_N_SOB_WR_BMON_BASE 0x7FFE46B000ull +#define DMA_IF_E_N_SOB_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_SOB_WR_BMON_SECTION 0x4000 +#define mmDMA_IF_E_N_FUNNEL_BASE 0x7FFE46F000ull +#define DMA_IF_E_N_FUNNEL_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_FUNNEL_SECTION 0x11000 +#define mmCPU_ROM_TABLE_BASE 0x7FFE480000ull +#define CPU_ROM_TABLE_MAX_OFFSET 0x1000 +#define CPU_ROM_TABLE_SECTION 0x1000 +#define mmCPU_ETF_0_BASE 0x7FFE481000ull +#define CPU_ETF_0_MAX_OFFSET 0x1000 +#define CPU_ETF_0_SECTION 0x1000 +#define mmCPU_ETF_1_BASE 0x7FFE482000ull +#define CPU_ETF_1_MAX_OFFSET 0x1000 +#define CPU_ETF_1_SECTION 0x2000 +#define mmCPU_CTI_BASE 0x7FFE484000ull +#define CPU_CTI_MAX_OFFSET 0x1000 +#define CPU_CTI_SECTION 0x1000 +#define mmCPU_FUNNEL_BASE 0x7FFE485000ull +#define CPU_FUNNEL_MAX_OFFSET 0x1000 +#define CPU_FUNNEL_SECTION 0x1000 +#define mmCPU_STM_BASE 0x7FFE486000ull +#define CPU_STM_MAX_OFFSET 0x1000 +#define CPU_STM_SECTION 0x1000 +#define mmCPU_CTI_TRACE_BASE 0x7FFE487000ull +#define CPU_CTI_TRACE_MAX_OFFSET 0x1000 +#define CPU_CTI_TRACE_SECTION 0x1000 +#define mmCPU_ETF_TRACE_BASE 0x7FFE488000ull +#define CPU_ETF_TRACE_MAX_OFFSET 0x1000 +#define CPU_ETF_TRACE_SECTION 0x1000 +#define mmCPU_WR_BMON_BASE 0x7FFE489000ull +#define CPU_WR_BMON_MAX_OFFSET 0x1000 +#define CPU_WR_BMON_SECTION 0x1000 +#define mmCPU_RD_BMON_BASE 0x7FFE48A000ull +#define CPU_RD_BMON_MAX_OFFSET 0x1000 +#define CPU_RD_BMON_SECTION 0x76000 +#define mmDMA_ROM_TABLE_BASE 0x7FFE500000ull +#define DMA_ROM_TABLE_MAX_OFFSET 0x1000 +#define DMA_ROM_TABLE_SECTION 0x1000 +#define mmDMA_CH_0_CS_STM_BASE 0x7FFE501000ull +#define DMA_CH_0_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_0_CS_STM_SECTION 0x1000 +#define mmDMA_CH_0_CS_CTI_BASE 0x7FFE502000ull +#define DMA_CH_0_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_0_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_0_CS_ETF_BASE 0x7FFE503000ull +#define DMA_CH_0_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_0_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_0_CS_SPMU_BASE 0x7FFE504000ull +#define DMA_CH_0_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_0_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_0_BMON_CTI_BASE 0x7FFE505000ull +#define DMA_CH_0_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_0_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_0_USER_CTI_BASE 0x7FFE506000ull +#define DMA_CH_0_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_0_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_0_BMON_0_BASE 0x7FFE507000ull +#define DMA_CH_0_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_0_BMON_0_SECTION 0x1000 +#define mmDMA_CH_0_BMON_1_BASE 0x7FFE508000ull +#define DMA_CH_0_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_0_BMON_1_SECTION 0x19000 +#define mmDMA_CH_1_CS_STM_BASE 0x7FFE521000ull +#define DMA_CH_1_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_1_CS_STM_SECTION 0x1000 +#define mmDMA_CH_1_CS_CTI_BASE 0x7FFE522000ull +#define DMA_CH_1_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_1_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_1_CS_ETF_BASE 0x7FFE523000ull +#define DMA_CH_1_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_1_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_1_CS_SPMU_BASE 0x7FFE524000ull +#define DMA_CH_1_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_1_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_1_BMON_CTI_BASE 0x7FFE525000ull +#define DMA_CH_1_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_1_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_1_USER_CTI_BASE 0x7FFE526000ull +#define DMA_CH_1_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_1_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_1_BMON_0_BASE 0x7FFE527000ull +#define DMA_CH_1_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_1_BMON_0_SECTION 0x1000 +#define mmDMA_CH_1_BMON_1_BASE 0x7FFE528000ull +#define DMA_CH_1_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_1_BMON_1_SECTION 0x19000 +#define mmDMA_CH_2_CS_STM_BASE 0x7FFE541000ull +#define DMA_CH_2_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_2_CS_STM_SECTION 0x1000 +#define mmDMA_CH_2_CS_CTI_BASE 0x7FFE542000ull +#define DMA_CH_2_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_2_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_2_CS_ETF_BASE 0x7FFE543000ull +#define DMA_CH_2_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_2_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_2_CS_SPMU_BASE 0x7FFE544000ull +#define DMA_CH_2_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_2_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_2_BMON_CTI_BASE 0x7FFE545000ull +#define DMA_CH_2_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_2_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_2_USER_CTI_BASE 0x7FFE546000ull +#define DMA_CH_2_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_2_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_2_BMON_0_BASE 0x7FFE547000ull +#define DMA_CH_2_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_2_BMON_0_SECTION 0x1000 +#define mmDMA_CH_2_BMON_1_BASE 0x7FFE548000ull +#define DMA_CH_2_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_2_BMON_1_SECTION 0x19000 +#define mmDMA_CH_3_CS_STM_BASE 0x7FFE561000ull +#define DMA_CH_3_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_3_CS_STM_SECTION 0x1000 +#define mmDMA_CH_3_CS_CTI_BASE 0x7FFE562000ull +#define DMA_CH_3_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_3_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_3_CS_ETF_BASE 0x7FFE563000ull +#define DMA_CH_3_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_3_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_3_CS_SPMU_BASE 0x7FFE564000ull +#define DMA_CH_3_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_3_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_3_BMON_CTI_BASE 0x7FFE565000ull +#define DMA_CH_3_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_3_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_3_USER_CTI_BASE 0x7FFE566000ull +#define DMA_CH_3_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_3_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_3_BMON_0_BASE 0x7FFE567000ull +#define DMA_CH_3_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_3_BMON_0_SECTION 0x1000 +#define mmDMA_CH_3_BMON_1_BASE 0x7FFE568000ull +#define DMA_CH_3_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_3_BMON_1_SECTION 0x19000 +#define mmDMA_CH_4_CS_STM_BASE 0x7FFE581000ull +#define DMA_CH_4_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_4_CS_STM_SECTION 0x1000 +#define mmDMA_CH_4_CS_CTI_BASE 0x7FFE582000ull +#define DMA_CH_4_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_4_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_4_CS_ETF_BASE 0x7FFE583000ull +#define DMA_CH_4_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_4_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_4_CS_SPMU_BASE 0x7FFE584000ull +#define DMA_CH_4_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_4_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_4_BMON_CTI_BASE 0x7FFE585000ull +#define DMA_CH_4_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_4_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_4_USER_CTI_BASE 0x7FFE586000ull +#define DMA_CH_4_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_4_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_4_BMON_0_BASE 0x7FFE587000ull +#define DMA_CH_4_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_4_BMON_0_SECTION 0x1000 +#define mmDMA_CH_4_BMON_1_BASE 0x7FFE588000ull +#define DMA_CH_4_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_4_BMON_1_SECTION 0x19000 +#define mmDMA_CH_5_CS_STM_BASE 0x7FFE5A1000ull +#define DMA_CH_5_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_5_CS_STM_SECTION 0x1000 +#define mmDMA_CH_5_CS_CTI_BASE 0x7FFE5A2000ull +#define DMA_CH_5_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_5_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_5_CS_ETF_BASE 0x7FFE5A3000ull +#define DMA_CH_5_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_5_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_5_CS_SPMU_BASE 0x7FFE5A4000ull +#define DMA_CH_5_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_5_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_5_BMON_CTI_BASE 0x7FFE5A5000ull +#define DMA_CH_5_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_5_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_5_USER_CTI_BASE 0x7FFE5A6000ull +#define DMA_CH_5_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_5_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_5_BMON_0_BASE 0x7FFE5A7000ull +#define DMA_CH_5_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_5_BMON_0_SECTION 0x1000 +#define mmDMA_CH_5_BMON_1_BASE 0x7FFE5A8000ull +#define DMA_CH_5_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_5_BMON_1_SECTION 0x19000 +#define mmDMA_CH_6_CS_STM_BASE 0x7FFE5C1000ull +#define DMA_CH_6_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_6_CS_STM_SECTION 0x1000 +#define mmDMA_CH_6_CS_CTI_BASE 0x7FFE5C2000ull +#define DMA_CH_6_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_6_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_6_CS_ETF_BASE 0x7FFE5C3000ull +#define DMA_CH_6_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_6_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_6_CS_SPMU_BASE 0x7FFE5C4000ull +#define DMA_CH_6_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_6_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_6_BMON_CTI_BASE 0x7FFE5C5000ull +#define DMA_CH_6_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_6_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_6_USER_CTI_BASE 0x7FFE5C6000ull +#define DMA_CH_6_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_6_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_6_BMON_0_BASE 0x7FFE5C7000ull +#define DMA_CH_6_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_6_BMON_0_SECTION 0x1000 +#define mmDMA_CH_6_BMON_1_BASE 0x7FFE5C8000ull +#define DMA_CH_6_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_6_BMON_1_SECTION 0x19000 +#define mmDMA_CH_7_CS_STM_BASE 0x7FFE5E1000ull +#define DMA_CH_7_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_7_CS_STM_SECTION 0x1000 +#define mmDMA_CH_7_CS_CTI_BASE 0x7FFE5E2000ull +#define DMA_CH_7_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_7_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_7_CS_ETF_BASE 0x7FFE5E3000ull +#define DMA_CH_7_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_7_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_7_CS_SPMU_BASE 0x7FFE5E4000ull +#define DMA_CH_7_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_7_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_7_BMON_CTI_BASE 0x7FFE5E5000ull +#define DMA_CH_7_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_7_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_7_USER_CTI_BASE 0x7FFE5E6000ull +#define DMA_CH_7_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_7_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_7_BMON_0_BASE 0x7FFE5E7000ull +#define DMA_CH_7_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_7_BMON_0_SECTION 0x1000 +#define mmDMA_CH_7_BMON_1_BASE 0x7FFE5E8000ull +#define DMA_CH_7_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_7_BMON_1_SECTION 0x18000 +#define mmNIC_TPC_FUNNEL_W_S_BASE 0x7FFE600000ull +#define NIC_TPC_FUNNEL_W_S_MAX_OFFSET 0x1000 +#define NIC_TPC_FUNNEL_W_S_SECTION 0x80000 +#define mmNIC_TPC_FUNNEL_E_S_BASE 0x7FFE680000ull +#define NIC_TPC_FUNNEL_E_S_MAX_OFFSET 0x1000 +#define NIC_TPC_FUNNEL_E_S_SECTION 0x80000 +#define mmNIC_TPC_FUNNEL_W_N_BASE 0x7FFE700000ull +#define NIC_TPC_FUNNEL_W_N_MAX_OFFSET 0x1000 +#define NIC_TPC_FUNNEL_W_N_SECTION 0x80000 +#define mmNIC_TPC_FUNNEL_E_N_BASE 0x7FFE780000ull +#define NIC_TPC_FUNNEL_E_N_MAX_OFFSET 0x1000 +#define NIC_TPC_FUNNEL_E_N_SECTION 0x80000 +#define mmCA53_BASE 0x7FFE800000ull +#define CA53_MAX_OFFSET 0x141000 +#define CA53_SECTION 0x400000 +#define mmPCI_ROM_TABLE_BASE 0x7FFEC00000ull +#define PCI_ROM_TABLE_MAX_OFFSET 0x1000 +#define PCI_ROM_TABLE_SECTION 0x1000 +#define mmPCIE_STM_BASE 0x7FFEC01000ull +#define PCIE_STM_MAX_OFFSET 0x1000 +#define PCIE_STM_SECTION 0x1000 +#define mmPCIE_ETF_BASE 0x7FFEC02000ull +#define PCIE_ETF_MAX_OFFSET 0x1000 +#define PCIE_ETF_SECTION 0x1000 +#define mmPCIE_CTI_0_BASE 0x7FFEC03000ull +#define PCIE_CTI_0_MAX_OFFSET 0x1000 +#define PCIE_CTI_0_SECTION 0x1000 +#define mmPCIE_SPMU_BASE 0x7FFEC04000ull +#define PCIE_SPMU_MAX_OFFSET 0x1000 +#define PCIE_SPMU_SECTION 0x1000 +#define mmPCIE_CTI_1_BASE 0x7FFEC05000ull +#define PCIE_CTI_1_MAX_OFFSET 0x1000 +#define PCIE_CTI_1_SECTION 0x1000 +#define mmPCIE_FUNNEL_BASE 0x7FFEC06000ull +#define PCIE_FUNNEL_MAX_OFFSET 0x1000 +#define PCIE_FUNNEL_SECTION 0x1000 +#define mmPCIE_BMON_MSTR_WR_BASE 0x7FFEC07000ull +#define PCIE_BMON_MSTR_WR_MAX_OFFSET 0x1000 +#define PCIE_BMON_MSTR_WR_SECTION 0x1000 +#define mmPCIE_BMON_MSTR_RD_BASE 0x7FFEC08000ull +#define PCIE_BMON_MSTR_RD_MAX_OFFSET 0x1000 +#define PCIE_BMON_MSTR_RD_SECTION 0x1000 +#define mmPCIE_BMON_SLV_WR_BASE 0x7FFEC09000ull +#define PCIE_BMON_SLV_WR_MAX_OFFSET 0x1000 +#define PCIE_BMON_SLV_WR_SECTION 0x1000 +#define mmPCIE_BMON_SLV_RD_BASE 0x7FFEC0A000ull +#define PCIE_BMON_SLV_RD_MAX_OFFSET 0x1000 +#define PCIE_BMON_SLV_RD_SECTION 0x7000 +#define mmMMU_CS_STM_BASE 0x7FFEC11000ull +#define MMU_CS_STM_MAX_OFFSET 0x1000 +#define MMU_CS_STM_SECTION 0x1000 +#define mmMMU_CS_CTI_BASE 0x7FFEC12000ull +#define MMU_CS_CTI_MAX_OFFSET 0x1000 +#define MMU_CS_CTI_SECTION 0x1000 +#define mmMMU_CS_ETF_BASE 0x7FFEC13000ull +#define MMU_CS_ETF_MAX_OFFSET 0x1000 +#define MMU_CS_ETF_SECTION 0x1000 +#define mmMMU_CS_SPMU_BASE 0x7FFEC14000ull +#define MMU_CS_SPMU_MAX_OFFSET 0x1000 +#define MMU_CS_SPMU_SECTION 0x1000 +#define mmMMU_BMON_CTI_BASE 0x7FFEC15000ull +#define MMU_BMON_CTI_MAX_OFFSET 0x1000 +#define MMU_BMON_CTI_SECTION 0x1000 +#define mmMMU_USER_CTI_BASE 0x7FFEC16000ull +#define MMU_USER_CTI_MAX_OFFSET 0x1000 +#define MMU_USER_CTI_SECTION 0x1000 +#define mmMMU_BMON_0_BASE 0x7FFEC17000ull +#define MMU_BMON_0_MAX_OFFSET 0x1000 +#define MMU_BMON_0_SECTION 0x1000 +#define mmMMU_BMON_1_BASE 0x7FFEC18000ull +#define MMU_BMON_1_MAX_OFFSET 0x1000 +#define MMU_BMON_1_SECTION 0x28000 +#define mmPSOC_CTI_BASE 0x7FFEC40000ull +#define PSOC_CTI_MAX_OFFSET 0x1000 +#define PSOC_CTI_SECTION 0x1000 +#define mmPSOC_STM_BASE 0x7FFEC41000ull +#define PSOC_STM_MAX_OFFSET 0x1000 +#define PSOC_STM_SECTION 0x1000 +#define mmPSOC_FUNNEL_BASE 0x7FFEC42000ull +#define PSOC_FUNNEL_MAX_OFFSET 0x1000 +#define PSOC_FUNNEL_SECTION 0x1000 +#define mmPSOC_ETR_BASE 0x7FFEC43000ull +#define PSOC_ETR_MAX_OFFSET 0x1000 +#define PSOC_ETR_SECTION 0x1000 +#define mmPSOC_ETF_BASE 0x7FFEC44000ull +#define PSOC_ETF_MAX_OFFSET 0x1000 +#define PSOC_ETF_SECTION 0x1000 +#define mmPSOC_TS_CTI_BASE 0x7FFEC45000ull +#define PSOC_TS_CTI_MAX_OFFSET 0x1000 +#define PSOC_TS_CTI_SECTION 0xB000 +#define mmTOP_ROM_TABLE_BASE 0x7FFEC50000ull +#define TOP_ROM_TABLE_MAX_OFFSET 0x1000 +#define TOP_ROM_TABLE_SECTION 0x70000 +#define mmNIC0_ROM_TABLE_BASE 0x7FFECC0000ull +#define NIC0_ROM_TABLE_MAX_OFFSET 0x1000 +#define NIC0_ROM_TABLE_SECTION 0x1000 +#define mmSTM_0_NIC0_DBG_BASE 0x7FFECC1000ull +#define STM_0_NIC0_DBG_MAX_OFFSET 0x21000 +#define STM_0_NIC0_DBG_SECTION 0x1000 +#define mmCTI_0_NIC0_DBG_BASE 0x7FFECC2000ull +#define CTI_0_NIC0_DBG_MAX_OFFSET 0x1000 +#define CTI_0_NIC0_DBG_SECTION 0x1000 +#define mmETF_0_NIC0_DBG_BASE 0x7FFECC3000ull +#define ETF_0_NIC0_DBG_MAX_OFFSET 0x1000 +#define ETF_0_NIC0_DBG_SECTION 0x1000 +#define mmSPMU_0_NIC0_DBG_BASE 0x7FFECC4000ull +#define SPMU_0_NIC0_DBG_MAX_OFFSET 0x1000 +#define SPMU_0_NIC0_DBG_SECTION 0x2000 +#define mmUSER_CTI_0_NIC0_DBG_BASE 0x7FFECC6000ull +#define USER_CTI_0_NIC0_DBG_MAX_OFFSET 0x1000 +#define USER_CTI_0_NIC0_DBG_SECTION 0xB000 +#define mmSTM_1_NIC0_DBG_BASE 0x7FFECD1000ull +#define STM_1_NIC0_DBG_MAX_OFFSET 0x1000 +#define STM_1_NIC0_DBG_SECTION 0x1000 +#define mmCTI_1_NIC0_DBG_BASE 0x7FFECD2000ull +#define CTI_1_NIC0_DBG_MAX_OFFSET 0x1000 +#define CTI_1_NIC0_DBG_SECTION 0x1000 +#define mmETF_1_NIC0_DBG_BASE 0x7FFECD3000ull +#define ETF_1_NIC0_DBG_MAX_OFFSET 0x1000 +#define ETF_1_NIC0_DBG_SECTION 0x1000 +#define mmSPMU_1_NIC0_DBG_BASE 0x7FFECD4000ull +#define SPMU_1_NIC0_DBG_MAX_OFFSET 0x1000 +#define SPMU_1_NIC0_DBG_SECTION 0x1000 +#define mmBMON_CTI_NIC0_DBG_BASE 0x7FFECD5000ull +#define BMON_CTI_NIC0_DBG_MAX_OFFSET 0x1000 +#define BMON_CTI_NIC0_DBG_SECTION 0x1000 +#define mmUSER_CTI_1_NIC0_DBG_BASE 0x7FFECD6000ull +#define USER_CTI_1_NIC0_DBG_MAX_OFFSET 0x1000 +#define USER_CTI_1_NIC0_DBG_SECTION 0x1000 +#define mmBMON0_NIC0_DBG_BASE 0x7FFECD7000ull +#define BMON0_NIC0_DBG_MAX_OFFSET 0x1000 +#define BMON0_NIC0_DBG_SECTION 0x1000 +#define mmBMON1_NIC0_DBG_BASE 0x7FFECD8000ull +#define BMON1_NIC0_DBG_MAX_OFFSET 0x1000 +#define BMON1_NIC0_DBG_SECTION 0x1000 +#define mmBMON2_NIC0_DBG_BASE 0x7FFECD9000ull +#define BMON2_NIC0_DBG_MAX_OFFSET 0x1000 +#define BMON2_NIC0_DBG_SECTION 0x1000 +#define mmBMON3_NIC0_DBG_BASE 0x7FFECDA000ull +#define BMON3_NIC0_DBG_MAX_OFFSET 0x1000 +#define BMON3_NIC0_DBG_SECTION 0x1000 +#define mmBMON4_NIC0_DBG_BASE 0x7FFECDB000ull +#define BMON4_NIC0_DBG_MAX_OFFSET 0x1000 +#define BMON4_NIC0_DBG_SECTION 0x6000 +#define mmFUNNEL_NIC0_DBG_BASE 0x7FFECE1000ull +#define FUNNEL_NIC0_DBG_MAX_OFFSET 0x1000 +#define FUNNEL_NIC0_DBG_SECTION 0x1F000 +#define mmNIC1_ROM_TABLE_BASE 0x7FFED00000ull +#define NIC1_ROM_TABLE_MAX_OFFSET 0x1000 +#define NIC1_ROM_TABLE_SECTION 0x1000 +#define mmSTM_0_NIC1_DBG_BASE 0x7FFED01000ull +#define STM_0_NIC1_DBG_MAX_OFFSET 0x21000 +#define STM_0_NIC1_DBG_SECTION 0x1000 +#define mmCTI_0_NIC1_DBG_BASE 0x7FFED02000ull +#define CTI_0_NIC1_DBG_MAX_OFFSET 0x1000 +#define CTI_0_NIC1_DBG_SECTION 0x1000 +#define mmETF_0_NIC1_DBG_BASE 0x7FFED03000ull +#define ETF_0_NIC1_DBG_MAX_OFFSET 0x1000 +#define ETF_0_NIC1_DBG_SECTION 0x1000 +#define mmSPMU_0_NIC1_DBG_BASE 0x7FFED04000ull +#define SPMU_0_NIC1_DBG_MAX_OFFSET 0x1000 +#define SPMU_0_NIC1_DBG_SECTION 0x2000 +#define mmUSER_CTI_0_NIC1_DBG_BASE 0x7FFED06000ull +#define USER_CTI_0_NIC1_DBG_MAX_OFFSET 0x1000 +#define USER_CTI_0_NIC1_DBG_SECTION 0xB000 +#define mmSTM_1_NIC1_DBG_BASE 0x7FFED11000ull +#define STM_1_NIC1_DBG_MAX_OFFSET 0x1000 +#define STM_1_NIC1_DBG_SECTION 0x1000 +#define mmCTI_1_NIC1_DBG_BASE 0x7FFED12000ull +#define CTI_1_NIC1_DBG_MAX_OFFSET 0x1000 +#define CTI_1_NIC1_DBG_SECTION 0x1000 +#define mmETF_1_NIC1_DBG_BASE 0x7FFED13000ull +#define ETF_1_NIC1_DBG_MAX_OFFSET 0x1000 +#define ETF_1_NIC1_DBG_SECTION 0x1000 +#define mmSPMU_1_NIC1_DBG_BASE 0x7FFED14000ull +#define SPMU_1_NIC1_DBG_MAX_OFFSET 0x1000 +#define SPMU_1_NIC1_DBG_SECTION 0x1000 +#define mmBMON_CTI_NIC1_DBG_BASE 0x7FFED15000ull +#define BMON_CTI_NIC1_DBG_MAX_OFFSET 0x1000 +#define BMON_CTI_NIC1_DBG_SECTION 0x1000 +#define mmUSER_CTI_1_NIC1_DBG_BASE 0x7FFED16000ull +#define USER_CTI_1_NIC1_DBG_MAX_OFFSET 0x1000 +#define USER_CTI_1_NIC1_DBG_SECTION 0x1000 +#define mmBMON0_NIC1_DBG_BASE 0x7FFED17000ull +#define BMON0_NIC1_DBG_MAX_OFFSET 0x1000 +#define BMON0_NIC1_DBG_SECTION 0x1000 +#define mmBMON1_NIC1_DBG_BASE 0x7FFED18000ull +#define BMON1_NIC1_DBG_MAX_OFFSET 0x1000 +#define BMON1_NIC1_DBG_SECTION 0x1000 +#define mmBMON2_NIC1_DBG_BASE 0x7FFED19000ull +#define BMON2_NIC1_DBG_MAX_OFFSET 0x1000 +#define BMON2_NIC1_DBG_SECTION 0x1000 +#define mmBMON3_NIC1_DBG_BASE 0x7FFED1A000ull +#define BMON3_NIC1_DBG_MAX_OFFSET 0x1000 +#define BMON3_NIC1_DBG_SECTION 0x1000 +#define mmBMON4_NIC1_DBG_BASE 0x7FFED1B000ull +#define BMON4_NIC1_DBG_MAX_OFFSET 0x1000 +#define BMON4_NIC1_DBG_SECTION 0x6000 +#define mmFUNNEL_NIC1_DBG_BASE 0x7FFED21000ull +#define FUNNEL_NIC1_DBG_MAX_OFFSET 0x1000 +#define FUNNEL_NIC1_DBG_SECTION 0x1F000 +#define mmNIC2_ROM_TABLE_BASE 0x7FFED40000ull +#define NIC2_ROM_TABLE_MAX_OFFSET 0x1000 +#define NIC2_ROM_TABLE_SECTION 0x1000 +#define mmSTM_0_NIC2_DBG_BASE 0x7FFED41000ull +#define STM_0_NIC2_DBG_MAX_OFFSET 0x21000 +#define STM_0_NIC2_DBG_SECTION 0x1000 +#define mmCTI_0_NIC2_DBG_BASE 0x7FFED42000ull +#define CTI_0_NIC2_DBG_MAX_OFFSET 0x1000 +#define CTI_0_NIC2_DBG_SECTION 0x1000 +#define mmETF_0_NIC2_DBG_BASE 0x7FFED43000ull +#define ETF_0_NIC2_DBG_MAX_OFFSET 0x1000 +#define ETF_0_NIC2_DBG_SECTION 0x1000 +#define mmSPMU_0_NIC2_DBG_BASE 0x7FFED44000ull +#define SPMU_0_NIC2_DBG_MAX_OFFSET 0x1000 +#define SPMU_0_NIC2_DBG_SECTION 0x2000 +#define mmUSER_CTI_0_NIC2_DBG_BASE 0x7FFED46000ull +#define USER_CTI_0_NIC2_DBG_MAX_OFFSET 0x1000 +#define USER_CTI_0_NIC2_DBG_SECTION 0xB000 +#define mmSTM_1_NIC2_DBG_BASE 0x7FFED51000ull +#define STM_1_NIC2_DBG_MAX_OFFSET 0x1000 +#define STM_1_NIC2_DBG_SECTION 0x1000 +#define mmCTI_1_NIC2_DBG_BASE 0x7FFED52000ull +#define CTI_1_NIC2_DBG_MAX_OFFSET 0x1000 +#define CTI_1_NIC2_DBG_SECTION 0x1000 +#define mmETF_1_NIC2_DBG_BASE 0x7FFED53000ull +#define ETF_1_NIC2_DBG_MAX_OFFSET 0x1000 +#define ETF_1_NIC2_DBG_SECTION 0x1000 +#define mmSPMU_1_NIC2_DBG_BASE 0x7FFED54000ull +#define SPMU_1_NIC2_DBG_MAX_OFFSET 0x1000 +#define SPMU_1_NIC2_DBG_SECTION 0x1000 +#define mmBMON_CTI_NIC2_DBG_BASE 0x7FFED55000ull +#define BMON_CTI_NIC2_DBG_MAX_OFFSET 0x1000 +#define BMON_CTI_NIC2_DBG_SECTION 0x1000 +#define mmUSER_CTI_1_NIC2_DBG_BASE 0x7FFED56000ull +#define USER_CTI_1_NIC2_DBG_MAX_OFFSET 0x1000 +#define USER_CTI_1_NIC2_DBG_SECTION 0x1000 +#define mmBMON0_NIC2_DBG_BASE 0x7FFED57000ull +#define BMON0_NIC2_DBG_MAX_OFFSET 0x1000 +#define BMON0_NIC2_DBG_SECTION 0x1000 +#define mmBMON1_NIC2_DBG_BASE 0x7FFED58000ull +#define BMON1_NIC2_DBG_MAX_OFFSET 0x1000 +#define BMON1_NIC2_DBG_SECTION 0x1000 +#define mmBMON2_NIC2_DBG_BASE 0x7FFED59000ull +#define BMON2_NIC2_DBG_MAX_OFFSET 0x1000 +#define BMON2_NIC2_DBG_SECTION 0x1000 +#define mmBMON3_NIC2_DBG_BASE 0x7FFED5A000ull +#define BMON3_NIC2_DBG_MAX_OFFSET 0x1000 +#define BMON3_NIC2_DBG_SECTION 0x1000 +#define mmBMON4_NIC2_DBG_BASE 0x7FFED5B000ull +#define BMON4_NIC2_DBG_MAX_OFFSET 0x1000 +#define BMON4_NIC2_DBG_SECTION 0x6000 +#define mmFUNNEL_NIC2_DBG_BASE 0x7FFED61000ull +#define FUNNEL_NIC2_DBG_MAX_OFFSET 0x1000 +#define FUNNEL_NIC2_DBG_SECTION 0x1F000 +#define mmNIC3_ROM_TABLE_BASE 0x7FFED80000ull +#define NIC3_ROM_TABLE_MAX_OFFSET 0x1000 +#define NIC3_ROM_TABLE_SECTION 0x1000 +#define mmSTM_0_NIC3_DBG_BASE 0x7FFED81000ull +#define STM_0_NIC3_DBG_MAX_OFFSET 0x21000 +#define STM_0_NIC3_DBG_SECTION 0x1000 +#define mmCTI_0_NIC3_DBG_BASE 0x7FFED82000ull +#define CTI_0_NIC3_DBG_MAX_OFFSET 0x1000 +#define CTI_0_NIC3_DBG_SECTION 0x1000 +#define mmETF_0_NIC3_DBG_BASE 0x7FFED83000ull +#define ETF_0_NIC3_DBG_MAX_OFFSET 0x1000 +#define ETF_0_NIC3_DBG_SECTION 0x1000 +#define mmSPMU_0_NIC3_DBG_BASE 0x7FFED84000ull +#define SPMU_0_NIC3_DBG_MAX_OFFSET 0x1000 +#define SPMU_0_NIC3_DBG_SECTION 0x2000 +#define mmUSER_CTI_0_NIC3_DBG_BASE 0x7FFED86000ull +#define USER_CTI_0_NIC3_DBG_MAX_OFFSET 0x1000 +#define USER_CTI_0_NIC3_DBG_SECTION 0xB000 +#define mmSTM_1_NIC3_DBG_BASE 0x7FFED91000ull +#define STM_1_NIC3_DBG_MAX_OFFSET 0x1000 +#define STM_1_NIC3_DBG_SECTION 0x1000 +#define mmCTI_1_NIC3_DBG_BASE 0x7FFED92000ull +#define CTI_1_NIC3_DBG_MAX_OFFSET 0x1000 +#define CTI_1_NIC3_DBG_SECTION 0x1000 +#define mmETF_1_NIC3_DBG_BASE 0x7FFED93000ull +#define ETF_1_NIC3_DBG_MAX_OFFSET 0x1000 +#define ETF_1_NIC3_DBG_SECTION 0x1000 +#define mmSPMU_1_NIC3_DBG_BASE 0x7FFED94000ull +#define SPMU_1_NIC3_DBG_MAX_OFFSET 0x1000 +#define SPMU_1_NIC3_DBG_SECTION 0x1000 +#define mmBMON_CTI_NIC3_DBG_BASE 0x7FFED95000ull +#define BMON_CTI_NIC3_DBG_MAX_OFFSET 0x1000 +#define BMON_CTI_NIC3_DBG_SECTION 0x1000 +#define mmUSER_CTI_1_NIC3_DBG_BASE 0x7FFED96000ull +#define USER_CTI_1_NIC3_DBG_MAX_OFFSET 0x1000 +#define USER_CTI_1_NIC3_DBG_SECTION 0x1000 +#define mmBMON0_NIC3_DBG_BASE 0x7FFED97000ull +#define BMON0_NIC3_DBG_MAX_OFFSET 0x1000 +#define BMON0_NIC3_DBG_SECTION 0x1000 +#define mmBMON1_NIC3_DBG_BASE 0x7FFED98000ull +#define BMON1_NIC3_DBG_MAX_OFFSET 0x1000 +#define BMON1_NIC3_DBG_SECTION 0x1000 +#define mmBMON2_NIC3_DBG_BASE 0x7FFED99000ull +#define BMON2_NIC3_DBG_MAX_OFFSET 0x1000 +#define BMON2_NIC3_DBG_SECTION 0x1000 +#define mmBMON3_NIC3_DBG_BASE 0x7FFED9A000ull +#define BMON3_NIC3_DBG_MAX_OFFSET 0x1000 +#define BMON3_NIC3_DBG_SECTION 0x1000 +#define mmBMON4_NIC3_DBG_BASE 0x7FFED9B000ull +#define BMON4_NIC3_DBG_MAX_OFFSET 0x1000 +#define BMON4_NIC3_DBG_SECTION 0x6000 +#define mmFUNNEL_NIC3_DBG_BASE 0x7FFEDA1000ull +#define FUNNEL_NIC3_DBG_MAX_OFFSET 0x1000 +#define FUNNEL_NIC3_DBG_SECTION 0x1F000 +#define mmNIC4_ROM_TABLE_BASE 0x7FFEDC0000ull +#define NIC4_ROM_TABLE_MAX_OFFSET 0x1000 +#define NIC4_ROM_TABLE_SECTION 0x1000 +#define mmSTM_0_NIC4_DBG_BASE 0x7FFEDC1000ull +#define STM_0_NIC4_DBG_MAX_OFFSET 0x21000 +#define STM_0_NIC4_DBG_SECTION 0x1000 +#define mmCTI_0_NIC4_DBG_BASE 0x7FFEDC2000ull +#define CTI_0_NIC4_DBG_MAX_OFFSET 0x1000 +#define CTI_0_NIC4_DBG_SECTION 0x1000 +#define mmETF_0_NIC4_DBG_BASE 0x7FFEDC3000ull +#define ETF_0_NIC4_DBG_MAX_OFFSET 0x1000 +#define ETF_0_NIC4_DBG_SECTION 0x1000 +#define mmSPMU_0_NIC4_DBG_BASE 0x7FFEDC4000ull +#define SPMU_0_NIC4_DBG_MAX_OFFSET 0x1000 +#define SPMU_0_NIC4_DBG_SECTION 0x2000 +#define mmUSER_CTI_0_NIC4_DBG_BASE 0x7FFEDC6000ull +#define USER_CTI_0_NIC4_DBG_MAX_OFFSET 0x1000 +#define USER_CTI_0_NIC4_DBG_SECTION 0xB000 +#define mmSTM_1_NIC4_DBG_BASE 0x7FFEDD1000ull +#define STM_1_NIC4_DBG_MAX_OFFSET 0x1000 +#define STM_1_NIC4_DBG_SECTION 0x1000 +#define mmCTI_1_NIC4_DBG_BASE 0x7FFEDD2000ull +#define CTI_1_NIC4_DBG_MAX_OFFSET 0x1000 +#define CTI_1_NIC4_DBG_SECTION 0x1000 +#define mmETF_1_NIC4_DBG_BASE 0x7FFEDD3000ull +#define ETF_1_NIC4_DBG_MAX_OFFSET 0x1000 +#define ETF_1_NIC4_DBG_SECTION 0x1000 +#define mmSPMU_1_NIC4_DBG_BASE 0x7FFEDD4000ull +#define SPMU_1_NIC4_DBG_MAX_OFFSET 0x1000 +#define SPMU_1_NIC4_DBG_SECTION 0x1000 +#define mmBMON_CTI_NIC4_DBG_BASE 0x7FFEDD5000ull +#define BMON_CTI_NIC4_DBG_MAX_OFFSET 0x1000 +#define BMON_CTI_NIC4_DBG_SECTION 0x1000 +#define mmUSER_CTI_1_NIC4_DBG_BASE 0x7FFEDD6000ull +#define USER_CTI_1_NIC4_DBG_MAX_OFFSET 0x1000 +#define USER_CTI_1_NIC4_DBG_SECTION 0x1000 +#define mmBMON0_NIC4_DBG_BASE 0x7FFEDD7000ull +#define BMON0_NIC4_DBG_MAX_OFFSET 0x1000 +#define BMON0_NIC4_DBG_SECTION 0x1000 +#define mmBMON1_NIC4_DBG_BASE 0x7FFEDD8000ull +#define BMON1_NIC4_DBG_MAX_OFFSET 0x1000 +#define BMON1_NIC4_DBG_SECTION 0x1000 +#define mmBMON2_NIC4_DBG_BASE 0x7FFEDD9000ull +#define BMON2_NIC4_DBG_MAX_OFFSET 0x1000 +#define BMON2_NIC4_DBG_SECTION 0x1000 +#define mmBMON3_NIC4_DBG_BASE 0x7FFEDDA000ull +#define BMON3_NIC4_DBG_MAX_OFFSET 0x1000 +#define BMON3_NIC4_DBG_SECTION 0x1000 +#define mmBMON4_NIC4_DBG_BASE 0x7FFEDDB000ull +#define BMON4_NIC4_DBG_MAX_OFFSET 0x1000 +#define BMON4_NIC4_DBG_SECTION 0x6000 +#define mmFUNNEL_NIC4_DBG_BASE 0x7FFEDE1000ull +#define FUNNEL_NIC4_DBG_MAX_OFFSET 0x1000 +#define FUNNEL_NIC4_DBG_SECTION 0x21F000 +#define mmTPC0_ROM_TABLE_BASE 0x7FFF000000ull +#define TPC0_ROM_TABLE_MAX_OFFSET 0x1000 +#define TPC0_ROM_TABLE_SECTION 0x1000 +#define mmTPC0_EML_SPMU_BASE 0x7FFF001000ull +#define TPC0_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC0_EML_SPMU_SECTION 0x1000 +#define mmTPC0_EML_ETF_BASE 0x7FFF002000ull +#define TPC0_EML_ETF_MAX_OFFSET 0x1000 +#define TPC0_EML_ETF_SECTION 0x1000 +#define mmTPC0_EML_STM_BASE 0x7FFF003000ull +#define TPC0_EML_STM_MAX_OFFSET 0x1000 +#define TPC0_EML_STM_SECTION 0x2000 +#define mmTPC0_EML_CTI_BASE 0x7FFF005000ull +#define TPC0_EML_CTI_MAX_OFFSET 0x1000 +#define TPC0_EML_CTI_SECTION 0x1000 +#define mmTPC0_EML_FUNNEL_BASE 0x7FFF006000ull +#define TPC0_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC0_EML_FUNNEL_SECTION 0x1000 +#define mmTPC0_EML_BUSMON_0_BASE 0x7FFF007000ull +#define TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC0_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC0_EML_BUSMON_1_BASE 0x7FFF008000ull +#define TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC0_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC0_EML_BUSMON_2_BASE 0x7FFF009000ull +#define TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC0_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC0_EML_BUSMON_3_BASE 0x7FFF00A000ull +#define TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC0_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC0_EML_CFG_BASE 0x7FFF040000ull +#define TPC0_EML_CFG_MAX_OFFSET 0x3380 +#define TPC0_EML_CFG_SECTION 0x1000 +#define mmTPC0_EML_TPC_CFG_BASE 0x7FFF041000ull +#define TPC0_EML_TPC_CFG_MAX_OFFSET 0xE400 +#define TPC0_EML_TPC_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC0_EML_TPC_CFG_BASE 0x7FFF041400ull +#define KERNEL_TENSOR_0_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC0_EML_TPC_CFG_BASE 0x7FFF041438ull +#define KERNEL_TENSOR_1_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC0_EML_TPC_CFG_BASE 0x7FFF041470ull +#define KERNEL_TENSOR_2_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC0_EML_TPC_CFG_BASE 0x7FFF0414A8ull +#define KERNEL_TENSOR_3_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC0_EML_TPC_CFG_BASE 0x7FFF0414E0ull +#define KERNEL_TENSOR_4_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC0_EML_TPC_CFG_BASE 0x7FFF041518ull +#define KERNEL_TENSOR_5_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC0_EML_TPC_CFG_BASE 0x7FFF041550ull +#define KERNEL_TENSOR_6_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC0_EML_TPC_CFG_BASE 0x7FFF041588ull +#define KERNEL_TENSOR_7_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC0_EML_TPC_CFG_BASE 0x7FFF0415C0ull +#define KERNEL_TENSOR_8_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC0_EML_TPC_CFG_BASE 0x7FFF0415F8ull +#define KERNEL_TENSOR_9_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC0_EML_TPC_CFG_BASE 0x7FFF041630ull +#define KERNEL_TENSOR_10_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC0_EML_TPC_CFG_BASE 0x7FFF041668ull +#define KERNEL_TENSOR_11_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC0_EML_TPC_CFG_BASE 0x7FFF0416A0ull +#define KERNEL_TENSOR_12_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC0_EML_TPC_CFG_BASE 0x7FFF0416D8ull +#define KERNEL_TENSOR_13_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC0_EML_TPC_CFG_BASE 0x7FFF041710ull +#define KERNEL_TENSOR_14_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC0_EML_TPC_CFG_BASE 0x7FFF041748ull +#define KERNEL_TENSOR_15_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC0_EML_TPC_CFG_BASE 0x7FFF041780ull +#define KERNEL_SYNC_OBJECT_TPC0_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC0_EML_TPC_CFG_SECTION 0x8000 +#define mmKERNEL_TPC0_EML_TPC_CFG_BASE 0x7FFF041788ull +#define KERNEL_TPC0_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC0_EML_TPC_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC0_EML_TPC_CFG_BASE 0x7FFF041A00ull +#define QM_TENSOR_0_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC0_EML_TPC_CFG_BASE 0x7FFF041A38ull +#define QM_TENSOR_1_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC0_EML_TPC_CFG_BASE 0x7FFF041A70ull +#define QM_TENSOR_2_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC0_EML_TPC_CFG_BASE 0x7FFF041AA8ull +#define QM_TENSOR_3_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC0_EML_TPC_CFG_BASE 0x7FFF041AE0ull +#define QM_TENSOR_4_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC0_EML_TPC_CFG_BASE 0x7FFF041B18ull +#define QM_TENSOR_5_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC0_EML_TPC_CFG_BASE 0x7FFF041B50ull +#define QM_TENSOR_6_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC0_EML_TPC_CFG_BASE 0x7FFF041B88ull +#define QM_TENSOR_7_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC0_EML_TPC_CFG_BASE 0x7FFF041BC0ull +#define QM_TENSOR_8_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC0_EML_TPC_CFG_BASE 0x7FFF041BF8ull +#define QM_TENSOR_9_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC0_EML_TPC_CFG_BASE 0x7FFF041C30ull +#define QM_TENSOR_10_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC0_EML_TPC_CFG_BASE 0x7FFF041C68ull +#define QM_TENSOR_11_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC0_EML_TPC_CFG_BASE 0x7FFF041CA0ull +#define QM_TENSOR_12_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC0_EML_TPC_CFG_BASE 0x7FFF041CD8ull +#define QM_TENSOR_13_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC0_EML_TPC_CFG_BASE 0x7FFF041D10ull +#define QM_TENSOR_14_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC0_EML_TPC_CFG_BASE 0x7FFF041D48ull +#define QM_TENSOR_15_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC0_EML_TPC_CFG_BASE 0x7FFF041D80ull +#define QM_SYNC_OBJECT_TPC0_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC0_EML_TPC_CFG_SECTION 0x8000 +#define mmQM_TPC0_EML_TPC_CFG_BASE 0x7FFF041D88ull +#define QM_TPC0_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define QM_TPC0_EML_TPC_CFG_SECTION 0x2780 +#define mmTPC0_EML_TPC_QM_BASE 0x7FFF042000ull +#define TPC0_EML_TPC_QM_MAX_OFFSET 0xD040 +#define TPC0_EML_TPC_QM_SECTION 0x1BD000 +#define mmTPC0_EML_CS_BASE 0x7FFF1FF000ull +#define TPC0_EML_CS_MAX_OFFSET 0x1000 +#define TPC0_EML_CS_SECTION 0x1000 +#define mmTPC1_ROM_TABLE_BASE 0x7FFF200000ull +#define TPC1_ROM_TABLE_MAX_OFFSET 0x1000 +#define TPC1_ROM_TABLE_SECTION 0x1000 +#define mmTPC1_EML_SPMU_BASE 0x7FFF201000ull +#define TPC1_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC1_EML_SPMU_SECTION 0x1000 +#define mmTPC1_EML_ETF_BASE 0x7FFF202000ull +#define TPC1_EML_ETF_MAX_OFFSET 0x1000 +#define TPC1_EML_ETF_SECTION 0x1000 +#define mmTPC1_EML_STM_BASE 0x7FFF203000ull +#define TPC1_EML_STM_MAX_OFFSET 0x1000 +#define TPC1_EML_STM_SECTION 0x2000 +#define mmTPC1_EML_CTI_BASE 0x7FFF205000ull +#define TPC1_EML_CTI_MAX_OFFSET 0x1000 +#define TPC1_EML_CTI_SECTION 0x1000 +#define mmTPC1_EML_FUNNEL_BASE 0x7FFF206000ull +#define TPC1_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC1_EML_FUNNEL_SECTION 0x1000 +#define mmTPC1_EML_BUSMON_0_BASE 0x7FFF207000ull +#define TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC1_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC1_EML_BUSMON_1_BASE 0x7FFF208000ull +#define TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC1_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC1_EML_BUSMON_2_BASE 0x7FFF209000ull +#define TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC1_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC1_EML_BUSMON_3_BASE 0x7FFF20A000ull +#define TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC1_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC1_EML_CFG_BASE 0x7FFF240000ull +#define TPC1_EML_CFG_MAX_OFFSET 0x3380 +#define TPC1_EML_CFG_SECTION 0x1000 +#define mmTPC1_EML_TPC_CFG_BASE 0x7FFF241000ull +#define TPC1_EML_TPC_CFG_MAX_OFFSET 0xE400 +#define TPC1_EML_TPC_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC1_EML_TPC_CFG_BASE 0x7FFF241400ull +#define KERNEL_TENSOR_0_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC1_EML_TPC_CFG_BASE 0x7FFF241438ull +#define KERNEL_TENSOR_1_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC1_EML_TPC_CFG_BASE 0x7FFF241470ull +#define KERNEL_TENSOR_2_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC1_EML_TPC_CFG_BASE 0x7FFF2414A8ull +#define KERNEL_TENSOR_3_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC1_EML_TPC_CFG_BASE 0x7FFF2414E0ull +#define KERNEL_TENSOR_4_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC1_EML_TPC_CFG_BASE 0x7FFF241518ull +#define KERNEL_TENSOR_5_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC1_EML_TPC_CFG_BASE 0x7FFF241550ull +#define KERNEL_TENSOR_6_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC1_EML_TPC_CFG_BASE 0x7FFF241588ull +#define KERNEL_TENSOR_7_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC1_EML_TPC_CFG_BASE 0x7FFF2415C0ull +#define KERNEL_TENSOR_8_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC1_EML_TPC_CFG_BASE 0x7FFF2415F8ull +#define KERNEL_TENSOR_9_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC1_EML_TPC_CFG_BASE 0x7FFF241630ull +#define KERNEL_TENSOR_10_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC1_EML_TPC_CFG_BASE 0x7FFF241668ull +#define KERNEL_TENSOR_11_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC1_EML_TPC_CFG_BASE 0x7FFF2416A0ull +#define KERNEL_TENSOR_12_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC1_EML_TPC_CFG_BASE 0x7FFF2416D8ull +#define KERNEL_TENSOR_13_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC1_EML_TPC_CFG_BASE 0x7FFF241710ull +#define KERNEL_TENSOR_14_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC1_EML_TPC_CFG_BASE 0x7FFF241748ull +#define KERNEL_TENSOR_15_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC1_EML_TPC_CFG_BASE 0x7FFF241780ull +#define KERNEL_SYNC_OBJECT_TPC1_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC1_EML_TPC_CFG_SECTION 0x8000 +#define mmKERNEL_TPC1_EML_TPC_CFG_BASE 0x7FFF241788ull +#define KERNEL_TPC1_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC1_EML_TPC_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC1_EML_TPC_CFG_BASE 0x7FFF241A00ull +#define QM_TENSOR_0_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC1_EML_TPC_CFG_BASE 0x7FFF241A38ull +#define QM_TENSOR_1_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC1_EML_TPC_CFG_BASE 0x7FFF241A70ull +#define QM_TENSOR_2_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC1_EML_TPC_CFG_BASE 0x7FFF241AA8ull +#define QM_TENSOR_3_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC1_EML_TPC_CFG_BASE 0x7FFF241AE0ull +#define QM_TENSOR_4_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC1_EML_TPC_CFG_BASE 0x7FFF241B18ull +#define QM_TENSOR_5_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC1_EML_TPC_CFG_BASE 0x7FFF241B50ull +#define QM_TENSOR_6_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC1_EML_TPC_CFG_BASE 0x7FFF241B88ull +#define QM_TENSOR_7_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC1_EML_TPC_CFG_BASE 0x7FFF241BC0ull +#define QM_TENSOR_8_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC1_EML_TPC_CFG_BASE 0x7FFF241BF8ull +#define QM_TENSOR_9_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC1_EML_TPC_CFG_BASE 0x7FFF241C30ull +#define QM_TENSOR_10_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC1_EML_TPC_CFG_BASE 0x7FFF241C68ull +#define QM_TENSOR_11_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC1_EML_TPC_CFG_BASE 0x7FFF241CA0ull +#define QM_TENSOR_12_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC1_EML_TPC_CFG_BASE 0x7FFF241CD8ull +#define QM_TENSOR_13_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC1_EML_TPC_CFG_BASE 0x7FFF241D10ull +#define QM_TENSOR_14_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC1_EML_TPC_CFG_BASE 0x7FFF241D48ull +#define QM_TENSOR_15_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC1_EML_TPC_CFG_BASE 0x7FFF241D80ull +#define QM_SYNC_OBJECT_TPC1_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC1_EML_TPC_CFG_SECTION 0x8000 +#define mmQM_TPC1_EML_TPC_CFG_BASE 0x7FFF241D88ull +#define QM_TPC1_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define QM_TPC1_EML_TPC_CFG_SECTION 0x2780 +#define mmTPC1_EML_TPC_QM_BASE 0x7FFF242000ull +#define TPC1_EML_TPC_QM_MAX_OFFSET 0xD040 +#define TPC1_EML_TPC_QM_SECTION 0x1BD000 +#define mmTPC1_EML_CS_BASE 0x7FFF3FF000ull +#define TPC1_EML_CS_MAX_OFFSET 0x1000 +#define TPC1_EML_CS_SECTION 0x1000 +#define mmTPC2_ROM_TABLE_BASE 0x7FFF400000ull +#define TPC2_ROM_TABLE_MAX_OFFSET 0x1000 +#define TPC2_ROM_TABLE_SECTION 0x1000 +#define mmTPC2_EML_SPMU_BASE 0x7FFF401000ull +#define TPC2_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC2_EML_SPMU_SECTION 0x1000 +#define mmTPC2_EML_ETF_BASE 0x7FFF402000ull +#define TPC2_EML_ETF_MAX_OFFSET 0x1000 +#define TPC2_EML_ETF_SECTION 0x1000 +#define mmTPC2_EML_STM_BASE 0x7FFF403000ull +#define TPC2_EML_STM_MAX_OFFSET 0x1000 +#define TPC2_EML_STM_SECTION 0x2000 +#define mmTPC2_EML_CTI_BASE 0x7FFF405000ull +#define TPC2_EML_CTI_MAX_OFFSET 0x1000 +#define TPC2_EML_CTI_SECTION 0x1000 +#define mmTPC2_EML_FUNNEL_BASE 0x7FFF406000ull +#define TPC2_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC2_EML_FUNNEL_SECTION 0x1000 +#define mmTPC2_EML_BUSMON_0_BASE 0x7FFF407000ull +#define TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC2_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC2_EML_BUSMON_1_BASE 0x7FFF408000ull +#define TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC2_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC2_EML_BUSMON_2_BASE 0x7FFF409000ull +#define TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC2_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC2_EML_BUSMON_3_BASE 0x7FFF40A000ull +#define TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC2_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC2_EML_CFG_BASE 0x7FFF440000ull +#define TPC2_EML_CFG_MAX_OFFSET 0x3380 +#define TPC2_EML_CFG_SECTION 0x1000 +#define mmTPC2_EML_TPC_CFG_BASE 0x7FFF441000ull +#define TPC2_EML_TPC_CFG_MAX_OFFSET 0xE400 +#define TPC2_EML_TPC_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC2_EML_TPC_CFG_BASE 0x7FFF441400ull +#define KERNEL_TENSOR_0_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC2_EML_TPC_CFG_BASE 0x7FFF441438ull +#define KERNEL_TENSOR_1_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC2_EML_TPC_CFG_BASE 0x7FFF441470ull +#define KERNEL_TENSOR_2_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC2_EML_TPC_CFG_BASE 0x7FFF4414A8ull +#define KERNEL_TENSOR_3_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC2_EML_TPC_CFG_BASE 0x7FFF4414E0ull +#define KERNEL_TENSOR_4_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC2_EML_TPC_CFG_BASE 0x7FFF441518ull +#define KERNEL_TENSOR_5_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC2_EML_TPC_CFG_BASE 0x7FFF441550ull +#define KERNEL_TENSOR_6_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC2_EML_TPC_CFG_BASE 0x7FFF441588ull +#define KERNEL_TENSOR_7_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC2_EML_TPC_CFG_BASE 0x7FFF4415C0ull +#define KERNEL_TENSOR_8_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC2_EML_TPC_CFG_BASE 0x7FFF4415F8ull +#define KERNEL_TENSOR_9_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC2_EML_TPC_CFG_BASE 0x7FFF441630ull +#define KERNEL_TENSOR_10_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC2_EML_TPC_CFG_BASE 0x7FFF441668ull +#define KERNEL_TENSOR_11_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC2_EML_TPC_CFG_BASE 0x7FFF4416A0ull +#define KERNEL_TENSOR_12_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC2_EML_TPC_CFG_BASE 0x7FFF4416D8ull +#define KERNEL_TENSOR_13_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC2_EML_TPC_CFG_BASE 0x7FFF441710ull +#define KERNEL_TENSOR_14_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC2_EML_TPC_CFG_BASE 0x7FFF441748ull +#define KERNEL_TENSOR_15_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC2_EML_TPC_CFG_BASE 0x7FFF441780ull +#define KERNEL_SYNC_OBJECT_TPC2_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC2_EML_TPC_CFG_SECTION 0x8000 +#define mmKERNEL_TPC2_EML_TPC_CFG_BASE 0x7FFF441788ull +#define KERNEL_TPC2_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC2_EML_TPC_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC2_EML_TPC_CFG_BASE 0x7FFF441A00ull +#define QM_TENSOR_0_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC2_EML_TPC_CFG_BASE 0x7FFF441A38ull +#define QM_TENSOR_1_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC2_EML_TPC_CFG_BASE 0x7FFF441A70ull +#define QM_TENSOR_2_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC2_EML_TPC_CFG_BASE 0x7FFF441AA8ull +#define QM_TENSOR_3_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC2_EML_TPC_CFG_BASE 0x7FFF441AE0ull +#define QM_TENSOR_4_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC2_EML_TPC_CFG_BASE 0x7FFF441B18ull +#define QM_TENSOR_5_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC2_EML_TPC_CFG_BASE 0x7FFF441B50ull +#define QM_TENSOR_6_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC2_EML_TPC_CFG_BASE 0x7FFF441B88ull +#define QM_TENSOR_7_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC2_EML_TPC_CFG_BASE 0x7FFF441BC0ull +#define QM_TENSOR_8_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC2_EML_TPC_CFG_BASE 0x7FFF441BF8ull +#define QM_TENSOR_9_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC2_EML_TPC_CFG_BASE 0x7FFF441C30ull +#define QM_TENSOR_10_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC2_EML_TPC_CFG_BASE 0x7FFF441C68ull +#define QM_TENSOR_11_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC2_EML_TPC_CFG_BASE 0x7FFF441CA0ull +#define QM_TENSOR_12_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC2_EML_TPC_CFG_BASE 0x7FFF441CD8ull +#define QM_TENSOR_13_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC2_EML_TPC_CFG_BASE 0x7FFF441D10ull +#define QM_TENSOR_14_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC2_EML_TPC_CFG_BASE 0x7FFF441D48ull +#define QM_TENSOR_15_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC2_EML_TPC_CFG_BASE 0x7FFF441D80ull +#define QM_SYNC_OBJECT_TPC2_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC2_EML_TPC_CFG_SECTION 0x8000 +#define mmQM_TPC2_EML_TPC_CFG_BASE 0x7FFF441D88ull +#define QM_TPC2_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define QM_TPC2_EML_TPC_CFG_SECTION 0x2780 +#define mmTPC2_EML_TPC_QM_BASE 0x7FFF442000ull +#define TPC2_EML_TPC_QM_MAX_OFFSET 0xD040 +#define TPC2_EML_TPC_QM_SECTION 0x1BD000 +#define mmTPC2_EML_CS_BASE 0x7FFF5FF000ull +#define TPC2_EML_CS_MAX_OFFSET 0x1000 +#define TPC2_EML_CS_SECTION 0x1000 +#define mmTPC3_ROM_TABLE_BASE 0x7FFF600000ull +#define TPC3_ROM_TABLE_MAX_OFFSET 0x1000 +#define TPC3_ROM_TABLE_SECTION 0x1000 +#define mmTPC3_EML_SPMU_BASE 0x7FFF601000ull +#define TPC3_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC3_EML_SPMU_SECTION 0x1000 +#define mmTPC3_EML_ETF_BASE 0x7FFF602000ull +#define TPC3_EML_ETF_MAX_OFFSET 0x1000 +#define TPC3_EML_ETF_SECTION 0x1000 +#define mmTPC3_EML_STM_BASE 0x7FFF603000ull +#define TPC3_EML_STM_MAX_OFFSET 0x1000 +#define TPC3_EML_STM_SECTION 0x2000 +#define mmTPC3_EML_CTI_BASE 0x7FFF605000ull +#define TPC3_EML_CTI_MAX_OFFSET 0x1000 +#define TPC3_EML_CTI_SECTION 0x1000 +#define mmTPC3_EML_FUNNEL_BASE 0x7FFF606000ull +#define TPC3_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC3_EML_FUNNEL_SECTION 0x1000 +#define mmTPC3_EML_BUSMON_0_BASE 0x7FFF607000ull +#define TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC3_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC3_EML_BUSMON_1_BASE 0x7FFF608000ull +#define TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC3_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC3_EML_BUSMON_2_BASE 0x7FFF609000ull +#define TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC3_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC3_EML_BUSMON_3_BASE 0x7FFF60A000ull +#define TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC3_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC3_EML_CFG_BASE 0x7FFF640000ull +#define TPC3_EML_CFG_MAX_OFFSET 0x3380 +#define TPC3_EML_CFG_SECTION 0x1000 +#define mmTPC3_EML_TPC_CFG_BASE 0x7FFF641000ull +#define TPC3_EML_TPC_CFG_MAX_OFFSET 0xE400 +#define TPC3_EML_TPC_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC3_EML_TPC_CFG_BASE 0x7FFF641400ull +#define KERNEL_TENSOR_0_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC3_EML_TPC_CFG_BASE 0x7FFF641438ull +#define KERNEL_TENSOR_1_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC3_EML_TPC_CFG_BASE 0x7FFF641470ull +#define KERNEL_TENSOR_2_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC3_EML_TPC_CFG_BASE 0x7FFF6414A8ull +#define KERNEL_TENSOR_3_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC3_EML_TPC_CFG_BASE 0x7FFF6414E0ull +#define KERNEL_TENSOR_4_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC3_EML_TPC_CFG_BASE 0x7FFF641518ull +#define KERNEL_TENSOR_5_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC3_EML_TPC_CFG_BASE 0x7FFF641550ull +#define KERNEL_TENSOR_6_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC3_EML_TPC_CFG_BASE 0x7FFF641588ull +#define KERNEL_TENSOR_7_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC3_EML_TPC_CFG_BASE 0x7FFF6415C0ull +#define KERNEL_TENSOR_8_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC3_EML_TPC_CFG_BASE 0x7FFF6415F8ull +#define KERNEL_TENSOR_9_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC3_EML_TPC_CFG_BASE 0x7FFF641630ull +#define KERNEL_TENSOR_10_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC3_EML_TPC_CFG_BASE 0x7FFF641668ull +#define KERNEL_TENSOR_11_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC3_EML_TPC_CFG_BASE 0x7FFF6416A0ull +#define KERNEL_TENSOR_12_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC3_EML_TPC_CFG_BASE 0x7FFF6416D8ull +#define KERNEL_TENSOR_13_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC3_EML_TPC_CFG_BASE 0x7FFF641710ull +#define KERNEL_TENSOR_14_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC3_EML_TPC_CFG_BASE 0x7FFF641748ull +#define KERNEL_TENSOR_15_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC3_EML_TPC_CFG_BASE 0x7FFF641780ull +#define KERNEL_SYNC_OBJECT_TPC3_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC3_EML_TPC_CFG_SECTION 0x8000 +#define mmKERNEL_TPC3_EML_TPC_CFG_BASE 0x7FFF641788ull +#define KERNEL_TPC3_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC3_EML_TPC_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC3_EML_TPC_CFG_BASE 0x7FFF641A00ull +#define QM_TENSOR_0_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC3_EML_TPC_CFG_BASE 0x7FFF641A38ull +#define QM_TENSOR_1_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC3_EML_TPC_CFG_BASE 0x7FFF641A70ull +#define QM_TENSOR_2_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC3_EML_TPC_CFG_BASE 0x7FFF641AA8ull +#define QM_TENSOR_3_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC3_EML_TPC_CFG_BASE 0x7FFF641AE0ull +#define QM_TENSOR_4_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC3_EML_TPC_CFG_BASE 0x7FFF641B18ull +#define QM_TENSOR_5_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC3_EML_TPC_CFG_BASE 0x7FFF641B50ull +#define QM_TENSOR_6_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC3_EML_TPC_CFG_BASE 0x7FFF641B88ull +#define QM_TENSOR_7_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC3_EML_TPC_CFG_BASE 0x7FFF641BC0ull +#define QM_TENSOR_8_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC3_EML_TPC_CFG_BASE 0x7FFF641BF8ull +#define QM_TENSOR_9_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC3_EML_TPC_CFG_BASE 0x7FFF641C30ull +#define QM_TENSOR_10_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC3_EML_TPC_CFG_BASE 0x7FFF641C68ull +#define QM_TENSOR_11_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC3_EML_TPC_CFG_BASE 0x7FFF641CA0ull +#define QM_TENSOR_12_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC3_EML_TPC_CFG_BASE 0x7FFF641CD8ull +#define QM_TENSOR_13_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC3_EML_TPC_CFG_BASE 0x7FFF641D10ull +#define QM_TENSOR_14_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC3_EML_TPC_CFG_BASE 0x7FFF641D48ull +#define QM_TENSOR_15_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC3_EML_TPC_CFG_BASE 0x7FFF641D80ull +#define QM_SYNC_OBJECT_TPC3_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC3_EML_TPC_CFG_SECTION 0x8000 +#define mmQM_TPC3_EML_TPC_CFG_BASE 0x7FFF641D88ull +#define QM_TPC3_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define QM_TPC3_EML_TPC_CFG_SECTION 0x2780 +#define mmTPC3_EML_TPC_QM_BASE 0x7FFF642000ull +#define TPC3_EML_TPC_QM_MAX_OFFSET 0xD040 +#define TPC3_EML_TPC_QM_SECTION 0x1BD000 +#define mmTPC3_EML_CS_BASE 0x7FFF7FF000ull +#define TPC3_EML_CS_MAX_OFFSET 0x1000 +#define TPC3_EML_CS_SECTION 0x1000 +#define mmTPC4_ROM_TABLE_BASE 0x7FFF800000ull +#define TPC4_ROM_TABLE_MAX_OFFSET 0x1000 +#define TPC4_ROM_TABLE_SECTION 0x1000 +#define mmTPC4_EML_SPMU_BASE 0x7FFF801000ull +#define TPC4_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC4_EML_SPMU_SECTION 0x1000 +#define mmTPC4_EML_ETF_BASE 0x7FFF802000ull +#define TPC4_EML_ETF_MAX_OFFSET 0x1000 +#define TPC4_EML_ETF_SECTION 0x1000 +#define mmTPC4_EML_STM_BASE 0x7FFF803000ull +#define TPC4_EML_STM_MAX_OFFSET 0x1000 +#define TPC4_EML_STM_SECTION 0x2000 +#define mmTPC4_EML_CTI_BASE 0x7FFF805000ull +#define TPC4_EML_CTI_MAX_OFFSET 0x1000 +#define TPC4_EML_CTI_SECTION 0x1000 +#define mmTPC4_EML_FUNNEL_BASE 0x7FFF806000ull +#define TPC4_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC4_EML_FUNNEL_SECTION 0x1000 +#define mmTPC4_EML_BUSMON_0_BASE 0x7FFF807000ull +#define TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC4_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC4_EML_BUSMON_1_BASE 0x7FFF808000ull +#define TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC4_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC4_EML_BUSMON_2_BASE 0x7FFF809000ull +#define TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC4_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC4_EML_BUSMON_3_BASE 0x7FFF80A000ull +#define TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC4_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC4_EML_CFG_BASE 0x7FFF840000ull +#define TPC4_EML_CFG_MAX_OFFSET 0x3380 +#define TPC4_EML_CFG_SECTION 0x1000 +#define mmTPC4_EML_TPC_CFG_BASE 0x7FFF841000ull +#define TPC4_EML_TPC_CFG_MAX_OFFSET 0xE400 +#define TPC4_EML_TPC_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC4_EML_TPC_CFG_BASE 0x7FFF841400ull +#define KERNEL_TENSOR_0_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC4_EML_TPC_CFG_BASE 0x7FFF841438ull +#define KERNEL_TENSOR_1_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC4_EML_TPC_CFG_BASE 0x7FFF841470ull +#define KERNEL_TENSOR_2_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC4_EML_TPC_CFG_BASE 0x7FFF8414A8ull +#define KERNEL_TENSOR_3_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC4_EML_TPC_CFG_BASE 0x7FFF8414E0ull +#define KERNEL_TENSOR_4_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC4_EML_TPC_CFG_BASE 0x7FFF841518ull +#define KERNEL_TENSOR_5_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC4_EML_TPC_CFG_BASE 0x7FFF841550ull +#define KERNEL_TENSOR_6_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC4_EML_TPC_CFG_BASE 0x7FFF841588ull +#define KERNEL_TENSOR_7_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC4_EML_TPC_CFG_BASE 0x7FFF8415C0ull +#define KERNEL_TENSOR_8_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC4_EML_TPC_CFG_BASE 0x7FFF8415F8ull +#define KERNEL_TENSOR_9_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC4_EML_TPC_CFG_BASE 0x7FFF841630ull +#define KERNEL_TENSOR_10_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC4_EML_TPC_CFG_BASE 0x7FFF841668ull +#define KERNEL_TENSOR_11_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC4_EML_TPC_CFG_BASE 0x7FFF8416A0ull +#define KERNEL_TENSOR_12_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC4_EML_TPC_CFG_BASE 0x7FFF8416D8ull +#define KERNEL_TENSOR_13_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC4_EML_TPC_CFG_BASE 0x7FFF841710ull +#define KERNEL_TENSOR_14_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC4_EML_TPC_CFG_BASE 0x7FFF841748ull +#define KERNEL_TENSOR_15_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC4_EML_TPC_CFG_BASE 0x7FFF841780ull +#define KERNEL_SYNC_OBJECT_TPC4_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC4_EML_TPC_CFG_SECTION 0x8000 +#define mmKERNEL_TPC4_EML_TPC_CFG_BASE 0x7FFF841788ull +#define KERNEL_TPC4_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC4_EML_TPC_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC4_EML_TPC_CFG_BASE 0x7FFF841A00ull +#define QM_TENSOR_0_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC4_EML_TPC_CFG_BASE 0x7FFF841A38ull +#define QM_TENSOR_1_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC4_EML_TPC_CFG_BASE 0x7FFF841A70ull +#define QM_TENSOR_2_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC4_EML_TPC_CFG_BASE 0x7FFF841AA8ull +#define QM_TENSOR_3_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC4_EML_TPC_CFG_BASE 0x7FFF841AE0ull +#define QM_TENSOR_4_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC4_EML_TPC_CFG_BASE 0x7FFF841B18ull +#define QM_TENSOR_5_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC4_EML_TPC_CFG_BASE 0x7FFF841B50ull +#define QM_TENSOR_6_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC4_EML_TPC_CFG_BASE 0x7FFF841B88ull +#define QM_TENSOR_7_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC4_EML_TPC_CFG_BASE 0x7FFF841BC0ull +#define QM_TENSOR_8_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC4_EML_TPC_CFG_BASE 0x7FFF841BF8ull +#define QM_TENSOR_9_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC4_EML_TPC_CFG_BASE 0x7FFF841C30ull +#define QM_TENSOR_10_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC4_EML_TPC_CFG_BASE 0x7FFF841C68ull +#define QM_TENSOR_11_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC4_EML_TPC_CFG_BASE 0x7FFF841CA0ull +#define QM_TENSOR_12_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC4_EML_TPC_CFG_BASE 0x7FFF841CD8ull +#define QM_TENSOR_13_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC4_EML_TPC_CFG_BASE 0x7FFF841D10ull +#define QM_TENSOR_14_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC4_EML_TPC_CFG_BASE 0x7FFF841D48ull +#define QM_TENSOR_15_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC4_EML_TPC_CFG_BASE 0x7FFF841D80ull +#define QM_SYNC_OBJECT_TPC4_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC4_EML_TPC_CFG_SECTION 0x8000 +#define mmQM_TPC4_EML_TPC_CFG_BASE 0x7FFF841D88ull +#define QM_TPC4_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define QM_TPC4_EML_TPC_CFG_SECTION 0x2780 +#define mmTPC4_EML_TPC_QM_BASE 0x7FFF842000ull +#define TPC4_EML_TPC_QM_MAX_OFFSET 0xD040 +#define TPC4_EML_TPC_QM_SECTION 0x1BD000 +#define mmTPC4_EML_CS_BASE 0x7FFF9FF000ull +#define TPC4_EML_CS_MAX_OFFSET 0x1000 +#define TPC4_EML_CS_SECTION 0x1000 +#define mmTPC5_ROM_TABLE_BASE 0x7FFFA00000ull +#define TPC5_ROM_TABLE_MAX_OFFSET 0x1000 +#define TPC5_ROM_TABLE_SECTION 0x1000 +#define mmTPC5_EML_SPMU_BASE 0x7FFFA01000ull +#define TPC5_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC5_EML_SPMU_SECTION 0x1000 +#define mmTPC5_EML_ETF_BASE 0x7FFFA02000ull +#define TPC5_EML_ETF_MAX_OFFSET 0x1000 +#define TPC5_EML_ETF_SECTION 0x1000 +#define mmTPC5_EML_STM_BASE 0x7FFFA03000ull +#define TPC5_EML_STM_MAX_OFFSET 0x1000 +#define TPC5_EML_STM_SECTION 0x2000 +#define mmTPC5_EML_CTI_BASE 0x7FFFA05000ull +#define TPC5_EML_CTI_MAX_OFFSET 0x1000 +#define TPC5_EML_CTI_SECTION 0x1000 +#define mmTPC5_EML_FUNNEL_BASE 0x7FFFA06000ull +#define TPC5_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC5_EML_FUNNEL_SECTION 0x1000 +#define mmTPC5_EML_BUSMON_0_BASE 0x7FFFA07000ull +#define TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC5_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC5_EML_BUSMON_1_BASE 0x7FFFA08000ull +#define TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC5_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC5_EML_BUSMON_2_BASE 0x7FFFA09000ull +#define TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC5_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC5_EML_BUSMON_3_BASE 0x7FFFA0A000ull +#define TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC5_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC5_EML_CFG_BASE 0x7FFFA40000ull +#define TPC5_EML_CFG_MAX_OFFSET 0x3380 +#define TPC5_EML_CFG_SECTION 0x1000 +#define mmTPC5_EML_TPC_CFG_BASE 0x7FFFA41000ull +#define TPC5_EML_TPC_CFG_MAX_OFFSET 0xE400 +#define TPC5_EML_TPC_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC5_EML_TPC_CFG_BASE 0x7FFFA41400ull +#define KERNEL_TENSOR_0_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC5_EML_TPC_CFG_BASE 0x7FFFA41438ull +#define KERNEL_TENSOR_1_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC5_EML_TPC_CFG_BASE 0x7FFFA41470ull +#define KERNEL_TENSOR_2_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC5_EML_TPC_CFG_BASE 0x7FFFA414A8ull +#define KERNEL_TENSOR_3_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC5_EML_TPC_CFG_BASE 0x7FFFA414E0ull +#define KERNEL_TENSOR_4_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC5_EML_TPC_CFG_BASE 0x7FFFA41518ull +#define KERNEL_TENSOR_5_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC5_EML_TPC_CFG_BASE 0x7FFFA41550ull +#define KERNEL_TENSOR_6_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC5_EML_TPC_CFG_BASE 0x7FFFA41588ull +#define KERNEL_TENSOR_7_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC5_EML_TPC_CFG_BASE 0x7FFFA415C0ull +#define KERNEL_TENSOR_8_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC5_EML_TPC_CFG_BASE 0x7FFFA415F8ull +#define KERNEL_TENSOR_9_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC5_EML_TPC_CFG_BASE 0x7FFFA41630ull +#define KERNEL_TENSOR_10_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC5_EML_TPC_CFG_BASE 0x7FFFA41668ull +#define KERNEL_TENSOR_11_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC5_EML_TPC_CFG_BASE 0x7FFFA416A0ull +#define KERNEL_TENSOR_12_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC5_EML_TPC_CFG_BASE 0x7FFFA416D8ull +#define KERNEL_TENSOR_13_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC5_EML_TPC_CFG_BASE 0x7FFFA41710ull +#define KERNEL_TENSOR_14_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC5_EML_TPC_CFG_BASE 0x7FFFA41748ull +#define KERNEL_TENSOR_15_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC5_EML_TPC_CFG_BASE 0x7FFFA41780ull +#define KERNEL_SYNC_OBJECT_TPC5_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC5_EML_TPC_CFG_SECTION 0x8000 +#define mmKERNEL_TPC5_EML_TPC_CFG_BASE 0x7FFFA41788ull +#define KERNEL_TPC5_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC5_EML_TPC_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC5_EML_TPC_CFG_BASE 0x7FFFA41A00ull +#define QM_TENSOR_0_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC5_EML_TPC_CFG_BASE 0x7FFFA41A38ull +#define QM_TENSOR_1_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC5_EML_TPC_CFG_BASE 0x7FFFA41A70ull +#define QM_TENSOR_2_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC5_EML_TPC_CFG_BASE 0x7FFFA41AA8ull +#define QM_TENSOR_3_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC5_EML_TPC_CFG_BASE 0x7FFFA41AE0ull +#define QM_TENSOR_4_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC5_EML_TPC_CFG_BASE 0x7FFFA41B18ull +#define QM_TENSOR_5_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC5_EML_TPC_CFG_BASE 0x7FFFA41B50ull +#define QM_TENSOR_6_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC5_EML_TPC_CFG_BASE 0x7FFFA41B88ull +#define QM_TENSOR_7_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC5_EML_TPC_CFG_BASE 0x7FFFA41BC0ull +#define QM_TENSOR_8_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC5_EML_TPC_CFG_BASE 0x7FFFA41BF8ull +#define QM_TENSOR_9_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC5_EML_TPC_CFG_BASE 0x7FFFA41C30ull +#define QM_TENSOR_10_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC5_EML_TPC_CFG_BASE 0x7FFFA41C68ull +#define QM_TENSOR_11_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC5_EML_TPC_CFG_BASE 0x7FFFA41CA0ull +#define QM_TENSOR_12_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC5_EML_TPC_CFG_BASE 0x7FFFA41CD8ull +#define QM_TENSOR_13_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D10ull +#define QM_TENSOR_14_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D48ull +#define QM_TENSOR_15_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D80ull +#define QM_SYNC_OBJECT_TPC5_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC5_EML_TPC_CFG_SECTION 0x8000 +#define mmQM_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D88ull +#define QM_TPC5_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define QM_TPC5_EML_TPC_CFG_SECTION 0x2780 +#define mmTPC5_EML_TPC_QM_BASE 0x7FFFA42000ull +#define TPC5_EML_TPC_QM_MAX_OFFSET 0xD040 +#define TPC5_EML_TPC_QM_SECTION 0x1BD000 +#define mmTPC5_EML_CS_BASE 0x7FFFBFF000ull +#define TPC5_EML_CS_MAX_OFFSET 0x1000 +#define TPC5_EML_CS_SECTION 0x1000 +#define mmTPC6_ROM_TABLE_BASE 0x7FFFC00000ull +#define TPC6_ROM_TABLE_MAX_OFFSET 0x1000 +#define TPC6_ROM_TABLE_SECTION 0x1000 +#define mmTPC6_EML_SPMU_BASE 0x7FFFC01000ull +#define TPC6_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC6_EML_SPMU_SECTION 0x1000 +#define mmTPC6_EML_ETF_BASE 0x7FFFC02000ull +#define TPC6_EML_ETF_MAX_OFFSET 0x1000 +#define TPC6_EML_ETF_SECTION 0x1000 +#define mmTPC6_EML_STM_BASE 0x7FFFC03000ull +#define TPC6_EML_STM_MAX_OFFSET 0x1000 +#define TPC6_EML_STM_SECTION 0x2000 +#define mmTPC6_EML_CTI_BASE 0x7FFFC05000ull +#define TPC6_EML_CTI_MAX_OFFSET 0x1000 +#define TPC6_EML_CTI_SECTION 0x1000 +#define mmTPC6_EML_FUNNEL_BASE 0x7FFFC06000ull +#define TPC6_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC6_EML_FUNNEL_SECTION 0x1000 +#define mmTPC6_EML_BUSMON_0_BASE 0x7FFFC07000ull +#define TPC6_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC6_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC6_EML_BUSMON_1_BASE 0x7FFFC08000ull +#define TPC6_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC6_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC6_EML_BUSMON_2_BASE 0x7FFFC09000ull +#define TPC6_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC6_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC6_EML_BUSMON_3_BASE 0x7FFFC0A000ull +#define TPC6_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC6_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC6_EML_CFG_BASE 0x7FFFC40000ull +#define TPC6_EML_CFG_MAX_OFFSET 0x3380 +#define TPC6_EML_CFG_SECTION 0x1000 +#define mmTPC6_EML_TPC_CFG_BASE 0x7FFFC41000ull +#define TPC6_EML_TPC_CFG_MAX_OFFSET 0xE400 +#define TPC6_EML_TPC_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC6_EML_TPC_CFG_BASE 0x7FFFC41400ull +#define KERNEL_TENSOR_0_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC6_EML_TPC_CFG_BASE 0x7FFFC41438ull +#define KERNEL_TENSOR_1_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC6_EML_TPC_CFG_BASE 0x7FFFC41470ull +#define KERNEL_TENSOR_2_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC6_EML_TPC_CFG_BASE 0x7FFFC414A8ull +#define KERNEL_TENSOR_3_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC6_EML_TPC_CFG_BASE 0x7FFFC414E0ull +#define KERNEL_TENSOR_4_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC6_EML_TPC_CFG_BASE 0x7FFFC41518ull +#define KERNEL_TENSOR_5_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC6_EML_TPC_CFG_BASE 0x7FFFC41550ull +#define KERNEL_TENSOR_6_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC6_EML_TPC_CFG_BASE 0x7FFFC41588ull +#define KERNEL_TENSOR_7_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC6_EML_TPC_CFG_BASE 0x7FFFC415C0ull +#define KERNEL_TENSOR_8_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC6_EML_TPC_CFG_BASE 0x7FFFC415F8ull +#define KERNEL_TENSOR_9_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC6_EML_TPC_CFG_BASE 0x7FFFC41630ull +#define KERNEL_TENSOR_10_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC6_EML_TPC_CFG_BASE 0x7FFFC41668ull +#define KERNEL_TENSOR_11_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC6_EML_TPC_CFG_BASE 0x7FFFC416A0ull +#define KERNEL_TENSOR_12_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC6_EML_TPC_CFG_BASE 0x7FFFC416D8ull +#define KERNEL_TENSOR_13_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC6_EML_TPC_CFG_BASE 0x7FFFC41710ull +#define KERNEL_TENSOR_14_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC6_EML_TPC_CFG_BASE 0x7FFFC41748ull +#define KERNEL_TENSOR_15_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC6_EML_TPC_CFG_BASE 0x7FFFC41780ull +#define KERNEL_SYNC_OBJECT_TPC6_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC6_EML_TPC_CFG_SECTION 0x8000 +#define mmKERNEL_TPC6_EML_TPC_CFG_BASE 0x7FFFC41788ull +#define KERNEL_TPC6_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC6_EML_TPC_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC6_EML_TPC_CFG_BASE 0x7FFFC41A00ull +#define QM_TENSOR_0_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC6_EML_TPC_CFG_BASE 0x7FFFC41A38ull +#define QM_TENSOR_1_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC6_EML_TPC_CFG_BASE 0x7FFFC41A70ull +#define QM_TENSOR_2_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC6_EML_TPC_CFG_BASE 0x7FFFC41AA8ull +#define QM_TENSOR_3_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC6_EML_TPC_CFG_BASE 0x7FFFC41AE0ull +#define QM_TENSOR_4_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC6_EML_TPC_CFG_BASE 0x7FFFC41B18ull +#define QM_TENSOR_5_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC6_EML_TPC_CFG_BASE 0x7FFFC41B50ull +#define QM_TENSOR_6_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC6_EML_TPC_CFG_BASE 0x7FFFC41B88ull +#define QM_TENSOR_7_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC6_EML_TPC_CFG_BASE 0x7FFFC41BC0ull +#define QM_TENSOR_8_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC6_EML_TPC_CFG_BASE 0x7FFFC41BF8ull +#define QM_TENSOR_9_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC6_EML_TPC_CFG_BASE 0x7FFFC41C30ull +#define QM_TENSOR_10_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC6_EML_TPC_CFG_BASE 0x7FFFC41C68ull +#define QM_TENSOR_11_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC6_EML_TPC_CFG_BASE 0x7FFFC41CA0ull +#define QM_TENSOR_12_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC6_EML_TPC_CFG_BASE 0x7FFFC41CD8ull +#define QM_TENSOR_13_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D10ull +#define QM_TENSOR_14_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D48ull +#define QM_TENSOR_15_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D80ull +#define QM_SYNC_OBJECT_TPC6_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC6_EML_TPC_CFG_SECTION 0x8000 +#define mmQM_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D88ull +#define QM_TPC6_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define QM_TPC6_EML_TPC_CFG_SECTION 0x2780 +#define mmTPC6_EML_TPC_QM_BASE 0x7FFFC42000ull +#define TPC6_EML_TPC_QM_MAX_OFFSET 0xD040 +#define TPC6_EML_TPC_QM_SECTION 0x1BD000 +#define mmTPC6_EML_CS_BASE 0x7FFFDFF000ull +#define TPC6_EML_CS_MAX_OFFSET 0x1000 +#define TPC6_EML_CS_SECTION 0x1000 +#define mmTPC7_ROM_TABLE_BASE 0x7FFFE00000ull +#define TPC7_ROM_TABLE_MAX_OFFSET 0x1000 +#define TPC7_ROM_TABLE_SECTION 0x1000 +#define mmTPC7_EML_SPMU_BASE 0x7FFFE01000ull +#define TPC7_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC7_EML_SPMU_SECTION 0x1000 +#define mmTPC7_EML_ETF_BASE 0x7FFFE02000ull +#define TPC7_EML_ETF_MAX_OFFSET 0x1000 +#define TPC7_EML_ETF_SECTION 0x1000 +#define mmTPC7_EML_STM_BASE 0x7FFFE03000ull +#define TPC7_EML_STM_MAX_OFFSET 0x1000 +#define TPC7_EML_STM_SECTION 0x2000 +#define mmTPC7_EML_CTI_BASE 0x7FFFE05000ull +#define TPC7_EML_CTI_MAX_OFFSET 0x1000 +#define TPC7_EML_CTI_SECTION 0x1000 +#define mmTPC7_EML_FUNNEL_BASE 0x7FFFE06000ull +#define TPC7_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC7_EML_FUNNEL_SECTION 0x1000 +#define mmTPC7_EML_BUSMON_0_BASE 0x7FFFE07000ull +#define TPC7_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC7_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC7_EML_BUSMON_1_BASE 0x7FFFE08000ull +#define TPC7_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC7_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC7_EML_BUSMON_2_BASE 0x7FFFE09000ull +#define TPC7_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC7_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC7_EML_BUSMON_3_BASE 0x7FFFE0A000ull +#define TPC7_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC7_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC7_EML_CFG_BASE 0x7FFFE40000ull +#define TPC7_EML_CFG_MAX_OFFSET 0x3380 +#define TPC7_EML_CFG_SECTION 0x1000 +#define mmTPC7_EML_TPC_CFG_BASE 0x7FFFE41000ull +#define TPC7_EML_TPC_CFG_MAX_OFFSET 0xE400 +#define TPC7_EML_TPC_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC7_EML_TPC_CFG_BASE 0x7FFFE41400ull +#define KERNEL_TENSOR_0_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC7_EML_TPC_CFG_BASE 0x7FFFE41438ull +#define KERNEL_TENSOR_1_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC7_EML_TPC_CFG_BASE 0x7FFFE41470ull +#define KERNEL_TENSOR_2_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC7_EML_TPC_CFG_BASE 0x7FFFE414A8ull +#define KERNEL_TENSOR_3_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC7_EML_TPC_CFG_BASE 0x7FFFE414E0ull +#define KERNEL_TENSOR_4_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC7_EML_TPC_CFG_BASE 0x7FFFE41518ull +#define KERNEL_TENSOR_5_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC7_EML_TPC_CFG_BASE 0x7FFFE41550ull +#define KERNEL_TENSOR_6_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC7_EML_TPC_CFG_BASE 0x7FFFE41588ull +#define KERNEL_TENSOR_7_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC7_EML_TPC_CFG_BASE 0x7FFFE415C0ull +#define KERNEL_TENSOR_8_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC7_EML_TPC_CFG_BASE 0x7FFFE415F8ull +#define KERNEL_TENSOR_9_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC7_EML_TPC_CFG_BASE 0x7FFFE41630ull +#define KERNEL_TENSOR_10_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC7_EML_TPC_CFG_BASE 0x7FFFE41668ull +#define KERNEL_TENSOR_11_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC7_EML_TPC_CFG_BASE 0x7FFFE416A0ull +#define KERNEL_TENSOR_12_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC7_EML_TPC_CFG_BASE 0x7FFFE416D8ull +#define KERNEL_TENSOR_13_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC7_EML_TPC_CFG_BASE 0x7FFFE41710ull +#define KERNEL_TENSOR_14_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC7_EML_TPC_CFG_BASE 0x7FFFE41748ull +#define KERNEL_TENSOR_15_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC7_EML_TPC_CFG_BASE 0x7FFFE41780ull +#define KERNEL_SYNC_OBJECT_TPC7_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC7_EML_TPC_CFG_SECTION 0x8000 +#define mmKERNEL_TPC7_EML_TPC_CFG_BASE 0x7FFFE41788ull +#define KERNEL_TPC7_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC7_EML_TPC_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC7_EML_TPC_CFG_BASE 0x7FFFE41A00ull +#define QM_TENSOR_0_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC7_EML_TPC_CFG_BASE 0x7FFFE41A38ull +#define QM_TENSOR_1_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC7_EML_TPC_CFG_BASE 0x7FFFE41A70ull +#define QM_TENSOR_2_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC7_EML_TPC_CFG_BASE 0x7FFFE41AA8ull +#define QM_TENSOR_3_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC7_EML_TPC_CFG_BASE 0x7FFFE41AE0ull +#define QM_TENSOR_4_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC7_EML_TPC_CFG_BASE 0x7FFFE41B18ull +#define QM_TENSOR_5_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC7_EML_TPC_CFG_BASE 0x7FFFE41B50ull +#define QM_TENSOR_6_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC7_EML_TPC_CFG_BASE 0x7FFFE41B88ull +#define QM_TENSOR_7_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC7_EML_TPC_CFG_BASE 0x7FFFE41BC0ull +#define QM_TENSOR_8_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC7_EML_TPC_CFG_BASE 0x7FFFE41BF8ull +#define QM_TENSOR_9_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC7_EML_TPC_CFG_BASE 0x7FFFE41C30ull +#define QM_TENSOR_10_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC7_EML_TPC_CFG_BASE 0x7FFFE41C68ull +#define QM_TENSOR_11_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC7_EML_TPC_CFG_BASE 0x7FFFE41CA0ull +#define QM_TENSOR_12_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC7_EML_TPC_CFG_BASE 0x7FFFE41CD8ull +#define QM_TENSOR_13_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D10ull +#define QM_TENSOR_14_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D48ull +#define QM_TENSOR_15_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D80ull +#define QM_SYNC_OBJECT_TPC7_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC7_EML_TPC_CFG_SECTION 0x8000 +#define mmQM_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D88ull +#define QM_TPC7_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define QM_TPC7_EML_TPC_CFG_SECTION 0x2780 +#define mmTPC7_EML_TPC_QM_BASE 0x7FFFE42000ull +#define TPC7_EML_TPC_QM_MAX_OFFSET 0xD040 +#define TPC7_EML_TPC_QM_SECTION 0x1BD000 +#define mmTPC7_EML_CS_BASE 0x7FFFFFF000ull +#define TPC7_EML_CS_MAX_OFFSET 0x1000 + +#endif /* GAUDI_BLOCKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/gaudi_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/gaudi_regs.h new file mode 100644 index 000000000000..85e3b5148595 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/gaudi_regs.h @@ -0,0 +1,299 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef ASIC_REG_GAUDI_REGS_H_ +#define ASIC_REG_GAUDI_REGS_H_ + +#include "gaudi_blocks.h" +#include "psoc_global_conf_regs.h" +#include "psoc_timestamp_regs.h" +#include "cpu_if_regs.h" +#include "mmu_up_regs.h" +#include "stlb_regs.h" +#include "dma0_qm_regs.h" +#include "dma1_qm_regs.h" +#include "dma2_qm_regs.h" +#include "dma3_qm_regs.h" +#include "dma4_qm_regs.h" +#include "dma5_qm_regs.h" +#include "dma6_qm_regs.h" +#include "dma7_qm_regs.h" +#include "dma0_core_regs.h" +#include "dma1_core_regs.h" +#include "dma2_core_regs.h" +#include "dma3_core_regs.h" +#include "dma4_core_regs.h" +#include "dma5_core_regs.h" +#include "dma6_core_regs.h" +#include "dma7_core_regs.h" +#include "mme0_ctrl_regs.h" +#include "mme1_ctrl_regs.h" +#include "mme2_ctrl_regs.h" +#include "mme3_ctrl_regs.h" +#include "mme0_qm_regs.h" +#include "mme2_qm_regs.h" +#include "tpc0_cfg_regs.h" +#include "tpc1_cfg_regs.h" +#include "tpc2_cfg_regs.h" +#include "tpc3_cfg_regs.h" +#include "tpc4_cfg_regs.h" +#include "tpc5_cfg_regs.h" +#include "tpc6_cfg_regs.h" +#include "tpc7_cfg_regs.h" +#include "tpc0_qm_regs.h" +#include "tpc1_qm_regs.h" +#include "tpc2_qm_regs.h" +#include "tpc3_qm_regs.h" +#include "tpc4_qm_regs.h" +#include "tpc5_qm_regs.h" +#include "tpc6_qm_regs.h" +#include "tpc7_qm_regs.h" +#include "dma_if_e_n_down_ch0_regs.h" +#include "dma_if_e_n_down_ch1_regs.h" +#include "dma_if_e_s_down_ch0_regs.h" +#include "dma_if_e_s_down_ch1_regs.h" +#include "dma_if_w_n_down_ch0_regs.h" +#include "dma_if_w_n_down_ch1_regs.h" +#include "dma_if_w_s_down_ch0_regs.h" +#include "dma_if_w_s_down_ch1_regs.h" +#include "dma_if_e_n_regs.h" +#include "dma_if_e_s_regs.h" +#include "dma_if_w_n_regs.h" +#include "dma_if_w_s_regs.h" +#include "nif_rtr_ctrl_0_regs.h" +#include "nif_rtr_ctrl_1_regs.h" +#include "nif_rtr_ctrl_2_regs.h" +#include "nif_rtr_ctrl_3_regs.h" +#include "nif_rtr_ctrl_4_regs.h" +#include "nif_rtr_ctrl_5_regs.h" +#include "nif_rtr_ctrl_6_regs.h" +#include "nif_rtr_ctrl_7_regs.h" +#include "sif_rtr_ctrl_0_regs.h" +#include "sif_rtr_ctrl_1_regs.h" +#include "sif_rtr_ctrl_2_regs.h" +#include "sif_rtr_ctrl_3_regs.h" +#include "sif_rtr_ctrl_4_regs.h" +#include "sif_rtr_ctrl_5_regs.h" +#include "sif_rtr_ctrl_6_regs.h" +#include "sif_rtr_ctrl_7_regs.h" +#include "psoc_etr_regs.h" + +#include "dma0_qm_masks.h" +#include "mme0_qm_masks.h" +#include "tpc0_qm_masks.h" +#include "dma0_core_masks.h" +#include "tpc0_cfg_masks.h" +#include "psoc_global_conf_masks.h" + +#include "psoc_pci_pll_regs.h" +#include "psoc_hbm_pll_regs.h" + +#define GAUDI_ECC_MEM_SEL_OFFSET 0xF18 +#define GAUDI_ECC_ADDRESS_OFFSET 0xF1C +#define GAUDI_ECC_SYNDROME_OFFSET 0xF20 +#define GAUDI_ECC_SERR0_OFFSET 0xF30 +#define GAUDI_ECC_SERR1_OFFSET 0xF34 +#define GAUDI_ECC_SERR2_OFFSET 0xF38 +#define GAUDI_ECC_SERR3_OFFSET 0xF3C +#define GAUDI_ECC_DERR0_OFFSET 0xF40 +#define GAUDI_ECC_DERR1_OFFSET 0xF44 +#define GAUDI_ECC_DERR2_OFFSET 0xF48 +#define GAUDI_ECC_DERR3_OFFSET 0xF4C + +#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0 0x492000 +#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 0x494000 +#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 0x494800 +#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_DATA_0 0x495000 +#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0 0x495800 +#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0 0x496000 +#define mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_SOB_OBJ_0 0x4B2000 +#define mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_MON_STATUS_0 0x4B6000 +#define mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_SOB_OBJ_0 0x4D2000 +#define mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_MON_STATUS_0 0x4D6000 +#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0 0x4F2000 +#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_1 0x4F2004 +#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_2047 0x4F3FFC +#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 0x4F4000 +#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_0 0x4F6000 +#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_511 0x4F67FC + +#define mmSIF_RTR_0_LBW_RANGE_PROT_HIT_AW 0x300400 +#define mmSIF_RTR_1_LBW_RANGE_PROT_HIT_AW 0x310400 +#define mmSIF_RTR_2_LBW_RANGE_PROT_HIT_AW 0x320400 +#define mmSIF_RTR_3_LBW_RANGE_PROT_HIT_AW 0x330400 +#define mmSIF_RTR_4_LBW_RANGE_PROT_HIT_AW 0x340400 +#define mmSIF_RTR_5_LBW_RANGE_PROT_HIT_AW 0x350400 +#define mmSIF_RTR_6_LBW_RANGE_PROT_HIT_AW 0x360400 +#define mmSIF_RTR_7_LBW_RANGE_PROT_HIT_AW 0x370400 + +#define mmSIF_RTR_0_LBW_RANGE_PROT_HIT_AR 0x300490 +#define mmSIF_RTR_1_LBW_RANGE_PROT_HIT_AR 0x310490 +#define mmSIF_RTR_2_LBW_RANGE_PROT_HIT_AR 0x320490 +#define mmSIF_RTR_3_LBW_RANGE_PROT_HIT_AR 0x330490 +#define mmSIF_RTR_4_LBW_RANGE_PROT_HIT_AR 0x340490 +#define mmSIF_RTR_5_LBW_RANGE_PROT_HIT_AR 0x350490 +#define mmSIF_RTR_6_LBW_RANGE_PROT_HIT_AR 0x360490 +#define mmSIF_RTR_7_LBW_RANGE_PROT_HIT_AR 0x370490 + +#define mmSIF_RTR_0_LBW_RANGE_PROT_MIN_AW_0 0x300410 +#define mmSIF_RTR_1_LBW_RANGE_PROT_MIN_AW_0 0x310410 +#define mmSIF_RTR_2_LBW_RANGE_PROT_MIN_AW_0 0x320410 +#define mmSIF_RTR_3_LBW_RANGE_PROT_MIN_AW_0 0x330410 +#define mmSIF_RTR_4_LBW_RANGE_PROT_MIN_AW_0 0x340410 +#define mmSIF_RTR_5_LBW_RANGE_PROT_MIN_AW_0 0x350410 +#define mmSIF_RTR_6_LBW_RANGE_PROT_MIN_AW_0 0x360410 +#define mmSIF_RTR_7_LBW_RANGE_PROT_MIN_AW_0 0x370410 + +#define mmSIF_RTR_0_LBW_RANGE_PROT_MAX_AW_0 0x300450 +#define mmSIF_RTR_1_LBW_RANGE_PROT_MAX_AW_0 0x310450 +#define mmSIF_RTR_2_LBW_RANGE_PROT_MAX_AW_0 0x320450 +#define mmSIF_RTR_3_LBW_RANGE_PROT_MAX_AW_0 0x330450 +#define mmSIF_RTR_4_LBW_RANGE_PROT_MAX_AW_0 0x340450 +#define mmSIF_RTR_5_LBW_RANGE_PROT_MAX_AW_0 0x350450 +#define mmSIF_RTR_6_LBW_RANGE_PROT_MAX_AW_0 0x360450 +#define mmSIF_RTR_7_LBW_RANGE_PROT_MAX_AW_0 0x370450 + +#define mmSIF_RTR_0_LBW_RANGE_PROT_MIN_AR_0 0x3004A0 +#define mmSIF_RTR_1_LBW_RANGE_PROT_MIN_AR_0 0x3104A0 +#define mmSIF_RTR_2_LBW_RANGE_PROT_MIN_AR_0 0x3204A0 +#define mmSIF_RTR_3_LBW_RANGE_PROT_MIN_AR_0 0x3304A0 +#define mmSIF_RTR_4_LBW_RANGE_PROT_MIN_AR_0 0x3404A0 +#define mmSIF_RTR_5_LBW_RANGE_PROT_MIN_AR_0 0x3504A0 +#define mmSIF_RTR_6_LBW_RANGE_PROT_MIN_AR_0 0x3604A0 +#define mmSIF_RTR_7_LBW_RANGE_PROT_MIN_AR_0 0x3704A0 + +#define mmSIF_RTR_0_LBW_RANGE_PROT_MAX_AR_0 0x3004E0 +#define mmSIF_RTR_1_LBW_RANGE_PROT_MAX_AR_0 0x3104E0 +#define mmSIF_RTR_2_LBW_RANGE_PROT_MAX_AR_0 0x3204E0 +#define mmSIF_RTR_3_LBW_RANGE_PROT_MAX_AR_0 0x3304E0 +#define mmSIF_RTR_4_LBW_RANGE_PROT_MAX_AR_0 0x3404E0 +#define mmSIF_RTR_5_LBW_RANGE_PROT_MAX_AR_0 0x3504E0 +#define mmSIF_RTR_6_LBW_RANGE_PROT_MAX_AR_0 0x3604E0 +#define mmSIF_RTR_7_LBW_RANGE_PROT_MAX_AR_0 0x3704E0 + +#define mmNIF_RTR_0_LBW_RANGE_PROT_HIT_AW 0x380400 +#define mmNIF_RTR_1_LBW_RANGE_PROT_HIT_AW 0x390400 +#define mmNIF_RTR_2_LBW_RANGE_PROT_HIT_AW 0x3A0400 +#define mmNIF_RTR_3_LBW_RANGE_PROT_HIT_AW 0x3B0400 +#define mmNIF_RTR_4_LBW_RANGE_PROT_HIT_AW 0x3C0400 +#define mmNIF_RTR_5_LBW_RANGE_PROT_HIT_AW 0x3D0400 +#define mmNIF_RTR_6_LBW_RANGE_PROT_HIT_AW 0x3E0400 +#define mmNIF_RTR_7_LBW_RANGE_PROT_HIT_AW 0x3F0400 + +#define mmNIF_RTR_0_LBW_RANGE_PROT_HIT_AR 0x380490 +#define mmNIF_RTR_1_LBW_RANGE_PROT_HIT_AR 0x390490 +#define mmNIF_RTR_2_LBW_RANGE_PROT_HIT_AR 0x3A0490 +#define mmNIF_RTR_3_LBW_RANGE_PROT_HIT_AR 0x3B0490 +#define mmNIF_RTR_4_LBW_RANGE_PROT_HIT_AR 0x3C0490 +#define mmNIF_RTR_5_LBW_RANGE_PROT_HIT_AR 0x3D0490 +#define mmNIF_RTR_6_LBW_RANGE_PROT_HIT_AR 0x3E0490 +#define mmNIF_RTR_7_LBW_RANGE_PROT_HIT_AR 0x3F0490 + +#define mmNIF_RTR_0_LBW_RANGE_PROT_MIN_AW_0 0x380410 +#define mmNIF_RTR_1_LBW_RANGE_PROT_MIN_AW_0 0x390410 +#define mmNIF_RTR_2_LBW_RANGE_PROT_MIN_AW_0 0x3A0410 +#define mmNIF_RTR_3_LBW_RANGE_PROT_MIN_AW_0 0x3B0410 +#define mmNIF_RTR_4_LBW_RANGE_PROT_MIN_AW_0 0x3C0410 +#define mmNIF_RTR_5_LBW_RANGE_PROT_MIN_AW_0 0x3D0410 +#define mmNIF_RTR_6_LBW_RANGE_PROT_MIN_AW_0 0x3E0410 +#define mmNIF_RTR_7_LBW_RANGE_PROT_MIN_AW_0 0x3F0410 + +#define mmNIF_RTR_0_LBW_RANGE_PROT_MAX_AW_0 0x380450 +#define mmNIF_RTR_1_LBW_RANGE_PROT_MAX_AW_0 0x390450 +#define mmNIF_RTR_2_LBW_RANGE_PROT_MAX_AW_0 0x3A0450 +#define mmNIF_RTR_3_LBW_RANGE_PROT_MAX_AW_0 0x3B0450 +#define mmNIF_RTR_4_LBW_RANGE_PROT_MAX_AW_0 0x3C0450 +#define mmNIF_RTR_5_LBW_RANGE_PROT_MAX_AW_0 0x3D0450 +#define mmNIF_RTR_6_LBW_RANGE_PROT_MAX_AW_0 0x3E0450 +#define mmNIF_RTR_7_LBW_RANGE_PROT_MAX_AW_0 0x3F0450 + +#define mmNIF_RTR_0_LBW_RANGE_PROT_MIN_AR_0 0x3804A0 +#define mmNIF_RTR_1_LBW_RANGE_PROT_MIN_AR_0 0x3904A0 +#define mmNIF_RTR_2_LBW_RANGE_PROT_MIN_AR_0 0x3A04A0 +#define mmNIF_RTR_3_LBW_RANGE_PROT_MIN_AR_0 0x3B04A0 +#define mmNIF_RTR_4_LBW_RANGE_PROT_MIN_AR_0 0x3C04A0 +#define mmNIF_RTR_5_LBW_RANGE_PROT_MIN_AR_0 0x3D04A0 +#define mmNIF_RTR_6_LBW_RANGE_PROT_MIN_AR_0 0x3E04A0 +#define mmNIF_RTR_7_LBW_RANGE_PROT_MIN_AR_0 0x3F04A0 + +#define mmNIF_RTR_0_LBW_RANGE_PROT_MAX_AR_0 0x3804E0 +#define mmNIF_RTR_1_LBW_RANGE_PROT_MAX_AR_0 0x3904E0 +#define mmNIF_RTR_2_LBW_RANGE_PROT_MAX_AR_0 0x3A04E0 +#define mmNIF_RTR_3_LBW_RANGE_PROT_MAX_AR_0 0x3B04E0 +#define mmNIF_RTR_4_LBW_RANGE_PROT_MAX_AR_0 0x3C04E0 +#define mmNIF_RTR_5_LBW_RANGE_PROT_MAX_AR_0 0x3D04E0 +#define mmNIF_RTR_6_LBW_RANGE_PROT_MAX_AR_0 0x3E04E0 +#define mmNIF_RTR_7_LBW_RANGE_PROT_MAX_AR_0 0x3F04E0 + +#define mmDMA_IF_W_S_DOWN_RSP_MID_WGHT_0 0x489030 +#define mmDMA_IF_W_S_DOWN_RSP_MID_WGHT_1 0x489034 + +#define mmDMA_IF_E_S_DOWN_RSP_MID_WGHT_0 0x4A9030 +#define mmDMA_IF_E_S_DOWN_RSP_MID_WGHT_1 0x4A9034 + +#define mmDMA_IF_W_N_DOWN_RSP_MID_WGHT_0 0x4C9030 +#define mmDMA_IF_W_N_DOWN_RSP_MID_WGHT_1 0x4C9034 + +#define mmDMA_IF_E_N_DOWN_RSP_MID_WGHT_0 0x4E9030 +#define mmDMA_IF_E_N_DOWN_RSP_MID_WGHT_1 0x4E9034 + +#define mmMME1_QM_GLBL_CFG0 0xE8000 +#define mmMME1_QM_GLBL_STS0 0xE8038 + +#define mmMME0_SBAB_SB_STALL 0x4002C +#define mmMME0_SBAB_ARUSER0 0x40034 +#define mmMME0_SBAB_ARUSER1 0x40038 +#define mmMME0_SBAB_PROT 0x40050 + +#define mmMME1_SBAB_SB_STALL 0xC002C +#define mmMME1_SBAB_ARUSER0 0xC0034 +#define mmMME1_SBAB_ARUSER1 0xC0038 +#define mmMME1_SBAB_PROT 0xC0050 + +#define mmMME2_SBAB_SB_STALL 0x14002C +#define mmMME2_SBAB_ARUSER0 0x140034 +#define mmMME2_SBAB_ARUSER1 0x140038 +#define mmMME2_SBAB_PROT 0x140050 + +#define mmMME3_SBAB_SB_STALL 0x1C002C +#define mmMME3_SBAB_ARUSER0 0x1C0034 +#define mmMME3_SBAB_ARUSER1 0x1C0038 +#define mmMME3_SBAB_PROT 0x1C0050 + +#define mmMME0_ACC_ACC_STALL 0x20028 +#define mmMME0_ACC_WBC 0x20038 +#define mmMME0_ACC_PROT 0x20050 + +#define mmMME1_ACC_ACC_STALL 0xA0028 +#define mmMME1_ACC_WBC 0xA0038 +#define mmMME1_ACC_PROT 0xA0050 + +#define mmMME2_ACC_ACC_STALL 0x120028 +#define mmMME2_ACC_WBC 0x120038 +#define mmMME2_ACC_PROT 0x120050 + +#define mmMME3_ACC_ACC_STALL 0x1A0028 +#define mmMME3_ACC_WBC 0x1A0038 +#define mmMME3_ACC_PROT 0x1A0050 + +#define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR 0x800040 + +#define mmPSOC_EFUSE_READ 0xC4A000 +#define mmPSOC_EFUSE_DATA_0 0xC4A080 + +#define mmPCIE_WRAP_MAX_OUTSTAND 0xC01B20 +#define mmPCIE_WRAP_LBW_PROT_OVR 0xC01B48 +#define mmPCIE_WRAP_HBW_DRAIN_CFG 0xC01D54 +#define mmPCIE_WRAP_LBW_DRAIN_CFG 0xC01D5C + +#define mmPCIE_MSI_INTR_0 0xC13000 + +#define mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG 0xC02000 + +#define mmPCIE_AUX_DBI 0xC07490 + +#endif /* ASIC_REG_GAUDI_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/mme0_ctrl_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme0_ctrl_regs.h new file mode 100644 index 000000000000..083d073a0128 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme0_ctrl_regs.h @@ -0,0 +1,1456 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME0_CTRL_REGS_H_ +#define ASIC_REG_MME0_CTRL_REGS_H_ + +/* + ***************************************** + * MME0_CTRL (Prototype: MME) + ***************************************** + */ + +#define mmMME0_CTRL_ARCH_STATUS 0x60000 + +#define mmMME0_CTRL_ARCH_BASE_ADDR_HIGH_S 0x60008 + +#define mmMME0_CTRL_ARCH_BASE_ADDR_HIGH_L 0x6000C + +#define mmMME0_CTRL_ARCH_BASE_ADDR_HIGH_O 0x60010 + +#define mmMME0_CTRL_ARCH_BASE_ADDR_LOW_S 0x60014 + +#define mmMME0_CTRL_ARCH_BASE_ADDR_LOW_L 0x60018 + +#define mmMME0_CTRL_ARCH_BASE_ADDR_LOW_O 0x6001C + +#define mmMME0_CTRL_ARCH_HEADER_LOW 0x60020 + +#define mmMME0_CTRL_ARCH_HEADER_HIGH 0x60024 + +#define mmMME0_CTRL_ARCH_CONV_KERNEL_SIZE_MINUS_1 0x60028 + +#define mmMME0_CTRL_ARCH_CONV_ASSOCIATED_DIMS_LOW 0x6002C + +#define mmMME0_CTRL_ARCH_CONV_ASSOCIATED_DIMS_HIGH 0x60030 + +#define mmMME0_CTRL_ARCH_NUM_ITERATIONS_MINUS_1 0x60034 + +#define mmMME0_CTRL_ARCH_OUTER_LOOP 0x60038 + +#define mmMME0_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_0 0x6003C + +#define mmMME0_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_1 0x60040 + +#define mmMME0_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_2 0x60044 + +#define mmMME0_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_3 0x60048 + +#define mmMME0_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_4 0x6004C + +#define mmMME0_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_0 0x60050 + +#define mmMME0_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_1 0x60054 + +#define mmMME0_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_2 0x60058 + +#define mmMME0_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_3 0x6005C + +#define mmMME0_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_4 0x60060 + +#define mmMME0_CTRL_ARCH_TENSOR_S_ROI_SIZE_0 0x60064 + +#define mmMME0_CTRL_ARCH_TENSOR_S_ROI_SIZE_1 0x60068 + +#define mmMME0_CTRL_ARCH_TENSOR_S_ROI_SIZE_2 0x6006C + +#define mmMME0_CTRL_ARCH_TENSOR_S_ROI_SIZE_3 0x60070 + +#define mmMME0_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_0 0x60074 + +#define mmMME0_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_1 0x60078 + +#define mmMME0_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_2 0x6007C + +#define mmMME0_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_3 0x60080 + +#define mmMME0_CTRL_ARCH_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x60084 + +#define mmMME0_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_0 0x60088 + +#define mmMME0_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_1 0x6008C + +#define mmMME0_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_2 0x60090 + +#define mmMME0_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_3 0x60094 + +#define mmMME0_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_4 0x60098 + +#define mmMME0_CTRL_ARCH_AGU_S_START_OFFSET_0 0x6009C + +#define mmMME0_CTRL_ARCH_AGU_S_START_OFFSET_1 0x600A0 + +#define mmMME0_CTRL_ARCH_AGU_S_START_OFFSET_2 0x600A4 + +#define mmMME0_CTRL_ARCH_AGU_S_START_OFFSET_3 0x600A8 + +#define mmMME0_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_0 0x600AC + +#define mmMME0_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_1 0x600B0 + +#define mmMME0_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_2 0x600B4 + +#define mmMME0_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_3 0x600B8 + +#define mmMME0_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_4 0x600BC + +#define mmMME0_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_0 0x600C0 + +#define mmMME0_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_1 0x600C4 + +#define mmMME0_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_2 0x600C8 + +#define mmMME0_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_3 0x600CC + +#define mmMME0_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_4 0x600D0 + +#define mmMME0_CTRL_ARCH_TENSOR_L_ROI_SIZE_0 0x600D4 + +#define mmMME0_CTRL_ARCH_TENSOR_L_ROI_SIZE_1 0x600D8 + +#define mmMME0_CTRL_ARCH_TENSOR_L_ROI_SIZE_2 0x600DC + +#define mmMME0_CTRL_ARCH_TENSOR_L_ROI_SIZE_3 0x600E0 + +#define mmMME0_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_0 0x600E4 + +#define mmMME0_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_1 0x600E8 + +#define mmMME0_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_2 0x600EC + +#define mmMME0_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_3 0x600F0 + +#define mmMME0_CTRL_ARCH_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x600F4 + +#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x600F8 + +#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x600FC + +#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x60100 + +#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x60104 + +#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x60108 + +#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_0 0x6010C + +#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_1 0x60110 + +#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_2 0x60114 + +#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_3 0x60118 + +#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x6011C + +#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x60120 + +#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x60124 + +#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x60128 + +#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x6012C + +#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_0 0x60130 + +#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_1 0x60134 + +#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_2 0x60138 + +#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_3 0x6013C + +#define mmMME0_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_0 0x60140 + +#define mmMME0_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_1 0x60144 + +#define mmMME0_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_2 0x60148 + +#define mmMME0_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_3 0x6014C + +#define mmMME0_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_4 0x60150 + +#define mmMME0_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_0 0x60154 + +#define mmMME0_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_1 0x60158 + +#define mmMME0_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_2 0x6015C + +#define mmMME0_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_3 0x60160 + +#define mmMME0_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_4 0x60164 + +#define mmMME0_CTRL_ARCH_TENSOR_O_ROI_SIZE_0 0x60168 + +#define mmMME0_CTRL_ARCH_TENSOR_O_ROI_SIZE_1 0x6016C + +#define mmMME0_CTRL_ARCH_TENSOR_O_ROI_SIZE_2 0x60170 + +#define mmMME0_CTRL_ARCH_TENSOR_O_ROI_SIZE_3 0x60174 + +#define mmMME0_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_0 0x60178 + +#define mmMME0_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_1 0x6017C + +#define mmMME0_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_2 0x60180 + +#define mmMME0_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_3 0x60184 + +#define mmMME0_CTRL_ARCH_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x60188 + +#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x6018C + +#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x60190 + +#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x60194 + +#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x60198 + +#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x6019C + +#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_0 0x601A0 + +#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_1 0x601A4 + +#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_2 0x601A8 + +#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_3 0x601AC + +#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x601B0 + +#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x601B4 + +#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x601B8 + +#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x601BC + +#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x601C0 + +#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_0 0x601C4 + +#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_1 0x601C8 + +#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_2 0x601CC + +#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_3 0x601D0 + +#define mmMME0_CTRL_ARCH_DESC_SB_REPEAT 0x601D4 + +#define mmMME0_CTRL_ARCH_DESC_RATE_LIMITER 0x601D8 + +#define mmMME0_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x601DC + +#define mmMME0_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x601E0 + +#define mmMME0_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_HIGH 0x601E4 + +#define mmMME0_CTRL_ARCH_DESC_SYNC_OBJECT_DATA 0x601E8 + +#define mmMME0_CTRL_ARCH_DESC_AXI_USER_DATA 0x601EC + +#define mmMME0_CTRL_ARCH_DESC_PERF_EVT_S 0x601F0 + +#define mmMME0_CTRL_ARCH_DESC_PERF_EVT_L_LOCAL 0x601F4 + +#define mmMME0_CTRL_ARCH_DESC_PERF_EVT_L_REMOTE 0x601F8 + +#define mmMME0_CTRL_ARCH_DESC_PERF_EVT_O_LOCAL 0x601FC + +#define mmMME0_CTRL_ARCH_DESC_PERF_EVT_O_REMOTE 0x60200 + +#define mmMME0_CTRL_ARCH_DESC_PADDING_VALUE_S 0x60204 + +#define mmMME0_CTRL_ARCH_DESC_PADDING_VALUE_L 0x60208 + +#define mmMME0_CTRL_ARCH_DESC_META_DATA_AGU_S 0x6020C + +#define mmMME0_CTRL_ARCH_DESC_META_DATA_AGU_L_LOCAL 0x60210 + +#define mmMME0_CTRL_ARCH_DESC_META_DATA_AGU_L_REMOTE 0x60214 + +#define mmMME0_CTRL_ARCH_DESC_META_DATA_AGU_O_LOCAL 0x60218 + +#define mmMME0_CTRL_ARCH_DESC_META_DATA_AGU_O_REMOTE 0x6021C + +#define mmMME0_CTRL_ARCH_DESC_PCU_RL_SATURATION 0x60220 + +#define mmMME0_CTRL_ARCH_DESC_DUMMY 0x60224 + +#define mmMME0_CTRL_CMD 0x60280 + +#define mmMME0_CTRL_STATUS1 0x60284 + +#define mmMME0_CTRL_RESET 0x60288 + +#define mmMME0_CTRL_QM_STALL 0x6028C + +#define mmMME0_CTRL_SYNC_OBJECT_FIFO_TH 0x60290 + +#define mmMME0_CTRL_EUS_ROLLUP_CNT_ADD 0x60294 + +#define mmMME0_CTRL_INTR_CAUSE 0x60298 + +#define mmMME0_CTRL_INTR_MASK 0x6029C + +#define mmMME0_CTRL_LOG_SHADOW 0x602A0 + +#define mmMME0_CTRL_PCU_RL_DESC0 0x602A4 + +#define mmMME0_CTRL_PCU_RL_TOKEN_UPDATE 0x602A8 + +#define mmMME0_CTRL_PCU_RL_TH 0x602AC + +#define mmMME0_CTRL_PCU_RL_MIN 0x602B0 + +#define mmMME0_CTRL_PCU_RL_CTRL_EN 0x602B4 + +#define mmMME0_CTRL_PCU_RL_HISTORY_LOG_SIZE 0x602B8 + +#define mmMME0_CTRL_PCU_DUMMY_A_BF16 0x602BC + +#define mmMME0_CTRL_PCU_DUMMY_B_BF16 0x602C0 + +#define mmMME0_CTRL_PCU_DUMMY_A_FP32_ODD 0x602C4 + +#define mmMME0_CTRL_PCU_DUMMY_A_FP32_EVEN 0x602C8 + +#define mmMME0_CTRL_PCU_DUMMY_B_FP32_ODD 0x602CC + +#define mmMME0_CTRL_PCU_DUMMY_B_FP32_EVEN 0x602D0 + +#define mmMME0_CTRL_PROT 0x602D4 + +#define mmMME0_CTRL_EU_POWER_SAVE_DISABLE 0x602D8 + +#define mmMME0_CTRL_CS_DBG_BLOCK_ID 0x602DC + +#define mmMME0_CTRL_CS_DBG_STATUS_DROP_CNT 0x602E0 + +#define mmMME0_CTRL_TE_CLOSE_CGATE 0x602E4 + +#define mmMME0_CTRL_AGU_SM_INFLIGHT_CNTR 0x602E8 + +#define mmMME0_CTRL_AGU_SM_TOTAL_CNTR 0x602EC + +#define mmMME0_CTRL_EZSYNC_OUT_CREDIT 0x602F0 + +#define mmMME0_CTRL_PCU_RL_SAT_SEC 0x602F4 + +#define mmMME0_CTRL_AGU_SYNC_MSG_AXI_USER 0x602F8 + +#define mmMME0_CTRL_QM_SLV_LBW_CLK_EN 0x602FC + +#define mmMME0_CTRL_SHADOW_0_STATUS 0x60400 + +#define mmMME0_CTRL_SHADOW_0_BASE_ADDR_HIGH_S 0x60408 + +#define mmMME0_CTRL_SHADOW_0_BASE_ADDR_HIGH_L 0x6040C + +#define mmMME0_CTRL_SHADOW_0_BASE_ADDR_HIGH_O 0x60410 + +#define mmMME0_CTRL_SHADOW_0_BASE_ADDR_LOW_S 0x60414 + +#define mmMME0_CTRL_SHADOW_0_BASE_ADDR_LOW_L 0x60418 + +#define mmMME0_CTRL_SHADOW_0_BASE_ADDR_LOW_O 0x6041C + +#define mmMME0_CTRL_SHADOW_0_HEADER_LOW 0x60420 + +#define mmMME0_CTRL_SHADOW_0_HEADER_HIGH 0x60424 + +#define mmMME0_CTRL_SHADOW_0_CONV_KERNEL_SIZE_MINUS_1 0x60428 + +#define mmMME0_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_LOW 0x6042C + +#define mmMME0_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_HIGH 0x60430 + +#define mmMME0_CTRL_SHADOW_0_NUM_ITERATIONS_MINUS_1 0x60434 + +#define mmMME0_CTRL_SHADOW_0_OUTER_LOOP 0x60438 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_0 0x6043C + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_1 0x60440 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_2 0x60444 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_3 0x60448 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_4 0x6044C + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_0 0x60450 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_1 0x60454 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_2 0x60458 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_3 0x6045C + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_4 0x60460 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_0 0x60464 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_1 0x60468 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_2 0x6046C + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_3 0x60470 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_0 0x60474 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_1 0x60478 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_2 0x6047C + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_3 0x60480 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x60484 + +#define mmMME0_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_0 0x60488 + +#define mmMME0_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_1 0x6048C + +#define mmMME0_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_2 0x60490 + +#define mmMME0_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_3 0x60494 + +#define mmMME0_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_4 0x60498 + +#define mmMME0_CTRL_SHADOW_0_AGU_S_START_OFFSET_0 0x6049C + +#define mmMME0_CTRL_SHADOW_0_AGU_S_START_OFFSET_1 0x604A0 + +#define mmMME0_CTRL_SHADOW_0_AGU_S_START_OFFSET_2 0x604A4 + +#define mmMME0_CTRL_SHADOW_0_AGU_S_START_OFFSET_3 0x604A8 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_0 0x604AC + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_1 0x604B0 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_2 0x604B4 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_3 0x604B8 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_4 0x604BC + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_0 0x604C0 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_1 0x604C4 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_2 0x604C8 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_3 0x604CC + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_4 0x604D0 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_0 0x604D4 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_1 0x604D8 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_2 0x604DC + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_3 0x604E0 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_0 0x604E4 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_1 0x604E8 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_2 0x604EC + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_3 0x604F0 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x604F4 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x604F8 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x604FC + +#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x60500 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x60504 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x60508 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_0 0x6050C + +#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_1 0x60510 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_2 0x60514 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_3 0x60518 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x6051C + +#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x60520 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x60524 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x60528 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x6052C + +#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_0 0x60530 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_1 0x60534 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_2 0x60538 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_3 0x6053C + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_0 0x60540 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_1 0x60544 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_2 0x60548 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_3 0x6054C + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_4 0x60550 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_0 0x60554 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_1 0x60558 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_2 0x6055C + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_3 0x60560 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_4 0x60564 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_0 0x60568 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_1 0x6056C + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_2 0x60570 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_3 0x60574 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_0 0x60578 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_1 0x6057C + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_2 0x60580 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_3 0x60584 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x60588 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x6058C + +#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x60590 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x60594 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x60598 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x6059C + +#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_0 0x605A0 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_1 0x605A4 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_2 0x605A8 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_3 0x605AC + +#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x605B0 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x605B4 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x605B8 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x605BC + +#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x605C0 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_0 0x605C4 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_1 0x605C8 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_2 0x605CC + +#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_3 0x605D0 + +#define mmMME0_CTRL_SHADOW_0_DESC_SB_REPEAT 0x605D4 + +#define mmMME0_CTRL_SHADOW_0_DESC_RATE_LIMITER 0x605D8 + +#define mmMME0_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x605DC + +#define mmMME0_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x605E0 + +#define mmMME0_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_HIGH 0x605E4 + +#define mmMME0_CTRL_SHADOW_0_DESC_SYNC_OBJECT_DATA 0x605E8 + +#define mmMME0_CTRL_SHADOW_0_DESC_AXI_USER_DATA 0x605EC + +#define mmMME0_CTRL_SHADOW_0_DESC_PERF_EVT_S 0x605F0 + +#define mmMME0_CTRL_SHADOW_0_DESC_PERF_EVT_L_LOCAL 0x605F4 + +#define mmMME0_CTRL_SHADOW_0_DESC_PERF_EVT_L_REMOTE 0x605F8 + +#define mmMME0_CTRL_SHADOW_0_DESC_PERF_EVT_O_LOCAL 0x605FC + +#define mmMME0_CTRL_SHADOW_0_DESC_PERF_EVT_O_REMOTE 0x60600 + +#define mmMME0_CTRL_SHADOW_0_DESC_PADDING_VALUE_S 0x60604 + +#define mmMME0_CTRL_SHADOW_0_DESC_PADDING_VALUE_L 0x60608 + +#define mmMME0_CTRL_SHADOW_0_DESC_META_DATA_AGU_S 0x6060C + +#define mmMME0_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_LOCAL 0x60610 + +#define mmMME0_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_REMOTE 0x60614 + +#define mmMME0_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_LOCAL 0x60618 + +#define mmMME0_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_REMOTE 0x6061C + +#define mmMME0_CTRL_SHADOW_0_DESC_PCU_RL_SATURATION 0x60620 + +#define mmMME0_CTRL_SHADOW_0_DESC_DUMMY 0x60624 + +#define mmMME0_CTRL_SHADOW_1_STATUS 0x60680 + +#define mmMME0_CTRL_SHADOW_1_BASE_ADDR_HIGH_S 0x60688 + +#define mmMME0_CTRL_SHADOW_1_BASE_ADDR_HIGH_L 0x6068C + +#define mmMME0_CTRL_SHADOW_1_BASE_ADDR_HIGH_O 0x60690 + +#define mmMME0_CTRL_SHADOW_1_BASE_ADDR_LOW_S 0x60694 + +#define mmMME0_CTRL_SHADOW_1_BASE_ADDR_LOW_L 0x60698 + +#define mmMME0_CTRL_SHADOW_1_BASE_ADDR_LOW_O 0x6069C + +#define mmMME0_CTRL_SHADOW_1_HEADER_LOW 0x606A0 + +#define mmMME0_CTRL_SHADOW_1_HEADER_HIGH 0x606A4 + +#define mmMME0_CTRL_SHADOW_1_CONV_KERNEL_SIZE_MINUS_1 0x606A8 + +#define mmMME0_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_LOW 0x606AC + +#define mmMME0_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_HIGH 0x606B0 + +#define mmMME0_CTRL_SHADOW_1_NUM_ITERATIONS_MINUS_1 0x606B4 + +#define mmMME0_CTRL_SHADOW_1_OUTER_LOOP 0x606B8 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_0 0x606BC + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_1 0x606C0 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_2 0x606C4 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_3 0x606C8 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_4 0x606CC + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_0 0x606D0 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_1 0x606D4 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_2 0x606D8 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_3 0x606DC + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_4 0x606E0 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_0 0x606E4 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_1 0x606E8 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_2 0x606EC + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_3 0x606F0 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_0 0x606F4 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_1 0x606F8 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_2 0x606FC + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_3 0x60700 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x60704 + +#define mmMME0_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_0 0x60708 + +#define mmMME0_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_1 0x6070C + +#define mmMME0_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_2 0x60710 + +#define mmMME0_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_3 0x60714 + +#define mmMME0_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_4 0x60718 + +#define mmMME0_CTRL_SHADOW_1_AGU_S_START_OFFSET_0 0x6071C + +#define mmMME0_CTRL_SHADOW_1_AGU_S_START_OFFSET_1 0x60720 + +#define mmMME0_CTRL_SHADOW_1_AGU_S_START_OFFSET_2 0x60724 + +#define mmMME0_CTRL_SHADOW_1_AGU_S_START_OFFSET_3 0x60728 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_0 0x6072C + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_1 0x60730 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_2 0x60734 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_3 0x60738 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_4 0x6073C + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_0 0x60740 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_1 0x60744 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_2 0x60748 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_3 0x6074C + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_4 0x60750 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_0 0x60754 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_1 0x60758 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_2 0x6075C + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_3 0x60760 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_0 0x60764 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_1 0x60768 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_2 0x6076C + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_3 0x60770 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x60774 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x60778 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x6077C + +#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x60780 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x60784 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x60788 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_0 0x6078C + +#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_1 0x60790 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_2 0x60794 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_3 0x60798 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x6079C + +#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x607A0 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x607A4 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x607A8 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x607AC + +#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_0 0x607B0 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_1 0x607B4 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_2 0x607B8 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_3 0x607BC + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_0 0x607C0 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_1 0x607C4 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_2 0x607C8 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_3 0x607CC + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_4 0x607D0 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_0 0x607D4 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_1 0x607D8 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_2 0x607DC + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_3 0x607E0 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_4 0x607E4 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_0 0x607E8 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_1 0x607EC + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_2 0x607F0 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_3 0x607F4 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_0 0x607F8 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_1 0x607FC + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_2 0x60800 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_3 0x60804 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x60808 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x6080C + +#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x60810 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x60814 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x60818 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x6081C + +#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_0 0x60820 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_1 0x60824 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_2 0x60828 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_3 0x6082C + +#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x60830 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x60834 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x60838 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x6083C + +#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x60840 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_0 0x60844 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_1 0x60848 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_2 0x6084C + +#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_3 0x60850 + +#define mmMME0_CTRL_SHADOW_1_DESC_SB_REPEAT 0x60854 + +#define mmMME0_CTRL_SHADOW_1_DESC_RATE_LIMITER 0x60858 + +#define mmMME0_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x6085C + +#define mmMME0_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x60860 + +#define mmMME0_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_HIGH 0x60864 + +#define mmMME0_CTRL_SHADOW_1_DESC_SYNC_OBJECT_DATA 0x60868 + +#define mmMME0_CTRL_SHADOW_1_DESC_AXI_USER_DATA 0x6086C + +#define mmMME0_CTRL_SHADOW_1_DESC_PERF_EVT_S 0x60870 + +#define mmMME0_CTRL_SHADOW_1_DESC_PERF_EVT_L_LOCAL 0x60874 + +#define mmMME0_CTRL_SHADOW_1_DESC_PERF_EVT_L_REMOTE 0x60878 + +#define mmMME0_CTRL_SHADOW_1_DESC_PERF_EVT_O_LOCAL 0x6087C + +#define mmMME0_CTRL_SHADOW_1_DESC_PERF_EVT_O_REMOTE 0x60880 + +#define mmMME0_CTRL_SHADOW_1_DESC_PADDING_VALUE_S 0x60884 + +#define mmMME0_CTRL_SHADOW_1_DESC_PADDING_VALUE_L 0x60888 + +#define mmMME0_CTRL_SHADOW_1_DESC_META_DATA_AGU_S 0x6088C + +#define mmMME0_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_LOCAL 0x60890 + +#define mmMME0_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_REMOTE 0x60894 + +#define mmMME0_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_LOCAL 0x60898 + +#define mmMME0_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_REMOTE 0x6089C + +#define mmMME0_CTRL_SHADOW_1_DESC_PCU_RL_SATURATION 0x608A0 + +#define mmMME0_CTRL_SHADOW_1_DESC_DUMMY 0x608A4 + +#define mmMME0_CTRL_SHADOW_2_STATUS 0x60900 + +#define mmMME0_CTRL_SHADOW_2_BASE_ADDR_HIGH_S 0x60908 + +#define mmMME0_CTRL_SHADOW_2_BASE_ADDR_HIGH_L 0x6090C + +#define mmMME0_CTRL_SHADOW_2_BASE_ADDR_HIGH_O 0x60910 + +#define mmMME0_CTRL_SHADOW_2_BASE_ADDR_LOW_S 0x60914 + +#define mmMME0_CTRL_SHADOW_2_BASE_ADDR_LOW_L 0x60918 + +#define mmMME0_CTRL_SHADOW_2_BASE_ADDR_LOW_O 0x6091C + +#define mmMME0_CTRL_SHADOW_2_HEADER_LOW 0x60920 + +#define mmMME0_CTRL_SHADOW_2_HEADER_HIGH 0x60924 + +#define mmMME0_CTRL_SHADOW_2_CONV_KERNEL_SIZE_MINUS_1 0x60928 + +#define mmMME0_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_LOW 0x6092C + +#define mmMME0_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_HIGH 0x60930 + +#define mmMME0_CTRL_SHADOW_2_NUM_ITERATIONS_MINUS_1 0x60934 + +#define mmMME0_CTRL_SHADOW_2_OUTER_LOOP 0x60938 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_0 0x6093C + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_1 0x60940 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_2 0x60944 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_3 0x60948 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_4 0x6094C + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_0 0x60950 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_1 0x60954 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_2 0x60958 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_3 0x6095C + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_4 0x60960 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_0 0x60964 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_1 0x60968 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_2 0x6096C + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_3 0x60970 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_0 0x60974 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_1 0x60978 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_2 0x6097C + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_3 0x60980 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x60984 + +#define mmMME0_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_0 0x60988 + +#define mmMME0_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_1 0x6098C + +#define mmMME0_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_2 0x60990 + +#define mmMME0_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_3 0x60994 + +#define mmMME0_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_4 0x60998 + +#define mmMME0_CTRL_SHADOW_2_AGU_S_START_OFFSET_0 0x6099C + +#define mmMME0_CTRL_SHADOW_2_AGU_S_START_OFFSET_1 0x609A0 + +#define mmMME0_CTRL_SHADOW_2_AGU_S_START_OFFSET_2 0x609A4 + +#define mmMME0_CTRL_SHADOW_2_AGU_S_START_OFFSET_3 0x609A8 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_0 0x609AC + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_1 0x609B0 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_2 0x609B4 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_3 0x609B8 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_4 0x609BC + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_0 0x609C0 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_1 0x609C4 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_2 0x609C8 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_3 0x609CC + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_4 0x609D0 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_0 0x609D4 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_1 0x609D8 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_2 0x609DC + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_3 0x609E0 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_0 0x609E4 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_1 0x609E8 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_2 0x609EC + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_3 0x609F0 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x609F4 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x609F8 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x609FC + +#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x60A00 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x60A04 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x60A08 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_0 0x60A0C + +#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_1 0x60A10 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_2 0x60A14 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_3 0x60A18 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x60A1C + +#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x60A20 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x60A24 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x60A28 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x60A2C + +#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_0 0x60A30 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_1 0x60A34 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_2 0x60A38 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_3 0x60A3C + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_0 0x60A40 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_1 0x60A44 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_2 0x60A48 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_3 0x60A4C + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_4 0x60A50 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_0 0x60A54 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_1 0x60A58 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_2 0x60A5C + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_3 0x60A60 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_4 0x60A64 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_0 0x60A68 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_1 0x60A6C + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_2 0x60A70 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_3 0x60A74 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_0 0x60A78 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_1 0x60A7C + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_2 0x60A80 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_3 0x60A84 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x60A88 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x60A8C + +#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x60A90 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x60A94 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x60A98 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x60A9C + +#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_0 0x60AA0 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_1 0x60AA4 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_2 0x60AA8 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_3 0x60AAC + +#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x60AB0 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x60AB4 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x60AB8 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x60ABC + +#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x60AC0 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_0 0x60AC4 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_1 0x60AC8 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_2 0x60ACC + +#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_3 0x60AD0 + +#define mmMME0_CTRL_SHADOW_2_DESC_SB_REPEAT 0x60AD4 + +#define mmMME0_CTRL_SHADOW_2_DESC_RATE_LIMITER 0x60AD8 + +#define mmMME0_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x60ADC + +#define mmMME0_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x60AE0 + +#define mmMME0_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_HIGH 0x60AE4 + +#define mmMME0_CTRL_SHADOW_2_DESC_SYNC_OBJECT_DATA 0x60AE8 + +#define mmMME0_CTRL_SHADOW_2_DESC_AXI_USER_DATA 0x60AEC + +#define mmMME0_CTRL_SHADOW_2_DESC_PERF_EVT_S 0x60AF0 + +#define mmMME0_CTRL_SHADOW_2_DESC_PERF_EVT_L_LOCAL 0x60AF4 + +#define mmMME0_CTRL_SHADOW_2_DESC_PERF_EVT_L_REMOTE 0x60AF8 + +#define mmMME0_CTRL_SHADOW_2_DESC_PERF_EVT_O_LOCAL 0x60AFC + +#define mmMME0_CTRL_SHADOW_2_DESC_PERF_EVT_O_REMOTE 0x60B00 + +#define mmMME0_CTRL_SHADOW_2_DESC_PADDING_VALUE_S 0x60B04 + +#define mmMME0_CTRL_SHADOW_2_DESC_PADDING_VALUE_L 0x60B08 + +#define mmMME0_CTRL_SHADOW_2_DESC_META_DATA_AGU_S 0x60B0C + +#define mmMME0_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_LOCAL 0x60B10 + +#define mmMME0_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_REMOTE 0x60B14 + +#define mmMME0_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_LOCAL 0x60B18 + +#define mmMME0_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_REMOTE 0x60B1C + +#define mmMME0_CTRL_SHADOW_2_DESC_PCU_RL_SATURATION 0x60B20 + +#define mmMME0_CTRL_SHADOW_2_DESC_DUMMY 0x60B24 + +#define mmMME0_CTRL_SHADOW_3_STATUS 0x60B80 + +#define mmMME0_CTRL_SHADOW_3_BASE_ADDR_HIGH_S 0x60B88 + +#define mmMME0_CTRL_SHADOW_3_BASE_ADDR_HIGH_L 0x60B8C + +#define mmMME0_CTRL_SHADOW_3_BASE_ADDR_HIGH_O 0x60B90 + +#define mmMME0_CTRL_SHADOW_3_BASE_ADDR_LOW_S 0x60B94 + +#define mmMME0_CTRL_SHADOW_3_BASE_ADDR_LOW_L 0x60B98 + +#define mmMME0_CTRL_SHADOW_3_BASE_ADDR_LOW_O 0x60B9C + +#define mmMME0_CTRL_SHADOW_3_HEADER_LOW 0x60BA0 + +#define mmMME0_CTRL_SHADOW_3_HEADER_HIGH 0x60BA4 + +#define mmMME0_CTRL_SHADOW_3_CONV_KERNEL_SIZE_MINUS_1 0x60BA8 + +#define mmMME0_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_LOW 0x60BAC + +#define mmMME0_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_HIGH 0x60BB0 + +#define mmMME0_CTRL_SHADOW_3_NUM_ITERATIONS_MINUS_1 0x60BB4 + +#define mmMME0_CTRL_SHADOW_3_OUTER_LOOP 0x60BB8 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_0 0x60BBC + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_1 0x60BC0 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_2 0x60BC4 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_3 0x60BC8 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_4 0x60BCC + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_0 0x60BD0 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_1 0x60BD4 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_2 0x60BD8 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_3 0x60BDC + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_4 0x60BE0 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_0 0x60BE4 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_1 0x60BE8 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_2 0x60BEC + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_3 0x60BF0 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_0 0x60BF4 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_1 0x60BF8 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_2 0x60BFC + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_3 0x60C00 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x60C04 + +#define mmMME0_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_0 0x60C08 + +#define mmMME0_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_1 0x60C0C + +#define mmMME0_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_2 0x60C10 + +#define mmMME0_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_3 0x60C14 + +#define mmMME0_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_4 0x60C18 + +#define mmMME0_CTRL_SHADOW_3_AGU_S_START_OFFSET_0 0x60C1C + +#define mmMME0_CTRL_SHADOW_3_AGU_S_START_OFFSET_1 0x60C20 + +#define mmMME0_CTRL_SHADOW_3_AGU_S_START_OFFSET_2 0x60C24 + +#define mmMME0_CTRL_SHADOW_3_AGU_S_START_OFFSET_3 0x60C28 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_0 0x60C2C + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_1 0x60C30 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_2 0x60C34 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_3 0x60C38 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_4 0x60C3C + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_0 0x60C40 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_1 0x60C44 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_2 0x60C48 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_3 0x60C4C + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_4 0x60C50 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_0 0x60C54 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_1 0x60C58 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_2 0x60C5C + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_3 0x60C60 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_0 0x60C64 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_1 0x60C68 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_2 0x60C6C + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_3 0x60C70 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x60C74 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x60C78 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x60C7C + +#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x60C80 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x60C84 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x60C88 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_0 0x60C8C + +#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_1 0x60C90 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_2 0x60C94 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_3 0x60C98 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x60C9C + +#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x60CA0 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x60CA4 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x60CA8 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x60CAC + +#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_0 0x60CB0 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_1 0x60CB4 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_2 0x60CB8 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_3 0x60CBC + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_0 0x60CC0 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_1 0x60CC4 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_2 0x60CC8 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_3 0x60CCC + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_4 0x60CD0 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_0 0x60CD4 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_1 0x60CD8 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_2 0x60CDC + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_3 0x60CE0 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_4 0x60CE4 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_0 0x60CE8 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_1 0x60CEC + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_2 0x60CF0 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_3 0x60CF4 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_0 0x60CF8 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_1 0x60CFC + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_2 0x60D00 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_3 0x60D04 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x60D08 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x60D0C + +#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x60D10 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x60D14 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x60D18 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x60D1C + +#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_0 0x60D20 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_1 0x60D24 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_2 0x60D28 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_3 0x60D2C + +#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x60D30 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x60D34 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x60D38 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x60D3C + +#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x60D40 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_0 0x60D44 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_1 0x60D48 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_2 0x60D4C + +#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_3 0x60D50 + +#define mmMME0_CTRL_SHADOW_3_DESC_SB_REPEAT 0x60D54 + +#define mmMME0_CTRL_SHADOW_3_DESC_RATE_LIMITER 0x60D58 + +#define mmMME0_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x60D5C + +#define mmMME0_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x60D60 + +#define mmMME0_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_HIGH 0x60D64 + +#define mmMME0_CTRL_SHADOW_3_DESC_SYNC_OBJECT_DATA 0x60D68 + +#define mmMME0_CTRL_SHADOW_3_DESC_AXI_USER_DATA 0x60D6C + +#define mmMME0_CTRL_SHADOW_3_DESC_PERF_EVT_S 0x60D70 + +#define mmMME0_CTRL_SHADOW_3_DESC_PERF_EVT_L_LOCAL 0x60D74 + +#define mmMME0_CTRL_SHADOW_3_DESC_PERF_EVT_L_REMOTE 0x60D78 + +#define mmMME0_CTRL_SHADOW_3_DESC_PERF_EVT_O_LOCAL 0x60D7C + +#define mmMME0_CTRL_SHADOW_3_DESC_PERF_EVT_O_REMOTE 0x60D80 + +#define mmMME0_CTRL_SHADOW_3_DESC_PADDING_VALUE_S 0x60D84 + +#define mmMME0_CTRL_SHADOW_3_DESC_PADDING_VALUE_L 0x60D88 + +#define mmMME0_CTRL_SHADOW_3_DESC_META_DATA_AGU_S 0x60D8C + +#define mmMME0_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_LOCAL 0x60D90 + +#define mmMME0_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_REMOTE 0x60D94 + +#define mmMME0_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_LOCAL 0x60D98 + +#define mmMME0_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_REMOTE 0x60D9C + +#define mmMME0_CTRL_SHADOW_3_DESC_PCU_RL_SATURATION 0x60DA0 + +#define mmMME0_CTRL_SHADOW_3_DESC_DUMMY 0x60DA4 + +#endif /* ASIC_REG_MME0_CTRL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/mme0_qm_masks.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme0_qm_masks.h new file mode 100644 index 000000000000..e6dd30ce0ca7 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme0_qm_masks.h @@ -0,0 +1,800 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME0_QM_MASKS_H_ +#define ASIC_REG_MME0_QM_MASKS_H_ + +/* + ***************************************** + * MME0_QM (Prototype: QMAN) + ***************************************** + */ + +/* MME0_QM_GLBL_CFG0 */ +#define MME0_QM_GLBL_CFG0_PQF_EN_SHIFT 0 +#define MME0_QM_GLBL_CFG0_PQF_EN_MASK 0xF +#define MME0_QM_GLBL_CFG0_CQF_EN_SHIFT 4 +#define MME0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0 +#define MME0_QM_GLBL_CFG0_CP_EN_SHIFT 9 +#define MME0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00 + +/* MME0_QM_GLBL_CFG1 */ +#define MME0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0 +#define MME0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF +#define MME0_QM_GLBL_CFG1_CQF_STOP_SHIFT 4 +#define MME0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0 +#define MME0_QM_GLBL_CFG1_CP_STOP_SHIFT 9 +#define MME0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00 +#define MME0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 16 +#define MME0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000 +#define MME0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 20 +#define MME0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000 +#define MME0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 25 +#define MME0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x3E000000 + +/* MME0_QM_GLBL_PROT */ +#define MME0_QM_GLBL_PROT_PQF_SHIFT 0 +#define MME0_QM_GLBL_PROT_PQF_MASK 0xF +#define MME0_QM_GLBL_PROT_CQF_SHIFT 4 +#define MME0_QM_GLBL_PROT_CQF_MASK 0x1F0 +#define MME0_QM_GLBL_PROT_CP_SHIFT 9 +#define MME0_QM_GLBL_PROT_CP_MASK 0x3E00 +#define MME0_QM_GLBL_PROT_ERR_SHIFT 14 +#define MME0_QM_GLBL_PROT_ERR_MASK 0x4000 +#define MME0_QM_GLBL_PROT_ARB_SHIFT 15 +#define MME0_QM_GLBL_PROT_ARB_MASK 0x8000 + +/* MME0_QM_GLBL_ERR_CFG */ +#define MME0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 0 +#define MME0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0xF +#define MME0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 +#define MME0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1F0 +#define MME0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 9 +#define MME0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x3E00 +#define MME0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 16 +#define MME0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0xF0000 +#define MME0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 20 +#define MME0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x1F00000 +#define MME0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 25 +#define MME0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x3E000000 +#define MME0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT 31 +#define MME0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK 0x80000000 + +/* MME0_QM_GLBL_SECURE_PROPS */ +#define MME0_QM_GLBL_SECURE_PROPS_0_ASID_SHIFT 0 +#define MME0_QM_GLBL_SECURE_PROPS_0_ASID_MASK 0x3FF +#define MME0_QM_GLBL_SECURE_PROPS_1_ASID_SHIFT 0 +#define MME0_QM_GLBL_SECURE_PROPS_1_ASID_MASK 0x3FF +#define MME0_QM_GLBL_SECURE_PROPS_2_ASID_SHIFT 0 +#define MME0_QM_GLBL_SECURE_PROPS_2_ASID_MASK 0x3FF +#define MME0_QM_GLBL_SECURE_PROPS_3_ASID_SHIFT 0 +#define MME0_QM_GLBL_SECURE_PROPS_3_ASID_MASK 0x3FF +#define MME0_QM_GLBL_SECURE_PROPS_4_ASID_SHIFT 0 +#define MME0_QM_GLBL_SECURE_PROPS_4_ASID_MASK 0x3FF +#define MME0_QM_GLBL_SECURE_PROPS_0_MMBP_SHIFT 10 +#define MME0_QM_GLBL_SECURE_PROPS_0_MMBP_MASK 0x400 +#define MME0_QM_GLBL_SECURE_PROPS_1_MMBP_SHIFT 10 +#define MME0_QM_GLBL_SECURE_PROPS_1_MMBP_MASK 0x400 +#define MME0_QM_GLBL_SECURE_PROPS_2_MMBP_SHIFT 10 +#define MME0_QM_GLBL_SECURE_PROPS_2_MMBP_MASK 0x400 +#define MME0_QM_GLBL_SECURE_PROPS_3_MMBP_SHIFT 10 +#define MME0_QM_GLBL_SECURE_PROPS_3_MMBP_MASK 0x400 +#define MME0_QM_GLBL_SECURE_PROPS_4_MMBP_SHIFT 10 +#define MME0_QM_GLBL_SECURE_PROPS_4_MMBP_MASK 0x400 + +/* MME0_QM_GLBL_NON_SECURE_PROPS */ +#define MME0_QM_GLBL_NON_SECURE_PROPS_0_ASID_SHIFT 0 +#define MME0_QM_GLBL_NON_SECURE_PROPS_0_ASID_MASK 0x3FF +#define MME0_QM_GLBL_NON_SECURE_PROPS_1_ASID_SHIFT 0 +#define MME0_QM_GLBL_NON_SECURE_PROPS_1_ASID_MASK 0x3FF +#define MME0_QM_GLBL_NON_SECURE_PROPS_2_ASID_SHIFT 0 +#define MME0_QM_GLBL_NON_SECURE_PROPS_2_ASID_MASK 0x3FF +#define MME0_QM_GLBL_NON_SECURE_PROPS_3_ASID_SHIFT 0 +#define MME0_QM_GLBL_NON_SECURE_PROPS_3_ASID_MASK 0x3FF +#define MME0_QM_GLBL_NON_SECURE_PROPS_4_ASID_SHIFT 0 +#define MME0_QM_GLBL_NON_SECURE_PROPS_4_ASID_MASK 0x3FF +#define MME0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_SHIFT 10 +#define MME0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_MASK 0x400 +#define MME0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_SHIFT 10 +#define MME0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_MASK 0x400 +#define MME0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_SHIFT 10 +#define MME0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_MASK 0x400 +#define MME0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_SHIFT 10 +#define MME0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_MASK 0x400 +#define MME0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_SHIFT 10 +#define MME0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_MASK 0x400 + +/* MME0_QM_GLBL_STS0 */ +#define MME0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0 +#define MME0_QM_GLBL_STS0_PQF_IDLE_MASK 0xF +#define MME0_QM_GLBL_STS0_CQF_IDLE_SHIFT 4 +#define MME0_QM_GLBL_STS0_CQF_IDLE_MASK 0x1F0 +#define MME0_QM_GLBL_STS0_CP_IDLE_SHIFT 9 +#define MME0_QM_GLBL_STS0_CP_IDLE_MASK 0x3E00 +#define MME0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 16 +#define MME0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0xF0000 +#define MME0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 20 +#define MME0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x1F00000 +#define MME0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 25 +#define MME0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x3E000000 +#define MME0_QM_GLBL_STS0_ARB_IS_STOP_SHIFT 31 +#define MME0_QM_GLBL_STS0_ARB_IS_STOP_MASK 0x80000000 + +/* MME0_QM_GLBL_STS1 */ +#define MME0_QM_GLBL_STS1_PQF_RD_ERR_SHIFT 0 +#define MME0_QM_GLBL_STS1_PQF_RD_ERR_MASK 0x1 +#define MME0_QM_GLBL_STS1_CQF_RD_ERR_SHIFT 1 +#define MME0_QM_GLBL_STS1_CQF_RD_ERR_MASK 0x2 +#define MME0_QM_GLBL_STS1_CP_RD_ERR_SHIFT 2 +#define MME0_QM_GLBL_STS1_CP_RD_ERR_MASK 0x4 +#define MME0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3 +#define MME0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8 +#define MME0_QM_GLBL_STS1_CP_STOP_OP_SHIFT 4 +#define MME0_QM_GLBL_STS1_CP_STOP_OP_MASK 0x10 +#define MME0_QM_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5 +#define MME0_QM_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20 +#define MME0_QM_GLBL_STS1_CP_WREG_ERR_SHIFT 6 +#define MME0_QM_GLBL_STS1_CP_WREG_ERR_MASK 0x40 +#define MME0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_SHIFT 8 +#define MME0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_MASK 0x100 +#define MME0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_SHIFT 9 +#define MME0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_MASK 0x200 +#define MME0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_SHIFT 10 +#define MME0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_MASK 0x400 +#define MME0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_SHIFT 11 +#define MME0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_MASK 0x800 +#define MME0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_SHIFT 12 +#define MME0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define MME0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_SHIFT 13 +#define MME0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define MME0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_SHIFT 14 +#define MME0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define MME0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_SHIFT 15 +#define MME0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* MME0_QM_GLBL_STS1_4 */ +#define MME0_QM_GLBL_STS1_4_CQF_RD_ERR_SHIFT 1 +#define MME0_QM_GLBL_STS1_4_CQF_RD_ERR_MASK 0x2 +#define MME0_QM_GLBL_STS1_4_CP_RD_ERR_SHIFT 2 +#define MME0_QM_GLBL_STS1_4_CP_RD_ERR_MASK 0x4 +#define MME0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_SHIFT 3 +#define MME0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_MASK 0x8 +#define MME0_QM_GLBL_STS1_4_CP_STOP_OP_SHIFT 4 +#define MME0_QM_GLBL_STS1_4_CP_STOP_OP_MASK 0x10 +#define MME0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_SHIFT 5 +#define MME0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_MASK 0x20 +#define MME0_QM_GLBL_STS1_4_CP_WREG_ERR_SHIFT 6 +#define MME0_QM_GLBL_STS1_4_CP_WREG_ERR_MASK 0x40 +#define MME0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_SHIFT 8 +#define MME0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_MASK 0x100 +#define MME0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_SHIFT 9 +#define MME0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_MASK 0x200 +#define MME0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_SHIFT 10 +#define MME0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_MASK 0x400 +#define MME0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_SHIFT 11 +#define MME0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_MASK 0x800 +#define MME0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_SHIFT 12 +#define MME0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define MME0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_SHIFT 13 +#define MME0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define MME0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_SHIFT 14 +#define MME0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define MME0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_SHIFT 15 +#define MME0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* MME0_QM_GLBL_MSG_EN */ +#define MME0_QM_GLBL_MSG_EN_PQF_RD_ERR_SHIFT 0 +#define MME0_QM_GLBL_MSG_EN_PQF_RD_ERR_MASK 0x1 +#define MME0_QM_GLBL_MSG_EN_CQF_RD_ERR_SHIFT 1 +#define MME0_QM_GLBL_MSG_EN_CQF_RD_ERR_MASK 0x2 +#define MME0_QM_GLBL_MSG_EN_CP_RD_ERR_SHIFT 2 +#define MME0_QM_GLBL_MSG_EN_CP_RD_ERR_MASK 0x4 +#define MME0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT 3 +#define MME0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_MASK 0x8 +#define MME0_QM_GLBL_MSG_EN_CP_STOP_OP_SHIFT 4 +#define MME0_QM_GLBL_MSG_EN_CP_STOP_OP_MASK 0x10 +#define MME0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_SHIFT 5 +#define MME0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_MASK 0x20 +#define MME0_QM_GLBL_MSG_EN_CP_WREG_ERR_SHIFT 6 +#define MME0_QM_GLBL_MSG_EN_CP_WREG_ERR_MASK 0x40 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT 8 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT 9 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT 10 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_MASK 0x400 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT 11 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT 12 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT 13 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT 14 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT 15 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* MME0_QM_GLBL_MSG_EN_4 */ +#define MME0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_SHIFT 1 +#define MME0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_MASK 0x2 +#define MME0_QM_GLBL_MSG_EN_4_CP_RD_ERR_SHIFT 2 +#define MME0_QM_GLBL_MSG_EN_4_CP_RD_ERR_MASK 0x4 +#define MME0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT 3 +#define MME0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK 0x8 +#define MME0_QM_GLBL_MSG_EN_4_CP_STOP_OP_SHIFT 4 +#define MME0_QM_GLBL_MSG_EN_4_CP_STOP_OP_MASK 0x10 +#define MME0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_SHIFT 5 +#define MME0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_MASK 0x20 +#define MME0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_SHIFT 6 +#define MME0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_MASK 0x40 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT 8 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT 9 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT 10 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK 0x400 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT 11 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT 12 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT 13 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT 14 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT 15 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* MME0_QM_PQ_BASE_LO */ +#define MME0_QM_PQ_BASE_LO_VAL_SHIFT 0 +#define MME0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_PQ_BASE_HI */ +#define MME0_QM_PQ_BASE_HI_VAL_SHIFT 0 +#define MME0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_PQ_SIZE */ +#define MME0_QM_PQ_SIZE_VAL_SHIFT 0 +#define MME0_QM_PQ_SIZE_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_PQ_PI */ +#define MME0_QM_PQ_PI_VAL_SHIFT 0 +#define MME0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_PQ_CI */ +#define MME0_QM_PQ_CI_VAL_SHIFT 0 +#define MME0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_PQ_CFG0 */ +#define MME0_QM_PQ_CFG0_RESERVED_SHIFT 0 +#define MME0_QM_PQ_CFG0_RESERVED_MASK 0x1 + +/* MME0_QM_PQ_CFG1 */ +#define MME0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0 +#define MME0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define MME0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define MME0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* MME0_QM_PQ_ARUSER_31_11 */ +#define MME0_QM_PQ_ARUSER_31_11_VAL_SHIFT 0 +#define MME0_QM_PQ_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* MME0_QM_PQ_STS0 */ +#define MME0_QM_PQ_STS0_PQ_CREDIT_CNT_SHIFT 0 +#define MME0_QM_PQ_STS0_PQ_CREDIT_CNT_MASK 0xFFFF +#define MME0_QM_PQ_STS0_PQ_FREE_CNT_SHIFT 16 +#define MME0_QM_PQ_STS0_PQ_FREE_CNT_MASK 0xFFFF0000 + +/* MME0_QM_PQ_STS1 */ +#define MME0_QM_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT 0 +#define MME0_QM_PQ_STS1_PQ_INFLIGHT_CNT_MASK 0xFFFF +#define MME0_QM_PQ_STS1_PQ_BUF_EMPTY_SHIFT 30 +#define MME0_QM_PQ_STS1_PQ_BUF_EMPTY_MASK 0x40000000 +#define MME0_QM_PQ_STS1_PQ_BUSY_SHIFT 31 +#define MME0_QM_PQ_STS1_PQ_BUSY_MASK 0x80000000 + +/* MME0_QM_CQ_CFG0 */ +#define MME0_QM_CQ_CFG0_RESERVED_SHIFT 0 +#define MME0_QM_CQ_CFG0_RESERVED_MASK 0x1 + +/* MME0_QM_CQ_CFG1 */ +#define MME0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0 +#define MME0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define MME0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define MME0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* MME0_QM_CQ_ARUSER_31_11 */ +#define MME0_QM_CQ_ARUSER_31_11_VAL_SHIFT 0 +#define MME0_QM_CQ_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* MME0_QM_CQ_STS0 */ +#define MME0_QM_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0 +#define MME0_QM_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF +#define MME0_QM_CQ_STS0_CQ_FREE_CNT_SHIFT 16 +#define MME0_QM_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000 + +/* MME0_QM_CQ_STS1 */ +#define MME0_QM_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0 +#define MME0_QM_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF +#define MME0_QM_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30 +#define MME0_QM_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000 +#define MME0_QM_CQ_STS1_CQ_BUSY_SHIFT 31 +#define MME0_QM_CQ_STS1_CQ_BUSY_MASK 0x80000000 + +/* MME0_QM_CQ_PTR_LO_0 */ +#define MME0_QM_CQ_PTR_LO_0_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_LO_0_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_PTR_HI_0 */ +#define MME0_QM_CQ_PTR_HI_0_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_HI_0_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_TSIZE_0 */ +#define MME0_QM_CQ_TSIZE_0_VAL_SHIFT 0 +#define MME0_QM_CQ_TSIZE_0_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_CTL_0 */ +#define MME0_QM_CQ_CTL_0_RPT_SHIFT 0 +#define MME0_QM_CQ_CTL_0_RPT_MASK 0xFFFF +#define MME0_QM_CQ_CTL_0_CTL_SHIFT 16 +#define MME0_QM_CQ_CTL_0_CTL_MASK 0xFFFF0000 + +/* MME0_QM_CQ_PTR_LO_1 */ +#define MME0_QM_CQ_PTR_LO_1_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_LO_1_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_PTR_HI_1 */ +#define MME0_QM_CQ_PTR_HI_1_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_HI_1_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_TSIZE_1 */ +#define MME0_QM_CQ_TSIZE_1_VAL_SHIFT 0 +#define MME0_QM_CQ_TSIZE_1_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_CTL_1 */ +#define MME0_QM_CQ_CTL_1_RPT_SHIFT 0 +#define MME0_QM_CQ_CTL_1_RPT_MASK 0xFFFF +#define MME0_QM_CQ_CTL_1_CTL_SHIFT 16 +#define MME0_QM_CQ_CTL_1_CTL_MASK 0xFFFF0000 + +/* MME0_QM_CQ_PTR_LO_2 */ +#define MME0_QM_CQ_PTR_LO_2_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_LO_2_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_PTR_HI_2 */ +#define MME0_QM_CQ_PTR_HI_2_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_HI_2_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_TSIZE_2 */ +#define MME0_QM_CQ_TSIZE_2_VAL_SHIFT 0 +#define MME0_QM_CQ_TSIZE_2_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_CTL_2 */ +#define MME0_QM_CQ_CTL_2_RPT_SHIFT 0 +#define MME0_QM_CQ_CTL_2_RPT_MASK 0xFFFF +#define MME0_QM_CQ_CTL_2_CTL_SHIFT 16 +#define MME0_QM_CQ_CTL_2_CTL_MASK 0xFFFF0000 + +/* MME0_QM_CQ_PTR_LO_3 */ +#define MME0_QM_CQ_PTR_LO_3_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_LO_3_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_PTR_HI_3 */ +#define MME0_QM_CQ_PTR_HI_3_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_HI_3_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_TSIZE_3 */ +#define MME0_QM_CQ_TSIZE_3_VAL_SHIFT 0 +#define MME0_QM_CQ_TSIZE_3_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_CTL_3 */ +#define MME0_QM_CQ_CTL_3_RPT_SHIFT 0 +#define MME0_QM_CQ_CTL_3_RPT_MASK 0xFFFF +#define MME0_QM_CQ_CTL_3_CTL_SHIFT 16 +#define MME0_QM_CQ_CTL_3_CTL_MASK 0xFFFF0000 + +/* MME0_QM_CQ_PTR_LO_4 */ +#define MME0_QM_CQ_PTR_LO_4_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_LO_4_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_PTR_HI_4 */ +#define MME0_QM_CQ_PTR_HI_4_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_HI_4_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_TSIZE_4 */ +#define MME0_QM_CQ_TSIZE_4_VAL_SHIFT 0 +#define MME0_QM_CQ_TSIZE_4_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_CTL_4 */ +#define MME0_QM_CQ_CTL_4_RPT_SHIFT 0 +#define MME0_QM_CQ_CTL_4_RPT_MASK 0xFFFF +#define MME0_QM_CQ_CTL_4_CTL_SHIFT 16 +#define MME0_QM_CQ_CTL_4_CTL_MASK 0xFFFF0000 + +/* MME0_QM_CQ_PTR_LO_STS */ +#define MME0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_PTR_HI_STS */ +#define MME0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_TSIZE_STS */ +#define MME0_QM_CQ_TSIZE_STS_VAL_SHIFT 0 +#define MME0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_CTL_STS */ +#define MME0_QM_CQ_CTL_STS_RPT_SHIFT 0 +#define MME0_QM_CQ_CTL_STS_RPT_MASK 0xFFFF +#define MME0_QM_CQ_CTL_STS_CTL_SHIFT 16 +#define MME0_QM_CQ_CTL_STS_CTL_MASK 0xFFFF0000 + +/* MME0_QM_CQ_IFIFO_CNT */ +#define MME0_QM_CQ_IFIFO_CNT_VAL_SHIFT 0 +#define MME0_QM_CQ_IFIFO_CNT_VAL_MASK 0x3 + +/* MME0_QM_CP_MSG_BASE0_ADDR_LO */ +#define MME0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 +#define MME0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_MSG_BASE0_ADDR_HI */ +#define MME0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 +#define MME0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_MSG_BASE1_ADDR_LO */ +#define MME0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 +#define MME0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_MSG_BASE1_ADDR_HI */ +#define MME0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 +#define MME0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_MSG_BASE2_ADDR_LO */ +#define MME0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 +#define MME0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_MSG_BASE2_ADDR_HI */ +#define MME0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 +#define MME0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_MSG_BASE3_ADDR_LO */ +#define MME0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 +#define MME0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_MSG_BASE3_ADDR_HI */ +#define MME0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 +#define MME0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_LDMA_TSIZE_OFFSET */ +#define MME0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 +#define MME0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */ +#define MME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 +#define MME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_LDMA_DST_BASE_LO_OFFSET */ +#define MME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 +#define MME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_FENCE0_RDATA */ +#define MME0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 +#define MME0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF + +/* MME0_QM_CP_FENCE1_RDATA */ +#define MME0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 +#define MME0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF + +/* MME0_QM_CP_FENCE2_RDATA */ +#define MME0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 +#define MME0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF + +/* MME0_QM_CP_FENCE3_RDATA */ +#define MME0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 +#define MME0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF + +/* MME0_QM_CP_FENCE0_CNT */ +#define MME0_QM_CP_FENCE0_CNT_VAL_SHIFT 0 +#define MME0_QM_CP_FENCE0_CNT_VAL_MASK 0x3FFF + +/* MME0_QM_CP_FENCE1_CNT */ +#define MME0_QM_CP_FENCE1_CNT_VAL_SHIFT 0 +#define MME0_QM_CP_FENCE1_CNT_VAL_MASK 0x3FFF + +/* MME0_QM_CP_FENCE2_CNT */ +#define MME0_QM_CP_FENCE2_CNT_VAL_SHIFT 0 +#define MME0_QM_CP_FENCE2_CNT_VAL_MASK 0x3FFF + +/* MME0_QM_CP_FENCE3_CNT */ +#define MME0_QM_CP_FENCE3_CNT_VAL_SHIFT 0 +#define MME0_QM_CP_FENCE3_CNT_VAL_MASK 0x3FFF + +/* MME0_QM_CP_STS */ +#define MME0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 +#define MME0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF +#define MME0_QM_CP_STS_ERDY_SHIFT 16 +#define MME0_QM_CP_STS_ERDY_MASK 0x10000 +#define MME0_QM_CP_STS_RRDY_SHIFT 17 +#define MME0_QM_CP_STS_RRDY_MASK 0x20000 +#define MME0_QM_CP_STS_MRDY_SHIFT 18 +#define MME0_QM_CP_STS_MRDY_MASK 0x40000 +#define MME0_QM_CP_STS_SW_STOP_SHIFT 19 +#define MME0_QM_CP_STS_SW_STOP_MASK 0x80000 +#define MME0_QM_CP_STS_FENCE_ID_SHIFT 20 +#define MME0_QM_CP_STS_FENCE_ID_MASK 0x300000 +#define MME0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 22 +#define MME0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000 + +/* MME0_QM_CP_CURRENT_INST_LO */ +#define MME0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0 +#define MME0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_CURRENT_INST_HI */ +#define MME0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0 +#define MME0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_BARRIER_CFG */ +#define MME0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0 +#define MME0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF +#define MME0_QM_CP_BARRIER_CFG_RBGUARD_SHIFT 16 +#define MME0_QM_CP_BARRIER_CFG_RBGUARD_MASK 0xF0000 + +/* MME0_QM_CP_DBG_0 */ +#define MME0_QM_CP_DBG_0_CS_SHIFT 0 +#define MME0_QM_CP_DBG_0_CS_MASK 0xF +#define MME0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT 4 +#define MME0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_MASK 0x10 +#define MME0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT 5 +#define MME0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK 0x20 +#define MME0_QM_CP_DBG_0_MREB_STALL_SHIFT 6 +#define MME0_QM_CP_DBG_0_MREB_STALL_MASK 0x40 +#define MME0_QM_CP_DBG_0_STALL_SHIFT 7 +#define MME0_QM_CP_DBG_0_STALL_MASK 0x80 + +/* MME0_QM_CP_ARUSER_31_11 */ +#define MME0_QM_CP_ARUSER_31_11_VAL_SHIFT 0 +#define MME0_QM_CP_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* MME0_QM_CP_AWUSER_31_11 */ +#define MME0_QM_CP_AWUSER_31_11_VAL_SHIFT 0 +#define MME0_QM_CP_AWUSER_31_11_VAL_MASK 0x1FFFFF + +/* MME0_QM_ARB_CFG_0 */ +#define MME0_QM_ARB_CFG_0_TYPE_SHIFT 0 +#define MME0_QM_ARB_CFG_0_TYPE_MASK 0x1 +#define MME0_QM_ARB_CFG_0_IS_MASTER_SHIFT 4 +#define MME0_QM_ARB_CFG_0_IS_MASTER_MASK 0x10 +#define MME0_QM_ARB_CFG_0_EN_SHIFT 8 +#define MME0_QM_ARB_CFG_0_EN_MASK 0x100 +#define MME0_QM_ARB_CFG_0_MASK_SHIFT 12 +#define MME0_QM_ARB_CFG_0_MASK_MASK 0xF000 +#define MME0_QM_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT 16 +#define MME0_QM_ARB_CFG_0_MST_MSG_NOSTALL_MASK 0x10000 + +/* MME0_QM_ARB_CHOISE_Q_PUSH */ +#define MME0_QM_ARB_CHOISE_Q_PUSH_VAL_SHIFT 0 +#define MME0_QM_ARB_CHOISE_Q_PUSH_VAL_MASK 0x3 + +/* MME0_QM_ARB_WRR_WEIGHT */ +#define MME0_QM_ARB_WRR_WEIGHT_VAL_SHIFT 0 +#define MME0_QM_ARB_WRR_WEIGHT_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_ARB_CFG_1 */ +#define MME0_QM_ARB_CFG_1_CLR_SHIFT 0 +#define MME0_QM_ARB_CFG_1_CLR_MASK 0x1 + +/* MME0_QM_ARB_MST_AVAIL_CRED */ +#define MME0_QM_ARB_MST_AVAIL_CRED_VAL_SHIFT 0 +#define MME0_QM_ARB_MST_AVAIL_CRED_VAL_MASK 0x7F + +/* MME0_QM_ARB_MST_CRED_INC */ +#define MME0_QM_ARB_MST_CRED_INC_VAL_SHIFT 0 +#define MME0_QM_ARB_MST_CRED_INC_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_ARB_MST_CHOISE_PUSH_OFST */ +#define MME0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_SHIFT 0 +#define MME0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_ARB_SLV_MASTER_INC_CRED_OFST */ +#define MME0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT 0 +#define MME0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_ARB_MST_SLAVE_EN */ +#define MME0_QM_ARB_MST_SLAVE_EN_VAL_SHIFT 0 +#define MME0_QM_ARB_MST_SLAVE_EN_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_ARB_MST_QUIET_PER */ +#define MME0_QM_ARB_MST_QUIET_PER_VAL_SHIFT 0 +#define MME0_QM_ARB_MST_QUIET_PER_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_ARB_SLV_CHOISE_WDT */ +#define MME0_QM_ARB_SLV_CHOISE_WDT_VAL_SHIFT 0 +#define MME0_QM_ARB_SLV_CHOISE_WDT_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_ARB_SLV_ID */ +#define MME0_QM_ARB_SLV_ID_VAL_SHIFT 0 +#define MME0_QM_ARB_SLV_ID_VAL_MASK 0x1F + +/* MME0_QM_ARB_MSG_MAX_INFLIGHT */ +#define MME0_QM_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT 0 +#define MME0_QM_ARB_MSG_MAX_INFLIGHT_VAL_MASK 0x3F + +/* MME0_QM_ARB_MSG_AWUSER_31_11 */ +#define MME0_QM_ARB_MSG_AWUSER_31_11_VAL_SHIFT 0 +#define MME0_QM_ARB_MSG_AWUSER_31_11_VAL_MASK 0x1FFFFF + +/* MME0_QM_ARB_MSG_AWUSER_SEC_PROP */ +#define MME0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_SHIFT 0 +#define MME0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_MASK 0x3FF +#define MME0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_SHIFT 10 +#define MME0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_MASK 0x400 + +/* MME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP */ +#define MME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_SHIFT 0 +#define MME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_MASK 0x3FF +#define MME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_SHIFT 10 +#define MME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_MASK 0x400 + +/* MME0_QM_ARB_BASE_LO */ +#define MME0_QM_ARB_BASE_LO_VAL_SHIFT 0 +#define MME0_QM_ARB_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_ARB_BASE_HI */ +#define MME0_QM_ARB_BASE_HI_VAL_SHIFT 0 +#define MME0_QM_ARB_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_ARB_STATE_STS */ +#define MME0_QM_ARB_STATE_STS_VAL_SHIFT 0 +#define MME0_QM_ARB_STATE_STS_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_ARB_CHOISE_FULLNESS_STS */ +#define MME0_QM_ARB_CHOISE_FULLNESS_STS_VAL_SHIFT 0 +#define MME0_QM_ARB_CHOISE_FULLNESS_STS_VAL_MASK 0x7F + +/* MME0_QM_ARB_MSG_STS */ +#define MME0_QM_ARB_MSG_STS_FULL_SHIFT 0 +#define MME0_QM_ARB_MSG_STS_FULL_MASK 0x1 +#define MME0_QM_ARB_MSG_STS_NO_INFLIGHT_SHIFT 1 +#define MME0_QM_ARB_MSG_STS_NO_INFLIGHT_MASK 0x2 + +/* MME0_QM_ARB_SLV_CHOISE_Q_HEAD */ +#define MME0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_SHIFT 0 +#define MME0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_MASK 0x3 + +/* MME0_QM_ARB_ERR_CAUSE */ +#define MME0_QM_ARB_ERR_CAUSE_CHOISE_OVF_SHIFT 0 +#define MME0_QM_ARB_ERR_CAUSE_CHOISE_OVF_MASK 0x1 +#define MME0_QM_ARB_ERR_CAUSE_CHOISE_WDT_SHIFT 1 +#define MME0_QM_ARB_ERR_CAUSE_CHOISE_WDT_MASK 0x2 +#define MME0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT 2 +#define MME0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK 0x4 + +/* MME0_QM_ARB_ERR_MSG_EN */ +#define MME0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_SHIFT 0 +#define MME0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1 +#define MME0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_SHIFT 1 +#define MME0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2 +#define MME0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT 2 +#define MME0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4 + +/* MME0_QM_ARB_ERR_STS_DRP */ +#define MME0_QM_ARB_ERR_STS_DRP_VAL_SHIFT 0 +#define MME0_QM_ARB_ERR_STS_DRP_VAL_MASK 0x3 + +/* MME0_QM_ARB_MST_CRED_STS */ +#define MME0_QM_ARB_MST_CRED_STS_VAL_SHIFT 0 +#define MME0_QM_ARB_MST_CRED_STS_VAL_MASK 0x7F + +/* MME0_QM_CGM_CFG */ +#define MME0_QM_CGM_CFG_IDLE_TH_SHIFT 0 +#define MME0_QM_CGM_CFG_IDLE_TH_MASK 0xFFF +#define MME0_QM_CGM_CFG_G2F_TH_SHIFT 16 +#define MME0_QM_CGM_CFG_G2F_TH_MASK 0xFF0000 +#define MME0_QM_CGM_CFG_CP_IDLE_MASK_SHIFT 24 +#define MME0_QM_CGM_CFG_CP_IDLE_MASK_MASK 0x1F000000 +#define MME0_QM_CGM_CFG_EN_SHIFT 31 +#define MME0_QM_CGM_CFG_EN_MASK 0x80000000 + +/* MME0_QM_CGM_STS */ +#define MME0_QM_CGM_STS_ST_SHIFT 0 +#define MME0_QM_CGM_STS_ST_MASK 0x3 +#define MME0_QM_CGM_STS_CG_SHIFT 4 +#define MME0_QM_CGM_STS_CG_MASK 0x10 +#define MME0_QM_CGM_STS_AGENT_IDLE_SHIFT 8 +#define MME0_QM_CGM_STS_AGENT_IDLE_MASK 0x100 +#define MME0_QM_CGM_STS_AXI_IDLE_SHIFT 9 +#define MME0_QM_CGM_STS_AXI_IDLE_MASK 0x200 +#define MME0_QM_CGM_STS_CP_IDLE_SHIFT 10 +#define MME0_QM_CGM_STS_CP_IDLE_MASK 0x400 + +/* MME0_QM_CGM_CFG1 */ +#define MME0_QM_CGM_CFG1_MASK_TH_SHIFT 0 +#define MME0_QM_CGM_CFG1_MASK_TH_MASK 0xFF + +/* MME0_QM_LOCAL_RANGE_BASE */ +#define MME0_QM_LOCAL_RANGE_BASE_VAL_SHIFT 0 +#define MME0_QM_LOCAL_RANGE_BASE_VAL_MASK 0xFFFF + +/* MME0_QM_LOCAL_RANGE_SIZE */ +#define MME0_QM_LOCAL_RANGE_SIZE_VAL_SHIFT 0 +#define MME0_QM_LOCAL_RANGE_SIZE_VAL_MASK 0xFFFF + +/* MME0_QM_CSMR_STRICT_PRIO_CFG */ +#define MME0_QM_CSMR_STRICT_PRIO_CFG_TYPE_SHIFT 0 +#define MME0_QM_CSMR_STRICT_PRIO_CFG_TYPE_MASK 0x1 + +/* MME0_QM_HBW_RD_RATE_LIM_CFG_1 */ +#define MME0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define MME0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define MME0_QM_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT 31 +#define MME0_QM_HBW_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* MME0_QM_LBW_WR_RATE_LIM_CFG_0 */ +#define MME0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define MME0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define MME0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define MME0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* MME0_QM_LBW_WR_RATE_LIM_CFG_1 */ +#define MME0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define MME0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define MME0_QM_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT 31 +#define MME0_QM_LBW_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* MME0_QM_HBW_RD_RATE_LIM_CFG_0 */ +#define MME0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define MME0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define MME0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define MME0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* MME0_QM_GLBL_AXCACHE */ +#define MME0_QM_GLBL_AXCACHE_AR_SHIFT 0 +#define MME0_QM_GLBL_AXCACHE_AR_MASK 0xF +#define MME0_QM_GLBL_AXCACHE_AW_SHIFT 16 +#define MME0_QM_GLBL_AXCACHE_AW_MASK 0xF0000 + +/* MME0_QM_IND_GW_APB_CFG */ +#define MME0_QM_IND_GW_APB_CFG_ADDR_SHIFT 0 +#define MME0_QM_IND_GW_APB_CFG_ADDR_MASK 0x7FFFFFFF +#define MME0_QM_IND_GW_APB_CFG_CMD_SHIFT 31 +#define MME0_QM_IND_GW_APB_CFG_CMD_MASK 0x80000000 + +/* MME0_QM_IND_GW_APB_WDATA */ +#define MME0_QM_IND_GW_APB_WDATA_VAL_SHIFT 0 +#define MME0_QM_IND_GW_APB_WDATA_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_IND_GW_APB_RDATA */ +#define MME0_QM_IND_GW_APB_RDATA_VAL_SHIFT 0 +#define MME0_QM_IND_GW_APB_RDATA_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_IND_GW_APB_STATUS */ +#define MME0_QM_IND_GW_APB_STATUS_RDY_SHIFT 0 +#define MME0_QM_IND_GW_APB_STATUS_RDY_MASK 0x1 +#define MME0_QM_IND_GW_APB_STATUS_ERR_SHIFT 1 +#define MME0_QM_IND_GW_APB_STATUS_ERR_MASK 0x2 + +/* MME0_QM_GLBL_ERR_ADDR_LO */ +#define MME0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 +#define MME0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_GLBL_ERR_ADDR_HI */ +#define MME0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 +#define MME0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_GLBL_ERR_WDATA */ +#define MME0_QM_GLBL_ERR_WDATA_VAL_SHIFT 0 +#define MME0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_GLBL_MEM_INIT_BUSY */ +#define MME0_QM_GLBL_MEM_INIT_BUSY_RBUF_SHIFT 0 +#define MME0_QM_GLBL_MEM_INIT_BUSY_RBUF_MASK 0xF + +#endif /* ASIC_REG_MME0_QM_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/mme0_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme0_qm_regs.h new file mode 100644 index 000000000000..4f078b328b00 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme0_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME0_QM_REGS_H_ +#define ASIC_REG_MME0_QM_REGS_H_ + +/* + ***************************************** + * MME0_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmMME0_QM_GLBL_CFG0 0x68000 + +#define mmMME0_QM_GLBL_CFG1 0x68004 + +#define mmMME0_QM_GLBL_PROT 0x68008 + +#define mmMME0_QM_GLBL_ERR_CFG 0x6800C + +#define mmMME0_QM_GLBL_SECURE_PROPS_0 0x68010 + +#define mmMME0_QM_GLBL_SECURE_PROPS_1 0x68014 + +#define mmMME0_QM_GLBL_SECURE_PROPS_2 0x68018 + +#define mmMME0_QM_GLBL_SECURE_PROPS_3 0x6801C + +#define mmMME0_QM_GLBL_SECURE_PROPS_4 0x68020 + +#define mmMME0_QM_GLBL_NON_SECURE_PROPS_0 0x68024 + +#define mmMME0_QM_GLBL_NON_SECURE_PROPS_1 0x68028 + +#define mmMME0_QM_GLBL_NON_SECURE_PROPS_2 0x6802C + +#define mmMME0_QM_GLBL_NON_SECURE_PROPS_3 0x68030 + +#define mmMME0_QM_GLBL_NON_SECURE_PROPS_4 0x68034 + +#define mmMME0_QM_GLBL_STS0 0x68038 + +#define mmMME0_QM_GLBL_STS1_0 0x68040 + +#define mmMME0_QM_GLBL_STS1_1 0x68044 + +#define mmMME0_QM_GLBL_STS1_2 0x68048 + +#define mmMME0_QM_GLBL_STS1_3 0x6804C + +#define mmMME0_QM_GLBL_STS1_4 0x68050 + +#define mmMME0_QM_GLBL_MSG_EN_0 0x68054 + +#define mmMME0_QM_GLBL_MSG_EN_1 0x68058 + +#define mmMME0_QM_GLBL_MSG_EN_2 0x6805C + +#define mmMME0_QM_GLBL_MSG_EN_3 0x68060 + +#define mmMME0_QM_GLBL_MSG_EN_4 0x68068 + +#define mmMME0_QM_PQ_BASE_LO_0 0x68070 + +#define mmMME0_QM_PQ_BASE_LO_1 0x68074 + +#define mmMME0_QM_PQ_BASE_LO_2 0x68078 + +#define mmMME0_QM_PQ_BASE_LO_3 0x6807C + +#define mmMME0_QM_PQ_BASE_HI_0 0x68080 + +#define mmMME0_QM_PQ_BASE_HI_1 0x68084 + +#define mmMME0_QM_PQ_BASE_HI_2 0x68088 + +#define mmMME0_QM_PQ_BASE_HI_3 0x6808C + +#define mmMME0_QM_PQ_SIZE_0 0x68090 + +#define mmMME0_QM_PQ_SIZE_1 0x68094 + +#define mmMME0_QM_PQ_SIZE_2 0x68098 + +#define mmMME0_QM_PQ_SIZE_3 0x6809C + +#define mmMME0_QM_PQ_PI_0 0x680A0 + +#define mmMME0_QM_PQ_PI_1 0x680A4 + +#define mmMME0_QM_PQ_PI_2 0x680A8 + +#define mmMME0_QM_PQ_PI_3 0x680AC + +#define mmMME0_QM_PQ_CI_0 0x680B0 + +#define mmMME0_QM_PQ_CI_1 0x680B4 + +#define mmMME0_QM_PQ_CI_2 0x680B8 + +#define mmMME0_QM_PQ_CI_3 0x680BC + +#define mmMME0_QM_PQ_CFG0_0 0x680C0 + +#define mmMME0_QM_PQ_CFG0_1 0x680C4 + +#define mmMME0_QM_PQ_CFG0_2 0x680C8 + +#define mmMME0_QM_PQ_CFG0_3 0x680CC + +#define mmMME0_QM_PQ_CFG1_0 0x680D0 + +#define mmMME0_QM_PQ_CFG1_1 0x680D4 + +#define mmMME0_QM_PQ_CFG1_2 0x680D8 + +#define mmMME0_QM_PQ_CFG1_3 0x680DC + +#define mmMME0_QM_PQ_ARUSER_31_11_0 0x680E0 + +#define mmMME0_QM_PQ_ARUSER_31_11_1 0x680E4 + +#define mmMME0_QM_PQ_ARUSER_31_11_2 0x680E8 + +#define mmMME0_QM_PQ_ARUSER_31_11_3 0x680EC + +#define mmMME0_QM_PQ_STS0_0 0x680F0 + +#define mmMME0_QM_PQ_STS0_1 0x680F4 + +#define mmMME0_QM_PQ_STS0_2 0x680F8 + +#define mmMME0_QM_PQ_STS0_3 0x680FC + +#define mmMME0_QM_PQ_STS1_0 0x68100 + +#define mmMME0_QM_PQ_STS1_1 0x68104 + +#define mmMME0_QM_PQ_STS1_2 0x68108 + +#define mmMME0_QM_PQ_STS1_3 0x6810C + +#define mmMME0_QM_CQ_CFG0_0 0x68110 + +#define mmMME0_QM_CQ_CFG0_1 0x68114 + +#define mmMME0_QM_CQ_CFG0_2 0x68118 + +#define mmMME0_QM_CQ_CFG0_3 0x6811C + +#define mmMME0_QM_CQ_CFG0_4 0x68120 + +#define mmMME0_QM_CQ_CFG1_0 0x68124 + +#define mmMME0_QM_CQ_CFG1_1 0x68128 + +#define mmMME0_QM_CQ_CFG1_2 0x6812C + +#define mmMME0_QM_CQ_CFG1_3 0x68130 + +#define mmMME0_QM_CQ_CFG1_4 0x68134 + +#define mmMME0_QM_CQ_ARUSER_31_11_0 0x68138 + +#define mmMME0_QM_CQ_ARUSER_31_11_1 0x6813C + +#define mmMME0_QM_CQ_ARUSER_31_11_2 0x68140 + +#define mmMME0_QM_CQ_ARUSER_31_11_3 0x68144 + +#define mmMME0_QM_CQ_ARUSER_31_11_4 0x68148 + +#define mmMME0_QM_CQ_STS0_0 0x6814C + +#define mmMME0_QM_CQ_STS0_1 0x68150 + +#define mmMME0_QM_CQ_STS0_2 0x68154 + +#define mmMME0_QM_CQ_STS0_3 0x68158 + +#define mmMME0_QM_CQ_STS0_4 0x6815C + +#define mmMME0_QM_CQ_STS1_0 0x68160 + +#define mmMME0_QM_CQ_STS1_1 0x68164 + +#define mmMME0_QM_CQ_STS1_2 0x68168 + +#define mmMME0_QM_CQ_STS1_3 0x6816C + +#define mmMME0_QM_CQ_STS1_4 0x68170 + +#define mmMME0_QM_CQ_PTR_LO_0 0x68174 + +#define mmMME0_QM_CQ_PTR_HI_0 0x68178 + +#define mmMME0_QM_CQ_TSIZE_0 0x6817C + +#define mmMME0_QM_CQ_CTL_0 0x68180 + +#define mmMME0_QM_CQ_PTR_LO_1 0x68184 + +#define mmMME0_QM_CQ_PTR_HI_1 0x68188 + +#define mmMME0_QM_CQ_TSIZE_1 0x6818C + +#define mmMME0_QM_CQ_CTL_1 0x68190 + +#define mmMME0_QM_CQ_PTR_LO_2 0x68194 + +#define mmMME0_QM_CQ_PTR_HI_2 0x68198 + +#define mmMME0_QM_CQ_TSIZE_2 0x6819C + +#define mmMME0_QM_CQ_CTL_2 0x681A0 + +#define mmMME0_QM_CQ_PTR_LO_3 0x681A4 + +#define mmMME0_QM_CQ_PTR_HI_3 0x681A8 + +#define mmMME0_QM_CQ_TSIZE_3 0x681AC + +#define mmMME0_QM_CQ_CTL_3 0x681B0 + +#define mmMME0_QM_CQ_PTR_LO_4 0x681B4 + +#define mmMME0_QM_CQ_PTR_HI_4 0x681B8 + +#define mmMME0_QM_CQ_TSIZE_4 0x681BC + +#define mmMME0_QM_CQ_CTL_4 0x681C0 + +#define mmMME0_QM_CQ_PTR_LO_STS_0 0x681C4 + +#define mmMME0_QM_CQ_PTR_LO_STS_1 0x681C8 + +#define mmMME0_QM_CQ_PTR_LO_STS_2 0x681CC + +#define mmMME0_QM_CQ_PTR_LO_STS_3 0x681D0 + +#define mmMME0_QM_CQ_PTR_LO_STS_4 0x681D4 + +#define mmMME0_QM_CQ_PTR_HI_STS_0 0x681D8 + +#define mmMME0_QM_CQ_PTR_HI_STS_1 0x681DC + +#define mmMME0_QM_CQ_PTR_HI_STS_2 0x681E0 + +#define mmMME0_QM_CQ_PTR_HI_STS_3 0x681E4 + +#define mmMME0_QM_CQ_PTR_HI_STS_4 0x681E8 + +#define mmMME0_QM_CQ_TSIZE_STS_0 0x681EC + +#define mmMME0_QM_CQ_TSIZE_STS_1 0x681F0 + +#define mmMME0_QM_CQ_TSIZE_STS_2 0x681F4 + +#define mmMME0_QM_CQ_TSIZE_STS_3 0x681F8 + +#define mmMME0_QM_CQ_TSIZE_STS_4 0x681FC + +#define mmMME0_QM_CQ_CTL_STS_0 0x68200 + +#define mmMME0_QM_CQ_CTL_STS_1 0x68204 + +#define mmMME0_QM_CQ_CTL_STS_2 0x68208 + +#define mmMME0_QM_CQ_CTL_STS_3 0x6820C + +#define mmMME0_QM_CQ_CTL_STS_4 0x68210 + +#define mmMME0_QM_CQ_IFIFO_CNT_0 0x68214 + +#define mmMME0_QM_CQ_IFIFO_CNT_1 0x68218 + +#define mmMME0_QM_CQ_IFIFO_CNT_2 0x6821C + +#define mmMME0_QM_CQ_IFIFO_CNT_3 0x68220 + +#define mmMME0_QM_CQ_IFIFO_CNT_4 0x68224 + +#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_0 0x68228 + +#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_1 0x6822C + +#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_2 0x68230 + +#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_3 0x68234 + +#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_4 0x68238 + +#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_0 0x6823C + +#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_1 0x68240 + +#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_2 0x68244 + +#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_3 0x68248 + +#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_4 0x6824C + +#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_0 0x68250 + +#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_1 0x68254 + +#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_2 0x68258 + +#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_3 0x6825C + +#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_4 0x68260 + +#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_0 0x68264 + +#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_1 0x68268 + +#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_2 0x6826C + +#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_3 0x68270 + +#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_4 0x68274 + +#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_0 0x68278 + +#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_1 0x6827C + +#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_2 0x68280 + +#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_3 0x68284 + +#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_4 0x68288 + +#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_0 0x6828C + +#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_1 0x68290 + +#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_2 0x68294 + +#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_3 0x68298 + +#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_4 0x6829C + +#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_0 0x682A0 + +#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_1 0x682A4 + +#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_2 0x682A8 + +#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_3 0x682AC + +#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_4 0x682B0 + +#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_0 0x682B4 + +#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_1 0x682B8 + +#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_2 0x682BC + +#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_3 0x682C0 + +#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_4 0x682C4 + +#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 0x682C8 + +#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_1 0x682CC + +#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_2 0x682D0 + +#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_3 0x682D4 + +#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_4 0x682D8 + +#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x682E0 + +#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x682E4 + +#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x682E8 + +#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x682EC + +#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x682F0 + +#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x682F4 + +#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x682F8 + +#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x682FC + +#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x68300 + +#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x68304 + +#define mmMME0_QM_CP_FENCE0_RDATA_0 0x68308 + +#define mmMME0_QM_CP_FENCE0_RDATA_1 0x6830C + +#define mmMME0_QM_CP_FENCE0_RDATA_2 0x68310 + +#define mmMME0_QM_CP_FENCE0_RDATA_3 0x68314 + +#define mmMME0_QM_CP_FENCE0_RDATA_4 0x68318 + +#define mmMME0_QM_CP_FENCE1_RDATA_0 0x6831C + +#define mmMME0_QM_CP_FENCE1_RDATA_1 0x68320 + +#define mmMME0_QM_CP_FENCE1_RDATA_2 0x68324 + +#define mmMME0_QM_CP_FENCE1_RDATA_3 0x68328 + +#define mmMME0_QM_CP_FENCE1_RDATA_4 0x6832C + +#define mmMME0_QM_CP_FENCE2_RDATA_0 0x68330 + +#define mmMME0_QM_CP_FENCE2_RDATA_1 0x68334 + +#define mmMME0_QM_CP_FENCE2_RDATA_2 0x68338 + +#define mmMME0_QM_CP_FENCE2_RDATA_3 0x6833C + +#define mmMME0_QM_CP_FENCE2_RDATA_4 0x68340 + +#define mmMME0_QM_CP_FENCE3_RDATA_0 0x68344 + +#define mmMME0_QM_CP_FENCE3_RDATA_1 0x68348 + +#define mmMME0_QM_CP_FENCE3_RDATA_2 0x6834C + +#define mmMME0_QM_CP_FENCE3_RDATA_3 0x68350 + +#define mmMME0_QM_CP_FENCE3_RDATA_4 0x68354 + +#define mmMME0_QM_CP_FENCE0_CNT_0 0x68358 + +#define mmMME0_QM_CP_FENCE0_CNT_1 0x6835C + +#define mmMME0_QM_CP_FENCE0_CNT_2 0x68360 + +#define mmMME0_QM_CP_FENCE0_CNT_3 0x68364 + +#define mmMME0_QM_CP_FENCE0_CNT_4 0x68368 + +#define mmMME0_QM_CP_FENCE1_CNT_0 0x6836C + +#define mmMME0_QM_CP_FENCE1_CNT_1 0x68370 + +#define mmMME0_QM_CP_FENCE1_CNT_2 0x68374 + +#define mmMME0_QM_CP_FENCE1_CNT_3 0x68378 + +#define mmMME0_QM_CP_FENCE1_CNT_4 0x6837C + +#define mmMME0_QM_CP_FENCE2_CNT_0 0x68380 + +#define mmMME0_QM_CP_FENCE2_CNT_1 0x68384 + +#define mmMME0_QM_CP_FENCE2_CNT_2 0x68388 + +#define mmMME0_QM_CP_FENCE2_CNT_3 0x6838C + +#define mmMME0_QM_CP_FENCE2_CNT_4 0x68390 + +#define mmMME0_QM_CP_FENCE3_CNT_0 0x68394 + +#define mmMME0_QM_CP_FENCE3_CNT_1 0x68398 + +#define mmMME0_QM_CP_FENCE3_CNT_2 0x6839C + +#define mmMME0_QM_CP_FENCE3_CNT_3 0x683A0 + +#define mmMME0_QM_CP_FENCE3_CNT_4 0x683A4 + +#define mmMME0_QM_CP_STS_0 0x683A8 + +#define mmMME0_QM_CP_STS_1 0x683AC + +#define mmMME0_QM_CP_STS_2 0x683B0 + +#define mmMME0_QM_CP_STS_3 0x683B4 + +#define mmMME0_QM_CP_STS_4 0x683B8 + +#define mmMME0_QM_CP_CURRENT_INST_LO_0 0x683BC + +#define mmMME0_QM_CP_CURRENT_INST_LO_1 0x683C0 + +#define mmMME0_QM_CP_CURRENT_INST_LO_2 0x683C4 + +#define mmMME0_QM_CP_CURRENT_INST_LO_3 0x683C8 + +#define mmMME0_QM_CP_CURRENT_INST_LO_4 0x683CC + +#define mmMME0_QM_CP_CURRENT_INST_HI_0 0x683D0 + +#define mmMME0_QM_CP_CURRENT_INST_HI_1 0x683D4 + +#define mmMME0_QM_CP_CURRENT_INST_HI_2 0x683D8 + +#define mmMME0_QM_CP_CURRENT_INST_HI_3 0x683DC + +#define mmMME0_QM_CP_CURRENT_INST_HI_4 0x683E0 + +#define mmMME0_QM_CP_BARRIER_CFG_0 0x683F4 + +#define mmMME0_QM_CP_BARRIER_CFG_1 0x683F8 + +#define mmMME0_QM_CP_BARRIER_CFG_2 0x683FC + +#define mmMME0_QM_CP_BARRIER_CFG_3 0x68400 + +#define mmMME0_QM_CP_BARRIER_CFG_4 0x68404 + +#define mmMME0_QM_CP_DBG_0_0 0x68408 + +#define mmMME0_QM_CP_DBG_0_1 0x6840C + +#define mmMME0_QM_CP_DBG_0_2 0x68410 + +#define mmMME0_QM_CP_DBG_0_3 0x68414 + +#define mmMME0_QM_CP_DBG_0_4 0x68418 + +#define mmMME0_QM_CP_ARUSER_31_11_0 0x6841C + +#define mmMME0_QM_CP_ARUSER_31_11_1 0x68420 + +#define mmMME0_QM_CP_ARUSER_31_11_2 0x68424 + +#define mmMME0_QM_CP_ARUSER_31_11_3 0x68428 + +#define mmMME0_QM_CP_ARUSER_31_11_4 0x6842C + +#define mmMME0_QM_CP_AWUSER_31_11_0 0x68430 + +#define mmMME0_QM_CP_AWUSER_31_11_1 0x68434 + +#define mmMME0_QM_CP_AWUSER_31_11_2 0x68438 + +#define mmMME0_QM_CP_AWUSER_31_11_3 0x6843C + +#define mmMME0_QM_CP_AWUSER_31_11_4 0x68440 + +#define mmMME0_QM_ARB_CFG_0 0x68A00 + +#define mmMME0_QM_ARB_CHOISE_Q_PUSH 0x68A04 + +#define mmMME0_QM_ARB_WRR_WEIGHT_0 0x68A08 + +#define mmMME0_QM_ARB_WRR_WEIGHT_1 0x68A0C + +#define mmMME0_QM_ARB_WRR_WEIGHT_2 0x68A10 + +#define mmMME0_QM_ARB_WRR_WEIGHT_3 0x68A14 + +#define mmMME0_QM_ARB_CFG_1 0x68A18 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_0 0x68A20 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_1 0x68A24 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_2 0x68A28 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_3 0x68A2C + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_4 0x68A30 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_5 0x68A34 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_6 0x68A38 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_7 0x68A3C + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_8 0x68A40 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_9 0x68A44 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_10 0x68A48 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_11 0x68A4C + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_12 0x68A50 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_13 0x68A54 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_14 0x68A58 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_15 0x68A5C + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_16 0x68A60 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_17 0x68A64 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_18 0x68A68 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_19 0x68A6C + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_20 0x68A70 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_21 0x68A74 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_22 0x68A78 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_23 0x68A7C + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_24 0x68A80 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_25 0x68A84 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_26 0x68A88 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_27 0x68A8C + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_28 0x68A90 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_29 0x68A94 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_30 0x68A98 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_31 0x68A9C + +#define mmMME0_QM_ARB_MST_CRED_INC 0x68AA0 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x68AA4 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x68AA8 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x68AAC + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x68AB0 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x68AB4 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x68AB8 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x68ABC + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x68AC0 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x68AC4 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x68AC8 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x68ACC + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x68AD0 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x68AD4 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x68AD8 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x68ADC + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x68AE0 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x68AE4 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x68AE8 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x68AEC + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x68AF0 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x68AF4 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x68AF8 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x68AFC + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x68B00 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x68B04 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x68B08 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x68B0C + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x68B10 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x68B14 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x68B18 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x68B1C + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x68B20 + +#define mmMME0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x68B28 + +#define mmMME0_QM_ARB_MST_SLAVE_EN 0x68B2C + +#define mmMME0_QM_ARB_MST_QUIET_PER 0x68B34 + +#define mmMME0_QM_ARB_SLV_CHOISE_WDT 0x68B38 + +#define mmMME0_QM_ARB_SLV_ID 0x68B3C + +#define mmMME0_QM_ARB_MSG_MAX_INFLIGHT 0x68B44 + +#define mmMME0_QM_ARB_MSG_AWUSER_31_11 0x68B48 + +#define mmMME0_QM_ARB_MSG_AWUSER_SEC_PROP 0x68B4C + +#define mmMME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x68B50 + +#define mmMME0_QM_ARB_BASE_LO 0x68B54 + +#define mmMME0_QM_ARB_BASE_HI 0x68B58 + +#define mmMME0_QM_ARB_STATE_STS 0x68B80 + +#define mmMME0_QM_ARB_CHOISE_FULLNESS_STS 0x68B84 + +#define mmMME0_QM_ARB_MSG_STS 0x68B88 + +#define mmMME0_QM_ARB_SLV_CHOISE_Q_HEAD 0x68B8C + +#define mmMME0_QM_ARB_ERR_CAUSE 0x68B9C + +#define mmMME0_QM_ARB_ERR_MSG_EN 0x68BA0 + +#define mmMME0_QM_ARB_ERR_STS_DRP 0x68BA8 + +#define mmMME0_QM_ARB_MST_CRED_STS_0 0x68BB0 + +#define mmMME0_QM_ARB_MST_CRED_STS_1 0x68BB4 + +#define mmMME0_QM_ARB_MST_CRED_STS_2 0x68BB8 + +#define mmMME0_QM_ARB_MST_CRED_STS_3 0x68BBC + +#define mmMME0_QM_ARB_MST_CRED_STS_4 0x68BC0 + +#define mmMME0_QM_ARB_MST_CRED_STS_5 0x68BC4 + +#define mmMME0_QM_ARB_MST_CRED_STS_6 0x68BC8 + +#define mmMME0_QM_ARB_MST_CRED_STS_7 0x68BCC + +#define mmMME0_QM_ARB_MST_CRED_STS_8 0x68BD0 + +#define mmMME0_QM_ARB_MST_CRED_STS_9 0x68BD4 + +#define mmMME0_QM_ARB_MST_CRED_STS_10 0x68BD8 + +#define mmMME0_QM_ARB_MST_CRED_STS_11 0x68BDC + +#define mmMME0_QM_ARB_MST_CRED_STS_12 0x68BE0 + +#define mmMME0_QM_ARB_MST_CRED_STS_13 0x68BE4 + +#define mmMME0_QM_ARB_MST_CRED_STS_14 0x68BE8 + +#define mmMME0_QM_ARB_MST_CRED_STS_15 0x68BEC + +#define mmMME0_QM_ARB_MST_CRED_STS_16 0x68BF0 + +#define mmMME0_QM_ARB_MST_CRED_STS_17 0x68BF4 + +#define mmMME0_QM_ARB_MST_CRED_STS_18 0x68BF8 + +#define mmMME0_QM_ARB_MST_CRED_STS_19 0x68BFC + +#define mmMME0_QM_ARB_MST_CRED_STS_20 0x68C00 + +#define mmMME0_QM_ARB_MST_CRED_STS_21 0x68C04 + +#define mmMME0_QM_ARB_MST_CRED_STS_22 0x68C08 + +#define mmMME0_QM_ARB_MST_CRED_STS_23 0x68C0C + +#define mmMME0_QM_ARB_MST_CRED_STS_24 0x68C10 + +#define mmMME0_QM_ARB_MST_CRED_STS_25 0x68C14 + +#define mmMME0_QM_ARB_MST_CRED_STS_26 0x68C18 + +#define mmMME0_QM_ARB_MST_CRED_STS_27 0x68C1C + +#define mmMME0_QM_ARB_MST_CRED_STS_28 0x68C20 + +#define mmMME0_QM_ARB_MST_CRED_STS_29 0x68C24 + +#define mmMME0_QM_ARB_MST_CRED_STS_30 0x68C28 + +#define mmMME0_QM_ARB_MST_CRED_STS_31 0x68C2C + +#define mmMME0_QM_CGM_CFG 0x68C70 + +#define mmMME0_QM_CGM_STS 0x68C74 + +#define mmMME0_QM_CGM_CFG1 0x68C78 + +#define mmMME0_QM_LOCAL_RANGE_BASE 0x68C80 + +#define mmMME0_QM_LOCAL_RANGE_SIZE 0x68C84 + +#define mmMME0_QM_CSMR_STRICT_PRIO_CFG 0x68C90 + +#define mmMME0_QM_HBW_RD_RATE_LIM_CFG_1 0x68C94 + +#define mmMME0_QM_LBW_WR_RATE_LIM_CFG_0 0x68C98 + +#define mmMME0_QM_LBW_WR_RATE_LIM_CFG_1 0x68C9C + +#define mmMME0_QM_HBW_RD_RATE_LIM_CFG_0 0x68CA0 + +#define mmMME0_QM_GLBL_AXCACHE 0x68CA4 + +#define mmMME0_QM_IND_GW_APB_CFG 0x68CB0 + +#define mmMME0_QM_IND_GW_APB_WDATA 0x68CB4 + +#define mmMME0_QM_IND_GW_APB_RDATA 0x68CB8 + +#define mmMME0_QM_IND_GW_APB_STATUS 0x68CBC + +#define mmMME0_QM_GLBL_ERR_ADDR_LO 0x68CD0 + +#define mmMME0_QM_GLBL_ERR_ADDR_HI 0x68CD4 + +#define mmMME0_QM_GLBL_ERR_WDATA 0x68CD8 + +#define mmMME0_QM_GLBL_MEM_INIT_BUSY 0x68D00 + +#endif /* ASIC_REG_MME0_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/mme1_ctrl_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme1_ctrl_regs.h new file mode 100644 index 000000000000..6c07f7d45490 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme1_ctrl_regs.h @@ -0,0 +1,1456 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME1_CTRL_REGS_H_ +#define ASIC_REG_MME1_CTRL_REGS_H_ + +/* + ***************************************** + * MME1_CTRL (Prototype: MME) + ***************************************** + */ + +#define mmMME1_CTRL_ARCH_STATUS 0xE0000 + +#define mmMME1_CTRL_ARCH_BASE_ADDR_HIGH_S 0xE0008 + +#define mmMME1_CTRL_ARCH_BASE_ADDR_HIGH_L 0xE000C + +#define mmMME1_CTRL_ARCH_BASE_ADDR_HIGH_O 0xE0010 + +#define mmMME1_CTRL_ARCH_BASE_ADDR_LOW_S 0xE0014 + +#define mmMME1_CTRL_ARCH_BASE_ADDR_LOW_L 0xE0018 + +#define mmMME1_CTRL_ARCH_BASE_ADDR_LOW_O 0xE001C + +#define mmMME1_CTRL_ARCH_HEADER_LOW 0xE0020 + +#define mmMME1_CTRL_ARCH_HEADER_HIGH 0xE0024 + +#define mmMME1_CTRL_ARCH_CONV_KERNEL_SIZE_MINUS_1 0xE0028 + +#define mmMME1_CTRL_ARCH_CONV_ASSOCIATED_DIMS_LOW 0xE002C + +#define mmMME1_CTRL_ARCH_CONV_ASSOCIATED_DIMS_HIGH 0xE0030 + +#define mmMME1_CTRL_ARCH_NUM_ITERATIONS_MINUS_1 0xE0034 + +#define mmMME1_CTRL_ARCH_OUTER_LOOP 0xE0038 + +#define mmMME1_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_0 0xE003C + +#define mmMME1_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_1 0xE0040 + +#define mmMME1_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_2 0xE0044 + +#define mmMME1_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_3 0xE0048 + +#define mmMME1_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_4 0xE004C + +#define mmMME1_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_0 0xE0050 + +#define mmMME1_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_1 0xE0054 + +#define mmMME1_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_2 0xE0058 + +#define mmMME1_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_3 0xE005C + +#define mmMME1_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_4 0xE0060 + +#define mmMME1_CTRL_ARCH_TENSOR_S_ROI_SIZE_0 0xE0064 + +#define mmMME1_CTRL_ARCH_TENSOR_S_ROI_SIZE_1 0xE0068 + +#define mmMME1_CTRL_ARCH_TENSOR_S_ROI_SIZE_2 0xE006C + +#define mmMME1_CTRL_ARCH_TENSOR_S_ROI_SIZE_3 0xE0070 + +#define mmMME1_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_0 0xE0074 + +#define mmMME1_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_1 0xE0078 + +#define mmMME1_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_2 0xE007C + +#define mmMME1_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_3 0xE0080 + +#define mmMME1_CTRL_ARCH_TENSOR_S_SPATIAL_SIZE_MINUS_1 0xE0084 + +#define mmMME1_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_0 0xE0088 + +#define mmMME1_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_1 0xE008C + +#define mmMME1_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_2 0xE0090 + +#define mmMME1_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_3 0xE0094 + +#define mmMME1_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_4 0xE0098 + +#define mmMME1_CTRL_ARCH_AGU_S_START_OFFSET_0 0xE009C + +#define mmMME1_CTRL_ARCH_AGU_S_START_OFFSET_1 0xE00A0 + +#define mmMME1_CTRL_ARCH_AGU_S_START_OFFSET_2 0xE00A4 + +#define mmMME1_CTRL_ARCH_AGU_S_START_OFFSET_3 0xE00A8 + +#define mmMME1_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_0 0xE00AC + +#define mmMME1_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_1 0xE00B0 + +#define mmMME1_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_2 0xE00B4 + +#define mmMME1_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_3 0xE00B8 + +#define mmMME1_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_4 0xE00BC + +#define mmMME1_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_0 0xE00C0 + +#define mmMME1_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_1 0xE00C4 + +#define mmMME1_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_2 0xE00C8 + +#define mmMME1_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_3 0xE00CC + +#define mmMME1_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_4 0xE00D0 + +#define mmMME1_CTRL_ARCH_TENSOR_L_ROI_SIZE_0 0xE00D4 + +#define mmMME1_CTRL_ARCH_TENSOR_L_ROI_SIZE_1 0xE00D8 + +#define mmMME1_CTRL_ARCH_TENSOR_L_ROI_SIZE_2 0xE00DC + +#define mmMME1_CTRL_ARCH_TENSOR_L_ROI_SIZE_3 0xE00E0 + +#define mmMME1_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_0 0xE00E4 + +#define mmMME1_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_1 0xE00E8 + +#define mmMME1_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_2 0xE00EC + +#define mmMME1_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_3 0xE00F0 + +#define mmMME1_CTRL_ARCH_TENSOR_L_SPATIAL_SIZE_MINUS_1 0xE00F4 + +#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0xE00F8 + +#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0xE00FC + +#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0xE0100 + +#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0xE0104 + +#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0xE0108 + +#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_0 0xE010C + +#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_1 0xE0110 + +#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_2 0xE0114 + +#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_3 0xE0118 + +#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0xE011C + +#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0xE0120 + +#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0xE0124 + +#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0xE0128 + +#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0xE012C + +#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_0 0xE0130 + +#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_1 0xE0134 + +#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_2 0xE0138 + +#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_3 0xE013C + +#define mmMME1_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_0 0xE0140 + +#define mmMME1_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_1 0xE0144 + +#define mmMME1_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_2 0xE0148 + +#define mmMME1_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_3 0xE014C + +#define mmMME1_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_4 0xE0150 + +#define mmMME1_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_0 0xE0154 + +#define mmMME1_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_1 0xE0158 + +#define mmMME1_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_2 0xE015C + +#define mmMME1_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_3 0xE0160 + +#define mmMME1_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_4 0xE0164 + +#define mmMME1_CTRL_ARCH_TENSOR_O_ROI_SIZE_0 0xE0168 + +#define mmMME1_CTRL_ARCH_TENSOR_O_ROI_SIZE_1 0xE016C + +#define mmMME1_CTRL_ARCH_TENSOR_O_ROI_SIZE_2 0xE0170 + +#define mmMME1_CTRL_ARCH_TENSOR_O_ROI_SIZE_3 0xE0174 + +#define mmMME1_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_0 0xE0178 + +#define mmMME1_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_1 0xE017C + +#define mmMME1_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_2 0xE0180 + +#define mmMME1_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_3 0xE0184 + +#define mmMME1_CTRL_ARCH_TENSOR_O_SPATIAL_SIZE_MINUS_1 0xE0188 + +#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0xE018C + +#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0xE0190 + +#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0xE0194 + +#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0xE0198 + +#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0xE019C + +#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_0 0xE01A0 + +#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_1 0xE01A4 + +#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_2 0xE01A8 + +#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_3 0xE01AC + +#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0xE01B0 + +#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0xE01B4 + +#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0xE01B8 + +#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0xE01BC + +#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0xE01C0 + +#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_0 0xE01C4 + +#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_1 0xE01C8 + +#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_2 0xE01CC + +#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_3 0xE01D0 + +#define mmMME1_CTRL_ARCH_DESC_SB_REPEAT 0xE01D4 + +#define mmMME1_CTRL_ARCH_DESC_RATE_LIMITER 0xE01D8 + +#define mmMME1_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0xE01DC + +#define mmMME1_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0xE01E0 + +#define mmMME1_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_HIGH 0xE01E4 + +#define mmMME1_CTRL_ARCH_DESC_SYNC_OBJECT_DATA 0xE01E8 + +#define mmMME1_CTRL_ARCH_DESC_AXI_USER_DATA 0xE01EC + +#define mmMME1_CTRL_ARCH_DESC_PERF_EVT_S 0xE01F0 + +#define mmMME1_CTRL_ARCH_DESC_PERF_EVT_L_LOCAL 0xE01F4 + +#define mmMME1_CTRL_ARCH_DESC_PERF_EVT_L_REMOTE 0xE01F8 + +#define mmMME1_CTRL_ARCH_DESC_PERF_EVT_O_LOCAL 0xE01FC + +#define mmMME1_CTRL_ARCH_DESC_PERF_EVT_O_REMOTE 0xE0200 + +#define mmMME1_CTRL_ARCH_DESC_PADDING_VALUE_S 0xE0204 + +#define mmMME1_CTRL_ARCH_DESC_PADDING_VALUE_L 0xE0208 + +#define mmMME1_CTRL_ARCH_DESC_META_DATA_AGU_S 0xE020C + +#define mmMME1_CTRL_ARCH_DESC_META_DATA_AGU_L_LOCAL 0xE0210 + +#define mmMME1_CTRL_ARCH_DESC_META_DATA_AGU_L_REMOTE 0xE0214 + +#define mmMME1_CTRL_ARCH_DESC_META_DATA_AGU_O_LOCAL 0xE0218 + +#define mmMME1_CTRL_ARCH_DESC_META_DATA_AGU_O_REMOTE 0xE021C + +#define mmMME1_CTRL_ARCH_DESC_PCU_RL_SATURATION 0xE0220 + +#define mmMME1_CTRL_ARCH_DESC_DUMMY 0xE0224 + +#define mmMME1_CTRL_CMD 0xE0280 + +#define mmMME1_CTRL_STATUS1 0xE0284 + +#define mmMME1_CTRL_RESET 0xE0288 + +#define mmMME1_CTRL_QM_STALL 0xE028C + +#define mmMME1_CTRL_SYNC_OBJECT_FIFO_TH 0xE0290 + +#define mmMME1_CTRL_EUS_ROLLUP_CNT_ADD 0xE0294 + +#define mmMME1_CTRL_INTR_CAUSE 0xE0298 + +#define mmMME1_CTRL_INTR_MASK 0xE029C + +#define mmMME1_CTRL_LOG_SHADOW 0xE02A0 + +#define mmMME1_CTRL_PCU_RL_DESC0 0xE02A4 + +#define mmMME1_CTRL_PCU_RL_TOKEN_UPDATE 0xE02A8 + +#define mmMME1_CTRL_PCU_RL_TH 0xE02AC + +#define mmMME1_CTRL_PCU_RL_MIN 0xE02B0 + +#define mmMME1_CTRL_PCU_RL_CTRL_EN 0xE02B4 + +#define mmMME1_CTRL_PCU_RL_HISTORY_LOG_SIZE 0xE02B8 + +#define mmMME1_CTRL_PCU_DUMMY_A_BF16 0xE02BC + +#define mmMME1_CTRL_PCU_DUMMY_B_BF16 0xE02C0 + +#define mmMME1_CTRL_PCU_DUMMY_A_FP32_ODD 0xE02C4 + +#define mmMME1_CTRL_PCU_DUMMY_A_FP32_EVEN 0xE02C8 + +#define mmMME1_CTRL_PCU_DUMMY_B_FP32_ODD 0xE02CC + +#define mmMME1_CTRL_PCU_DUMMY_B_FP32_EVEN 0xE02D0 + +#define mmMME1_CTRL_PROT 0xE02D4 + +#define mmMME1_CTRL_EU_POWER_SAVE_DISABLE 0xE02D8 + +#define mmMME1_CTRL_CS_DBG_BLOCK_ID 0xE02DC + +#define mmMME1_CTRL_CS_DBG_STATUS_DROP_CNT 0xE02E0 + +#define mmMME1_CTRL_TE_CLOSE_CGATE 0xE02E4 + +#define mmMME1_CTRL_AGU_SM_INFLIGHT_CNTR 0xE02E8 + +#define mmMME1_CTRL_AGU_SM_TOTAL_CNTR 0xE02EC + +#define mmMME1_CTRL_EZSYNC_OUT_CREDIT 0xE02F0 + +#define mmMME1_CTRL_PCU_RL_SAT_SEC 0xE02F4 + +#define mmMME1_CTRL_AGU_SYNC_MSG_AXI_USER 0xE02F8 + +#define mmMME1_CTRL_QM_SLV_LBW_CLK_EN 0xE02FC + +#define mmMME1_CTRL_SHADOW_0_STATUS 0xE0400 + +#define mmMME1_CTRL_SHADOW_0_BASE_ADDR_HIGH_S 0xE0408 + +#define mmMME1_CTRL_SHADOW_0_BASE_ADDR_HIGH_L 0xE040C + +#define mmMME1_CTRL_SHADOW_0_BASE_ADDR_HIGH_O 0xE0410 + +#define mmMME1_CTRL_SHADOW_0_BASE_ADDR_LOW_S 0xE0414 + +#define mmMME1_CTRL_SHADOW_0_BASE_ADDR_LOW_L 0xE0418 + +#define mmMME1_CTRL_SHADOW_0_BASE_ADDR_LOW_O 0xE041C + +#define mmMME1_CTRL_SHADOW_0_HEADER_LOW 0xE0420 + +#define mmMME1_CTRL_SHADOW_0_HEADER_HIGH 0xE0424 + +#define mmMME1_CTRL_SHADOW_0_CONV_KERNEL_SIZE_MINUS_1 0xE0428 + +#define mmMME1_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_LOW 0xE042C + +#define mmMME1_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_HIGH 0xE0430 + +#define mmMME1_CTRL_SHADOW_0_NUM_ITERATIONS_MINUS_1 0xE0434 + +#define mmMME1_CTRL_SHADOW_0_OUTER_LOOP 0xE0438 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_0 0xE043C + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_1 0xE0440 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_2 0xE0444 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_3 0xE0448 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_4 0xE044C + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_0 0xE0450 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_1 0xE0454 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_2 0xE0458 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_3 0xE045C + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_4 0xE0460 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_0 0xE0464 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_1 0xE0468 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_2 0xE046C + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_3 0xE0470 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_0 0xE0474 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_1 0xE0478 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_2 0xE047C + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_3 0xE0480 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_SPATIAL_SIZE_MINUS_1 0xE0484 + +#define mmMME1_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_0 0xE0488 + +#define mmMME1_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_1 0xE048C + +#define mmMME1_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_2 0xE0490 + +#define mmMME1_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_3 0xE0494 + +#define mmMME1_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_4 0xE0498 + +#define mmMME1_CTRL_SHADOW_0_AGU_S_START_OFFSET_0 0xE049C + +#define mmMME1_CTRL_SHADOW_0_AGU_S_START_OFFSET_1 0xE04A0 + +#define mmMME1_CTRL_SHADOW_0_AGU_S_START_OFFSET_2 0xE04A4 + +#define mmMME1_CTRL_SHADOW_0_AGU_S_START_OFFSET_3 0xE04A8 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_0 0xE04AC + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_1 0xE04B0 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_2 0xE04B4 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_3 0xE04B8 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_4 0xE04BC + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_0 0xE04C0 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_1 0xE04C4 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_2 0xE04C8 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_3 0xE04CC + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_4 0xE04D0 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_0 0xE04D4 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_1 0xE04D8 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_2 0xE04DC + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_3 0xE04E0 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_0 0xE04E4 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_1 0xE04E8 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_2 0xE04EC + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_3 0xE04F0 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_SPATIAL_SIZE_MINUS_1 0xE04F4 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0xE04F8 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0xE04FC + +#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0xE0500 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0xE0504 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0xE0508 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_0 0xE050C + +#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_1 0xE0510 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_2 0xE0514 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_3 0xE0518 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0xE051C + +#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0xE0520 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0xE0524 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0xE0528 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0xE052C + +#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_0 0xE0530 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_1 0xE0534 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_2 0xE0538 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_3 0xE053C + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_0 0xE0540 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_1 0xE0544 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_2 0xE0548 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_3 0xE054C + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_4 0xE0550 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_0 0xE0554 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_1 0xE0558 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_2 0xE055C + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_3 0xE0560 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_4 0xE0564 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_0 0xE0568 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_1 0xE056C + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_2 0xE0570 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_3 0xE0574 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_0 0xE0578 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_1 0xE057C + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_2 0xE0580 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_3 0xE0584 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_SPATIAL_SIZE_MINUS_1 0xE0588 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0xE058C + +#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0xE0590 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0xE0594 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0xE0598 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0xE059C + +#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_0 0xE05A0 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_1 0xE05A4 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_2 0xE05A8 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_3 0xE05AC + +#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0xE05B0 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0xE05B4 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0xE05B8 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0xE05BC + +#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0xE05C0 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_0 0xE05C4 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_1 0xE05C8 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_2 0xE05CC + +#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_3 0xE05D0 + +#define mmMME1_CTRL_SHADOW_0_DESC_SB_REPEAT 0xE05D4 + +#define mmMME1_CTRL_SHADOW_0_DESC_RATE_LIMITER 0xE05D8 + +#define mmMME1_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0xE05DC + +#define mmMME1_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0xE05E0 + +#define mmMME1_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_HIGH 0xE05E4 + +#define mmMME1_CTRL_SHADOW_0_DESC_SYNC_OBJECT_DATA 0xE05E8 + +#define mmMME1_CTRL_SHADOW_0_DESC_AXI_USER_DATA 0xE05EC + +#define mmMME1_CTRL_SHADOW_0_DESC_PERF_EVT_S 0xE05F0 + +#define mmMME1_CTRL_SHADOW_0_DESC_PERF_EVT_L_LOCAL 0xE05F4 + +#define mmMME1_CTRL_SHADOW_0_DESC_PERF_EVT_L_REMOTE 0xE05F8 + +#define mmMME1_CTRL_SHADOW_0_DESC_PERF_EVT_O_LOCAL 0xE05FC + +#define mmMME1_CTRL_SHADOW_0_DESC_PERF_EVT_O_REMOTE 0xE0600 + +#define mmMME1_CTRL_SHADOW_0_DESC_PADDING_VALUE_S 0xE0604 + +#define mmMME1_CTRL_SHADOW_0_DESC_PADDING_VALUE_L 0xE0608 + +#define mmMME1_CTRL_SHADOW_0_DESC_META_DATA_AGU_S 0xE060C + +#define mmMME1_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_LOCAL 0xE0610 + +#define mmMME1_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_REMOTE 0xE0614 + +#define mmMME1_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_LOCAL 0xE0618 + +#define mmMME1_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_REMOTE 0xE061C + +#define mmMME1_CTRL_SHADOW_0_DESC_PCU_RL_SATURATION 0xE0620 + +#define mmMME1_CTRL_SHADOW_0_DESC_DUMMY 0xE0624 + +#define mmMME1_CTRL_SHADOW_1_STATUS 0xE0680 + +#define mmMME1_CTRL_SHADOW_1_BASE_ADDR_HIGH_S 0xE0688 + +#define mmMME1_CTRL_SHADOW_1_BASE_ADDR_HIGH_L 0xE068C + +#define mmMME1_CTRL_SHADOW_1_BASE_ADDR_HIGH_O 0xE0690 + +#define mmMME1_CTRL_SHADOW_1_BASE_ADDR_LOW_S 0xE0694 + +#define mmMME1_CTRL_SHADOW_1_BASE_ADDR_LOW_L 0xE0698 + +#define mmMME1_CTRL_SHADOW_1_BASE_ADDR_LOW_O 0xE069C + +#define mmMME1_CTRL_SHADOW_1_HEADER_LOW 0xE06A0 + +#define mmMME1_CTRL_SHADOW_1_HEADER_HIGH 0xE06A4 + +#define mmMME1_CTRL_SHADOW_1_CONV_KERNEL_SIZE_MINUS_1 0xE06A8 + +#define mmMME1_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_LOW 0xE06AC + +#define mmMME1_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_HIGH 0xE06B0 + +#define mmMME1_CTRL_SHADOW_1_NUM_ITERATIONS_MINUS_1 0xE06B4 + +#define mmMME1_CTRL_SHADOW_1_OUTER_LOOP 0xE06B8 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_0 0xE06BC + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_1 0xE06C0 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_2 0xE06C4 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_3 0xE06C8 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_4 0xE06CC + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_0 0xE06D0 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_1 0xE06D4 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_2 0xE06D8 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_3 0xE06DC + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_4 0xE06E0 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_0 0xE06E4 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_1 0xE06E8 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_2 0xE06EC + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_3 0xE06F0 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_0 0xE06F4 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_1 0xE06F8 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_2 0xE06FC + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_3 0xE0700 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_SPATIAL_SIZE_MINUS_1 0xE0704 + +#define mmMME1_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_0 0xE0708 + +#define mmMME1_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_1 0xE070C + +#define mmMME1_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_2 0xE0710 + +#define mmMME1_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_3 0xE0714 + +#define mmMME1_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_4 0xE0718 + +#define mmMME1_CTRL_SHADOW_1_AGU_S_START_OFFSET_0 0xE071C + +#define mmMME1_CTRL_SHADOW_1_AGU_S_START_OFFSET_1 0xE0720 + +#define mmMME1_CTRL_SHADOW_1_AGU_S_START_OFFSET_2 0xE0724 + +#define mmMME1_CTRL_SHADOW_1_AGU_S_START_OFFSET_3 0xE0728 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_0 0xE072C + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_1 0xE0730 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_2 0xE0734 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_3 0xE0738 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_4 0xE073C + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_0 0xE0740 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_1 0xE0744 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_2 0xE0748 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_3 0xE074C + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_4 0xE0750 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_0 0xE0754 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_1 0xE0758 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_2 0xE075C + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_3 0xE0760 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_0 0xE0764 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_1 0xE0768 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_2 0xE076C + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_3 0xE0770 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_SPATIAL_SIZE_MINUS_1 0xE0774 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0xE0778 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0xE077C + +#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0xE0780 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0xE0784 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0xE0788 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_0 0xE078C + +#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_1 0xE0790 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_2 0xE0794 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_3 0xE0798 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0xE079C + +#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0xE07A0 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0xE07A4 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0xE07A8 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0xE07AC + +#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_0 0xE07B0 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_1 0xE07B4 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_2 0xE07B8 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_3 0xE07BC + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_0 0xE07C0 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_1 0xE07C4 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_2 0xE07C8 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_3 0xE07CC + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_4 0xE07D0 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_0 0xE07D4 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_1 0xE07D8 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_2 0xE07DC + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_3 0xE07E0 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_4 0xE07E4 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_0 0xE07E8 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_1 0xE07EC + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_2 0xE07F0 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_3 0xE07F4 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_0 0xE07F8 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_1 0xE07FC + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_2 0xE0800 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_3 0xE0804 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_SPATIAL_SIZE_MINUS_1 0xE0808 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0xE080C + +#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0xE0810 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0xE0814 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0xE0818 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0xE081C + +#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_0 0xE0820 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_1 0xE0824 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_2 0xE0828 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_3 0xE082C + +#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0xE0830 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0xE0834 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0xE0838 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0xE083C + +#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0xE0840 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_0 0xE0844 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_1 0xE0848 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_2 0xE084C + +#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_3 0xE0850 + +#define mmMME1_CTRL_SHADOW_1_DESC_SB_REPEAT 0xE0854 + +#define mmMME1_CTRL_SHADOW_1_DESC_RATE_LIMITER 0xE0858 + +#define mmMME1_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0xE085C + +#define mmMME1_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0xE0860 + +#define mmMME1_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_HIGH 0xE0864 + +#define mmMME1_CTRL_SHADOW_1_DESC_SYNC_OBJECT_DATA 0xE0868 + +#define mmMME1_CTRL_SHADOW_1_DESC_AXI_USER_DATA 0xE086C + +#define mmMME1_CTRL_SHADOW_1_DESC_PERF_EVT_S 0xE0870 + +#define mmMME1_CTRL_SHADOW_1_DESC_PERF_EVT_L_LOCAL 0xE0874 + +#define mmMME1_CTRL_SHADOW_1_DESC_PERF_EVT_L_REMOTE 0xE0878 + +#define mmMME1_CTRL_SHADOW_1_DESC_PERF_EVT_O_LOCAL 0xE087C + +#define mmMME1_CTRL_SHADOW_1_DESC_PERF_EVT_O_REMOTE 0xE0880 + +#define mmMME1_CTRL_SHADOW_1_DESC_PADDING_VALUE_S 0xE0884 + +#define mmMME1_CTRL_SHADOW_1_DESC_PADDING_VALUE_L 0xE0888 + +#define mmMME1_CTRL_SHADOW_1_DESC_META_DATA_AGU_S 0xE088C + +#define mmMME1_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_LOCAL 0xE0890 + +#define mmMME1_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_REMOTE 0xE0894 + +#define mmMME1_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_LOCAL 0xE0898 + +#define mmMME1_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_REMOTE 0xE089C + +#define mmMME1_CTRL_SHADOW_1_DESC_PCU_RL_SATURATION 0xE08A0 + +#define mmMME1_CTRL_SHADOW_1_DESC_DUMMY 0xE08A4 + +#define mmMME1_CTRL_SHADOW_2_STATUS 0xE0900 + +#define mmMME1_CTRL_SHADOW_2_BASE_ADDR_HIGH_S 0xE0908 + +#define mmMME1_CTRL_SHADOW_2_BASE_ADDR_HIGH_L 0xE090C + +#define mmMME1_CTRL_SHADOW_2_BASE_ADDR_HIGH_O 0xE0910 + +#define mmMME1_CTRL_SHADOW_2_BASE_ADDR_LOW_S 0xE0914 + +#define mmMME1_CTRL_SHADOW_2_BASE_ADDR_LOW_L 0xE0918 + +#define mmMME1_CTRL_SHADOW_2_BASE_ADDR_LOW_O 0xE091C + +#define mmMME1_CTRL_SHADOW_2_HEADER_LOW 0xE0920 + +#define mmMME1_CTRL_SHADOW_2_HEADER_HIGH 0xE0924 + +#define mmMME1_CTRL_SHADOW_2_CONV_KERNEL_SIZE_MINUS_1 0xE0928 + +#define mmMME1_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_LOW 0xE092C + +#define mmMME1_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_HIGH 0xE0930 + +#define mmMME1_CTRL_SHADOW_2_NUM_ITERATIONS_MINUS_1 0xE0934 + +#define mmMME1_CTRL_SHADOW_2_OUTER_LOOP 0xE0938 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_0 0xE093C + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_1 0xE0940 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_2 0xE0944 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_3 0xE0948 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_4 0xE094C + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_0 0xE0950 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_1 0xE0954 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_2 0xE0958 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_3 0xE095C + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_4 0xE0960 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_0 0xE0964 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_1 0xE0968 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_2 0xE096C + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_3 0xE0970 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_0 0xE0974 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_1 0xE0978 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_2 0xE097C + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_3 0xE0980 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_SPATIAL_SIZE_MINUS_1 0xE0984 + +#define mmMME1_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_0 0xE0988 + +#define mmMME1_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_1 0xE098C + +#define mmMME1_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_2 0xE0990 + +#define mmMME1_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_3 0xE0994 + +#define mmMME1_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_4 0xE0998 + +#define mmMME1_CTRL_SHADOW_2_AGU_S_START_OFFSET_0 0xE099C + +#define mmMME1_CTRL_SHADOW_2_AGU_S_START_OFFSET_1 0xE09A0 + +#define mmMME1_CTRL_SHADOW_2_AGU_S_START_OFFSET_2 0xE09A4 + +#define mmMME1_CTRL_SHADOW_2_AGU_S_START_OFFSET_3 0xE09A8 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_0 0xE09AC + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_1 0xE09B0 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_2 0xE09B4 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_3 0xE09B8 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_4 0xE09BC + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_0 0xE09C0 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_1 0xE09C4 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_2 0xE09C8 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_3 0xE09CC + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_4 0xE09D0 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_0 0xE09D4 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_1 0xE09D8 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_2 0xE09DC + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_3 0xE09E0 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_0 0xE09E4 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_1 0xE09E8 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_2 0xE09EC + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_3 0xE09F0 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_SPATIAL_SIZE_MINUS_1 0xE09F4 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0xE09F8 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0xE09FC + +#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0xE0A00 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0xE0A04 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0xE0A08 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_0 0xE0A0C + +#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_1 0xE0A10 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_2 0xE0A14 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_3 0xE0A18 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0xE0A1C + +#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0xE0A20 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0xE0A24 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0xE0A28 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0xE0A2C + +#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_0 0xE0A30 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_1 0xE0A34 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_2 0xE0A38 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_3 0xE0A3C + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_0 0xE0A40 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_1 0xE0A44 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_2 0xE0A48 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_3 0xE0A4C + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_4 0xE0A50 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_0 0xE0A54 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_1 0xE0A58 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_2 0xE0A5C + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_3 0xE0A60 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_4 0xE0A64 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_0 0xE0A68 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_1 0xE0A6C + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_2 0xE0A70 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_3 0xE0A74 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_0 0xE0A78 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_1 0xE0A7C + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_2 0xE0A80 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_3 0xE0A84 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_SPATIAL_SIZE_MINUS_1 0xE0A88 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0xE0A8C + +#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0xE0A90 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0xE0A94 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0xE0A98 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0xE0A9C + +#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_0 0xE0AA0 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_1 0xE0AA4 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_2 0xE0AA8 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_3 0xE0AAC + +#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0xE0AB0 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0xE0AB4 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0xE0AB8 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0xE0ABC + +#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0xE0AC0 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_0 0xE0AC4 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_1 0xE0AC8 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_2 0xE0ACC + +#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_3 0xE0AD0 + +#define mmMME1_CTRL_SHADOW_2_DESC_SB_REPEAT 0xE0AD4 + +#define mmMME1_CTRL_SHADOW_2_DESC_RATE_LIMITER 0xE0AD8 + +#define mmMME1_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0xE0ADC + +#define mmMME1_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0xE0AE0 + +#define mmMME1_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_HIGH 0xE0AE4 + +#define mmMME1_CTRL_SHADOW_2_DESC_SYNC_OBJECT_DATA 0xE0AE8 + +#define mmMME1_CTRL_SHADOW_2_DESC_AXI_USER_DATA 0xE0AEC + +#define mmMME1_CTRL_SHADOW_2_DESC_PERF_EVT_S 0xE0AF0 + +#define mmMME1_CTRL_SHADOW_2_DESC_PERF_EVT_L_LOCAL 0xE0AF4 + +#define mmMME1_CTRL_SHADOW_2_DESC_PERF_EVT_L_REMOTE 0xE0AF8 + +#define mmMME1_CTRL_SHADOW_2_DESC_PERF_EVT_O_LOCAL 0xE0AFC + +#define mmMME1_CTRL_SHADOW_2_DESC_PERF_EVT_O_REMOTE 0xE0B00 + +#define mmMME1_CTRL_SHADOW_2_DESC_PADDING_VALUE_S 0xE0B04 + +#define mmMME1_CTRL_SHADOW_2_DESC_PADDING_VALUE_L 0xE0B08 + +#define mmMME1_CTRL_SHADOW_2_DESC_META_DATA_AGU_S 0xE0B0C + +#define mmMME1_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_LOCAL 0xE0B10 + +#define mmMME1_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_REMOTE 0xE0B14 + +#define mmMME1_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_LOCAL 0xE0B18 + +#define mmMME1_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_REMOTE 0xE0B1C + +#define mmMME1_CTRL_SHADOW_2_DESC_PCU_RL_SATURATION 0xE0B20 + +#define mmMME1_CTRL_SHADOW_2_DESC_DUMMY 0xE0B24 + +#define mmMME1_CTRL_SHADOW_3_STATUS 0xE0B80 + +#define mmMME1_CTRL_SHADOW_3_BASE_ADDR_HIGH_S 0xE0B88 + +#define mmMME1_CTRL_SHADOW_3_BASE_ADDR_HIGH_L 0xE0B8C + +#define mmMME1_CTRL_SHADOW_3_BASE_ADDR_HIGH_O 0xE0B90 + +#define mmMME1_CTRL_SHADOW_3_BASE_ADDR_LOW_S 0xE0B94 + +#define mmMME1_CTRL_SHADOW_3_BASE_ADDR_LOW_L 0xE0B98 + +#define mmMME1_CTRL_SHADOW_3_BASE_ADDR_LOW_O 0xE0B9C + +#define mmMME1_CTRL_SHADOW_3_HEADER_LOW 0xE0BA0 + +#define mmMME1_CTRL_SHADOW_3_HEADER_HIGH 0xE0BA4 + +#define mmMME1_CTRL_SHADOW_3_CONV_KERNEL_SIZE_MINUS_1 0xE0BA8 + +#define mmMME1_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_LOW 0xE0BAC + +#define mmMME1_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_HIGH 0xE0BB0 + +#define mmMME1_CTRL_SHADOW_3_NUM_ITERATIONS_MINUS_1 0xE0BB4 + +#define mmMME1_CTRL_SHADOW_3_OUTER_LOOP 0xE0BB8 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_0 0xE0BBC + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_1 0xE0BC0 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_2 0xE0BC4 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_3 0xE0BC8 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_4 0xE0BCC + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_0 0xE0BD0 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_1 0xE0BD4 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_2 0xE0BD8 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_3 0xE0BDC + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_4 0xE0BE0 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_0 0xE0BE4 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_1 0xE0BE8 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_2 0xE0BEC + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_3 0xE0BF0 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_0 0xE0BF4 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_1 0xE0BF8 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_2 0xE0BFC + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_3 0xE0C00 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_SPATIAL_SIZE_MINUS_1 0xE0C04 + +#define mmMME1_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_0 0xE0C08 + +#define mmMME1_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_1 0xE0C0C + +#define mmMME1_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_2 0xE0C10 + +#define mmMME1_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_3 0xE0C14 + +#define mmMME1_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_4 0xE0C18 + +#define mmMME1_CTRL_SHADOW_3_AGU_S_START_OFFSET_0 0xE0C1C + +#define mmMME1_CTRL_SHADOW_3_AGU_S_START_OFFSET_1 0xE0C20 + +#define mmMME1_CTRL_SHADOW_3_AGU_S_START_OFFSET_2 0xE0C24 + +#define mmMME1_CTRL_SHADOW_3_AGU_S_START_OFFSET_3 0xE0C28 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_0 0xE0C2C + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_1 0xE0C30 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_2 0xE0C34 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_3 0xE0C38 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_4 0xE0C3C + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_0 0xE0C40 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_1 0xE0C44 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_2 0xE0C48 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_3 0xE0C4C + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_4 0xE0C50 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_0 0xE0C54 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_1 0xE0C58 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_2 0xE0C5C + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_3 0xE0C60 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_0 0xE0C64 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_1 0xE0C68 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_2 0xE0C6C + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_3 0xE0C70 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_SPATIAL_SIZE_MINUS_1 0xE0C74 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0xE0C78 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0xE0C7C + +#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0xE0C80 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0xE0C84 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0xE0C88 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_0 0xE0C8C + +#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_1 0xE0C90 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_2 0xE0C94 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_3 0xE0C98 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0xE0C9C + +#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0xE0CA0 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0xE0CA4 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0xE0CA8 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0xE0CAC + +#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_0 0xE0CB0 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_1 0xE0CB4 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_2 0xE0CB8 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_3 0xE0CBC + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_0 0xE0CC0 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_1 0xE0CC4 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_2 0xE0CC8 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_3 0xE0CCC + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_4 0xE0CD0 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_0 0xE0CD4 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_1 0xE0CD8 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_2 0xE0CDC + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_3 0xE0CE0 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_4 0xE0CE4 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_0 0xE0CE8 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_1 0xE0CEC + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_2 0xE0CF0 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_3 0xE0CF4 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_0 0xE0CF8 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_1 0xE0CFC + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_2 0xE0D00 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_3 0xE0D04 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_SPATIAL_SIZE_MINUS_1 0xE0D08 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0xE0D0C + +#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0xE0D10 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0xE0D14 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0xE0D18 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0xE0D1C + +#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_0 0xE0D20 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_1 0xE0D24 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_2 0xE0D28 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_3 0xE0D2C + +#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0xE0D30 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0xE0D34 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0xE0D38 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0xE0D3C + +#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0xE0D40 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_0 0xE0D44 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_1 0xE0D48 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_2 0xE0D4C + +#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_3 0xE0D50 + +#define mmMME1_CTRL_SHADOW_3_DESC_SB_REPEAT 0xE0D54 + +#define mmMME1_CTRL_SHADOW_3_DESC_RATE_LIMITER 0xE0D58 + +#define mmMME1_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0xE0D5C + +#define mmMME1_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0xE0D60 + +#define mmMME1_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_HIGH 0xE0D64 + +#define mmMME1_CTRL_SHADOW_3_DESC_SYNC_OBJECT_DATA 0xE0D68 + +#define mmMME1_CTRL_SHADOW_3_DESC_AXI_USER_DATA 0xE0D6C + +#define mmMME1_CTRL_SHADOW_3_DESC_PERF_EVT_S 0xE0D70 + +#define mmMME1_CTRL_SHADOW_3_DESC_PERF_EVT_L_LOCAL 0xE0D74 + +#define mmMME1_CTRL_SHADOW_3_DESC_PERF_EVT_L_REMOTE 0xE0D78 + +#define mmMME1_CTRL_SHADOW_3_DESC_PERF_EVT_O_LOCAL 0xE0D7C + +#define mmMME1_CTRL_SHADOW_3_DESC_PERF_EVT_O_REMOTE 0xE0D80 + +#define mmMME1_CTRL_SHADOW_3_DESC_PADDING_VALUE_S 0xE0D84 + +#define mmMME1_CTRL_SHADOW_3_DESC_PADDING_VALUE_L 0xE0D88 + +#define mmMME1_CTRL_SHADOW_3_DESC_META_DATA_AGU_S 0xE0D8C + +#define mmMME1_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_LOCAL 0xE0D90 + +#define mmMME1_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_REMOTE 0xE0D94 + +#define mmMME1_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_LOCAL 0xE0D98 + +#define mmMME1_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_REMOTE 0xE0D9C + +#define mmMME1_CTRL_SHADOW_3_DESC_PCU_RL_SATURATION 0xE0DA0 + +#define mmMME1_CTRL_SHADOW_3_DESC_DUMMY 0xE0DA4 + +#endif /* ASIC_REG_MME1_CTRL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/mme2_ctrl_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme2_ctrl_regs.h new file mode 100644 index 000000000000..a1f2eb8b91bd --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme2_ctrl_regs.h @@ -0,0 +1,1456 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME2_CTRL_REGS_H_ +#define ASIC_REG_MME2_CTRL_REGS_H_ + +/* + ***************************************** + * MME2_CTRL (Prototype: MME) + ***************************************** + */ + +#define mmMME2_CTRL_ARCH_STATUS 0x160000 + +#define mmMME2_CTRL_ARCH_BASE_ADDR_HIGH_S 0x160008 + +#define mmMME2_CTRL_ARCH_BASE_ADDR_HIGH_L 0x16000C + +#define mmMME2_CTRL_ARCH_BASE_ADDR_HIGH_O 0x160010 + +#define mmMME2_CTRL_ARCH_BASE_ADDR_LOW_S 0x160014 + +#define mmMME2_CTRL_ARCH_BASE_ADDR_LOW_L 0x160018 + +#define mmMME2_CTRL_ARCH_BASE_ADDR_LOW_O 0x16001C + +#define mmMME2_CTRL_ARCH_HEADER_LOW 0x160020 + +#define mmMME2_CTRL_ARCH_HEADER_HIGH 0x160024 + +#define mmMME2_CTRL_ARCH_CONV_KERNEL_SIZE_MINUS_1 0x160028 + +#define mmMME2_CTRL_ARCH_CONV_ASSOCIATED_DIMS_LOW 0x16002C + +#define mmMME2_CTRL_ARCH_CONV_ASSOCIATED_DIMS_HIGH 0x160030 + +#define mmMME2_CTRL_ARCH_NUM_ITERATIONS_MINUS_1 0x160034 + +#define mmMME2_CTRL_ARCH_OUTER_LOOP 0x160038 + +#define mmMME2_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_0 0x16003C + +#define mmMME2_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_1 0x160040 + +#define mmMME2_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_2 0x160044 + +#define mmMME2_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_3 0x160048 + +#define mmMME2_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_4 0x16004C + +#define mmMME2_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_0 0x160050 + +#define mmMME2_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_1 0x160054 + +#define mmMME2_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_2 0x160058 + +#define mmMME2_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_3 0x16005C + +#define mmMME2_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_4 0x160060 + +#define mmMME2_CTRL_ARCH_TENSOR_S_ROI_SIZE_0 0x160064 + +#define mmMME2_CTRL_ARCH_TENSOR_S_ROI_SIZE_1 0x160068 + +#define mmMME2_CTRL_ARCH_TENSOR_S_ROI_SIZE_2 0x16006C + +#define mmMME2_CTRL_ARCH_TENSOR_S_ROI_SIZE_3 0x160070 + +#define mmMME2_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_0 0x160074 + +#define mmMME2_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_1 0x160078 + +#define mmMME2_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_2 0x16007C + +#define mmMME2_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_3 0x160080 + +#define mmMME2_CTRL_ARCH_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x160084 + +#define mmMME2_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_0 0x160088 + +#define mmMME2_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_1 0x16008C + +#define mmMME2_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_2 0x160090 + +#define mmMME2_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_3 0x160094 + +#define mmMME2_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_4 0x160098 + +#define mmMME2_CTRL_ARCH_AGU_S_START_OFFSET_0 0x16009C + +#define mmMME2_CTRL_ARCH_AGU_S_START_OFFSET_1 0x1600A0 + +#define mmMME2_CTRL_ARCH_AGU_S_START_OFFSET_2 0x1600A4 + +#define mmMME2_CTRL_ARCH_AGU_S_START_OFFSET_3 0x1600A8 + +#define mmMME2_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_0 0x1600AC + +#define mmMME2_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_1 0x1600B0 + +#define mmMME2_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_2 0x1600B4 + +#define mmMME2_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_3 0x1600B8 + +#define mmMME2_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_4 0x1600BC + +#define mmMME2_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_0 0x1600C0 + +#define mmMME2_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_1 0x1600C4 + +#define mmMME2_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_2 0x1600C8 + +#define mmMME2_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_3 0x1600CC + +#define mmMME2_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_4 0x1600D0 + +#define mmMME2_CTRL_ARCH_TENSOR_L_ROI_SIZE_0 0x1600D4 + +#define mmMME2_CTRL_ARCH_TENSOR_L_ROI_SIZE_1 0x1600D8 + +#define mmMME2_CTRL_ARCH_TENSOR_L_ROI_SIZE_2 0x1600DC + +#define mmMME2_CTRL_ARCH_TENSOR_L_ROI_SIZE_3 0x1600E0 + +#define mmMME2_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_0 0x1600E4 + +#define mmMME2_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_1 0x1600E8 + +#define mmMME2_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_2 0x1600EC + +#define mmMME2_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_3 0x1600F0 + +#define mmMME2_CTRL_ARCH_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1600F4 + +#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1600F8 + +#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1600FC + +#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x160100 + +#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x160104 + +#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x160108 + +#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_0 0x16010C + +#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_1 0x160110 + +#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_2 0x160114 + +#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_3 0x160118 + +#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x16011C + +#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x160120 + +#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x160124 + +#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x160128 + +#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x16012C + +#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_0 0x160130 + +#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_1 0x160134 + +#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_2 0x160138 + +#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_3 0x16013C + +#define mmMME2_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_0 0x160140 + +#define mmMME2_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_1 0x160144 + +#define mmMME2_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_2 0x160148 + +#define mmMME2_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_3 0x16014C + +#define mmMME2_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_4 0x160150 + +#define mmMME2_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_0 0x160154 + +#define mmMME2_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_1 0x160158 + +#define mmMME2_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_2 0x16015C + +#define mmMME2_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_3 0x160160 + +#define mmMME2_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_4 0x160164 + +#define mmMME2_CTRL_ARCH_TENSOR_O_ROI_SIZE_0 0x160168 + +#define mmMME2_CTRL_ARCH_TENSOR_O_ROI_SIZE_1 0x16016C + +#define mmMME2_CTRL_ARCH_TENSOR_O_ROI_SIZE_2 0x160170 + +#define mmMME2_CTRL_ARCH_TENSOR_O_ROI_SIZE_3 0x160174 + +#define mmMME2_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_0 0x160178 + +#define mmMME2_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_1 0x16017C + +#define mmMME2_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_2 0x160180 + +#define mmMME2_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_3 0x160184 + +#define mmMME2_CTRL_ARCH_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x160188 + +#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x16018C + +#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x160190 + +#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x160194 + +#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x160198 + +#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x16019C + +#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_0 0x1601A0 + +#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_1 0x1601A4 + +#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_2 0x1601A8 + +#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_3 0x1601AC + +#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x1601B0 + +#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x1601B4 + +#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x1601B8 + +#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x1601BC + +#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x1601C0 + +#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_0 0x1601C4 + +#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_1 0x1601C8 + +#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_2 0x1601CC + +#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_3 0x1601D0 + +#define mmMME2_CTRL_ARCH_DESC_SB_REPEAT 0x1601D4 + +#define mmMME2_CTRL_ARCH_DESC_RATE_LIMITER 0x1601D8 + +#define mmMME2_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x1601DC + +#define mmMME2_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x1601E0 + +#define mmMME2_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_HIGH 0x1601E4 + +#define mmMME2_CTRL_ARCH_DESC_SYNC_OBJECT_DATA 0x1601E8 + +#define mmMME2_CTRL_ARCH_DESC_AXI_USER_DATA 0x1601EC + +#define mmMME2_CTRL_ARCH_DESC_PERF_EVT_S 0x1601F0 + +#define mmMME2_CTRL_ARCH_DESC_PERF_EVT_L_LOCAL 0x1601F4 + +#define mmMME2_CTRL_ARCH_DESC_PERF_EVT_L_REMOTE 0x1601F8 + +#define mmMME2_CTRL_ARCH_DESC_PERF_EVT_O_LOCAL 0x1601FC + +#define mmMME2_CTRL_ARCH_DESC_PERF_EVT_O_REMOTE 0x160200 + +#define mmMME2_CTRL_ARCH_DESC_PADDING_VALUE_S 0x160204 + +#define mmMME2_CTRL_ARCH_DESC_PADDING_VALUE_L 0x160208 + +#define mmMME2_CTRL_ARCH_DESC_META_DATA_AGU_S 0x16020C + +#define mmMME2_CTRL_ARCH_DESC_META_DATA_AGU_L_LOCAL 0x160210 + +#define mmMME2_CTRL_ARCH_DESC_META_DATA_AGU_L_REMOTE 0x160214 + +#define mmMME2_CTRL_ARCH_DESC_META_DATA_AGU_O_LOCAL 0x160218 + +#define mmMME2_CTRL_ARCH_DESC_META_DATA_AGU_O_REMOTE 0x16021C + +#define mmMME2_CTRL_ARCH_DESC_PCU_RL_SATURATION 0x160220 + +#define mmMME2_CTRL_ARCH_DESC_DUMMY 0x160224 + +#define mmMME2_CTRL_CMD 0x160280 + +#define mmMME2_CTRL_STATUS1 0x160284 + +#define mmMME2_CTRL_RESET 0x160288 + +#define mmMME2_CTRL_QM_STALL 0x16028C + +#define mmMME2_CTRL_SYNC_OBJECT_FIFO_TH 0x160290 + +#define mmMME2_CTRL_EUS_ROLLUP_CNT_ADD 0x160294 + +#define mmMME2_CTRL_INTR_CAUSE 0x160298 + +#define mmMME2_CTRL_INTR_MASK 0x16029C + +#define mmMME2_CTRL_LOG_SHADOW 0x1602A0 + +#define mmMME2_CTRL_PCU_RL_DESC0 0x1602A4 + +#define mmMME2_CTRL_PCU_RL_TOKEN_UPDATE 0x1602A8 + +#define mmMME2_CTRL_PCU_RL_TH 0x1602AC + +#define mmMME2_CTRL_PCU_RL_MIN 0x1602B0 + +#define mmMME2_CTRL_PCU_RL_CTRL_EN 0x1602B4 + +#define mmMME2_CTRL_PCU_RL_HISTORY_LOG_SIZE 0x1602B8 + +#define mmMME2_CTRL_PCU_DUMMY_A_BF16 0x1602BC + +#define mmMME2_CTRL_PCU_DUMMY_B_BF16 0x1602C0 + +#define mmMME2_CTRL_PCU_DUMMY_A_FP32_ODD 0x1602C4 + +#define mmMME2_CTRL_PCU_DUMMY_A_FP32_EVEN 0x1602C8 + +#define mmMME2_CTRL_PCU_DUMMY_B_FP32_ODD 0x1602CC + +#define mmMME2_CTRL_PCU_DUMMY_B_FP32_EVEN 0x1602D0 + +#define mmMME2_CTRL_PROT 0x1602D4 + +#define mmMME2_CTRL_EU_POWER_SAVE_DISABLE 0x1602D8 + +#define mmMME2_CTRL_CS_DBG_BLOCK_ID 0x1602DC + +#define mmMME2_CTRL_CS_DBG_STATUS_DROP_CNT 0x1602E0 + +#define mmMME2_CTRL_TE_CLOSE_CGATE 0x1602E4 + +#define mmMME2_CTRL_AGU_SM_INFLIGHT_CNTR 0x1602E8 + +#define mmMME2_CTRL_AGU_SM_TOTAL_CNTR 0x1602EC + +#define mmMME2_CTRL_EZSYNC_OUT_CREDIT 0x1602F0 + +#define mmMME2_CTRL_PCU_RL_SAT_SEC 0x1602F4 + +#define mmMME2_CTRL_AGU_SYNC_MSG_AXI_USER 0x1602F8 + +#define mmMME2_CTRL_QM_SLV_LBW_CLK_EN 0x1602FC + +#define mmMME2_CTRL_SHADOW_0_STATUS 0x160400 + +#define mmMME2_CTRL_SHADOW_0_BASE_ADDR_HIGH_S 0x160408 + +#define mmMME2_CTRL_SHADOW_0_BASE_ADDR_HIGH_L 0x16040C + +#define mmMME2_CTRL_SHADOW_0_BASE_ADDR_HIGH_O 0x160410 + +#define mmMME2_CTRL_SHADOW_0_BASE_ADDR_LOW_S 0x160414 + +#define mmMME2_CTRL_SHADOW_0_BASE_ADDR_LOW_L 0x160418 + +#define mmMME2_CTRL_SHADOW_0_BASE_ADDR_LOW_O 0x16041C + +#define mmMME2_CTRL_SHADOW_0_HEADER_LOW 0x160420 + +#define mmMME2_CTRL_SHADOW_0_HEADER_HIGH 0x160424 + +#define mmMME2_CTRL_SHADOW_0_CONV_KERNEL_SIZE_MINUS_1 0x160428 + +#define mmMME2_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_LOW 0x16042C + +#define mmMME2_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_HIGH 0x160430 + +#define mmMME2_CTRL_SHADOW_0_NUM_ITERATIONS_MINUS_1 0x160434 + +#define mmMME2_CTRL_SHADOW_0_OUTER_LOOP 0x160438 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_0 0x16043C + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_1 0x160440 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_2 0x160444 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_3 0x160448 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_4 0x16044C + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_0 0x160450 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_1 0x160454 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_2 0x160458 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_3 0x16045C + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_4 0x160460 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_0 0x160464 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_1 0x160468 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_2 0x16046C + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_3 0x160470 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_0 0x160474 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_1 0x160478 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_2 0x16047C + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_3 0x160480 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x160484 + +#define mmMME2_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_0 0x160488 + +#define mmMME2_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_1 0x16048C + +#define mmMME2_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_2 0x160490 + +#define mmMME2_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_3 0x160494 + +#define mmMME2_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_4 0x160498 + +#define mmMME2_CTRL_SHADOW_0_AGU_S_START_OFFSET_0 0x16049C + +#define mmMME2_CTRL_SHADOW_0_AGU_S_START_OFFSET_1 0x1604A0 + +#define mmMME2_CTRL_SHADOW_0_AGU_S_START_OFFSET_2 0x1604A4 + +#define mmMME2_CTRL_SHADOW_0_AGU_S_START_OFFSET_3 0x1604A8 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_0 0x1604AC + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_1 0x1604B0 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_2 0x1604B4 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_3 0x1604B8 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_4 0x1604BC + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_0 0x1604C0 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_1 0x1604C4 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_2 0x1604C8 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_3 0x1604CC + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_4 0x1604D0 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_0 0x1604D4 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_1 0x1604D8 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_2 0x1604DC + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_3 0x1604E0 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_0 0x1604E4 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_1 0x1604E8 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_2 0x1604EC + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_3 0x1604F0 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1604F4 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1604F8 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1604FC + +#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x160500 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x160504 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x160508 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_0 0x16050C + +#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_1 0x160510 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_2 0x160514 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_3 0x160518 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x16051C + +#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x160520 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x160524 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x160528 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x16052C + +#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_0 0x160530 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_1 0x160534 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_2 0x160538 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_3 0x16053C + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_0 0x160540 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_1 0x160544 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_2 0x160548 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_3 0x16054C + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_4 0x160550 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_0 0x160554 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_1 0x160558 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_2 0x16055C + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_3 0x160560 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_4 0x160564 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_0 0x160568 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_1 0x16056C + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_2 0x160570 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_3 0x160574 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_0 0x160578 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_1 0x16057C + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_2 0x160580 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_3 0x160584 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x160588 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x16058C + +#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x160590 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x160594 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x160598 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x16059C + +#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_0 0x1605A0 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_1 0x1605A4 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_2 0x1605A8 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_3 0x1605AC + +#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x1605B0 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x1605B4 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x1605B8 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x1605BC + +#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x1605C0 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_0 0x1605C4 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_1 0x1605C8 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_2 0x1605CC + +#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_3 0x1605D0 + +#define mmMME2_CTRL_SHADOW_0_DESC_SB_REPEAT 0x1605D4 + +#define mmMME2_CTRL_SHADOW_0_DESC_RATE_LIMITER 0x1605D8 + +#define mmMME2_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x1605DC + +#define mmMME2_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x1605E0 + +#define mmMME2_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_HIGH 0x1605E4 + +#define mmMME2_CTRL_SHADOW_0_DESC_SYNC_OBJECT_DATA 0x1605E8 + +#define mmMME2_CTRL_SHADOW_0_DESC_AXI_USER_DATA 0x1605EC + +#define mmMME2_CTRL_SHADOW_0_DESC_PERF_EVT_S 0x1605F0 + +#define mmMME2_CTRL_SHADOW_0_DESC_PERF_EVT_L_LOCAL 0x1605F4 + +#define mmMME2_CTRL_SHADOW_0_DESC_PERF_EVT_L_REMOTE 0x1605F8 + +#define mmMME2_CTRL_SHADOW_0_DESC_PERF_EVT_O_LOCAL 0x1605FC + +#define mmMME2_CTRL_SHADOW_0_DESC_PERF_EVT_O_REMOTE 0x160600 + +#define mmMME2_CTRL_SHADOW_0_DESC_PADDING_VALUE_S 0x160604 + +#define mmMME2_CTRL_SHADOW_0_DESC_PADDING_VALUE_L 0x160608 + +#define mmMME2_CTRL_SHADOW_0_DESC_META_DATA_AGU_S 0x16060C + +#define mmMME2_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_LOCAL 0x160610 + +#define mmMME2_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_REMOTE 0x160614 + +#define mmMME2_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_LOCAL 0x160618 + +#define mmMME2_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_REMOTE 0x16061C + +#define mmMME2_CTRL_SHADOW_0_DESC_PCU_RL_SATURATION 0x160620 + +#define mmMME2_CTRL_SHADOW_0_DESC_DUMMY 0x160624 + +#define mmMME2_CTRL_SHADOW_1_STATUS 0x160680 + +#define mmMME2_CTRL_SHADOW_1_BASE_ADDR_HIGH_S 0x160688 + +#define mmMME2_CTRL_SHADOW_1_BASE_ADDR_HIGH_L 0x16068C + +#define mmMME2_CTRL_SHADOW_1_BASE_ADDR_HIGH_O 0x160690 + +#define mmMME2_CTRL_SHADOW_1_BASE_ADDR_LOW_S 0x160694 + +#define mmMME2_CTRL_SHADOW_1_BASE_ADDR_LOW_L 0x160698 + +#define mmMME2_CTRL_SHADOW_1_BASE_ADDR_LOW_O 0x16069C + +#define mmMME2_CTRL_SHADOW_1_HEADER_LOW 0x1606A0 + +#define mmMME2_CTRL_SHADOW_1_HEADER_HIGH 0x1606A4 + +#define mmMME2_CTRL_SHADOW_1_CONV_KERNEL_SIZE_MINUS_1 0x1606A8 + +#define mmMME2_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_LOW 0x1606AC + +#define mmMME2_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_HIGH 0x1606B0 + +#define mmMME2_CTRL_SHADOW_1_NUM_ITERATIONS_MINUS_1 0x1606B4 + +#define mmMME2_CTRL_SHADOW_1_OUTER_LOOP 0x1606B8 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_0 0x1606BC + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_1 0x1606C0 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_2 0x1606C4 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_3 0x1606C8 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_4 0x1606CC + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_0 0x1606D0 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_1 0x1606D4 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_2 0x1606D8 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_3 0x1606DC + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_4 0x1606E0 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_0 0x1606E4 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_1 0x1606E8 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_2 0x1606EC + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_3 0x1606F0 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_0 0x1606F4 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_1 0x1606F8 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_2 0x1606FC + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_3 0x160700 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x160704 + +#define mmMME2_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_0 0x160708 + +#define mmMME2_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_1 0x16070C + +#define mmMME2_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_2 0x160710 + +#define mmMME2_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_3 0x160714 + +#define mmMME2_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_4 0x160718 + +#define mmMME2_CTRL_SHADOW_1_AGU_S_START_OFFSET_0 0x16071C + +#define mmMME2_CTRL_SHADOW_1_AGU_S_START_OFFSET_1 0x160720 + +#define mmMME2_CTRL_SHADOW_1_AGU_S_START_OFFSET_2 0x160724 + +#define mmMME2_CTRL_SHADOW_1_AGU_S_START_OFFSET_3 0x160728 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_0 0x16072C + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_1 0x160730 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_2 0x160734 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_3 0x160738 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_4 0x16073C + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_0 0x160740 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_1 0x160744 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_2 0x160748 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_3 0x16074C + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_4 0x160750 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_0 0x160754 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_1 0x160758 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_2 0x16075C + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_3 0x160760 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_0 0x160764 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_1 0x160768 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_2 0x16076C + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_3 0x160770 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x160774 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x160778 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x16077C + +#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x160780 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x160784 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x160788 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_0 0x16078C + +#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_1 0x160790 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_2 0x160794 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_3 0x160798 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x16079C + +#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x1607A0 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x1607A4 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x1607A8 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x1607AC + +#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_0 0x1607B0 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_1 0x1607B4 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_2 0x1607B8 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_3 0x1607BC + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_0 0x1607C0 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_1 0x1607C4 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_2 0x1607C8 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_3 0x1607CC + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_4 0x1607D0 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_0 0x1607D4 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_1 0x1607D8 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_2 0x1607DC + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_3 0x1607E0 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_4 0x1607E4 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_0 0x1607E8 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_1 0x1607EC + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_2 0x1607F0 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_3 0x1607F4 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_0 0x1607F8 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_1 0x1607FC + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_2 0x160800 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_3 0x160804 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x160808 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x16080C + +#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x160810 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x160814 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x160818 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x16081C + +#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_0 0x160820 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_1 0x160824 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_2 0x160828 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_3 0x16082C + +#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x160830 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x160834 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x160838 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x16083C + +#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x160840 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_0 0x160844 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_1 0x160848 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_2 0x16084C + +#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_3 0x160850 + +#define mmMME2_CTRL_SHADOW_1_DESC_SB_REPEAT 0x160854 + +#define mmMME2_CTRL_SHADOW_1_DESC_RATE_LIMITER 0x160858 + +#define mmMME2_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x16085C + +#define mmMME2_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x160860 + +#define mmMME2_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_HIGH 0x160864 + +#define mmMME2_CTRL_SHADOW_1_DESC_SYNC_OBJECT_DATA 0x160868 + +#define mmMME2_CTRL_SHADOW_1_DESC_AXI_USER_DATA 0x16086C + +#define mmMME2_CTRL_SHADOW_1_DESC_PERF_EVT_S 0x160870 + +#define mmMME2_CTRL_SHADOW_1_DESC_PERF_EVT_L_LOCAL 0x160874 + +#define mmMME2_CTRL_SHADOW_1_DESC_PERF_EVT_L_REMOTE 0x160878 + +#define mmMME2_CTRL_SHADOW_1_DESC_PERF_EVT_O_LOCAL 0x16087C + +#define mmMME2_CTRL_SHADOW_1_DESC_PERF_EVT_O_REMOTE 0x160880 + +#define mmMME2_CTRL_SHADOW_1_DESC_PADDING_VALUE_S 0x160884 + +#define mmMME2_CTRL_SHADOW_1_DESC_PADDING_VALUE_L 0x160888 + +#define mmMME2_CTRL_SHADOW_1_DESC_META_DATA_AGU_S 0x16088C + +#define mmMME2_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_LOCAL 0x160890 + +#define mmMME2_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_REMOTE 0x160894 + +#define mmMME2_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_LOCAL 0x160898 + +#define mmMME2_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_REMOTE 0x16089C + +#define mmMME2_CTRL_SHADOW_1_DESC_PCU_RL_SATURATION 0x1608A0 + +#define mmMME2_CTRL_SHADOW_1_DESC_DUMMY 0x1608A4 + +#define mmMME2_CTRL_SHADOW_2_STATUS 0x160900 + +#define mmMME2_CTRL_SHADOW_2_BASE_ADDR_HIGH_S 0x160908 + +#define mmMME2_CTRL_SHADOW_2_BASE_ADDR_HIGH_L 0x16090C + +#define mmMME2_CTRL_SHADOW_2_BASE_ADDR_HIGH_O 0x160910 + +#define mmMME2_CTRL_SHADOW_2_BASE_ADDR_LOW_S 0x160914 + +#define mmMME2_CTRL_SHADOW_2_BASE_ADDR_LOW_L 0x160918 + +#define mmMME2_CTRL_SHADOW_2_BASE_ADDR_LOW_O 0x16091C + +#define mmMME2_CTRL_SHADOW_2_HEADER_LOW 0x160920 + +#define mmMME2_CTRL_SHADOW_2_HEADER_HIGH 0x160924 + +#define mmMME2_CTRL_SHADOW_2_CONV_KERNEL_SIZE_MINUS_1 0x160928 + +#define mmMME2_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_LOW 0x16092C + +#define mmMME2_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_HIGH 0x160930 + +#define mmMME2_CTRL_SHADOW_2_NUM_ITERATIONS_MINUS_1 0x160934 + +#define mmMME2_CTRL_SHADOW_2_OUTER_LOOP 0x160938 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_0 0x16093C + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_1 0x160940 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_2 0x160944 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_3 0x160948 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_4 0x16094C + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_0 0x160950 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_1 0x160954 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_2 0x160958 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_3 0x16095C + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_4 0x160960 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_0 0x160964 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_1 0x160968 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_2 0x16096C + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_3 0x160970 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_0 0x160974 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_1 0x160978 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_2 0x16097C + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_3 0x160980 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x160984 + +#define mmMME2_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_0 0x160988 + +#define mmMME2_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_1 0x16098C + +#define mmMME2_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_2 0x160990 + +#define mmMME2_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_3 0x160994 + +#define mmMME2_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_4 0x160998 + +#define mmMME2_CTRL_SHADOW_2_AGU_S_START_OFFSET_0 0x16099C + +#define mmMME2_CTRL_SHADOW_2_AGU_S_START_OFFSET_1 0x1609A0 + +#define mmMME2_CTRL_SHADOW_2_AGU_S_START_OFFSET_2 0x1609A4 + +#define mmMME2_CTRL_SHADOW_2_AGU_S_START_OFFSET_3 0x1609A8 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_0 0x1609AC + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_1 0x1609B0 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_2 0x1609B4 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_3 0x1609B8 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_4 0x1609BC + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_0 0x1609C0 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_1 0x1609C4 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_2 0x1609C8 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_3 0x1609CC + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_4 0x1609D0 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_0 0x1609D4 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_1 0x1609D8 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_2 0x1609DC + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_3 0x1609E0 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_0 0x1609E4 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_1 0x1609E8 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_2 0x1609EC + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_3 0x1609F0 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1609F4 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1609F8 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1609FC + +#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x160A00 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x160A04 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x160A08 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_0 0x160A0C + +#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_1 0x160A10 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_2 0x160A14 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_3 0x160A18 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x160A1C + +#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x160A20 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x160A24 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x160A28 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x160A2C + +#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_0 0x160A30 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_1 0x160A34 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_2 0x160A38 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_3 0x160A3C + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_0 0x160A40 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_1 0x160A44 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_2 0x160A48 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_3 0x160A4C + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_4 0x160A50 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_0 0x160A54 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_1 0x160A58 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_2 0x160A5C + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_3 0x160A60 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_4 0x160A64 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_0 0x160A68 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_1 0x160A6C + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_2 0x160A70 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_3 0x160A74 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_0 0x160A78 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_1 0x160A7C + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_2 0x160A80 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_3 0x160A84 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x160A88 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x160A8C + +#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x160A90 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x160A94 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x160A98 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x160A9C + +#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_0 0x160AA0 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_1 0x160AA4 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_2 0x160AA8 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_3 0x160AAC + +#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x160AB0 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x160AB4 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x160AB8 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x160ABC + +#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x160AC0 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_0 0x160AC4 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_1 0x160AC8 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_2 0x160ACC + +#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_3 0x160AD0 + +#define mmMME2_CTRL_SHADOW_2_DESC_SB_REPEAT 0x160AD4 + +#define mmMME2_CTRL_SHADOW_2_DESC_RATE_LIMITER 0x160AD8 + +#define mmMME2_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x160ADC + +#define mmMME2_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x160AE0 + +#define mmMME2_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_HIGH 0x160AE4 + +#define mmMME2_CTRL_SHADOW_2_DESC_SYNC_OBJECT_DATA 0x160AE8 + +#define mmMME2_CTRL_SHADOW_2_DESC_AXI_USER_DATA 0x160AEC + +#define mmMME2_CTRL_SHADOW_2_DESC_PERF_EVT_S 0x160AF0 + +#define mmMME2_CTRL_SHADOW_2_DESC_PERF_EVT_L_LOCAL 0x160AF4 + +#define mmMME2_CTRL_SHADOW_2_DESC_PERF_EVT_L_REMOTE 0x160AF8 + +#define mmMME2_CTRL_SHADOW_2_DESC_PERF_EVT_O_LOCAL 0x160AFC + +#define mmMME2_CTRL_SHADOW_2_DESC_PERF_EVT_O_REMOTE 0x160B00 + +#define mmMME2_CTRL_SHADOW_2_DESC_PADDING_VALUE_S 0x160B04 + +#define mmMME2_CTRL_SHADOW_2_DESC_PADDING_VALUE_L 0x160B08 + +#define mmMME2_CTRL_SHADOW_2_DESC_META_DATA_AGU_S 0x160B0C + +#define mmMME2_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_LOCAL 0x160B10 + +#define mmMME2_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_REMOTE 0x160B14 + +#define mmMME2_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_LOCAL 0x160B18 + +#define mmMME2_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_REMOTE 0x160B1C + +#define mmMME2_CTRL_SHADOW_2_DESC_PCU_RL_SATURATION 0x160B20 + +#define mmMME2_CTRL_SHADOW_2_DESC_DUMMY 0x160B24 + +#define mmMME2_CTRL_SHADOW_3_STATUS 0x160B80 + +#define mmMME2_CTRL_SHADOW_3_BASE_ADDR_HIGH_S 0x160B88 + +#define mmMME2_CTRL_SHADOW_3_BASE_ADDR_HIGH_L 0x160B8C + +#define mmMME2_CTRL_SHADOW_3_BASE_ADDR_HIGH_O 0x160B90 + +#define mmMME2_CTRL_SHADOW_3_BASE_ADDR_LOW_S 0x160B94 + +#define mmMME2_CTRL_SHADOW_3_BASE_ADDR_LOW_L 0x160B98 + +#define mmMME2_CTRL_SHADOW_3_BASE_ADDR_LOW_O 0x160B9C + +#define mmMME2_CTRL_SHADOW_3_HEADER_LOW 0x160BA0 + +#define mmMME2_CTRL_SHADOW_3_HEADER_HIGH 0x160BA4 + +#define mmMME2_CTRL_SHADOW_3_CONV_KERNEL_SIZE_MINUS_1 0x160BA8 + +#define mmMME2_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_LOW 0x160BAC + +#define mmMME2_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_HIGH 0x160BB0 + +#define mmMME2_CTRL_SHADOW_3_NUM_ITERATIONS_MINUS_1 0x160BB4 + +#define mmMME2_CTRL_SHADOW_3_OUTER_LOOP 0x160BB8 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_0 0x160BBC + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_1 0x160BC0 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_2 0x160BC4 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_3 0x160BC8 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_4 0x160BCC + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_0 0x160BD0 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_1 0x160BD4 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_2 0x160BD8 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_3 0x160BDC + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_4 0x160BE0 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_0 0x160BE4 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_1 0x160BE8 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_2 0x160BEC + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_3 0x160BF0 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_0 0x160BF4 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_1 0x160BF8 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_2 0x160BFC + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_3 0x160C00 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x160C04 + +#define mmMME2_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_0 0x160C08 + +#define mmMME2_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_1 0x160C0C + +#define mmMME2_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_2 0x160C10 + +#define mmMME2_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_3 0x160C14 + +#define mmMME2_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_4 0x160C18 + +#define mmMME2_CTRL_SHADOW_3_AGU_S_START_OFFSET_0 0x160C1C + +#define mmMME2_CTRL_SHADOW_3_AGU_S_START_OFFSET_1 0x160C20 + +#define mmMME2_CTRL_SHADOW_3_AGU_S_START_OFFSET_2 0x160C24 + +#define mmMME2_CTRL_SHADOW_3_AGU_S_START_OFFSET_3 0x160C28 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_0 0x160C2C + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_1 0x160C30 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_2 0x160C34 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_3 0x160C38 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_4 0x160C3C + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_0 0x160C40 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_1 0x160C44 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_2 0x160C48 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_3 0x160C4C + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_4 0x160C50 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_0 0x160C54 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_1 0x160C58 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_2 0x160C5C + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_3 0x160C60 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_0 0x160C64 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_1 0x160C68 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_2 0x160C6C + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_3 0x160C70 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x160C74 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x160C78 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x160C7C + +#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x160C80 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x160C84 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x160C88 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_0 0x160C8C + +#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_1 0x160C90 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_2 0x160C94 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_3 0x160C98 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x160C9C + +#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x160CA0 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x160CA4 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x160CA8 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x160CAC + +#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_0 0x160CB0 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_1 0x160CB4 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_2 0x160CB8 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_3 0x160CBC + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_0 0x160CC0 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_1 0x160CC4 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_2 0x160CC8 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_3 0x160CCC + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_4 0x160CD0 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_0 0x160CD4 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_1 0x160CD8 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_2 0x160CDC + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_3 0x160CE0 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_4 0x160CE4 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_0 0x160CE8 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_1 0x160CEC + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_2 0x160CF0 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_3 0x160CF4 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_0 0x160CF8 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_1 0x160CFC + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_2 0x160D00 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_3 0x160D04 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x160D08 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x160D0C + +#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x160D10 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x160D14 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x160D18 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x160D1C + +#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_0 0x160D20 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_1 0x160D24 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_2 0x160D28 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_3 0x160D2C + +#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x160D30 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x160D34 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x160D38 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x160D3C + +#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x160D40 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_0 0x160D44 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_1 0x160D48 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_2 0x160D4C + +#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_3 0x160D50 + +#define mmMME2_CTRL_SHADOW_3_DESC_SB_REPEAT 0x160D54 + +#define mmMME2_CTRL_SHADOW_3_DESC_RATE_LIMITER 0x160D58 + +#define mmMME2_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x160D5C + +#define mmMME2_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x160D60 + +#define mmMME2_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_HIGH 0x160D64 + +#define mmMME2_CTRL_SHADOW_3_DESC_SYNC_OBJECT_DATA 0x160D68 + +#define mmMME2_CTRL_SHADOW_3_DESC_AXI_USER_DATA 0x160D6C + +#define mmMME2_CTRL_SHADOW_3_DESC_PERF_EVT_S 0x160D70 + +#define mmMME2_CTRL_SHADOW_3_DESC_PERF_EVT_L_LOCAL 0x160D74 + +#define mmMME2_CTRL_SHADOW_3_DESC_PERF_EVT_L_REMOTE 0x160D78 + +#define mmMME2_CTRL_SHADOW_3_DESC_PERF_EVT_O_LOCAL 0x160D7C + +#define mmMME2_CTRL_SHADOW_3_DESC_PERF_EVT_O_REMOTE 0x160D80 + +#define mmMME2_CTRL_SHADOW_3_DESC_PADDING_VALUE_S 0x160D84 + +#define mmMME2_CTRL_SHADOW_3_DESC_PADDING_VALUE_L 0x160D88 + +#define mmMME2_CTRL_SHADOW_3_DESC_META_DATA_AGU_S 0x160D8C + +#define mmMME2_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_LOCAL 0x160D90 + +#define mmMME2_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_REMOTE 0x160D94 + +#define mmMME2_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_LOCAL 0x160D98 + +#define mmMME2_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_REMOTE 0x160D9C + +#define mmMME2_CTRL_SHADOW_3_DESC_PCU_RL_SATURATION 0x160DA0 + +#define mmMME2_CTRL_SHADOW_3_DESC_DUMMY 0x160DA4 + +#endif /* ASIC_REG_MME2_CTRL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/mme2_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme2_qm_regs.h new file mode 100644 index 000000000000..c1ea6a422010 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme2_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME2_QM_REGS_H_ +#define ASIC_REG_MME2_QM_REGS_H_ + +/* + ***************************************** + * MME2_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmMME2_QM_GLBL_CFG0 0x168000 + +#define mmMME2_QM_GLBL_CFG1 0x168004 + +#define mmMME2_QM_GLBL_PROT 0x168008 + +#define mmMME2_QM_GLBL_ERR_CFG 0x16800C + +#define mmMME2_QM_GLBL_SECURE_PROPS_0 0x168010 + +#define mmMME2_QM_GLBL_SECURE_PROPS_1 0x168014 + +#define mmMME2_QM_GLBL_SECURE_PROPS_2 0x168018 + +#define mmMME2_QM_GLBL_SECURE_PROPS_3 0x16801C + +#define mmMME2_QM_GLBL_SECURE_PROPS_4 0x168020 + +#define mmMME2_QM_GLBL_NON_SECURE_PROPS_0 0x168024 + +#define mmMME2_QM_GLBL_NON_SECURE_PROPS_1 0x168028 + +#define mmMME2_QM_GLBL_NON_SECURE_PROPS_2 0x16802C + +#define mmMME2_QM_GLBL_NON_SECURE_PROPS_3 0x168030 + +#define mmMME2_QM_GLBL_NON_SECURE_PROPS_4 0x168034 + +#define mmMME2_QM_GLBL_STS0 0x168038 + +#define mmMME2_QM_GLBL_STS1_0 0x168040 + +#define mmMME2_QM_GLBL_STS1_1 0x168044 + +#define mmMME2_QM_GLBL_STS1_2 0x168048 + +#define mmMME2_QM_GLBL_STS1_3 0x16804C + +#define mmMME2_QM_GLBL_STS1_4 0x168050 + +#define mmMME2_QM_GLBL_MSG_EN_0 0x168054 + +#define mmMME2_QM_GLBL_MSG_EN_1 0x168058 + +#define mmMME2_QM_GLBL_MSG_EN_2 0x16805C + +#define mmMME2_QM_GLBL_MSG_EN_3 0x168060 + +#define mmMME2_QM_GLBL_MSG_EN_4 0x168068 + +#define mmMME2_QM_PQ_BASE_LO_0 0x168070 + +#define mmMME2_QM_PQ_BASE_LO_1 0x168074 + +#define mmMME2_QM_PQ_BASE_LO_2 0x168078 + +#define mmMME2_QM_PQ_BASE_LO_3 0x16807C + +#define mmMME2_QM_PQ_BASE_HI_0 0x168080 + +#define mmMME2_QM_PQ_BASE_HI_1 0x168084 + +#define mmMME2_QM_PQ_BASE_HI_2 0x168088 + +#define mmMME2_QM_PQ_BASE_HI_3 0x16808C + +#define mmMME2_QM_PQ_SIZE_0 0x168090 + +#define mmMME2_QM_PQ_SIZE_1 0x168094 + +#define mmMME2_QM_PQ_SIZE_2 0x168098 + +#define mmMME2_QM_PQ_SIZE_3 0x16809C + +#define mmMME2_QM_PQ_PI_0 0x1680A0 + +#define mmMME2_QM_PQ_PI_1 0x1680A4 + +#define mmMME2_QM_PQ_PI_2 0x1680A8 + +#define mmMME2_QM_PQ_PI_3 0x1680AC + +#define mmMME2_QM_PQ_CI_0 0x1680B0 + +#define mmMME2_QM_PQ_CI_1 0x1680B4 + +#define mmMME2_QM_PQ_CI_2 0x1680B8 + +#define mmMME2_QM_PQ_CI_3 0x1680BC + +#define mmMME2_QM_PQ_CFG0_0 0x1680C0 + +#define mmMME2_QM_PQ_CFG0_1 0x1680C4 + +#define mmMME2_QM_PQ_CFG0_2 0x1680C8 + +#define mmMME2_QM_PQ_CFG0_3 0x1680CC + +#define mmMME2_QM_PQ_CFG1_0 0x1680D0 + +#define mmMME2_QM_PQ_CFG1_1 0x1680D4 + +#define mmMME2_QM_PQ_CFG1_2 0x1680D8 + +#define mmMME2_QM_PQ_CFG1_3 0x1680DC + +#define mmMME2_QM_PQ_ARUSER_31_11_0 0x1680E0 + +#define mmMME2_QM_PQ_ARUSER_31_11_1 0x1680E4 + +#define mmMME2_QM_PQ_ARUSER_31_11_2 0x1680E8 + +#define mmMME2_QM_PQ_ARUSER_31_11_3 0x1680EC + +#define mmMME2_QM_PQ_STS0_0 0x1680F0 + +#define mmMME2_QM_PQ_STS0_1 0x1680F4 + +#define mmMME2_QM_PQ_STS0_2 0x1680F8 + +#define mmMME2_QM_PQ_STS0_3 0x1680FC + +#define mmMME2_QM_PQ_STS1_0 0x168100 + +#define mmMME2_QM_PQ_STS1_1 0x168104 + +#define mmMME2_QM_PQ_STS1_2 0x168108 + +#define mmMME2_QM_PQ_STS1_3 0x16810C + +#define mmMME2_QM_CQ_CFG0_0 0x168110 + +#define mmMME2_QM_CQ_CFG0_1 0x168114 + +#define mmMME2_QM_CQ_CFG0_2 0x168118 + +#define mmMME2_QM_CQ_CFG0_3 0x16811C + +#define mmMME2_QM_CQ_CFG0_4 0x168120 + +#define mmMME2_QM_CQ_CFG1_0 0x168124 + +#define mmMME2_QM_CQ_CFG1_1 0x168128 + +#define mmMME2_QM_CQ_CFG1_2 0x16812C + +#define mmMME2_QM_CQ_CFG1_3 0x168130 + +#define mmMME2_QM_CQ_CFG1_4 0x168134 + +#define mmMME2_QM_CQ_ARUSER_31_11_0 0x168138 + +#define mmMME2_QM_CQ_ARUSER_31_11_1 0x16813C + +#define mmMME2_QM_CQ_ARUSER_31_11_2 0x168140 + +#define mmMME2_QM_CQ_ARUSER_31_11_3 0x168144 + +#define mmMME2_QM_CQ_ARUSER_31_11_4 0x168148 + +#define mmMME2_QM_CQ_STS0_0 0x16814C + +#define mmMME2_QM_CQ_STS0_1 0x168150 + +#define mmMME2_QM_CQ_STS0_2 0x168154 + +#define mmMME2_QM_CQ_STS0_3 0x168158 + +#define mmMME2_QM_CQ_STS0_4 0x16815C + +#define mmMME2_QM_CQ_STS1_0 0x168160 + +#define mmMME2_QM_CQ_STS1_1 0x168164 + +#define mmMME2_QM_CQ_STS1_2 0x168168 + +#define mmMME2_QM_CQ_STS1_3 0x16816C + +#define mmMME2_QM_CQ_STS1_4 0x168170 + +#define mmMME2_QM_CQ_PTR_LO_0 0x168174 + +#define mmMME2_QM_CQ_PTR_HI_0 0x168178 + +#define mmMME2_QM_CQ_TSIZE_0 0x16817C + +#define mmMME2_QM_CQ_CTL_0 0x168180 + +#define mmMME2_QM_CQ_PTR_LO_1 0x168184 + +#define mmMME2_QM_CQ_PTR_HI_1 0x168188 + +#define mmMME2_QM_CQ_TSIZE_1 0x16818C + +#define mmMME2_QM_CQ_CTL_1 0x168190 + +#define mmMME2_QM_CQ_PTR_LO_2 0x168194 + +#define mmMME2_QM_CQ_PTR_HI_2 0x168198 + +#define mmMME2_QM_CQ_TSIZE_2 0x16819C + +#define mmMME2_QM_CQ_CTL_2 0x1681A0 + +#define mmMME2_QM_CQ_PTR_LO_3 0x1681A4 + +#define mmMME2_QM_CQ_PTR_HI_3 0x1681A8 + +#define mmMME2_QM_CQ_TSIZE_3 0x1681AC + +#define mmMME2_QM_CQ_CTL_3 0x1681B0 + +#define mmMME2_QM_CQ_PTR_LO_4 0x1681B4 + +#define mmMME2_QM_CQ_PTR_HI_4 0x1681B8 + +#define mmMME2_QM_CQ_TSIZE_4 0x1681BC + +#define mmMME2_QM_CQ_CTL_4 0x1681C0 + +#define mmMME2_QM_CQ_PTR_LO_STS_0 0x1681C4 + +#define mmMME2_QM_CQ_PTR_LO_STS_1 0x1681C8 + +#define mmMME2_QM_CQ_PTR_LO_STS_2 0x1681CC + +#define mmMME2_QM_CQ_PTR_LO_STS_3 0x1681D0 + +#define mmMME2_QM_CQ_PTR_LO_STS_4 0x1681D4 + +#define mmMME2_QM_CQ_PTR_HI_STS_0 0x1681D8 + +#define mmMME2_QM_CQ_PTR_HI_STS_1 0x1681DC + +#define mmMME2_QM_CQ_PTR_HI_STS_2 0x1681E0 + +#define mmMME2_QM_CQ_PTR_HI_STS_3 0x1681E4 + +#define mmMME2_QM_CQ_PTR_HI_STS_4 0x1681E8 + +#define mmMME2_QM_CQ_TSIZE_STS_0 0x1681EC + +#define mmMME2_QM_CQ_TSIZE_STS_1 0x1681F0 + +#define mmMME2_QM_CQ_TSIZE_STS_2 0x1681F4 + +#define mmMME2_QM_CQ_TSIZE_STS_3 0x1681F8 + +#define mmMME2_QM_CQ_TSIZE_STS_4 0x1681FC + +#define mmMME2_QM_CQ_CTL_STS_0 0x168200 + +#define mmMME2_QM_CQ_CTL_STS_1 0x168204 + +#define mmMME2_QM_CQ_CTL_STS_2 0x168208 + +#define mmMME2_QM_CQ_CTL_STS_3 0x16820C + +#define mmMME2_QM_CQ_CTL_STS_4 0x168210 + +#define mmMME2_QM_CQ_IFIFO_CNT_0 0x168214 + +#define mmMME2_QM_CQ_IFIFO_CNT_1 0x168218 + +#define mmMME2_QM_CQ_IFIFO_CNT_2 0x16821C + +#define mmMME2_QM_CQ_IFIFO_CNT_3 0x168220 + +#define mmMME2_QM_CQ_IFIFO_CNT_4 0x168224 + +#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_0 0x168228 + +#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_1 0x16822C + +#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_2 0x168230 + +#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_3 0x168234 + +#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_4 0x168238 + +#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_0 0x16823C + +#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_1 0x168240 + +#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_2 0x168244 + +#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_3 0x168248 + +#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_4 0x16824C + +#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_0 0x168250 + +#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_1 0x168254 + +#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_2 0x168258 + +#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_3 0x16825C + +#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_4 0x168260 + +#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_0 0x168264 + +#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_1 0x168268 + +#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_2 0x16826C + +#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_3 0x168270 + +#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_4 0x168274 + +#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_0 0x168278 + +#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_1 0x16827C + +#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_2 0x168280 + +#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_3 0x168284 + +#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_4 0x168288 + +#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_0 0x16828C + +#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_1 0x168290 + +#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_2 0x168294 + +#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_3 0x168298 + +#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_4 0x16829C + +#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_0 0x1682A0 + +#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_1 0x1682A4 + +#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_2 0x1682A8 + +#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_3 0x1682AC + +#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_4 0x1682B0 + +#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_0 0x1682B4 + +#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_1 0x1682B8 + +#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_2 0x1682BC + +#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_3 0x1682C0 + +#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_4 0x1682C4 + +#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_0 0x1682C8 + +#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_1 0x1682CC + +#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_2 0x1682D0 + +#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_3 0x1682D4 + +#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_4 0x1682D8 + +#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x1682E0 + +#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x1682E4 + +#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x1682E8 + +#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x1682EC + +#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x1682F0 + +#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x1682F4 + +#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x1682F8 + +#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x1682FC + +#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x168300 + +#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x168304 + +#define mmMME2_QM_CP_FENCE0_RDATA_0 0x168308 + +#define mmMME2_QM_CP_FENCE0_RDATA_1 0x16830C + +#define mmMME2_QM_CP_FENCE0_RDATA_2 0x168310 + +#define mmMME2_QM_CP_FENCE0_RDATA_3 0x168314 + +#define mmMME2_QM_CP_FENCE0_RDATA_4 0x168318 + +#define mmMME2_QM_CP_FENCE1_RDATA_0 0x16831C + +#define mmMME2_QM_CP_FENCE1_RDATA_1 0x168320 + +#define mmMME2_QM_CP_FENCE1_RDATA_2 0x168324 + +#define mmMME2_QM_CP_FENCE1_RDATA_3 0x168328 + +#define mmMME2_QM_CP_FENCE1_RDATA_4 0x16832C + +#define mmMME2_QM_CP_FENCE2_RDATA_0 0x168330 + +#define mmMME2_QM_CP_FENCE2_RDATA_1 0x168334 + +#define mmMME2_QM_CP_FENCE2_RDATA_2 0x168338 + +#define mmMME2_QM_CP_FENCE2_RDATA_3 0x16833C + +#define mmMME2_QM_CP_FENCE2_RDATA_4 0x168340 + +#define mmMME2_QM_CP_FENCE3_RDATA_0 0x168344 + +#define mmMME2_QM_CP_FENCE3_RDATA_1 0x168348 + +#define mmMME2_QM_CP_FENCE3_RDATA_2 0x16834C + +#define mmMME2_QM_CP_FENCE3_RDATA_3 0x168350 + +#define mmMME2_QM_CP_FENCE3_RDATA_4 0x168354 + +#define mmMME2_QM_CP_FENCE0_CNT_0 0x168358 + +#define mmMME2_QM_CP_FENCE0_CNT_1 0x16835C + +#define mmMME2_QM_CP_FENCE0_CNT_2 0x168360 + +#define mmMME2_QM_CP_FENCE0_CNT_3 0x168364 + +#define mmMME2_QM_CP_FENCE0_CNT_4 0x168368 + +#define mmMME2_QM_CP_FENCE1_CNT_0 0x16836C + +#define mmMME2_QM_CP_FENCE1_CNT_1 0x168370 + +#define mmMME2_QM_CP_FENCE1_CNT_2 0x168374 + +#define mmMME2_QM_CP_FENCE1_CNT_3 0x168378 + +#define mmMME2_QM_CP_FENCE1_CNT_4 0x16837C + +#define mmMME2_QM_CP_FENCE2_CNT_0 0x168380 + +#define mmMME2_QM_CP_FENCE2_CNT_1 0x168384 + +#define mmMME2_QM_CP_FENCE2_CNT_2 0x168388 + +#define mmMME2_QM_CP_FENCE2_CNT_3 0x16838C + +#define mmMME2_QM_CP_FENCE2_CNT_4 0x168390 + +#define mmMME2_QM_CP_FENCE3_CNT_0 0x168394 + +#define mmMME2_QM_CP_FENCE3_CNT_1 0x168398 + +#define mmMME2_QM_CP_FENCE3_CNT_2 0x16839C + +#define mmMME2_QM_CP_FENCE3_CNT_3 0x1683A0 + +#define mmMME2_QM_CP_FENCE3_CNT_4 0x1683A4 + +#define mmMME2_QM_CP_STS_0 0x1683A8 + +#define mmMME2_QM_CP_STS_1 0x1683AC + +#define mmMME2_QM_CP_STS_2 0x1683B0 + +#define mmMME2_QM_CP_STS_3 0x1683B4 + +#define mmMME2_QM_CP_STS_4 0x1683B8 + +#define mmMME2_QM_CP_CURRENT_INST_LO_0 0x1683BC + +#define mmMME2_QM_CP_CURRENT_INST_LO_1 0x1683C0 + +#define mmMME2_QM_CP_CURRENT_INST_LO_2 0x1683C4 + +#define mmMME2_QM_CP_CURRENT_INST_LO_3 0x1683C8 + +#define mmMME2_QM_CP_CURRENT_INST_LO_4 0x1683CC + +#define mmMME2_QM_CP_CURRENT_INST_HI_0 0x1683D0 + +#define mmMME2_QM_CP_CURRENT_INST_HI_1 0x1683D4 + +#define mmMME2_QM_CP_CURRENT_INST_HI_2 0x1683D8 + +#define mmMME2_QM_CP_CURRENT_INST_HI_3 0x1683DC + +#define mmMME2_QM_CP_CURRENT_INST_HI_4 0x1683E0 + +#define mmMME2_QM_CP_BARRIER_CFG_0 0x1683F4 + +#define mmMME2_QM_CP_BARRIER_CFG_1 0x1683F8 + +#define mmMME2_QM_CP_BARRIER_CFG_2 0x1683FC + +#define mmMME2_QM_CP_BARRIER_CFG_3 0x168400 + +#define mmMME2_QM_CP_BARRIER_CFG_4 0x168404 + +#define mmMME2_QM_CP_DBG_0_0 0x168408 + +#define mmMME2_QM_CP_DBG_0_1 0x16840C + +#define mmMME2_QM_CP_DBG_0_2 0x168410 + +#define mmMME2_QM_CP_DBG_0_3 0x168414 + +#define mmMME2_QM_CP_DBG_0_4 0x168418 + +#define mmMME2_QM_CP_ARUSER_31_11_0 0x16841C + +#define mmMME2_QM_CP_ARUSER_31_11_1 0x168420 + +#define mmMME2_QM_CP_ARUSER_31_11_2 0x168424 + +#define mmMME2_QM_CP_ARUSER_31_11_3 0x168428 + +#define mmMME2_QM_CP_ARUSER_31_11_4 0x16842C + +#define mmMME2_QM_CP_AWUSER_31_11_0 0x168430 + +#define mmMME2_QM_CP_AWUSER_31_11_1 0x168434 + +#define mmMME2_QM_CP_AWUSER_31_11_2 0x168438 + +#define mmMME2_QM_CP_AWUSER_31_11_3 0x16843C + +#define mmMME2_QM_CP_AWUSER_31_11_4 0x168440 + +#define mmMME2_QM_ARB_CFG_0 0x168A00 + +#define mmMME2_QM_ARB_CHOISE_Q_PUSH 0x168A04 + +#define mmMME2_QM_ARB_WRR_WEIGHT_0 0x168A08 + +#define mmMME2_QM_ARB_WRR_WEIGHT_1 0x168A0C + +#define mmMME2_QM_ARB_WRR_WEIGHT_2 0x168A10 + +#define mmMME2_QM_ARB_WRR_WEIGHT_3 0x168A14 + +#define mmMME2_QM_ARB_CFG_1 0x168A18 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_0 0x168A20 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_1 0x168A24 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_2 0x168A28 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_3 0x168A2C + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_4 0x168A30 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_5 0x168A34 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_6 0x168A38 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_7 0x168A3C + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_8 0x168A40 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_9 0x168A44 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_10 0x168A48 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_11 0x168A4C + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_12 0x168A50 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_13 0x168A54 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_14 0x168A58 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_15 0x168A5C + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_16 0x168A60 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_17 0x168A64 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_18 0x168A68 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_19 0x168A6C + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_20 0x168A70 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_21 0x168A74 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_22 0x168A78 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_23 0x168A7C + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_24 0x168A80 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_25 0x168A84 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_26 0x168A88 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_27 0x168A8C + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_28 0x168A90 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_29 0x168A94 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_30 0x168A98 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_31 0x168A9C + +#define mmMME2_QM_ARB_MST_CRED_INC 0x168AA0 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x168AA4 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x168AA8 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x168AAC + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x168AB0 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x168AB4 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x168AB8 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x168ABC + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x168AC0 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x168AC4 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x168AC8 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x168ACC + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x168AD0 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x168AD4 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x168AD8 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x168ADC + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x168AE0 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x168AE4 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x168AE8 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x168AEC + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x168AF0 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x168AF4 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x168AF8 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x168AFC + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x168B00 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x168B04 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x168B08 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x168B0C + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x168B10 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x168B14 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x168B18 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x168B1C + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x168B20 + +#define mmMME2_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x168B28 + +#define mmMME2_QM_ARB_MST_SLAVE_EN 0x168B2C + +#define mmMME2_QM_ARB_MST_QUIET_PER 0x168B34 + +#define mmMME2_QM_ARB_SLV_CHOISE_WDT 0x168B38 + +#define mmMME2_QM_ARB_SLV_ID 0x168B3C + +#define mmMME2_QM_ARB_MSG_MAX_INFLIGHT 0x168B44 + +#define mmMME2_QM_ARB_MSG_AWUSER_31_11 0x168B48 + +#define mmMME2_QM_ARB_MSG_AWUSER_SEC_PROP 0x168B4C + +#define mmMME2_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x168B50 + +#define mmMME2_QM_ARB_BASE_LO 0x168B54 + +#define mmMME2_QM_ARB_BASE_HI 0x168B58 + +#define mmMME2_QM_ARB_STATE_STS 0x168B80 + +#define mmMME2_QM_ARB_CHOISE_FULLNESS_STS 0x168B84 + +#define mmMME2_QM_ARB_MSG_STS 0x168B88 + +#define mmMME2_QM_ARB_SLV_CHOISE_Q_HEAD 0x168B8C + +#define mmMME2_QM_ARB_ERR_CAUSE 0x168B9C + +#define mmMME2_QM_ARB_ERR_MSG_EN 0x168BA0 + +#define mmMME2_QM_ARB_ERR_STS_DRP 0x168BA8 + +#define mmMME2_QM_ARB_MST_CRED_STS_0 0x168BB0 + +#define mmMME2_QM_ARB_MST_CRED_STS_1 0x168BB4 + +#define mmMME2_QM_ARB_MST_CRED_STS_2 0x168BB8 + +#define mmMME2_QM_ARB_MST_CRED_STS_3 0x168BBC + +#define mmMME2_QM_ARB_MST_CRED_STS_4 0x168BC0 + +#define mmMME2_QM_ARB_MST_CRED_STS_5 0x168BC4 + +#define mmMME2_QM_ARB_MST_CRED_STS_6 0x168BC8 + +#define mmMME2_QM_ARB_MST_CRED_STS_7 0x168BCC + +#define mmMME2_QM_ARB_MST_CRED_STS_8 0x168BD0 + +#define mmMME2_QM_ARB_MST_CRED_STS_9 0x168BD4 + +#define mmMME2_QM_ARB_MST_CRED_STS_10 0x168BD8 + +#define mmMME2_QM_ARB_MST_CRED_STS_11 0x168BDC + +#define mmMME2_QM_ARB_MST_CRED_STS_12 0x168BE0 + +#define mmMME2_QM_ARB_MST_CRED_STS_13 0x168BE4 + +#define mmMME2_QM_ARB_MST_CRED_STS_14 0x168BE8 + +#define mmMME2_QM_ARB_MST_CRED_STS_15 0x168BEC + +#define mmMME2_QM_ARB_MST_CRED_STS_16 0x168BF0 + +#define mmMME2_QM_ARB_MST_CRED_STS_17 0x168BF4 + +#define mmMME2_QM_ARB_MST_CRED_STS_18 0x168BF8 + +#define mmMME2_QM_ARB_MST_CRED_STS_19 0x168BFC + +#define mmMME2_QM_ARB_MST_CRED_STS_20 0x168C00 + +#define mmMME2_QM_ARB_MST_CRED_STS_21 0x168C04 + +#define mmMME2_QM_ARB_MST_CRED_STS_22 0x168C08 + +#define mmMME2_QM_ARB_MST_CRED_STS_23 0x168C0C + +#define mmMME2_QM_ARB_MST_CRED_STS_24 0x168C10 + +#define mmMME2_QM_ARB_MST_CRED_STS_25 0x168C14 + +#define mmMME2_QM_ARB_MST_CRED_STS_26 0x168C18 + +#define mmMME2_QM_ARB_MST_CRED_STS_27 0x168C1C + +#define mmMME2_QM_ARB_MST_CRED_STS_28 0x168C20 + +#define mmMME2_QM_ARB_MST_CRED_STS_29 0x168C24 + +#define mmMME2_QM_ARB_MST_CRED_STS_30 0x168C28 + +#define mmMME2_QM_ARB_MST_CRED_STS_31 0x168C2C + +#define mmMME2_QM_CGM_CFG 0x168C70 + +#define mmMME2_QM_CGM_STS 0x168C74 + +#define mmMME2_QM_CGM_CFG1 0x168C78 + +#define mmMME2_QM_LOCAL_RANGE_BASE 0x168C80 + +#define mmMME2_QM_LOCAL_RANGE_SIZE 0x168C84 + +#define mmMME2_QM_CSMR_STRICT_PRIO_CFG 0x168C90 + +#define mmMME2_QM_HBW_RD_RATE_LIM_CFG_1 0x168C94 + +#define mmMME2_QM_LBW_WR_RATE_LIM_CFG_0 0x168C98 + +#define mmMME2_QM_LBW_WR_RATE_LIM_CFG_1 0x168C9C + +#define mmMME2_QM_HBW_RD_RATE_LIM_CFG_0 0x168CA0 + +#define mmMME2_QM_GLBL_AXCACHE 0x168CA4 + +#define mmMME2_QM_IND_GW_APB_CFG 0x168CB0 + +#define mmMME2_QM_IND_GW_APB_WDATA 0x168CB4 + +#define mmMME2_QM_IND_GW_APB_RDATA 0x168CB8 + +#define mmMME2_QM_IND_GW_APB_STATUS 0x168CBC + +#define mmMME2_QM_GLBL_ERR_ADDR_LO 0x168CD0 + +#define mmMME2_QM_GLBL_ERR_ADDR_HI 0x168CD4 + +#define mmMME2_QM_GLBL_ERR_WDATA 0x168CD8 + +#define mmMME2_QM_GLBL_MEM_INIT_BUSY 0x168D00 + +#endif /* ASIC_REG_MME2_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/mme3_ctrl_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme3_ctrl_regs.h new file mode 100644 index 000000000000..36f6edc72e3d --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme3_ctrl_regs.h @@ -0,0 +1,1456 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME3_CTRL_REGS_H_ +#define ASIC_REG_MME3_CTRL_REGS_H_ + +/* + ***************************************** + * MME3_CTRL (Prototype: MME) + ***************************************** + */ + +#define mmMME3_CTRL_ARCH_STATUS 0x1E0000 + +#define mmMME3_CTRL_ARCH_BASE_ADDR_HIGH_S 0x1E0008 + +#define mmMME3_CTRL_ARCH_BASE_ADDR_HIGH_L 0x1E000C + +#define mmMME3_CTRL_ARCH_BASE_ADDR_HIGH_O 0x1E0010 + +#define mmMME3_CTRL_ARCH_BASE_ADDR_LOW_S 0x1E0014 + +#define mmMME3_CTRL_ARCH_BASE_ADDR_LOW_L 0x1E0018 + +#define mmMME3_CTRL_ARCH_BASE_ADDR_LOW_O 0x1E001C + +#define mmMME3_CTRL_ARCH_HEADER_LOW 0x1E0020 + +#define mmMME3_CTRL_ARCH_HEADER_HIGH 0x1E0024 + +#define mmMME3_CTRL_ARCH_CONV_KERNEL_SIZE_MINUS_1 0x1E0028 + +#define mmMME3_CTRL_ARCH_CONV_ASSOCIATED_DIMS_LOW 0x1E002C + +#define mmMME3_CTRL_ARCH_CONV_ASSOCIATED_DIMS_HIGH 0x1E0030 + +#define mmMME3_CTRL_ARCH_NUM_ITERATIONS_MINUS_1 0x1E0034 + +#define mmMME3_CTRL_ARCH_OUTER_LOOP 0x1E0038 + +#define mmMME3_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_0 0x1E003C + +#define mmMME3_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_1 0x1E0040 + +#define mmMME3_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_2 0x1E0044 + +#define mmMME3_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_3 0x1E0048 + +#define mmMME3_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_4 0x1E004C + +#define mmMME3_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_0 0x1E0050 + +#define mmMME3_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_1 0x1E0054 + +#define mmMME3_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_2 0x1E0058 + +#define mmMME3_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_3 0x1E005C + +#define mmMME3_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_4 0x1E0060 + +#define mmMME3_CTRL_ARCH_TENSOR_S_ROI_SIZE_0 0x1E0064 + +#define mmMME3_CTRL_ARCH_TENSOR_S_ROI_SIZE_1 0x1E0068 + +#define mmMME3_CTRL_ARCH_TENSOR_S_ROI_SIZE_2 0x1E006C + +#define mmMME3_CTRL_ARCH_TENSOR_S_ROI_SIZE_3 0x1E0070 + +#define mmMME3_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_0 0x1E0074 + +#define mmMME3_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_1 0x1E0078 + +#define mmMME3_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_2 0x1E007C + +#define mmMME3_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_3 0x1E0080 + +#define mmMME3_CTRL_ARCH_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x1E0084 + +#define mmMME3_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_0 0x1E0088 + +#define mmMME3_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_1 0x1E008C + +#define mmMME3_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_2 0x1E0090 + +#define mmMME3_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_3 0x1E0094 + +#define mmMME3_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_4 0x1E0098 + +#define mmMME3_CTRL_ARCH_AGU_S_START_OFFSET_0 0x1E009C + +#define mmMME3_CTRL_ARCH_AGU_S_START_OFFSET_1 0x1E00A0 + +#define mmMME3_CTRL_ARCH_AGU_S_START_OFFSET_2 0x1E00A4 + +#define mmMME3_CTRL_ARCH_AGU_S_START_OFFSET_3 0x1E00A8 + +#define mmMME3_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_0 0x1E00AC + +#define mmMME3_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_1 0x1E00B0 + +#define mmMME3_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_2 0x1E00B4 + +#define mmMME3_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_3 0x1E00B8 + +#define mmMME3_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_4 0x1E00BC + +#define mmMME3_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_0 0x1E00C0 + +#define mmMME3_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_1 0x1E00C4 + +#define mmMME3_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_2 0x1E00C8 + +#define mmMME3_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_3 0x1E00CC + +#define mmMME3_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_4 0x1E00D0 + +#define mmMME3_CTRL_ARCH_TENSOR_L_ROI_SIZE_0 0x1E00D4 + +#define mmMME3_CTRL_ARCH_TENSOR_L_ROI_SIZE_1 0x1E00D8 + +#define mmMME3_CTRL_ARCH_TENSOR_L_ROI_SIZE_2 0x1E00DC + +#define mmMME3_CTRL_ARCH_TENSOR_L_ROI_SIZE_3 0x1E00E0 + +#define mmMME3_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_0 0x1E00E4 + +#define mmMME3_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_1 0x1E00E8 + +#define mmMME3_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_2 0x1E00EC + +#define mmMME3_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_3 0x1E00F0 + +#define mmMME3_CTRL_ARCH_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1E00F4 + +#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1E00F8 + +#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1E00FC + +#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x1E0100 + +#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x1E0104 + +#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x1E0108 + +#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_0 0x1E010C + +#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_1 0x1E0110 + +#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_2 0x1E0114 + +#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_3 0x1E0118 + +#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x1E011C + +#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x1E0120 + +#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x1E0124 + +#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x1E0128 + +#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x1E012C + +#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_0 0x1E0130 + +#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_1 0x1E0134 + +#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_2 0x1E0138 + +#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_3 0x1E013C + +#define mmMME3_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_0 0x1E0140 + +#define mmMME3_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_1 0x1E0144 + +#define mmMME3_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_2 0x1E0148 + +#define mmMME3_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_3 0x1E014C + +#define mmMME3_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_4 0x1E0150 + +#define mmMME3_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_0 0x1E0154 + +#define mmMME3_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_1 0x1E0158 + +#define mmMME3_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_2 0x1E015C + +#define mmMME3_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_3 0x1E0160 + +#define mmMME3_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_4 0x1E0164 + +#define mmMME3_CTRL_ARCH_TENSOR_O_ROI_SIZE_0 0x1E0168 + +#define mmMME3_CTRL_ARCH_TENSOR_O_ROI_SIZE_1 0x1E016C + +#define mmMME3_CTRL_ARCH_TENSOR_O_ROI_SIZE_2 0x1E0170 + +#define mmMME3_CTRL_ARCH_TENSOR_O_ROI_SIZE_3 0x1E0174 + +#define mmMME3_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_0 0x1E0178 + +#define mmMME3_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_1 0x1E017C + +#define mmMME3_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_2 0x1E0180 + +#define mmMME3_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_3 0x1E0184 + +#define mmMME3_CTRL_ARCH_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x1E0188 + +#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x1E018C + +#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x1E0190 + +#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x1E0194 + +#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x1E0198 + +#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x1E019C + +#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_0 0x1E01A0 + +#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_1 0x1E01A4 + +#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_2 0x1E01A8 + +#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_3 0x1E01AC + +#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x1E01B0 + +#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x1E01B4 + +#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x1E01B8 + +#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x1E01BC + +#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x1E01C0 + +#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_0 0x1E01C4 + +#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_1 0x1E01C8 + +#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_2 0x1E01CC + +#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_3 0x1E01D0 + +#define mmMME3_CTRL_ARCH_DESC_SB_REPEAT 0x1E01D4 + +#define mmMME3_CTRL_ARCH_DESC_RATE_LIMITER 0x1E01D8 + +#define mmMME3_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x1E01DC + +#define mmMME3_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x1E01E0 + +#define mmMME3_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_HIGH 0x1E01E4 + +#define mmMME3_CTRL_ARCH_DESC_SYNC_OBJECT_DATA 0x1E01E8 + +#define mmMME3_CTRL_ARCH_DESC_AXI_USER_DATA 0x1E01EC + +#define mmMME3_CTRL_ARCH_DESC_PERF_EVT_S 0x1E01F0 + +#define mmMME3_CTRL_ARCH_DESC_PERF_EVT_L_LOCAL 0x1E01F4 + +#define mmMME3_CTRL_ARCH_DESC_PERF_EVT_L_REMOTE 0x1E01F8 + +#define mmMME3_CTRL_ARCH_DESC_PERF_EVT_O_LOCAL 0x1E01FC + +#define mmMME3_CTRL_ARCH_DESC_PERF_EVT_O_REMOTE 0x1E0200 + +#define mmMME3_CTRL_ARCH_DESC_PADDING_VALUE_S 0x1E0204 + +#define mmMME3_CTRL_ARCH_DESC_PADDING_VALUE_L 0x1E0208 + +#define mmMME3_CTRL_ARCH_DESC_META_DATA_AGU_S 0x1E020C + +#define mmMME3_CTRL_ARCH_DESC_META_DATA_AGU_L_LOCAL 0x1E0210 + +#define mmMME3_CTRL_ARCH_DESC_META_DATA_AGU_L_REMOTE 0x1E0214 + +#define mmMME3_CTRL_ARCH_DESC_META_DATA_AGU_O_LOCAL 0x1E0218 + +#define mmMME3_CTRL_ARCH_DESC_META_DATA_AGU_O_REMOTE 0x1E021C + +#define mmMME3_CTRL_ARCH_DESC_PCU_RL_SATURATION 0x1E0220 + +#define mmMME3_CTRL_ARCH_DESC_DUMMY 0x1E0224 + +#define mmMME3_CTRL_CMD 0x1E0280 + +#define mmMME3_CTRL_STATUS1 0x1E0284 + +#define mmMME3_CTRL_RESET 0x1E0288 + +#define mmMME3_CTRL_QM_STALL 0x1E028C + +#define mmMME3_CTRL_SYNC_OBJECT_FIFO_TH 0x1E0290 + +#define mmMME3_CTRL_EUS_ROLLUP_CNT_ADD 0x1E0294 + +#define mmMME3_CTRL_INTR_CAUSE 0x1E0298 + +#define mmMME3_CTRL_INTR_MASK 0x1E029C + +#define mmMME3_CTRL_LOG_SHADOW 0x1E02A0 + +#define mmMME3_CTRL_PCU_RL_DESC0 0x1E02A4 + +#define mmMME3_CTRL_PCU_RL_TOKEN_UPDATE 0x1E02A8 + +#define mmMME3_CTRL_PCU_RL_TH 0x1E02AC + +#define mmMME3_CTRL_PCU_RL_MIN 0x1E02B0 + +#define mmMME3_CTRL_PCU_RL_CTRL_EN 0x1E02B4 + +#define mmMME3_CTRL_PCU_RL_HISTORY_LOG_SIZE 0x1E02B8 + +#define mmMME3_CTRL_PCU_DUMMY_A_BF16 0x1E02BC + +#define mmMME3_CTRL_PCU_DUMMY_B_BF16 0x1E02C0 + +#define mmMME3_CTRL_PCU_DUMMY_A_FP32_ODD 0x1E02C4 + +#define mmMME3_CTRL_PCU_DUMMY_A_FP32_EVEN 0x1E02C8 + +#define mmMME3_CTRL_PCU_DUMMY_B_FP32_ODD 0x1E02CC + +#define mmMME3_CTRL_PCU_DUMMY_B_FP32_EVEN 0x1E02D0 + +#define mmMME3_CTRL_PROT 0x1E02D4 + +#define mmMME3_CTRL_EU_POWER_SAVE_DISABLE 0x1E02D8 + +#define mmMME3_CTRL_CS_DBG_BLOCK_ID 0x1E02DC + +#define mmMME3_CTRL_CS_DBG_STATUS_DROP_CNT 0x1E02E0 + +#define mmMME3_CTRL_TE_CLOSE_CGATE 0x1E02E4 + +#define mmMME3_CTRL_AGU_SM_INFLIGHT_CNTR 0x1E02E8 + +#define mmMME3_CTRL_AGU_SM_TOTAL_CNTR 0x1E02EC + +#define mmMME3_CTRL_EZSYNC_OUT_CREDIT 0x1E02F0 + +#define mmMME3_CTRL_PCU_RL_SAT_SEC 0x1E02F4 + +#define mmMME3_CTRL_AGU_SYNC_MSG_AXI_USER 0x1E02F8 + +#define mmMME3_CTRL_QM_SLV_LBW_CLK_EN 0x1E02FC + +#define mmMME3_CTRL_SHADOW_0_STATUS 0x1E0400 + +#define mmMME3_CTRL_SHADOW_0_BASE_ADDR_HIGH_S 0x1E0408 + +#define mmMME3_CTRL_SHADOW_0_BASE_ADDR_HIGH_L 0x1E040C + +#define mmMME3_CTRL_SHADOW_0_BASE_ADDR_HIGH_O 0x1E0410 + +#define mmMME3_CTRL_SHADOW_0_BASE_ADDR_LOW_S 0x1E0414 + +#define mmMME3_CTRL_SHADOW_0_BASE_ADDR_LOW_L 0x1E0418 + +#define mmMME3_CTRL_SHADOW_0_BASE_ADDR_LOW_O 0x1E041C + +#define mmMME3_CTRL_SHADOW_0_HEADER_LOW 0x1E0420 + +#define mmMME3_CTRL_SHADOW_0_HEADER_HIGH 0x1E0424 + +#define mmMME3_CTRL_SHADOW_0_CONV_KERNEL_SIZE_MINUS_1 0x1E0428 + +#define mmMME3_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_LOW 0x1E042C + +#define mmMME3_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_HIGH 0x1E0430 + +#define mmMME3_CTRL_SHADOW_0_NUM_ITERATIONS_MINUS_1 0x1E0434 + +#define mmMME3_CTRL_SHADOW_0_OUTER_LOOP 0x1E0438 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_0 0x1E043C + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_1 0x1E0440 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_2 0x1E0444 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_3 0x1E0448 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_4 0x1E044C + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_0 0x1E0450 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_1 0x1E0454 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_2 0x1E0458 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_3 0x1E045C + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_4 0x1E0460 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_0 0x1E0464 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_1 0x1E0468 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_2 0x1E046C + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_3 0x1E0470 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_0 0x1E0474 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_1 0x1E0478 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_2 0x1E047C + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_3 0x1E0480 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x1E0484 + +#define mmMME3_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_0 0x1E0488 + +#define mmMME3_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_1 0x1E048C + +#define mmMME3_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_2 0x1E0490 + +#define mmMME3_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_3 0x1E0494 + +#define mmMME3_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_4 0x1E0498 + +#define mmMME3_CTRL_SHADOW_0_AGU_S_START_OFFSET_0 0x1E049C + +#define mmMME3_CTRL_SHADOW_0_AGU_S_START_OFFSET_1 0x1E04A0 + +#define mmMME3_CTRL_SHADOW_0_AGU_S_START_OFFSET_2 0x1E04A4 + +#define mmMME3_CTRL_SHADOW_0_AGU_S_START_OFFSET_3 0x1E04A8 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_0 0x1E04AC + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_1 0x1E04B0 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_2 0x1E04B4 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_3 0x1E04B8 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_4 0x1E04BC + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_0 0x1E04C0 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_1 0x1E04C4 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_2 0x1E04C8 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_3 0x1E04CC + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_4 0x1E04D0 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_0 0x1E04D4 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_1 0x1E04D8 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_2 0x1E04DC + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_3 0x1E04E0 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_0 0x1E04E4 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_1 0x1E04E8 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_2 0x1E04EC + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_3 0x1E04F0 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1E04F4 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1E04F8 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1E04FC + +#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x1E0500 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x1E0504 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x1E0508 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_0 0x1E050C + +#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_1 0x1E0510 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_2 0x1E0514 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_3 0x1E0518 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x1E051C + +#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x1E0520 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x1E0524 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x1E0528 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x1E052C + +#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_0 0x1E0530 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_1 0x1E0534 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_2 0x1E0538 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_3 0x1E053C + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_0 0x1E0540 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_1 0x1E0544 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_2 0x1E0548 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_3 0x1E054C + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_4 0x1E0550 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_0 0x1E0554 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_1 0x1E0558 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_2 0x1E055C + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_3 0x1E0560 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_4 0x1E0564 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_0 0x1E0568 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_1 0x1E056C + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_2 0x1E0570 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_3 0x1E0574 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_0 0x1E0578 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_1 0x1E057C + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_2 0x1E0580 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_3 0x1E0584 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x1E0588 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x1E058C + +#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x1E0590 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x1E0594 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x1E0598 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x1E059C + +#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_0 0x1E05A0 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_1 0x1E05A4 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_2 0x1E05A8 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_3 0x1E05AC + +#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x1E05B0 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x1E05B4 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x1E05B8 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x1E05BC + +#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x1E05C0 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_0 0x1E05C4 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_1 0x1E05C8 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_2 0x1E05CC + +#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_3 0x1E05D0 + +#define mmMME3_CTRL_SHADOW_0_DESC_SB_REPEAT 0x1E05D4 + +#define mmMME3_CTRL_SHADOW_0_DESC_RATE_LIMITER 0x1E05D8 + +#define mmMME3_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x1E05DC + +#define mmMME3_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x1E05E0 + +#define mmMME3_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_HIGH 0x1E05E4 + +#define mmMME3_CTRL_SHADOW_0_DESC_SYNC_OBJECT_DATA 0x1E05E8 + +#define mmMME3_CTRL_SHADOW_0_DESC_AXI_USER_DATA 0x1E05EC + +#define mmMME3_CTRL_SHADOW_0_DESC_PERF_EVT_S 0x1E05F0 + +#define mmMME3_CTRL_SHADOW_0_DESC_PERF_EVT_L_LOCAL 0x1E05F4 + +#define mmMME3_CTRL_SHADOW_0_DESC_PERF_EVT_L_REMOTE 0x1E05F8 + +#define mmMME3_CTRL_SHADOW_0_DESC_PERF_EVT_O_LOCAL 0x1E05FC + +#define mmMME3_CTRL_SHADOW_0_DESC_PERF_EVT_O_REMOTE 0x1E0600 + +#define mmMME3_CTRL_SHADOW_0_DESC_PADDING_VALUE_S 0x1E0604 + +#define mmMME3_CTRL_SHADOW_0_DESC_PADDING_VALUE_L 0x1E0608 + +#define mmMME3_CTRL_SHADOW_0_DESC_META_DATA_AGU_S 0x1E060C + +#define mmMME3_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_LOCAL 0x1E0610 + +#define mmMME3_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_REMOTE 0x1E0614 + +#define mmMME3_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_LOCAL 0x1E0618 + +#define mmMME3_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_REMOTE 0x1E061C + +#define mmMME3_CTRL_SHADOW_0_DESC_PCU_RL_SATURATION 0x1E0620 + +#define mmMME3_CTRL_SHADOW_0_DESC_DUMMY 0x1E0624 + +#define mmMME3_CTRL_SHADOW_1_STATUS 0x1E0680 + +#define mmMME3_CTRL_SHADOW_1_BASE_ADDR_HIGH_S 0x1E0688 + +#define mmMME3_CTRL_SHADOW_1_BASE_ADDR_HIGH_L 0x1E068C + +#define mmMME3_CTRL_SHADOW_1_BASE_ADDR_HIGH_O 0x1E0690 + +#define mmMME3_CTRL_SHADOW_1_BASE_ADDR_LOW_S 0x1E0694 + +#define mmMME3_CTRL_SHADOW_1_BASE_ADDR_LOW_L 0x1E0698 + +#define mmMME3_CTRL_SHADOW_1_BASE_ADDR_LOW_O 0x1E069C + +#define mmMME3_CTRL_SHADOW_1_HEADER_LOW 0x1E06A0 + +#define mmMME3_CTRL_SHADOW_1_HEADER_HIGH 0x1E06A4 + +#define mmMME3_CTRL_SHADOW_1_CONV_KERNEL_SIZE_MINUS_1 0x1E06A8 + +#define mmMME3_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_LOW 0x1E06AC + +#define mmMME3_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_HIGH 0x1E06B0 + +#define mmMME3_CTRL_SHADOW_1_NUM_ITERATIONS_MINUS_1 0x1E06B4 + +#define mmMME3_CTRL_SHADOW_1_OUTER_LOOP 0x1E06B8 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_0 0x1E06BC + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_1 0x1E06C0 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_2 0x1E06C4 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_3 0x1E06C8 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_4 0x1E06CC + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_0 0x1E06D0 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_1 0x1E06D4 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_2 0x1E06D8 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_3 0x1E06DC + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_4 0x1E06E0 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_0 0x1E06E4 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_1 0x1E06E8 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_2 0x1E06EC + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_3 0x1E06F0 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_0 0x1E06F4 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_1 0x1E06F8 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_2 0x1E06FC + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_3 0x1E0700 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x1E0704 + +#define mmMME3_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_0 0x1E0708 + +#define mmMME3_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_1 0x1E070C + +#define mmMME3_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_2 0x1E0710 + +#define mmMME3_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_3 0x1E0714 + +#define mmMME3_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_4 0x1E0718 + +#define mmMME3_CTRL_SHADOW_1_AGU_S_START_OFFSET_0 0x1E071C + +#define mmMME3_CTRL_SHADOW_1_AGU_S_START_OFFSET_1 0x1E0720 + +#define mmMME3_CTRL_SHADOW_1_AGU_S_START_OFFSET_2 0x1E0724 + +#define mmMME3_CTRL_SHADOW_1_AGU_S_START_OFFSET_3 0x1E0728 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_0 0x1E072C + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_1 0x1E0730 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_2 0x1E0734 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_3 0x1E0738 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_4 0x1E073C + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_0 0x1E0740 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_1 0x1E0744 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_2 0x1E0748 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_3 0x1E074C + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_4 0x1E0750 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_0 0x1E0754 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_1 0x1E0758 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_2 0x1E075C + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_3 0x1E0760 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_0 0x1E0764 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_1 0x1E0768 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_2 0x1E076C + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_3 0x1E0770 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1E0774 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1E0778 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1E077C + +#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x1E0780 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x1E0784 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x1E0788 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_0 0x1E078C + +#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_1 0x1E0790 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_2 0x1E0794 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_3 0x1E0798 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x1E079C + +#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x1E07A0 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x1E07A4 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x1E07A8 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x1E07AC + +#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_0 0x1E07B0 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_1 0x1E07B4 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_2 0x1E07B8 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_3 0x1E07BC + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_0 0x1E07C0 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_1 0x1E07C4 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_2 0x1E07C8 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_3 0x1E07CC + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_4 0x1E07D0 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_0 0x1E07D4 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_1 0x1E07D8 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_2 0x1E07DC + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_3 0x1E07E0 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_4 0x1E07E4 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_0 0x1E07E8 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_1 0x1E07EC + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_2 0x1E07F0 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_3 0x1E07F4 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_0 0x1E07F8 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_1 0x1E07FC + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_2 0x1E0800 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_3 0x1E0804 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x1E0808 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x1E080C + +#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x1E0810 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x1E0814 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x1E0818 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x1E081C + +#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_0 0x1E0820 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_1 0x1E0824 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_2 0x1E0828 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_3 0x1E082C + +#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x1E0830 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x1E0834 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x1E0838 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x1E083C + +#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x1E0840 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_0 0x1E0844 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_1 0x1E0848 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_2 0x1E084C + +#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_3 0x1E0850 + +#define mmMME3_CTRL_SHADOW_1_DESC_SB_REPEAT 0x1E0854 + +#define mmMME3_CTRL_SHADOW_1_DESC_RATE_LIMITER 0x1E0858 + +#define mmMME3_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x1E085C + +#define mmMME3_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x1E0860 + +#define mmMME3_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_HIGH 0x1E0864 + +#define mmMME3_CTRL_SHADOW_1_DESC_SYNC_OBJECT_DATA 0x1E0868 + +#define mmMME3_CTRL_SHADOW_1_DESC_AXI_USER_DATA 0x1E086C + +#define mmMME3_CTRL_SHADOW_1_DESC_PERF_EVT_S 0x1E0870 + +#define mmMME3_CTRL_SHADOW_1_DESC_PERF_EVT_L_LOCAL 0x1E0874 + +#define mmMME3_CTRL_SHADOW_1_DESC_PERF_EVT_L_REMOTE 0x1E0878 + +#define mmMME3_CTRL_SHADOW_1_DESC_PERF_EVT_O_LOCAL 0x1E087C + +#define mmMME3_CTRL_SHADOW_1_DESC_PERF_EVT_O_REMOTE 0x1E0880 + +#define mmMME3_CTRL_SHADOW_1_DESC_PADDING_VALUE_S 0x1E0884 + +#define mmMME3_CTRL_SHADOW_1_DESC_PADDING_VALUE_L 0x1E0888 + +#define mmMME3_CTRL_SHADOW_1_DESC_META_DATA_AGU_S 0x1E088C + +#define mmMME3_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_LOCAL 0x1E0890 + +#define mmMME3_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_REMOTE 0x1E0894 + +#define mmMME3_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_LOCAL 0x1E0898 + +#define mmMME3_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_REMOTE 0x1E089C + +#define mmMME3_CTRL_SHADOW_1_DESC_PCU_RL_SATURATION 0x1E08A0 + +#define mmMME3_CTRL_SHADOW_1_DESC_DUMMY 0x1E08A4 + +#define mmMME3_CTRL_SHADOW_2_STATUS 0x1E0900 + +#define mmMME3_CTRL_SHADOW_2_BASE_ADDR_HIGH_S 0x1E0908 + +#define mmMME3_CTRL_SHADOW_2_BASE_ADDR_HIGH_L 0x1E090C + +#define mmMME3_CTRL_SHADOW_2_BASE_ADDR_HIGH_O 0x1E0910 + +#define mmMME3_CTRL_SHADOW_2_BASE_ADDR_LOW_S 0x1E0914 + +#define mmMME3_CTRL_SHADOW_2_BASE_ADDR_LOW_L 0x1E0918 + +#define mmMME3_CTRL_SHADOW_2_BASE_ADDR_LOW_O 0x1E091C + +#define mmMME3_CTRL_SHADOW_2_HEADER_LOW 0x1E0920 + +#define mmMME3_CTRL_SHADOW_2_HEADER_HIGH 0x1E0924 + +#define mmMME3_CTRL_SHADOW_2_CONV_KERNEL_SIZE_MINUS_1 0x1E0928 + +#define mmMME3_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_LOW 0x1E092C + +#define mmMME3_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_HIGH 0x1E0930 + +#define mmMME3_CTRL_SHADOW_2_NUM_ITERATIONS_MINUS_1 0x1E0934 + +#define mmMME3_CTRL_SHADOW_2_OUTER_LOOP 0x1E0938 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_0 0x1E093C + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_1 0x1E0940 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_2 0x1E0944 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_3 0x1E0948 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_4 0x1E094C + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_0 0x1E0950 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_1 0x1E0954 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_2 0x1E0958 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_3 0x1E095C + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_4 0x1E0960 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_0 0x1E0964 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_1 0x1E0968 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_2 0x1E096C + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_3 0x1E0970 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_0 0x1E0974 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_1 0x1E0978 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_2 0x1E097C + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_3 0x1E0980 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x1E0984 + +#define mmMME3_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_0 0x1E0988 + +#define mmMME3_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_1 0x1E098C + +#define mmMME3_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_2 0x1E0990 + +#define mmMME3_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_3 0x1E0994 + +#define mmMME3_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_4 0x1E0998 + +#define mmMME3_CTRL_SHADOW_2_AGU_S_START_OFFSET_0 0x1E099C + +#define mmMME3_CTRL_SHADOW_2_AGU_S_START_OFFSET_1 0x1E09A0 + +#define mmMME3_CTRL_SHADOW_2_AGU_S_START_OFFSET_2 0x1E09A4 + +#define mmMME3_CTRL_SHADOW_2_AGU_S_START_OFFSET_3 0x1E09A8 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_0 0x1E09AC + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_1 0x1E09B0 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_2 0x1E09B4 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_3 0x1E09B8 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_4 0x1E09BC + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_0 0x1E09C0 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_1 0x1E09C4 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_2 0x1E09C8 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_3 0x1E09CC + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_4 0x1E09D0 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_0 0x1E09D4 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_1 0x1E09D8 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_2 0x1E09DC + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_3 0x1E09E0 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_0 0x1E09E4 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_1 0x1E09E8 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_2 0x1E09EC + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_3 0x1E09F0 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1E09F4 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1E09F8 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1E09FC + +#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x1E0A00 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x1E0A04 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x1E0A08 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_0 0x1E0A0C + +#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_1 0x1E0A10 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_2 0x1E0A14 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_3 0x1E0A18 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x1E0A1C + +#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x1E0A20 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x1E0A24 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x1E0A28 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x1E0A2C + +#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_0 0x1E0A30 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_1 0x1E0A34 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_2 0x1E0A38 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_3 0x1E0A3C + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_0 0x1E0A40 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_1 0x1E0A44 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_2 0x1E0A48 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_3 0x1E0A4C + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_4 0x1E0A50 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_0 0x1E0A54 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_1 0x1E0A58 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_2 0x1E0A5C + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_3 0x1E0A60 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_4 0x1E0A64 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_0 0x1E0A68 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_1 0x1E0A6C + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_2 0x1E0A70 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_3 0x1E0A74 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_0 0x1E0A78 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_1 0x1E0A7C + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_2 0x1E0A80 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_3 0x1E0A84 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x1E0A88 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x1E0A8C + +#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x1E0A90 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x1E0A94 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x1E0A98 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x1E0A9C + +#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_0 0x1E0AA0 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_1 0x1E0AA4 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_2 0x1E0AA8 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_3 0x1E0AAC + +#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x1E0AB0 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x1E0AB4 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x1E0AB8 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x1E0ABC + +#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x1E0AC0 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_0 0x1E0AC4 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_1 0x1E0AC8 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_2 0x1E0ACC + +#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_3 0x1E0AD0 + +#define mmMME3_CTRL_SHADOW_2_DESC_SB_REPEAT 0x1E0AD4 + +#define mmMME3_CTRL_SHADOW_2_DESC_RATE_LIMITER 0x1E0AD8 + +#define mmMME3_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x1E0ADC + +#define mmMME3_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x1E0AE0 + +#define mmMME3_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_HIGH 0x1E0AE4 + +#define mmMME3_CTRL_SHADOW_2_DESC_SYNC_OBJECT_DATA 0x1E0AE8 + +#define mmMME3_CTRL_SHADOW_2_DESC_AXI_USER_DATA 0x1E0AEC + +#define mmMME3_CTRL_SHADOW_2_DESC_PERF_EVT_S 0x1E0AF0 + +#define mmMME3_CTRL_SHADOW_2_DESC_PERF_EVT_L_LOCAL 0x1E0AF4 + +#define mmMME3_CTRL_SHADOW_2_DESC_PERF_EVT_L_REMOTE 0x1E0AF8 + +#define mmMME3_CTRL_SHADOW_2_DESC_PERF_EVT_O_LOCAL 0x1E0AFC + +#define mmMME3_CTRL_SHADOW_2_DESC_PERF_EVT_O_REMOTE 0x1E0B00 + +#define mmMME3_CTRL_SHADOW_2_DESC_PADDING_VALUE_S 0x1E0B04 + +#define mmMME3_CTRL_SHADOW_2_DESC_PADDING_VALUE_L 0x1E0B08 + +#define mmMME3_CTRL_SHADOW_2_DESC_META_DATA_AGU_S 0x1E0B0C + +#define mmMME3_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_LOCAL 0x1E0B10 + +#define mmMME3_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_REMOTE 0x1E0B14 + +#define mmMME3_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_LOCAL 0x1E0B18 + +#define mmMME3_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_REMOTE 0x1E0B1C + +#define mmMME3_CTRL_SHADOW_2_DESC_PCU_RL_SATURATION 0x1E0B20 + +#define mmMME3_CTRL_SHADOW_2_DESC_DUMMY 0x1E0B24 + +#define mmMME3_CTRL_SHADOW_3_STATUS 0x1E0B80 + +#define mmMME3_CTRL_SHADOW_3_BASE_ADDR_HIGH_S 0x1E0B88 + +#define mmMME3_CTRL_SHADOW_3_BASE_ADDR_HIGH_L 0x1E0B8C + +#define mmMME3_CTRL_SHADOW_3_BASE_ADDR_HIGH_O 0x1E0B90 + +#define mmMME3_CTRL_SHADOW_3_BASE_ADDR_LOW_S 0x1E0B94 + +#define mmMME3_CTRL_SHADOW_3_BASE_ADDR_LOW_L 0x1E0B98 + +#define mmMME3_CTRL_SHADOW_3_BASE_ADDR_LOW_O 0x1E0B9C + +#define mmMME3_CTRL_SHADOW_3_HEADER_LOW 0x1E0BA0 + +#define mmMME3_CTRL_SHADOW_3_HEADER_HIGH 0x1E0BA4 + +#define mmMME3_CTRL_SHADOW_3_CONV_KERNEL_SIZE_MINUS_1 0x1E0BA8 + +#define mmMME3_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_LOW 0x1E0BAC + +#define mmMME3_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_HIGH 0x1E0BB0 + +#define mmMME3_CTRL_SHADOW_3_NUM_ITERATIONS_MINUS_1 0x1E0BB4 + +#define mmMME3_CTRL_SHADOW_3_OUTER_LOOP 0x1E0BB8 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_0 0x1E0BBC + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_1 0x1E0BC0 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_2 0x1E0BC4 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_3 0x1E0BC8 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_4 0x1E0BCC + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_0 0x1E0BD0 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_1 0x1E0BD4 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_2 0x1E0BD8 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_3 0x1E0BDC + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_4 0x1E0BE0 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_0 0x1E0BE4 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_1 0x1E0BE8 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_2 0x1E0BEC + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_3 0x1E0BF0 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_0 0x1E0BF4 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_1 0x1E0BF8 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_2 0x1E0BFC + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_3 0x1E0C00 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x1E0C04 + +#define mmMME3_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_0 0x1E0C08 + +#define mmMME3_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_1 0x1E0C0C + +#define mmMME3_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_2 0x1E0C10 + +#define mmMME3_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_3 0x1E0C14 + +#define mmMME3_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_4 0x1E0C18 + +#define mmMME3_CTRL_SHADOW_3_AGU_S_START_OFFSET_0 0x1E0C1C + +#define mmMME3_CTRL_SHADOW_3_AGU_S_START_OFFSET_1 0x1E0C20 + +#define mmMME3_CTRL_SHADOW_3_AGU_S_START_OFFSET_2 0x1E0C24 + +#define mmMME3_CTRL_SHADOW_3_AGU_S_START_OFFSET_3 0x1E0C28 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_0 0x1E0C2C + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_1 0x1E0C30 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_2 0x1E0C34 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_3 0x1E0C38 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_4 0x1E0C3C + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_0 0x1E0C40 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_1 0x1E0C44 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_2 0x1E0C48 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_3 0x1E0C4C + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_4 0x1E0C50 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_0 0x1E0C54 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_1 0x1E0C58 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_2 0x1E0C5C + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_3 0x1E0C60 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_0 0x1E0C64 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_1 0x1E0C68 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_2 0x1E0C6C + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_3 0x1E0C70 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1E0C74 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1E0C78 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1E0C7C + +#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x1E0C80 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x1E0C84 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x1E0C88 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_0 0x1E0C8C + +#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_1 0x1E0C90 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_2 0x1E0C94 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_3 0x1E0C98 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x1E0C9C + +#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x1E0CA0 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x1E0CA4 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x1E0CA8 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x1E0CAC + +#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_0 0x1E0CB0 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_1 0x1E0CB4 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_2 0x1E0CB8 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_3 0x1E0CBC + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_0 0x1E0CC0 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_1 0x1E0CC4 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_2 0x1E0CC8 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_3 0x1E0CCC + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_4 0x1E0CD0 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_0 0x1E0CD4 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_1 0x1E0CD8 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_2 0x1E0CDC + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_3 0x1E0CE0 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_4 0x1E0CE4 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_0 0x1E0CE8 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_1 0x1E0CEC + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_2 0x1E0CF0 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_3 0x1E0CF4 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_0 0x1E0CF8 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_1 0x1E0CFC + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_2 0x1E0D00 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_3 0x1E0D04 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x1E0D08 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x1E0D0C + +#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x1E0D10 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x1E0D14 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x1E0D18 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x1E0D1C + +#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_0 0x1E0D20 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_1 0x1E0D24 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_2 0x1E0D28 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_3 0x1E0D2C + +#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x1E0D30 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x1E0D34 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x1E0D38 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x1E0D3C + +#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x1E0D40 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_0 0x1E0D44 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_1 0x1E0D48 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_2 0x1E0D4C + +#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_3 0x1E0D50 + +#define mmMME3_CTRL_SHADOW_3_DESC_SB_REPEAT 0x1E0D54 + +#define mmMME3_CTRL_SHADOW_3_DESC_RATE_LIMITER 0x1E0D58 + +#define mmMME3_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x1E0D5C + +#define mmMME3_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x1E0D60 + +#define mmMME3_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_HIGH 0x1E0D64 + +#define mmMME3_CTRL_SHADOW_3_DESC_SYNC_OBJECT_DATA 0x1E0D68 + +#define mmMME3_CTRL_SHADOW_3_DESC_AXI_USER_DATA 0x1E0D6C + +#define mmMME3_CTRL_SHADOW_3_DESC_PERF_EVT_S 0x1E0D70 + +#define mmMME3_CTRL_SHADOW_3_DESC_PERF_EVT_L_LOCAL 0x1E0D74 + +#define mmMME3_CTRL_SHADOW_3_DESC_PERF_EVT_L_REMOTE 0x1E0D78 + +#define mmMME3_CTRL_SHADOW_3_DESC_PERF_EVT_O_LOCAL 0x1E0D7C + +#define mmMME3_CTRL_SHADOW_3_DESC_PERF_EVT_O_REMOTE 0x1E0D80 + +#define mmMME3_CTRL_SHADOW_3_DESC_PADDING_VALUE_S 0x1E0D84 + +#define mmMME3_CTRL_SHADOW_3_DESC_PADDING_VALUE_L 0x1E0D88 + +#define mmMME3_CTRL_SHADOW_3_DESC_META_DATA_AGU_S 0x1E0D8C + +#define mmMME3_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_LOCAL 0x1E0D90 + +#define mmMME3_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_REMOTE 0x1E0D94 + +#define mmMME3_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_LOCAL 0x1E0D98 + +#define mmMME3_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_REMOTE 0x1E0D9C + +#define mmMME3_CTRL_SHADOW_3_DESC_PCU_RL_SATURATION 0x1E0DA0 + +#define mmMME3_CTRL_SHADOW_3_DESC_DUMMY 0x1E0DA4 + +#endif /* ASIC_REG_MME3_CTRL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/mmu_up_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/mmu_up_regs.h new file mode 100644 index 000000000000..61465b599850 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/mmu_up_regs.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MMU_UP_REGS_H_ +#define ASIC_REG_MMU_UP_REGS_H_ + +/* + ***************************************** + * MMU_UP (Prototype: MMU) + ***************************************** + */ + +#define mmMMU_UP_MMU_ENABLE 0xC1100C + +#define mmMMU_UP_FORCE_ORDERING 0xC11010 + +#define mmMMU_UP_FEATURE_ENABLE 0xC11014 + +#define mmMMU_UP_VA_ORDERING_MASK_31_7 0xC11018 + +#define mmMMU_UP_VA_ORDERING_MASK_49_32 0xC1101C + +#define mmMMU_UP_LOG2_DDR_SIZE 0xC11020 + +#define mmMMU_UP_SCRAMBLER 0xC11024 + +#define mmMMU_UP_MEM_INIT_BUSY 0xC11028 + +#define mmMMU_UP_SPI_MASK 0xC1102C + +#define mmMMU_UP_SPI_CAUSE 0xC11030 + +#define mmMMU_UP_PAGE_ERROR_CAPTURE 0xC11034 + +#define mmMMU_UP_PAGE_ERROR_CAPTURE_VA 0xC11038 + +#define mmMMU_UP_ACCESS_ERROR_CAPTURE 0xC1103C + +#define mmMMU_UP_ACCESS_ERROR_CAPTURE_VA 0xC11040 + +#define mmMMU_UP_SPI_INTERRUPT_CLR 0xC11044 + +#define mmMMU_UP_SPI_INTERRUPT_MASK 0xC11048 + +#define mmMMU_UP_DBG_MEM_WRAP_RM 0xC1104C + +#define mmMMU_UP_SPI_CAUSE_CLR 0xC11050 + +#define mmMMU_UP_SLICE_CREDIT 0xC11054 + +#define mmMMU_UP_PIPE_CREDIT 0xC11058 + +#define mmMMU_UP_RAZWI_WRITE_VLD 0xC1105C + +#define mmMMU_UP_RAZWI_WRITE_ID 0xC11060 + +#define mmMMU_UP_RAZWI_READ_VLD 0xC11064 + +#define mmMMU_UP_RAZWI_READ_ID 0xC11068 + +#define mmMMU_UP_MMU_BYPASS 0xC1106C + +#endif /* ASIC_REG_MMU_UP_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_0_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_0_regs.h new file mode 100644 index 000000000000..2efa2a54deb4 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_0_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIF_RTR_CTRL_0_REGS_H_ +#define ASIC_REG_NIF_RTR_CTRL_0_REGS_H_ + +/* + ***************************************** + * NIF_RTR_CTRL_0 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmNIF_RTR_CTRL_0_PERM_SEL 0x386108 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_0 0x386114 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_1 0x386118 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_2 0x38611C + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_3 0x386120 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_4 0x386124 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_5 0x386128 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_6 0x38612C + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_7 0x386130 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_8 0x386134 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_9 0x386138 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_10 0x38613C + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_11 0x386140 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_12 0x386144 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_13 0x386148 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_14 0x38614C + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_15 0x386150 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_16 0x386154 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_17 0x386158 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_18 0x38615C + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_19 0x386160 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_20 0x386164 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_21 0x386168 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_22 0x38616C + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_23 0x386170 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_24 0x386174 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_25 0x386178 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_26 0x38617C + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_27 0x386180 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_0 0x386184 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_1 0x386188 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_2 0x38618C + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_3 0x386190 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_4 0x386194 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_5 0x386198 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_6 0x38619C + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_7 0x3861A0 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_8 0x3861A4 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_9 0x3861A8 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_10 0x3861AC + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_11 0x3861B0 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_12 0x3861B4 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_13 0x3861B8 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_14 0x3861BC + +#define mmNIF_RTR_CTRL_0_SCRAM_SRAM_EN 0x38626C + +#define mmNIF_RTR_CTRL_0_RL_HBM_EN 0x386274 + +#define mmNIF_RTR_CTRL_0_RL_HBM_SAT 0x386278 + +#define mmNIF_RTR_CTRL_0_RL_HBM_RST 0x38627C + +#define mmNIF_RTR_CTRL_0_RL_HBM_TIMEOUT 0x386280 + +#define mmNIF_RTR_CTRL_0_SCRAM_HBM_EN 0x386284 + +#define mmNIF_RTR_CTRL_0_RL_PCI_EN 0x386288 + +#define mmNIF_RTR_CTRL_0_RL_PCI_SAT 0x38628C + +#define mmNIF_RTR_CTRL_0_RL_PCI_RST 0x386290 + +#define mmNIF_RTR_CTRL_0_RL_PCI_TIMEOUT 0x386294 + +#define mmNIF_RTR_CTRL_0_RL_SRAM_EN 0x38629C + +#define mmNIF_RTR_CTRL_0_RL_SRAM_SAT 0x3862A0 + +#define mmNIF_RTR_CTRL_0_RL_SRAM_RST 0x3862A4 + +#define mmNIF_RTR_CTRL_0_RL_SRAM_TIMEOUT 0x3862AC + +#define mmNIF_RTR_CTRL_0_RL_SRAM_RED 0x3862B4 + +#define mmNIF_RTR_CTRL_0_E2E_HBM_EN 0x3862EC + +#define mmNIF_RTR_CTRL_0_E2E_PCI_EN 0x3862F0 + +#define mmNIF_RTR_CTRL_0_E2E_HBM_WR_SIZE 0x3862F4 + +#define mmNIF_RTR_CTRL_0_E2E_PCI_WR_SIZE 0x3862F8 + +#define mmNIF_RTR_CTRL_0_E2E_AW_PCI_CTR_SET_EN 0x386404 + +#define mmNIF_RTR_CTRL_0_E2E_AW_PCI_CTR_SET 0x386408 + +#define mmNIF_RTR_CTRL_0_E2E_AW_PCI_CTR_WRAP 0x38640C + +#define mmNIF_RTR_CTRL_0_E2E_AW_PCI_CTR_CNT 0x386410 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM_CTR_SET_EN 0x386414 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM_CTR_SET 0x386418 + +#define mmNIF_RTR_CTRL_0_E2E_HBM_RD_SIZE 0x38641C + +#define mmNIF_RTR_CTRL_0_E2E_PCI_RD_SIZE 0x386420 + +#define mmNIF_RTR_CTRL_0_E2E_AR_PCI_CTR_SET_EN 0x386424 + +#define mmNIF_RTR_CTRL_0_E2E_AR_PCI_CTR_SET 0x386428 + +#define mmNIF_RTR_CTRL_0_E2E_AR_PCI_CTR_WRAP 0x38642C + +#define mmNIF_RTR_CTRL_0_E2E_AR_PCI_CTR_CNT 0x386430 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM_CTR_SET_EN 0x386434 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM_CTR_SET 0x386438 + +#define mmNIF_RTR_CTRL_0_NL_HBM_SEL_0 0x386450 + +#define mmNIF_RTR_CTRL_0_NL_HBM_SEL_1 0x386454 + +#define mmNIF_RTR_CTRL_0_NON_LIN_EN 0x386480 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_BANK_0 0x386500 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_BANK_1 0x386504 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_BANK_2 0x386508 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_BANK_3 0x38650C + +#define mmNIF_RTR_CTRL_0_NL_SRAM_BANK_4 0x386510 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_0 0x386514 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_1 0x386520 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_2 0x386524 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_3 0x386528 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_4 0x38652C + +#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_5 0x386530 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_6 0x386534 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_7 0x386538 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_8 0x38653C + +#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_9 0x386540 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_0 0x386550 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_1 0x386554 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_2 0x386558 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_3 0x38655C + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_4 0x386560 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_5 0x386564 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_6 0x386568 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_7 0x38656C + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_8 0x386570 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_9 0x386574 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_10 0x386578 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_11 0x38657C + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_12 0x386580 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_13 0x386584 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_14 0x386588 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_15 0x38658C + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_16 0x386590 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_17 0x386594 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_18 0x386598 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_0 0x3865E4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_1 0x3865E8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_2 0x3865EC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_3 0x3865F0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_4 0x3865F4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_5 0x3865F8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_6 0x3865FC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_7 0x386600 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_8 0x386604 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_9 0x386608 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_10 0x38660C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_11 0x386610 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_12 0x386614 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_13 0x386618 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_14 0x38661C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_15 0x386620 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_0 0x386624 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_1 0x386628 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_2 0x38662C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_3 0x386630 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_4 0x386634 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_5 0x386638 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_6 0x38663C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_7 0x386640 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_8 0x386644 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_9 0x386648 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_10 0x38664C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_11 0x386650 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_12 0x386654 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_13 0x386658 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_14 0x38665C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_15 0x386660 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_0 0x386664 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_1 0x386668 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_2 0x38666C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_3 0x386670 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_4 0x386674 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_5 0x386678 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_6 0x38667C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_7 0x386680 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_8 0x386684 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_9 0x386688 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_10 0x38668C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_11 0x386690 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_12 0x386694 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_13 0x386698 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_14 0x38669C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_15 0x3866A0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_0 0x3866A4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_1 0x3866A8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_2 0x3866AC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_3 0x3866B0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_4 0x3866B4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_5 0x3866B8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_6 0x3866BC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_7 0x3866C0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_8 0x3866C4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_9 0x3866C8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_10 0x3866CC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_11 0x3866D0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_12 0x3866D4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_13 0x3866D8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_14 0x3866DC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_15 0x3866E0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_0 0x3866E4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_1 0x3866E8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_2 0x3866EC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_3 0x3866F0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_4 0x3866F4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_5 0x3866F8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_6 0x3866FC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_7 0x386700 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_8 0x386704 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_9 0x386708 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_10 0x38670C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_11 0x386710 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_12 0x386714 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_13 0x386718 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_14 0x38671C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_15 0x386720 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_0 0x386724 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_1 0x386728 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_2 0x38672C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_3 0x386730 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_4 0x386734 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_5 0x386738 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_6 0x38673C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_7 0x386740 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_8 0x386744 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_9 0x386748 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_10 0x38674C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_11 0x386750 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_12 0x386754 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_13 0x386758 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_14 0x38675C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_15 0x386760 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_0 0x386764 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_1 0x386768 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_2 0x38676C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_3 0x386770 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_4 0x386774 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_5 0x386778 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_6 0x38677C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_7 0x386780 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_8 0x386784 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_9 0x386788 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_10 0x38678C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_11 0x386790 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_12 0x386794 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_13 0x386798 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_14 0x38679C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_15 0x3867A0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_0 0x3867A4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_1 0x3867A8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_2 0x3867AC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_3 0x3867B0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_4 0x3867B4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_5 0x3867B8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_6 0x3867BC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_7 0x3867C0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_8 0x3867C4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_9 0x3867C8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_10 0x3867CC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_11 0x3867D0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_12 0x3867D4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_13 0x3867D8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_14 0x3867DC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_15 0x3867E0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_0 0x386824 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_1 0x386828 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_2 0x38682C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_3 0x386830 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_4 0x386834 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_5 0x386838 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_6 0x38683C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_7 0x386840 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_8 0x386844 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_9 0x386848 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_10 0x38684C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_11 0x386850 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_12 0x386854 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_13 0x386858 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_14 0x38685C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_15 0x386860 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_0 0x386864 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_1 0x386868 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_2 0x38686C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_3 0x386870 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_4 0x386874 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_5 0x386878 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_6 0x38687C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_7 0x386880 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_8 0x386884 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_9 0x386888 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_10 0x38688C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_11 0x386890 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_12 0x386894 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_13 0x386898 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_14 0x38689C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_15 0x3868A0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_0 0x3868A4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_1 0x3868A8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_2 0x3868AC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_3 0x3868B0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_4 0x3868B4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_5 0x3868B8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_6 0x3868BC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_7 0x3868C0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_8 0x3868C4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_9 0x3868C8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_10 0x3868CC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_11 0x3868D0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_12 0x3868D4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_13 0x3868D8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_14 0x3868DC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_15 0x3868E0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_0 0x3868E4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_1 0x3868E8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_2 0x3868EC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_3 0x3868F0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_4 0x3868F4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_5 0x3868F8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_6 0x3868FC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_7 0x386900 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_8 0x386904 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_9 0x386908 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_10 0x38690C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_11 0x386910 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_12 0x386914 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_13 0x386918 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_14 0x38691C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_15 0x386920 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_0 0x386924 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_1 0x386928 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_2 0x38692C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_3 0x386930 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_4 0x386934 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_5 0x386938 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_6 0x38693C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_7 0x386940 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_8 0x386944 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_9 0x386948 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_10 0x38694C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_11 0x386950 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_12 0x386954 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_13 0x386958 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_14 0x38695C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_15 0x386960 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_0 0x386964 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_1 0x386968 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_2 0x38696C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_3 0x386970 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_4 0x386974 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_5 0x386978 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_6 0x38697C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_7 0x386980 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_8 0x386984 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_9 0x386988 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_10 0x38698C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_11 0x386990 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_12 0x386994 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_13 0x386998 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_14 0x38699C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_15 0x3869A0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_0 0x3869A4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_1 0x3869A8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_2 0x3869AC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_3 0x3869B0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_4 0x3869B4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_5 0x3869B8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_6 0x3869BC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_7 0x3869C0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_8 0x3869C4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_9 0x3869C8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_10 0x3869CC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_11 0x3869D0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_12 0x3869D4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_13 0x3869D8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_14 0x3869DC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_15 0x3869E0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_0 0x3869E4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_1 0x3869E8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_2 0x3869EC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_3 0x3869F0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_4 0x3869F4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_5 0x3869F8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_6 0x3869FC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_7 0x386A00 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_8 0x386A04 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_9 0x386A08 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_10 0x386A0C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_11 0x386A10 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_12 0x386A14 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_13 0x386A18 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_14 0x386A1C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_15 0x386A20 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_HIT_AW 0x386A64 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_HIT_AR 0x386A68 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_HIT_AW 0x386A6C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_HIT_AR 0x386A70 + +#define mmNIF_RTR_CTRL_0_RGL_CFG 0x386B64 + +#define mmNIF_RTR_CTRL_0_RGL_SHIFT 0x386B68 + +#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_0 0x386B6C + +#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_1 0x386B70 + +#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_2 0x386B74 + +#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_3 0x386B78 + +#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_4 0x386B7C + +#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_5 0x386B80 + +#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_6 0x386B84 + +#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_7 0x386B88 + +#define mmNIF_RTR_CTRL_0_RGL_TOKEN_0 0x386BAC + +#define mmNIF_RTR_CTRL_0_RGL_TOKEN_1 0x386BB0 + +#define mmNIF_RTR_CTRL_0_RGL_TOKEN_2 0x386BB4 + +#define mmNIF_RTR_CTRL_0_RGL_TOKEN_3 0x386BB8 + +#define mmNIF_RTR_CTRL_0_RGL_TOKEN_4 0x386BBC + +#define mmNIF_RTR_CTRL_0_RGL_TOKEN_5 0x386BC0 + +#define mmNIF_RTR_CTRL_0_RGL_TOKEN_6 0x386BC4 + +#define mmNIF_RTR_CTRL_0_RGL_TOKEN_7 0x386BC8 + +#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_0 0x386BEC + +#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_1 0x386BF0 + +#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_2 0x386BF4 + +#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_3 0x386BF8 + +#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_4 0x386BFC + +#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_5 0x386C00 + +#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_6 0x386C04 + +#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_7 0x386C08 + +#define mmNIF_RTR_CTRL_0_RGL_WDT 0x386C2C + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM0_CH0_CTR_WRAP 0x386C30 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM0_CH1_CTR_WRAP 0x386C34 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM1_CH0_CTR_WRAP 0x386C38 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM1_CH1_CTR_WRAP 0x386C3C + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM2_CH0_CTR_WRAP 0x386C40 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM2_CH1_CTR_WRAP 0x386C44 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM3_CH0_CTR_WRAP 0x386C48 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM3_CH1_CTR_WRAP 0x386C4C + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM0_CH0_CTR_CNT 0x386C50 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM0_CH1_CTR_CNT 0x386C54 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM1_CH0_CTR_CNT 0x386C58 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM1_CH1_CTR_CNT 0x386C5C + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM2_CH0_CTR_CNT 0x386C60 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM2_CH1_CTR_CNT 0x386C64 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM3_CH0_CTR_CNT 0x386C68 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM3_CH1_CTR_CNT 0x386C6C + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM0_CH0_CTR_WRAP 0x386C70 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM0_CH1_CTR_WRAP 0x386C74 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM1_CH0_CTR_WRAP 0x386C78 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM1_CH1_CTR_WRAP 0x386C7C + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM2_CH0_CTR_WRAP 0x386C80 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM2_CH1_CTR_WRAP 0x386C84 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM3_CH0_CTR_WRAP 0x386C88 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM3_CH1_CTR_WRAP 0x386C8C + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM0_CH0_CTR_CNT 0x386C90 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM0_CH1_CTR_CNT 0x386C94 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM1_CH0_CTR_CNT 0x386C98 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM1_CH1_CTR_CNT 0x386C9C + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM2_CH0_CTR_CNT 0x386CA0 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM2_CH1_CTR_CNT 0x386CA4 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM3_CH0_CTR_CNT 0x386CA8 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM3_CH1_CTR_CNT 0x386CAC + +#define mmNIF_RTR_CTRL_0_NL_HBM_PC_SEL_0 0x386CB0 + +#define mmNIF_RTR_CTRL_0_NL_HBM_PC_SEL_1 0x386CB4 + +#define mmNIF_RTR_CTRL_0_NL_HBM_PC_SEL_2 0x386CB8 + +#define mmNIF_RTR_CTRL_0_NL_HBM_PC_SEL_3 0x386CBC + +#endif /* ASIC_REG_NIF_RTR_CTRL_0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_1_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_1_regs.h new file mode 100644 index 000000000000..a6047d4e2560 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_1_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIF_RTR_CTRL_1_REGS_H_ +#define ASIC_REG_NIF_RTR_CTRL_1_REGS_H_ + +/* + ***************************************** + * NIF_RTR_CTRL_1 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmNIF_RTR_CTRL_1_PERM_SEL 0x396108 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_0 0x396114 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_1 0x396118 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_2 0x39611C + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_3 0x396120 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_4 0x396124 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_5 0x396128 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_6 0x39612C + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_7 0x396130 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_8 0x396134 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_9 0x396138 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_10 0x39613C + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_11 0x396140 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_12 0x396144 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_13 0x396148 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_14 0x39614C + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_15 0x396150 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_16 0x396154 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_17 0x396158 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_18 0x39615C + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_19 0x396160 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_20 0x396164 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_21 0x396168 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_22 0x39616C + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_23 0x396170 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_24 0x396174 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_25 0x396178 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_26 0x39617C + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_27 0x396180 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_0 0x396184 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_1 0x396188 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_2 0x39618C + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_3 0x396190 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_4 0x396194 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_5 0x396198 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_6 0x39619C + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_7 0x3961A0 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_8 0x3961A4 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_9 0x3961A8 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_10 0x3961AC + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_11 0x3961B0 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_12 0x3961B4 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_13 0x3961B8 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_14 0x3961BC + +#define mmNIF_RTR_CTRL_1_SCRAM_SRAM_EN 0x39626C + +#define mmNIF_RTR_CTRL_1_RL_HBM_EN 0x396274 + +#define mmNIF_RTR_CTRL_1_RL_HBM_SAT 0x396278 + +#define mmNIF_RTR_CTRL_1_RL_HBM_RST 0x39627C + +#define mmNIF_RTR_CTRL_1_RL_HBM_TIMEOUT 0x396280 + +#define mmNIF_RTR_CTRL_1_SCRAM_HBM_EN 0x396284 + +#define mmNIF_RTR_CTRL_1_RL_PCI_EN 0x396288 + +#define mmNIF_RTR_CTRL_1_RL_PCI_SAT 0x39628C + +#define mmNIF_RTR_CTRL_1_RL_PCI_RST 0x396290 + +#define mmNIF_RTR_CTRL_1_RL_PCI_TIMEOUT 0x396294 + +#define mmNIF_RTR_CTRL_1_RL_SRAM_EN 0x39629C + +#define mmNIF_RTR_CTRL_1_RL_SRAM_SAT 0x3962A0 + +#define mmNIF_RTR_CTRL_1_RL_SRAM_RST 0x3962A4 + +#define mmNIF_RTR_CTRL_1_RL_SRAM_TIMEOUT 0x3962AC + +#define mmNIF_RTR_CTRL_1_RL_SRAM_RED 0x3962B4 + +#define mmNIF_RTR_CTRL_1_E2E_HBM_EN 0x3962EC + +#define mmNIF_RTR_CTRL_1_E2E_PCI_EN 0x3962F0 + +#define mmNIF_RTR_CTRL_1_E2E_HBM_WR_SIZE 0x3962F4 + +#define mmNIF_RTR_CTRL_1_E2E_PCI_WR_SIZE 0x3962F8 + +#define mmNIF_RTR_CTRL_1_E2E_AW_PCI_CTR_SET_EN 0x396404 + +#define mmNIF_RTR_CTRL_1_E2E_AW_PCI_CTR_SET 0x396408 + +#define mmNIF_RTR_CTRL_1_E2E_AW_PCI_CTR_WRAP 0x39640C + +#define mmNIF_RTR_CTRL_1_E2E_AW_PCI_CTR_CNT 0x396410 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM_CTR_SET_EN 0x396414 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM_CTR_SET 0x396418 + +#define mmNIF_RTR_CTRL_1_E2E_HBM_RD_SIZE 0x39641C + +#define mmNIF_RTR_CTRL_1_E2E_PCI_RD_SIZE 0x396420 + +#define mmNIF_RTR_CTRL_1_E2E_AR_PCI_CTR_SET_EN 0x396424 + +#define mmNIF_RTR_CTRL_1_E2E_AR_PCI_CTR_SET 0x396428 + +#define mmNIF_RTR_CTRL_1_E2E_AR_PCI_CTR_WRAP 0x39642C + +#define mmNIF_RTR_CTRL_1_E2E_AR_PCI_CTR_CNT 0x396430 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM_CTR_SET_EN 0x396434 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM_CTR_SET 0x396438 + +#define mmNIF_RTR_CTRL_1_NL_HBM_SEL_0 0x396450 + +#define mmNIF_RTR_CTRL_1_NL_HBM_SEL_1 0x396454 + +#define mmNIF_RTR_CTRL_1_NON_LIN_EN 0x396480 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_BANK_0 0x396500 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_BANK_1 0x396504 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_BANK_2 0x396508 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_BANK_3 0x39650C + +#define mmNIF_RTR_CTRL_1_NL_SRAM_BANK_4 0x396510 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_0 0x396514 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_1 0x396520 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_2 0x396524 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_3 0x396528 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_4 0x39652C + +#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_5 0x396530 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_6 0x396534 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_7 0x396538 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_8 0x39653C + +#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_9 0x396540 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_0 0x396550 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_1 0x396554 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_2 0x396558 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_3 0x39655C + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_4 0x396560 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_5 0x396564 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_6 0x396568 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_7 0x39656C + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_8 0x396570 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_9 0x396574 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_10 0x396578 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_11 0x39657C + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_12 0x396580 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_13 0x396584 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_14 0x396588 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_15 0x39658C + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_16 0x396590 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_17 0x396594 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_18 0x396598 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_0 0x3965E4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_1 0x3965E8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_2 0x3965EC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_3 0x3965F0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_4 0x3965F4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_5 0x3965F8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_6 0x3965FC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_7 0x396600 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_8 0x396604 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_9 0x396608 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_10 0x39660C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_11 0x396610 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_12 0x396614 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_13 0x396618 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_14 0x39661C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_15 0x396620 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_0 0x396624 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_1 0x396628 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_2 0x39662C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_3 0x396630 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_4 0x396634 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_5 0x396638 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_6 0x39663C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_7 0x396640 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_8 0x396644 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_9 0x396648 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_10 0x39664C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_11 0x396650 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_12 0x396654 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_13 0x396658 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_14 0x39665C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_15 0x396660 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_0 0x396664 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_1 0x396668 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_2 0x39666C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_3 0x396670 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_4 0x396674 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_5 0x396678 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_6 0x39667C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_7 0x396680 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_8 0x396684 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_9 0x396688 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_10 0x39668C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_11 0x396690 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_12 0x396694 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_13 0x396698 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_14 0x39669C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_15 0x3966A0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_0 0x3966A4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_1 0x3966A8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_2 0x3966AC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_3 0x3966B0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_4 0x3966B4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_5 0x3966B8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_6 0x3966BC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_7 0x3966C0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_8 0x3966C4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_9 0x3966C8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_10 0x3966CC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_11 0x3966D0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_12 0x3966D4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_13 0x3966D8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_14 0x3966DC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_15 0x3966E0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_0 0x3966E4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_1 0x3966E8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_2 0x3966EC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_3 0x3966F0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_4 0x3966F4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_5 0x3966F8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_6 0x3966FC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_7 0x396700 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_8 0x396704 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_9 0x396708 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_10 0x39670C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_11 0x396710 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_12 0x396714 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_13 0x396718 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_14 0x39671C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_15 0x396720 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_0 0x396724 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_1 0x396728 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_2 0x39672C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_3 0x396730 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_4 0x396734 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_5 0x396738 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_6 0x39673C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_7 0x396740 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_8 0x396744 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_9 0x396748 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_10 0x39674C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_11 0x396750 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_12 0x396754 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_13 0x396758 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_14 0x39675C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_15 0x396760 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_0 0x396764 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_1 0x396768 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_2 0x39676C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_3 0x396770 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_4 0x396774 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_5 0x396778 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_6 0x39677C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_7 0x396780 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_8 0x396784 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_9 0x396788 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_10 0x39678C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_11 0x396790 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_12 0x396794 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_13 0x396798 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_14 0x39679C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_15 0x3967A0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_0 0x3967A4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_1 0x3967A8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_2 0x3967AC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_3 0x3967B0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_4 0x3967B4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_5 0x3967B8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_6 0x3967BC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_7 0x3967C0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_8 0x3967C4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_9 0x3967C8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_10 0x3967CC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_11 0x3967D0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_12 0x3967D4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_13 0x3967D8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_14 0x3967DC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_15 0x3967E0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_0 0x396824 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_1 0x396828 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_2 0x39682C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_3 0x396830 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_4 0x396834 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_5 0x396838 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_6 0x39683C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_7 0x396840 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_8 0x396844 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_9 0x396848 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_10 0x39684C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_11 0x396850 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_12 0x396854 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_13 0x396858 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_14 0x39685C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_15 0x396860 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_0 0x396864 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_1 0x396868 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_2 0x39686C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_3 0x396870 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_4 0x396874 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_5 0x396878 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_6 0x39687C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_7 0x396880 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_8 0x396884 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_9 0x396888 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_10 0x39688C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_11 0x396890 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_12 0x396894 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_13 0x396898 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_14 0x39689C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_15 0x3968A0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_0 0x3968A4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_1 0x3968A8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_2 0x3968AC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_3 0x3968B0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_4 0x3968B4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_5 0x3968B8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_6 0x3968BC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_7 0x3968C0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_8 0x3968C4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_9 0x3968C8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_10 0x3968CC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_11 0x3968D0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_12 0x3968D4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_13 0x3968D8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_14 0x3968DC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_15 0x3968E0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_0 0x3968E4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_1 0x3968E8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_2 0x3968EC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_3 0x3968F0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_4 0x3968F4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_5 0x3968F8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_6 0x3968FC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_7 0x396900 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_8 0x396904 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_9 0x396908 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_10 0x39690C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_11 0x396910 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_12 0x396914 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_13 0x396918 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_14 0x39691C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_15 0x396920 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_0 0x396924 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_1 0x396928 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_2 0x39692C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_3 0x396930 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_4 0x396934 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_5 0x396938 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_6 0x39693C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_7 0x396940 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_8 0x396944 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_9 0x396948 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_10 0x39694C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_11 0x396950 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_12 0x396954 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_13 0x396958 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_14 0x39695C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_15 0x396960 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_0 0x396964 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_1 0x396968 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_2 0x39696C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_3 0x396970 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_4 0x396974 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_5 0x396978 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_6 0x39697C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_7 0x396980 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_8 0x396984 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_9 0x396988 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_10 0x39698C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_11 0x396990 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_12 0x396994 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_13 0x396998 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_14 0x39699C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_15 0x3969A0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_0 0x3969A4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_1 0x3969A8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_2 0x3969AC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_3 0x3969B0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_4 0x3969B4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_5 0x3969B8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_6 0x3969BC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_7 0x3969C0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_8 0x3969C4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_9 0x3969C8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_10 0x3969CC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_11 0x3969D0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_12 0x3969D4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_13 0x3969D8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_14 0x3969DC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_15 0x3969E0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_0 0x3969E4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_1 0x3969E8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_2 0x3969EC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_3 0x3969F0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_4 0x3969F4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_5 0x3969F8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_6 0x3969FC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_7 0x396A00 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_8 0x396A04 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_9 0x396A08 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_10 0x396A0C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_11 0x396A10 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_12 0x396A14 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_13 0x396A18 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_14 0x396A1C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_15 0x396A20 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_HIT_AW 0x396A64 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_HIT_AR 0x396A68 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_HIT_AW 0x396A6C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_HIT_AR 0x396A70 + +#define mmNIF_RTR_CTRL_1_RGL_CFG 0x396B64 + +#define mmNIF_RTR_CTRL_1_RGL_SHIFT 0x396B68 + +#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_0 0x396B6C + +#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_1 0x396B70 + +#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_2 0x396B74 + +#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_3 0x396B78 + +#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_4 0x396B7C + +#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_5 0x396B80 + +#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_6 0x396B84 + +#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_7 0x396B88 + +#define mmNIF_RTR_CTRL_1_RGL_TOKEN_0 0x396BAC + +#define mmNIF_RTR_CTRL_1_RGL_TOKEN_1 0x396BB0 + +#define mmNIF_RTR_CTRL_1_RGL_TOKEN_2 0x396BB4 + +#define mmNIF_RTR_CTRL_1_RGL_TOKEN_3 0x396BB8 + +#define mmNIF_RTR_CTRL_1_RGL_TOKEN_4 0x396BBC + +#define mmNIF_RTR_CTRL_1_RGL_TOKEN_5 0x396BC0 + +#define mmNIF_RTR_CTRL_1_RGL_TOKEN_6 0x396BC4 + +#define mmNIF_RTR_CTRL_1_RGL_TOKEN_7 0x396BC8 + +#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_0 0x396BEC + +#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_1 0x396BF0 + +#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_2 0x396BF4 + +#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_3 0x396BF8 + +#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_4 0x396BFC + +#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_5 0x396C00 + +#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_6 0x396C04 + +#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_7 0x396C08 + +#define mmNIF_RTR_CTRL_1_RGL_WDT 0x396C2C + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM0_CH0_CTR_WRAP 0x396C30 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM0_CH1_CTR_WRAP 0x396C34 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM1_CH0_CTR_WRAP 0x396C38 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM1_CH1_CTR_WRAP 0x396C3C + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM2_CH0_CTR_WRAP 0x396C40 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM2_CH1_CTR_WRAP 0x396C44 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM3_CH0_CTR_WRAP 0x396C48 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM3_CH1_CTR_WRAP 0x396C4C + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM0_CH0_CTR_CNT 0x396C50 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM0_CH1_CTR_CNT 0x396C54 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM1_CH0_CTR_CNT 0x396C58 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM1_CH1_CTR_CNT 0x396C5C + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM2_CH0_CTR_CNT 0x396C60 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM2_CH1_CTR_CNT 0x396C64 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM3_CH0_CTR_CNT 0x396C68 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM3_CH1_CTR_CNT 0x396C6C + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM0_CH0_CTR_WRAP 0x396C70 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM0_CH1_CTR_WRAP 0x396C74 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM1_CH0_CTR_WRAP 0x396C78 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM1_CH1_CTR_WRAP 0x396C7C + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM2_CH0_CTR_WRAP 0x396C80 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM2_CH1_CTR_WRAP 0x396C84 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM3_CH0_CTR_WRAP 0x396C88 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM3_CH1_CTR_WRAP 0x396C8C + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM0_CH0_CTR_CNT 0x396C90 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM0_CH1_CTR_CNT 0x396C94 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM1_CH0_CTR_CNT 0x396C98 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM1_CH1_CTR_CNT 0x396C9C + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM2_CH0_CTR_CNT 0x396CA0 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM2_CH1_CTR_CNT 0x396CA4 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM3_CH0_CTR_CNT 0x396CA8 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM3_CH1_CTR_CNT 0x396CAC + +#define mmNIF_RTR_CTRL_1_NL_HBM_PC_SEL_0 0x396CB0 + +#define mmNIF_RTR_CTRL_1_NL_HBM_PC_SEL_1 0x396CB4 + +#define mmNIF_RTR_CTRL_1_NL_HBM_PC_SEL_2 0x396CB8 + +#define mmNIF_RTR_CTRL_1_NL_HBM_PC_SEL_3 0x396CBC + +#endif /* ASIC_REG_NIF_RTR_CTRL_1_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_2_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_2_regs.h new file mode 100644 index 000000000000..9de8442f9bc2 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_2_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIF_RTR_CTRL_2_REGS_H_ +#define ASIC_REG_NIF_RTR_CTRL_2_REGS_H_ + +/* + ***************************************** + * NIF_RTR_CTRL_2 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmNIF_RTR_CTRL_2_PERM_SEL 0x3A6108 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_0 0x3A6114 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_1 0x3A6118 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_2 0x3A611C + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_3 0x3A6120 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_4 0x3A6124 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_5 0x3A6128 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_6 0x3A612C + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_7 0x3A6130 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_8 0x3A6134 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_9 0x3A6138 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_10 0x3A613C + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_11 0x3A6140 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_12 0x3A6144 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_13 0x3A6148 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_14 0x3A614C + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_15 0x3A6150 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_16 0x3A6154 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_17 0x3A6158 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_18 0x3A615C + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_19 0x3A6160 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_20 0x3A6164 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_21 0x3A6168 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_22 0x3A616C + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_23 0x3A6170 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_24 0x3A6174 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_25 0x3A6178 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_26 0x3A617C + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_27 0x3A6180 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_0 0x3A6184 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_1 0x3A6188 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_2 0x3A618C + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_3 0x3A6190 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_4 0x3A6194 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_5 0x3A6198 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_6 0x3A619C + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_7 0x3A61A0 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_8 0x3A61A4 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_9 0x3A61A8 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_10 0x3A61AC + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_11 0x3A61B0 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_12 0x3A61B4 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_13 0x3A61B8 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_14 0x3A61BC + +#define mmNIF_RTR_CTRL_2_SCRAM_SRAM_EN 0x3A626C + +#define mmNIF_RTR_CTRL_2_RL_HBM_EN 0x3A6274 + +#define mmNIF_RTR_CTRL_2_RL_HBM_SAT 0x3A6278 + +#define mmNIF_RTR_CTRL_2_RL_HBM_RST 0x3A627C + +#define mmNIF_RTR_CTRL_2_RL_HBM_TIMEOUT 0x3A6280 + +#define mmNIF_RTR_CTRL_2_SCRAM_HBM_EN 0x3A6284 + +#define mmNIF_RTR_CTRL_2_RL_PCI_EN 0x3A6288 + +#define mmNIF_RTR_CTRL_2_RL_PCI_SAT 0x3A628C + +#define mmNIF_RTR_CTRL_2_RL_PCI_RST 0x3A6290 + +#define mmNIF_RTR_CTRL_2_RL_PCI_TIMEOUT 0x3A6294 + +#define mmNIF_RTR_CTRL_2_RL_SRAM_EN 0x3A629C + +#define mmNIF_RTR_CTRL_2_RL_SRAM_SAT 0x3A62A0 + +#define mmNIF_RTR_CTRL_2_RL_SRAM_RST 0x3A62A4 + +#define mmNIF_RTR_CTRL_2_RL_SRAM_TIMEOUT 0x3A62AC + +#define mmNIF_RTR_CTRL_2_RL_SRAM_RED 0x3A62B4 + +#define mmNIF_RTR_CTRL_2_E2E_HBM_EN 0x3A62EC + +#define mmNIF_RTR_CTRL_2_E2E_PCI_EN 0x3A62F0 + +#define mmNIF_RTR_CTRL_2_E2E_HBM_WR_SIZE 0x3A62F4 + +#define mmNIF_RTR_CTRL_2_E2E_PCI_WR_SIZE 0x3A62F8 + +#define mmNIF_RTR_CTRL_2_E2E_AW_PCI_CTR_SET_EN 0x3A6404 + +#define mmNIF_RTR_CTRL_2_E2E_AW_PCI_CTR_SET 0x3A6408 + +#define mmNIF_RTR_CTRL_2_E2E_AW_PCI_CTR_WRAP 0x3A640C + +#define mmNIF_RTR_CTRL_2_E2E_AW_PCI_CTR_CNT 0x3A6410 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM_CTR_SET_EN 0x3A6414 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM_CTR_SET 0x3A6418 + +#define mmNIF_RTR_CTRL_2_E2E_HBM_RD_SIZE 0x3A641C + +#define mmNIF_RTR_CTRL_2_E2E_PCI_RD_SIZE 0x3A6420 + +#define mmNIF_RTR_CTRL_2_E2E_AR_PCI_CTR_SET_EN 0x3A6424 + +#define mmNIF_RTR_CTRL_2_E2E_AR_PCI_CTR_SET 0x3A6428 + +#define mmNIF_RTR_CTRL_2_E2E_AR_PCI_CTR_WRAP 0x3A642C + +#define mmNIF_RTR_CTRL_2_E2E_AR_PCI_CTR_CNT 0x3A6430 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM_CTR_SET_EN 0x3A6434 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM_CTR_SET 0x3A6438 + +#define mmNIF_RTR_CTRL_2_NL_HBM_SEL_0 0x3A6450 + +#define mmNIF_RTR_CTRL_2_NL_HBM_SEL_1 0x3A6454 + +#define mmNIF_RTR_CTRL_2_NON_LIN_EN 0x3A6480 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_BANK_0 0x3A6500 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_BANK_1 0x3A6504 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_BANK_2 0x3A6508 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_BANK_3 0x3A650C + +#define mmNIF_RTR_CTRL_2_NL_SRAM_BANK_4 0x3A6510 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_0 0x3A6514 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_1 0x3A6520 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_2 0x3A6524 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_3 0x3A6528 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_4 0x3A652C + +#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_5 0x3A6530 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_6 0x3A6534 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_7 0x3A6538 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_8 0x3A653C + +#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_9 0x3A6540 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_0 0x3A6550 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_1 0x3A6554 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_2 0x3A6558 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_3 0x3A655C + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_4 0x3A6560 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_5 0x3A6564 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_6 0x3A6568 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_7 0x3A656C + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_8 0x3A6570 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_9 0x3A6574 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_10 0x3A6578 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_11 0x3A657C + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_12 0x3A6580 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_13 0x3A6584 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_14 0x3A6588 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_15 0x3A658C + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_16 0x3A6590 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_17 0x3A6594 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_18 0x3A6598 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_0 0x3A65E4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_1 0x3A65E8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_2 0x3A65EC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_3 0x3A65F0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_4 0x3A65F4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_5 0x3A65F8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_6 0x3A65FC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_7 0x3A6600 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_8 0x3A6604 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_9 0x3A6608 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_10 0x3A660C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_11 0x3A6610 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_12 0x3A6614 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_13 0x3A6618 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_14 0x3A661C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_15 0x3A6620 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_0 0x3A6624 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_1 0x3A6628 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_2 0x3A662C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_3 0x3A6630 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_4 0x3A6634 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_5 0x3A6638 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_6 0x3A663C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_7 0x3A6640 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_8 0x3A6644 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_9 0x3A6648 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_10 0x3A664C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_11 0x3A6650 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_12 0x3A6654 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_13 0x3A6658 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_14 0x3A665C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_15 0x3A6660 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_0 0x3A6664 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_1 0x3A6668 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_2 0x3A666C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_3 0x3A6670 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_4 0x3A6674 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_5 0x3A6678 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_6 0x3A667C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_7 0x3A6680 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_8 0x3A6684 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_9 0x3A6688 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_10 0x3A668C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_11 0x3A6690 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_12 0x3A6694 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_13 0x3A6698 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_14 0x3A669C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_15 0x3A66A0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_0 0x3A66A4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_1 0x3A66A8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_2 0x3A66AC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_3 0x3A66B0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_4 0x3A66B4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_5 0x3A66B8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_6 0x3A66BC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_7 0x3A66C0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_8 0x3A66C4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_9 0x3A66C8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_10 0x3A66CC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_11 0x3A66D0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_12 0x3A66D4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_13 0x3A66D8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_14 0x3A66DC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_15 0x3A66E0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_0 0x3A66E4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_1 0x3A66E8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_2 0x3A66EC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_3 0x3A66F0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_4 0x3A66F4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_5 0x3A66F8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_6 0x3A66FC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_7 0x3A6700 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_8 0x3A6704 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_9 0x3A6708 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_10 0x3A670C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_11 0x3A6710 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_12 0x3A6714 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_13 0x3A6718 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_14 0x3A671C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_15 0x3A6720 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_0 0x3A6724 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_1 0x3A6728 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_2 0x3A672C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_3 0x3A6730 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_4 0x3A6734 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_5 0x3A6738 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_6 0x3A673C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_7 0x3A6740 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_8 0x3A6744 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_9 0x3A6748 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_10 0x3A674C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_11 0x3A6750 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_12 0x3A6754 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_13 0x3A6758 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_14 0x3A675C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_15 0x3A6760 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_0 0x3A6764 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_1 0x3A6768 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_2 0x3A676C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_3 0x3A6770 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_4 0x3A6774 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_5 0x3A6778 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_6 0x3A677C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_7 0x3A6780 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_8 0x3A6784 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_9 0x3A6788 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_10 0x3A678C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_11 0x3A6790 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_12 0x3A6794 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_13 0x3A6798 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_14 0x3A679C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_15 0x3A67A0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_0 0x3A67A4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_1 0x3A67A8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_2 0x3A67AC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_3 0x3A67B0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_4 0x3A67B4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_5 0x3A67B8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_6 0x3A67BC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_7 0x3A67C0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_8 0x3A67C4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_9 0x3A67C8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_10 0x3A67CC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_11 0x3A67D0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_12 0x3A67D4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_13 0x3A67D8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_14 0x3A67DC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_15 0x3A67E0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_0 0x3A6824 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_1 0x3A6828 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_2 0x3A682C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_3 0x3A6830 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_4 0x3A6834 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_5 0x3A6838 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_6 0x3A683C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_7 0x3A6840 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_8 0x3A6844 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_9 0x3A6848 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_10 0x3A684C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_11 0x3A6850 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_12 0x3A6854 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_13 0x3A6858 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_14 0x3A685C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_15 0x3A6860 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_0 0x3A6864 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_1 0x3A6868 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_2 0x3A686C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_3 0x3A6870 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_4 0x3A6874 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_5 0x3A6878 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_6 0x3A687C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_7 0x3A6880 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_8 0x3A6884 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_9 0x3A6888 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_10 0x3A688C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_11 0x3A6890 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_12 0x3A6894 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_13 0x3A6898 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_14 0x3A689C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_15 0x3A68A0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_0 0x3A68A4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_1 0x3A68A8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_2 0x3A68AC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_3 0x3A68B0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_4 0x3A68B4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_5 0x3A68B8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_6 0x3A68BC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_7 0x3A68C0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_8 0x3A68C4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_9 0x3A68C8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_10 0x3A68CC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_11 0x3A68D0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_12 0x3A68D4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_13 0x3A68D8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_14 0x3A68DC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_15 0x3A68E0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_0 0x3A68E4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_1 0x3A68E8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_2 0x3A68EC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_3 0x3A68F0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_4 0x3A68F4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_5 0x3A68F8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_6 0x3A68FC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_7 0x3A6900 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_8 0x3A6904 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_9 0x3A6908 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_10 0x3A690C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_11 0x3A6910 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_12 0x3A6914 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_13 0x3A6918 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_14 0x3A691C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_15 0x3A6920 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_0 0x3A6924 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_1 0x3A6928 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_2 0x3A692C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_3 0x3A6930 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_4 0x3A6934 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_5 0x3A6938 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_6 0x3A693C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_7 0x3A6940 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_8 0x3A6944 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_9 0x3A6948 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_10 0x3A694C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_11 0x3A6950 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_12 0x3A6954 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_13 0x3A6958 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_14 0x3A695C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_15 0x3A6960 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_0 0x3A6964 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_1 0x3A6968 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_2 0x3A696C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_3 0x3A6970 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_4 0x3A6974 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_5 0x3A6978 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_6 0x3A697C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_7 0x3A6980 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_8 0x3A6984 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_9 0x3A6988 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_10 0x3A698C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_11 0x3A6990 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_12 0x3A6994 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_13 0x3A6998 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_14 0x3A699C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_15 0x3A69A0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_0 0x3A69A4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_1 0x3A69A8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_2 0x3A69AC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_3 0x3A69B0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_4 0x3A69B4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_5 0x3A69B8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_6 0x3A69BC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_7 0x3A69C0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_8 0x3A69C4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_9 0x3A69C8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_10 0x3A69CC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_11 0x3A69D0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_12 0x3A69D4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_13 0x3A69D8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_14 0x3A69DC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_15 0x3A69E0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_0 0x3A69E4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_1 0x3A69E8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_2 0x3A69EC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_3 0x3A69F0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_4 0x3A69F4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_5 0x3A69F8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_6 0x3A69FC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_7 0x3A6A00 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_8 0x3A6A04 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_9 0x3A6A08 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_10 0x3A6A0C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_11 0x3A6A10 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_12 0x3A6A14 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_13 0x3A6A18 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_14 0x3A6A1C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_15 0x3A6A20 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_HIT_AW 0x3A6A64 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_HIT_AR 0x3A6A68 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_HIT_AW 0x3A6A6C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_HIT_AR 0x3A6A70 + +#define mmNIF_RTR_CTRL_2_RGL_CFG 0x3A6B64 + +#define mmNIF_RTR_CTRL_2_RGL_SHIFT 0x3A6B68 + +#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_0 0x3A6B6C + +#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_1 0x3A6B70 + +#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_2 0x3A6B74 + +#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_3 0x3A6B78 + +#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_4 0x3A6B7C + +#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_5 0x3A6B80 + +#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_6 0x3A6B84 + +#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_7 0x3A6B88 + +#define mmNIF_RTR_CTRL_2_RGL_TOKEN_0 0x3A6BAC + +#define mmNIF_RTR_CTRL_2_RGL_TOKEN_1 0x3A6BB0 + +#define mmNIF_RTR_CTRL_2_RGL_TOKEN_2 0x3A6BB4 + +#define mmNIF_RTR_CTRL_2_RGL_TOKEN_3 0x3A6BB8 + +#define mmNIF_RTR_CTRL_2_RGL_TOKEN_4 0x3A6BBC + +#define mmNIF_RTR_CTRL_2_RGL_TOKEN_5 0x3A6BC0 + +#define mmNIF_RTR_CTRL_2_RGL_TOKEN_6 0x3A6BC4 + +#define mmNIF_RTR_CTRL_2_RGL_TOKEN_7 0x3A6BC8 + +#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_0 0x3A6BEC + +#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_1 0x3A6BF0 + +#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_2 0x3A6BF4 + +#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_3 0x3A6BF8 + +#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_4 0x3A6BFC + +#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_5 0x3A6C00 + +#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_6 0x3A6C04 + +#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_7 0x3A6C08 + +#define mmNIF_RTR_CTRL_2_RGL_WDT 0x3A6C2C + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM0_CH0_CTR_WRAP 0x3A6C30 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM0_CH1_CTR_WRAP 0x3A6C34 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM1_CH0_CTR_WRAP 0x3A6C38 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM1_CH1_CTR_WRAP 0x3A6C3C + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM2_CH0_CTR_WRAP 0x3A6C40 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM2_CH1_CTR_WRAP 0x3A6C44 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM3_CH0_CTR_WRAP 0x3A6C48 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM3_CH1_CTR_WRAP 0x3A6C4C + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM0_CH0_CTR_CNT 0x3A6C50 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM0_CH1_CTR_CNT 0x3A6C54 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM1_CH0_CTR_CNT 0x3A6C58 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM1_CH1_CTR_CNT 0x3A6C5C + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM2_CH0_CTR_CNT 0x3A6C60 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM2_CH1_CTR_CNT 0x3A6C64 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM3_CH0_CTR_CNT 0x3A6C68 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM3_CH1_CTR_CNT 0x3A6C6C + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM0_CH0_CTR_WRAP 0x3A6C70 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM0_CH1_CTR_WRAP 0x3A6C74 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM1_CH0_CTR_WRAP 0x3A6C78 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM1_CH1_CTR_WRAP 0x3A6C7C + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM2_CH0_CTR_WRAP 0x3A6C80 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM2_CH1_CTR_WRAP 0x3A6C84 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM3_CH0_CTR_WRAP 0x3A6C88 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM3_CH1_CTR_WRAP 0x3A6C8C + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM0_CH0_CTR_CNT 0x3A6C90 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM0_CH1_CTR_CNT 0x3A6C94 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM1_CH0_CTR_CNT 0x3A6C98 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM1_CH1_CTR_CNT 0x3A6C9C + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM2_CH0_CTR_CNT 0x3A6CA0 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM2_CH1_CTR_CNT 0x3A6CA4 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM3_CH0_CTR_CNT 0x3A6CA8 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM3_CH1_CTR_CNT 0x3A6CAC + +#define mmNIF_RTR_CTRL_2_NL_HBM_PC_SEL_0 0x3A6CB0 + +#define mmNIF_RTR_CTRL_2_NL_HBM_PC_SEL_1 0x3A6CB4 + +#define mmNIF_RTR_CTRL_2_NL_HBM_PC_SEL_2 0x3A6CB8 + +#define mmNIF_RTR_CTRL_2_NL_HBM_PC_SEL_3 0x3A6CBC + +#endif /* ASIC_REG_NIF_RTR_CTRL_2_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_3_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_3_regs.h new file mode 100644 index 000000000000..34fd47685edd --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_3_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIF_RTR_CTRL_3_REGS_H_ +#define ASIC_REG_NIF_RTR_CTRL_3_REGS_H_ + +/* + ***************************************** + * NIF_RTR_CTRL_3 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmNIF_RTR_CTRL_3_PERM_SEL 0x3B6108 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_0 0x3B6114 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_1 0x3B6118 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_2 0x3B611C + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_3 0x3B6120 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_4 0x3B6124 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_5 0x3B6128 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_6 0x3B612C + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_7 0x3B6130 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_8 0x3B6134 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_9 0x3B6138 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_10 0x3B613C + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_11 0x3B6140 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_12 0x3B6144 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_13 0x3B6148 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_14 0x3B614C + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_15 0x3B6150 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_16 0x3B6154 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_17 0x3B6158 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_18 0x3B615C + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_19 0x3B6160 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_20 0x3B6164 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_21 0x3B6168 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_22 0x3B616C + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_23 0x3B6170 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_24 0x3B6174 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_25 0x3B6178 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_26 0x3B617C + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_27 0x3B6180 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_0 0x3B6184 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_1 0x3B6188 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_2 0x3B618C + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_3 0x3B6190 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_4 0x3B6194 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_5 0x3B6198 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_6 0x3B619C + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_7 0x3B61A0 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_8 0x3B61A4 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_9 0x3B61A8 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_10 0x3B61AC + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_11 0x3B61B0 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_12 0x3B61B4 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_13 0x3B61B8 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_14 0x3B61BC + +#define mmNIF_RTR_CTRL_3_SCRAM_SRAM_EN 0x3B626C + +#define mmNIF_RTR_CTRL_3_RL_HBM_EN 0x3B6274 + +#define mmNIF_RTR_CTRL_3_RL_HBM_SAT 0x3B6278 + +#define mmNIF_RTR_CTRL_3_RL_HBM_RST 0x3B627C + +#define mmNIF_RTR_CTRL_3_RL_HBM_TIMEOUT 0x3B6280 + +#define mmNIF_RTR_CTRL_3_SCRAM_HBM_EN 0x3B6284 + +#define mmNIF_RTR_CTRL_3_RL_PCI_EN 0x3B6288 + +#define mmNIF_RTR_CTRL_3_RL_PCI_SAT 0x3B628C + +#define mmNIF_RTR_CTRL_3_RL_PCI_RST 0x3B6290 + +#define mmNIF_RTR_CTRL_3_RL_PCI_TIMEOUT 0x3B6294 + +#define mmNIF_RTR_CTRL_3_RL_SRAM_EN 0x3B629C + +#define mmNIF_RTR_CTRL_3_RL_SRAM_SAT 0x3B62A0 + +#define mmNIF_RTR_CTRL_3_RL_SRAM_RST 0x3B62A4 + +#define mmNIF_RTR_CTRL_3_RL_SRAM_TIMEOUT 0x3B62AC + +#define mmNIF_RTR_CTRL_3_RL_SRAM_RED 0x3B62B4 + +#define mmNIF_RTR_CTRL_3_E2E_HBM_EN 0x3B62EC + +#define mmNIF_RTR_CTRL_3_E2E_PCI_EN 0x3B62F0 + +#define mmNIF_RTR_CTRL_3_E2E_HBM_WR_SIZE 0x3B62F4 + +#define mmNIF_RTR_CTRL_3_E2E_PCI_WR_SIZE 0x3B62F8 + +#define mmNIF_RTR_CTRL_3_E2E_AW_PCI_CTR_SET_EN 0x3B6404 + +#define mmNIF_RTR_CTRL_3_E2E_AW_PCI_CTR_SET 0x3B6408 + +#define mmNIF_RTR_CTRL_3_E2E_AW_PCI_CTR_WRAP 0x3B640C + +#define mmNIF_RTR_CTRL_3_E2E_AW_PCI_CTR_CNT 0x3B6410 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM_CTR_SET_EN 0x3B6414 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM_CTR_SET 0x3B6418 + +#define mmNIF_RTR_CTRL_3_E2E_HBM_RD_SIZE 0x3B641C + +#define mmNIF_RTR_CTRL_3_E2E_PCI_RD_SIZE 0x3B6420 + +#define mmNIF_RTR_CTRL_3_E2E_AR_PCI_CTR_SET_EN 0x3B6424 + +#define mmNIF_RTR_CTRL_3_E2E_AR_PCI_CTR_SET 0x3B6428 + +#define mmNIF_RTR_CTRL_3_E2E_AR_PCI_CTR_WRAP 0x3B642C + +#define mmNIF_RTR_CTRL_3_E2E_AR_PCI_CTR_CNT 0x3B6430 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM_CTR_SET_EN 0x3B6434 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM_CTR_SET 0x3B6438 + +#define mmNIF_RTR_CTRL_3_NL_HBM_SEL_0 0x3B6450 + +#define mmNIF_RTR_CTRL_3_NL_HBM_SEL_1 0x3B6454 + +#define mmNIF_RTR_CTRL_3_NON_LIN_EN 0x3B6480 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_BANK_0 0x3B6500 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_BANK_1 0x3B6504 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_BANK_2 0x3B6508 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_BANK_3 0x3B650C + +#define mmNIF_RTR_CTRL_3_NL_SRAM_BANK_4 0x3B6510 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_0 0x3B6514 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_1 0x3B6520 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_2 0x3B6524 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_3 0x3B6528 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_4 0x3B652C + +#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_5 0x3B6530 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_6 0x3B6534 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_7 0x3B6538 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_8 0x3B653C + +#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_9 0x3B6540 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_0 0x3B6550 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_1 0x3B6554 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_2 0x3B6558 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_3 0x3B655C + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_4 0x3B6560 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_5 0x3B6564 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_6 0x3B6568 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_7 0x3B656C + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_8 0x3B6570 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_9 0x3B6574 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_10 0x3B6578 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_11 0x3B657C + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_12 0x3B6580 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_13 0x3B6584 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_14 0x3B6588 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_15 0x3B658C + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_16 0x3B6590 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_17 0x3B6594 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_18 0x3B6598 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_0 0x3B65E4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_1 0x3B65E8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_2 0x3B65EC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_3 0x3B65F0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_4 0x3B65F4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_5 0x3B65F8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_6 0x3B65FC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_7 0x3B6600 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_8 0x3B6604 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_9 0x3B6608 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_10 0x3B660C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_11 0x3B6610 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_12 0x3B6614 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_13 0x3B6618 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_14 0x3B661C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_15 0x3B6620 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_0 0x3B6624 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_1 0x3B6628 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_2 0x3B662C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_3 0x3B6630 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_4 0x3B6634 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_5 0x3B6638 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_6 0x3B663C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_7 0x3B6640 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_8 0x3B6644 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_9 0x3B6648 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_10 0x3B664C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_11 0x3B6650 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_12 0x3B6654 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_13 0x3B6658 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_14 0x3B665C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_15 0x3B6660 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_0 0x3B6664 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_1 0x3B6668 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_2 0x3B666C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_3 0x3B6670 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_4 0x3B6674 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_5 0x3B6678 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_6 0x3B667C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_7 0x3B6680 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_8 0x3B6684 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_9 0x3B6688 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_10 0x3B668C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_11 0x3B6690 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_12 0x3B6694 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_13 0x3B6698 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_14 0x3B669C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_15 0x3B66A0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_0 0x3B66A4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_1 0x3B66A8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_2 0x3B66AC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_3 0x3B66B0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_4 0x3B66B4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_5 0x3B66B8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_6 0x3B66BC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_7 0x3B66C0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_8 0x3B66C4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_9 0x3B66C8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_10 0x3B66CC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_11 0x3B66D0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_12 0x3B66D4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_13 0x3B66D8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_14 0x3B66DC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_15 0x3B66E0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_0 0x3B66E4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_1 0x3B66E8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_2 0x3B66EC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_3 0x3B66F0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_4 0x3B66F4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_5 0x3B66F8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_6 0x3B66FC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_7 0x3B6700 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_8 0x3B6704 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_9 0x3B6708 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_10 0x3B670C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_11 0x3B6710 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_12 0x3B6714 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_13 0x3B6718 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_14 0x3B671C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_15 0x3B6720 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_0 0x3B6724 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_1 0x3B6728 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_2 0x3B672C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_3 0x3B6730 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_4 0x3B6734 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_5 0x3B6738 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_6 0x3B673C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_7 0x3B6740 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_8 0x3B6744 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_9 0x3B6748 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_10 0x3B674C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_11 0x3B6750 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_12 0x3B6754 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_13 0x3B6758 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_14 0x3B675C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_15 0x3B6760 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_0 0x3B6764 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_1 0x3B6768 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_2 0x3B676C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_3 0x3B6770 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_4 0x3B6774 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_5 0x3B6778 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_6 0x3B677C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_7 0x3B6780 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_8 0x3B6784 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_9 0x3B6788 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_10 0x3B678C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_11 0x3B6790 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_12 0x3B6794 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_13 0x3B6798 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_14 0x3B679C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_15 0x3B67A0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_0 0x3B67A4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_1 0x3B67A8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_2 0x3B67AC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_3 0x3B67B0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_4 0x3B67B4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_5 0x3B67B8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_6 0x3B67BC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_7 0x3B67C0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_8 0x3B67C4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_9 0x3B67C8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_10 0x3B67CC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_11 0x3B67D0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_12 0x3B67D4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_13 0x3B67D8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_14 0x3B67DC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_15 0x3B67E0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_0 0x3B6824 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_1 0x3B6828 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_2 0x3B682C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_3 0x3B6830 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_4 0x3B6834 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_5 0x3B6838 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_6 0x3B683C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_7 0x3B6840 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_8 0x3B6844 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_9 0x3B6848 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_10 0x3B684C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_11 0x3B6850 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_12 0x3B6854 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_13 0x3B6858 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_14 0x3B685C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_15 0x3B6860 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_0 0x3B6864 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_1 0x3B6868 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_2 0x3B686C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_3 0x3B6870 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_4 0x3B6874 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_5 0x3B6878 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_6 0x3B687C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_7 0x3B6880 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_8 0x3B6884 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_9 0x3B6888 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_10 0x3B688C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_11 0x3B6890 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_12 0x3B6894 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_13 0x3B6898 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_14 0x3B689C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_15 0x3B68A0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_0 0x3B68A4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_1 0x3B68A8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_2 0x3B68AC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_3 0x3B68B0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_4 0x3B68B4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_5 0x3B68B8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_6 0x3B68BC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_7 0x3B68C0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_8 0x3B68C4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_9 0x3B68C8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_10 0x3B68CC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_11 0x3B68D0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_12 0x3B68D4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_13 0x3B68D8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_14 0x3B68DC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_15 0x3B68E0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_0 0x3B68E4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_1 0x3B68E8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_2 0x3B68EC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_3 0x3B68F0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_4 0x3B68F4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_5 0x3B68F8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_6 0x3B68FC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_7 0x3B6900 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_8 0x3B6904 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_9 0x3B6908 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_10 0x3B690C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_11 0x3B6910 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_12 0x3B6914 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_13 0x3B6918 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_14 0x3B691C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_15 0x3B6920 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_0 0x3B6924 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_1 0x3B6928 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_2 0x3B692C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_3 0x3B6930 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_4 0x3B6934 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_5 0x3B6938 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_6 0x3B693C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_7 0x3B6940 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_8 0x3B6944 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_9 0x3B6948 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_10 0x3B694C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_11 0x3B6950 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_12 0x3B6954 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_13 0x3B6958 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_14 0x3B695C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_15 0x3B6960 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_0 0x3B6964 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_1 0x3B6968 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_2 0x3B696C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_3 0x3B6970 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_4 0x3B6974 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_5 0x3B6978 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_6 0x3B697C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_7 0x3B6980 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_8 0x3B6984 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_9 0x3B6988 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_10 0x3B698C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_11 0x3B6990 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_12 0x3B6994 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_13 0x3B6998 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_14 0x3B699C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_15 0x3B69A0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_0 0x3B69A4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_1 0x3B69A8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_2 0x3B69AC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_3 0x3B69B0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_4 0x3B69B4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_5 0x3B69B8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_6 0x3B69BC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_7 0x3B69C0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_8 0x3B69C4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_9 0x3B69C8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_10 0x3B69CC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_11 0x3B69D0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_12 0x3B69D4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_13 0x3B69D8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_14 0x3B69DC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_15 0x3B69E0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_0 0x3B69E4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_1 0x3B69E8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_2 0x3B69EC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_3 0x3B69F0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_4 0x3B69F4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_5 0x3B69F8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_6 0x3B69FC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_7 0x3B6A00 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_8 0x3B6A04 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_9 0x3B6A08 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_10 0x3B6A0C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_11 0x3B6A10 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_12 0x3B6A14 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_13 0x3B6A18 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_14 0x3B6A1C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_15 0x3B6A20 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_HIT_AW 0x3B6A64 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_HIT_AR 0x3B6A68 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_HIT_AW 0x3B6A6C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_HIT_AR 0x3B6A70 + +#define mmNIF_RTR_CTRL_3_RGL_CFG 0x3B6B64 + +#define mmNIF_RTR_CTRL_3_RGL_SHIFT 0x3B6B68 + +#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_0 0x3B6B6C + +#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_1 0x3B6B70 + +#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_2 0x3B6B74 + +#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_3 0x3B6B78 + +#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_4 0x3B6B7C + +#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_5 0x3B6B80 + +#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_6 0x3B6B84 + +#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_7 0x3B6B88 + +#define mmNIF_RTR_CTRL_3_RGL_TOKEN_0 0x3B6BAC + +#define mmNIF_RTR_CTRL_3_RGL_TOKEN_1 0x3B6BB0 + +#define mmNIF_RTR_CTRL_3_RGL_TOKEN_2 0x3B6BB4 + +#define mmNIF_RTR_CTRL_3_RGL_TOKEN_3 0x3B6BB8 + +#define mmNIF_RTR_CTRL_3_RGL_TOKEN_4 0x3B6BBC + +#define mmNIF_RTR_CTRL_3_RGL_TOKEN_5 0x3B6BC0 + +#define mmNIF_RTR_CTRL_3_RGL_TOKEN_6 0x3B6BC4 + +#define mmNIF_RTR_CTRL_3_RGL_TOKEN_7 0x3B6BC8 + +#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_0 0x3B6BEC + +#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_1 0x3B6BF0 + +#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_2 0x3B6BF4 + +#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_3 0x3B6BF8 + +#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_4 0x3B6BFC + +#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_5 0x3B6C00 + +#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_6 0x3B6C04 + +#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_7 0x3B6C08 + +#define mmNIF_RTR_CTRL_3_RGL_WDT 0x3B6C2C + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM0_CH0_CTR_WRAP 0x3B6C30 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM0_CH1_CTR_WRAP 0x3B6C34 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM1_CH0_CTR_WRAP 0x3B6C38 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM1_CH1_CTR_WRAP 0x3B6C3C + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM2_CH0_CTR_WRAP 0x3B6C40 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM2_CH1_CTR_WRAP 0x3B6C44 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM3_CH0_CTR_WRAP 0x3B6C48 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM3_CH1_CTR_WRAP 0x3B6C4C + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM0_CH0_CTR_CNT 0x3B6C50 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM0_CH1_CTR_CNT 0x3B6C54 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM1_CH0_CTR_CNT 0x3B6C58 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM1_CH1_CTR_CNT 0x3B6C5C + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM2_CH0_CTR_CNT 0x3B6C60 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM2_CH1_CTR_CNT 0x3B6C64 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM3_CH0_CTR_CNT 0x3B6C68 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM3_CH1_CTR_CNT 0x3B6C6C + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM0_CH0_CTR_WRAP 0x3B6C70 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM0_CH1_CTR_WRAP 0x3B6C74 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM1_CH0_CTR_WRAP 0x3B6C78 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM1_CH1_CTR_WRAP 0x3B6C7C + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM2_CH0_CTR_WRAP 0x3B6C80 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM2_CH1_CTR_WRAP 0x3B6C84 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM3_CH0_CTR_WRAP 0x3B6C88 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM3_CH1_CTR_WRAP 0x3B6C8C + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM0_CH0_CTR_CNT 0x3B6C90 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM0_CH1_CTR_CNT 0x3B6C94 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM1_CH0_CTR_CNT 0x3B6C98 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM1_CH1_CTR_CNT 0x3B6C9C + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM2_CH0_CTR_CNT 0x3B6CA0 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM2_CH1_CTR_CNT 0x3B6CA4 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM3_CH0_CTR_CNT 0x3B6CA8 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM3_CH1_CTR_CNT 0x3B6CAC + +#define mmNIF_RTR_CTRL_3_NL_HBM_PC_SEL_0 0x3B6CB0 + +#define mmNIF_RTR_CTRL_3_NL_HBM_PC_SEL_1 0x3B6CB4 + +#define mmNIF_RTR_CTRL_3_NL_HBM_PC_SEL_2 0x3B6CB8 + +#define mmNIF_RTR_CTRL_3_NL_HBM_PC_SEL_3 0x3B6CBC + +#endif /* ASIC_REG_NIF_RTR_CTRL_3_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_4_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_4_regs.h new file mode 100644 index 000000000000..543a98f81767 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_4_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIF_RTR_CTRL_4_REGS_H_ +#define ASIC_REG_NIF_RTR_CTRL_4_REGS_H_ + +/* + ***************************************** + * NIF_RTR_CTRL_4 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmNIF_RTR_CTRL_4_PERM_SEL 0x3C6108 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_0 0x3C6114 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_1 0x3C6118 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_2 0x3C611C + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_3 0x3C6120 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_4 0x3C6124 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_5 0x3C6128 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_6 0x3C612C + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_7 0x3C6130 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_8 0x3C6134 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_9 0x3C6138 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_10 0x3C613C + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_11 0x3C6140 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_12 0x3C6144 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_13 0x3C6148 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_14 0x3C614C + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_15 0x3C6150 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_16 0x3C6154 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_17 0x3C6158 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_18 0x3C615C + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_19 0x3C6160 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_20 0x3C6164 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_21 0x3C6168 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_22 0x3C616C + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_23 0x3C6170 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_24 0x3C6174 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_25 0x3C6178 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_26 0x3C617C + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_27 0x3C6180 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_0 0x3C6184 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_1 0x3C6188 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_2 0x3C618C + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_3 0x3C6190 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_4 0x3C6194 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_5 0x3C6198 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_6 0x3C619C + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_7 0x3C61A0 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_8 0x3C61A4 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_9 0x3C61A8 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_10 0x3C61AC + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_11 0x3C61B0 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_12 0x3C61B4 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_13 0x3C61B8 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_14 0x3C61BC + +#define mmNIF_RTR_CTRL_4_SCRAM_SRAM_EN 0x3C626C + +#define mmNIF_RTR_CTRL_4_RL_HBM_EN 0x3C6274 + +#define mmNIF_RTR_CTRL_4_RL_HBM_SAT 0x3C6278 + +#define mmNIF_RTR_CTRL_4_RL_HBM_RST 0x3C627C + +#define mmNIF_RTR_CTRL_4_RL_HBM_TIMEOUT 0x3C6280 + +#define mmNIF_RTR_CTRL_4_SCRAM_HBM_EN 0x3C6284 + +#define mmNIF_RTR_CTRL_4_RL_PCI_EN 0x3C6288 + +#define mmNIF_RTR_CTRL_4_RL_PCI_SAT 0x3C628C + +#define mmNIF_RTR_CTRL_4_RL_PCI_RST 0x3C6290 + +#define mmNIF_RTR_CTRL_4_RL_PCI_TIMEOUT 0x3C6294 + +#define mmNIF_RTR_CTRL_4_RL_SRAM_EN 0x3C629C + +#define mmNIF_RTR_CTRL_4_RL_SRAM_SAT 0x3C62A0 + +#define mmNIF_RTR_CTRL_4_RL_SRAM_RST 0x3C62A4 + +#define mmNIF_RTR_CTRL_4_RL_SRAM_TIMEOUT 0x3C62AC + +#define mmNIF_RTR_CTRL_4_RL_SRAM_RED 0x3C62B4 + +#define mmNIF_RTR_CTRL_4_E2E_HBM_EN 0x3C62EC + +#define mmNIF_RTR_CTRL_4_E2E_PCI_EN 0x3C62F0 + +#define mmNIF_RTR_CTRL_4_E2E_HBM_WR_SIZE 0x3C62F4 + +#define mmNIF_RTR_CTRL_4_E2E_PCI_WR_SIZE 0x3C62F8 + +#define mmNIF_RTR_CTRL_4_E2E_AW_PCI_CTR_SET_EN 0x3C6404 + +#define mmNIF_RTR_CTRL_4_E2E_AW_PCI_CTR_SET 0x3C6408 + +#define mmNIF_RTR_CTRL_4_E2E_AW_PCI_CTR_WRAP 0x3C640C + +#define mmNIF_RTR_CTRL_4_E2E_AW_PCI_CTR_CNT 0x3C6410 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM_CTR_SET_EN 0x3C6414 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM_CTR_SET 0x3C6418 + +#define mmNIF_RTR_CTRL_4_E2E_HBM_RD_SIZE 0x3C641C + +#define mmNIF_RTR_CTRL_4_E2E_PCI_RD_SIZE 0x3C6420 + +#define mmNIF_RTR_CTRL_4_E2E_AR_PCI_CTR_SET_EN 0x3C6424 + +#define mmNIF_RTR_CTRL_4_E2E_AR_PCI_CTR_SET 0x3C6428 + +#define mmNIF_RTR_CTRL_4_E2E_AR_PCI_CTR_WRAP 0x3C642C + +#define mmNIF_RTR_CTRL_4_E2E_AR_PCI_CTR_CNT 0x3C6430 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM_CTR_SET_EN 0x3C6434 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM_CTR_SET 0x3C6438 + +#define mmNIF_RTR_CTRL_4_NL_HBM_SEL_0 0x3C6450 + +#define mmNIF_RTR_CTRL_4_NL_HBM_SEL_1 0x3C6454 + +#define mmNIF_RTR_CTRL_4_NON_LIN_EN 0x3C6480 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_BANK_0 0x3C6500 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_BANK_1 0x3C6504 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_BANK_2 0x3C6508 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_BANK_3 0x3C650C + +#define mmNIF_RTR_CTRL_4_NL_SRAM_BANK_4 0x3C6510 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_0 0x3C6514 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_1 0x3C6520 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_2 0x3C6524 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_3 0x3C6528 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_4 0x3C652C + +#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_5 0x3C6530 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_6 0x3C6534 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_7 0x3C6538 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_8 0x3C653C + +#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_9 0x3C6540 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_0 0x3C6550 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_1 0x3C6554 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_2 0x3C6558 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_3 0x3C655C + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_4 0x3C6560 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_5 0x3C6564 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_6 0x3C6568 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_7 0x3C656C + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_8 0x3C6570 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_9 0x3C6574 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_10 0x3C6578 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_11 0x3C657C + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_12 0x3C6580 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_13 0x3C6584 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_14 0x3C6588 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_15 0x3C658C + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_16 0x3C6590 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_17 0x3C6594 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_18 0x3C6598 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_0 0x3C65E4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_1 0x3C65E8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_2 0x3C65EC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_3 0x3C65F0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_4 0x3C65F4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_5 0x3C65F8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_6 0x3C65FC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_7 0x3C6600 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_8 0x3C6604 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_9 0x3C6608 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_10 0x3C660C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_11 0x3C6610 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_12 0x3C6614 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_13 0x3C6618 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_14 0x3C661C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_15 0x3C6620 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_0 0x3C6624 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_1 0x3C6628 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_2 0x3C662C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_3 0x3C6630 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_4 0x3C6634 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_5 0x3C6638 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_6 0x3C663C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_7 0x3C6640 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_8 0x3C6644 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_9 0x3C6648 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_10 0x3C664C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_11 0x3C6650 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_12 0x3C6654 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_13 0x3C6658 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_14 0x3C665C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_15 0x3C6660 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_0 0x3C6664 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_1 0x3C6668 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_2 0x3C666C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_3 0x3C6670 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_4 0x3C6674 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_5 0x3C6678 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_6 0x3C667C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_7 0x3C6680 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_8 0x3C6684 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_9 0x3C6688 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_10 0x3C668C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_11 0x3C6690 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_12 0x3C6694 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_13 0x3C6698 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_14 0x3C669C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_15 0x3C66A0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_0 0x3C66A4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_1 0x3C66A8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_2 0x3C66AC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_3 0x3C66B0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_4 0x3C66B4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_5 0x3C66B8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_6 0x3C66BC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_7 0x3C66C0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_8 0x3C66C4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_9 0x3C66C8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_10 0x3C66CC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_11 0x3C66D0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_12 0x3C66D4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_13 0x3C66D8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_14 0x3C66DC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_15 0x3C66E0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_0 0x3C66E4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_1 0x3C66E8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_2 0x3C66EC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_3 0x3C66F0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_4 0x3C66F4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_5 0x3C66F8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_6 0x3C66FC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_7 0x3C6700 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_8 0x3C6704 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_9 0x3C6708 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_10 0x3C670C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_11 0x3C6710 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_12 0x3C6714 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_13 0x3C6718 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_14 0x3C671C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_15 0x3C6720 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_0 0x3C6724 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_1 0x3C6728 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_2 0x3C672C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_3 0x3C6730 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_4 0x3C6734 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_5 0x3C6738 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_6 0x3C673C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_7 0x3C6740 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_8 0x3C6744 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_9 0x3C6748 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_10 0x3C674C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_11 0x3C6750 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_12 0x3C6754 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_13 0x3C6758 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_14 0x3C675C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_15 0x3C6760 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_0 0x3C6764 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_1 0x3C6768 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_2 0x3C676C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_3 0x3C6770 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_4 0x3C6774 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_5 0x3C6778 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_6 0x3C677C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_7 0x3C6780 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_8 0x3C6784 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_9 0x3C6788 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_10 0x3C678C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_11 0x3C6790 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_12 0x3C6794 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_13 0x3C6798 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_14 0x3C679C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_15 0x3C67A0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_0 0x3C67A4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_1 0x3C67A8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_2 0x3C67AC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_3 0x3C67B0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_4 0x3C67B4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_5 0x3C67B8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_6 0x3C67BC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_7 0x3C67C0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_8 0x3C67C4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_9 0x3C67C8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_10 0x3C67CC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_11 0x3C67D0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_12 0x3C67D4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_13 0x3C67D8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_14 0x3C67DC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_15 0x3C67E0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_0 0x3C6824 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_1 0x3C6828 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_2 0x3C682C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_3 0x3C6830 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_4 0x3C6834 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_5 0x3C6838 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_6 0x3C683C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_7 0x3C6840 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_8 0x3C6844 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_9 0x3C6848 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_10 0x3C684C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_11 0x3C6850 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_12 0x3C6854 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_13 0x3C6858 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_14 0x3C685C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_15 0x3C6860 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_0 0x3C6864 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_1 0x3C6868 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_2 0x3C686C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_3 0x3C6870 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_4 0x3C6874 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_5 0x3C6878 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_6 0x3C687C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_7 0x3C6880 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_8 0x3C6884 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_9 0x3C6888 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_10 0x3C688C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_11 0x3C6890 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_12 0x3C6894 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_13 0x3C6898 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_14 0x3C689C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_15 0x3C68A0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_0 0x3C68A4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_1 0x3C68A8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_2 0x3C68AC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_3 0x3C68B0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_4 0x3C68B4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_5 0x3C68B8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_6 0x3C68BC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_7 0x3C68C0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_8 0x3C68C4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_9 0x3C68C8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_10 0x3C68CC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_11 0x3C68D0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_12 0x3C68D4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_13 0x3C68D8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_14 0x3C68DC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_15 0x3C68E0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_0 0x3C68E4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_1 0x3C68E8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_2 0x3C68EC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_3 0x3C68F0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_4 0x3C68F4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_5 0x3C68F8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_6 0x3C68FC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_7 0x3C6900 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_8 0x3C6904 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_9 0x3C6908 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_10 0x3C690C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_11 0x3C6910 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_12 0x3C6914 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_13 0x3C6918 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_14 0x3C691C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_15 0x3C6920 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_0 0x3C6924 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_1 0x3C6928 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_2 0x3C692C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_3 0x3C6930 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_4 0x3C6934 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_5 0x3C6938 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_6 0x3C693C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_7 0x3C6940 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_8 0x3C6944 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_9 0x3C6948 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_10 0x3C694C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_11 0x3C6950 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_12 0x3C6954 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_13 0x3C6958 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_14 0x3C695C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_15 0x3C6960 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_0 0x3C6964 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_1 0x3C6968 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_2 0x3C696C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_3 0x3C6970 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_4 0x3C6974 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_5 0x3C6978 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_6 0x3C697C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_7 0x3C6980 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_8 0x3C6984 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_9 0x3C6988 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_10 0x3C698C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_11 0x3C6990 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_12 0x3C6994 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_13 0x3C6998 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_14 0x3C699C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_15 0x3C69A0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_0 0x3C69A4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_1 0x3C69A8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_2 0x3C69AC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_3 0x3C69B0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_4 0x3C69B4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_5 0x3C69B8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_6 0x3C69BC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_7 0x3C69C0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_8 0x3C69C4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_9 0x3C69C8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_10 0x3C69CC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_11 0x3C69D0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_12 0x3C69D4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_13 0x3C69D8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_14 0x3C69DC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_15 0x3C69E0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_0 0x3C69E4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_1 0x3C69E8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_2 0x3C69EC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_3 0x3C69F0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_4 0x3C69F4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_5 0x3C69F8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_6 0x3C69FC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_7 0x3C6A00 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_8 0x3C6A04 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_9 0x3C6A08 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_10 0x3C6A0C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_11 0x3C6A10 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_12 0x3C6A14 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_13 0x3C6A18 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_14 0x3C6A1C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_15 0x3C6A20 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_HIT_AW 0x3C6A64 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_HIT_AR 0x3C6A68 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_HIT_AW 0x3C6A6C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_HIT_AR 0x3C6A70 + +#define mmNIF_RTR_CTRL_4_RGL_CFG 0x3C6B64 + +#define mmNIF_RTR_CTRL_4_RGL_SHIFT 0x3C6B68 + +#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_0 0x3C6B6C + +#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_1 0x3C6B70 + +#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_2 0x3C6B74 + +#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_3 0x3C6B78 + +#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_4 0x3C6B7C + +#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_5 0x3C6B80 + +#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_6 0x3C6B84 + +#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_7 0x3C6B88 + +#define mmNIF_RTR_CTRL_4_RGL_TOKEN_0 0x3C6BAC + +#define mmNIF_RTR_CTRL_4_RGL_TOKEN_1 0x3C6BB0 + +#define mmNIF_RTR_CTRL_4_RGL_TOKEN_2 0x3C6BB4 + +#define mmNIF_RTR_CTRL_4_RGL_TOKEN_3 0x3C6BB8 + +#define mmNIF_RTR_CTRL_4_RGL_TOKEN_4 0x3C6BBC + +#define mmNIF_RTR_CTRL_4_RGL_TOKEN_5 0x3C6BC0 + +#define mmNIF_RTR_CTRL_4_RGL_TOKEN_6 0x3C6BC4 + +#define mmNIF_RTR_CTRL_4_RGL_TOKEN_7 0x3C6BC8 + +#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_0 0x3C6BEC + +#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_1 0x3C6BF0 + +#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_2 0x3C6BF4 + +#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_3 0x3C6BF8 + +#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_4 0x3C6BFC + +#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_5 0x3C6C00 + +#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_6 0x3C6C04 + +#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_7 0x3C6C08 + +#define mmNIF_RTR_CTRL_4_RGL_WDT 0x3C6C2C + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM0_CH0_CTR_WRAP 0x3C6C30 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM0_CH1_CTR_WRAP 0x3C6C34 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM1_CH0_CTR_WRAP 0x3C6C38 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM1_CH1_CTR_WRAP 0x3C6C3C + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM2_CH0_CTR_WRAP 0x3C6C40 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM2_CH1_CTR_WRAP 0x3C6C44 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM3_CH0_CTR_WRAP 0x3C6C48 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM3_CH1_CTR_WRAP 0x3C6C4C + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM0_CH0_CTR_CNT 0x3C6C50 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM0_CH1_CTR_CNT 0x3C6C54 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM1_CH0_CTR_CNT 0x3C6C58 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM1_CH1_CTR_CNT 0x3C6C5C + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM2_CH0_CTR_CNT 0x3C6C60 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM2_CH1_CTR_CNT 0x3C6C64 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM3_CH0_CTR_CNT 0x3C6C68 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM3_CH1_CTR_CNT 0x3C6C6C + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM0_CH0_CTR_WRAP 0x3C6C70 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM0_CH1_CTR_WRAP 0x3C6C74 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM1_CH0_CTR_WRAP 0x3C6C78 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM1_CH1_CTR_WRAP 0x3C6C7C + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM2_CH0_CTR_WRAP 0x3C6C80 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM2_CH1_CTR_WRAP 0x3C6C84 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM3_CH0_CTR_WRAP 0x3C6C88 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM3_CH1_CTR_WRAP 0x3C6C8C + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM0_CH0_CTR_CNT 0x3C6C90 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM0_CH1_CTR_CNT 0x3C6C94 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM1_CH0_CTR_CNT 0x3C6C98 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM1_CH1_CTR_CNT 0x3C6C9C + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM2_CH0_CTR_CNT 0x3C6CA0 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM2_CH1_CTR_CNT 0x3C6CA4 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM3_CH0_CTR_CNT 0x3C6CA8 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM3_CH1_CTR_CNT 0x3C6CAC + +#define mmNIF_RTR_CTRL_4_NL_HBM_PC_SEL_0 0x3C6CB0 + +#define mmNIF_RTR_CTRL_4_NL_HBM_PC_SEL_1 0x3C6CB4 + +#define mmNIF_RTR_CTRL_4_NL_HBM_PC_SEL_2 0x3C6CB8 + +#define mmNIF_RTR_CTRL_4_NL_HBM_PC_SEL_3 0x3C6CBC + +#endif /* ASIC_REG_NIF_RTR_CTRL_4_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_5_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_5_regs.h new file mode 100644 index 000000000000..95486b7ddf1d --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_5_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIF_RTR_CTRL_5_REGS_H_ +#define ASIC_REG_NIF_RTR_CTRL_5_REGS_H_ + +/* + ***************************************** + * NIF_RTR_CTRL_5 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmNIF_RTR_CTRL_5_PERM_SEL 0x3D6108 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_0 0x3D6114 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_1 0x3D6118 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_2 0x3D611C + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_3 0x3D6120 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_4 0x3D6124 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_5 0x3D6128 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_6 0x3D612C + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_7 0x3D6130 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_8 0x3D6134 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_9 0x3D6138 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_10 0x3D613C + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_11 0x3D6140 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_12 0x3D6144 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_13 0x3D6148 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_14 0x3D614C + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_15 0x3D6150 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_16 0x3D6154 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_17 0x3D6158 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_18 0x3D615C + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_19 0x3D6160 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_20 0x3D6164 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_21 0x3D6168 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_22 0x3D616C + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_23 0x3D6170 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_24 0x3D6174 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_25 0x3D6178 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_26 0x3D617C + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_27 0x3D6180 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_0 0x3D6184 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_1 0x3D6188 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_2 0x3D618C + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_3 0x3D6190 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_4 0x3D6194 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_5 0x3D6198 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_6 0x3D619C + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_7 0x3D61A0 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_8 0x3D61A4 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_9 0x3D61A8 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_10 0x3D61AC + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_11 0x3D61B0 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_12 0x3D61B4 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_13 0x3D61B8 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_14 0x3D61BC + +#define mmNIF_RTR_CTRL_5_SCRAM_SRAM_EN 0x3D626C + +#define mmNIF_RTR_CTRL_5_RL_HBM_EN 0x3D6274 + +#define mmNIF_RTR_CTRL_5_RL_HBM_SAT 0x3D6278 + +#define mmNIF_RTR_CTRL_5_RL_HBM_RST 0x3D627C + +#define mmNIF_RTR_CTRL_5_RL_HBM_TIMEOUT 0x3D6280 + +#define mmNIF_RTR_CTRL_5_SCRAM_HBM_EN 0x3D6284 + +#define mmNIF_RTR_CTRL_5_RL_PCI_EN 0x3D6288 + +#define mmNIF_RTR_CTRL_5_RL_PCI_SAT 0x3D628C + +#define mmNIF_RTR_CTRL_5_RL_PCI_RST 0x3D6290 + +#define mmNIF_RTR_CTRL_5_RL_PCI_TIMEOUT 0x3D6294 + +#define mmNIF_RTR_CTRL_5_RL_SRAM_EN 0x3D629C + +#define mmNIF_RTR_CTRL_5_RL_SRAM_SAT 0x3D62A0 + +#define mmNIF_RTR_CTRL_5_RL_SRAM_RST 0x3D62A4 + +#define mmNIF_RTR_CTRL_5_RL_SRAM_TIMEOUT 0x3D62AC + +#define mmNIF_RTR_CTRL_5_RL_SRAM_RED 0x3D62B4 + +#define mmNIF_RTR_CTRL_5_E2E_HBM_EN 0x3D62EC + +#define mmNIF_RTR_CTRL_5_E2E_PCI_EN 0x3D62F0 + +#define mmNIF_RTR_CTRL_5_E2E_HBM_WR_SIZE 0x3D62F4 + +#define mmNIF_RTR_CTRL_5_E2E_PCI_WR_SIZE 0x3D62F8 + +#define mmNIF_RTR_CTRL_5_E2E_AW_PCI_CTR_SET_EN 0x3D6404 + +#define mmNIF_RTR_CTRL_5_E2E_AW_PCI_CTR_SET 0x3D6408 + +#define mmNIF_RTR_CTRL_5_E2E_AW_PCI_CTR_WRAP 0x3D640C + +#define mmNIF_RTR_CTRL_5_E2E_AW_PCI_CTR_CNT 0x3D6410 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM_CTR_SET_EN 0x3D6414 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM_CTR_SET 0x3D6418 + +#define mmNIF_RTR_CTRL_5_E2E_HBM_RD_SIZE 0x3D641C + +#define mmNIF_RTR_CTRL_5_E2E_PCI_RD_SIZE 0x3D6420 + +#define mmNIF_RTR_CTRL_5_E2E_AR_PCI_CTR_SET_EN 0x3D6424 + +#define mmNIF_RTR_CTRL_5_E2E_AR_PCI_CTR_SET 0x3D6428 + +#define mmNIF_RTR_CTRL_5_E2E_AR_PCI_CTR_WRAP 0x3D642C + +#define mmNIF_RTR_CTRL_5_E2E_AR_PCI_CTR_CNT 0x3D6430 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM_CTR_SET_EN 0x3D6434 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM_CTR_SET 0x3D6438 + +#define mmNIF_RTR_CTRL_5_NL_HBM_SEL_0 0x3D6450 + +#define mmNIF_RTR_CTRL_5_NL_HBM_SEL_1 0x3D6454 + +#define mmNIF_RTR_CTRL_5_NON_LIN_EN 0x3D6480 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_BANK_0 0x3D6500 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_BANK_1 0x3D6504 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_BANK_2 0x3D6508 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_BANK_3 0x3D650C + +#define mmNIF_RTR_CTRL_5_NL_SRAM_BANK_4 0x3D6510 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_0 0x3D6514 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_1 0x3D6520 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_2 0x3D6524 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_3 0x3D6528 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_4 0x3D652C + +#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_5 0x3D6530 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_6 0x3D6534 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_7 0x3D6538 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_8 0x3D653C + +#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_9 0x3D6540 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_0 0x3D6550 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_1 0x3D6554 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_2 0x3D6558 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_3 0x3D655C + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_4 0x3D6560 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_5 0x3D6564 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_6 0x3D6568 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_7 0x3D656C + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_8 0x3D6570 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_9 0x3D6574 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_10 0x3D6578 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_11 0x3D657C + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_12 0x3D6580 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_13 0x3D6584 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_14 0x3D6588 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_15 0x3D658C + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_16 0x3D6590 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_17 0x3D6594 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_18 0x3D6598 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_0 0x3D65E4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_1 0x3D65E8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_2 0x3D65EC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_3 0x3D65F0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_4 0x3D65F4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_5 0x3D65F8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_6 0x3D65FC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_7 0x3D6600 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_8 0x3D6604 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_9 0x3D6608 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_10 0x3D660C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_11 0x3D6610 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_12 0x3D6614 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_13 0x3D6618 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_14 0x3D661C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_15 0x3D6620 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_0 0x3D6624 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_1 0x3D6628 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_2 0x3D662C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_3 0x3D6630 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_4 0x3D6634 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_5 0x3D6638 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_6 0x3D663C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_7 0x3D6640 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_8 0x3D6644 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_9 0x3D6648 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_10 0x3D664C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_11 0x3D6650 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_12 0x3D6654 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_13 0x3D6658 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_14 0x3D665C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_15 0x3D6660 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_0 0x3D6664 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_1 0x3D6668 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_2 0x3D666C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_3 0x3D6670 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_4 0x3D6674 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_5 0x3D6678 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_6 0x3D667C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_7 0x3D6680 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_8 0x3D6684 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_9 0x3D6688 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_10 0x3D668C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_11 0x3D6690 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_12 0x3D6694 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_13 0x3D6698 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_14 0x3D669C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_15 0x3D66A0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_0 0x3D66A4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_1 0x3D66A8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_2 0x3D66AC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_3 0x3D66B0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_4 0x3D66B4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_5 0x3D66B8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_6 0x3D66BC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_7 0x3D66C0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_8 0x3D66C4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_9 0x3D66C8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_10 0x3D66CC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_11 0x3D66D0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_12 0x3D66D4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_13 0x3D66D8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_14 0x3D66DC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_15 0x3D66E0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_0 0x3D66E4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_1 0x3D66E8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_2 0x3D66EC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_3 0x3D66F0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_4 0x3D66F4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_5 0x3D66F8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_6 0x3D66FC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_7 0x3D6700 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_8 0x3D6704 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_9 0x3D6708 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_10 0x3D670C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_11 0x3D6710 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_12 0x3D6714 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_13 0x3D6718 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_14 0x3D671C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_15 0x3D6720 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_0 0x3D6724 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_1 0x3D6728 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_2 0x3D672C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_3 0x3D6730 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_4 0x3D6734 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_5 0x3D6738 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_6 0x3D673C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_7 0x3D6740 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_8 0x3D6744 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_9 0x3D6748 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_10 0x3D674C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_11 0x3D6750 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_12 0x3D6754 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_13 0x3D6758 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_14 0x3D675C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_15 0x3D6760 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_0 0x3D6764 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_1 0x3D6768 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_2 0x3D676C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_3 0x3D6770 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_4 0x3D6774 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_5 0x3D6778 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_6 0x3D677C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_7 0x3D6780 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_8 0x3D6784 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_9 0x3D6788 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_10 0x3D678C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_11 0x3D6790 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_12 0x3D6794 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_13 0x3D6798 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_14 0x3D679C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_15 0x3D67A0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_0 0x3D67A4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_1 0x3D67A8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_2 0x3D67AC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_3 0x3D67B0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_4 0x3D67B4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_5 0x3D67B8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_6 0x3D67BC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_7 0x3D67C0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_8 0x3D67C4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_9 0x3D67C8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_10 0x3D67CC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_11 0x3D67D0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_12 0x3D67D4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_13 0x3D67D8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_14 0x3D67DC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_15 0x3D67E0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_0 0x3D6824 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_1 0x3D6828 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_2 0x3D682C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_3 0x3D6830 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_4 0x3D6834 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_5 0x3D6838 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_6 0x3D683C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_7 0x3D6840 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_8 0x3D6844 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_9 0x3D6848 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_10 0x3D684C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_11 0x3D6850 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_12 0x3D6854 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_13 0x3D6858 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_14 0x3D685C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_15 0x3D6860 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_0 0x3D6864 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_1 0x3D6868 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_2 0x3D686C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_3 0x3D6870 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_4 0x3D6874 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_5 0x3D6878 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_6 0x3D687C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_7 0x3D6880 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_8 0x3D6884 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_9 0x3D6888 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_10 0x3D688C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_11 0x3D6890 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_12 0x3D6894 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_13 0x3D6898 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_14 0x3D689C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_15 0x3D68A0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_0 0x3D68A4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_1 0x3D68A8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_2 0x3D68AC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_3 0x3D68B0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_4 0x3D68B4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_5 0x3D68B8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_6 0x3D68BC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_7 0x3D68C0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_8 0x3D68C4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_9 0x3D68C8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_10 0x3D68CC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_11 0x3D68D0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_12 0x3D68D4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_13 0x3D68D8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_14 0x3D68DC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_15 0x3D68E0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_0 0x3D68E4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_1 0x3D68E8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_2 0x3D68EC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_3 0x3D68F0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_4 0x3D68F4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_5 0x3D68F8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_6 0x3D68FC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_7 0x3D6900 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_8 0x3D6904 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_9 0x3D6908 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_10 0x3D690C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_11 0x3D6910 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_12 0x3D6914 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_13 0x3D6918 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_14 0x3D691C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_15 0x3D6920 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_0 0x3D6924 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_1 0x3D6928 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_2 0x3D692C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_3 0x3D6930 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_4 0x3D6934 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_5 0x3D6938 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_6 0x3D693C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_7 0x3D6940 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_8 0x3D6944 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_9 0x3D6948 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_10 0x3D694C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_11 0x3D6950 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_12 0x3D6954 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_13 0x3D6958 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_14 0x3D695C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_15 0x3D6960 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_0 0x3D6964 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_1 0x3D6968 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_2 0x3D696C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_3 0x3D6970 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_4 0x3D6974 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_5 0x3D6978 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_6 0x3D697C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_7 0x3D6980 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_8 0x3D6984 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_9 0x3D6988 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_10 0x3D698C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_11 0x3D6990 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_12 0x3D6994 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_13 0x3D6998 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_14 0x3D699C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_15 0x3D69A0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_0 0x3D69A4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_1 0x3D69A8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_2 0x3D69AC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_3 0x3D69B0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_4 0x3D69B4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_5 0x3D69B8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_6 0x3D69BC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_7 0x3D69C0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_8 0x3D69C4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_9 0x3D69C8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_10 0x3D69CC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_11 0x3D69D0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_12 0x3D69D4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_13 0x3D69D8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_14 0x3D69DC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_15 0x3D69E0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_0 0x3D69E4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_1 0x3D69E8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_2 0x3D69EC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_3 0x3D69F0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_4 0x3D69F4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_5 0x3D69F8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_6 0x3D69FC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_7 0x3D6A00 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_8 0x3D6A04 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_9 0x3D6A08 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_10 0x3D6A0C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_11 0x3D6A10 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_12 0x3D6A14 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_13 0x3D6A18 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_14 0x3D6A1C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_15 0x3D6A20 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_HIT_AW 0x3D6A64 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_HIT_AR 0x3D6A68 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_HIT_AW 0x3D6A6C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_HIT_AR 0x3D6A70 + +#define mmNIF_RTR_CTRL_5_RGL_CFG 0x3D6B64 + +#define mmNIF_RTR_CTRL_5_RGL_SHIFT 0x3D6B68 + +#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_0 0x3D6B6C + +#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_1 0x3D6B70 + +#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_2 0x3D6B74 + +#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_3 0x3D6B78 + +#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_4 0x3D6B7C + +#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_5 0x3D6B80 + +#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_6 0x3D6B84 + +#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_7 0x3D6B88 + +#define mmNIF_RTR_CTRL_5_RGL_TOKEN_0 0x3D6BAC + +#define mmNIF_RTR_CTRL_5_RGL_TOKEN_1 0x3D6BB0 + +#define mmNIF_RTR_CTRL_5_RGL_TOKEN_2 0x3D6BB4 + +#define mmNIF_RTR_CTRL_5_RGL_TOKEN_3 0x3D6BB8 + +#define mmNIF_RTR_CTRL_5_RGL_TOKEN_4 0x3D6BBC + +#define mmNIF_RTR_CTRL_5_RGL_TOKEN_5 0x3D6BC0 + +#define mmNIF_RTR_CTRL_5_RGL_TOKEN_6 0x3D6BC4 + +#define mmNIF_RTR_CTRL_5_RGL_TOKEN_7 0x3D6BC8 + +#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_0 0x3D6BEC + +#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_1 0x3D6BF0 + +#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_2 0x3D6BF4 + +#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_3 0x3D6BF8 + +#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_4 0x3D6BFC + +#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_5 0x3D6C00 + +#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_6 0x3D6C04 + +#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_7 0x3D6C08 + +#define mmNIF_RTR_CTRL_5_RGL_WDT 0x3D6C2C + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM0_CH0_CTR_WRAP 0x3D6C30 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM0_CH1_CTR_WRAP 0x3D6C34 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM1_CH0_CTR_WRAP 0x3D6C38 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM1_CH1_CTR_WRAP 0x3D6C3C + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM2_CH0_CTR_WRAP 0x3D6C40 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM2_CH1_CTR_WRAP 0x3D6C44 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM3_CH0_CTR_WRAP 0x3D6C48 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM3_CH1_CTR_WRAP 0x3D6C4C + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM0_CH0_CTR_CNT 0x3D6C50 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM0_CH1_CTR_CNT 0x3D6C54 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM1_CH0_CTR_CNT 0x3D6C58 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM1_CH1_CTR_CNT 0x3D6C5C + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM2_CH0_CTR_CNT 0x3D6C60 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM2_CH1_CTR_CNT 0x3D6C64 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM3_CH0_CTR_CNT 0x3D6C68 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM3_CH1_CTR_CNT 0x3D6C6C + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM0_CH0_CTR_WRAP 0x3D6C70 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM0_CH1_CTR_WRAP 0x3D6C74 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM1_CH0_CTR_WRAP 0x3D6C78 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM1_CH1_CTR_WRAP 0x3D6C7C + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM2_CH0_CTR_WRAP 0x3D6C80 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM2_CH1_CTR_WRAP 0x3D6C84 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM3_CH0_CTR_WRAP 0x3D6C88 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM3_CH1_CTR_WRAP 0x3D6C8C + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM0_CH0_CTR_CNT 0x3D6C90 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM0_CH1_CTR_CNT 0x3D6C94 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM1_CH0_CTR_CNT 0x3D6C98 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM1_CH1_CTR_CNT 0x3D6C9C + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM2_CH0_CTR_CNT 0x3D6CA0 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM2_CH1_CTR_CNT 0x3D6CA4 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM3_CH0_CTR_CNT 0x3D6CA8 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM3_CH1_CTR_CNT 0x3D6CAC + +#define mmNIF_RTR_CTRL_5_NL_HBM_PC_SEL_0 0x3D6CB0 + +#define mmNIF_RTR_CTRL_5_NL_HBM_PC_SEL_1 0x3D6CB4 + +#define mmNIF_RTR_CTRL_5_NL_HBM_PC_SEL_2 0x3D6CB8 + +#define mmNIF_RTR_CTRL_5_NL_HBM_PC_SEL_3 0x3D6CBC + +#endif /* ASIC_REG_NIF_RTR_CTRL_5_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_6_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_6_regs.h new file mode 100644 index 000000000000..b79c59887b21 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_6_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIF_RTR_CTRL_6_REGS_H_ +#define ASIC_REG_NIF_RTR_CTRL_6_REGS_H_ + +/* + ***************************************** + * NIF_RTR_CTRL_6 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmNIF_RTR_CTRL_6_PERM_SEL 0x3E6108 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_0 0x3E6114 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_1 0x3E6118 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_2 0x3E611C + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_3 0x3E6120 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_4 0x3E6124 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_5 0x3E6128 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_6 0x3E612C + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_7 0x3E6130 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_8 0x3E6134 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_9 0x3E6138 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_10 0x3E613C + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_11 0x3E6140 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_12 0x3E6144 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_13 0x3E6148 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_14 0x3E614C + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_15 0x3E6150 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_16 0x3E6154 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_17 0x3E6158 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_18 0x3E615C + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_19 0x3E6160 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_20 0x3E6164 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_21 0x3E6168 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_22 0x3E616C + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_23 0x3E6170 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_24 0x3E6174 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_25 0x3E6178 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_26 0x3E617C + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_27 0x3E6180 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_0 0x3E6184 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_1 0x3E6188 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_2 0x3E618C + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_3 0x3E6190 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_4 0x3E6194 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_5 0x3E6198 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_6 0x3E619C + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_7 0x3E61A0 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_8 0x3E61A4 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_9 0x3E61A8 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_10 0x3E61AC + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_11 0x3E61B0 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_12 0x3E61B4 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_13 0x3E61B8 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_14 0x3E61BC + +#define mmNIF_RTR_CTRL_6_SCRAM_SRAM_EN 0x3E626C + +#define mmNIF_RTR_CTRL_6_RL_HBM_EN 0x3E6274 + +#define mmNIF_RTR_CTRL_6_RL_HBM_SAT 0x3E6278 + +#define mmNIF_RTR_CTRL_6_RL_HBM_RST 0x3E627C + +#define mmNIF_RTR_CTRL_6_RL_HBM_TIMEOUT 0x3E6280 + +#define mmNIF_RTR_CTRL_6_SCRAM_HBM_EN 0x3E6284 + +#define mmNIF_RTR_CTRL_6_RL_PCI_EN 0x3E6288 + +#define mmNIF_RTR_CTRL_6_RL_PCI_SAT 0x3E628C + +#define mmNIF_RTR_CTRL_6_RL_PCI_RST 0x3E6290 + +#define mmNIF_RTR_CTRL_6_RL_PCI_TIMEOUT 0x3E6294 + +#define mmNIF_RTR_CTRL_6_RL_SRAM_EN 0x3E629C + +#define mmNIF_RTR_CTRL_6_RL_SRAM_SAT 0x3E62A0 + +#define mmNIF_RTR_CTRL_6_RL_SRAM_RST 0x3E62A4 + +#define mmNIF_RTR_CTRL_6_RL_SRAM_TIMEOUT 0x3E62AC + +#define mmNIF_RTR_CTRL_6_RL_SRAM_RED 0x3E62B4 + +#define mmNIF_RTR_CTRL_6_E2E_HBM_EN 0x3E62EC + +#define mmNIF_RTR_CTRL_6_E2E_PCI_EN 0x3E62F0 + +#define mmNIF_RTR_CTRL_6_E2E_HBM_WR_SIZE 0x3E62F4 + +#define mmNIF_RTR_CTRL_6_E2E_PCI_WR_SIZE 0x3E62F8 + +#define mmNIF_RTR_CTRL_6_E2E_AW_PCI_CTR_SET_EN 0x3E6404 + +#define mmNIF_RTR_CTRL_6_E2E_AW_PCI_CTR_SET 0x3E6408 + +#define mmNIF_RTR_CTRL_6_E2E_AW_PCI_CTR_WRAP 0x3E640C + +#define mmNIF_RTR_CTRL_6_E2E_AW_PCI_CTR_CNT 0x3E6410 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM_CTR_SET_EN 0x3E6414 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM_CTR_SET 0x3E6418 + +#define mmNIF_RTR_CTRL_6_E2E_HBM_RD_SIZE 0x3E641C + +#define mmNIF_RTR_CTRL_6_E2E_PCI_RD_SIZE 0x3E6420 + +#define mmNIF_RTR_CTRL_6_E2E_AR_PCI_CTR_SET_EN 0x3E6424 + +#define mmNIF_RTR_CTRL_6_E2E_AR_PCI_CTR_SET 0x3E6428 + +#define mmNIF_RTR_CTRL_6_E2E_AR_PCI_CTR_WRAP 0x3E642C + +#define mmNIF_RTR_CTRL_6_E2E_AR_PCI_CTR_CNT 0x3E6430 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM_CTR_SET_EN 0x3E6434 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM_CTR_SET 0x3E6438 + +#define mmNIF_RTR_CTRL_6_NL_HBM_SEL_0 0x3E6450 + +#define mmNIF_RTR_CTRL_6_NL_HBM_SEL_1 0x3E6454 + +#define mmNIF_RTR_CTRL_6_NON_LIN_EN 0x3E6480 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_BANK_0 0x3E6500 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_BANK_1 0x3E6504 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_BANK_2 0x3E6508 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_BANK_3 0x3E650C + +#define mmNIF_RTR_CTRL_6_NL_SRAM_BANK_4 0x3E6510 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_0 0x3E6514 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_1 0x3E6520 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_2 0x3E6524 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_3 0x3E6528 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_4 0x3E652C + +#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_5 0x3E6530 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_6 0x3E6534 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_7 0x3E6538 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_8 0x3E653C + +#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_9 0x3E6540 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_0 0x3E6550 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_1 0x3E6554 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_2 0x3E6558 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_3 0x3E655C + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_4 0x3E6560 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_5 0x3E6564 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_6 0x3E6568 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_7 0x3E656C + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_8 0x3E6570 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_9 0x3E6574 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_10 0x3E6578 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_11 0x3E657C + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_12 0x3E6580 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_13 0x3E6584 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_14 0x3E6588 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_15 0x3E658C + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_16 0x3E6590 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_17 0x3E6594 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_18 0x3E6598 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_0 0x3E65E4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_1 0x3E65E8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_2 0x3E65EC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_3 0x3E65F0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_4 0x3E65F4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_5 0x3E65F8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_6 0x3E65FC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_7 0x3E6600 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_8 0x3E6604 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_9 0x3E6608 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_10 0x3E660C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_11 0x3E6610 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_12 0x3E6614 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_13 0x3E6618 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_14 0x3E661C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_15 0x3E6620 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_0 0x3E6624 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_1 0x3E6628 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_2 0x3E662C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_3 0x3E6630 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_4 0x3E6634 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_5 0x3E6638 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_6 0x3E663C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_7 0x3E6640 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_8 0x3E6644 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_9 0x3E6648 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_10 0x3E664C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_11 0x3E6650 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_12 0x3E6654 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_13 0x3E6658 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_14 0x3E665C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_15 0x3E6660 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_0 0x3E6664 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_1 0x3E6668 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_2 0x3E666C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_3 0x3E6670 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_4 0x3E6674 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_5 0x3E6678 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_6 0x3E667C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_7 0x3E6680 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_8 0x3E6684 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_9 0x3E6688 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_10 0x3E668C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_11 0x3E6690 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_12 0x3E6694 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_13 0x3E6698 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_14 0x3E669C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_15 0x3E66A0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_0 0x3E66A4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_1 0x3E66A8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_2 0x3E66AC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_3 0x3E66B0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_4 0x3E66B4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_5 0x3E66B8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_6 0x3E66BC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_7 0x3E66C0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_8 0x3E66C4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_9 0x3E66C8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_10 0x3E66CC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_11 0x3E66D0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_12 0x3E66D4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_13 0x3E66D8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_14 0x3E66DC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_15 0x3E66E0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_0 0x3E66E4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_1 0x3E66E8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_2 0x3E66EC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_3 0x3E66F0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_4 0x3E66F4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_5 0x3E66F8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_6 0x3E66FC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_7 0x3E6700 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_8 0x3E6704 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_9 0x3E6708 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_10 0x3E670C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_11 0x3E6710 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_12 0x3E6714 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_13 0x3E6718 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_14 0x3E671C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_15 0x3E6720 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_0 0x3E6724 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_1 0x3E6728 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_2 0x3E672C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_3 0x3E6730 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_4 0x3E6734 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_5 0x3E6738 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_6 0x3E673C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_7 0x3E6740 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_8 0x3E6744 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_9 0x3E6748 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_10 0x3E674C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_11 0x3E6750 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_12 0x3E6754 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_13 0x3E6758 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_14 0x3E675C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_15 0x3E6760 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_0 0x3E6764 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_1 0x3E6768 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_2 0x3E676C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_3 0x3E6770 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_4 0x3E6774 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_5 0x3E6778 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_6 0x3E677C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_7 0x3E6780 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_8 0x3E6784 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_9 0x3E6788 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_10 0x3E678C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_11 0x3E6790 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_12 0x3E6794 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_13 0x3E6798 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_14 0x3E679C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_15 0x3E67A0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_0 0x3E67A4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_1 0x3E67A8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_2 0x3E67AC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_3 0x3E67B0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_4 0x3E67B4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_5 0x3E67B8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_6 0x3E67BC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_7 0x3E67C0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_8 0x3E67C4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_9 0x3E67C8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_10 0x3E67CC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_11 0x3E67D0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_12 0x3E67D4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_13 0x3E67D8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_14 0x3E67DC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_15 0x3E67E0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_0 0x3E6824 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_1 0x3E6828 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_2 0x3E682C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_3 0x3E6830 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_4 0x3E6834 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_5 0x3E6838 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_6 0x3E683C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_7 0x3E6840 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_8 0x3E6844 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_9 0x3E6848 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_10 0x3E684C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_11 0x3E6850 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_12 0x3E6854 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_13 0x3E6858 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_14 0x3E685C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_15 0x3E6860 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_0 0x3E6864 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_1 0x3E6868 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_2 0x3E686C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_3 0x3E6870 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_4 0x3E6874 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_5 0x3E6878 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_6 0x3E687C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_7 0x3E6880 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_8 0x3E6884 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_9 0x3E6888 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_10 0x3E688C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_11 0x3E6890 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_12 0x3E6894 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_13 0x3E6898 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_14 0x3E689C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_15 0x3E68A0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_0 0x3E68A4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_1 0x3E68A8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_2 0x3E68AC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_3 0x3E68B0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_4 0x3E68B4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_5 0x3E68B8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_6 0x3E68BC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_7 0x3E68C0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_8 0x3E68C4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_9 0x3E68C8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_10 0x3E68CC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_11 0x3E68D0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_12 0x3E68D4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_13 0x3E68D8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_14 0x3E68DC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_15 0x3E68E0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_0 0x3E68E4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_1 0x3E68E8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_2 0x3E68EC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_3 0x3E68F0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_4 0x3E68F4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_5 0x3E68F8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_6 0x3E68FC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_7 0x3E6900 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_8 0x3E6904 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_9 0x3E6908 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_10 0x3E690C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_11 0x3E6910 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_12 0x3E6914 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_13 0x3E6918 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_14 0x3E691C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_15 0x3E6920 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_0 0x3E6924 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_1 0x3E6928 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_2 0x3E692C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_3 0x3E6930 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_4 0x3E6934 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_5 0x3E6938 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_6 0x3E693C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_7 0x3E6940 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_8 0x3E6944 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_9 0x3E6948 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_10 0x3E694C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_11 0x3E6950 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_12 0x3E6954 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_13 0x3E6958 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_14 0x3E695C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_15 0x3E6960 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_0 0x3E6964 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_1 0x3E6968 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_2 0x3E696C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_3 0x3E6970 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_4 0x3E6974 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_5 0x3E6978 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_6 0x3E697C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_7 0x3E6980 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_8 0x3E6984 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_9 0x3E6988 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_10 0x3E698C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_11 0x3E6990 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_12 0x3E6994 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_13 0x3E6998 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_14 0x3E699C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_15 0x3E69A0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_0 0x3E69A4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_1 0x3E69A8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_2 0x3E69AC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_3 0x3E69B0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_4 0x3E69B4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_5 0x3E69B8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_6 0x3E69BC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_7 0x3E69C0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_8 0x3E69C4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_9 0x3E69C8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_10 0x3E69CC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_11 0x3E69D0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_12 0x3E69D4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_13 0x3E69D8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_14 0x3E69DC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_15 0x3E69E0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_0 0x3E69E4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_1 0x3E69E8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_2 0x3E69EC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_3 0x3E69F0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_4 0x3E69F4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_5 0x3E69F8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_6 0x3E69FC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_7 0x3E6A00 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_8 0x3E6A04 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_9 0x3E6A08 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_10 0x3E6A0C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_11 0x3E6A10 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_12 0x3E6A14 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_13 0x3E6A18 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_14 0x3E6A1C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_15 0x3E6A20 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_HIT_AW 0x3E6A64 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_HIT_AR 0x3E6A68 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_HIT_AW 0x3E6A6C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_HIT_AR 0x3E6A70 + +#define mmNIF_RTR_CTRL_6_RGL_CFG 0x3E6B64 + +#define mmNIF_RTR_CTRL_6_RGL_SHIFT 0x3E6B68 + +#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_0 0x3E6B6C + +#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_1 0x3E6B70 + +#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_2 0x3E6B74 + +#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_3 0x3E6B78 + +#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_4 0x3E6B7C + +#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_5 0x3E6B80 + +#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_6 0x3E6B84 + +#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_7 0x3E6B88 + +#define mmNIF_RTR_CTRL_6_RGL_TOKEN_0 0x3E6BAC + +#define mmNIF_RTR_CTRL_6_RGL_TOKEN_1 0x3E6BB0 + +#define mmNIF_RTR_CTRL_6_RGL_TOKEN_2 0x3E6BB4 + +#define mmNIF_RTR_CTRL_6_RGL_TOKEN_3 0x3E6BB8 + +#define mmNIF_RTR_CTRL_6_RGL_TOKEN_4 0x3E6BBC + +#define mmNIF_RTR_CTRL_6_RGL_TOKEN_5 0x3E6BC0 + +#define mmNIF_RTR_CTRL_6_RGL_TOKEN_6 0x3E6BC4 + +#define mmNIF_RTR_CTRL_6_RGL_TOKEN_7 0x3E6BC8 + +#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_0 0x3E6BEC + +#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_1 0x3E6BF0 + +#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_2 0x3E6BF4 + +#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_3 0x3E6BF8 + +#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_4 0x3E6BFC + +#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_5 0x3E6C00 + +#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_6 0x3E6C04 + +#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_7 0x3E6C08 + +#define mmNIF_RTR_CTRL_6_RGL_WDT 0x3E6C2C + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM0_CH0_CTR_WRAP 0x3E6C30 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM0_CH1_CTR_WRAP 0x3E6C34 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM1_CH0_CTR_WRAP 0x3E6C38 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM1_CH1_CTR_WRAP 0x3E6C3C + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM2_CH0_CTR_WRAP 0x3E6C40 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM2_CH1_CTR_WRAP 0x3E6C44 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM3_CH0_CTR_WRAP 0x3E6C48 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM3_CH1_CTR_WRAP 0x3E6C4C + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM0_CH0_CTR_CNT 0x3E6C50 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM0_CH1_CTR_CNT 0x3E6C54 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM1_CH0_CTR_CNT 0x3E6C58 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM1_CH1_CTR_CNT 0x3E6C5C + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM2_CH0_CTR_CNT 0x3E6C60 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM2_CH1_CTR_CNT 0x3E6C64 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM3_CH0_CTR_CNT 0x3E6C68 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM3_CH1_CTR_CNT 0x3E6C6C + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM0_CH0_CTR_WRAP 0x3E6C70 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM0_CH1_CTR_WRAP 0x3E6C74 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM1_CH0_CTR_WRAP 0x3E6C78 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM1_CH1_CTR_WRAP 0x3E6C7C + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM2_CH0_CTR_WRAP 0x3E6C80 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM2_CH1_CTR_WRAP 0x3E6C84 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM3_CH0_CTR_WRAP 0x3E6C88 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM3_CH1_CTR_WRAP 0x3E6C8C + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM0_CH0_CTR_CNT 0x3E6C90 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM0_CH1_CTR_CNT 0x3E6C94 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM1_CH0_CTR_CNT 0x3E6C98 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM1_CH1_CTR_CNT 0x3E6C9C + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM2_CH0_CTR_CNT 0x3E6CA0 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM2_CH1_CTR_CNT 0x3E6CA4 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM3_CH0_CTR_CNT 0x3E6CA8 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM3_CH1_CTR_CNT 0x3E6CAC + +#define mmNIF_RTR_CTRL_6_NL_HBM_PC_SEL_0 0x3E6CB0 + +#define mmNIF_RTR_CTRL_6_NL_HBM_PC_SEL_1 0x3E6CB4 + +#define mmNIF_RTR_CTRL_6_NL_HBM_PC_SEL_2 0x3E6CB8 + +#define mmNIF_RTR_CTRL_6_NL_HBM_PC_SEL_3 0x3E6CBC + +#endif /* ASIC_REG_NIF_RTR_CTRL_6_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_7_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_7_regs.h new file mode 100644 index 000000000000..3a6a34ba2958 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_7_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIF_RTR_CTRL_7_REGS_H_ +#define ASIC_REG_NIF_RTR_CTRL_7_REGS_H_ + +/* + ***************************************** + * NIF_RTR_CTRL_7 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmNIF_RTR_CTRL_7_PERM_SEL 0x3F6108 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_0 0x3F6114 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_1 0x3F6118 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_2 0x3F611C + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_3 0x3F6120 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_4 0x3F6124 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_5 0x3F6128 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_6 0x3F612C + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_7 0x3F6130 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_8 0x3F6134 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_9 0x3F6138 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_10 0x3F613C + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_11 0x3F6140 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_12 0x3F6144 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_13 0x3F6148 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_14 0x3F614C + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_15 0x3F6150 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_16 0x3F6154 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_17 0x3F6158 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_18 0x3F615C + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_19 0x3F6160 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_20 0x3F6164 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_21 0x3F6168 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_22 0x3F616C + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_23 0x3F6170 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_24 0x3F6174 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_25 0x3F6178 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_26 0x3F617C + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_27 0x3F6180 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_0 0x3F6184 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_1 0x3F6188 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_2 0x3F618C + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_3 0x3F6190 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_4 0x3F6194 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_5 0x3F6198 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_6 0x3F619C + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_7 0x3F61A0 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_8 0x3F61A4 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_9 0x3F61A8 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_10 0x3F61AC + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_11 0x3F61B0 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_12 0x3F61B4 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_13 0x3F61B8 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_14 0x3F61BC + +#define mmNIF_RTR_CTRL_7_SCRAM_SRAM_EN 0x3F626C + +#define mmNIF_RTR_CTRL_7_RL_HBM_EN 0x3F6274 + +#define mmNIF_RTR_CTRL_7_RL_HBM_SAT 0x3F6278 + +#define mmNIF_RTR_CTRL_7_RL_HBM_RST 0x3F627C + +#define mmNIF_RTR_CTRL_7_RL_HBM_TIMEOUT 0x3F6280 + +#define mmNIF_RTR_CTRL_7_SCRAM_HBM_EN 0x3F6284 + +#define mmNIF_RTR_CTRL_7_RL_PCI_EN 0x3F6288 + +#define mmNIF_RTR_CTRL_7_RL_PCI_SAT 0x3F628C + +#define mmNIF_RTR_CTRL_7_RL_PCI_RST 0x3F6290 + +#define mmNIF_RTR_CTRL_7_RL_PCI_TIMEOUT 0x3F6294 + +#define mmNIF_RTR_CTRL_7_RL_SRAM_EN 0x3F629C + +#define mmNIF_RTR_CTRL_7_RL_SRAM_SAT 0x3F62A0 + +#define mmNIF_RTR_CTRL_7_RL_SRAM_RST 0x3F62A4 + +#define mmNIF_RTR_CTRL_7_RL_SRAM_TIMEOUT 0x3F62AC + +#define mmNIF_RTR_CTRL_7_RL_SRAM_RED 0x3F62B4 + +#define mmNIF_RTR_CTRL_7_E2E_HBM_EN 0x3F62EC + +#define mmNIF_RTR_CTRL_7_E2E_PCI_EN 0x3F62F0 + +#define mmNIF_RTR_CTRL_7_E2E_HBM_WR_SIZE 0x3F62F4 + +#define mmNIF_RTR_CTRL_7_E2E_PCI_WR_SIZE 0x3F62F8 + +#define mmNIF_RTR_CTRL_7_E2E_AW_PCI_CTR_SET_EN 0x3F6404 + +#define mmNIF_RTR_CTRL_7_E2E_AW_PCI_CTR_SET 0x3F6408 + +#define mmNIF_RTR_CTRL_7_E2E_AW_PCI_CTR_WRAP 0x3F640C + +#define mmNIF_RTR_CTRL_7_E2E_AW_PCI_CTR_CNT 0x3F6410 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM_CTR_SET_EN 0x3F6414 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM_CTR_SET 0x3F6418 + +#define mmNIF_RTR_CTRL_7_E2E_HBM_RD_SIZE 0x3F641C + +#define mmNIF_RTR_CTRL_7_E2E_PCI_RD_SIZE 0x3F6420 + +#define mmNIF_RTR_CTRL_7_E2E_AR_PCI_CTR_SET_EN 0x3F6424 + +#define mmNIF_RTR_CTRL_7_E2E_AR_PCI_CTR_SET 0x3F6428 + +#define mmNIF_RTR_CTRL_7_E2E_AR_PCI_CTR_WRAP 0x3F642C + +#define mmNIF_RTR_CTRL_7_E2E_AR_PCI_CTR_CNT 0x3F6430 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM_CTR_SET_EN 0x3F6434 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM_CTR_SET 0x3F6438 + +#define mmNIF_RTR_CTRL_7_NL_HBM_SEL_0 0x3F6450 + +#define mmNIF_RTR_CTRL_7_NL_HBM_SEL_1 0x3F6454 + +#define mmNIF_RTR_CTRL_7_NON_LIN_EN 0x3F6480 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_BANK_0 0x3F6500 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_BANK_1 0x3F6504 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_BANK_2 0x3F6508 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_BANK_3 0x3F650C + +#define mmNIF_RTR_CTRL_7_NL_SRAM_BANK_4 0x3F6510 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_0 0x3F6514 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_1 0x3F6520 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_2 0x3F6524 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_3 0x3F6528 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_4 0x3F652C + +#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_5 0x3F6530 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_6 0x3F6534 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_7 0x3F6538 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_8 0x3F653C + +#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_9 0x3F6540 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_0 0x3F6550 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_1 0x3F6554 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_2 0x3F6558 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_3 0x3F655C + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_4 0x3F6560 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_5 0x3F6564 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_6 0x3F6568 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_7 0x3F656C + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_8 0x3F6570 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_9 0x3F6574 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_10 0x3F6578 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_11 0x3F657C + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_12 0x3F6580 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_13 0x3F6584 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_14 0x3F6588 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_15 0x3F658C + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_16 0x3F6590 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_17 0x3F6594 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_18 0x3F6598 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_0 0x3F65E4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_1 0x3F65E8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_2 0x3F65EC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_3 0x3F65F0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_4 0x3F65F4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_5 0x3F65F8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_6 0x3F65FC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_7 0x3F6600 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_8 0x3F6604 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_9 0x3F6608 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_10 0x3F660C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_11 0x3F6610 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_12 0x3F6614 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_13 0x3F6618 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_14 0x3F661C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_15 0x3F6620 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_0 0x3F6624 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_1 0x3F6628 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_2 0x3F662C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_3 0x3F6630 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_4 0x3F6634 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_5 0x3F6638 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_6 0x3F663C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_7 0x3F6640 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_8 0x3F6644 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_9 0x3F6648 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_10 0x3F664C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_11 0x3F6650 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_12 0x3F6654 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_13 0x3F6658 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_14 0x3F665C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_15 0x3F6660 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_0 0x3F6664 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_1 0x3F6668 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_2 0x3F666C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_3 0x3F6670 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_4 0x3F6674 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_5 0x3F6678 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_6 0x3F667C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_7 0x3F6680 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_8 0x3F6684 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_9 0x3F6688 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_10 0x3F668C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_11 0x3F6690 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_12 0x3F6694 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_13 0x3F6698 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_14 0x3F669C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_15 0x3F66A0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_0 0x3F66A4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_1 0x3F66A8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_2 0x3F66AC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_3 0x3F66B0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_4 0x3F66B4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_5 0x3F66B8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_6 0x3F66BC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_7 0x3F66C0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_8 0x3F66C4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_9 0x3F66C8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_10 0x3F66CC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_11 0x3F66D0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_12 0x3F66D4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_13 0x3F66D8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_14 0x3F66DC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_15 0x3F66E0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_0 0x3F66E4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_1 0x3F66E8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_2 0x3F66EC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_3 0x3F66F0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_4 0x3F66F4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_5 0x3F66F8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_6 0x3F66FC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_7 0x3F6700 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_8 0x3F6704 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_9 0x3F6708 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_10 0x3F670C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_11 0x3F6710 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_12 0x3F6714 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_13 0x3F6718 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_14 0x3F671C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_15 0x3F6720 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_0 0x3F6724 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_1 0x3F6728 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_2 0x3F672C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_3 0x3F6730 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_4 0x3F6734 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_5 0x3F6738 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_6 0x3F673C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_7 0x3F6740 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_8 0x3F6744 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_9 0x3F6748 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_10 0x3F674C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_11 0x3F6750 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_12 0x3F6754 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_13 0x3F6758 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_14 0x3F675C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_15 0x3F6760 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_0 0x3F6764 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_1 0x3F6768 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_2 0x3F676C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_3 0x3F6770 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_4 0x3F6774 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_5 0x3F6778 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_6 0x3F677C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_7 0x3F6780 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_8 0x3F6784 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_9 0x3F6788 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_10 0x3F678C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_11 0x3F6790 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_12 0x3F6794 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_13 0x3F6798 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_14 0x3F679C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_15 0x3F67A0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_0 0x3F67A4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_1 0x3F67A8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_2 0x3F67AC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_3 0x3F67B0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_4 0x3F67B4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_5 0x3F67B8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_6 0x3F67BC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_7 0x3F67C0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_8 0x3F67C4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_9 0x3F67C8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_10 0x3F67CC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_11 0x3F67D0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_12 0x3F67D4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_13 0x3F67D8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_14 0x3F67DC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_15 0x3F67E0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_0 0x3F6824 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_1 0x3F6828 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_2 0x3F682C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_3 0x3F6830 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_4 0x3F6834 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_5 0x3F6838 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_6 0x3F683C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_7 0x3F6840 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_8 0x3F6844 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_9 0x3F6848 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_10 0x3F684C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_11 0x3F6850 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_12 0x3F6854 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_13 0x3F6858 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_14 0x3F685C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_15 0x3F6860 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_0 0x3F6864 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_1 0x3F6868 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_2 0x3F686C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_3 0x3F6870 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_4 0x3F6874 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_5 0x3F6878 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_6 0x3F687C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_7 0x3F6880 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_8 0x3F6884 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_9 0x3F6888 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_10 0x3F688C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_11 0x3F6890 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_12 0x3F6894 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_13 0x3F6898 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_14 0x3F689C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_15 0x3F68A0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_0 0x3F68A4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_1 0x3F68A8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_2 0x3F68AC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_3 0x3F68B0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_4 0x3F68B4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_5 0x3F68B8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_6 0x3F68BC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_7 0x3F68C0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_8 0x3F68C4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_9 0x3F68C8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_10 0x3F68CC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_11 0x3F68D0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_12 0x3F68D4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_13 0x3F68D8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_14 0x3F68DC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_15 0x3F68E0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_0 0x3F68E4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_1 0x3F68E8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_2 0x3F68EC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_3 0x3F68F0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_4 0x3F68F4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_5 0x3F68F8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_6 0x3F68FC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_7 0x3F6900 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_8 0x3F6904 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_9 0x3F6908 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_10 0x3F690C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_11 0x3F6910 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_12 0x3F6914 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_13 0x3F6918 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_14 0x3F691C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_15 0x3F6920 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_0 0x3F6924 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_1 0x3F6928 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_2 0x3F692C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_3 0x3F6930 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_4 0x3F6934 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_5 0x3F6938 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_6 0x3F693C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_7 0x3F6940 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_8 0x3F6944 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_9 0x3F6948 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_10 0x3F694C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_11 0x3F6950 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_12 0x3F6954 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_13 0x3F6958 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_14 0x3F695C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_15 0x3F6960 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_0 0x3F6964 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_1 0x3F6968 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_2 0x3F696C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_3 0x3F6970 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_4 0x3F6974 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_5 0x3F6978 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_6 0x3F697C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_7 0x3F6980 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_8 0x3F6984 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_9 0x3F6988 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_10 0x3F698C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_11 0x3F6990 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_12 0x3F6994 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_13 0x3F6998 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_14 0x3F699C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_15 0x3F69A0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_0 0x3F69A4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_1 0x3F69A8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_2 0x3F69AC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_3 0x3F69B0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_4 0x3F69B4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_5 0x3F69B8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_6 0x3F69BC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_7 0x3F69C0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_8 0x3F69C4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_9 0x3F69C8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_10 0x3F69CC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_11 0x3F69D0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_12 0x3F69D4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_13 0x3F69D8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_14 0x3F69DC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_15 0x3F69E0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_0 0x3F69E4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_1 0x3F69E8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_2 0x3F69EC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_3 0x3F69F0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_4 0x3F69F4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_5 0x3F69F8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_6 0x3F69FC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_7 0x3F6A00 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_8 0x3F6A04 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_9 0x3F6A08 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_10 0x3F6A0C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_11 0x3F6A10 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_12 0x3F6A14 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_13 0x3F6A18 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_14 0x3F6A1C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_15 0x3F6A20 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_HIT_AW 0x3F6A64 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_HIT_AR 0x3F6A68 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_HIT_AW 0x3F6A6C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_HIT_AR 0x3F6A70 + +#define mmNIF_RTR_CTRL_7_RGL_CFG 0x3F6B64 + +#define mmNIF_RTR_CTRL_7_RGL_SHIFT 0x3F6B68 + +#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_0 0x3F6B6C + +#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_1 0x3F6B70 + +#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_2 0x3F6B74 + +#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_3 0x3F6B78 + +#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_4 0x3F6B7C + +#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_5 0x3F6B80 + +#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_6 0x3F6B84 + +#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_7 0x3F6B88 + +#define mmNIF_RTR_CTRL_7_RGL_TOKEN_0 0x3F6BAC + +#define mmNIF_RTR_CTRL_7_RGL_TOKEN_1 0x3F6BB0 + +#define mmNIF_RTR_CTRL_7_RGL_TOKEN_2 0x3F6BB4 + +#define mmNIF_RTR_CTRL_7_RGL_TOKEN_3 0x3F6BB8 + +#define mmNIF_RTR_CTRL_7_RGL_TOKEN_4 0x3F6BBC + +#define mmNIF_RTR_CTRL_7_RGL_TOKEN_5 0x3F6BC0 + +#define mmNIF_RTR_CTRL_7_RGL_TOKEN_6 0x3F6BC4 + +#define mmNIF_RTR_CTRL_7_RGL_TOKEN_7 0x3F6BC8 + +#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_0 0x3F6BEC + +#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_1 0x3F6BF0 + +#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_2 0x3F6BF4 + +#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_3 0x3F6BF8 + +#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_4 0x3F6BFC + +#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_5 0x3F6C00 + +#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_6 0x3F6C04 + +#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_7 0x3F6C08 + +#define mmNIF_RTR_CTRL_7_RGL_WDT 0x3F6C2C + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM0_CH0_CTR_WRAP 0x3F6C30 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM0_CH1_CTR_WRAP 0x3F6C34 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM1_CH0_CTR_WRAP 0x3F6C38 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM1_CH1_CTR_WRAP 0x3F6C3C + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM2_CH0_CTR_WRAP 0x3F6C40 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM2_CH1_CTR_WRAP 0x3F6C44 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM3_CH0_CTR_WRAP 0x3F6C48 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM3_CH1_CTR_WRAP 0x3F6C4C + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM0_CH0_CTR_CNT 0x3F6C50 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM0_CH1_CTR_CNT 0x3F6C54 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM1_CH0_CTR_CNT 0x3F6C58 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM1_CH1_CTR_CNT 0x3F6C5C + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM2_CH0_CTR_CNT 0x3F6C60 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM2_CH1_CTR_CNT 0x3F6C64 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM3_CH0_CTR_CNT 0x3F6C68 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM3_CH1_CTR_CNT 0x3F6C6C + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM0_CH0_CTR_WRAP 0x3F6C70 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM0_CH1_CTR_WRAP 0x3F6C74 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM1_CH0_CTR_WRAP 0x3F6C78 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM1_CH1_CTR_WRAP 0x3F6C7C + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM2_CH0_CTR_WRAP 0x3F6C80 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM2_CH1_CTR_WRAP 0x3F6C84 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM3_CH0_CTR_WRAP 0x3F6C88 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM3_CH1_CTR_WRAP 0x3F6C8C + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM0_CH0_CTR_CNT 0x3F6C90 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM0_CH1_CTR_CNT 0x3F6C94 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM1_CH0_CTR_CNT 0x3F6C98 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM1_CH1_CTR_CNT 0x3F6C9C + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM2_CH0_CTR_CNT 0x3F6CA0 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM2_CH1_CTR_CNT 0x3F6CA4 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM3_CH0_CTR_CNT 0x3F6CA8 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM3_CH1_CTR_CNT 0x3F6CAC + +#define mmNIF_RTR_CTRL_7_NL_HBM_PC_SEL_0 0x3F6CB0 + +#define mmNIF_RTR_CTRL_7_NL_HBM_PC_SEL_1 0x3F6CB4 + +#define mmNIF_RTR_CTRL_7_NL_HBM_PC_SEL_2 0x3F6CB8 + +#define mmNIF_RTR_CTRL_7_NL_HBM_PC_SEL_3 0x3F6CBC + +#endif /* ASIC_REG_NIF_RTR_CTRL_7_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_etr_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_etr_regs.h new file mode 100644 index 000000000000..b7c33e025db5 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_etr_regs.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_ETR_REGS_H_ +#define ASIC_REG_PSOC_ETR_REGS_H_ + +/* + ***************************************** + * PSOC_ETR (Prototype: ETR) + ***************************************** + */ + +#define mmPSOC_ETR_RSZ 0x2C43004 + +#define mmPSOC_ETR_STS 0x2C4300C + +#define mmPSOC_ETR_RRD 0x2C43010 + +#define mmPSOC_ETR_RRP 0x2C43014 + +#define mmPSOC_ETR_RWP 0x2C43018 + +#define mmPSOC_ETR_TRG 0x2C4301C + +#define mmPSOC_ETR_CTL 0x2C43020 + +#define mmPSOC_ETR_RWD 0x2C43024 + +#define mmPSOC_ETR_MODE 0x2C43028 + +#define mmPSOC_ETR_LBUFLEVEL 0x2C4302C + +#define mmPSOC_ETR_CBUFLEVEL 0x2C43030 + +#define mmPSOC_ETR_BUFWM 0x2C43034 + +#define mmPSOC_ETR_RRPHI 0x2C43038 + +#define mmPSOC_ETR_RWPHI 0x2C4303C + +#define mmPSOC_ETR_AXICTL 0x2C43110 + +#define mmPSOC_ETR_DBALO 0x2C43118 + +#define mmPSOC_ETR_DBAHI 0x2C4311C + +#define mmPSOC_ETR_FFSR 0x2C43300 + +#define mmPSOC_ETR_FFCR 0x2C43304 + +#define mmPSOC_ETR_PSCR 0x2C43308 + +#define mmPSOC_ETR_ITMISCOP0 0x2C43EE0 + +#define mmPSOC_ETR_ITTRFLIN 0x2C43EE8 + +#define mmPSOC_ETR_ITATBDATA0 0x2C43EEC + +#define mmPSOC_ETR_ITATBCTR2 0x2C43EF0 + +#define mmPSOC_ETR_ITATBCTR1 0x2C43EF4 + +#define mmPSOC_ETR_ITATBCTR0 0x2C43EF8 + +#define mmPSOC_ETR_ITCTRL 0x2C43F00 + +#define mmPSOC_ETR_CLAIMSET 0x2C43FA0 + +#define mmPSOC_ETR_CLAIMCLR 0x2C43FA4 + +#define mmPSOC_ETR_LAR 0x2C43FB0 + +#define mmPSOC_ETR_LSR 0x2C43FB4 + +#define mmPSOC_ETR_AUTHSTATUS 0x2C43FB8 + +#define mmPSOC_ETR_DEVID 0x2C43FC8 + +#define mmPSOC_ETR_DEVTYPE 0x2C43FCC + +#define mmPSOC_ETR_PERIPHID4 0x2C43FD0 + +#define mmPSOC_ETR_PERIPHID5 0x2C43FD4 + +#define mmPSOC_ETR_PERIPHID6 0x2C43FD8 + +#define mmPSOC_ETR_PERIPHID7 0x2C43FDC + +#define mmPSOC_ETR_PERIPHID0 0x2C43FE0 + +#define mmPSOC_ETR_PERIPHID1 0x2C43FE4 + +#define mmPSOC_ETR_PERIPHID2 0x2C43FE8 + +#define mmPSOC_ETR_PERIPHID3 0x2C43FEC + +#define mmPSOC_ETR_COMPID0 0x2C43FF0 + +#define mmPSOC_ETR_COMPID1 0x2C43FF4 + +#define mmPSOC_ETR_COMPID2 0x2C43FF8 + +#define mmPSOC_ETR_COMPID3 0x2C43FFC + +#endif /* ASIC_REG_PSOC_ETR_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_global_conf_masks.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_global_conf_masks.h new file mode 100644 index 000000000000..6703e678ee9f --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_global_conf_masks.h @@ -0,0 +1,502 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ +#define ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ + +/* + ***************************************** + * PSOC_GLOBAL_CONF (Prototype: GLOBAL_CONF) + ***************************************** + */ + +/* PSOC_GLOBAL_CONF_NON_RST_FLOPS */ +#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_PCI_FW_FSM */ +#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK 0x1 + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_BTM_FSM */ +#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_SHIFT 0 +#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK 0xF + +/* PSOC_GLOBAL_CONF_SW_BTM_FSM */ +#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_MASK 0xF + +/* PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM */ +#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_MASK 0xF + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SPI_MEM_EN */ +#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PRSTN */ +#define PSOC_GLOBAL_CONF_PRSTN_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PRSTN_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PCIE_EN */ +#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_SHIFT 0 +#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR */ +#define PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_SPI_IMG_STS */ +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRI_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRI_MASK 0x1 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SEC_SHIFT 1 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SEC_MASK 0x2 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_SHIFT 2 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_MASK 0x4 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCI_SHIFT 3 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCI_MASK 0x8 + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_FSM */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_MASK 0x1 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_SHIFT 1 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_MASK 0x2 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_SHIFT 2 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_MASK 0x4 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_SHIFT 3 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_MASK 0x8 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_SHIFT 4 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_MASK 0x10 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_SHIFT 5 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_MASK 0x20 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_SHIFT 6 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_MASK 0x40 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_SHIFT 7 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_MASK 0x80 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_SHIFT 8 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_MASK 0x100 + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD_DONE_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD_DONE_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PHY_STABLE */ +#define PSOC_GLOBAL_CONF_PHY_STABLE_PRSTN_SHIFT 0 +#define PSOC_GLOBAL_CONF_PHY_STABLE_PRSTN_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PRSTN_OVR */ +#define PSOC_GLOBAL_CONF_PRSTN_OVR_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_PRSTN_OVR_EN_MASK 0x1 +#define PSOC_GLOBAL_CONF_PRSTN_OVR_VAL_SHIFT 4 +#define PSOC_GLOBAL_CONF_PRSTN_OVR_VAL_MASK 0x10 + +/* PSOC_GLOBAL_CONF_ETR_FLUSH */ +#define PSOC_GLOBAL_CONF_ETR_FLUSH_MASK_SHIFT 0 +#define PSOC_GLOBAL_CONF_ETR_FLUSH_MASK_MASK 0x1 + +/* PSOC_GLOBAL_CONF_COLD_RST_FLOPS */ +#define PSOC_GLOBAL_CONF_COLD_RST_FLOPS_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_COLD_RST_FLOPS_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_DIS_RAZWI_ERR */ +#define PSOC_GLOBAL_CONF_DIS_RAZWI_ERR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_DIS_RAZWI_ERR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PCIE_PHY_RST_N */ +#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_RAZWI */ +#define PSOC_GLOBAL_CONF_RAZWI_INTR_SHIFT 0 +#define PSOC_GLOBAL_CONF_RAZWI_INTR_MASK 0x1 +#define PSOC_GLOBAL_CONF_RAZWI_MASK_SHIFT 4 +#define PSOC_GLOBAL_CONF_RAZWI_MASK_MASK 0x10 + +/* PSOC_GLOBAL_CONF_PROT */ +#define PSOC_GLOBAL_CONF_PROT_AR_SHIFT 0 +#define PSOC_GLOBAL_CONF_PROT_AR_MASK 0x7 +#define PSOC_GLOBAL_CONF_PROT_AW_SHIFT 4 +#define PSOC_GLOBAL_CONF_PROT_AW_MASK 0x70 + +/* PSOC_GLOBAL_CONF_ADC */ +#define PSOC_GLOBAL_CONF_ADC_INTR_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_INTR_MASK 0x1 +#define PSOC_GLOBAL_CONF_ADC_MASK_SHIFT 4 +#define PSOC_GLOBAL_CONF_ADC_MASK_MASK 0x10 + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_TO */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_TO_MASK_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_TO_MASK_MASK 0x1 + +/* PSOC_GLOBAL_CONF_SCRATCHPAD */ +#define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_SHIFT 0 +#define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SEMAPHORE */ +#define PSOC_GLOBAL_CONF_SEMAPHORE_REG_SHIFT 0 +#define PSOC_GLOBAL_CONF_SEMAPHORE_REG_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_CPU_BOOT_STATUS */ +#define PSOC_GLOBAL_CONF_CPU_BOOT_STATUS_CNTR_SHIFT 0 +#define PSOC_GLOBAL_CONF_CPU_BOOT_STATUS_CNTR_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU */ +#define PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SPL_SOURCE */ +#define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_MASK 0x7 + +/* PSOC_GLOBAL_CONF_I2C_MSTR1_DBG */ +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_SHIFT 0 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_MASK 0x1 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_SHIFT 1 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_MASK 0x2 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_SHIFT 2 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_MASK 0x4 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_SHIFT 3 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_MASK 0x8 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_SHIFT 4 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_MASK 0x10 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_SHIFT 5 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_MASK 0x20 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_SHIFT 6 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_MASK 0x40 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_SHIFT 7 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_MASK 0x80 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_SHIFT 8 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_MASK 0x100 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_SHIFT 9 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_MASK 0x200 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_SHIFT 10 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_MASK 0x7C00 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_SHIFT 15 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_MASK 0x78000 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_SHIFT 19 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_MASK 0x80000 + +/* PSOC_GLOBAL_CONF_I2C_SLV */ +#define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_SHIFT 0 +#define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK */ +#define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_FLD_INT_SHIFT 0 +#define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_FLD_INT_MASK 0x1 + +/* PSOC_GLOBAL_CONF_TRACE_ADDR */ +#define PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_SHIFT 0 +#define PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_MASK 0x3FF + +/* PSOC_GLOBAL_CONF_ARUSER */ +#define PSOC_GLOBAL_CONF_ARUSER_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ARUSER_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_AWUSER */ +#define PSOC_GLOBAL_CONF_AWUSER_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_AWUSER_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_TRACE_AWUSER */ +#define PSOC_GLOBAL_CONF_TRACE_AWUSER_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_TRACE_AWUSER_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_TRACE_ARUSER */ +#define PSOC_GLOBAL_CONF_TRACE_ARUSER_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_TRACE_ARUSER_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_BTL_STS */ +#define PSOC_GLOBAL_CONF_BTL_STS_DONE_SHIFT 0 +#define PSOC_GLOBAL_CONF_BTL_STS_DONE_MASK 0x1 +#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_SHIFT 4 +#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_MASK 0x10 +#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_SHIFT 8 +#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_MASK 0xF00 + +/* PSOC_GLOBAL_CONF_TIMEOUT_INTR */ +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_SHIFT 0 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_MASK 0x1 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_SHIFT 1 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_MASK 0x2 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_SHIFT 2 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_MASK 0x4 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_SHIFT 3 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_MASK 0x8 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_SHIFT 4 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_MASK 0x10 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_SHIFT 5 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_MASK 0x20 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_SHIFT 6 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_MASK 0x40 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_SHIFT 7 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_MASK 0x80 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_5_SHIFT 8 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_5_MASK 0x100 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_6_SHIFT 9 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_6_MASK 0x200 + +/* PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR */ +#define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PERIPH_INTR */ +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_SHIFT 0 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_MASK 0x1 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_SHIFT 1 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_MASK 0x2 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_SHIFT 2 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_MASK 0x4 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_SHIFT 3 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_MASK 0x8 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_SHIFT 4 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_MASK 0x10 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_SHIFT 5 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_MASK 0x20 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_SHIFT 6 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_MASK 0x40 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_SHIFT 7 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_MASK 0x80 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_SHIFT 12 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_MASK 0x1000 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_SHIFT 13 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_MASK 0x2000 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_SHIFT 16 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_MASK 0x10000 + +/* PSOC_GLOBAL_CONF_COMB_PERIPH_INTR */ +#define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_AXI_ERR_INTR */ +#define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_TARGETID */ +#define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_SHIFT 1 +#define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_MASK 0xFFE +#define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_SHIFT 16 +#define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_MASK 0xFFF0000 +#define PSOC_GLOBAL_CONF_TARGETID_TREVISION_SHIFT 28 +#define PSOC_GLOBAL_CONF_TARGETID_TREVISION_MASK 0xF0000000 + +/* PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE */ +#define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_BOOT_STRAP_PINS */ +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SLV_ADDR_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SLV_ADDR_MASK 0x1 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PCIE_EN_SHIFT 1 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PCIE_EN_MASK 0x2 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_REPAIR_CFG_SHIFT 2 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_REPAIR_CFG_MASK 0xC +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPOL_SHIFT 4 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPOL_MASK 0x10 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPHA_SHIFT 5 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPHA_MASK 0x20 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_EN_SHIFT 6 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_EN_MASK 0x40 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_ROM_EN_SHIFT 7 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_ROM_EN_MASK 0x80 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_SEL_SHIFT 8 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_SEL_MASK 0x1FFF00 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_GRAD_RST_SHIFT 22 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_GRAD_RST_MASK 0x400000 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_DIS_SHIFT 23 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_DIS_MASK 0x800000 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SHIFT 24 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_MASK 0x1F000000 + +/* PSOC_GLOBAL_CONF_MEM_REPAIR_DIV */ +#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_EN_MASK 0x1 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_VAL_SHIFT 8 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_VAL_MASK 0xFF00 + +/* PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL */ +#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_MASK 0x1 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_CLR_SHIFT 1 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_CLR_MASK 0x2 + +/* PSOC_GLOBAL_CONF_MEM_REPAIR_STS */ +#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_MASK 0x1 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_FAIL_SHIFT 4 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_FAIL_MASK 0x10 + +/* PSOC_GLOBAL_CONF_OUTSTANT_TRANS */ +#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_SHIFT 0 +#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_MASK 0x1 +#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_SHIFT 1 +#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_MASK 0x2 + +/* PSOC_GLOBAL_CONF_MASK_REQ */ +#define PSOC_GLOBAL_CONF_MASK_REQ_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_MASK_REQ_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_WD_RST_CFG_L */ +#define PSOC_GLOBAL_CONF_WD_RST_CFG_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_WD_RST_CFG_H */ +#define PSOC_GLOBAL_CONF_WD_RST_CFG_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_H_VAL_MASK 0x3FFFFF + +/* PSOC_GLOBAL_CONF_MNL_RST_CFG_L */ +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_MNL_RST_CFG_H */ +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_H_VAL_MASK 0x3FFFFF + +/* PSOC_GLOBAL_CONF_PRSTN_RST_CFG_L */ +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_PRSTN_RST_CFG_H */ +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_H_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L */ +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H */ +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H_VAL_MASK 0x3FFFFF + +/* PSOC_GLOBAL_CONF_SW_ALL_RST */ +#define PSOC_GLOBAL_CONF_SW_ALL_RST_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_SOFT_RST */ +#define PSOC_GLOBAL_CONF_SOFT_RST_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_SOFT_RST_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_SOFT_RST_CFG_L */ +#define PSOC_GLOBAL_CONF_SOFT_RST_CFG_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SOFT_RST_CFG_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SOFT_RST_CFG_H */ +#define PSOC_GLOBAL_CONF_SOFT_RST_CFG_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SOFT_RST_CFG_H_VAL_MASK 0x3FFFFF + +/* PSOC_GLOBAL_CONF_UNIT_RST_N */ +#define PSOC_GLOBAL_CONF_UNIT_RST_N_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_UNIT_RST_N_L */ +#define PSOC_GLOBAL_CONF_UNIT_RST_N_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_UNIT_RST_N_H */ +#define PSOC_GLOBAL_CONF_UNIT_RST_N_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_H_VAL_MASK 0x3FFFFF + +/* PSOC_GLOBAL_CONF_BTL_IMG */ +#define PSOC_GLOBAL_CONF_BTL_IMG_SEL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BTL_IMG_SEL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PRSTN_MASK */ +#define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_WD_MASK */ +#define PSOC_GLOBAL_CONF_WD_MASK_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_WD_MASK_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_RST_SRC */ +#define PSOC_GLOBAL_CONF_RST_SRC_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_RST_SRC_VAL_MASK 0xF + +/* PSOC_GLOBAL_CONF_BOOT_STATE */ +#define PSOC_GLOBAL_CONF_BOOT_STATE_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_STATE_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PAD_1V8_CFG */ +#define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_MASK 0x7F + +/* PSOC_GLOBAL_CONF_PAD_3V3_CFG */ +#define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_MASK 0x7F + +/* PSOC_GLOBAL_CONF_PAD_1V8_INPUT */ +#define PSOC_GLOBAL_CONF_PAD_1V8_INPUT_CFG_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_1V8_INPUT_CFG_MASK 0x7 + +/* PSOC_GLOBAL_CONF_BNK3V3_MS */ +#define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_MASK 0x3 + +/* PSOC_GLOBAL_CONF_ADC_CLK_FREQ */ +#define PSOC_GLOBAL_CONF_ADC_CLK_FREQ_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_CLK_FREQ_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START */ +#define PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_ADC_DATA_SAMPLES */ +#define PSOC_GLOBAL_CONF_ADC_DATA_SAMPLES_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_DATA_SAMPLES_VAL_MASK 0x1F + +/* PSOC_GLOBAL_CONF_ADC_TPH_CS */ +#define PSOC_GLOBAL_CONF_ADC_TPH_CS_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_TPH_CS_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_ADC_LSB_NMSB */ +#define PSOC_GLOBAL_CONF_ADC_LSB_NMSB_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_LSB_NMSB_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES */ +#define PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE */ +#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ADC_CFG_DATA */ +#define PSOC_GLOBAL_CONF_ADC_CFG_DATA_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_CFG_DATA_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_ADC_TDV_CSDO */ +#define PSOC_GLOBAL_CONF_ADC_TDV_CSDO_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_TDV_CSDO_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_ADC_TSU_CSCK */ +#define PSOC_GLOBAL_CONF_ADC_TSU_CSCK_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_TSU_CSCK_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_PAD_DEFAULT */ +#define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_MASK 0xF + +/* PSOC_GLOBAL_CONF_PAD_SEL */ +#define PSOC_GLOBAL_CONF_PAD_SEL_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_SEL_VAL_MASK 0x3 + +/* PSOC_GLOBAL_CONF_RST_CTRL */ +#define PSOC_GLOBAL_CONF_RST_CTRL_SEL_SHIFT 0 +#define PSOC_GLOBAL_CONF_RST_CTRL_SEL_MASK 0xFF + +#endif /* ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_global_conf_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_global_conf_regs.h new file mode 100644 index 000000000000..1b5cfcc1d85f --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_global_conf_regs.h @@ -0,0 +1,1062 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ +#define ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ + +/* + ***************************************** + * PSOC_GLOBAL_CONF (Prototype: GLOBAL_CONF) + ***************************************** + */ + +#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_0 0xC4B000 + +#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_1 0xC4B004 + +#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_2 0xC4B008 + +#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_3 0xC4B00C + +#define mmPSOC_GLOBAL_CONF_PCI_FW_FSM 0xC4B020 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START 0xC4B024 + +#define mmPSOC_GLOBAL_CONF_BTM_FSM 0xC4B028 + +#define mmPSOC_GLOBAL_CONF_SW_BTM_FSM 0xC4B030 + +#define mmPSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM 0xC4B034 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT 0xC4B038 + +#define mmPSOC_GLOBAL_CONF_SPI_MEM_EN 0xC4B040 + +#define mmPSOC_GLOBAL_CONF_PRSTN 0xC4B044 + +#define mmPSOC_GLOBAL_CONF_PCIE_EN 0xC4B048 + +#define mmPSOC_GLOBAL_CONF_PCIE_PRSTN_INTR 0xC4B04C + +#define mmPSOC_GLOBAL_CONF_SPI_IMG_STS 0xC4B050 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_FSM 0xC4B054 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD 0xC4B058 + +#define mmPSOC_GLOBAL_CONF_PHY_STABLE 0xC4B060 + +#define mmPSOC_GLOBAL_CONF_PRSTN_OVR 0xC4B064 + +#define mmPSOC_GLOBAL_CONF_ETR_FLUSH 0xC4B068 + +#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_0 0xC4B070 + +#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_1 0xC4B074 + +#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_2 0xC4B078 + +#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_3 0xC4B07C + +#define mmPSOC_GLOBAL_CONF_DIS_RAZWI_ERR 0xC4B080 + +#define mmPSOC_GLOBAL_CONF_PCIE_PHY_RST_N 0xC4B084 + +#define mmPSOC_GLOBAL_CONF_RAZWI 0xC4B088 + +#define mmPSOC_GLOBAL_CONF_PROT 0xC4B090 + +#define mmPSOC_GLOBAL_CONF_ADC 0xC4B094 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_TO 0xC4B098 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_0 0xC4B100 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_1 0xC4B104 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_2 0xC4B108 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_3 0xC4B10C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_4 0xC4B110 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_5 0xC4B114 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_6 0xC4B118 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_7 0xC4B11C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_8 0xC4B120 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_9 0xC4B124 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_10 0xC4B128 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_11 0xC4B12C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_12 0xC4B130 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_13 0xC4B134 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_14 0xC4B138 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_15 0xC4B13C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_16 0xC4B140 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_17 0xC4B144 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_18 0xC4B148 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_19 0xC4B14C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_20 0xC4B150 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_21 0xC4B154 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_22 0xC4B158 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_23 0xC4B15C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_24 0xC4B160 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_25 0xC4B164 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_26 0xC4B168 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_27 0xC4B16C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_28 0xC4B170 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_29 0xC4B174 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_30 0xC4B178 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_31 0xC4B17C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_0 0xC4B200 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_1 0xC4B204 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_2 0xC4B208 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_3 0xC4B20C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_4 0xC4B210 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_5 0xC4B214 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_6 0xC4B218 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_7 0xC4B21C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_8 0xC4B220 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_9 0xC4B224 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_10 0xC4B228 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_11 0xC4B22C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_12 0xC4B230 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_13 0xC4B234 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_14 0xC4B238 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_15 0xC4B23C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_16 0xC4B240 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_17 0xC4B244 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_18 0xC4B248 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_19 0xC4B24C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_20 0xC4B250 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_21 0xC4B254 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_22 0xC4B258 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_23 0xC4B25C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_24 0xC4B260 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_25 0xC4B264 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_26 0xC4B268 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_27 0xC4B26C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_28 0xC4B270 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_29 0xC4B274 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_30 0xC4B278 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_31 0xC4B27C + +#define mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS 0xC4B300 + +#define mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU 0xC4B304 + +#define mmPSOC_GLOBAL_CONF_SPL_SOURCE 0xC4B308 + +#define mmPSOC_GLOBAL_CONF_I2C_MSTR1_DBG 0xC4B30C + +#define mmPSOC_GLOBAL_CONF_I2C_SLV 0xC4B310 + +#define mmPSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK 0xC4B314 + +#define mmPSOC_GLOBAL_CONF_TRACE_ADDR 0xC4B320 + +#define mmPSOC_GLOBAL_CONF_ARUSER 0xC4B330 + +#define mmPSOC_GLOBAL_CONF_AWUSER 0xC4B334 + +#define mmPSOC_GLOBAL_CONF_TRACE_AWUSER 0xC4B338 + +#define mmPSOC_GLOBAL_CONF_TRACE_ARUSER 0xC4B33C + +#define mmPSOC_GLOBAL_CONF_BTL_STS 0xC4B340 + +#define mmPSOC_GLOBAL_CONF_TIMEOUT_INTR 0xC4B350 + +#define mmPSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR 0xC4B354 + +#define mmPSOC_GLOBAL_CONF_PERIPH_INTR 0xC4B358 + +#define mmPSOC_GLOBAL_CONF_COMB_PERIPH_INTR 0xC4B35C + +#define mmPSOC_GLOBAL_CONF_AXI_ERR_INTR 0xC4B360 + +#define mmPSOC_GLOBAL_CONF_TARGETID 0xC4B400 + +#define mmPSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE 0xC4B420 + +#define mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS 0xC4B430 + +#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_DIV 0xC4B44C + +#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_CTRL 0xC4B450 + +#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_STS 0xC4B454 + +#define mmPSOC_GLOBAL_CONF_OUTSTANT_TRANS 0xC4B458 + +#define mmPSOC_GLOBAL_CONF_MASK_REQ 0xC4B45C + +#define mmPSOC_GLOBAL_CONF_WD_RST_CFG_L 0xC4B460 + +#define mmPSOC_GLOBAL_CONF_WD_RST_CFG_H 0xC4B464 + +#define mmPSOC_GLOBAL_CONF_MNL_RST_CFG_L 0xC4B470 + +#define mmPSOC_GLOBAL_CONF_MNL_RST_CFG_H 0xC4B474 + +#define mmPSOC_GLOBAL_CONF_PRSTN_RST_CFG_L 0xC4B480 + +#define mmPSOC_GLOBAL_CONF_PRSTN_RST_CFG_H 0xC4B484 + +#define mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L 0xC4B490 + +#define mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H 0xC4B494 + +#define mmPSOC_GLOBAL_CONF_SW_ALL_RST 0xC4B498 + +#define mmPSOC_GLOBAL_CONF_SOFT_RST 0xC4B4A0 + +#define mmPSOC_GLOBAL_CONF_SOFT_RST_CFG_L 0xC4B4A4 + +#define mmPSOC_GLOBAL_CONF_SOFT_RST_CFG_H 0xC4B4A8 + +#define mmPSOC_GLOBAL_CONF_UNIT_RST_N 0xC4B4B0 + +#define mmPSOC_GLOBAL_CONF_UNIT_RST_N_L 0xC4B4B4 + +#define mmPSOC_GLOBAL_CONF_UNIT_RST_N_H 0xC4B4B8 + +#define mmPSOC_GLOBAL_CONF_BTL_IMG 0xC4B4E0 + +#define mmPSOC_GLOBAL_CONF_PRSTN_MASK 0xC4B4E4 + +#define mmPSOC_GLOBAL_CONF_WD_MASK 0xC4B4E8 + +#define mmPSOC_GLOBAL_CONF_RST_SRC 0xC4B4F0 + +#define mmPSOC_GLOBAL_CONF_BOOT_STATE 0xC4B4F4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_0 0xC4B500 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_1 0xC4B504 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_2 0xC4B508 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_3 0xC4B50C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_4 0xC4B510 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_5 0xC4B514 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_6 0xC4B518 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_7 0xC4B51C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_8 0xC4B520 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_9 0xC4B524 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_10 0xC4B528 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_11 0xC4B52C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_12 0xC4B530 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_13 0xC4B534 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_14 0xC4B538 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_15 0xC4B53C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_16 0xC4B540 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_17 0xC4B544 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_18 0xC4B548 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_19 0xC4B54C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_20 0xC4B550 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_21 0xC4B554 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_22 0xC4B558 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_23 0xC4B55C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_24 0xC4B560 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_25 0xC4B564 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_26 0xC4B568 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_27 0xC4B56C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_28 0xC4B570 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_29 0xC4B574 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_30 0xC4B578 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_31 0xC4B57C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_32 0xC4B580 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_33 0xC4B584 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_34 0xC4B588 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_35 0xC4B58C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_36 0xC4B590 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_37 0xC4B594 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_38 0xC4B598 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_39 0xC4B59C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_40 0xC4B5A0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_41 0xC4B5A4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_42 0xC4B5A8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_43 0xC4B5AC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_44 0xC4B5B0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_45 0xC4B5B4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_46 0xC4B5B8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_47 0xC4B5BC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_48 0xC4B5C0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_49 0xC4B5C4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_50 0xC4B5C8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_51 0xC4B5CC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_52 0xC4B5D0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_53 0xC4B5D4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_54 0xC4B5D8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_55 0xC4B5DC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_56 0xC4B5E0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_57 0xC4B5E4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_58 0xC4B5E8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_59 0xC4B5EC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_60 0xC4B5F0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_61 0xC4B5F4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_62 0xC4B5F8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_63 0xC4B5FC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_64 0xC4B600 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_65 0xC4B604 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_66 0xC4B608 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_67 0xC4B60C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_68 0xC4B610 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_69 0xC4B614 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_70 0xC4B618 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_71 0xC4B61C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_72 0xC4B620 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_73 0xC4B624 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_74 0xC4B628 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_75 0xC4B62C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_76 0xC4B630 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_77 0xC4B634 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_78 0xC4B638 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_79 0xC4B63C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_80 0xC4B640 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_81 0xC4B644 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_82 0xC4B648 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_83 0xC4B64C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_84 0xC4B650 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_85 0xC4B654 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_86 0xC4B658 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_87 0xC4B65C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_88 0xC4B660 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_89 0xC4B664 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_0 0xC4B690 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_1 0xC4B694 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_2 0xC4B698 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_3 0xC4B69C + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_4 0xC4B6A0 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_5 0xC4B6A4 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_6 0xC4B6A8 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_7 0xC4B6AC + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_8 0xC4B6B0 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_9 0xC4B6B4 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_10 0xC4B6B8 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_11 0xC4B6BC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_0 0xC4B6C0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_1 0xC4B6C4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_2 0xC4B6C8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_3 0xC4B6CC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_4 0xC4B6D0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_5 0xC4B6D4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_6 0xC4B6D8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_7 0xC4B6DC + +#define mmPSOC_GLOBAL_CONF_BNK3V3_MS 0xC4B710 + +#define mmPSOC_GLOBAL_CONF_ADC_CLK_FREQ 0xC4B720 + +#define mmPSOC_GLOBAL_CONF_ADC_DELAY_FROM_START 0xC4B724 + +#define mmPSOC_GLOBAL_CONF_ADC_DATA_SAMPLES 0xC4B728 + +#define mmPSOC_GLOBAL_CONF_ADC_TPH_CS 0xC4B72C + +#define mmPSOC_GLOBAL_CONF_ADC_LSB_NMSB 0xC4B730 + +#define mmPSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES 0xC4B734 + +#define mmPSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE 0xC4B738 + +#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA 0xC4B73C + +#define mmPSOC_GLOBAL_CONF_ADC_TDV_CSDO 0xC4B740 + +#define mmPSOC_GLOBAL_CONF_ADC_TSU_CSCK 0xC4B744 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_0 0xC4B800 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_1 0xC4B804 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_2 0xC4B808 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_3 0xC4B80C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_4 0xC4B810 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_5 0xC4B814 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_6 0xC4B818 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_7 0xC4B81C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_8 0xC4B820 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_9 0xC4B824 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_10 0xC4B828 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_11 0xC4B82C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_12 0xC4B830 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_13 0xC4B834 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_14 0xC4B838 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_15 0xC4B83C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_16 0xC4B840 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_17 0xC4B844 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_18 0xC4B848 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_19 0xC4B84C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_20 0xC4B850 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_21 0xC4B854 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_22 0xC4B858 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_23 0xC4B85C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_24 0xC4B860 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_25 0xC4B864 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_26 0xC4B868 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_27 0xC4B86C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_28 0xC4B870 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_29 0xC4B874 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_30 0xC4B878 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_31 0xC4B87C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_32 0xC4B880 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_33 0xC4B884 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_34 0xC4B888 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_35 0xC4B88C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_36 0xC4B890 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_37 0xC4B894 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_38 0xC4B898 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_39 0xC4B89C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_40 0xC4B8A0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_41 0xC4B8A4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_42 0xC4B8A8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_43 0xC4B8AC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_44 0xC4B8B0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_45 0xC4B8B4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_46 0xC4B8B8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_47 0xC4B8BC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_48 0xC4B8C0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_49 0xC4B8C4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_50 0xC4B8C8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_51 0xC4B8CC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_52 0xC4B8D0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_53 0xC4B8D4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_54 0xC4B8D8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_55 0xC4B8DC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_56 0xC4B8E0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_57 0xC4B8E4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_58 0xC4B8E8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_59 0xC4B8EC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_60 0xC4B8F0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_61 0xC4B8F4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_62 0xC4B8F8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_63 0xC4B8FC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_64 0xC4B900 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_65 0xC4B904 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_66 0xC4B908 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_67 0xC4B90C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_68 0xC4B910 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_69 0xC4B914 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_70 0xC4B918 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_71 0xC4B91C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_72 0xC4B920 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_73 0xC4B924 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_74 0xC4B928 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_75 0xC4B92C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_76 0xC4B930 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_77 0xC4B934 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_78 0xC4B938 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_79 0xC4B93C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_80 0xC4B940 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_81 0xC4B944 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_82 0xC4B948 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_83 0xC4B94C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_84 0xC4B950 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_85 0xC4B954 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_86 0xC4B958 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_87 0xC4B95C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_88 0xC4B960 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_89 0xC4B964 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_90 0xC4B968 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_91 0xC4B96C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_92 0xC4B970 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_93 0xC4B974 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_94 0xC4B978 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_95 0xC4B97C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_96 0xC4B980 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_97 0xC4B984 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_98 0xC4B988 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_99 0xC4B98C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_100 0xC4B990 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_101 0xC4B994 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_102 0xC4B998 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_0 0xC4BA00 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_1 0xC4BA04 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_2 0xC4BA08 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_3 0xC4BA0C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_4 0xC4BA10 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_5 0xC4BA14 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_6 0xC4BA18 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_7 0xC4BA1C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_8 0xC4BA20 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_9 0xC4BA24 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_10 0xC4BA28 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_11 0xC4BA2C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_12 0xC4BA30 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_13 0xC4BA34 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_14 0xC4BA38 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_15 0xC4BA3C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_16 0xC4BA40 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_17 0xC4BA44 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_18 0xC4BA48 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_19 0xC4BA4C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_20 0xC4BA50 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_21 0xC4BA54 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_22 0xC4BA58 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_23 0xC4BA5C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_24 0xC4BA60 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_25 0xC4BA64 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_26 0xC4BA68 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_27 0xC4BA6C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_28 0xC4BA70 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_29 0xC4BA74 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_30 0xC4BA78 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_31 0xC4BA7C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_32 0xC4BA80 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_33 0xC4BA84 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_34 0xC4BA88 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_35 0xC4BA8C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_36 0xC4BA90 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_37 0xC4BA94 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_38 0xC4BA98 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_39 0xC4BA9C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_40 0xC4BAA0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_41 0xC4BAA4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_42 0xC4BAA8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_43 0xC4BAAC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_44 0xC4BAB0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_45 0xC4BAB4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_46 0xC4BAB8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_47 0xC4BABC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_48 0xC4BAC0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_49 0xC4BAC4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_50 0xC4BAC8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_51 0xC4BACC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_52 0xC4BAD0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_53 0xC4BAD4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_54 0xC4BAD8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_55 0xC4BADC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_56 0xC4BAE0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_57 0xC4BAE4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_58 0xC4BAE8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_59 0xC4BAEC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_60 0xC4BAF0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_61 0xC4BAF4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_62 0xC4BAF8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_63 0xC4BAFC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_64 0xC4BB00 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_65 0xC4BB04 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_66 0xC4BB08 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_67 0xC4BB0C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_68 0xC4BB10 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_69 0xC4BB14 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_70 0xC4BB18 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_71 0xC4BB1C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_72 0xC4BB20 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_73 0xC4BB24 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_74 0xC4BB28 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_75 0xC4BB2C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_76 0xC4BB30 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_77 0xC4BB34 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_78 0xC4BB38 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_79 0xC4BB3C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_80 0xC4BB40 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_81 0xC4BB44 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_82 0xC4BB48 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_83 0xC4BB4C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_84 0xC4BB50 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_85 0xC4BB54 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_86 0xC4BB58 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_87 0xC4BB5C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_88 0xC4BB60 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_89 0xC4BB64 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_90 0xC4BB68 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_91 0xC4BB6C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_92 0xC4BB70 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_93 0xC4BB74 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_94 0xC4BB78 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_95 0xC4BB7C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_96 0xC4BB80 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_97 0xC4BB84 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_98 0xC4BB88 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_99 0xC4BB8C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_100 0xC4BB90 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_101 0xC4BB94 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_102 0xC4BB98 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_0 0xC4BC00 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_1 0xC4BC04 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_2 0xC4BC08 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_3 0xC4BC0C + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_4 0xC4BC10 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_5 0xC4BC14 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_6 0xC4BC18 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_7 0xC4BC1C + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_8 0xC4BC20 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_9 0xC4BC24 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_10 0xC4BC28 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_11 0xC4BC2C + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_12 0xC4BC30 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_13 0xC4BC34 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_14 0xC4BC38 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_15 0xC4BC3C + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_16 0xC4BC40 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_17 0xC4BC44 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_18 0xC4BC48 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_19 0xC4BC4C + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_20 0xC4BC50 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_21 0xC4BC54 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_22 0xC4BC58 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_23 0xC4BC5C + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_24 0xC4BC60 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_25 0xC4BC64 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_26 0xC4BC68 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_27 0xC4BC6C + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_28 0xC4BC70 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_29 0xC4BC74 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_30 0xC4BC78 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_31 0xC4BC7C + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_32 0xC4BC80 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_33 0xC4BC84 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_34 0xC4BC88 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_35 0xC4BC8C + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_36 0xC4BC90 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_37 0xC4BC94 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_38 0xC4BC98 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_39 0xC4BC9C + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_40 0xC4BCA0 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_41 0xC4BCA4 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_42 0xC4BCA8 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_43 0xC4BCAC + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_44 0xC4BCB0 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_45 0xC4BCB4 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_46 0xC4BCB8 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_47 0xC4BCBC + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_48 0xC4BCC0 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_49 0xC4BCC4 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_50 0xC4BCC8 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_51 0xC4BCCC + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_52 0xC4BCD0 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_53 0xC4BCD4 + +#endif /* ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_hbm_pll_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_hbm_pll_regs.h new file mode 100644 index 000000000000..687e2255cb19 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_hbm_pll_regs.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_HBM_PLL_REGS_H_ +#define ASIC_REG_PSOC_HBM_PLL_REGS_H_ + +/* + ***************************************** + * PSOC_HBM_PLL (Prototype: PLL) + ***************************************** + */ + +#define mmPSOC_HBM_PLL_NR 0xC74100 + +#define mmPSOC_HBM_PLL_NF 0xC74104 + +#define mmPSOC_HBM_PLL_OD 0xC74108 + +#define mmPSOC_HBM_PLL_NB 0xC7410C + +#define mmPSOC_HBM_PLL_CFG 0xC74110 + +#define mmPSOC_HBM_PLL_LOSE_MASK 0xC74120 + +#define mmPSOC_HBM_PLL_LOCK_INTR 0xC74128 + +#define mmPSOC_HBM_PLL_LOCK_BYPASS 0xC7412C + +#define mmPSOC_HBM_PLL_DATA_CHNG 0xC74130 + +#define mmPSOC_HBM_PLL_RST 0xC74134 + +#define mmPSOC_HBM_PLL_SLIP_WD_CNTR 0xC74150 + +#define mmPSOC_HBM_PLL_DIV_FACTOR_0 0xC74200 + +#define mmPSOC_HBM_PLL_DIV_FACTOR_1 0xC74204 + +#define mmPSOC_HBM_PLL_DIV_FACTOR_2 0xC74208 + +#define mmPSOC_HBM_PLL_DIV_FACTOR_3 0xC7420C + +#define mmPSOC_HBM_PLL_DIV_FACTOR_CMD_0 0xC74220 + +#define mmPSOC_HBM_PLL_DIV_FACTOR_CMD_1 0xC74224 + +#define mmPSOC_HBM_PLL_DIV_FACTOR_CMD_2 0xC74228 + +#define mmPSOC_HBM_PLL_DIV_FACTOR_CMD_3 0xC7422C + +#define mmPSOC_HBM_PLL_DIV_SEL_0 0xC74280 + +#define mmPSOC_HBM_PLL_DIV_SEL_1 0xC74284 + +#define mmPSOC_HBM_PLL_DIV_SEL_2 0xC74288 + +#define mmPSOC_HBM_PLL_DIV_SEL_3 0xC7428C + +#define mmPSOC_HBM_PLL_DIV_EN_0 0xC742A0 + +#define mmPSOC_HBM_PLL_DIV_EN_1 0xC742A4 + +#define mmPSOC_HBM_PLL_DIV_EN_2 0xC742A8 + +#define mmPSOC_HBM_PLL_DIV_EN_3 0xC742AC + +#define mmPSOC_HBM_PLL_DIV_FACTOR_BUSY_0 0xC742C0 + +#define mmPSOC_HBM_PLL_DIV_FACTOR_BUSY_1 0xC742C4 + +#define mmPSOC_HBM_PLL_DIV_FACTOR_BUSY_2 0xC742C8 + +#define mmPSOC_HBM_PLL_DIV_FACTOR_BUSY_3 0xC742CC + +#define mmPSOC_HBM_PLL_CLK_GATER 0xC74300 + +#define mmPSOC_HBM_PLL_CLK_RLX_0 0xC74310 + +#define mmPSOC_HBM_PLL_CLK_RLX_1 0xC74314 + +#define mmPSOC_HBM_PLL_CLK_RLX_2 0xC74318 + +#define mmPSOC_HBM_PLL_CLK_RLX_3 0xC7431C + +#define mmPSOC_HBM_PLL_REF_CNTR_PERIOD 0xC74400 + +#define mmPSOC_HBM_PLL_REF_LOW_THRESHOLD 0xC74410 + +#define mmPSOC_HBM_PLL_REF_HIGH_THRESHOLD 0xC74420 + +#define mmPSOC_HBM_PLL_PLL_NOT_STABLE 0xC74430 + +#define mmPSOC_HBM_PLL_FREQ_CALC_EN 0xC74440 + +#define mmPSOC_HBM_PLL_RLX_BITMAP_CFG 0xC74500 + +#define mmPSOC_HBM_PLL_RLX_BITMAP_0 0xC74510 + +#define mmPSOC_HBM_PLL_RLX_BITMAP_1 0xC74514 + +#define mmPSOC_HBM_PLL_RLX_BITMAP_2 0xC74518 + +#define mmPSOC_HBM_PLL_RLX_BITMAP_3 0xC7451C + +#endif /* ASIC_REG_PSOC_HBM_PLL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_pci_pll_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_pci_pll_regs.h new file mode 100644 index 000000000000..3dc9bb4542dd --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_pci_pll_regs.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_PCI_PLL_REGS_H_ +#define ASIC_REG_PSOC_PCI_PLL_REGS_H_ + +/* + ***************************************** + * PSOC_PCI_PLL (Prototype: PLL) + ***************************************** + */ + +#define mmPSOC_PCI_PLL_NR 0xC72100 + +#define mmPSOC_PCI_PLL_NF 0xC72104 + +#define mmPSOC_PCI_PLL_OD 0xC72108 + +#define mmPSOC_PCI_PLL_NB 0xC7210C + +#define mmPSOC_PCI_PLL_CFG 0xC72110 + +#define mmPSOC_PCI_PLL_LOSE_MASK 0xC72120 + +#define mmPSOC_PCI_PLL_LOCK_INTR 0xC72128 + +#define mmPSOC_PCI_PLL_LOCK_BYPASS 0xC7212C + +#define mmPSOC_PCI_PLL_DATA_CHNG 0xC72130 + +#define mmPSOC_PCI_PLL_RST 0xC72134 + +#define mmPSOC_PCI_PLL_SLIP_WD_CNTR 0xC72150 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_0 0xC72200 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_1 0xC72204 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_2 0xC72208 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_3 0xC7220C + +#define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_0 0xC72220 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_1 0xC72224 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_2 0xC72228 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_3 0xC7222C + +#define mmPSOC_PCI_PLL_DIV_SEL_0 0xC72280 + +#define mmPSOC_PCI_PLL_DIV_SEL_1 0xC72284 + +#define mmPSOC_PCI_PLL_DIV_SEL_2 0xC72288 + +#define mmPSOC_PCI_PLL_DIV_SEL_3 0xC7228C + +#define mmPSOC_PCI_PLL_DIV_EN_0 0xC722A0 + +#define mmPSOC_PCI_PLL_DIV_EN_1 0xC722A4 + +#define mmPSOC_PCI_PLL_DIV_EN_2 0xC722A8 + +#define mmPSOC_PCI_PLL_DIV_EN_3 0xC722AC + +#define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_0 0xC722C0 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_1 0xC722C4 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_2 0xC722C8 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_3 0xC722CC + +#define mmPSOC_PCI_PLL_CLK_GATER 0xC72300 + +#define mmPSOC_PCI_PLL_CLK_RLX_0 0xC72310 + +#define mmPSOC_PCI_PLL_CLK_RLX_1 0xC72314 + +#define mmPSOC_PCI_PLL_CLK_RLX_2 0xC72318 + +#define mmPSOC_PCI_PLL_CLK_RLX_3 0xC7231C + +#define mmPSOC_PCI_PLL_REF_CNTR_PERIOD 0xC72400 + +#define mmPSOC_PCI_PLL_REF_LOW_THRESHOLD 0xC72410 + +#define mmPSOC_PCI_PLL_REF_HIGH_THRESHOLD 0xC72420 + +#define mmPSOC_PCI_PLL_PLL_NOT_STABLE 0xC72430 + +#define mmPSOC_PCI_PLL_FREQ_CALC_EN 0xC72440 + +#define mmPSOC_PCI_PLL_RLX_BITMAP_CFG 0xC72500 + +#define mmPSOC_PCI_PLL_RLX_BITMAP_0 0xC72510 + +#define mmPSOC_PCI_PLL_RLX_BITMAP_1 0xC72514 + +#define mmPSOC_PCI_PLL_RLX_BITMAP_2 0xC72518 + +#define mmPSOC_PCI_PLL_RLX_BITMAP_3 0xC7251C + +#endif /* ASIC_REG_PSOC_PCI_PLL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_timestamp_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_timestamp_regs.h new file mode 100644 index 000000000000..9ce24597d4b0 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_timestamp_regs.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_TIMESTAMP_REGS_H_ +#define ASIC_REG_PSOC_TIMESTAMP_REGS_H_ + +/* + ***************************************** + * PSOC_TIMESTAMP (Prototype: TIMESTAMP) + ***************************************** + */ + +#define mmPSOC_TIMESTAMP_CNTCR 0xC49000 + +#define mmPSOC_TIMESTAMP_CNTSR 0xC49004 + +#define mmPSOC_TIMESTAMP_CNTCVL 0xC49008 + +#define mmPSOC_TIMESTAMP_CNTCVU 0xC4900C + +#define mmPSOC_TIMESTAMP_CNTFID0 0xC49020 + +#define mmPSOC_TIMESTAMP_PIDR4 0xC49FD0 + +#define mmPSOC_TIMESTAMP_PIDR5 0xC49FD4 + +#define mmPSOC_TIMESTAMP_PIDR6 0xC49FD8 + +#define mmPSOC_TIMESTAMP_PIDR7 0xC49FDC + +#define mmPSOC_TIMESTAMP_PIDR0 0xC49FE0 + +#define mmPSOC_TIMESTAMP_PIDR1 0xC49FE4 + +#define mmPSOC_TIMESTAMP_PIDR2 0xC49FE8 + +#define mmPSOC_TIMESTAMP_PIDR3 0xC49FEC + +#define mmPSOC_TIMESTAMP_CIDR0 0xC49FF0 + +#define mmPSOC_TIMESTAMP_CIDR1 0xC49FF4 + +#define mmPSOC_TIMESTAMP_CIDR2 0xC49FF8 + +#define mmPSOC_TIMESTAMP_CIDR3 0xC49FFC + +#endif /* ASIC_REG_PSOC_TIMESTAMP_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_0_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_0_regs.h new file mode 100644 index 000000000000..ddf824392cf7 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_0_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SIF_RTR_CTRL_0_REGS_H_ +#define ASIC_REG_SIF_RTR_CTRL_0_REGS_H_ + +/* + ***************************************** + * SIF_RTR_CTRL_0 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmSIF_RTR_CTRL_0_PERM_SEL 0x306108 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_0 0x306114 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_1 0x306118 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_2 0x30611C + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_3 0x306120 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_4 0x306124 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_5 0x306128 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_6 0x30612C + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_7 0x306130 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_8 0x306134 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_9 0x306138 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_10 0x30613C + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_11 0x306140 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_12 0x306144 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_13 0x306148 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_14 0x30614C + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_15 0x306150 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_16 0x306154 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_17 0x306158 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_18 0x30615C + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_19 0x306160 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_20 0x306164 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_21 0x306168 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_22 0x30616C + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_23 0x306170 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_24 0x306174 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_25 0x306178 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_26 0x30617C + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_27 0x306180 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_0 0x306184 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_1 0x306188 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_2 0x30618C + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_3 0x306190 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_4 0x306194 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_5 0x306198 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_6 0x30619C + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_7 0x3061A0 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_8 0x3061A4 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_9 0x3061A8 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_10 0x3061AC + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_11 0x3061B0 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_12 0x3061B4 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_13 0x3061B8 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_14 0x3061BC + +#define mmSIF_RTR_CTRL_0_SCRAM_SRAM_EN 0x30626C + +#define mmSIF_RTR_CTRL_0_RL_HBM_EN 0x306274 + +#define mmSIF_RTR_CTRL_0_RL_HBM_SAT 0x306278 + +#define mmSIF_RTR_CTRL_0_RL_HBM_RST 0x30627C + +#define mmSIF_RTR_CTRL_0_RL_HBM_TIMEOUT 0x306280 + +#define mmSIF_RTR_CTRL_0_SCRAM_HBM_EN 0x306284 + +#define mmSIF_RTR_CTRL_0_RL_PCI_EN 0x306288 + +#define mmSIF_RTR_CTRL_0_RL_PCI_SAT 0x30628C + +#define mmSIF_RTR_CTRL_0_RL_PCI_RST 0x306290 + +#define mmSIF_RTR_CTRL_0_RL_PCI_TIMEOUT 0x306294 + +#define mmSIF_RTR_CTRL_0_RL_SRAM_EN 0x30629C + +#define mmSIF_RTR_CTRL_0_RL_SRAM_SAT 0x3062A0 + +#define mmSIF_RTR_CTRL_0_RL_SRAM_RST 0x3062A4 + +#define mmSIF_RTR_CTRL_0_RL_SRAM_TIMEOUT 0x3062AC + +#define mmSIF_RTR_CTRL_0_RL_SRAM_RED 0x3062B4 + +#define mmSIF_RTR_CTRL_0_E2E_HBM_EN 0x3062EC + +#define mmSIF_RTR_CTRL_0_E2E_PCI_EN 0x3062F0 + +#define mmSIF_RTR_CTRL_0_E2E_HBM_WR_SIZE 0x3062F4 + +#define mmSIF_RTR_CTRL_0_E2E_PCI_WR_SIZE 0x3062F8 + +#define mmSIF_RTR_CTRL_0_E2E_AW_PCI_CTR_SET_EN 0x306404 + +#define mmSIF_RTR_CTRL_0_E2E_AW_PCI_CTR_SET 0x306408 + +#define mmSIF_RTR_CTRL_0_E2E_AW_PCI_CTR_WRAP 0x30640C + +#define mmSIF_RTR_CTRL_0_E2E_AW_PCI_CTR_CNT 0x306410 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM_CTR_SET_EN 0x306414 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM_CTR_SET 0x306418 + +#define mmSIF_RTR_CTRL_0_E2E_HBM_RD_SIZE 0x30641C + +#define mmSIF_RTR_CTRL_0_E2E_PCI_RD_SIZE 0x306420 + +#define mmSIF_RTR_CTRL_0_E2E_AR_PCI_CTR_SET_EN 0x306424 + +#define mmSIF_RTR_CTRL_0_E2E_AR_PCI_CTR_SET 0x306428 + +#define mmSIF_RTR_CTRL_0_E2E_AR_PCI_CTR_WRAP 0x30642C + +#define mmSIF_RTR_CTRL_0_E2E_AR_PCI_CTR_CNT 0x306430 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM_CTR_SET_EN 0x306434 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM_CTR_SET 0x306438 + +#define mmSIF_RTR_CTRL_0_NL_HBM_SEL_0 0x306450 + +#define mmSIF_RTR_CTRL_0_NL_HBM_SEL_1 0x306454 + +#define mmSIF_RTR_CTRL_0_NON_LIN_EN 0x306480 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_BANK_0 0x306500 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_BANK_1 0x306504 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_BANK_2 0x306508 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_BANK_3 0x30650C + +#define mmSIF_RTR_CTRL_0_NL_SRAM_BANK_4 0x306510 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_0 0x306514 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_1 0x306520 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_2 0x306524 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_3 0x306528 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_4 0x30652C + +#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_5 0x306530 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_6 0x306534 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_7 0x306538 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_8 0x30653C + +#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_9 0x306540 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_0 0x306550 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_1 0x306554 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_2 0x306558 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_3 0x30655C + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_4 0x306560 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_5 0x306564 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_6 0x306568 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_7 0x30656C + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_8 0x306570 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_9 0x306574 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_10 0x306578 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_11 0x30657C + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_12 0x306580 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_13 0x306584 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_14 0x306588 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_15 0x30658C + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_16 0x306590 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_17 0x306594 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_18 0x306598 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_0 0x3065E4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_1 0x3065E8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_2 0x3065EC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_3 0x3065F0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_4 0x3065F4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_5 0x3065F8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_6 0x3065FC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_7 0x306600 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_8 0x306604 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_9 0x306608 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_10 0x30660C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_11 0x306610 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_12 0x306614 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_13 0x306618 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_14 0x30661C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_15 0x306620 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_0 0x306624 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_1 0x306628 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_2 0x30662C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_3 0x306630 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_4 0x306634 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_5 0x306638 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_6 0x30663C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_7 0x306640 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_8 0x306644 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_9 0x306648 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_10 0x30664C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_11 0x306650 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_12 0x306654 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_13 0x306658 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_14 0x30665C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_15 0x306660 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_0 0x306664 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_1 0x306668 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_2 0x30666C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_3 0x306670 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_4 0x306674 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_5 0x306678 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_6 0x30667C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_7 0x306680 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_8 0x306684 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_9 0x306688 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_10 0x30668C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_11 0x306690 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_12 0x306694 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_13 0x306698 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_14 0x30669C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_15 0x3066A0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_0 0x3066A4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_1 0x3066A8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_2 0x3066AC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_3 0x3066B0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_4 0x3066B4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_5 0x3066B8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_6 0x3066BC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_7 0x3066C0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_8 0x3066C4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_9 0x3066C8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_10 0x3066CC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_11 0x3066D0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_12 0x3066D4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_13 0x3066D8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_14 0x3066DC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_15 0x3066E0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_0 0x3066E4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_1 0x3066E8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_2 0x3066EC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_3 0x3066F0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_4 0x3066F4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_5 0x3066F8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_6 0x3066FC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_7 0x306700 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_8 0x306704 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_9 0x306708 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_10 0x30670C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_11 0x306710 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_12 0x306714 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_13 0x306718 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_14 0x30671C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_15 0x306720 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_0 0x306724 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_1 0x306728 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_2 0x30672C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_3 0x306730 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_4 0x306734 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_5 0x306738 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_6 0x30673C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_7 0x306740 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_8 0x306744 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_9 0x306748 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_10 0x30674C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_11 0x306750 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_12 0x306754 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_13 0x306758 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_14 0x30675C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_15 0x306760 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_0 0x306764 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_1 0x306768 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_2 0x30676C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_3 0x306770 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_4 0x306774 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_5 0x306778 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_6 0x30677C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_7 0x306780 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_8 0x306784 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_9 0x306788 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_10 0x30678C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_11 0x306790 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_12 0x306794 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_13 0x306798 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_14 0x30679C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_15 0x3067A0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_0 0x3067A4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_1 0x3067A8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_2 0x3067AC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_3 0x3067B0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_4 0x3067B4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_5 0x3067B8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_6 0x3067BC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_7 0x3067C0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_8 0x3067C4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_9 0x3067C8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_10 0x3067CC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_11 0x3067D0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_12 0x3067D4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_13 0x3067D8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_14 0x3067DC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_15 0x3067E0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_0 0x306824 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_1 0x306828 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_2 0x30682C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_3 0x306830 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_4 0x306834 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_5 0x306838 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_6 0x30683C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_7 0x306840 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_8 0x306844 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_9 0x306848 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_10 0x30684C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_11 0x306850 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_12 0x306854 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_13 0x306858 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_14 0x30685C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_15 0x306860 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_0 0x306864 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_1 0x306868 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_2 0x30686C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_3 0x306870 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_4 0x306874 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_5 0x306878 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_6 0x30687C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_7 0x306880 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_8 0x306884 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_9 0x306888 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_10 0x30688C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_11 0x306890 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_12 0x306894 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_13 0x306898 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_14 0x30689C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_15 0x3068A0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_0 0x3068A4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_1 0x3068A8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_2 0x3068AC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_3 0x3068B0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_4 0x3068B4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_5 0x3068B8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_6 0x3068BC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_7 0x3068C0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_8 0x3068C4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_9 0x3068C8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_10 0x3068CC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_11 0x3068D0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_12 0x3068D4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_13 0x3068D8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_14 0x3068DC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_15 0x3068E0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_0 0x3068E4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_1 0x3068E8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_2 0x3068EC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_3 0x3068F0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_4 0x3068F4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_5 0x3068F8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_6 0x3068FC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_7 0x306900 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_8 0x306904 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_9 0x306908 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_10 0x30690C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_11 0x306910 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_12 0x306914 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_13 0x306918 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_14 0x30691C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_15 0x306920 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_0 0x306924 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_1 0x306928 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_2 0x30692C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_3 0x306930 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_4 0x306934 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_5 0x306938 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_6 0x30693C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_7 0x306940 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_8 0x306944 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_9 0x306948 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_10 0x30694C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_11 0x306950 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_12 0x306954 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_13 0x306958 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_14 0x30695C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_15 0x306960 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_0 0x306964 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_1 0x306968 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_2 0x30696C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_3 0x306970 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_4 0x306974 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_5 0x306978 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_6 0x30697C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_7 0x306980 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_8 0x306984 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_9 0x306988 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_10 0x30698C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_11 0x306990 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_12 0x306994 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_13 0x306998 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_14 0x30699C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_15 0x3069A0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_0 0x3069A4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_1 0x3069A8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_2 0x3069AC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_3 0x3069B0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_4 0x3069B4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_5 0x3069B8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_6 0x3069BC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_7 0x3069C0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_8 0x3069C4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_9 0x3069C8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_10 0x3069CC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_11 0x3069D0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_12 0x3069D4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_13 0x3069D8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_14 0x3069DC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_15 0x3069E0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_0 0x3069E4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_1 0x3069E8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_2 0x3069EC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_3 0x3069F0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_4 0x3069F4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_5 0x3069F8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_6 0x3069FC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_7 0x306A00 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_8 0x306A04 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_9 0x306A08 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_10 0x306A0C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_11 0x306A10 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_12 0x306A14 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_13 0x306A18 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_14 0x306A1C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_15 0x306A20 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_HIT_AW 0x306A64 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_HIT_AR 0x306A68 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_HIT_AW 0x306A6C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_HIT_AR 0x306A70 + +#define mmSIF_RTR_CTRL_0_RGL_CFG 0x306B64 + +#define mmSIF_RTR_CTRL_0_RGL_SHIFT 0x306B68 + +#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_0 0x306B6C + +#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_1 0x306B70 + +#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_2 0x306B74 + +#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_3 0x306B78 + +#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_4 0x306B7C + +#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_5 0x306B80 + +#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_6 0x306B84 + +#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_7 0x306B88 + +#define mmSIF_RTR_CTRL_0_RGL_TOKEN_0 0x306BAC + +#define mmSIF_RTR_CTRL_0_RGL_TOKEN_1 0x306BB0 + +#define mmSIF_RTR_CTRL_0_RGL_TOKEN_2 0x306BB4 + +#define mmSIF_RTR_CTRL_0_RGL_TOKEN_3 0x306BB8 + +#define mmSIF_RTR_CTRL_0_RGL_TOKEN_4 0x306BBC + +#define mmSIF_RTR_CTRL_0_RGL_TOKEN_5 0x306BC0 + +#define mmSIF_RTR_CTRL_0_RGL_TOKEN_6 0x306BC4 + +#define mmSIF_RTR_CTRL_0_RGL_TOKEN_7 0x306BC8 + +#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_0 0x306BEC + +#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_1 0x306BF0 + +#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_2 0x306BF4 + +#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_3 0x306BF8 + +#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_4 0x306BFC + +#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_5 0x306C00 + +#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_6 0x306C04 + +#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_7 0x306C08 + +#define mmSIF_RTR_CTRL_0_RGL_WDT 0x306C2C + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM0_CH0_CTR_WRAP 0x306C30 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM0_CH1_CTR_WRAP 0x306C34 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM1_CH0_CTR_WRAP 0x306C38 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM1_CH1_CTR_WRAP 0x306C3C + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM2_CH0_CTR_WRAP 0x306C40 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM2_CH1_CTR_WRAP 0x306C44 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM3_CH0_CTR_WRAP 0x306C48 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM3_CH1_CTR_WRAP 0x306C4C + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM0_CH0_CTR_CNT 0x306C50 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM0_CH1_CTR_CNT 0x306C54 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM1_CH0_CTR_CNT 0x306C58 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM1_CH1_CTR_CNT 0x306C5C + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM2_CH0_CTR_CNT 0x306C60 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM2_CH1_CTR_CNT 0x306C64 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM3_CH0_CTR_CNT 0x306C68 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM3_CH1_CTR_CNT 0x306C6C + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM0_CH0_CTR_WRAP 0x306C70 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM0_CH1_CTR_WRAP 0x306C74 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM1_CH0_CTR_WRAP 0x306C78 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM1_CH1_CTR_WRAP 0x306C7C + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM2_CH0_CTR_WRAP 0x306C80 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM2_CH1_CTR_WRAP 0x306C84 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM3_CH0_CTR_WRAP 0x306C88 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM3_CH1_CTR_WRAP 0x306C8C + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM0_CH0_CTR_CNT 0x306C90 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM0_CH1_CTR_CNT 0x306C94 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM1_CH0_CTR_CNT 0x306C98 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM1_CH1_CTR_CNT 0x306C9C + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM2_CH0_CTR_CNT 0x306CA0 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM2_CH1_CTR_CNT 0x306CA4 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM3_CH0_CTR_CNT 0x306CA8 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM3_CH1_CTR_CNT 0x306CAC + +#define mmSIF_RTR_CTRL_0_NL_HBM_PC_SEL_0 0x306CB0 + +#define mmSIF_RTR_CTRL_0_NL_HBM_PC_SEL_1 0x306CB4 + +#define mmSIF_RTR_CTRL_0_NL_HBM_PC_SEL_2 0x306CB8 + +#define mmSIF_RTR_CTRL_0_NL_HBM_PC_SEL_3 0x306CBC + +#endif /* ASIC_REG_SIF_RTR_CTRL_0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_1_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_1_regs.h new file mode 100644 index 000000000000..c6d517dbbd54 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_1_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SIF_RTR_CTRL_1_REGS_H_ +#define ASIC_REG_SIF_RTR_CTRL_1_REGS_H_ + +/* + ***************************************** + * SIF_RTR_CTRL_1 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmSIF_RTR_CTRL_1_PERM_SEL 0x316108 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_0 0x316114 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_1 0x316118 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_2 0x31611C + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_3 0x316120 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_4 0x316124 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_5 0x316128 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_6 0x31612C + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_7 0x316130 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_8 0x316134 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_9 0x316138 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_10 0x31613C + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_11 0x316140 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_12 0x316144 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_13 0x316148 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_14 0x31614C + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_15 0x316150 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_16 0x316154 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_17 0x316158 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_18 0x31615C + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_19 0x316160 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_20 0x316164 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_21 0x316168 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_22 0x31616C + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_23 0x316170 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_24 0x316174 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_25 0x316178 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_26 0x31617C + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_27 0x316180 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_0 0x316184 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_1 0x316188 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_2 0x31618C + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_3 0x316190 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_4 0x316194 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_5 0x316198 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_6 0x31619C + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_7 0x3161A0 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_8 0x3161A4 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_9 0x3161A8 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_10 0x3161AC + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_11 0x3161B0 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_12 0x3161B4 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_13 0x3161B8 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_14 0x3161BC + +#define mmSIF_RTR_CTRL_1_SCRAM_SRAM_EN 0x31626C + +#define mmSIF_RTR_CTRL_1_RL_HBM_EN 0x316274 + +#define mmSIF_RTR_CTRL_1_RL_HBM_SAT 0x316278 + +#define mmSIF_RTR_CTRL_1_RL_HBM_RST 0x31627C + +#define mmSIF_RTR_CTRL_1_RL_HBM_TIMEOUT 0x316280 + +#define mmSIF_RTR_CTRL_1_SCRAM_HBM_EN 0x316284 + +#define mmSIF_RTR_CTRL_1_RL_PCI_EN 0x316288 + +#define mmSIF_RTR_CTRL_1_RL_PCI_SAT 0x31628C + +#define mmSIF_RTR_CTRL_1_RL_PCI_RST 0x316290 + +#define mmSIF_RTR_CTRL_1_RL_PCI_TIMEOUT 0x316294 + +#define mmSIF_RTR_CTRL_1_RL_SRAM_EN 0x31629C + +#define mmSIF_RTR_CTRL_1_RL_SRAM_SAT 0x3162A0 + +#define mmSIF_RTR_CTRL_1_RL_SRAM_RST 0x3162A4 + +#define mmSIF_RTR_CTRL_1_RL_SRAM_TIMEOUT 0x3162AC + +#define mmSIF_RTR_CTRL_1_RL_SRAM_RED 0x3162B4 + +#define mmSIF_RTR_CTRL_1_E2E_HBM_EN 0x3162EC + +#define mmSIF_RTR_CTRL_1_E2E_PCI_EN 0x3162F0 + +#define mmSIF_RTR_CTRL_1_E2E_HBM_WR_SIZE 0x3162F4 + +#define mmSIF_RTR_CTRL_1_E2E_PCI_WR_SIZE 0x3162F8 + +#define mmSIF_RTR_CTRL_1_E2E_AW_PCI_CTR_SET_EN 0x316404 + +#define mmSIF_RTR_CTRL_1_E2E_AW_PCI_CTR_SET 0x316408 + +#define mmSIF_RTR_CTRL_1_E2E_AW_PCI_CTR_WRAP 0x31640C + +#define mmSIF_RTR_CTRL_1_E2E_AW_PCI_CTR_CNT 0x316410 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM_CTR_SET_EN 0x316414 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM_CTR_SET 0x316418 + +#define mmSIF_RTR_CTRL_1_E2E_HBM_RD_SIZE 0x31641C + +#define mmSIF_RTR_CTRL_1_E2E_PCI_RD_SIZE 0x316420 + +#define mmSIF_RTR_CTRL_1_E2E_AR_PCI_CTR_SET_EN 0x316424 + +#define mmSIF_RTR_CTRL_1_E2E_AR_PCI_CTR_SET 0x316428 + +#define mmSIF_RTR_CTRL_1_E2E_AR_PCI_CTR_WRAP 0x31642C + +#define mmSIF_RTR_CTRL_1_E2E_AR_PCI_CTR_CNT 0x316430 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM_CTR_SET_EN 0x316434 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM_CTR_SET 0x316438 + +#define mmSIF_RTR_CTRL_1_NL_HBM_SEL_0 0x316450 + +#define mmSIF_RTR_CTRL_1_NL_HBM_SEL_1 0x316454 + +#define mmSIF_RTR_CTRL_1_NON_LIN_EN 0x316480 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_BANK_0 0x316500 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_BANK_1 0x316504 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_BANK_2 0x316508 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_BANK_3 0x31650C + +#define mmSIF_RTR_CTRL_1_NL_SRAM_BANK_4 0x316510 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_0 0x316514 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_1 0x316520 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_2 0x316524 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_3 0x316528 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_4 0x31652C + +#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_5 0x316530 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_6 0x316534 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_7 0x316538 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_8 0x31653C + +#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_9 0x316540 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_0 0x316550 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_1 0x316554 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_2 0x316558 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_3 0x31655C + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_4 0x316560 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_5 0x316564 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_6 0x316568 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_7 0x31656C + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_8 0x316570 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_9 0x316574 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_10 0x316578 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_11 0x31657C + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_12 0x316580 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_13 0x316584 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_14 0x316588 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_15 0x31658C + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_16 0x316590 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_17 0x316594 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_18 0x316598 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_0 0x3165E4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_1 0x3165E8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_2 0x3165EC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_3 0x3165F0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_4 0x3165F4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_5 0x3165F8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_6 0x3165FC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_7 0x316600 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_8 0x316604 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_9 0x316608 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_10 0x31660C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_11 0x316610 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_12 0x316614 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_13 0x316618 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_14 0x31661C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_15 0x316620 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_0 0x316624 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_1 0x316628 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_2 0x31662C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_3 0x316630 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_4 0x316634 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_5 0x316638 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_6 0x31663C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_7 0x316640 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_8 0x316644 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_9 0x316648 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_10 0x31664C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_11 0x316650 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_12 0x316654 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_13 0x316658 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_14 0x31665C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_15 0x316660 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_0 0x316664 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_1 0x316668 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_2 0x31666C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_3 0x316670 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_4 0x316674 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_5 0x316678 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_6 0x31667C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_7 0x316680 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_8 0x316684 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_9 0x316688 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_10 0x31668C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_11 0x316690 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_12 0x316694 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_13 0x316698 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_14 0x31669C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_15 0x3166A0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_0 0x3166A4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_1 0x3166A8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_2 0x3166AC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_3 0x3166B0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_4 0x3166B4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_5 0x3166B8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_6 0x3166BC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_7 0x3166C0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_8 0x3166C4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_9 0x3166C8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_10 0x3166CC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_11 0x3166D0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_12 0x3166D4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_13 0x3166D8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_14 0x3166DC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_15 0x3166E0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_0 0x3166E4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_1 0x3166E8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_2 0x3166EC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_3 0x3166F0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_4 0x3166F4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_5 0x3166F8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_6 0x3166FC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_7 0x316700 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_8 0x316704 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_9 0x316708 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_10 0x31670C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_11 0x316710 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_12 0x316714 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_13 0x316718 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_14 0x31671C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_15 0x316720 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_0 0x316724 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_1 0x316728 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_2 0x31672C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_3 0x316730 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_4 0x316734 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_5 0x316738 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_6 0x31673C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_7 0x316740 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_8 0x316744 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_9 0x316748 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_10 0x31674C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_11 0x316750 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_12 0x316754 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_13 0x316758 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_14 0x31675C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_15 0x316760 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_0 0x316764 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_1 0x316768 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_2 0x31676C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_3 0x316770 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_4 0x316774 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_5 0x316778 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_6 0x31677C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_7 0x316780 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_8 0x316784 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_9 0x316788 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_10 0x31678C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_11 0x316790 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_12 0x316794 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_13 0x316798 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_14 0x31679C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_15 0x3167A0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_0 0x3167A4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_1 0x3167A8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_2 0x3167AC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_3 0x3167B0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_4 0x3167B4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_5 0x3167B8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_6 0x3167BC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_7 0x3167C0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_8 0x3167C4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_9 0x3167C8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_10 0x3167CC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_11 0x3167D0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_12 0x3167D4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_13 0x3167D8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_14 0x3167DC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_15 0x3167E0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_0 0x316824 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_1 0x316828 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_2 0x31682C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_3 0x316830 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_4 0x316834 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_5 0x316838 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_6 0x31683C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_7 0x316840 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_8 0x316844 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_9 0x316848 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_10 0x31684C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_11 0x316850 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_12 0x316854 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_13 0x316858 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_14 0x31685C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_15 0x316860 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_0 0x316864 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_1 0x316868 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_2 0x31686C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_3 0x316870 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_4 0x316874 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_5 0x316878 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_6 0x31687C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_7 0x316880 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_8 0x316884 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_9 0x316888 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_10 0x31688C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_11 0x316890 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_12 0x316894 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_13 0x316898 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_14 0x31689C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_15 0x3168A0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_0 0x3168A4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_1 0x3168A8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_2 0x3168AC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_3 0x3168B0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_4 0x3168B4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_5 0x3168B8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_6 0x3168BC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_7 0x3168C0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_8 0x3168C4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_9 0x3168C8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_10 0x3168CC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_11 0x3168D0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_12 0x3168D4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_13 0x3168D8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_14 0x3168DC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_15 0x3168E0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_0 0x3168E4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_1 0x3168E8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_2 0x3168EC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_3 0x3168F0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_4 0x3168F4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_5 0x3168F8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_6 0x3168FC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_7 0x316900 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_8 0x316904 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_9 0x316908 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_10 0x31690C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_11 0x316910 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_12 0x316914 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_13 0x316918 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_14 0x31691C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_15 0x316920 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_0 0x316924 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_1 0x316928 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_2 0x31692C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_3 0x316930 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_4 0x316934 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_5 0x316938 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_6 0x31693C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_7 0x316940 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_8 0x316944 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_9 0x316948 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_10 0x31694C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_11 0x316950 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_12 0x316954 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_13 0x316958 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_14 0x31695C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_15 0x316960 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_0 0x316964 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_1 0x316968 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_2 0x31696C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_3 0x316970 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_4 0x316974 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_5 0x316978 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_6 0x31697C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_7 0x316980 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_8 0x316984 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_9 0x316988 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_10 0x31698C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_11 0x316990 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_12 0x316994 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_13 0x316998 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_14 0x31699C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_15 0x3169A0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_0 0x3169A4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_1 0x3169A8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_2 0x3169AC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_3 0x3169B0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_4 0x3169B4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_5 0x3169B8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_6 0x3169BC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_7 0x3169C0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_8 0x3169C4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_9 0x3169C8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_10 0x3169CC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_11 0x3169D0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_12 0x3169D4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_13 0x3169D8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_14 0x3169DC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_15 0x3169E0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_0 0x3169E4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_1 0x3169E8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_2 0x3169EC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_3 0x3169F0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_4 0x3169F4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_5 0x3169F8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_6 0x3169FC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_7 0x316A00 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_8 0x316A04 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_9 0x316A08 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_10 0x316A0C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_11 0x316A10 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_12 0x316A14 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_13 0x316A18 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_14 0x316A1C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_15 0x316A20 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_HIT_AW 0x316A64 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_HIT_AR 0x316A68 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_HIT_AW 0x316A6C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_HIT_AR 0x316A70 + +#define mmSIF_RTR_CTRL_1_RGL_CFG 0x316B64 + +#define mmSIF_RTR_CTRL_1_RGL_SHIFT 0x316B68 + +#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_0 0x316B6C + +#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_1 0x316B70 + +#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_2 0x316B74 + +#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_3 0x316B78 + +#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_4 0x316B7C + +#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_5 0x316B80 + +#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_6 0x316B84 + +#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_7 0x316B88 + +#define mmSIF_RTR_CTRL_1_RGL_TOKEN_0 0x316BAC + +#define mmSIF_RTR_CTRL_1_RGL_TOKEN_1 0x316BB0 + +#define mmSIF_RTR_CTRL_1_RGL_TOKEN_2 0x316BB4 + +#define mmSIF_RTR_CTRL_1_RGL_TOKEN_3 0x316BB8 + +#define mmSIF_RTR_CTRL_1_RGL_TOKEN_4 0x316BBC + +#define mmSIF_RTR_CTRL_1_RGL_TOKEN_5 0x316BC0 + +#define mmSIF_RTR_CTRL_1_RGL_TOKEN_6 0x316BC4 + +#define mmSIF_RTR_CTRL_1_RGL_TOKEN_7 0x316BC8 + +#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_0 0x316BEC + +#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_1 0x316BF0 + +#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_2 0x316BF4 + +#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_3 0x316BF8 + +#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_4 0x316BFC + +#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_5 0x316C00 + +#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_6 0x316C04 + +#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_7 0x316C08 + +#define mmSIF_RTR_CTRL_1_RGL_WDT 0x316C2C + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM0_CH0_CTR_WRAP 0x316C30 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM0_CH1_CTR_WRAP 0x316C34 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM1_CH0_CTR_WRAP 0x316C38 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM1_CH1_CTR_WRAP 0x316C3C + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM2_CH0_CTR_WRAP 0x316C40 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM2_CH1_CTR_WRAP 0x316C44 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM3_CH0_CTR_WRAP 0x316C48 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM3_CH1_CTR_WRAP 0x316C4C + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM0_CH0_CTR_CNT 0x316C50 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM0_CH1_CTR_CNT 0x316C54 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM1_CH0_CTR_CNT 0x316C58 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM1_CH1_CTR_CNT 0x316C5C + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM2_CH0_CTR_CNT 0x316C60 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM2_CH1_CTR_CNT 0x316C64 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM3_CH0_CTR_CNT 0x316C68 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM3_CH1_CTR_CNT 0x316C6C + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM0_CH0_CTR_WRAP 0x316C70 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM0_CH1_CTR_WRAP 0x316C74 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM1_CH0_CTR_WRAP 0x316C78 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM1_CH1_CTR_WRAP 0x316C7C + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM2_CH0_CTR_WRAP 0x316C80 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM2_CH1_CTR_WRAP 0x316C84 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM3_CH0_CTR_WRAP 0x316C88 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM3_CH1_CTR_WRAP 0x316C8C + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM0_CH0_CTR_CNT 0x316C90 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM0_CH1_CTR_CNT 0x316C94 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM1_CH0_CTR_CNT 0x316C98 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM1_CH1_CTR_CNT 0x316C9C + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM2_CH0_CTR_CNT 0x316CA0 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM2_CH1_CTR_CNT 0x316CA4 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM3_CH0_CTR_CNT 0x316CA8 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM3_CH1_CTR_CNT 0x316CAC + +#define mmSIF_RTR_CTRL_1_NL_HBM_PC_SEL_0 0x316CB0 + +#define mmSIF_RTR_CTRL_1_NL_HBM_PC_SEL_1 0x316CB4 + +#define mmSIF_RTR_CTRL_1_NL_HBM_PC_SEL_2 0x316CB8 + +#define mmSIF_RTR_CTRL_1_NL_HBM_PC_SEL_3 0x316CBC + +#endif /* ASIC_REG_SIF_RTR_CTRL_1_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_2_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_2_regs.h new file mode 100644 index 000000000000..330e5b42d679 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_2_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SIF_RTR_CTRL_2_REGS_H_ +#define ASIC_REG_SIF_RTR_CTRL_2_REGS_H_ + +/* + ***************************************** + * SIF_RTR_CTRL_2 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmSIF_RTR_CTRL_2_PERM_SEL 0x326108 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_0 0x326114 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_1 0x326118 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_2 0x32611C + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_3 0x326120 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_4 0x326124 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_5 0x326128 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_6 0x32612C + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_7 0x326130 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_8 0x326134 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_9 0x326138 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_10 0x32613C + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_11 0x326140 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_12 0x326144 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_13 0x326148 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_14 0x32614C + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_15 0x326150 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_16 0x326154 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_17 0x326158 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_18 0x32615C + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_19 0x326160 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_20 0x326164 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_21 0x326168 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_22 0x32616C + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_23 0x326170 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_24 0x326174 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_25 0x326178 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_26 0x32617C + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_27 0x326180 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_0 0x326184 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_1 0x326188 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_2 0x32618C + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_3 0x326190 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_4 0x326194 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_5 0x326198 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_6 0x32619C + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_7 0x3261A0 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_8 0x3261A4 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_9 0x3261A8 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_10 0x3261AC + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_11 0x3261B0 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_12 0x3261B4 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_13 0x3261B8 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_14 0x3261BC + +#define mmSIF_RTR_CTRL_2_SCRAM_SRAM_EN 0x32626C + +#define mmSIF_RTR_CTRL_2_RL_HBM_EN 0x326274 + +#define mmSIF_RTR_CTRL_2_RL_HBM_SAT 0x326278 + +#define mmSIF_RTR_CTRL_2_RL_HBM_RST 0x32627C + +#define mmSIF_RTR_CTRL_2_RL_HBM_TIMEOUT 0x326280 + +#define mmSIF_RTR_CTRL_2_SCRAM_HBM_EN 0x326284 + +#define mmSIF_RTR_CTRL_2_RL_PCI_EN 0x326288 + +#define mmSIF_RTR_CTRL_2_RL_PCI_SAT 0x32628C + +#define mmSIF_RTR_CTRL_2_RL_PCI_RST 0x326290 + +#define mmSIF_RTR_CTRL_2_RL_PCI_TIMEOUT 0x326294 + +#define mmSIF_RTR_CTRL_2_RL_SRAM_EN 0x32629C + +#define mmSIF_RTR_CTRL_2_RL_SRAM_SAT 0x3262A0 + +#define mmSIF_RTR_CTRL_2_RL_SRAM_RST 0x3262A4 + +#define mmSIF_RTR_CTRL_2_RL_SRAM_TIMEOUT 0x3262AC + +#define mmSIF_RTR_CTRL_2_RL_SRAM_RED 0x3262B4 + +#define mmSIF_RTR_CTRL_2_E2E_HBM_EN 0x3262EC + +#define mmSIF_RTR_CTRL_2_E2E_PCI_EN 0x3262F0 + +#define mmSIF_RTR_CTRL_2_E2E_HBM_WR_SIZE 0x3262F4 + +#define mmSIF_RTR_CTRL_2_E2E_PCI_WR_SIZE 0x3262F8 + +#define mmSIF_RTR_CTRL_2_E2E_AW_PCI_CTR_SET_EN 0x326404 + +#define mmSIF_RTR_CTRL_2_E2E_AW_PCI_CTR_SET 0x326408 + +#define mmSIF_RTR_CTRL_2_E2E_AW_PCI_CTR_WRAP 0x32640C + +#define mmSIF_RTR_CTRL_2_E2E_AW_PCI_CTR_CNT 0x326410 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM_CTR_SET_EN 0x326414 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM_CTR_SET 0x326418 + +#define mmSIF_RTR_CTRL_2_E2E_HBM_RD_SIZE 0x32641C + +#define mmSIF_RTR_CTRL_2_E2E_PCI_RD_SIZE 0x326420 + +#define mmSIF_RTR_CTRL_2_E2E_AR_PCI_CTR_SET_EN 0x326424 + +#define mmSIF_RTR_CTRL_2_E2E_AR_PCI_CTR_SET 0x326428 + +#define mmSIF_RTR_CTRL_2_E2E_AR_PCI_CTR_WRAP 0x32642C + +#define mmSIF_RTR_CTRL_2_E2E_AR_PCI_CTR_CNT 0x326430 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM_CTR_SET_EN 0x326434 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM_CTR_SET 0x326438 + +#define mmSIF_RTR_CTRL_2_NL_HBM_SEL_0 0x326450 + +#define mmSIF_RTR_CTRL_2_NL_HBM_SEL_1 0x326454 + +#define mmSIF_RTR_CTRL_2_NON_LIN_EN 0x326480 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_BANK_0 0x326500 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_BANK_1 0x326504 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_BANK_2 0x326508 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_BANK_3 0x32650C + +#define mmSIF_RTR_CTRL_2_NL_SRAM_BANK_4 0x326510 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_0 0x326514 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_1 0x326520 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_2 0x326524 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_3 0x326528 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_4 0x32652C + +#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_5 0x326530 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_6 0x326534 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_7 0x326538 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_8 0x32653C + +#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_9 0x326540 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_0 0x326550 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_1 0x326554 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_2 0x326558 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_3 0x32655C + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_4 0x326560 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_5 0x326564 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_6 0x326568 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_7 0x32656C + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_8 0x326570 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_9 0x326574 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_10 0x326578 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_11 0x32657C + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_12 0x326580 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_13 0x326584 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_14 0x326588 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_15 0x32658C + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_16 0x326590 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_17 0x326594 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_18 0x326598 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_0 0x3265E4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_1 0x3265E8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_2 0x3265EC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_3 0x3265F0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_4 0x3265F4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_5 0x3265F8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_6 0x3265FC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_7 0x326600 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_8 0x326604 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_9 0x326608 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_10 0x32660C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_11 0x326610 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_12 0x326614 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_13 0x326618 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_14 0x32661C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_15 0x326620 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_0 0x326624 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_1 0x326628 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_2 0x32662C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_3 0x326630 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_4 0x326634 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_5 0x326638 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_6 0x32663C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_7 0x326640 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_8 0x326644 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_9 0x326648 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_10 0x32664C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_11 0x326650 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_12 0x326654 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_13 0x326658 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_14 0x32665C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_15 0x326660 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_0 0x326664 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_1 0x326668 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_2 0x32666C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_3 0x326670 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_4 0x326674 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_5 0x326678 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_6 0x32667C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_7 0x326680 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_8 0x326684 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_9 0x326688 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_10 0x32668C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_11 0x326690 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_12 0x326694 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_13 0x326698 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_14 0x32669C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_15 0x3266A0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_0 0x3266A4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_1 0x3266A8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_2 0x3266AC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_3 0x3266B0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_4 0x3266B4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_5 0x3266B8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_6 0x3266BC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_7 0x3266C0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_8 0x3266C4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_9 0x3266C8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_10 0x3266CC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_11 0x3266D0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_12 0x3266D4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_13 0x3266D8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_14 0x3266DC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_15 0x3266E0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_0 0x3266E4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_1 0x3266E8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_2 0x3266EC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_3 0x3266F0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_4 0x3266F4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_5 0x3266F8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_6 0x3266FC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_7 0x326700 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_8 0x326704 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_9 0x326708 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_10 0x32670C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_11 0x326710 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_12 0x326714 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_13 0x326718 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_14 0x32671C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_15 0x326720 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_0 0x326724 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_1 0x326728 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_2 0x32672C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_3 0x326730 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_4 0x326734 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_5 0x326738 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_6 0x32673C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_7 0x326740 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_8 0x326744 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_9 0x326748 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_10 0x32674C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_11 0x326750 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_12 0x326754 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_13 0x326758 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_14 0x32675C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_15 0x326760 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_0 0x326764 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_1 0x326768 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_2 0x32676C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_3 0x326770 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_4 0x326774 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_5 0x326778 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_6 0x32677C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_7 0x326780 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_8 0x326784 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_9 0x326788 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_10 0x32678C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_11 0x326790 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_12 0x326794 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_13 0x326798 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_14 0x32679C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_15 0x3267A0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_0 0x3267A4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_1 0x3267A8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_2 0x3267AC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_3 0x3267B0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_4 0x3267B4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_5 0x3267B8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_6 0x3267BC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_7 0x3267C0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_8 0x3267C4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_9 0x3267C8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_10 0x3267CC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_11 0x3267D0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_12 0x3267D4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_13 0x3267D8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_14 0x3267DC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_15 0x3267E0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_0 0x326824 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_1 0x326828 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_2 0x32682C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_3 0x326830 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_4 0x326834 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_5 0x326838 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_6 0x32683C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_7 0x326840 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_8 0x326844 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_9 0x326848 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_10 0x32684C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_11 0x326850 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_12 0x326854 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_13 0x326858 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_14 0x32685C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_15 0x326860 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_0 0x326864 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_1 0x326868 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_2 0x32686C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_3 0x326870 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_4 0x326874 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_5 0x326878 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_6 0x32687C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_7 0x326880 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_8 0x326884 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_9 0x326888 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_10 0x32688C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_11 0x326890 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_12 0x326894 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_13 0x326898 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_14 0x32689C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_15 0x3268A0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_0 0x3268A4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_1 0x3268A8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_2 0x3268AC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_3 0x3268B0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_4 0x3268B4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_5 0x3268B8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_6 0x3268BC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_7 0x3268C0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_8 0x3268C4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_9 0x3268C8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_10 0x3268CC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_11 0x3268D0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_12 0x3268D4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_13 0x3268D8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_14 0x3268DC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_15 0x3268E0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_0 0x3268E4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_1 0x3268E8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_2 0x3268EC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_3 0x3268F0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_4 0x3268F4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_5 0x3268F8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_6 0x3268FC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_7 0x326900 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_8 0x326904 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_9 0x326908 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_10 0x32690C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_11 0x326910 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_12 0x326914 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_13 0x326918 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_14 0x32691C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_15 0x326920 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_0 0x326924 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_1 0x326928 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_2 0x32692C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_3 0x326930 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_4 0x326934 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_5 0x326938 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_6 0x32693C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_7 0x326940 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_8 0x326944 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_9 0x326948 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_10 0x32694C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_11 0x326950 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_12 0x326954 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_13 0x326958 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_14 0x32695C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_15 0x326960 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_0 0x326964 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_1 0x326968 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_2 0x32696C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_3 0x326970 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_4 0x326974 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_5 0x326978 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_6 0x32697C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_7 0x326980 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_8 0x326984 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_9 0x326988 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_10 0x32698C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_11 0x326990 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_12 0x326994 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_13 0x326998 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_14 0x32699C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_15 0x3269A0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_0 0x3269A4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_1 0x3269A8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_2 0x3269AC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_3 0x3269B0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_4 0x3269B4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_5 0x3269B8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_6 0x3269BC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_7 0x3269C0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_8 0x3269C4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_9 0x3269C8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_10 0x3269CC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_11 0x3269D0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_12 0x3269D4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_13 0x3269D8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_14 0x3269DC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_15 0x3269E0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_0 0x3269E4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_1 0x3269E8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_2 0x3269EC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_3 0x3269F0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_4 0x3269F4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_5 0x3269F8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_6 0x3269FC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_7 0x326A00 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_8 0x326A04 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_9 0x326A08 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_10 0x326A0C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_11 0x326A10 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_12 0x326A14 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_13 0x326A18 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_14 0x326A1C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_15 0x326A20 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_HIT_AW 0x326A64 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_HIT_AR 0x326A68 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_HIT_AW 0x326A6C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_HIT_AR 0x326A70 + +#define mmSIF_RTR_CTRL_2_RGL_CFG 0x326B64 + +#define mmSIF_RTR_CTRL_2_RGL_SHIFT 0x326B68 + +#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_0 0x326B6C + +#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_1 0x326B70 + +#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_2 0x326B74 + +#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_3 0x326B78 + +#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_4 0x326B7C + +#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_5 0x326B80 + +#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_6 0x326B84 + +#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_7 0x326B88 + +#define mmSIF_RTR_CTRL_2_RGL_TOKEN_0 0x326BAC + +#define mmSIF_RTR_CTRL_2_RGL_TOKEN_1 0x326BB0 + +#define mmSIF_RTR_CTRL_2_RGL_TOKEN_2 0x326BB4 + +#define mmSIF_RTR_CTRL_2_RGL_TOKEN_3 0x326BB8 + +#define mmSIF_RTR_CTRL_2_RGL_TOKEN_4 0x326BBC + +#define mmSIF_RTR_CTRL_2_RGL_TOKEN_5 0x326BC0 + +#define mmSIF_RTR_CTRL_2_RGL_TOKEN_6 0x326BC4 + +#define mmSIF_RTR_CTRL_2_RGL_TOKEN_7 0x326BC8 + +#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_0 0x326BEC + +#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_1 0x326BF0 + +#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_2 0x326BF4 + +#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_3 0x326BF8 + +#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_4 0x326BFC + +#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_5 0x326C00 + +#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_6 0x326C04 + +#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_7 0x326C08 + +#define mmSIF_RTR_CTRL_2_RGL_WDT 0x326C2C + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM0_CH0_CTR_WRAP 0x326C30 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM0_CH1_CTR_WRAP 0x326C34 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM1_CH0_CTR_WRAP 0x326C38 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM1_CH1_CTR_WRAP 0x326C3C + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM2_CH0_CTR_WRAP 0x326C40 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM2_CH1_CTR_WRAP 0x326C44 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM3_CH0_CTR_WRAP 0x326C48 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM3_CH1_CTR_WRAP 0x326C4C + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM0_CH0_CTR_CNT 0x326C50 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM0_CH1_CTR_CNT 0x326C54 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM1_CH0_CTR_CNT 0x326C58 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM1_CH1_CTR_CNT 0x326C5C + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM2_CH0_CTR_CNT 0x326C60 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM2_CH1_CTR_CNT 0x326C64 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM3_CH0_CTR_CNT 0x326C68 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM3_CH1_CTR_CNT 0x326C6C + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM0_CH0_CTR_WRAP 0x326C70 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM0_CH1_CTR_WRAP 0x326C74 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM1_CH0_CTR_WRAP 0x326C78 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM1_CH1_CTR_WRAP 0x326C7C + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM2_CH0_CTR_WRAP 0x326C80 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM2_CH1_CTR_WRAP 0x326C84 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM3_CH0_CTR_WRAP 0x326C88 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM3_CH1_CTR_WRAP 0x326C8C + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM0_CH0_CTR_CNT 0x326C90 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM0_CH1_CTR_CNT 0x326C94 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM1_CH0_CTR_CNT 0x326C98 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM1_CH1_CTR_CNT 0x326C9C + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM2_CH0_CTR_CNT 0x326CA0 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM2_CH1_CTR_CNT 0x326CA4 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM3_CH0_CTR_CNT 0x326CA8 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM3_CH1_CTR_CNT 0x326CAC + +#define mmSIF_RTR_CTRL_2_NL_HBM_PC_SEL_0 0x326CB0 + +#define mmSIF_RTR_CTRL_2_NL_HBM_PC_SEL_1 0x326CB4 + +#define mmSIF_RTR_CTRL_2_NL_HBM_PC_SEL_2 0x326CB8 + +#define mmSIF_RTR_CTRL_2_NL_HBM_PC_SEL_3 0x326CBC + +#endif /* ASIC_REG_SIF_RTR_CTRL_2_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_3_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_3_regs.h new file mode 100644 index 000000000000..d749f1968e5e --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_3_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SIF_RTR_CTRL_3_REGS_H_ +#define ASIC_REG_SIF_RTR_CTRL_3_REGS_H_ + +/* + ***************************************** + * SIF_RTR_CTRL_3 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmSIF_RTR_CTRL_3_PERM_SEL 0x336108 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_0 0x336114 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_1 0x336118 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_2 0x33611C + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_3 0x336120 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_4 0x336124 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_5 0x336128 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_6 0x33612C + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_7 0x336130 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_8 0x336134 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_9 0x336138 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_10 0x33613C + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_11 0x336140 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_12 0x336144 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_13 0x336148 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_14 0x33614C + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_15 0x336150 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_16 0x336154 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_17 0x336158 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_18 0x33615C + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_19 0x336160 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_20 0x336164 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_21 0x336168 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_22 0x33616C + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_23 0x336170 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_24 0x336174 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_25 0x336178 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_26 0x33617C + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_27 0x336180 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_0 0x336184 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_1 0x336188 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_2 0x33618C + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_3 0x336190 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_4 0x336194 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_5 0x336198 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_6 0x33619C + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_7 0x3361A0 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_8 0x3361A4 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_9 0x3361A8 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_10 0x3361AC + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_11 0x3361B0 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_12 0x3361B4 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_13 0x3361B8 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_14 0x3361BC + +#define mmSIF_RTR_CTRL_3_SCRAM_SRAM_EN 0x33626C + +#define mmSIF_RTR_CTRL_3_RL_HBM_EN 0x336274 + +#define mmSIF_RTR_CTRL_3_RL_HBM_SAT 0x336278 + +#define mmSIF_RTR_CTRL_3_RL_HBM_RST 0x33627C + +#define mmSIF_RTR_CTRL_3_RL_HBM_TIMEOUT 0x336280 + +#define mmSIF_RTR_CTRL_3_SCRAM_HBM_EN 0x336284 + +#define mmSIF_RTR_CTRL_3_RL_PCI_EN 0x336288 + +#define mmSIF_RTR_CTRL_3_RL_PCI_SAT 0x33628C + +#define mmSIF_RTR_CTRL_3_RL_PCI_RST 0x336290 + +#define mmSIF_RTR_CTRL_3_RL_PCI_TIMEOUT 0x336294 + +#define mmSIF_RTR_CTRL_3_RL_SRAM_EN 0x33629C + +#define mmSIF_RTR_CTRL_3_RL_SRAM_SAT 0x3362A0 + +#define mmSIF_RTR_CTRL_3_RL_SRAM_RST 0x3362A4 + +#define mmSIF_RTR_CTRL_3_RL_SRAM_TIMEOUT 0x3362AC + +#define mmSIF_RTR_CTRL_3_RL_SRAM_RED 0x3362B4 + +#define mmSIF_RTR_CTRL_3_E2E_HBM_EN 0x3362EC + +#define mmSIF_RTR_CTRL_3_E2E_PCI_EN 0x3362F0 + +#define mmSIF_RTR_CTRL_3_E2E_HBM_WR_SIZE 0x3362F4 + +#define mmSIF_RTR_CTRL_3_E2E_PCI_WR_SIZE 0x3362F8 + +#define mmSIF_RTR_CTRL_3_E2E_AW_PCI_CTR_SET_EN 0x336404 + +#define mmSIF_RTR_CTRL_3_E2E_AW_PCI_CTR_SET 0x336408 + +#define mmSIF_RTR_CTRL_3_E2E_AW_PCI_CTR_WRAP 0x33640C + +#define mmSIF_RTR_CTRL_3_E2E_AW_PCI_CTR_CNT 0x336410 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM_CTR_SET_EN 0x336414 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM_CTR_SET 0x336418 + +#define mmSIF_RTR_CTRL_3_E2E_HBM_RD_SIZE 0x33641C + +#define mmSIF_RTR_CTRL_3_E2E_PCI_RD_SIZE 0x336420 + +#define mmSIF_RTR_CTRL_3_E2E_AR_PCI_CTR_SET_EN 0x336424 + +#define mmSIF_RTR_CTRL_3_E2E_AR_PCI_CTR_SET 0x336428 + +#define mmSIF_RTR_CTRL_3_E2E_AR_PCI_CTR_WRAP 0x33642C + +#define mmSIF_RTR_CTRL_3_E2E_AR_PCI_CTR_CNT 0x336430 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM_CTR_SET_EN 0x336434 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM_CTR_SET 0x336438 + +#define mmSIF_RTR_CTRL_3_NL_HBM_SEL_0 0x336450 + +#define mmSIF_RTR_CTRL_3_NL_HBM_SEL_1 0x336454 + +#define mmSIF_RTR_CTRL_3_NON_LIN_EN 0x336480 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_BANK_0 0x336500 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_BANK_1 0x336504 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_BANK_2 0x336508 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_BANK_3 0x33650C + +#define mmSIF_RTR_CTRL_3_NL_SRAM_BANK_4 0x336510 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_0 0x336514 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_1 0x336520 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_2 0x336524 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_3 0x336528 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_4 0x33652C + +#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_5 0x336530 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_6 0x336534 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_7 0x336538 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_8 0x33653C + +#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_9 0x336540 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_0 0x336550 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_1 0x336554 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_2 0x336558 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_3 0x33655C + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_4 0x336560 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_5 0x336564 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_6 0x336568 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_7 0x33656C + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_8 0x336570 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_9 0x336574 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_10 0x336578 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_11 0x33657C + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_12 0x336580 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_13 0x336584 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_14 0x336588 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_15 0x33658C + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_16 0x336590 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_17 0x336594 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_18 0x336598 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_0 0x3365E4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_1 0x3365E8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_2 0x3365EC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_3 0x3365F0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_4 0x3365F4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_5 0x3365F8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_6 0x3365FC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_7 0x336600 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_8 0x336604 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_9 0x336608 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_10 0x33660C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_11 0x336610 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_12 0x336614 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_13 0x336618 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_14 0x33661C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_15 0x336620 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_0 0x336624 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_1 0x336628 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_2 0x33662C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_3 0x336630 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_4 0x336634 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_5 0x336638 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_6 0x33663C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_7 0x336640 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_8 0x336644 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_9 0x336648 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_10 0x33664C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_11 0x336650 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_12 0x336654 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_13 0x336658 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_14 0x33665C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_15 0x336660 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_0 0x336664 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_1 0x336668 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_2 0x33666C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_3 0x336670 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_4 0x336674 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_5 0x336678 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_6 0x33667C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_7 0x336680 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_8 0x336684 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_9 0x336688 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_10 0x33668C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_11 0x336690 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_12 0x336694 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_13 0x336698 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_14 0x33669C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_15 0x3366A0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_0 0x3366A4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_1 0x3366A8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_2 0x3366AC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_3 0x3366B0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_4 0x3366B4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_5 0x3366B8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_6 0x3366BC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_7 0x3366C0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_8 0x3366C4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_9 0x3366C8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_10 0x3366CC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_11 0x3366D0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_12 0x3366D4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_13 0x3366D8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_14 0x3366DC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_15 0x3366E0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_0 0x3366E4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_1 0x3366E8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_2 0x3366EC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_3 0x3366F0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_4 0x3366F4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_5 0x3366F8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_6 0x3366FC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_7 0x336700 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_8 0x336704 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_9 0x336708 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_10 0x33670C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_11 0x336710 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_12 0x336714 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_13 0x336718 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_14 0x33671C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_15 0x336720 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_0 0x336724 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_1 0x336728 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_2 0x33672C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_3 0x336730 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_4 0x336734 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_5 0x336738 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_6 0x33673C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_7 0x336740 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_8 0x336744 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_9 0x336748 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_10 0x33674C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_11 0x336750 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_12 0x336754 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_13 0x336758 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_14 0x33675C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_15 0x336760 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_0 0x336764 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_1 0x336768 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_2 0x33676C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_3 0x336770 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_4 0x336774 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_5 0x336778 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_6 0x33677C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_7 0x336780 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_8 0x336784 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_9 0x336788 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_10 0x33678C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_11 0x336790 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_12 0x336794 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_13 0x336798 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_14 0x33679C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_15 0x3367A0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_0 0x3367A4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_1 0x3367A8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_2 0x3367AC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_3 0x3367B0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_4 0x3367B4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_5 0x3367B8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_6 0x3367BC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_7 0x3367C0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_8 0x3367C4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_9 0x3367C8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_10 0x3367CC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_11 0x3367D0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_12 0x3367D4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_13 0x3367D8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_14 0x3367DC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_15 0x3367E0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_0 0x336824 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_1 0x336828 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_2 0x33682C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_3 0x336830 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_4 0x336834 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_5 0x336838 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_6 0x33683C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_7 0x336840 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_8 0x336844 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_9 0x336848 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_10 0x33684C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_11 0x336850 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_12 0x336854 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_13 0x336858 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_14 0x33685C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_15 0x336860 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_0 0x336864 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_1 0x336868 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_2 0x33686C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_3 0x336870 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_4 0x336874 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_5 0x336878 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_6 0x33687C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_7 0x336880 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_8 0x336884 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_9 0x336888 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_10 0x33688C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_11 0x336890 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_12 0x336894 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_13 0x336898 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_14 0x33689C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_15 0x3368A0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_0 0x3368A4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_1 0x3368A8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_2 0x3368AC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_3 0x3368B0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_4 0x3368B4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_5 0x3368B8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_6 0x3368BC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_7 0x3368C0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_8 0x3368C4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_9 0x3368C8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_10 0x3368CC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_11 0x3368D0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_12 0x3368D4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_13 0x3368D8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_14 0x3368DC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_15 0x3368E0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_0 0x3368E4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_1 0x3368E8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_2 0x3368EC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_3 0x3368F0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_4 0x3368F4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_5 0x3368F8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_6 0x3368FC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_7 0x336900 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_8 0x336904 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_9 0x336908 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_10 0x33690C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_11 0x336910 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_12 0x336914 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_13 0x336918 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_14 0x33691C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_15 0x336920 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_0 0x336924 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_1 0x336928 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_2 0x33692C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_3 0x336930 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_4 0x336934 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_5 0x336938 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_6 0x33693C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_7 0x336940 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_8 0x336944 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_9 0x336948 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_10 0x33694C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_11 0x336950 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_12 0x336954 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_13 0x336958 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_14 0x33695C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_15 0x336960 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_0 0x336964 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_1 0x336968 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_2 0x33696C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_3 0x336970 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_4 0x336974 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_5 0x336978 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_6 0x33697C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_7 0x336980 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_8 0x336984 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_9 0x336988 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_10 0x33698C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_11 0x336990 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_12 0x336994 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_13 0x336998 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_14 0x33699C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_15 0x3369A0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_0 0x3369A4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_1 0x3369A8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_2 0x3369AC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_3 0x3369B0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_4 0x3369B4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_5 0x3369B8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_6 0x3369BC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_7 0x3369C0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_8 0x3369C4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_9 0x3369C8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_10 0x3369CC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_11 0x3369D0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_12 0x3369D4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_13 0x3369D8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_14 0x3369DC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_15 0x3369E0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_0 0x3369E4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_1 0x3369E8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_2 0x3369EC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_3 0x3369F0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_4 0x3369F4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_5 0x3369F8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_6 0x3369FC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_7 0x336A00 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_8 0x336A04 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_9 0x336A08 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_10 0x336A0C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_11 0x336A10 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_12 0x336A14 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_13 0x336A18 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_14 0x336A1C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_15 0x336A20 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_HIT_AW 0x336A64 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_HIT_AR 0x336A68 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_HIT_AW 0x336A6C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_HIT_AR 0x336A70 + +#define mmSIF_RTR_CTRL_3_RGL_CFG 0x336B64 + +#define mmSIF_RTR_CTRL_3_RGL_SHIFT 0x336B68 + +#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_0 0x336B6C + +#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_1 0x336B70 + +#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_2 0x336B74 + +#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_3 0x336B78 + +#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_4 0x336B7C + +#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_5 0x336B80 + +#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_6 0x336B84 + +#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_7 0x336B88 + +#define mmSIF_RTR_CTRL_3_RGL_TOKEN_0 0x336BAC + +#define mmSIF_RTR_CTRL_3_RGL_TOKEN_1 0x336BB0 + +#define mmSIF_RTR_CTRL_3_RGL_TOKEN_2 0x336BB4 + +#define mmSIF_RTR_CTRL_3_RGL_TOKEN_3 0x336BB8 + +#define mmSIF_RTR_CTRL_3_RGL_TOKEN_4 0x336BBC + +#define mmSIF_RTR_CTRL_3_RGL_TOKEN_5 0x336BC0 + +#define mmSIF_RTR_CTRL_3_RGL_TOKEN_6 0x336BC4 + +#define mmSIF_RTR_CTRL_3_RGL_TOKEN_7 0x336BC8 + +#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_0 0x336BEC + +#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_1 0x336BF0 + +#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_2 0x336BF4 + +#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_3 0x336BF8 + +#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_4 0x336BFC + +#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_5 0x336C00 + +#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_6 0x336C04 + +#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_7 0x336C08 + +#define mmSIF_RTR_CTRL_3_RGL_WDT 0x336C2C + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM0_CH0_CTR_WRAP 0x336C30 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM0_CH1_CTR_WRAP 0x336C34 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM1_CH0_CTR_WRAP 0x336C38 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM1_CH1_CTR_WRAP 0x336C3C + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM2_CH0_CTR_WRAP 0x336C40 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM2_CH1_CTR_WRAP 0x336C44 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM3_CH0_CTR_WRAP 0x336C48 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM3_CH1_CTR_WRAP 0x336C4C + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM0_CH0_CTR_CNT 0x336C50 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM0_CH1_CTR_CNT 0x336C54 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM1_CH0_CTR_CNT 0x336C58 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM1_CH1_CTR_CNT 0x336C5C + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM2_CH0_CTR_CNT 0x336C60 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM2_CH1_CTR_CNT 0x336C64 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM3_CH0_CTR_CNT 0x336C68 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM3_CH1_CTR_CNT 0x336C6C + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM0_CH0_CTR_WRAP 0x336C70 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM0_CH1_CTR_WRAP 0x336C74 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM1_CH0_CTR_WRAP 0x336C78 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM1_CH1_CTR_WRAP 0x336C7C + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM2_CH0_CTR_WRAP 0x336C80 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM2_CH1_CTR_WRAP 0x336C84 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM3_CH0_CTR_WRAP 0x336C88 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM3_CH1_CTR_WRAP 0x336C8C + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM0_CH0_CTR_CNT 0x336C90 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM0_CH1_CTR_CNT 0x336C94 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM1_CH0_CTR_CNT 0x336C98 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM1_CH1_CTR_CNT 0x336C9C + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM2_CH0_CTR_CNT 0x336CA0 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM2_CH1_CTR_CNT 0x336CA4 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM3_CH0_CTR_CNT 0x336CA8 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM3_CH1_CTR_CNT 0x336CAC + +#define mmSIF_RTR_CTRL_3_NL_HBM_PC_SEL_0 0x336CB0 + +#define mmSIF_RTR_CTRL_3_NL_HBM_PC_SEL_1 0x336CB4 + +#define mmSIF_RTR_CTRL_3_NL_HBM_PC_SEL_2 0x336CB8 + +#define mmSIF_RTR_CTRL_3_NL_HBM_PC_SEL_3 0x336CBC + +#endif /* ASIC_REG_SIF_RTR_CTRL_3_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_4_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_4_regs.h new file mode 100644 index 000000000000..ad48773c4bbd --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_4_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SIF_RTR_CTRL_4_REGS_H_ +#define ASIC_REG_SIF_RTR_CTRL_4_REGS_H_ + +/* + ***************************************** + * SIF_RTR_CTRL_4 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmSIF_RTR_CTRL_4_PERM_SEL 0x346108 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_0 0x346114 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_1 0x346118 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_2 0x34611C + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_3 0x346120 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_4 0x346124 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_5 0x346128 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_6 0x34612C + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_7 0x346130 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_8 0x346134 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_9 0x346138 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_10 0x34613C + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_11 0x346140 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_12 0x346144 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_13 0x346148 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_14 0x34614C + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_15 0x346150 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_16 0x346154 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_17 0x346158 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_18 0x34615C + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_19 0x346160 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_20 0x346164 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_21 0x346168 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_22 0x34616C + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_23 0x346170 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_24 0x346174 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_25 0x346178 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_26 0x34617C + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_27 0x346180 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_0 0x346184 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_1 0x346188 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_2 0x34618C + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_3 0x346190 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_4 0x346194 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_5 0x346198 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_6 0x34619C + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_7 0x3461A0 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_8 0x3461A4 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_9 0x3461A8 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_10 0x3461AC + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_11 0x3461B0 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_12 0x3461B4 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_13 0x3461B8 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_14 0x3461BC + +#define mmSIF_RTR_CTRL_4_SCRAM_SRAM_EN 0x34626C + +#define mmSIF_RTR_CTRL_4_RL_HBM_EN 0x346274 + +#define mmSIF_RTR_CTRL_4_RL_HBM_SAT 0x346278 + +#define mmSIF_RTR_CTRL_4_RL_HBM_RST 0x34627C + +#define mmSIF_RTR_CTRL_4_RL_HBM_TIMEOUT 0x346280 + +#define mmSIF_RTR_CTRL_4_SCRAM_HBM_EN 0x346284 + +#define mmSIF_RTR_CTRL_4_RL_PCI_EN 0x346288 + +#define mmSIF_RTR_CTRL_4_RL_PCI_SAT 0x34628C + +#define mmSIF_RTR_CTRL_4_RL_PCI_RST 0x346290 + +#define mmSIF_RTR_CTRL_4_RL_PCI_TIMEOUT 0x346294 + +#define mmSIF_RTR_CTRL_4_RL_SRAM_EN 0x34629C + +#define mmSIF_RTR_CTRL_4_RL_SRAM_SAT 0x3462A0 + +#define mmSIF_RTR_CTRL_4_RL_SRAM_RST 0x3462A4 + +#define mmSIF_RTR_CTRL_4_RL_SRAM_TIMEOUT 0x3462AC + +#define mmSIF_RTR_CTRL_4_RL_SRAM_RED 0x3462B4 + +#define mmSIF_RTR_CTRL_4_E2E_HBM_EN 0x3462EC + +#define mmSIF_RTR_CTRL_4_E2E_PCI_EN 0x3462F0 + +#define mmSIF_RTR_CTRL_4_E2E_HBM_WR_SIZE 0x3462F4 + +#define mmSIF_RTR_CTRL_4_E2E_PCI_WR_SIZE 0x3462F8 + +#define mmSIF_RTR_CTRL_4_E2E_AW_PCI_CTR_SET_EN 0x346404 + +#define mmSIF_RTR_CTRL_4_E2E_AW_PCI_CTR_SET 0x346408 + +#define mmSIF_RTR_CTRL_4_E2E_AW_PCI_CTR_WRAP 0x34640C + +#define mmSIF_RTR_CTRL_4_E2E_AW_PCI_CTR_CNT 0x346410 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM_CTR_SET_EN 0x346414 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM_CTR_SET 0x346418 + +#define mmSIF_RTR_CTRL_4_E2E_HBM_RD_SIZE 0x34641C + +#define mmSIF_RTR_CTRL_4_E2E_PCI_RD_SIZE 0x346420 + +#define mmSIF_RTR_CTRL_4_E2E_AR_PCI_CTR_SET_EN 0x346424 + +#define mmSIF_RTR_CTRL_4_E2E_AR_PCI_CTR_SET 0x346428 + +#define mmSIF_RTR_CTRL_4_E2E_AR_PCI_CTR_WRAP 0x34642C + +#define mmSIF_RTR_CTRL_4_E2E_AR_PCI_CTR_CNT 0x346430 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM_CTR_SET_EN 0x346434 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM_CTR_SET 0x346438 + +#define mmSIF_RTR_CTRL_4_NL_HBM_SEL_0 0x346450 + +#define mmSIF_RTR_CTRL_4_NL_HBM_SEL_1 0x346454 + +#define mmSIF_RTR_CTRL_4_NON_LIN_EN 0x346480 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_BANK_0 0x346500 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_BANK_1 0x346504 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_BANK_2 0x346508 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_BANK_3 0x34650C + +#define mmSIF_RTR_CTRL_4_NL_SRAM_BANK_4 0x346510 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_0 0x346514 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_1 0x346520 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_2 0x346524 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_3 0x346528 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_4 0x34652C + +#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_5 0x346530 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_6 0x346534 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_7 0x346538 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_8 0x34653C + +#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_9 0x346540 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_0 0x346550 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_1 0x346554 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_2 0x346558 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_3 0x34655C + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_4 0x346560 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_5 0x346564 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_6 0x346568 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_7 0x34656C + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_8 0x346570 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_9 0x346574 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_10 0x346578 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_11 0x34657C + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_12 0x346580 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_13 0x346584 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_14 0x346588 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_15 0x34658C + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_16 0x346590 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_17 0x346594 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_18 0x346598 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_0 0x3465E4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_1 0x3465E8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_2 0x3465EC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_3 0x3465F0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_4 0x3465F4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_5 0x3465F8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_6 0x3465FC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_7 0x346600 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_8 0x346604 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_9 0x346608 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_10 0x34660C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_11 0x346610 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_12 0x346614 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_13 0x346618 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_14 0x34661C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_15 0x346620 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_0 0x346624 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_1 0x346628 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_2 0x34662C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_3 0x346630 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_4 0x346634 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_5 0x346638 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_6 0x34663C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_7 0x346640 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_8 0x346644 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_9 0x346648 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_10 0x34664C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_11 0x346650 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_12 0x346654 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_13 0x346658 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_14 0x34665C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_15 0x346660 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_0 0x346664 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_1 0x346668 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_2 0x34666C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_3 0x346670 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_4 0x346674 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_5 0x346678 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_6 0x34667C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_7 0x346680 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_8 0x346684 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_9 0x346688 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_10 0x34668C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_11 0x346690 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_12 0x346694 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_13 0x346698 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_14 0x34669C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_15 0x3466A0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_0 0x3466A4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_1 0x3466A8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_2 0x3466AC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_3 0x3466B0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_4 0x3466B4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_5 0x3466B8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_6 0x3466BC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_7 0x3466C0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_8 0x3466C4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_9 0x3466C8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_10 0x3466CC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_11 0x3466D0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_12 0x3466D4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_13 0x3466D8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_14 0x3466DC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_15 0x3466E0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_0 0x3466E4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_1 0x3466E8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_2 0x3466EC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_3 0x3466F0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_4 0x3466F4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_5 0x3466F8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_6 0x3466FC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_7 0x346700 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_8 0x346704 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_9 0x346708 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_10 0x34670C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_11 0x346710 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_12 0x346714 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_13 0x346718 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_14 0x34671C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_15 0x346720 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_0 0x346724 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_1 0x346728 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_2 0x34672C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_3 0x346730 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_4 0x346734 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_5 0x346738 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_6 0x34673C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_7 0x346740 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_8 0x346744 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_9 0x346748 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_10 0x34674C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_11 0x346750 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_12 0x346754 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_13 0x346758 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_14 0x34675C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_15 0x346760 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_0 0x346764 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_1 0x346768 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_2 0x34676C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_3 0x346770 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_4 0x346774 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_5 0x346778 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_6 0x34677C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_7 0x346780 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_8 0x346784 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_9 0x346788 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_10 0x34678C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_11 0x346790 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_12 0x346794 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_13 0x346798 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_14 0x34679C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_15 0x3467A0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_0 0x3467A4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_1 0x3467A8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_2 0x3467AC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_3 0x3467B0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_4 0x3467B4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_5 0x3467B8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_6 0x3467BC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_7 0x3467C0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_8 0x3467C4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_9 0x3467C8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_10 0x3467CC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_11 0x3467D0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_12 0x3467D4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_13 0x3467D8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_14 0x3467DC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_15 0x3467E0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_0 0x346824 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_1 0x346828 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_2 0x34682C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_3 0x346830 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_4 0x346834 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_5 0x346838 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_6 0x34683C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_7 0x346840 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_8 0x346844 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_9 0x346848 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_10 0x34684C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_11 0x346850 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_12 0x346854 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_13 0x346858 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_14 0x34685C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_15 0x346860 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_0 0x346864 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_1 0x346868 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_2 0x34686C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_3 0x346870 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_4 0x346874 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_5 0x346878 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_6 0x34687C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_7 0x346880 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_8 0x346884 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_9 0x346888 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_10 0x34688C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_11 0x346890 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_12 0x346894 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_13 0x346898 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_14 0x34689C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_15 0x3468A0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_0 0x3468A4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_1 0x3468A8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_2 0x3468AC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_3 0x3468B0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_4 0x3468B4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_5 0x3468B8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_6 0x3468BC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_7 0x3468C0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_8 0x3468C4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_9 0x3468C8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_10 0x3468CC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_11 0x3468D0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_12 0x3468D4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_13 0x3468D8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_14 0x3468DC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_15 0x3468E0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_0 0x3468E4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_1 0x3468E8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_2 0x3468EC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_3 0x3468F0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_4 0x3468F4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_5 0x3468F8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_6 0x3468FC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_7 0x346900 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_8 0x346904 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_9 0x346908 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_10 0x34690C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_11 0x346910 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_12 0x346914 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_13 0x346918 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_14 0x34691C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_15 0x346920 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_0 0x346924 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_1 0x346928 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_2 0x34692C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_3 0x346930 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_4 0x346934 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_5 0x346938 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_6 0x34693C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_7 0x346940 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_8 0x346944 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_9 0x346948 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_10 0x34694C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_11 0x346950 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_12 0x346954 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_13 0x346958 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_14 0x34695C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_15 0x346960 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_0 0x346964 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_1 0x346968 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_2 0x34696C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_3 0x346970 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_4 0x346974 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_5 0x346978 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_6 0x34697C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_7 0x346980 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_8 0x346984 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_9 0x346988 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_10 0x34698C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_11 0x346990 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_12 0x346994 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_13 0x346998 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_14 0x34699C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_15 0x3469A0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_0 0x3469A4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_1 0x3469A8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_2 0x3469AC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_3 0x3469B0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_4 0x3469B4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_5 0x3469B8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_6 0x3469BC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_7 0x3469C0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_8 0x3469C4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_9 0x3469C8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_10 0x3469CC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_11 0x3469D0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_12 0x3469D4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_13 0x3469D8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_14 0x3469DC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_15 0x3469E0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_0 0x3469E4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_1 0x3469E8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_2 0x3469EC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_3 0x3469F0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_4 0x3469F4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_5 0x3469F8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_6 0x3469FC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_7 0x346A00 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_8 0x346A04 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_9 0x346A08 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_10 0x346A0C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_11 0x346A10 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_12 0x346A14 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_13 0x346A18 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_14 0x346A1C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_15 0x346A20 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_HIT_AW 0x346A64 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_HIT_AR 0x346A68 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_HIT_AW 0x346A6C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_HIT_AR 0x346A70 + +#define mmSIF_RTR_CTRL_4_RGL_CFG 0x346B64 + +#define mmSIF_RTR_CTRL_4_RGL_SHIFT 0x346B68 + +#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_0 0x346B6C + +#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_1 0x346B70 + +#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_2 0x346B74 + +#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_3 0x346B78 + +#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_4 0x346B7C + +#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_5 0x346B80 + +#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_6 0x346B84 + +#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_7 0x346B88 + +#define mmSIF_RTR_CTRL_4_RGL_TOKEN_0 0x346BAC + +#define mmSIF_RTR_CTRL_4_RGL_TOKEN_1 0x346BB0 + +#define mmSIF_RTR_CTRL_4_RGL_TOKEN_2 0x346BB4 + +#define mmSIF_RTR_CTRL_4_RGL_TOKEN_3 0x346BB8 + +#define mmSIF_RTR_CTRL_4_RGL_TOKEN_4 0x346BBC + +#define mmSIF_RTR_CTRL_4_RGL_TOKEN_5 0x346BC0 + +#define mmSIF_RTR_CTRL_4_RGL_TOKEN_6 0x346BC4 + +#define mmSIF_RTR_CTRL_4_RGL_TOKEN_7 0x346BC8 + +#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_0 0x346BEC + +#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_1 0x346BF0 + +#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_2 0x346BF4 + +#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_3 0x346BF8 + +#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_4 0x346BFC + +#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_5 0x346C00 + +#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_6 0x346C04 + +#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_7 0x346C08 + +#define mmSIF_RTR_CTRL_4_RGL_WDT 0x346C2C + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM0_CH0_CTR_WRAP 0x346C30 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM0_CH1_CTR_WRAP 0x346C34 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM1_CH0_CTR_WRAP 0x346C38 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM1_CH1_CTR_WRAP 0x346C3C + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM2_CH0_CTR_WRAP 0x346C40 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM2_CH1_CTR_WRAP 0x346C44 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM3_CH0_CTR_WRAP 0x346C48 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM3_CH1_CTR_WRAP 0x346C4C + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM0_CH0_CTR_CNT 0x346C50 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM0_CH1_CTR_CNT 0x346C54 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM1_CH0_CTR_CNT 0x346C58 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM1_CH1_CTR_CNT 0x346C5C + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM2_CH0_CTR_CNT 0x346C60 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM2_CH1_CTR_CNT 0x346C64 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM3_CH0_CTR_CNT 0x346C68 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM3_CH1_CTR_CNT 0x346C6C + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM0_CH0_CTR_WRAP 0x346C70 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM0_CH1_CTR_WRAP 0x346C74 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM1_CH0_CTR_WRAP 0x346C78 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM1_CH1_CTR_WRAP 0x346C7C + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM2_CH0_CTR_WRAP 0x346C80 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM2_CH1_CTR_WRAP 0x346C84 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM3_CH0_CTR_WRAP 0x346C88 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM3_CH1_CTR_WRAP 0x346C8C + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM0_CH0_CTR_CNT 0x346C90 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM0_CH1_CTR_CNT 0x346C94 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM1_CH0_CTR_CNT 0x346C98 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM1_CH1_CTR_CNT 0x346C9C + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM2_CH0_CTR_CNT 0x346CA0 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM2_CH1_CTR_CNT 0x346CA4 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM3_CH0_CTR_CNT 0x346CA8 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM3_CH1_CTR_CNT 0x346CAC + +#define mmSIF_RTR_CTRL_4_NL_HBM_PC_SEL_0 0x346CB0 + +#define mmSIF_RTR_CTRL_4_NL_HBM_PC_SEL_1 0x346CB4 + +#define mmSIF_RTR_CTRL_4_NL_HBM_PC_SEL_2 0x346CB8 + +#define mmSIF_RTR_CTRL_4_NL_HBM_PC_SEL_3 0x346CBC + +#endif /* ASIC_REG_SIF_RTR_CTRL_4_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_5_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_5_regs.h new file mode 100644 index 000000000000..6c27850ca3f5 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_5_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SIF_RTR_CTRL_5_REGS_H_ +#define ASIC_REG_SIF_RTR_CTRL_5_REGS_H_ + +/* + ***************************************** + * SIF_RTR_CTRL_5 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmSIF_RTR_CTRL_5_PERM_SEL 0x356108 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_0 0x356114 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_1 0x356118 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_2 0x35611C + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_3 0x356120 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_4 0x356124 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_5 0x356128 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_6 0x35612C + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_7 0x356130 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_8 0x356134 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_9 0x356138 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_10 0x35613C + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_11 0x356140 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_12 0x356144 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_13 0x356148 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_14 0x35614C + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_15 0x356150 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_16 0x356154 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_17 0x356158 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_18 0x35615C + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_19 0x356160 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_20 0x356164 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_21 0x356168 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_22 0x35616C + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_23 0x356170 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_24 0x356174 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_25 0x356178 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_26 0x35617C + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_27 0x356180 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_0 0x356184 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_1 0x356188 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_2 0x35618C + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_3 0x356190 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_4 0x356194 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_5 0x356198 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_6 0x35619C + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_7 0x3561A0 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_8 0x3561A4 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_9 0x3561A8 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_10 0x3561AC + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_11 0x3561B0 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_12 0x3561B4 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_13 0x3561B8 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_14 0x3561BC + +#define mmSIF_RTR_CTRL_5_SCRAM_SRAM_EN 0x35626C + +#define mmSIF_RTR_CTRL_5_RL_HBM_EN 0x356274 + +#define mmSIF_RTR_CTRL_5_RL_HBM_SAT 0x356278 + +#define mmSIF_RTR_CTRL_5_RL_HBM_RST 0x35627C + +#define mmSIF_RTR_CTRL_5_RL_HBM_TIMEOUT 0x356280 + +#define mmSIF_RTR_CTRL_5_SCRAM_HBM_EN 0x356284 + +#define mmSIF_RTR_CTRL_5_RL_PCI_EN 0x356288 + +#define mmSIF_RTR_CTRL_5_RL_PCI_SAT 0x35628C + +#define mmSIF_RTR_CTRL_5_RL_PCI_RST 0x356290 + +#define mmSIF_RTR_CTRL_5_RL_PCI_TIMEOUT 0x356294 + +#define mmSIF_RTR_CTRL_5_RL_SRAM_EN 0x35629C + +#define mmSIF_RTR_CTRL_5_RL_SRAM_SAT 0x3562A0 + +#define mmSIF_RTR_CTRL_5_RL_SRAM_RST 0x3562A4 + +#define mmSIF_RTR_CTRL_5_RL_SRAM_TIMEOUT 0x3562AC + +#define mmSIF_RTR_CTRL_5_RL_SRAM_RED 0x3562B4 + +#define mmSIF_RTR_CTRL_5_E2E_HBM_EN 0x3562EC + +#define mmSIF_RTR_CTRL_5_E2E_PCI_EN 0x3562F0 + +#define mmSIF_RTR_CTRL_5_E2E_HBM_WR_SIZE 0x3562F4 + +#define mmSIF_RTR_CTRL_5_E2E_PCI_WR_SIZE 0x3562F8 + +#define mmSIF_RTR_CTRL_5_E2E_AW_PCI_CTR_SET_EN 0x356404 + +#define mmSIF_RTR_CTRL_5_E2E_AW_PCI_CTR_SET 0x356408 + +#define mmSIF_RTR_CTRL_5_E2E_AW_PCI_CTR_WRAP 0x35640C + +#define mmSIF_RTR_CTRL_5_E2E_AW_PCI_CTR_CNT 0x356410 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM_CTR_SET_EN 0x356414 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM_CTR_SET 0x356418 + +#define mmSIF_RTR_CTRL_5_E2E_HBM_RD_SIZE 0x35641C + +#define mmSIF_RTR_CTRL_5_E2E_PCI_RD_SIZE 0x356420 + +#define mmSIF_RTR_CTRL_5_E2E_AR_PCI_CTR_SET_EN 0x356424 + +#define mmSIF_RTR_CTRL_5_E2E_AR_PCI_CTR_SET 0x356428 + +#define mmSIF_RTR_CTRL_5_E2E_AR_PCI_CTR_WRAP 0x35642C + +#define mmSIF_RTR_CTRL_5_E2E_AR_PCI_CTR_CNT 0x356430 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM_CTR_SET_EN 0x356434 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM_CTR_SET 0x356438 + +#define mmSIF_RTR_CTRL_5_NL_HBM_SEL_0 0x356450 + +#define mmSIF_RTR_CTRL_5_NL_HBM_SEL_1 0x356454 + +#define mmSIF_RTR_CTRL_5_NON_LIN_EN 0x356480 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_BANK_0 0x356500 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_BANK_1 0x356504 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_BANK_2 0x356508 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_BANK_3 0x35650C + +#define mmSIF_RTR_CTRL_5_NL_SRAM_BANK_4 0x356510 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_0 0x356514 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_1 0x356520 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_2 0x356524 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_3 0x356528 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_4 0x35652C + +#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_5 0x356530 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_6 0x356534 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_7 0x356538 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_8 0x35653C + +#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_9 0x356540 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_0 0x356550 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_1 0x356554 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_2 0x356558 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_3 0x35655C + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_4 0x356560 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_5 0x356564 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_6 0x356568 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_7 0x35656C + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_8 0x356570 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_9 0x356574 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_10 0x356578 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_11 0x35657C + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_12 0x356580 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_13 0x356584 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_14 0x356588 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_15 0x35658C + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_16 0x356590 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_17 0x356594 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_18 0x356598 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_0 0x3565E4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_1 0x3565E8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_2 0x3565EC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_3 0x3565F0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_4 0x3565F4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_5 0x3565F8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_6 0x3565FC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_7 0x356600 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_8 0x356604 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_9 0x356608 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_10 0x35660C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_11 0x356610 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_12 0x356614 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_13 0x356618 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_14 0x35661C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_15 0x356620 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_0 0x356624 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_1 0x356628 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_2 0x35662C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_3 0x356630 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_4 0x356634 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_5 0x356638 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_6 0x35663C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_7 0x356640 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_8 0x356644 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_9 0x356648 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_10 0x35664C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_11 0x356650 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_12 0x356654 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_13 0x356658 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_14 0x35665C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_15 0x356660 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_0 0x356664 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_1 0x356668 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_2 0x35666C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_3 0x356670 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_4 0x356674 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_5 0x356678 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_6 0x35667C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_7 0x356680 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_8 0x356684 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_9 0x356688 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_10 0x35668C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_11 0x356690 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_12 0x356694 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_13 0x356698 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_14 0x35669C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_15 0x3566A0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_0 0x3566A4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_1 0x3566A8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_2 0x3566AC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_3 0x3566B0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_4 0x3566B4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_5 0x3566B8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_6 0x3566BC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_7 0x3566C0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_8 0x3566C4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_9 0x3566C8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_10 0x3566CC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_11 0x3566D0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_12 0x3566D4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_13 0x3566D8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_14 0x3566DC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_15 0x3566E0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_0 0x3566E4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_1 0x3566E8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_2 0x3566EC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_3 0x3566F0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_4 0x3566F4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_5 0x3566F8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_6 0x3566FC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_7 0x356700 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_8 0x356704 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_9 0x356708 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_10 0x35670C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_11 0x356710 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_12 0x356714 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_13 0x356718 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_14 0x35671C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_15 0x356720 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_0 0x356724 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_1 0x356728 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_2 0x35672C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_3 0x356730 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_4 0x356734 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_5 0x356738 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_6 0x35673C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_7 0x356740 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_8 0x356744 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_9 0x356748 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_10 0x35674C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_11 0x356750 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_12 0x356754 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_13 0x356758 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_14 0x35675C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_15 0x356760 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_0 0x356764 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_1 0x356768 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_2 0x35676C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_3 0x356770 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_4 0x356774 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_5 0x356778 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_6 0x35677C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_7 0x356780 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_8 0x356784 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_9 0x356788 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_10 0x35678C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_11 0x356790 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_12 0x356794 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_13 0x356798 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_14 0x35679C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_15 0x3567A0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_0 0x3567A4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_1 0x3567A8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_2 0x3567AC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_3 0x3567B0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_4 0x3567B4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_5 0x3567B8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_6 0x3567BC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_7 0x3567C0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_8 0x3567C4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_9 0x3567C8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_10 0x3567CC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_11 0x3567D0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_12 0x3567D4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_13 0x3567D8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_14 0x3567DC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_15 0x3567E0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_0 0x356824 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_1 0x356828 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_2 0x35682C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_3 0x356830 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_4 0x356834 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_5 0x356838 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_6 0x35683C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_7 0x356840 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_8 0x356844 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_9 0x356848 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_10 0x35684C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_11 0x356850 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_12 0x356854 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_13 0x356858 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_14 0x35685C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_15 0x356860 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_0 0x356864 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_1 0x356868 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_2 0x35686C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_3 0x356870 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_4 0x356874 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_5 0x356878 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_6 0x35687C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_7 0x356880 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_8 0x356884 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_9 0x356888 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_10 0x35688C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_11 0x356890 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_12 0x356894 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_13 0x356898 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_14 0x35689C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_15 0x3568A0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_0 0x3568A4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_1 0x3568A8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_2 0x3568AC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_3 0x3568B0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_4 0x3568B4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_5 0x3568B8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_6 0x3568BC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_7 0x3568C0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_8 0x3568C4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_9 0x3568C8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_10 0x3568CC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_11 0x3568D0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_12 0x3568D4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_13 0x3568D8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_14 0x3568DC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_15 0x3568E0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_0 0x3568E4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_1 0x3568E8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_2 0x3568EC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_3 0x3568F0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_4 0x3568F4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_5 0x3568F8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_6 0x3568FC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_7 0x356900 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_8 0x356904 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_9 0x356908 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_10 0x35690C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_11 0x356910 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_12 0x356914 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_13 0x356918 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_14 0x35691C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_15 0x356920 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_0 0x356924 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_1 0x356928 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_2 0x35692C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_3 0x356930 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_4 0x356934 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_5 0x356938 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_6 0x35693C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_7 0x356940 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_8 0x356944 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_9 0x356948 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_10 0x35694C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_11 0x356950 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_12 0x356954 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_13 0x356958 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_14 0x35695C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_15 0x356960 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_0 0x356964 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_1 0x356968 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_2 0x35696C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_3 0x356970 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_4 0x356974 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_5 0x356978 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_6 0x35697C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_7 0x356980 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_8 0x356984 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_9 0x356988 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_10 0x35698C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_11 0x356990 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_12 0x356994 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_13 0x356998 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_14 0x35699C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_15 0x3569A0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_0 0x3569A4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_1 0x3569A8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_2 0x3569AC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_3 0x3569B0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_4 0x3569B4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_5 0x3569B8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_6 0x3569BC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_7 0x3569C0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_8 0x3569C4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_9 0x3569C8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_10 0x3569CC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_11 0x3569D0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_12 0x3569D4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_13 0x3569D8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_14 0x3569DC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_15 0x3569E0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_0 0x3569E4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_1 0x3569E8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_2 0x3569EC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_3 0x3569F0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_4 0x3569F4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_5 0x3569F8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_6 0x3569FC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_7 0x356A00 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_8 0x356A04 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_9 0x356A08 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_10 0x356A0C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_11 0x356A10 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_12 0x356A14 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_13 0x356A18 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_14 0x356A1C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_15 0x356A20 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_HIT_AW 0x356A64 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_HIT_AR 0x356A68 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_HIT_AW 0x356A6C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_HIT_AR 0x356A70 + +#define mmSIF_RTR_CTRL_5_RGL_CFG 0x356B64 + +#define mmSIF_RTR_CTRL_5_RGL_SHIFT 0x356B68 + +#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_0 0x356B6C + +#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_1 0x356B70 + +#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_2 0x356B74 + +#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_3 0x356B78 + +#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_4 0x356B7C + +#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_5 0x356B80 + +#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_6 0x356B84 + +#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_7 0x356B88 + +#define mmSIF_RTR_CTRL_5_RGL_TOKEN_0 0x356BAC + +#define mmSIF_RTR_CTRL_5_RGL_TOKEN_1 0x356BB0 + +#define mmSIF_RTR_CTRL_5_RGL_TOKEN_2 0x356BB4 + +#define mmSIF_RTR_CTRL_5_RGL_TOKEN_3 0x356BB8 + +#define mmSIF_RTR_CTRL_5_RGL_TOKEN_4 0x356BBC + +#define mmSIF_RTR_CTRL_5_RGL_TOKEN_5 0x356BC0 + +#define mmSIF_RTR_CTRL_5_RGL_TOKEN_6 0x356BC4 + +#define mmSIF_RTR_CTRL_5_RGL_TOKEN_7 0x356BC8 + +#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_0 0x356BEC + +#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_1 0x356BF0 + +#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_2 0x356BF4 + +#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_3 0x356BF8 + +#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_4 0x356BFC + +#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_5 0x356C00 + +#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_6 0x356C04 + +#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_7 0x356C08 + +#define mmSIF_RTR_CTRL_5_RGL_WDT 0x356C2C + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM0_CH0_CTR_WRAP 0x356C30 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM0_CH1_CTR_WRAP 0x356C34 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM1_CH0_CTR_WRAP 0x356C38 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM1_CH1_CTR_WRAP 0x356C3C + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM2_CH0_CTR_WRAP 0x356C40 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM2_CH1_CTR_WRAP 0x356C44 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM3_CH0_CTR_WRAP 0x356C48 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM3_CH1_CTR_WRAP 0x356C4C + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM0_CH0_CTR_CNT 0x356C50 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM0_CH1_CTR_CNT 0x356C54 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM1_CH0_CTR_CNT 0x356C58 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM1_CH1_CTR_CNT 0x356C5C + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM2_CH0_CTR_CNT 0x356C60 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM2_CH1_CTR_CNT 0x356C64 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM3_CH0_CTR_CNT 0x356C68 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM3_CH1_CTR_CNT 0x356C6C + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM0_CH0_CTR_WRAP 0x356C70 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM0_CH1_CTR_WRAP 0x356C74 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM1_CH0_CTR_WRAP 0x356C78 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM1_CH1_CTR_WRAP 0x356C7C + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM2_CH0_CTR_WRAP 0x356C80 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM2_CH1_CTR_WRAP 0x356C84 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM3_CH0_CTR_WRAP 0x356C88 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM3_CH1_CTR_WRAP 0x356C8C + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM0_CH0_CTR_CNT 0x356C90 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM0_CH1_CTR_CNT 0x356C94 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM1_CH0_CTR_CNT 0x356C98 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM1_CH1_CTR_CNT 0x356C9C + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM2_CH0_CTR_CNT 0x356CA0 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM2_CH1_CTR_CNT 0x356CA4 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM3_CH0_CTR_CNT 0x356CA8 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM3_CH1_CTR_CNT 0x356CAC + +#define mmSIF_RTR_CTRL_5_NL_HBM_PC_SEL_0 0x356CB0 + +#define mmSIF_RTR_CTRL_5_NL_HBM_PC_SEL_1 0x356CB4 + +#define mmSIF_RTR_CTRL_5_NL_HBM_PC_SEL_2 0x356CB8 + +#define mmSIF_RTR_CTRL_5_NL_HBM_PC_SEL_3 0x356CBC + +#endif /* ASIC_REG_SIF_RTR_CTRL_5_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_6_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_6_regs.h new file mode 100644 index 000000000000..a9ea89aa6405 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_6_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SIF_RTR_CTRL_6_REGS_H_ +#define ASIC_REG_SIF_RTR_CTRL_6_REGS_H_ + +/* + ***************************************** + * SIF_RTR_CTRL_6 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmSIF_RTR_CTRL_6_PERM_SEL 0x366108 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_0 0x366114 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_1 0x366118 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_2 0x36611C + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_3 0x366120 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_4 0x366124 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_5 0x366128 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_6 0x36612C + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_7 0x366130 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_8 0x366134 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_9 0x366138 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_10 0x36613C + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_11 0x366140 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_12 0x366144 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_13 0x366148 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_14 0x36614C + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_15 0x366150 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_16 0x366154 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_17 0x366158 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_18 0x36615C + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_19 0x366160 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_20 0x366164 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_21 0x366168 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_22 0x36616C + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_23 0x366170 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_24 0x366174 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_25 0x366178 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_26 0x36617C + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_27 0x366180 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_0 0x366184 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_1 0x366188 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_2 0x36618C + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_3 0x366190 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_4 0x366194 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_5 0x366198 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_6 0x36619C + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_7 0x3661A0 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_8 0x3661A4 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_9 0x3661A8 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_10 0x3661AC + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_11 0x3661B0 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_12 0x3661B4 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_13 0x3661B8 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_14 0x3661BC + +#define mmSIF_RTR_CTRL_6_SCRAM_SRAM_EN 0x36626C + +#define mmSIF_RTR_CTRL_6_RL_HBM_EN 0x366274 + +#define mmSIF_RTR_CTRL_6_RL_HBM_SAT 0x366278 + +#define mmSIF_RTR_CTRL_6_RL_HBM_RST 0x36627C + +#define mmSIF_RTR_CTRL_6_RL_HBM_TIMEOUT 0x366280 + +#define mmSIF_RTR_CTRL_6_SCRAM_HBM_EN 0x366284 + +#define mmSIF_RTR_CTRL_6_RL_PCI_EN 0x366288 + +#define mmSIF_RTR_CTRL_6_RL_PCI_SAT 0x36628C + +#define mmSIF_RTR_CTRL_6_RL_PCI_RST 0x366290 + +#define mmSIF_RTR_CTRL_6_RL_PCI_TIMEOUT 0x366294 + +#define mmSIF_RTR_CTRL_6_RL_SRAM_EN 0x36629C + +#define mmSIF_RTR_CTRL_6_RL_SRAM_SAT 0x3662A0 + +#define mmSIF_RTR_CTRL_6_RL_SRAM_RST 0x3662A4 + +#define mmSIF_RTR_CTRL_6_RL_SRAM_TIMEOUT 0x3662AC + +#define mmSIF_RTR_CTRL_6_RL_SRAM_RED 0x3662B4 + +#define mmSIF_RTR_CTRL_6_E2E_HBM_EN 0x3662EC + +#define mmSIF_RTR_CTRL_6_E2E_PCI_EN 0x3662F0 + +#define mmSIF_RTR_CTRL_6_E2E_HBM_WR_SIZE 0x3662F4 + +#define mmSIF_RTR_CTRL_6_E2E_PCI_WR_SIZE 0x3662F8 + +#define mmSIF_RTR_CTRL_6_E2E_AW_PCI_CTR_SET_EN 0x366404 + +#define mmSIF_RTR_CTRL_6_E2E_AW_PCI_CTR_SET 0x366408 + +#define mmSIF_RTR_CTRL_6_E2E_AW_PCI_CTR_WRAP 0x36640C + +#define mmSIF_RTR_CTRL_6_E2E_AW_PCI_CTR_CNT 0x366410 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM_CTR_SET_EN 0x366414 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM_CTR_SET 0x366418 + +#define mmSIF_RTR_CTRL_6_E2E_HBM_RD_SIZE 0x36641C + +#define mmSIF_RTR_CTRL_6_E2E_PCI_RD_SIZE 0x366420 + +#define mmSIF_RTR_CTRL_6_E2E_AR_PCI_CTR_SET_EN 0x366424 + +#define mmSIF_RTR_CTRL_6_E2E_AR_PCI_CTR_SET 0x366428 + +#define mmSIF_RTR_CTRL_6_E2E_AR_PCI_CTR_WRAP 0x36642C + +#define mmSIF_RTR_CTRL_6_E2E_AR_PCI_CTR_CNT 0x366430 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM_CTR_SET_EN 0x366434 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM_CTR_SET 0x366438 + +#define mmSIF_RTR_CTRL_6_NL_HBM_SEL_0 0x366450 + +#define mmSIF_RTR_CTRL_6_NL_HBM_SEL_1 0x366454 + +#define mmSIF_RTR_CTRL_6_NON_LIN_EN 0x366480 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_BANK_0 0x366500 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_BANK_1 0x366504 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_BANK_2 0x366508 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_BANK_3 0x36650C + +#define mmSIF_RTR_CTRL_6_NL_SRAM_BANK_4 0x366510 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_0 0x366514 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_1 0x366520 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_2 0x366524 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_3 0x366528 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_4 0x36652C + +#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_5 0x366530 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_6 0x366534 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_7 0x366538 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_8 0x36653C + +#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_9 0x366540 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_0 0x366550 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_1 0x366554 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_2 0x366558 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_3 0x36655C + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_4 0x366560 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_5 0x366564 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_6 0x366568 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_7 0x36656C + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_8 0x366570 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_9 0x366574 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_10 0x366578 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_11 0x36657C + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_12 0x366580 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_13 0x366584 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_14 0x366588 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_15 0x36658C + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_16 0x366590 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_17 0x366594 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_18 0x366598 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_0 0x3665E4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_1 0x3665E8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_2 0x3665EC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_3 0x3665F0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_4 0x3665F4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_5 0x3665F8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_6 0x3665FC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_7 0x366600 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_8 0x366604 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_9 0x366608 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_10 0x36660C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_11 0x366610 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_12 0x366614 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_13 0x366618 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_14 0x36661C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_15 0x366620 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_0 0x366624 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_1 0x366628 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_2 0x36662C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_3 0x366630 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_4 0x366634 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_5 0x366638 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_6 0x36663C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_7 0x366640 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_8 0x366644 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_9 0x366648 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_10 0x36664C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_11 0x366650 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_12 0x366654 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_13 0x366658 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_14 0x36665C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_15 0x366660 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_0 0x366664 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_1 0x366668 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_2 0x36666C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_3 0x366670 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_4 0x366674 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_5 0x366678 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_6 0x36667C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_7 0x366680 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_8 0x366684 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_9 0x366688 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_10 0x36668C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_11 0x366690 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_12 0x366694 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_13 0x366698 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_14 0x36669C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_15 0x3666A0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_0 0x3666A4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_1 0x3666A8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_2 0x3666AC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_3 0x3666B0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_4 0x3666B4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_5 0x3666B8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_6 0x3666BC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_7 0x3666C0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_8 0x3666C4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_9 0x3666C8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_10 0x3666CC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_11 0x3666D0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_12 0x3666D4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_13 0x3666D8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_14 0x3666DC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_15 0x3666E0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_0 0x3666E4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_1 0x3666E8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_2 0x3666EC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_3 0x3666F0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_4 0x3666F4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_5 0x3666F8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_6 0x3666FC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_7 0x366700 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_8 0x366704 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_9 0x366708 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_10 0x36670C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_11 0x366710 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_12 0x366714 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_13 0x366718 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_14 0x36671C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_15 0x366720 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_0 0x366724 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_1 0x366728 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_2 0x36672C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_3 0x366730 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_4 0x366734 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_5 0x366738 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_6 0x36673C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_7 0x366740 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_8 0x366744 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_9 0x366748 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_10 0x36674C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_11 0x366750 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_12 0x366754 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_13 0x366758 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_14 0x36675C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_15 0x366760 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_0 0x366764 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_1 0x366768 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_2 0x36676C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_3 0x366770 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_4 0x366774 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_5 0x366778 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_6 0x36677C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_7 0x366780 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_8 0x366784 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_9 0x366788 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_10 0x36678C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_11 0x366790 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_12 0x366794 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_13 0x366798 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_14 0x36679C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_15 0x3667A0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_0 0x3667A4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_1 0x3667A8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_2 0x3667AC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_3 0x3667B0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_4 0x3667B4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_5 0x3667B8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_6 0x3667BC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_7 0x3667C0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_8 0x3667C4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_9 0x3667C8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_10 0x3667CC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_11 0x3667D0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_12 0x3667D4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_13 0x3667D8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_14 0x3667DC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_15 0x3667E0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_0 0x366824 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_1 0x366828 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_2 0x36682C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_3 0x366830 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_4 0x366834 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_5 0x366838 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_6 0x36683C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_7 0x366840 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_8 0x366844 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_9 0x366848 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_10 0x36684C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_11 0x366850 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_12 0x366854 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_13 0x366858 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_14 0x36685C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_15 0x366860 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_0 0x366864 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_1 0x366868 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_2 0x36686C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_3 0x366870 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_4 0x366874 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_5 0x366878 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_6 0x36687C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_7 0x366880 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_8 0x366884 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_9 0x366888 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_10 0x36688C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_11 0x366890 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_12 0x366894 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_13 0x366898 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_14 0x36689C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_15 0x3668A0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_0 0x3668A4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_1 0x3668A8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_2 0x3668AC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_3 0x3668B0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_4 0x3668B4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_5 0x3668B8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_6 0x3668BC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_7 0x3668C0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_8 0x3668C4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_9 0x3668C8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_10 0x3668CC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_11 0x3668D0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_12 0x3668D4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_13 0x3668D8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_14 0x3668DC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_15 0x3668E0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_0 0x3668E4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_1 0x3668E8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_2 0x3668EC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_3 0x3668F0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_4 0x3668F4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_5 0x3668F8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_6 0x3668FC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_7 0x366900 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_8 0x366904 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_9 0x366908 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_10 0x36690C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_11 0x366910 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_12 0x366914 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_13 0x366918 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_14 0x36691C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_15 0x366920 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_0 0x366924 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_1 0x366928 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_2 0x36692C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_3 0x366930 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_4 0x366934 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_5 0x366938 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_6 0x36693C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_7 0x366940 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_8 0x366944 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_9 0x366948 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_10 0x36694C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_11 0x366950 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_12 0x366954 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_13 0x366958 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_14 0x36695C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_15 0x366960 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_0 0x366964 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_1 0x366968 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_2 0x36696C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_3 0x366970 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_4 0x366974 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_5 0x366978 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_6 0x36697C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_7 0x366980 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_8 0x366984 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_9 0x366988 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_10 0x36698C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_11 0x366990 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_12 0x366994 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_13 0x366998 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_14 0x36699C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_15 0x3669A0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_0 0x3669A4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_1 0x3669A8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_2 0x3669AC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_3 0x3669B0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_4 0x3669B4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_5 0x3669B8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_6 0x3669BC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_7 0x3669C0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_8 0x3669C4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_9 0x3669C8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_10 0x3669CC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_11 0x3669D0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_12 0x3669D4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_13 0x3669D8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_14 0x3669DC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_15 0x3669E0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_0 0x3669E4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_1 0x3669E8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_2 0x3669EC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_3 0x3669F0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_4 0x3669F4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_5 0x3669F8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_6 0x3669FC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_7 0x366A00 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_8 0x366A04 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_9 0x366A08 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_10 0x366A0C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_11 0x366A10 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_12 0x366A14 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_13 0x366A18 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_14 0x366A1C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_15 0x366A20 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_HIT_AW 0x366A64 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_HIT_AR 0x366A68 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_HIT_AW 0x366A6C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_HIT_AR 0x366A70 + +#define mmSIF_RTR_CTRL_6_RGL_CFG 0x366B64 + +#define mmSIF_RTR_CTRL_6_RGL_SHIFT 0x366B68 + +#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_0 0x366B6C + +#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_1 0x366B70 + +#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_2 0x366B74 + +#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_3 0x366B78 + +#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_4 0x366B7C + +#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_5 0x366B80 + +#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_6 0x366B84 + +#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_7 0x366B88 + +#define mmSIF_RTR_CTRL_6_RGL_TOKEN_0 0x366BAC + +#define mmSIF_RTR_CTRL_6_RGL_TOKEN_1 0x366BB0 + +#define mmSIF_RTR_CTRL_6_RGL_TOKEN_2 0x366BB4 + +#define mmSIF_RTR_CTRL_6_RGL_TOKEN_3 0x366BB8 + +#define mmSIF_RTR_CTRL_6_RGL_TOKEN_4 0x366BBC + +#define mmSIF_RTR_CTRL_6_RGL_TOKEN_5 0x366BC0 + +#define mmSIF_RTR_CTRL_6_RGL_TOKEN_6 0x366BC4 + +#define mmSIF_RTR_CTRL_6_RGL_TOKEN_7 0x366BC8 + +#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_0 0x366BEC + +#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_1 0x366BF0 + +#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_2 0x366BF4 + +#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_3 0x366BF8 + +#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_4 0x366BFC + +#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_5 0x366C00 + +#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_6 0x366C04 + +#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_7 0x366C08 + +#define mmSIF_RTR_CTRL_6_RGL_WDT 0x366C2C + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM0_CH0_CTR_WRAP 0x366C30 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM0_CH1_CTR_WRAP 0x366C34 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM1_CH0_CTR_WRAP 0x366C38 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM1_CH1_CTR_WRAP 0x366C3C + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM2_CH0_CTR_WRAP 0x366C40 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM2_CH1_CTR_WRAP 0x366C44 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM3_CH0_CTR_WRAP 0x366C48 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM3_CH1_CTR_WRAP 0x366C4C + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM0_CH0_CTR_CNT 0x366C50 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM0_CH1_CTR_CNT 0x366C54 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM1_CH0_CTR_CNT 0x366C58 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM1_CH1_CTR_CNT 0x366C5C + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM2_CH0_CTR_CNT 0x366C60 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM2_CH1_CTR_CNT 0x366C64 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM3_CH0_CTR_CNT 0x366C68 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM3_CH1_CTR_CNT 0x366C6C + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM0_CH0_CTR_WRAP 0x366C70 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM0_CH1_CTR_WRAP 0x366C74 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM1_CH0_CTR_WRAP 0x366C78 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM1_CH1_CTR_WRAP 0x366C7C + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM2_CH0_CTR_WRAP 0x366C80 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM2_CH1_CTR_WRAP 0x366C84 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM3_CH0_CTR_WRAP 0x366C88 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM3_CH1_CTR_WRAP 0x366C8C + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM0_CH0_CTR_CNT 0x366C90 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM0_CH1_CTR_CNT 0x366C94 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM1_CH0_CTR_CNT 0x366C98 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM1_CH1_CTR_CNT 0x366C9C + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM2_CH0_CTR_CNT 0x366CA0 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM2_CH1_CTR_CNT 0x366CA4 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM3_CH0_CTR_CNT 0x366CA8 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM3_CH1_CTR_CNT 0x366CAC + +#define mmSIF_RTR_CTRL_6_NL_HBM_PC_SEL_0 0x366CB0 + +#define mmSIF_RTR_CTRL_6_NL_HBM_PC_SEL_1 0x366CB4 + +#define mmSIF_RTR_CTRL_6_NL_HBM_PC_SEL_2 0x366CB8 + +#define mmSIF_RTR_CTRL_6_NL_HBM_PC_SEL_3 0x366CBC + +#endif /* ASIC_REG_SIF_RTR_CTRL_6_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_7_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_7_regs.h new file mode 100644 index 000000000000..a37772c531d9 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_7_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SIF_RTR_CTRL_7_REGS_H_ +#define ASIC_REG_SIF_RTR_CTRL_7_REGS_H_ + +/* + ***************************************** + * SIF_RTR_CTRL_7 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmSIF_RTR_CTRL_7_PERM_SEL 0x376108 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_0 0x376114 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_1 0x376118 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_2 0x37611C + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_3 0x376120 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_4 0x376124 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_5 0x376128 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_6 0x37612C + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_7 0x376130 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_8 0x376134 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_9 0x376138 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_10 0x37613C + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_11 0x376140 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_12 0x376144 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_13 0x376148 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_14 0x37614C + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_15 0x376150 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_16 0x376154 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_17 0x376158 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_18 0x37615C + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_19 0x376160 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_20 0x376164 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_21 0x376168 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_22 0x37616C + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_23 0x376170 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_24 0x376174 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_25 0x376178 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_26 0x37617C + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_27 0x376180 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_0 0x376184 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_1 0x376188 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_2 0x37618C + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_3 0x376190 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_4 0x376194 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_5 0x376198 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_6 0x37619C + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_7 0x3761A0 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_8 0x3761A4 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_9 0x3761A8 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_10 0x3761AC + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_11 0x3761B0 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_12 0x3761B4 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_13 0x3761B8 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_14 0x3761BC + +#define mmSIF_RTR_CTRL_7_SCRAM_SRAM_EN 0x37626C + +#define mmSIF_RTR_CTRL_7_RL_HBM_EN 0x376274 + +#define mmSIF_RTR_CTRL_7_RL_HBM_SAT 0x376278 + +#define mmSIF_RTR_CTRL_7_RL_HBM_RST 0x37627C + +#define mmSIF_RTR_CTRL_7_RL_HBM_TIMEOUT 0x376280 + +#define mmSIF_RTR_CTRL_7_SCRAM_HBM_EN 0x376284 + +#define mmSIF_RTR_CTRL_7_RL_PCI_EN 0x376288 + +#define mmSIF_RTR_CTRL_7_RL_PCI_SAT 0x37628C + +#define mmSIF_RTR_CTRL_7_RL_PCI_RST 0x376290 + +#define mmSIF_RTR_CTRL_7_RL_PCI_TIMEOUT 0x376294 + +#define mmSIF_RTR_CTRL_7_RL_SRAM_EN 0x37629C + +#define mmSIF_RTR_CTRL_7_RL_SRAM_SAT 0x3762A0 + +#define mmSIF_RTR_CTRL_7_RL_SRAM_RST 0x3762A4 + +#define mmSIF_RTR_CTRL_7_RL_SRAM_TIMEOUT 0x3762AC + +#define mmSIF_RTR_CTRL_7_RL_SRAM_RED 0x3762B4 + +#define mmSIF_RTR_CTRL_7_E2E_HBM_EN 0x3762EC + +#define mmSIF_RTR_CTRL_7_E2E_PCI_EN 0x3762F0 + +#define mmSIF_RTR_CTRL_7_E2E_HBM_WR_SIZE 0x3762F4 + +#define mmSIF_RTR_CTRL_7_E2E_PCI_WR_SIZE 0x3762F8 + +#define mmSIF_RTR_CTRL_7_E2E_AW_PCI_CTR_SET_EN 0x376404 + +#define mmSIF_RTR_CTRL_7_E2E_AW_PCI_CTR_SET 0x376408 + +#define mmSIF_RTR_CTRL_7_E2E_AW_PCI_CTR_WRAP 0x37640C + +#define mmSIF_RTR_CTRL_7_E2E_AW_PCI_CTR_CNT 0x376410 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM_CTR_SET_EN 0x376414 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM_CTR_SET 0x376418 + +#define mmSIF_RTR_CTRL_7_E2E_HBM_RD_SIZE 0x37641C + +#define mmSIF_RTR_CTRL_7_E2E_PCI_RD_SIZE 0x376420 + +#define mmSIF_RTR_CTRL_7_E2E_AR_PCI_CTR_SET_EN 0x376424 + +#define mmSIF_RTR_CTRL_7_E2E_AR_PCI_CTR_SET 0x376428 + +#define mmSIF_RTR_CTRL_7_E2E_AR_PCI_CTR_WRAP 0x37642C + +#define mmSIF_RTR_CTRL_7_E2E_AR_PCI_CTR_CNT 0x376430 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM_CTR_SET_EN 0x376434 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM_CTR_SET 0x376438 + +#define mmSIF_RTR_CTRL_7_NL_HBM_SEL_0 0x376450 + +#define mmSIF_RTR_CTRL_7_NL_HBM_SEL_1 0x376454 + +#define mmSIF_RTR_CTRL_7_NON_LIN_EN 0x376480 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_BANK_0 0x376500 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_BANK_1 0x376504 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_BANK_2 0x376508 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_BANK_3 0x37650C + +#define mmSIF_RTR_CTRL_7_NL_SRAM_BANK_4 0x376510 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_0 0x376514 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_1 0x376520 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_2 0x376524 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_3 0x376528 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_4 0x37652C + +#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_5 0x376530 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_6 0x376534 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_7 0x376538 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_8 0x37653C + +#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_9 0x376540 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_0 0x376550 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_1 0x376554 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_2 0x376558 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_3 0x37655C + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_4 0x376560 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_5 0x376564 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_6 0x376568 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_7 0x37656C + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_8 0x376570 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_9 0x376574 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_10 0x376578 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_11 0x37657C + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_12 0x376580 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_13 0x376584 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_14 0x376588 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_15 0x37658C + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_16 0x376590 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_17 0x376594 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_18 0x376598 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_0 0x3765E4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_1 0x3765E8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_2 0x3765EC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_3 0x3765F0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_4 0x3765F4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_5 0x3765F8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_6 0x3765FC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_7 0x376600 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_8 0x376604 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_9 0x376608 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_10 0x37660C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_11 0x376610 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_12 0x376614 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_13 0x376618 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_14 0x37661C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_15 0x376620 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_0 0x376624 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_1 0x376628 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_2 0x37662C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_3 0x376630 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_4 0x376634 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_5 0x376638 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_6 0x37663C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_7 0x376640 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_8 0x376644 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_9 0x376648 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_10 0x37664C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_11 0x376650 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_12 0x376654 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_13 0x376658 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_14 0x37665C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_15 0x376660 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_0 0x376664 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_1 0x376668 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_2 0x37666C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_3 0x376670 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_4 0x376674 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_5 0x376678 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_6 0x37667C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_7 0x376680 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_8 0x376684 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_9 0x376688 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_10 0x37668C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_11 0x376690 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_12 0x376694 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_13 0x376698 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_14 0x37669C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_15 0x3766A0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_0 0x3766A4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_1 0x3766A8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_2 0x3766AC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_3 0x3766B0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_4 0x3766B4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_5 0x3766B8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_6 0x3766BC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_7 0x3766C0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_8 0x3766C4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_9 0x3766C8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_10 0x3766CC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_11 0x3766D0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_12 0x3766D4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_13 0x3766D8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_14 0x3766DC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_15 0x3766E0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_0 0x3766E4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_1 0x3766E8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_2 0x3766EC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_3 0x3766F0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_4 0x3766F4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_5 0x3766F8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_6 0x3766FC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_7 0x376700 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_8 0x376704 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_9 0x376708 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_10 0x37670C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_11 0x376710 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_12 0x376714 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_13 0x376718 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_14 0x37671C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_15 0x376720 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_0 0x376724 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_1 0x376728 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_2 0x37672C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_3 0x376730 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_4 0x376734 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_5 0x376738 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_6 0x37673C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_7 0x376740 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_8 0x376744 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_9 0x376748 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_10 0x37674C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_11 0x376750 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_12 0x376754 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_13 0x376758 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_14 0x37675C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_15 0x376760 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_0 0x376764 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_1 0x376768 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_2 0x37676C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_3 0x376770 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_4 0x376774 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_5 0x376778 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_6 0x37677C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_7 0x376780 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_8 0x376784 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_9 0x376788 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_10 0x37678C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_11 0x376790 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_12 0x376794 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_13 0x376798 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_14 0x37679C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_15 0x3767A0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_0 0x3767A4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_1 0x3767A8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_2 0x3767AC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_3 0x3767B0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_4 0x3767B4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_5 0x3767B8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_6 0x3767BC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_7 0x3767C0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_8 0x3767C4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_9 0x3767C8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_10 0x3767CC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_11 0x3767D0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_12 0x3767D4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_13 0x3767D8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_14 0x3767DC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_15 0x3767E0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_0 0x376824 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_1 0x376828 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_2 0x37682C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_3 0x376830 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_4 0x376834 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_5 0x376838 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_6 0x37683C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_7 0x376840 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_8 0x376844 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_9 0x376848 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_10 0x37684C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_11 0x376850 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_12 0x376854 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_13 0x376858 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_14 0x37685C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_15 0x376860 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_0 0x376864 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_1 0x376868 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_2 0x37686C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_3 0x376870 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_4 0x376874 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_5 0x376878 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_6 0x37687C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_7 0x376880 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_8 0x376884 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_9 0x376888 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_10 0x37688C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_11 0x376890 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_12 0x376894 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_13 0x376898 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_14 0x37689C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_15 0x3768A0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_0 0x3768A4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_1 0x3768A8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_2 0x3768AC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_3 0x3768B0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_4 0x3768B4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_5 0x3768B8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_6 0x3768BC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_7 0x3768C0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_8 0x3768C4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_9 0x3768C8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_10 0x3768CC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_11 0x3768D0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_12 0x3768D4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_13 0x3768D8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_14 0x3768DC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_15 0x3768E0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_0 0x3768E4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_1 0x3768E8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_2 0x3768EC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_3 0x3768F0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_4 0x3768F4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_5 0x3768F8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_6 0x3768FC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_7 0x376900 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_8 0x376904 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_9 0x376908 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_10 0x37690C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_11 0x376910 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_12 0x376914 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_13 0x376918 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_14 0x37691C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_15 0x376920 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_0 0x376924 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_1 0x376928 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_2 0x37692C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_3 0x376930 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_4 0x376934 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_5 0x376938 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_6 0x37693C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_7 0x376940 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_8 0x376944 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_9 0x376948 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_10 0x37694C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_11 0x376950 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_12 0x376954 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_13 0x376958 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_14 0x37695C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_15 0x376960 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_0 0x376964 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_1 0x376968 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_2 0x37696C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_3 0x376970 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_4 0x376974 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_5 0x376978 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_6 0x37697C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_7 0x376980 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_8 0x376984 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_9 0x376988 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_10 0x37698C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_11 0x376990 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_12 0x376994 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_13 0x376998 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_14 0x37699C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_15 0x3769A0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_0 0x3769A4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_1 0x3769A8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_2 0x3769AC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_3 0x3769B0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_4 0x3769B4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_5 0x3769B8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_6 0x3769BC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_7 0x3769C0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_8 0x3769C4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_9 0x3769C8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_10 0x3769CC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_11 0x3769D0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_12 0x3769D4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_13 0x3769D8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_14 0x3769DC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_15 0x3769E0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_0 0x3769E4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_1 0x3769E8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_2 0x3769EC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_3 0x3769F0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_4 0x3769F4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_5 0x3769F8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_6 0x3769FC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_7 0x376A00 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_8 0x376A04 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_9 0x376A08 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_10 0x376A0C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_11 0x376A10 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_12 0x376A14 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_13 0x376A18 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_14 0x376A1C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_15 0x376A20 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_HIT_AW 0x376A64 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_HIT_AR 0x376A68 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_HIT_AW 0x376A6C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_HIT_AR 0x376A70 + +#define mmSIF_RTR_CTRL_7_RGL_CFG 0x376B64 + +#define mmSIF_RTR_CTRL_7_RGL_SHIFT 0x376B68 + +#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_0 0x376B6C + +#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_1 0x376B70 + +#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_2 0x376B74 + +#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_3 0x376B78 + +#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_4 0x376B7C + +#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_5 0x376B80 + +#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_6 0x376B84 + +#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_7 0x376B88 + +#define mmSIF_RTR_CTRL_7_RGL_TOKEN_0 0x376BAC + +#define mmSIF_RTR_CTRL_7_RGL_TOKEN_1 0x376BB0 + +#define mmSIF_RTR_CTRL_7_RGL_TOKEN_2 0x376BB4 + +#define mmSIF_RTR_CTRL_7_RGL_TOKEN_3 0x376BB8 + +#define mmSIF_RTR_CTRL_7_RGL_TOKEN_4 0x376BBC + +#define mmSIF_RTR_CTRL_7_RGL_TOKEN_5 0x376BC0 + +#define mmSIF_RTR_CTRL_7_RGL_TOKEN_6 0x376BC4 + +#define mmSIF_RTR_CTRL_7_RGL_TOKEN_7 0x376BC8 + +#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_0 0x376BEC + +#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_1 0x376BF0 + +#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_2 0x376BF4 + +#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_3 0x376BF8 + +#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_4 0x376BFC + +#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_5 0x376C00 + +#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_6 0x376C04 + +#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_7 0x376C08 + +#define mmSIF_RTR_CTRL_7_RGL_WDT 0x376C2C + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM0_CH0_CTR_WRAP 0x376C30 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM0_CH1_CTR_WRAP 0x376C34 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM1_CH0_CTR_WRAP 0x376C38 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM1_CH1_CTR_WRAP 0x376C3C + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM2_CH0_CTR_WRAP 0x376C40 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM2_CH1_CTR_WRAP 0x376C44 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM3_CH0_CTR_WRAP 0x376C48 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM3_CH1_CTR_WRAP 0x376C4C + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM0_CH0_CTR_CNT 0x376C50 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM0_CH1_CTR_CNT 0x376C54 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM1_CH0_CTR_CNT 0x376C58 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM1_CH1_CTR_CNT 0x376C5C + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM2_CH0_CTR_CNT 0x376C60 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM2_CH1_CTR_CNT 0x376C64 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM3_CH0_CTR_CNT 0x376C68 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM3_CH1_CTR_CNT 0x376C6C + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM0_CH0_CTR_WRAP 0x376C70 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM0_CH1_CTR_WRAP 0x376C74 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM1_CH0_CTR_WRAP 0x376C78 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM1_CH1_CTR_WRAP 0x376C7C + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM2_CH0_CTR_WRAP 0x376C80 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM2_CH1_CTR_WRAP 0x376C84 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM3_CH0_CTR_WRAP 0x376C88 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM3_CH1_CTR_WRAP 0x376C8C + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM0_CH0_CTR_CNT 0x376C90 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM0_CH1_CTR_CNT 0x376C94 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM1_CH0_CTR_CNT 0x376C98 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM1_CH1_CTR_CNT 0x376C9C + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM2_CH0_CTR_CNT 0x376CA0 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM2_CH1_CTR_CNT 0x376CA4 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM3_CH0_CTR_CNT 0x376CA8 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM3_CH1_CTR_CNT 0x376CAC + +#define mmSIF_RTR_CTRL_7_NL_HBM_PC_SEL_0 0x376CB0 + +#define mmSIF_RTR_CTRL_7_NL_HBM_PC_SEL_1 0x376CB4 + +#define mmSIF_RTR_CTRL_7_NL_HBM_PC_SEL_2 0x376CB8 + +#define mmSIF_RTR_CTRL_7_NL_HBM_PC_SEL_3 0x376CBC + +#endif /* ASIC_REG_SIF_RTR_CTRL_7_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/stlb_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/stlb_regs.h new file mode 100644 index 000000000000..07d2a9000102 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/stlb_regs.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_STLB_REGS_H_ +#define ASIC_REG_STLB_REGS_H_ + +/* + ***************************************** + * STLB (Prototype: STLB) + ***************************************** + */ + +#define mmSTLB_CACHE_INV 0xC12010 + +#define mmSTLB_CACHE_INV_BASE_39_8 0xC12014 + +#define mmSTLB_CACHE_INV_BASE_49_40 0xC12018 + +#define mmSTLB_STLB_FEATURE_EN 0xC1201C + +#define mmSTLB_STLB_AXI_CACHE 0xC12020 + +#define mmSTLB_HOP_CONFIGURATION 0xC12024 + +#define mmSTLB_LINK_LIST_LOOKUP_MASK_49_32 0xC12028 + +#define mmSTLB_LINK_LIST_LOOKUP_MASK_31_0 0xC1202C + +#define mmSTLB_LINK_LIST 0xC12030 + +#define mmSTLB_INV_ALL_START 0xC12034 + +#define mmSTLB_INV_ALL_SET 0xC12038 + +#define mmSTLB_INV_PS 0xC1203C + +#define mmSTLB_INV_CONSUMER_INDEX 0xC12040 + +#define mmSTLB_INV_HIT_COUNT 0xC12044 + +#define mmSTLB_INV_SET 0xC12048 + +#define mmSTLB_SRAM_INIT 0xC1204C + +#define mmSTLB_MEM_CACHE_INVALIDATION 0xC12050 + +#define mmSTLB_MEM_CACHE_INV_STATUS 0xC12054 + +#define mmSTLB_MEM_CACHE_BASE_38_7 0xC12058 + +#define mmSTLB_MEM_CACHE_BASE_49_39 0xC1205C + +#define mmSTLB_MEM_CACHE_CONFIG 0xC12060 + +#define mmSTLB_SET_THRESHOLD_HOP4 0xC12064 + +#define mmSTLB_SET_THRESHOLD_HOP3 0xC12068 + +#define mmSTLB_SET_THRESHOLD_HOP2 0xC1206C + +#define mmSTLB_SET_THRESHOLD_HOP1 0xC12070 + +#define mmSTLB_SET_THRESHOLD_HOP0 0xC12074 + +#define mmSTLB_MULTI_HIT_INTERRUPT_CLR 0xC12078 + +#define mmSTLB_MULTI_HIT_INTERRUPT_MASK 0xC1207C + +#define mmSTLB_MEM_L0_CACHE_CFG 0xC12080 + +#define mmSTLB_MEM_READ_ARPROT 0xC12084 + +#endif /* ASIC_REG_STLB_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_cfg_masks.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_cfg_masks.h new file mode 100644 index 000000000000..8f67c11c8de9 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_cfg_masks.h @@ -0,0 +1,2578 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_CFG_MASKS_H_ +#define ASIC_REG_TPC0_CFG_MASKS_H_ + +/* + ***************************************** + * TPC0_CFG (Prototype: TPC) + ***************************************** + */ + +/* TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE */ +#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT 0 +#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK 0xFFFF +#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_RSV_SHIFT 16 +#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_RSV_MASK 0x1FFF0000 +#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT 29 +#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK 0xE0000000 + +/* TPC0_CFG_KERNEL_SYNC_OBJECT_ADDR */ +#define TPC0_CFG_KERNEL_SYNC_OBJECT_ADDR_V_SHIFT 0 +#define TPC0_CFG_KERNEL_SYNC_OBJECT_ADDR_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW */ +#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH */ +#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_BASE_DIM_0 */ +#define TPC0_CFG_KERNEL_TID_BASE_DIM_0_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_BASE_DIM_0_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_SIZE_DIM_0 */ +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_0_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_0_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_BASE_DIM_1 */ +#define TPC0_CFG_KERNEL_TID_BASE_DIM_1_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_BASE_DIM_1_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_SIZE_DIM_1 */ +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_1_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_1_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_BASE_DIM_2 */ +#define TPC0_CFG_KERNEL_TID_BASE_DIM_2_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_BASE_DIM_2_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_SIZE_DIM_2 */ +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_2_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_2_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_BASE_DIM_3 */ +#define TPC0_CFG_KERNEL_TID_BASE_DIM_3_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_BASE_DIM_3_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_SIZE_DIM_3 */ +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_3_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_3_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_BASE_DIM_4 */ +#define TPC0_CFG_KERNEL_TID_BASE_DIM_4_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_BASE_DIM_4_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_SIZE_DIM_4 */ +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_4_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_4_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_KERNEL_CONFIG */ +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_SMALL_VLM_SHIFT 0 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_SMALL_VLM_MASK 0x1 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT 1 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_MASK 0x2 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT 2 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_MASK 0xFC +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_SHIFT 8 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_MASK 0xFF00 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_SHIFT 16 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_MASK 0xFF0000 + +/* TPC0_CFG_KERNEL_KERNEL_ID */ +#define TPC0_CFG_KERNEL_KERNEL_ID_V_SHIFT 0 +#define TPC0_CFG_KERNEL_KERNEL_ID_V_MASK 0xFFFF + +/* TPC0_CFG_KERNEL_SRF */ +#define TPC0_CFG_KERNEL_SRF_V_SHIFT 0 +#define TPC0_CFG_KERNEL_SRF_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_ROUND_CSR */ +#define TPC0_CFG_ROUND_CSR_MODE_SHIFT 0 +#define TPC0_CFG_ROUND_CSR_MODE_MASK 0x7 + +/* TPC0_CFG_PROT */ +#define TPC0_CFG_PROT_AWPROT_SHIFT 0 +#define TPC0_CFG_PROT_AWPROT_MASK 0x7 +#define TPC0_CFG_PROT_ARPROT_SHIFT 3 +#define TPC0_CFG_PROT_ARPROT_MASK 0x38 + +/* TPC0_CFG_SEMAPHORE */ +#define TPC0_CFG_SEMAPHORE_V_SHIFT 0 +#define TPC0_CFG_SEMAPHORE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_VFLAGS */ +#define TPC0_CFG_VFLAGS_V_SHIFT 0 +#define TPC0_CFG_VFLAGS_V_MASK 0xF + +/* TPC0_CFG_SFLAGS */ +#define TPC0_CFG_SFLAGS_V_SHIFT 0 +#define TPC0_CFG_SFLAGS_V_MASK 0xF + +/* TPC0_CFG_LFSR_POLYNOM */ +#define TPC0_CFG_LFSR_POLYNOM_V_SHIFT 0 +#define TPC0_CFG_LFSR_POLYNOM_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_STATUS */ +#define TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT 1 +#define TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK 0x2 +#define TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT 2 +#define TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK 0x4 +#define TPC0_CFG_STATUS_IQ_EMPTY_SHIFT 3 +#define TPC0_CFG_STATUS_IQ_EMPTY_MASK 0x8 +#define TPC0_CFG_STATUS_SB_EMPTY_SHIFT 5 +#define TPC0_CFG_STATUS_SB_EMPTY_MASK 0x20 +#define TPC0_CFG_STATUS_QM_IDLE_SHIFT 6 +#define TPC0_CFG_STATUS_QM_IDLE_MASK 0x40 +#define TPC0_CFG_STATUS_QM_RDY_SHIFT 7 +#define TPC0_CFG_STATUS_QM_RDY_MASK 0x80 + +/* TPC0_CFG_CFG_BASE_ADDRESS_HIGH */ +#define TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_CFG_SUBTRACT_VALUE */ +#define TPC0_CFG_CFG_SUBTRACT_VALUE_V_SHIFT 0 +#define TPC0_CFG_CFG_SUBTRACT_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_SM_BASE_ADDRESS_HIGH */ +#define TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_TPC_CMD */ +#define TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_SHIFT 0 +#define TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_MASK 0x1 +#define TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_SHIFT 1 +#define TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_MASK 0x2 +#define TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_SHIFT 2 +#define TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_MASK 0x4 +#define TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_SHIFT 3 +#define TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_MASK 0x8 +#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_SHIFT 4 +#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_MASK 0x10 +#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_SHIFT 5 +#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_MASK 0x20 +#define TPC0_CFG_TPC_CMD_QMAN_STOP_SHIFT 6 +#define TPC0_CFG_TPC_CMD_QMAN_STOP_MASK 0x40 + +/* TPC0_CFG_TPC_EXECUTE */ +#define TPC0_CFG_TPC_EXECUTE_V_SHIFT 0 +#define TPC0_CFG_TPC_EXECUTE_V_MASK 0x1 + +/* TPC0_CFG_TPC_STALL */ +#define TPC0_CFG_TPC_STALL_V_SHIFT 0 +#define TPC0_CFG_TPC_STALL_V_MASK 0x1 + +/* TPC0_CFG_ICACHE_BASE_ADDERESS_LOW */ +#define TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_SHIFT 0 +#define TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH */ +#define TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_SHIFT 0 +#define TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_RD_RATE_LIMIT */ +#define TPC0_CFG_RD_RATE_LIMIT_ENABLE_SHIFT 0 +#define TPC0_CFG_RD_RATE_LIMIT_ENABLE_MASK 0x1 +#define TPC0_CFG_RD_RATE_LIMIT_SATURATION_SHIFT 1 +#define TPC0_CFG_RD_RATE_LIMIT_SATURATION_MASK 0x1FE +#define TPC0_CFG_RD_RATE_LIMIT_TIMEOUT_SHIFT 9 +#define TPC0_CFG_RD_RATE_LIMIT_TIMEOUT_MASK 0x1FE00 + +/* TPC0_CFG_WR_RATE_LIMIT */ +#define TPC0_CFG_WR_RATE_LIMIT_ENABLE_SHIFT 0 +#define TPC0_CFG_WR_RATE_LIMIT_ENABLE_MASK 0x1 +#define TPC0_CFG_WR_RATE_LIMIT_SATURATION_SHIFT 1 +#define TPC0_CFG_WR_RATE_LIMIT_SATURATION_MASK 0x1FE +#define TPC0_CFG_WR_RATE_LIMIT_TIMEOUT_SHIFT 9 +#define TPC0_CFG_WR_RATE_LIMIT_TIMEOUT_MASK 0x1FE00 + +/* TPC0_CFG_MSS_CONFIG */ +#define TPC0_CFG_MSS_CONFIG_AWCACHE_SHIFT 0 +#define TPC0_CFG_MSS_CONFIG_AWCACHE_MASK 0xF +#define TPC0_CFG_MSS_CONFIG_ARCACHE_SHIFT 4 +#define TPC0_CFG_MSS_CONFIG_ARCACHE_MASK 0xF0 +#define TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_SHIFT 8 +#define TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_MASK 0x300 +#define TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_SHIFT 10 +#define TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_MASK 0x400 +#define TPC0_CFG_MSS_CONFIG_DCACHE_PREFETCH_DIS_SHIFT 11 +#define TPC0_CFG_MSS_CONFIG_DCACHE_PREFETCH_DIS_MASK 0x800 + +/* TPC0_CFG_TPC_INTR_CAUSE */ +#define TPC0_CFG_TPC_INTR_CAUSE_CAUSE_SHIFT 0 +#define TPC0_CFG_TPC_INTR_CAUSE_CAUSE_MASK 0xFFFFF + +/* TPC0_CFG_TPC_INTR_MASK */ +#define TPC0_CFG_TPC_INTR_MASK_MASK_SHIFT 0 +#define TPC0_CFG_TPC_INTR_MASK_MASK_MASK 0xFFFFF + +/* TPC0_CFG_WQ_CREDITS */ +#define TPC0_CFG_WQ_CREDITS_ST_G_SHIFT 0 +#define TPC0_CFG_WQ_CREDITS_ST_G_MASK 0xF +#define TPC0_CFG_WQ_CREDITS_KERNEL_FIFO_SHIFT 4 +#define TPC0_CFG_WQ_CREDITS_KERNEL_FIFO_MASK 0x70 + +/* TPC0_CFG_ARUSER_LO */ +#define TPC0_CFG_ARUSER_LO_V_SHIFT 0 +#define TPC0_CFG_ARUSER_LO_V_MASK 0x7FF + +/* TPC0_CFG_ARUSER_HI */ +#define TPC0_CFG_ARUSER_HI_V_SHIFT 11 +#define TPC0_CFG_ARUSER_HI_V_MASK 0x1800 +#define TPC0_CFG_ARUSER_HI_RSRV_SHIFT 13 +#define TPC0_CFG_ARUSER_HI_RSRV_MASK 0xFFFFE000 + +/* TPC0_CFG_AWUSER_LO */ +#define TPC0_CFG_AWUSER_LO_V_SHIFT 0 +#define TPC0_CFG_AWUSER_LO_V_MASK 0x7FF + +/* TPC0_CFG_AWUSER_HI */ +#define TPC0_CFG_AWUSER_HI_V_SHIFT 11 +#define TPC0_CFG_AWUSER_HI_V_MASK 0x1800 +#define TPC0_CFG_AWUSER_HI_RSRV_SHIFT 13 +#define TPC0_CFG_AWUSER_HI_RSRV_MASK 0xFFFFE000 + +/* TPC0_CFG_OPCODE_EXEC */ +#define TPC0_CFG_OPCODE_EXEC_SPU_OP_SHIFT 0 +#define TPC0_CFG_OPCODE_EXEC_SPU_OP_MASK 0x7F +#define TPC0_CFG_OPCODE_EXEC_SPU_EN_SHIFT 7 +#define TPC0_CFG_OPCODE_EXEC_SPU_EN_MASK 0x80 +#define TPC0_CFG_OPCODE_EXEC_VPU_OP_SHIFT 8 +#define TPC0_CFG_OPCODE_EXEC_VPU_OP_MASK 0x7F00 +#define TPC0_CFG_OPCODE_EXEC_VPU_EN_SHIFT 15 +#define TPC0_CFG_OPCODE_EXEC_VPU_EN_MASK 0x8000 +#define TPC0_CFG_OPCODE_EXEC_LD_OP_SHIFT 16 +#define TPC0_CFG_OPCODE_EXEC_LD_OP_MASK 0x7F0000 +#define TPC0_CFG_OPCODE_EXEC_LD_EN_SHIFT 23 +#define TPC0_CFG_OPCODE_EXEC_LD_EN_MASK 0x800000 +#define TPC0_CFG_OPCODE_EXEC_ST_OP_SHIFT 24 +#define TPC0_CFG_OPCODE_EXEC_ST_OP_MASK 0x7F000000 +#define TPC0_CFG_OPCODE_EXEC_ST_EN_SHIFT 31 +#define TPC0_CFG_OPCODE_EXEC_ST_EN_MASK 0x80000000 + +/* TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO */ +#define TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO_V_SHIFT 0 +#define TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI */ +#define TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI_V_SHIFT 0 +#define TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO */ +#define TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO_V_SHIFT 0 +#define TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI */ +#define TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI_V_SHIFT 0 +#define TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO */ +#define TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO_V_SHIFT 0 +#define TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI */ +#define TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI_V_SHIFT 0 +#define TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO */ +#define TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO_V_SHIFT 0 +#define TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI */ +#define TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI_V_SHIFT 0 +#define TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_TSB_CFG_MAX_SIZE */ +#define TPC0_CFG_TSB_CFG_MAX_SIZE_DATA_SHIFT 0 +#define TPC0_CFG_TSB_CFG_MAX_SIZE_DATA_MASK 0xFFFF +#define TPC0_CFG_TSB_CFG_MAX_SIZE_MD_SHIFT 16 +#define TPC0_CFG_TSB_CFG_MAX_SIZE_MD_MASK 0xFFFF0000 + +/* TPC0_CFG_TSB_CFG */ +#define TPC0_CFG_TSB_CFG_FORCE_MISS_SHIFT 0 +#define TPC0_CFG_TSB_CFG_FORCE_MISS_MASK 0x1 +#define TPC0_CFG_TSB_CFG_MAX_OS_SHIFT 1 +#define TPC0_CFG_TSB_CFG_MAX_OS_MASK 0x1FFFE + +/* TPC0_CFG_DBGMEM_ADD */ +#define TPC0_CFG_DBGMEM_ADD_V_SHIFT 0 +#define TPC0_CFG_DBGMEM_ADD_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_DBGMEM_DATA_WR */ +#define TPC0_CFG_DBGMEM_DATA_WR_V_SHIFT 0 +#define TPC0_CFG_DBGMEM_DATA_WR_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_DBGMEM_DATA_RD */ +#define TPC0_CFG_DBGMEM_DATA_RD_V_SHIFT 0 +#define TPC0_CFG_DBGMEM_DATA_RD_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_DBGMEM_CTRL */ +#define TPC0_CFG_DBGMEM_CTRL_WR_NRD_SHIFT 0 +#define TPC0_CFG_DBGMEM_CTRL_WR_NRD_MASK 0x1 + +/* TPC0_CFG_DBGMEM_RC */ +#define TPC0_CFG_DBGMEM_RC_VALID_SHIFT 0 +#define TPC0_CFG_DBGMEM_RC_VALID_MASK 0x1 + +/* TPC0_CFG_TSB_INFLIGHT_CNTR */ +#define TPC0_CFG_TSB_INFLIGHT_CNTR_V_SHIFT 0 +#define TPC0_CFG_TSB_INFLIGHT_CNTR_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_WQ_INFLIGHT_CNTR */ +#define TPC0_CFG_WQ_INFLIGHT_CNTR_HBW_SHIFT 0 +#define TPC0_CFG_WQ_INFLIGHT_CNTR_HBW_MASK 0xFFFF +#define TPC0_CFG_WQ_INFLIGHT_CNTR_LBW_SHIFT 16 +#define TPC0_CFG_WQ_INFLIGHT_CNTR_LBW_MASK 0xF0000 + +/* TPC0_CFG_WQ_LBW_TOTAL_CNTR */ +#define TPC0_CFG_WQ_LBW_TOTAL_CNTR_V_SHIFT 0 +#define TPC0_CFG_WQ_LBW_TOTAL_CNTR_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_WQ_HBW_TOTAL_CNTR */ +#define TPC0_CFG_WQ_HBW_TOTAL_CNTR_V_SHIFT 0 +#define TPC0_CFG_WQ_HBW_TOTAL_CNTR_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_IRQ_OCCOUPY_CNTR */ +#define TPC0_CFG_IRQ_OCCOUPY_CNTR_V_SHIFT 0 +#define TPC0_CFG_IRQ_OCCOUPY_CNTR_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_FUNC_MBIST_CNTRL */ +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_SHIFT 0 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_MASK 0x1 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_SHIFT 1 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_MASK 0x2 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_SHIFT 2 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_MASK 0x4 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_FAILED_SHIFT 16 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_FAILED_MASK 0x3FF0000 + +/* TPC0_CFG_FUNC_MBIST_PAT */ +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_EVEN_SHIFT 0 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_EVEN_MASK 0x3 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_ODD_SHIFT 2 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_ODD_MASK 0xC +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_EVEN_SHIFT 4 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_EVEN_MASK 0x30 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_ODD_SHIFT 6 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_ODD_MASK 0xC0 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_EVEN_SHIFT 8 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_EVEN_MASK 0x300 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_ODD_SHIFT 10 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_ODD_MASK 0xC00 + +/* TPC0_CFG_FUNC_MBIST_MEM */ +#define TPC0_CFG_FUNC_MBIST_MEM_MAX_ADDR_SHIFT 0 +#define TPC0_CFG_FUNC_MBIST_MEM_MAX_ADDR_MASK 0x7FF +#define TPC0_CFG_FUNC_MBIST_MEM_PATTERN_EN_SHIFT 12 +#define TPC0_CFG_FUNC_MBIST_MEM_PATTERN_EN_MASK 0x7000 +#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_ADDR_SHIFT 16 +#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_ADDR_MASK 0x7FF0000 +#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_PATTERN_SHIFT 28 +#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_PATTERN_MASK 0x70000000 + +/* TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_0_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_1_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_2_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_3_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_4_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_5_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_6_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_7_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_8_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_8_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_8_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_8_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_8_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_8_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_8_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_9_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_9_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_9_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_9_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_9_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_9_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_9_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_10_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_10_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_10_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_10_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_10_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_10_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_10_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_11_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_11_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_11_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_11_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_11_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_11_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_11_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_12_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_12_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_12_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_12_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_12_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_12_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_12_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_13_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_13_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_13_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_13_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_13_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_13_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_13_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_14_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_14_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_14_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_14_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_14_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_14_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_14_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_15_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_15_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_15_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_15_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_15_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_15_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_15_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_SYNC_OBJECT_MESSAGE */ +#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT 0 +#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK 0xFFFF +#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_RSV_SHIFT 16 +#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_RSV_MASK 0x1FFF0000 +#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT 29 +#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK 0xE0000000 + +/* TPC0_CFG_QM_SYNC_OBJECT_ADDR */ +#define TPC0_CFG_QM_SYNC_OBJECT_ADDR_V_SHIFT 0 +#define TPC0_CFG_QM_SYNC_OBJECT_ADDR_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW */ +#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH */ +#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_BASE_DIM_0 */ +#define TPC0_CFG_QM_TID_BASE_DIM_0_V_SHIFT 0 +#define TPC0_CFG_QM_TID_BASE_DIM_0_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_SIZE_DIM_0 */ +#define TPC0_CFG_QM_TID_SIZE_DIM_0_V_SHIFT 0 +#define TPC0_CFG_QM_TID_SIZE_DIM_0_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_BASE_DIM_1 */ +#define TPC0_CFG_QM_TID_BASE_DIM_1_V_SHIFT 0 +#define TPC0_CFG_QM_TID_BASE_DIM_1_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_SIZE_DIM_1 */ +#define TPC0_CFG_QM_TID_SIZE_DIM_1_V_SHIFT 0 +#define TPC0_CFG_QM_TID_SIZE_DIM_1_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_BASE_DIM_2 */ +#define TPC0_CFG_QM_TID_BASE_DIM_2_V_SHIFT 0 +#define TPC0_CFG_QM_TID_BASE_DIM_2_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_SIZE_DIM_2 */ +#define TPC0_CFG_QM_TID_SIZE_DIM_2_V_SHIFT 0 +#define TPC0_CFG_QM_TID_SIZE_DIM_2_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_BASE_DIM_3 */ +#define TPC0_CFG_QM_TID_BASE_DIM_3_V_SHIFT 0 +#define TPC0_CFG_QM_TID_BASE_DIM_3_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_SIZE_DIM_3 */ +#define TPC0_CFG_QM_TID_SIZE_DIM_3_V_SHIFT 0 +#define TPC0_CFG_QM_TID_SIZE_DIM_3_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_BASE_DIM_4 */ +#define TPC0_CFG_QM_TID_BASE_DIM_4_V_SHIFT 0 +#define TPC0_CFG_QM_TID_BASE_DIM_4_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_SIZE_DIM_4 */ +#define TPC0_CFG_QM_TID_SIZE_DIM_4_V_SHIFT 0 +#define TPC0_CFG_QM_TID_SIZE_DIM_4_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_KERNEL_CONFIG */ +#define TPC0_CFG_QM_KERNEL_CONFIG_SMALL_VLM_SHIFT 0 +#define TPC0_CFG_QM_KERNEL_CONFIG_SMALL_VLM_MASK 0x1 +#define TPC0_CFG_QM_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT 1 +#define TPC0_CFG_QM_KERNEL_CONFIG_ASO_EVICT_L0_MASK 0x2 +#define TPC0_CFG_QM_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT 2 +#define TPC0_CFG_QM_KERNEL_CONFIG_NUM_VALID_SRFS_MASK 0xFC +#define TPC0_CFG_QM_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_SHIFT 8 +#define TPC0_CFG_QM_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_MASK 0xFF00 +#define TPC0_CFG_QM_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_SHIFT 16 +#define TPC0_CFG_QM_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_MASK 0xFF0000 + +/* TPC0_CFG_QM_KERNEL_ID */ +#define TPC0_CFG_QM_KERNEL_ID_V_SHIFT 0 +#define TPC0_CFG_QM_KERNEL_ID_V_MASK 0xFFFF + +/* TPC0_CFG_QM_SRF */ +#define TPC0_CFG_QM_SRF_V_SHIFT 0 +#define TPC0_CFG_QM_SRF_V_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_TPC0_CFG_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_cfg_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_cfg_regs.h new file mode 100644 index 000000000000..b82a906265a8 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_cfg_regs.h @@ -0,0 +1,1226 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_CFG_REGS_H_ +#define ASIC_REG_TPC0_CFG_REGS_H_ + +/* + ***************************************** + * TPC0_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE06400 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE06404 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE06408 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE0640C + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE06410 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE06414 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE06418 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE0641C + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE06420 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE06424 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE06428 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE0642C + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE06430 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE06434 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE06438 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE0643C + +#define mmTPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE06440 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE06444 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE06448 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE0644C + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE06450 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE06454 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE06458 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE0645C + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE06460 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE06464 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE06468 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE0646C + +#define mmTPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE06470 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE06474 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE06478 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE0647C + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE06480 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE06484 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE06488 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE0648C + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE06490 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE06494 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE06498 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE0649C + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE064A0 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE064A4 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE064A8 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE064AC + +#define mmTPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE064B0 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE064B4 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE064B8 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE064BC + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE064C0 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE064C4 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE064C8 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE064CC + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE064D0 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE064D4 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE064D8 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE064DC + +#define mmTPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE064E0 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE064E4 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE064E8 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE064EC + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE064F0 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE064F4 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE064F8 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE064FC + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE06500 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE06504 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE06508 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE0650C + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE06510 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE06514 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE06518 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE0651C + +#define mmTPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE06520 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE06524 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE06528 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE0652C + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE06530 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE06534 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE06538 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE0653C + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE06540 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE06544 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE06548 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE0654C + +#define mmTPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE06550 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE06554 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE06558 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE0655C + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE06560 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE06564 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE06568 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE0656C + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE06570 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE06574 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE06578 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE0657C + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE06580 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE06584 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE06588 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE0658C + +#define mmTPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE06590 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE06594 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE06598 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE0659C + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE065A0 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE065A4 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE065A8 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE065AC + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE065B0 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE065B4 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE065B8 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE065BC + +#define mmTPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xE065C0 + +#define mmTPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xE065C4 + +#define mmTPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xE065C8 + +#define mmTPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xE065CC + +#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xE065D0 + +#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xE065D4 + +#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xE065D8 + +#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xE065DC + +#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xE065E0 + +#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xE065E4 + +#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xE065E8 + +#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xE065EC + +#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xE065F0 + +#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xE065F4 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xE065F8 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xE065FC + +#define mmTPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xE06600 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xE06604 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xE06608 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xE0660C + +#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xE06610 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xE06614 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xE06618 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xE0661C + +#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xE06620 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xE06624 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xE06628 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xE0662C + +#define mmTPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xE06630 + +#define mmTPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xE06634 + +#define mmTPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xE06638 + +#define mmTPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xE0663C + +#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xE06640 + +#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xE06644 + +#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xE06648 + +#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xE0664C + +#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xE06650 + +#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xE06654 + +#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xE06658 + +#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xE0665C + +#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xE06660 + +#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xE06664 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xE06668 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xE0666C + +#define mmTPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xE06670 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xE06674 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xE06678 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xE0667C + +#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xE06680 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xE06684 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xE06688 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xE0668C + +#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xE06690 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xE06694 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xE06698 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xE0669C + +#define mmTPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xE066A0 + +#define mmTPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xE066A4 + +#define mmTPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xE066A8 + +#define mmTPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xE066AC + +#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xE066B0 + +#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xE066B4 + +#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xE066B8 + +#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xE066BC + +#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xE066C0 + +#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xE066C4 + +#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xE066C8 + +#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xE066CC + +#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xE066D0 + +#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xE066D4 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xE066D8 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xE066DC + +#define mmTPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xE066E0 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xE066E4 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xE066E8 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xE066EC + +#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xE066F0 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xE066F4 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xE066F8 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xE066FC + +#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xE06700 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xE06704 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xE06708 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xE0670C + +#define mmTPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xE06710 + +#define mmTPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xE06714 + +#define mmTPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xE06718 + +#define mmTPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xE0671C + +#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xE06720 + +#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xE06724 + +#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xE06728 + +#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xE0672C + +#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xE06730 + +#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xE06734 + +#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xE06738 + +#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xE0673C + +#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xE06740 + +#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xE06744 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xE06748 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xE0674C + +#define mmTPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xE06750 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xE06754 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xE06758 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xE0675C + +#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xE06760 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xE06764 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xE06768 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xE0676C + +#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xE06770 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xE06774 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xE06778 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xE0677C + +#define mmTPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE06780 + +#define mmTPC0_CFG_KERNEL_SYNC_OBJECT_ADDR 0xE06784 + +#define mmTPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE06788 + +#define mmTPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE0678C + +#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_0 0xE06790 + +#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_0 0xE06794 + +#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_1 0xE06798 + +#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_1 0xE0679C + +#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_2 0xE067A0 + +#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_2 0xE067A4 + +#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_3 0xE067A8 + +#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_3 0xE067AC + +#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_4 0xE067B0 + +#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_4 0xE067B4 + +#define mmTPC0_CFG_KERNEL_KERNEL_CONFIG 0xE067B8 + +#define mmTPC0_CFG_KERNEL_KERNEL_ID 0xE067BC + +#define mmTPC0_CFG_KERNEL_SRF_0 0xE067C0 + +#define mmTPC0_CFG_KERNEL_SRF_1 0xE067C4 + +#define mmTPC0_CFG_KERNEL_SRF_2 0xE067C8 + +#define mmTPC0_CFG_KERNEL_SRF_3 0xE067CC + +#define mmTPC0_CFG_KERNEL_SRF_4 0xE067D0 + +#define mmTPC0_CFG_KERNEL_SRF_5 0xE067D4 + +#define mmTPC0_CFG_KERNEL_SRF_6 0xE067D8 + +#define mmTPC0_CFG_KERNEL_SRF_7 0xE067DC + +#define mmTPC0_CFG_KERNEL_SRF_8 0xE067E0 + +#define mmTPC0_CFG_KERNEL_SRF_9 0xE067E4 + +#define mmTPC0_CFG_KERNEL_SRF_10 0xE067E8 + +#define mmTPC0_CFG_KERNEL_SRF_11 0xE067EC + +#define mmTPC0_CFG_KERNEL_SRF_12 0xE067F0 + +#define mmTPC0_CFG_KERNEL_SRF_13 0xE067F4 + +#define mmTPC0_CFG_KERNEL_SRF_14 0xE067F8 + +#define mmTPC0_CFG_KERNEL_SRF_15 0xE067FC + +#define mmTPC0_CFG_KERNEL_SRF_16 0xE06800 + +#define mmTPC0_CFG_KERNEL_SRF_17 0xE06804 + +#define mmTPC0_CFG_KERNEL_SRF_18 0xE06808 + +#define mmTPC0_CFG_KERNEL_SRF_19 0xE0680C + +#define mmTPC0_CFG_KERNEL_SRF_20 0xE06810 + +#define mmTPC0_CFG_KERNEL_SRF_21 0xE06814 + +#define mmTPC0_CFG_KERNEL_SRF_22 0xE06818 + +#define mmTPC0_CFG_KERNEL_SRF_23 0xE0681C + +#define mmTPC0_CFG_KERNEL_SRF_24 0xE06820 + +#define mmTPC0_CFG_KERNEL_SRF_25 0xE06824 + +#define mmTPC0_CFG_KERNEL_SRF_26 0xE06828 + +#define mmTPC0_CFG_KERNEL_SRF_27 0xE0682C + +#define mmTPC0_CFG_KERNEL_SRF_28 0xE06830 + +#define mmTPC0_CFG_KERNEL_SRF_29 0xE06834 + +#define mmTPC0_CFG_KERNEL_SRF_30 0xE06838 + +#define mmTPC0_CFG_KERNEL_SRF_31 0xE0683C + +#define mmTPC0_CFG_ROUND_CSR 0xE068FC + +#define mmTPC0_CFG_PROT 0xE06900 + +#define mmTPC0_CFG_SEMAPHORE 0xE06908 + +#define mmTPC0_CFG_VFLAGS 0xE0690C + +#define mmTPC0_CFG_SFLAGS 0xE06910 + +#define mmTPC0_CFG_LFSR_POLYNOM 0xE06918 + +#define mmTPC0_CFG_STATUS 0xE0691C + +#define mmTPC0_CFG_CFG_BASE_ADDRESS_HIGH 0xE06920 + +#define mmTPC0_CFG_CFG_SUBTRACT_VALUE 0xE06924 + +#define mmTPC0_CFG_SM_BASE_ADDRESS_HIGH 0xE0692C + +#define mmTPC0_CFG_TPC_CMD 0xE06930 + +#define mmTPC0_CFG_TPC_EXECUTE 0xE06938 + +#define mmTPC0_CFG_TPC_STALL 0xE0693C + +#define mmTPC0_CFG_ICACHE_BASE_ADDERESS_LOW 0xE06940 + +#define mmTPC0_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE06944 + +#define mmTPC0_CFG_RD_RATE_LIMIT 0xE06948 + +#define mmTPC0_CFG_WR_RATE_LIMIT 0xE06950 + +#define mmTPC0_CFG_MSS_CONFIG 0xE06954 + +#define mmTPC0_CFG_TPC_INTR_CAUSE 0xE06958 + +#define mmTPC0_CFG_TPC_INTR_MASK 0xE0695C + +#define mmTPC0_CFG_WQ_CREDITS 0xE06960 + +#define mmTPC0_CFG_ARUSER_LO 0xE06964 + +#define mmTPC0_CFG_ARUSER_HI 0xE06968 + +#define mmTPC0_CFG_AWUSER_LO 0xE0696C + +#define mmTPC0_CFG_AWUSER_HI 0xE06970 + +#define mmTPC0_CFG_OPCODE_EXEC 0xE06974 + +#define mmTPC0_CFG_LUT_FUNC32_BASE_ADDR_LO 0xE06978 + +#define mmTPC0_CFG_LUT_FUNC32_BASE_ADDR_HI 0xE0697C + +#define mmTPC0_CFG_LUT_FUNC64_BASE_ADDR_LO 0xE06980 + +#define mmTPC0_CFG_LUT_FUNC64_BASE_ADDR_HI 0xE06984 + +#define mmTPC0_CFG_LUT_FUNC128_BASE_ADDR_LO 0xE06988 + +#define mmTPC0_CFG_LUT_FUNC128_BASE_ADDR_HI 0xE0698C + +#define mmTPC0_CFG_LUT_FUNC256_BASE_ADDR_LO 0xE06990 + +#define mmTPC0_CFG_LUT_FUNC256_BASE_ADDR_HI 0xE06994 + +#define mmTPC0_CFG_TSB_CFG_MAX_SIZE 0xE06998 + +#define mmTPC0_CFG_TSB_CFG 0xE0699C + +#define mmTPC0_CFG_DBGMEM_ADD 0xE069A0 + +#define mmTPC0_CFG_DBGMEM_DATA_WR 0xE069A4 + +#define mmTPC0_CFG_DBGMEM_DATA_RD 0xE069A8 + +#define mmTPC0_CFG_DBGMEM_CTRL 0xE069AC + +#define mmTPC0_CFG_DBGMEM_RC 0xE069B0 + +#define mmTPC0_CFG_TSB_INFLIGHT_CNTR 0xE069B4 + +#define mmTPC0_CFG_WQ_INFLIGHT_CNTR 0xE069B8 + +#define mmTPC0_CFG_WQ_LBW_TOTAL_CNTR 0xE069BC + +#define mmTPC0_CFG_WQ_HBW_TOTAL_CNTR 0xE069C0 + +#define mmTPC0_CFG_IRQ_OCCOUPY_CNTR 0xE069C4 + +#define mmTPC0_CFG_FUNC_MBIST_CNTRL 0xE069D0 + +#define mmTPC0_CFG_FUNC_MBIST_PAT 0xE069D4 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_0 0xE069D8 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_1 0xE069DC + +#define mmTPC0_CFG_FUNC_MBIST_MEM_2 0xE069E0 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_3 0xE069E4 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_4 0xE069E8 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_5 0xE069EC + +#define mmTPC0_CFG_FUNC_MBIST_MEM_6 0xE069F0 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_7 0xE069F4 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_8 0xE069F8 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_9 0xE069FC + +#define mmTPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE06A00 + +#define mmTPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE06A04 + +#define mmTPC0_CFG_QM_TENSOR_0_PADDING_VALUE 0xE06A08 + +#define mmTPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE06A0C + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE06A10 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE06A14 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE06A18 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE06A1C + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE06A20 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE06A24 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE06A28 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE06A2C + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE06A30 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE06A34 + +#define mmTPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE06A38 + +#define mmTPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE06A3C + +#define mmTPC0_CFG_QM_TENSOR_1_PADDING_VALUE 0xE06A40 + +#define mmTPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE06A44 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE06A48 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE06A4C + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE06A50 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE06A54 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE06A58 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE06A5C + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE06A60 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE06A64 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE06A68 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE06A6C + +#define mmTPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE06A70 + +#define mmTPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE06A74 + +#define mmTPC0_CFG_QM_TENSOR_2_PADDING_VALUE 0xE06A78 + +#define mmTPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE06A7C + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE06A80 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE06A84 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE06A88 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE06A8C + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE06A90 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE06A94 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE06A98 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE06A9C + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE06AA0 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE06AA4 + +#define mmTPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE06AA8 + +#define mmTPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE06AAC + +#define mmTPC0_CFG_QM_TENSOR_3_PADDING_VALUE 0xE06AB0 + +#define mmTPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE06AB4 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE06AB8 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE06ABC + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE06AC0 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE06AC4 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE06AC8 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE06ACC + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE06AD0 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE06AD4 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE06AD8 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE06ADC + +#define mmTPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE06AE0 + +#define mmTPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE06AE4 + +#define mmTPC0_CFG_QM_TENSOR_4_PADDING_VALUE 0xE06AE8 + +#define mmTPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE06AEC + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE06AF0 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE06AF4 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE06AF8 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE06AFC + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE06B00 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE06B04 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE06B08 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE06B0C + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE06B10 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE06B14 + +#define mmTPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE06B18 + +#define mmTPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE06B1C + +#define mmTPC0_CFG_QM_TENSOR_5_PADDING_VALUE 0xE06B20 + +#define mmTPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE06B24 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE06B28 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE06B2C + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE06B30 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE06B34 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE06B38 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE06B3C + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE06B40 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE06B44 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE06B48 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE06B4C + +#define mmTPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE06B50 + +#define mmTPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE06B54 + +#define mmTPC0_CFG_QM_TENSOR_6_PADDING_VALUE 0xE06B58 + +#define mmTPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE06B5C + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE06B60 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE06B64 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE06B68 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE06B6C + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE06B70 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE06B74 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE06B78 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE06B7C + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE06B80 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE06B84 + +#define mmTPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE06B88 + +#define mmTPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE06B8C + +#define mmTPC0_CFG_QM_TENSOR_7_PADDING_VALUE 0xE06B90 + +#define mmTPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE06B94 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE06B98 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE06B9C + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE06BA0 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE06BA4 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE06BA8 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE06BAC + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE06BB0 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE06BB4 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE06BB8 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE06BBC + +#define mmTPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xE06BC0 + +#define mmTPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xE06BC4 + +#define mmTPC0_CFG_QM_TENSOR_8_PADDING_VALUE 0xE06BC8 + +#define mmTPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xE06BCC + +#define mmTPC0_CFG_QM_TENSOR_8_DIM_0_SIZE 0xE06BD0 + +#define mmTPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xE06BD4 + +#define mmTPC0_CFG_QM_TENSOR_8_DIM_1_SIZE 0xE06BD8 + +#define mmTPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xE06BDC + +#define mmTPC0_CFG_QM_TENSOR_8_DIM_2_SIZE 0xE06BE0 + +#define mmTPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xE06BE4 + +#define mmTPC0_CFG_QM_TENSOR_8_DIM_3_SIZE 0xE06BE8 + +#define mmTPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xE06BEC + +#define mmTPC0_CFG_QM_TENSOR_8_DIM_4_SIZE 0xE06BF0 + +#define mmTPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xE06BF4 + +#define mmTPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xE06BF8 + +#define mmTPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xE06BFC + +#define mmTPC0_CFG_QM_TENSOR_9_PADDING_VALUE 0xE06C00 + +#define mmTPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xE06C04 + +#define mmTPC0_CFG_QM_TENSOR_9_DIM_0_SIZE 0xE06C08 + +#define mmTPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xE06C0C + +#define mmTPC0_CFG_QM_TENSOR_9_DIM_1_SIZE 0xE06C10 + +#define mmTPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xE06C14 + +#define mmTPC0_CFG_QM_TENSOR_9_DIM_2_SIZE 0xE06C18 + +#define mmTPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xE06C1C + +#define mmTPC0_CFG_QM_TENSOR_9_DIM_3_SIZE 0xE06C20 + +#define mmTPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xE06C24 + +#define mmTPC0_CFG_QM_TENSOR_9_DIM_4_SIZE 0xE06C28 + +#define mmTPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xE06C2C + +#define mmTPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xE06C30 + +#define mmTPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xE06C34 + +#define mmTPC0_CFG_QM_TENSOR_10_PADDING_VALUE 0xE06C38 + +#define mmTPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xE06C3C + +#define mmTPC0_CFG_QM_TENSOR_10_DIM_0_SIZE 0xE06C40 + +#define mmTPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xE06C44 + +#define mmTPC0_CFG_QM_TENSOR_10_DIM_1_SIZE 0xE06C48 + +#define mmTPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xE06C4C + +#define mmTPC0_CFG_QM_TENSOR_10_DIM_2_SIZE 0xE06C50 + +#define mmTPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xE06C54 + +#define mmTPC0_CFG_QM_TENSOR_10_DIM_3_SIZE 0xE06C58 + +#define mmTPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xE06C5C + +#define mmTPC0_CFG_QM_TENSOR_10_DIM_4_SIZE 0xE06C60 + +#define mmTPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xE06C64 + +#define mmTPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xE06C68 + +#define mmTPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xE06C6C + +#define mmTPC0_CFG_QM_TENSOR_11_PADDING_VALUE 0xE06C70 + +#define mmTPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xE06C74 + +#define mmTPC0_CFG_QM_TENSOR_11_DIM_0_SIZE 0xE06C78 + +#define mmTPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xE06C7C + +#define mmTPC0_CFG_QM_TENSOR_11_DIM_1_SIZE 0xE06C80 + +#define mmTPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xE06C84 + +#define mmTPC0_CFG_QM_TENSOR_11_DIM_2_SIZE 0xE06C88 + +#define mmTPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xE06C8C + +#define mmTPC0_CFG_QM_TENSOR_11_DIM_3_SIZE 0xE06C90 + +#define mmTPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xE06C94 + +#define mmTPC0_CFG_QM_TENSOR_11_DIM_4_SIZE 0xE06C98 + +#define mmTPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xE06C9C + +#define mmTPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xE06CA0 + +#define mmTPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xE06CA4 + +#define mmTPC0_CFG_QM_TENSOR_12_PADDING_VALUE 0xE06CA8 + +#define mmTPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xE06CAC + +#define mmTPC0_CFG_QM_TENSOR_12_DIM_0_SIZE 0xE06CB0 + +#define mmTPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xE06CB4 + +#define mmTPC0_CFG_QM_TENSOR_12_DIM_1_SIZE 0xE06CB8 + +#define mmTPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xE06CBC + +#define mmTPC0_CFG_QM_TENSOR_12_DIM_2_SIZE 0xE06CC0 + +#define mmTPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xE06CC4 + +#define mmTPC0_CFG_QM_TENSOR_12_DIM_3_SIZE 0xE06CC8 + +#define mmTPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xE06CCC + +#define mmTPC0_CFG_QM_TENSOR_12_DIM_4_SIZE 0xE06CD0 + +#define mmTPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xE06CD4 + +#define mmTPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xE06CD8 + +#define mmTPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xE06CDC + +#define mmTPC0_CFG_QM_TENSOR_13_PADDING_VALUE 0xE06CE0 + +#define mmTPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xE06CE4 + +#define mmTPC0_CFG_QM_TENSOR_13_DIM_0_SIZE 0xE06CE8 + +#define mmTPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xE06CEC + +#define mmTPC0_CFG_QM_TENSOR_13_DIM_1_SIZE 0xE06CF0 + +#define mmTPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xE06CF4 + +#define mmTPC0_CFG_QM_TENSOR_13_DIM_2_SIZE 0xE06CF8 + +#define mmTPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xE06CFC + +#define mmTPC0_CFG_QM_TENSOR_13_DIM_3_SIZE 0xE06D00 + +#define mmTPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xE06D04 + +#define mmTPC0_CFG_QM_TENSOR_13_DIM_4_SIZE 0xE06D08 + +#define mmTPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xE06D0C + +#define mmTPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xE06D10 + +#define mmTPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xE06D14 + +#define mmTPC0_CFG_QM_TENSOR_14_PADDING_VALUE 0xE06D18 + +#define mmTPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xE06D1C + +#define mmTPC0_CFG_QM_TENSOR_14_DIM_0_SIZE 0xE06D20 + +#define mmTPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xE06D24 + +#define mmTPC0_CFG_QM_TENSOR_14_DIM_1_SIZE 0xE06D28 + +#define mmTPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xE06D2C + +#define mmTPC0_CFG_QM_TENSOR_14_DIM_2_SIZE 0xE06D30 + +#define mmTPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xE06D34 + +#define mmTPC0_CFG_QM_TENSOR_14_DIM_3_SIZE 0xE06D38 + +#define mmTPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xE06D3C + +#define mmTPC0_CFG_QM_TENSOR_14_DIM_4_SIZE 0xE06D40 + +#define mmTPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xE06D44 + +#define mmTPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xE06D48 + +#define mmTPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xE06D4C + +#define mmTPC0_CFG_QM_TENSOR_15_PADDING_VALUE 0xE06D50 + +#define mmTPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xE06D54 + +#define mmTPC0_CFG_QM_TENSOR_15_DIM_0_SIZE 0xE06D58 + +#define mmTPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xE06D5C + +#define mmTPC0_CFG_QM_TENSOR_15_DIM_1_SIZE 0xE06D60 + +#define mmTPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xE06D64 + +#define mmTPC0_CFG_QM_TENSOR_15_DIM_2_SIZE 0xE06D68 + +#define mmTPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xE06D6C + +#define mmTPC0_CFG_QM_TENSOR_15_DIM_3_SIZE 0xE06D70 + +#define mmTPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xE06D74 + +#define mmTPC0_CFG_QM_TENSOR_15_DIM_4_SIZE 0xE06D78 + +#define mmTPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xE06D7C + +#define mmTPC0_CFG_QM_SYNC_OBJECT_MESSAGE 0xE06D80 + +#define mmTPC0_CFG_QM_SYNC_OBJECT_ADDR 0xE06D84 + +#define mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE06D88 + +#define mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE06D8C + +#define mmTPC0_CFG_QM_TID_BASE_DIM_0 0xE06D90 + +#define mmTPC0_CFG_QM_TID_SIZE_DIM_0 0xE06D94 + +#define mmTPC0_CFG_QM_TID_BASE_DIM_1 0xE06D98 + +#define mmTPC0_CFG_QM_TID_SIZE_DIM_1 0xE06D9C + +#define mmTPC0_CFG_QM_TID_BASE_DIM_2 0xE06DA0 + +#define mmTPC0_CFG_QM_TID_SIZE_DIM_2 0xE06DA4 + +#define mmTPC0_CFG_QM_TID_BASE_DIM_3 0xE06DA8 + +#define mmTPC0_CFG_QM_TID_SIZE_DIM_3 0xE06DAC + +#define mmTPC0_CFG_QM_TID_BASE_DIM_4 0xE06DB0 + +#define mmTPC0_CFG_QM_TID_SIZE_DIM_4 0xE06DB4 + +#define mmTPC0_CFG_QM_KERNEL_CONFIG 0xE06DB8 + +#define mmTPC0_CFG_QM_KERNEL_ID 0xE06DBC + +#define mmTPC0_CFG_QM_SRF_0 0xE06DC0 + +#define mmTPC0_CFG_QM_SRF_1 0xE06DC4 + +#define mmTPC0_CFG_QM_SRF_2 0xE06DC8 + +#define mmTPC0_CFG_QM_SRF_3 0xE06DCC + +#define mmTPC0_CFG_QM_SRF_4 0xE06DD0 + +#define mmTPC0_CFG_QM_SRF_5 0xE06DD4 + +#define mmTPC0_CFG_QM_SRF_6 0xE06DD8 + +#define mmTPC0_CFG_QM_SRF_7 0xE06DDC + +#define mmTPC0_CFG_QM_SRF_8 0xE06DE0 + +#define mmTPC0_CFG_QM_SRF_9 0xE06DE4 + +#define mmTPC0_CFG_QM_SRF_10 0xE06DE8 + +#define mmTPC0_CFG_QM_SRF_11 0xE06DEC + +#define mmTPC0_CFG_QM_SRF_12 0xE06DF0 + +#define mmTPC0_CFG_QM_SRF_13 0xE06DF4 + +#define mmTPC0_CFG_QM_SRF_14 0xE06DF8 + +#define mmTPC0_CFG_QM_SRF_15 0xE06DFC + +#define mmTPC0_CFG_QM_SRF_16 0xE06E00 + +#define mmTPC0_CFG_QM_SRF_17 0xE06E04 + +#define mmTPC0_CFG_QM_SRF_18 0xE06E08 + +#define mmTPC0_CFG_QM_SRF_19 0xE06E0C + +#define mmTPC0_CFG_QM_SRF_20 0xE06E10 + +#define mmTPC0_CFG_QM_SRF_21 0xE06E14 + +#define mmTPC0_CFG_QM_SRF_22 0xE06E18 + +#define mmTPC0_CFG_QM_SRF_23 0xE06E1C + +#define mmTPC0_CFG_QM_SRF_24 0xE06E20 + +#define mmTPC0_CFG_QM_SRF_25 0xE06E24 + +#define mmTPC0_CFG_QM_SRF_26 0xE06E28 + +#define mmTPC0_CFG_QM_SRF_27 0xE06E2C + +#define mmTPC0_CFG_QM_SRF_28 0xE06E30 + +#define mmTPC0_CFG_QM_SRF_29 0xE06E34 + +#define mmTPC0_CFG_QM_SRF_30 0xE06E38 + +#define mmTPC0_CFG_QM_SRF_31 0xE06E3C + +#endif /* ASIC_REG_TPC0_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_qm_masks.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_qm_masks.h new file mode 100644 index 000000000000..8e71532c6f36 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_qm_masks.h @@ -0,0 +1,800 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_QM_MASKS_H_ +#define ASIC_REG_TPC0_QM_MASKS_H_ + +/* + ***************************************** + * TPC0_QM (Prototype: QMAN) + ***************************************** + */ + +/* TPC0_QM_GLBL_CFG0 */ +#define TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT 0 +#define TPC0_QM_GLBL_CFG0_PQF_EN_MASK 0xF +#define TPC0_QM_GLBL_CFG0_CQF_EN_SHIFT 4 +#define TPC0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0 +#define TPC0_QM_GLBL_CFG0_CP_EN_SHIFT 9 +#define TPC0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00 + +/* TPC0_QM_GLBL_CFG1 */ +#define TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0 +#define TPC0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF +#define TPC0_QM_GLBL_CFG1_CQF_STOP_SHIFT 4 +#define TPC0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0 +#define TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT 9 +#define TPC0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00 +#define TPC0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 16 +#define TPC0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000 +#define TPC0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 20 +#define TPC0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000 +#define TPC0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 25 +#define TPC0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x3E000000 + +/* TPC0_QM_GLBL_PROT */ +#define TPC0_QM_GLBL_PROT_PQF_SHIFT 0 +#define TPC0_QM_GLBL_PROT_PQF_MASK 0xF +#define TPC0_QM_GLBL_PROT_CQF_SHIFT 4 +#define TPC0_QM_GLBL_PROT_CQF_MASK 0x1F0 +#define TPC0_QM_GLBL_PROT_CP_SHIFT 9 +#define TPC0_QM_GLBL_PROT_CP_MASK 0x3E00 +#define TPC0_QM_GLBL_PROT_ERR_SHIFT 14 +#define TPC0_QM_GLBL_PROT_ERR_MASK 0x4000 +#define TPC0_QM_GLBL_PROT_ARB_SHIFT 15 +#define TPC0_QM_GLBL_PROT_ARB_MASK 0x8000 + +/* TPC0_QM_GLBL_ERR_CFG */ +#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 0 +#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0xF +#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 +#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1F0 +#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 9 +#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x3E00 +#define TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 16 +#define TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0xF0000 +#define TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 20 +#define TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x1F00000 +#define TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 25 +#define TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x3E000000 +#define TPC0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT 31 +#define TPC0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK 0x80000000 + +/* TPC0_QM_GLBL_SECURE_PROPS */ +#define TPC0_QM_GLBL_SECURE_PROPS_0_ASID_SHIFT 0 +#define TPC0_QM_GLBL_SECURE_PROPS_0_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_SECURE_PROPS_1_ASID_SHIFT 0 +#define TPC0_QM_GLBL_SECURE_PROPS_1_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_SECURE_PROPS_2_ASID_SHIFT 0 +#define TPC0_QM_GLBL_SECURE_PROPS_2_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_SECURE_PROPS_3_ASID_SHIFT 0 +#define TPC0_QM_GLBL_SECURE_PROPS_3_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_SECURE_PROPS_4_ASID_SHIFT 0 +#define TPC0_QM_GLBL_SECURE_PROPS_4_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_SECURE_PROPS_0_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_SECURE_PROPS_0_MMBP_MASK 0x400 +#define TPC0_QM_GLBL_SECURE_PROPS_1_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_SECURE_PROPS_1_MMBP_MASK 0x400 +#define TPC0_QM_GLBL_SECURE_PROPS_2_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_SECURE_PROPS_2_MMBP_MASK 0x400 +#define TPC0_QM_GLBL_SECURE_PROPS_3_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_SECURE_PROPS_3_MMBP_MASK 0x400 +#define TPC0_QM_GLBL_SECURE_PROPS_4_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_SECURE_PROPS_4_MMBP_MASK 0x400 + +/* TPC0_QM_GLBL_NON_SECURE_PROPS */ +#define TPC0_QM_GLBL_NON_SECURE_PROPS_0_ASID_SHIFT 0 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_0_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_NON_SECURE_PROPS_1_ASID_SHIFT 0 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_1_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_NON_SECURE_PROPS_2_ASID_SHIFT 0 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_2_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_NON_SECURE_PROPS_3_ASID_SHIFT 0 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_3_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_NON_SECURE_PROPS_4_ASID_SHIFT 0 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_4_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_MASK 0x400 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_MASK 0x400 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_MASK 0x400 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_MASK 0x400 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_MASK 0x400 + +/* TPC0_QM_GLBL_STS0 */ +#define TPC0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0 +#define TPC0_QM_GLBL_STS0_PQF_IDLE_MASK 0xF +#define TPC0_QM_GLBL_STS0_CQF_IDLE_SHIFT 4 +#define TPC0_QM_GLBL_STS0_CQF_IDLE_MASK 0x1F0 +#define TPC0_QM_GLBL_STS0_CP_IDLE_SHIFT 9 +#define TPC0_QM_GLBL_STS0_CP_IDLE_MASK 0x3E00 +#define TPC0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 16 +#define TPC0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0xF0000 +#define TPC0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 20 +#define TPC0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x1F00000 +#define TPC0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 25 +#define TPC0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x3E000000 +#define TPC0_QM_GLBL_STS0_ARB_IS_STOP_SHIFT 31 +#define TPC0_QM_GLBL_STS0_ARB_IS_STOP_MASK 0x80000000 + +/* TPC0_QM_GLBL_STS1 */ +#define TPC0_QM_GLBL_STS1_PQF_RD_ERR_SHIFT 0 +#define TPC0_QM_GLBL_STS1_PQF_RD_ERR_MASK 0x1 +#define TPC0_QM_GLBL_STS1_CQF_RD_ERR_SHIFT 1 +#define TPC0_QM_GLBL_STS1_CQF_RD_ERR_MASK 0x2 +#define TPC0_QM_GLBL_STS1_CP_RD_ERR_SHIFT 2 +#define TPC0_QM_GLBL_STS1_CP_RD_ERR_MASK 0x4 +#define TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3 +#define TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8 +#define TPC0_QM_GLBL_STS1_CP_STOP_OP_SHIFT 4 +#define TPC0_QM_GLBL_STS1_CP_STOP_OP_MASK 0x10 +#define TPC0_QM_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5 +#define TPC0_QM_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20 +#define TPC0_QM_GLBL_STS1_CP_WREG_ERR_SHIFT 6 +#define TPC0_QM_GLBL_STS1_CP_WREG_ERR_MASK 0x40 +#define TPC0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_SHIFT 8 +#define TPC0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_MASK 0x100 +#define TPC0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_SHIFT 9 +#define TPC0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_MASK 0x200 +#define TPC0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_SHIFT 10 +#define TPC0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_MASK 0x400 +#define TPC0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_SHIFT 11 +#define TPC0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_MASK 0x800 +#define TPC0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_SHIFT 12 +#define TPC0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define TPC0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_SHIFT 13 +#define TPC0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define TPC0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_SHIFT 14 +#define TPC0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define TPC0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_SHIFT 15 +#define TPC0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* TPC0_QM_GLBL_STS1_4 */ +#define TPC0_QM_GLBL_STS1_4_CQF_RD_ERR_SHIFT 1 +#define TPC0_QM_GLBL_STS1_4_CQF_RD_ERR_MASK 0x2 +#define TPC0_QM_GLBL_STS1_4_CP_RD_ERR_SHIFT 2 +#define TPC0_QM_GLBL_STS1_4_CP_RD_ERR_MASK 0x4 +#define TPC0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_SHIFT 3 +#define TPC0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_MASK 0x8 +#define TPC0_QM_GLBL_STS1_4_CP_STOP_OP_SHIFT 4 +#define TPC0_QM_GLBL_STS1_4_CP_STOP_OP_MASK 0x10 +#define TPC0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_SHIFT 5 +#define TPC0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_MASK 0x20 +#define TPC0_QM_GLBL_STS1_4_CP_WREG_ERR_SHIFT 6 +#define TPC0_QM_GLBL_STS1_4_CP_WREG_ERR_MASK 0x40 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_SHIFT 8 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_MASK 0x100 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_SHIFT 9 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_MASK 0x200 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_SHIFT 10 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_MASK 0x400 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_SHIFT 11 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_MASK 0x800 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_SHIFT 12 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_SHIFT 13 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_SHIFT 14 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_SHIFT 15 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* TPC0_QM_GLBL_MSG_EN */ +#define TPC0_QM_GLBL_MSG_EN_PQF_RD_ERR_SHIFT 0 +#define TPC0_QM_GLBL_MSG_EN_PQF_RD_ERR_MASK 0x1 +#define TPC0_QM_GLBL_MSG_EN_CQF_RD_ERR_SHIFT 1 +#define TPC0_QM_GLBL_MSG_EN_CQF_RD_ERR_MASK 0x2 +#define TPC0_QM_GLBL_MSG_EN_CP_RD_ERR_SHIFT 2 +#define TPC0_QM_GLBL_MSG_EN_CP_RD_ERR_MASK 0x4 +#define TPC0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT 3 +#define TPC0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_MASK 0x8 +#define TPC0_QM_GLBL_MSG_EN_CP_STOP_OP_SHIFT 4 +#define TPC0_QM_GLBL_MSG_EN_CP_STOP_OP_MASK 0x10 +#define TPC0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_SHIFT 5 +#define TPC0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_MASK 0x20 +#define TPC0_QM_GLBL_MSG_EN_CP_WREG_ERR_SHIFT 6 +#define TPC0_QM_GLBL_MSG_EN_CP_WREG_ERR_MASK 0x40 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT 8 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT 9 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT 10 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_MASK 0x400 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT 11 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT 12 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT 13 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT 14 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT 15 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* TPC0_QM_GLBL_MSG_EN_4 */ +#define TPC0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_SHIFT 1 +#define TPC0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_MASK 0x2 +#define TPC0_QM_GLBL_MSG_EN_4_CP_RD_ERR_SHIFT 2 +#define TPC0_QM_GLBL_MSG_EN_4_CP_RD_ERR_MASK 0x4 +#define TPC0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT 3 +#define TPC0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK 0x8 +#define TPC0_QM_GLBL_MSG_EN_4_CP_STOP_OP_SHIFT 4 +#define TPC0_QM_GLBL_MSG_EN_4_CP_STOP_OP_MASK 0x10 +#define TPC0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_SHIFT 5 +#define TPC0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_MASK 0x20 +#define TPC0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_SHIFT 6 +#define TPC0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_MASK 0x40 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT 8 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT 9 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT 10 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK 0x400 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT 11 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT 12 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT 13 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT 14 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT 15 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* TPC0_QM_PQ_BASE_LO */ +#define TPC0_QM_PQ_BASE_LO_VAL_SHIFT 0 +#define TPC0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_BASE_HI */ +#define TPC0_QM_PQ_BASE_HI_VAL_SHIFT 0 +#define TPC0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_SIZE */ +#define TPC0_QM_PQ_SIZE_VAL_SHIFT 0 +#define TPC0_QM_PQ_SIZE_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_PI */ +#define TPC0_QM_PQ_PI_VAL_SHIFT 0 +#define TPC0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_CI */ +#define TPC0_QM_PQ_CI_VAL_SHIFT 0 +#define TPC0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_CFG0 */ +#define TPC0_QM_PQ_CFG0_RESERVED_SHIFT 0 +#define TPC0_QM_PQ_CFG0_RESERVED_MASK 0x1 + +/* TPC0_QM_PQ_CFG1 */ +#define TPC0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0 +#define TPC0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define TPC0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define TPC0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* TPC0_QM_PQ_ARUSER_31_11 */ +#define TPC0_QM_PQ_ARUSER_31_11_VAL_SHIFT 0 +#define TPC0_QM_PQ_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* TPC0_QM_PQ_STS0 */ +#define TPC0_QM_PQ_STS0_PQ_CREDIT_CNT_SHIFT 0 +#define TPC0_QM_PQ_STS0_PQ_CREDIT_CNT_MASK 0xFFFF +#define TPC0_QM_PQ_STS0_PQ_FREE_CNT_SHIFT 16 +#define TPC0_QM_PQ_STS0_PQ_FREE_CNT_MASK 0xFFFF0000 + +/* TPC0_QM_PQ_STS1 */ +#define TPC0_QM_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT 0 +#define TPC0_QM_PQ_STS1_PQ_INFLIGHT_CNT_MASK 0xFFFF +#define TPC0_QM_PQ_STS1_PQ_BUF_EMPTY_SHIFT 30 +#define TPC0_QM_PQ_STS1_PQ_BUF_EMPTY_MASK 0x40000000 +#define TPC0_QM_PQ_STS1_PQ_BUSY_SHIFT 31 +#define TPC0_QM_PQ_STS1_PQ_BUSY_MASK 0x80000000 + +/* TPC0_QM_CQ_CFG0 */ +#define TPC0_QM_CQ_CFG0_RESERVED_SHIFT 0 +#define TPC0_QM_CQ_CFG0_RESERVED_MASK 0x1 + +/* TPC0_QM_CQ_CFG1 */ +#define TPC0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0 +#define TPC0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define TPC0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define TPC0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_ARUSER_31_11 */ +#define TPC0_QM_CQ_ARUSER_31_11_VAL_SHIFT 0 +#define TPC0_QM_CQ_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* TPC0_QM_CQ_STS0 */ +#define TPC0_QM_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0 +#define TPC0_QM_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF +#define TPC0_QM_CQ_STS0_CQ_FREE_CNT_SHIFT 16 +#define TPC0_QM_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_STS1 */ +#define TPC0_QM_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0 +#define TPC0_QM_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF +#define TPC0_QM_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30 +#define TPC0_QM_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000 +#define TPC0_QM_CQ_STS1_CQ_BUSY_SHIFT 31 +#define TPC0_QM_CQ_STS1_CQ_BUSY_MASK 0x80000000 + +/* TPC0_QM_CQ_PTR_LO_0 */ +#define TPC0_QM_CQ_PTR_LO_0_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_LO_0_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_PTR_HI_0 */ +#define TPC0_QM_CQ_PTR_HI_0_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_HI_0_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_TSIZE_0 */ +#define TPC0_QM_CQ_TSIZE_0_VAL_SHIFT 0 +#define TPC0_QM_CQ_TSIZE_0_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_CTL_0 */ +#define TPC0_QM_CQ_CTL_0_RPT_SHIFT 0 +#define TPC0_QM_CQ_CTL_0_RPT_MASK 0xFFFF +#define TPC0_QM_CQ_CTL_0_CTL_SHIFT 16 +#define TPC0_QM_CQ_CTL_0_CTL_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_PTR_LO_1 */ +#define TPC0_QM_CQ_PTR_LO_1_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_LO_1_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_PTR_HI_1 */ +#define TPC0_QM_CQ_PTR_HI_1_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_HI_1_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_TSIZE_1 */ +#define TPC0_QM_CQ_TSIZE_1_VAL_SHIFT 0 +#define TPC0_QM_CQ_TSIZE_1_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_CTL_1 */ +#define TPC0_QM_CQ_CTL_1_RPT_SHIFT 0 +#define TPC0_QM_CQ_CTL_1_RPT_MASK 0xFFFF +#define TPC0_QM_CQ_CTL_1_CTL_SHIFT 16 +#define TPC0_QM_CQ_CTL_1_CTL_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_PTR_LO_2 */ +#define TPC0_QM_CQ_PTR_LO_2_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_LO_2_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_PTR_HI_2 */ +#define TPC0_QM_CQ_PTR_HI_2_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_HI_2_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_TSIZE_2 */ +#define TPC0_QM_CQ_TSIZE_2_VAL_SHIFT 0 +#define TPC0_QM_CQ_TSIZE_2_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_CTL_2 */ +#define TPC0_QM_CQ_CTL_2_RPT_SHIFT 0 +#define TPC0_QM_CQ_CTL_2_RPT_MASK 0xFFFF +#define TPC0_QM_CQ_CTL_2_CTL_SHIFT 16 +#define TPC0_QM_CQ_CTL_2_CTL_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_PTR_LO_3 */ +#define TPC0_QM_CQ_PTR_LO_3_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_LO_3_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_PTR_HI_3 */ +#define TPC0_QM_CQ_PTR_HI_3_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_HI_3_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_TSIZE_3 */ +#define TPC0_QM_CQ_TSIZE_3_VAL_SHIFT 0 +#define TPC0_QM_CQ_TSIZE_3_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_CTL_3 */ +#define TPC0_QM_CQ_CTL_3_RPT_SHIFT 0 +#define TPC0_QM_CQ_CTL_3_RPT_MASK 0xFFFF +#define TPC0_QM_CQ_CTL_3_CTL_SHIFT 16 +#define TPC0_QM_CQ_CTL_3_CTL_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_PTR_LO_4 */ +#define TPC0_QM_CQ_PTR_LO_4_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_LO_4_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_PTR_HI_4 */ +#define TPC0_QM_CQ_PTR_HI_4_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_HI_4_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_TSIZE_4 */ +#define TPC0_QM_CQ_TSIZE_4_VAL_SHIFT 0 +#define TPC0_QM_CQ_TSIZE_4_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_CTL_4 */ +#define TPC0_QM_CQ_CTL_4_RPT_SHIFT 0 +#define TPC0_QM_CQ_CTL_4_RPT_MASK 0xFFFF +#define TPC0_QM_CQ_CTL_4_CTL_SHIFT 16 +#define TPC0_QM_CQ_CTL_4_CTL_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_PTR_LO_STS */ +#define TPC0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_PTR_HI_STS */ +#define TPC0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_TSIZE_STS */ +#define TPC0_QM_CQ_TSIZE_STS_VAL_SHIFT 0 +#define TPC0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_CTL_STS */ +#define TPC0_QM_CQ_CTL_STS_RPT_SHIFT 0 +#define TPC0_QM_CQ_CTL_STS_RPT_MASK 0xFFFF +#define TPC0_QM_CQ_CTL_STS_CTL_SHIFT 16 +#define TPC0_QM_CQ_CTL_STS_CTL_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_IFIFO_CNT */ +#define TPC0_QM_CQ_IFIFO_CNT_VAL_SHIFT 0 +#define TPC0_QM_CQ_IFIFO_CNT_VAL_MASK 0x3 + +/* TPC0_QM_CP_MSG_BASE0_ADDR_LO */ +#define TPC0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE0_ADDR_HI */ +#define TPC0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE1_ADDR_LO */ +#define TPC0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE1_ADDR_HI */ +#define TPC0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE2_ADDR_LO */ +#define TPC0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE2_ADDR_HI */ +#define TPC0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE3_ADDR_LO */ +#define TPC0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE3_ADDR_HI */ +#define TPC0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_LDMA_TSIZE_OFFSET */ +#define TPC0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 +#define TPC0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */ +#define TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 +#define TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET */ +#define TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 +#define TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_FENCE0_RDATA */ +#define TPC0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF + +/* TPC0_QM_CP_FENCE1_RDATA */ +#define TPC0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF + +/* TPC0_QM_CP_FENCE2_RDATA */ +#define TPC0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF + +/* TPC0_QM_CP_FENCE3_RDATA */ +#define TPC0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF + +/* TPC0_QM_CP_FENCE0_CNT */ +#define TPC0_QM_CP_FENCE0_CNT_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE0_CNT_VAL_MASK 0x3FFF + +/* TPC0_QM_CP_FENCE1_CNT */ +#define TPC0_QM_CP_FENCE1_CNT_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE1_CNT_VAL_MASK 0x3FFF + +/* TPC0_QM_CP_FENCE2_CNT */ +#define TPC0_QM_CP_FENCE2_CNT_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE2_CNT_VAL_MASK 0x3FFF + +/* TPC0_QM_CP_FENCE3_CNT */ +#define TPC0_QM_CP_FENCE3_CNT_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE3_CNT_VAL_MASK 0x3FFF + +/* TPC0_QM_CP_STS */ +#define TPC0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 +#define TPC0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF +#define TPC0_QM_CP_STS_ERDY_SHIFT 16 +#define TPC0_QM_CP_STS_ERDY_MASK 0x10000 +#define TPC0_QM_CP_STS_RRDY_SHIFT 17 +#define TPC0_QM_CP_STS_RRDY_MASK 0x20000 +#define TPC0_QM_CP_STS_MRDY_SHIFT 18 +#define TPC0_QM_CP_STS_MRDY_MASK 0x40000 +#define TPC0_QM_CP_STS_SW_STOP_SHIFT 19 +#define TPC0_QM_CP_STS_SW_STOP_MASK 0x80000 +#define TPC0_QM_CP_STS_FENCE_ID_SHIFT 20 +#define TPC0_QM_CP_STS_FENCE_ID_MASK 0x300000 +#define TPC0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 22 +#define TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000 + +/* TPC0_QM_CP_CURRENT_INST_LO */ +#define TPC0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0 +#define TPC0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_CURRENT_INST_HI */ +#define TPC0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0 +#define TPC0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_BARRIER_CFG */ +#define TPC0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0 +#define TPC0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF +#define TPC0_QM_CP_BARRIER_CFG_RBGUARD_SHIFT 16 +#define TPC0_QM_CP_BARRIER_CFG_RBGUARD_MASK 0xF0000 + +/* TPC0_QM_CP_DBG_0 */ +#define TPC0_QM_CP_DBG_0_CS_SHIFT 0 +#define TPC0_QM_CP_DBG_0_CS_MASK 0xF +#define TPC0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT 4 +#define TPC0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_MASK 0x10 +#define TPC0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT 5 +#define TPC0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK 0x20 +#define TPC0_QM_CP_DBG_0_MREB_STALL_SHIFT 6 +#define TPC0_QM_CP_DBG_0_MREB_STALL_MASK 0x40 +#define TPC0_QM_CP_DBG_0_STALL_SHIFT 7 +#define TPC0_QM_CP_DBG_0_STALL_MASK 0x80 + +/* TPC0_QM_CP_ARUSER_31_11 */ +#define TPC0_QM_CP_ARUSER_31_11_VAL_SHIFT 0 +#define TPC0_QM_CP_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* TPC0_QM_CP_AWUSER_31_11 */ +#define TPC0_QM_CP_AWUSER_31_11_VAL_SHIFT 0 +#define TPC0_QM_CP_AWUSER_31_11_VAL_MASK 0x1FFFFF + +/* TPC0_QM_ARB_CFG_0 */ +#define TPC0_QM_ARB_CFG_0_TYPE_SHIFT 0 +#define TPC0_QM_ARB_CFG_0_TYPE_MASK 0x1 +#define TPC0_QM_ARB_CFG_0_IS_MASTER_SHIFT 4 +#define TPC0_QM_ARB_CFG_0_IS_MASTER_MASK 0x10 +#define TPC0_QM_ARB_CFG_0_EN_SHIFT 8 +#define TPC0_QM_ARB_CFG_0_EN_MASK 0x100 +#define TPC0_QM_ARB_CFG_0_MASK_SHIFT 12 +#define TPC0_QM_ARB_CFG_0_MASK_MASK 0xF000 +#define TPC0_QM_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT 16 +#define TPC0_QM_ARB_CFG_0_MST_MSG_NOSTALL_MASK 0x10000 + +/* TPC0_QM_ARB_CHOISE_Q_PUSH */ +#define TPC0_QM_ARB_CHOISE_Q_PUSH_VAL_SHIFT 0 +#define TPC0_QM_ARB_CHOISE_Q_PUSH_VAL_MASK 0x3 + +/* TPC0_QM_ARB_WRR_WEIGHT */ +#define TPC0_QM_ARB_WRR_WEIGHT_VAL_SHIFT 0 +#define TPC0_QM_ARB_WRR_WEIGHT_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_ARB_CFG_1 */ +#define TPC0_QM_ARB_CFG_1_CLR_SHIFT 0 +#define TPC0_QM_ARB_CFG_1_CLR_MASK 0x1 + +/* TPC0_QM_ARB_MST_AVAIL_CRED */ +#define TPC0_QM_ARB_MST_AVAIL_CRED_VAL_SHIFT 0 +#define TPC0_QM_ARB_MST_AVAIL_CRED_VAL_MASK 0x7F + +/* TPC0_QM_ARB_MST_CRED_INC */ +#define TPC0_QM_ARB_MST_CRED_INC_VAL_SHIFT 0 +#define TPC0_QM_ARB_MST_CRED_INC_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_ARB_MST_CHOISE_PUSH_OFST */ +#define TPC0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_SHIFT 0 +#define TPC0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST */ +#define TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT 0 +#define TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_ARB_MST_SLAVE_EN */ +#define TPC0_QM_ARB_MST_SLAVE_EN_VAL_SHIFT 0 +#define TPC0_QM_ARB_MST_SLAVE_EN_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_ARB_MST_QUIET_PER */ +#define TPC0_QM_ARB_MST_QUIET_PER_VAL_SHIFT 0 +#define TPC0_QM_ARB_MST_QUIET_PER_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_ARB_SLV_CHOISE_WDT */ +#define TPC0_QM_ARB_SLV_CHOISE_WDT_VAL_SHIFT 0 +#define TPC0_QM_ARB_SLV_CHOISE_WDT_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_ARB_SLV_ID */ +#define TPC0_QM_ARB_SLV_ID_VAL_SHIFT 0 +#define TPC0_QM_ARB_SLV_ID_VAL_MASK 0x1F + +/* TPC0_QM_ARB_MSG_MAX_INFLIGHT */ +#define TPC0_QM_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT 0 +#define TPC0_QM_ARB_MSG_MAX_INFLIGHT_VAL_MASK 0x3F + +/* TPC0_QM_ARB_MSG_AWUSER_31_11 */ +#define TPC0_QM_ARB_MSG_AWUSER_31_11_VAL_SHIFT 0 +#define TPC0_QM_ARB_MSG_AWUSER_31_11_VAL_MASK 0x1FFFFF + +/* TPC0_QM_ARB_MSG_AWUSER_SEC_PROP */ +#define TPC0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_SHIFT 0 +#define TPC0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_MASK 0x3FF +#define TPC0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_SHIFT 10 +#define TPC0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_MASK 0x400 + +/* TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP */ +#define TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_SHIFT 0 +#define TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_MASK 0x3FF +#define TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_SHIFT 10 +#define TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_MASK 0x400 + +/* TPC0_QM_ARB_BASE_LO */ +#define TPC0_QM_ARB_BASE_LO_VAL_SHIFT 0 +#define TPC0_QM_ARB_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_ARB_BASE_HI */ +#define TPC0_QM_ARB_BASE_HI_VAL_SHIFT 0 +#define TPC0_QM_ARB_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_ARB_STATE_STS */ +#define TPC0_QM_ARB_STATE_STS_VAL_SHIFT 0 +#define TPC0_QM_ARB_STATE_STS_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_ARB_CHOISE_FULLNESS_STS */ +#define TPC0_QM_ARB_CHOISE_FULLNESS_STS_VAL_SHIFT 0 +#define TPC0_QM_ARB_CHOISE_FULLNESS_STS_VAL_MASK 0x7F + +/* TPC0_QM_ARB_MSG_STS */ +#define TPC0_QM_ARB_MSG_STS_FULL_SHIFT 0 +#define TPC0_QM_ARB_MSG_STS_FULL_MASK 0x1 +#define TPC0_QM_ARB_MSG_STS_NO_INFLIGHT_SHIFT 1 +#define TPC0_QM_ARB_MSG_STS_NO_INFLIGHT_MASK 0x2 + +/* TPC0_QM_ARB_SLV_CHOISE_Q_HEAD */ +#define TPC0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_SHIFT 0 +#define TPC0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_MASK 0x3 + +/* TPC0_QM_ARB_ERR_CAUSE */ +#define TPC0_QM_ARB_ERR_CAUSE_CHOISE_OVF_SHIFT 0 +#define TPC0_QM_ARB_ERR_CAUSE_CHOISE_OVF_MASK 0x1 +#define TPC0_QM_ARB_ERR_CAUSE_CHOISE_WDT_SHIFT 1 +#define TPC0_QM_ARB_ERR_CAUSE_CHOISE_WDT_MASK 0x2 +#define TPC0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT 2 +#define TPC0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK 0x4 + +/* TPC0_QM_ARB_ERR_MSG_EN */ +#define TPC0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_SHIFT 0 +#define TPC0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1 +#define TPC0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_SHIFT 1 +#define TPC0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2 +#define TPC0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT 2 +#define TPC0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4 + +/* TPC0_QM_ARB_ERR_STS_DRP */ +#define TPC0_QM_ARB_ERR_STS_DRP_VAL_SHIFT 0 +#define TPC0_QM_ARB_ERR_STS_DRP_VAL_MASK 0x3 + +/* TPC0_QM_ARB_MST_CRED_STS */ +#define TPC0_QM_ARB_MST_CRED_STS_VAL_SHIFT 0 +#define TPC0_QM_ARB_MST_CRED_STS_VAL_MASK 0x7F + +/* TPC0_QM_CGM_CFG */ +#define TPC0_QM_CGM_CFG_IDLE_TH_SHIFT 0 +#define TPC0_QM_CGM_CFG_IDLE_TH_MASK 0xFFF +#define TPC0_QM_CGM_CFG_G2F_TH_SHIFT 16 +#define TPC0_QM_CGM_CFG_G2F_TH_MASK 0xFF0000 +#define TPC0_QM_CGM_CFG_CP_IDLE_MASK_SHIFT 24 +#define TPC0_QM_CGM_CFG_CP_IDLE_MASK_MASK 0x1F000000 +#define TPC0_QM_CGM_CFG_EN_SHIFT 31 +#define TPC0_QM_CGM_CFG_EN_MASK 0x80000000 + +/* TPC0_QM_CGM_STS */ +#define TPC0_QM_CGM_STS_ST_SHIFT 0 +#define TPC0_QM_CGM_STS_ST_MASK 0x3 +#define TPC0_QM_CGM_STS_CG_SHIFT 4 +#define TPC0_QM_CGM_STS_CG_MASK 0x10 +#define TPC0_QM_CGM_STS_AGENT_IDLE_SHIFT 8 +#define TPC0_QM_CGM_STS_AGENT_IDLE_MASK 0x100 +#define TPC0_QM_CGM_STS_AXI_IDLE_SHIFT 9 +#define TPC0_QM_CGM_STS_AXI_IDLE_MASK 0x200 +#define TPC0_QM_CGM_STS_CP_IDLE_SHIFT 10 +#define TPC0_QM_CGM_STS_CP_IDLE_MASK 0x400 + +/* TPC0_QM_CGM_CFG1 */ +#define TPC0_QM_CGM_CFG1_MASK_TH_SHIFT 0 +#define TPC0_QM_CGM_CFG1_MASK_TH_MASK 0xFF + +/* TPC0_QM_LOCAL_RANGE_BASE */ +#define TPC0_QM_LOCAL_RANGE_BASE_VAL_SHIFT 0 +#define TPC0_QM_LOCAL_RANGE_BASE_VAL_MASK 0xFFFF + +/* TPC0_QM_LOCAL_RANGE_SIZE */ +#define TPC0_QM_LOCAL_RANGE_SIZE_VAL_SHIFT 0 +#define TPC0_QM_LOCAL_RANGE_SIZE_VAL_MASK 0xFFFF + +/* TPC0_QM_CSMR_STRICT_PRIO_CFG */ +#define TPC0_QM_CSMR_STRICT_PRIO_CFG_TYPE_SHIFT 0 +#define TPC0_QM_CSMR_STRICT_PRIO_CFG_TYPE_MASK 0x1 + +/* TPC0_QM_HBW_RD_RATE_LIM_CFG_1 */ +#define TPC0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define TPC0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define TPC0_QM_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT 31 +#define TPC0_QM_HBW_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* TPC0_QM_LBW_WR_RATE_LIM_CFG_0 */ +#define TPC0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define TPC0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define TPC0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define TPC0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* TPC0_QM_LBW_WR_RATE_LIM_CFG_1 */ +#define TPC0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define TPC0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define TPC0_QM_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT 31 +#define TPC0_QM_LBW_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* TPC0_QM_HBW_RD_RATE_LIM_CFG_0 */ +#define TPC0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define TPC0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define TPC0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define TPC0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* TPC0_QM_GLBL_AXCACHE */ +#define TPC0_QM_GLBL_AXCACHE_AR_SHIFT 0 +#define TPC0_QM_GLBL_AXCACHE_AR_MASK 0xF +#define TPC0_QM_GLBL_AXCACHE_AW_SHIFT 16 +#define TPC0_QM_GLBL_AXCACHE_AW_MASK 0xF0000 + +/* TPC0_QM_IND_GW_APB_CFG */ +#define TPC0_QM_IND_GW_APB_CFG_ADDR_SHIFT 0 +#define TPC0_QM_IND_GW_APB_CFG_ADDR_MASK 0x7FFFFFFF +#define TPC0_QM_IND_GW_APB_CFG_CMD_SHIFT 31 +#define TPC0_QM_IND_GW_APB_CFG_CMD_MASK 0x80000000 + +/* TPC0_QM_IND_GW_APB_WDATA */ +#define TPC0_QM_IND_GW_APB_WDATA_VAL_SHIFT 0 +#define TPC0_QM_IND_GW_APB_WDATA_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_IND_GW_APB_RDATA */ +#define TPC0_QM_IND_GW_APB_RDATA_VAL_SHIFT 0 +#define TPC0_QM_IND_GW_APB_RDATA_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_IND_GW_APB_STATUS */ +#define TPC0_QM_IND_GW_APB_STATUS_RDY_SHIFT 0 +#define TPC0_QM_IND_GW_APB_STATUS_RDY_MASK 0x1 +#define TPC0_QM_IND_GW_APB_STATUS_ERR_SHIFT 1 +#define TPC0_QM_IND_GW_APB_STATUS_ERR_MASK 0x2 + +/* TPC0_QM_GLBL_ERR_ADDR_LO */ +#define TPC0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 +#define TPC0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_GLBL_ERR_ADDR_HI */ +#define TPC0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 +#define TPC0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_GLBL_ERR_WDATA */ +#define TPC0_QM_GLBL_ERR_WDATA_VAL_SHIFT 0 +#define TPC0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_GLBL_MEM_INIT_BUSY */ +#define TPC0_QM_GLBL_MEM_INIT_BUSY_RBUF_SHIFT 0 +#define TPC0_QM_GLBL_MEM_INIT_BUSY_RBUF_MASK 0xF + +#endif /* ASIC_REG_TPC0_QM_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_qm_regs.h new file mode 100644 index 000000000000..f9e310ab6df2 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_QM_REGS_H_ +#define ASIC_REG_TPC0_QM_REGS_H_ + +/* + ***************************************** + * TPC0_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC0_QM_GLBL_CFG0 0xE08000 + +#define mmTPC0_QM_GLBL_CFG1 0xE08004 + +#define mmTPC0_QM_GLBL_PROT 0xE08008 + +#define mmTPC0_QM_GLBL_ERR_CFG 0xE0800C + +#define mmTPC0_QM_GLBL_SECURE_PROPS_0 0xE08010 + +#define mmTPC0_QM_GLBL_SECURE_PROPS_1 0xE08014 + +#define mmTPC0_QM_GLBL_SECURE_PROPS_2 0xE08018 + +#define mmTPC0_QM_GLBL_SECURE_PROPS_3 0xE0801C + +#define mmTPC0_QM_GLBL_SECURE_PROPS_4 0xE08020 + +#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_0 0xE08024 + +#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_1 0xE08028 + +#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_2 0xE0802C + +#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_3 0xE08030 + +#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_4 0xE08034 + +#define mmTPC0_QM_GLBL_STS0 0xE08038 + +#define mmTPC0_QM_GLBL_STS1_0 0xE08040 + +#define mmTPC0_QM_GLBL_STS1_1 0xE08044 + +#define mmTPC0_QM_GLBL_STS1_2 0xE08048 + +#define mmTPC0_QM_GLBL_STS1_3 0xE0804C + +#define mmTPC0_QM_GLBL_STS1_4 0xE08050 + +#define mmTPC0_QM_GLBL_MSG_EN_0 0xE08054 + +#define mmTPC0_QM_GLBL_MSG_EN_1 0xE08058 + +#define mmTPC0_QM_GLBL_MSG_EN_2 0xE0805C + +#define mmTPC0_QM_GLBL_MSG_EN_3 0xE08060 + +#define mmTPC0_QM_GLBL_MSG_EN_4 0xE08068 + +#define mmTPC0_QM_PQ_BASE_LO_0 0xE08070 + +#define mmTPC0_QM_PQ_BASE_LO_1 0xE08074 + +#define mmTPC0_QM_PQ_BASE_LO_2 0xE08078 + +#define mmTPC0_QM_PQ_BASE_LO_3 0xE0807C + +#define mmTPC0_QM_PQ_BASE_HI_0 0xE08080 + +#define mmTPC0_QM_PQ_BASE_HI_1 0xE08084 + +#define mmTPC0_QM_PQ_BASE_HI_2 0xE08088 + +#define mmTPC0_QM_PQ_BASE_HI_3 0xE0808C + +#define mmTPC0_QM_PQ_SIZE_0 0xE08090 + +#define mmTPC0_QM_PQ_SIZE_1 0xE08094 + +#define mmTPC0_QM_PQ_SIZE_2 0xE08098 + +#define mmTPC0_QM_PQ_SIZE_3 0xE0809C + +#define mmTPC0_QM_PQ_PI_0 0xE080A0 + +#define mmTPC0_QM_PQ_PI_1 0xE080A4 + +#define mmTPC0_QM_PQ_PI_2 0xE080A8 + +#define mmTPC0_QM_PQ_PI_3 0xE080AC + +#define mmTPC0_QM_PQ_CI_0 0xE080B0 + +#define mmTPC0_QM_PQ_CI_1 0xE080B4 + +#define mmTPC0_QM_PQ_CI_2 0xE080B8 + +#define mmTPC0_QM_PQ_CI_3 0xE080BC + +#define mmTPC0_QM_PQ_CFG0_0 0xE080C0 + +#define mmTPC0_QM_PQ_CFG0_1 0xE080C4 + +#define mmTPC0_QM_PQ_CFG0_2 0xE080C8 + +#define mmTPC0_QM_PQ_CFG0_3 0xE080CC + +#define mmTPC0_QM_PQ_CFG1_0 0xE080D0 + +#define mmTPC0_QM_PQ_CFG1_1 0xE080D4 + +#define mmTPC0_QM_PQ_CFG1_2 0xE080D8 + +#define mmTPC0_QM_PQ_CFG1_3 0xE080DC + +#define mmTPC0_QM_PQ_ARUSER_31_11_0 0xE080E0 + +#define mmTPC0_QM_PQ_ARUSER_31_11_1 0xE080E4 + +#define mmTPC0_QM_PQ_ARUSER_31_11_2 0xE080E8 + +#define mmTPC0_QM_PQ_ARUSER_31_11_3 0xE080EC + +#define mmTPC0_QM_PQ_STS0_0 0xE080F0 + +#define mmTPC0_QM_PQ_STS0_1 0xE080F4 + +#define mmTPC0_QM_PQ_STS0_2 0xE080F8 + +#define mmTPC0_QM_PQ_STS0_3 0xE080FC + +#define mmTPC0_QM_PQ_STS1_0 0xE08100 + +#define mmTPC0_QM_PQ_STS1_1 0xE08104 + +#define mmTPC0_QM_PQ_STS1_2 0xE08108 + +#define mmTPC0_QM_PQ_STS1_3 0xE0810C + +#define mmTPC0_QM_CQ_CFG0_0 0xE08110 + +#define mmTPC0_QM_CQ_CFG0_1 0xE08114 + +#define mmTPC0_QM_CQ_CFG0_2 0xE08118 + +#define mmTPC0_QM_CQ_CFG0_3 0xE0811C + +#define mmTPC0_QM_CQ_CFG0_4 0xE08120 + +#define mmTPC0_QM_CQ_CFG1_0 0xE08124 + +#define mmTPC0_QM_CQ_CFG1_1 0xE08128 + +#define mmTPC0_QM_CQ_CFG1_2 0xE0812C + +#define mmTPC0_QM_CQ_CFG1_3 0xE08130 + +#define mmTPC0_QM_CQ_CFG1_4 0xE08134 + +#define mmTPC0_QM_CQ_ARUSER_31_11_0 0xE08138 + +#define mmTPC0_QM_CQ_ARUSER_31_11_1 0xE0813C + +#define mmTPC0_QM_CQ_ARUSER_31_11_2 0xE08140 + +#define mmTPC0_QM_CQ_ARUSER_31_11_3 0xE08144 + +#define mmTPC0_QM_CQ_ARUSER_31_11_4 0xE08148 + +#define mmTPC0_QM_CQ_STS0_0 0xE0814C + +#define mmTPC0_QM_CQ_STS0_1 0xE08150 + +#define mmTPC0_QM_CQ_STS0_2 0xE08154 + +#define mmTPC0_QM_CQ_STS0_3 0xE08158 + +#define mmTPC0_QM_CQ_STS0_4 0xE0815C + +#define mmTPC0_QM_CQ_STS1_0 0xE08160 + +#define mmTPC0_QM_CQ_STS1_1 0xE08164 + +#define mmTPC0_QM_CQ_STS1_2 0xE08168 + +#define mmTPC0_QM_CQ_STS1_3 0xE0816C + +#define mmTPC0_QM_CQ_STS1_4 0xE08170 + +#define mmTPC0_QM_CQ_PTR_LO_0 0xE08174 + +#define mmTPC0_QM_CQ_PTR_HI_0 0xE08178 + +#define mmTPC0_QM_CQ_TSIZE_0 0xE0817C + +#define mmTPC0_QM_CQ_CTL_0 0xE08180 + +#define mmTPC0_QM_CQ_PTR_LO_1 0xE08184 + +#define mmTPC0_QM_CQ_PTR_HI_1 0xE08188 + +#define mmTPC0_QM_CQ_TSIZE_1 0xE0818C + +#define mmTPC0_QM_CQ_CTL_1 0xE08190 + +#define mmTPC0_QM_CQ_PTR_LO_2 0xE08194 + +#define mmTPC0_QM_CQ_PTR_HI_2 0xE08198 + +#define mmTPC0_QM_CQ_TSIZE_2 0xE0819C + +#define mmTPC0_QM_CQ_CTL_2 0xE081A0 + +#define mmTPC0_QM_CQ_PTR_LO_3 0xE081A4 + +#define mmTPC0_QM_CQ_PTR_HI_3 0xE081A8 + +#define mmTPC0_QM_CQ_TSIZE_3 0xE081AC + +#define mmTPC0_QM_CQ_CTL_3 0xE081B0 + +#define mmTPC0_QM_CQ_PTR_LO_4 0xE081B4 + +#define mmTPC0_QM_CQ_PTR_HI_4 0xE081B8 + +#define mmTPC0_QM_CQ_TSIZE_4 0xE081BC + +#define mmTPC0_QM_CQ_CTL_4 0xE081C0 + +#define mmTPC0_QM_CQ_PTR_LO_STS_0 0xE081C4 + +#define mmTPC0_QM_CQ_PTR_LO_STS_1 0xE081C8 + +#define mmTPC0_QM_CQ_PTR_LO_STS_2 0xE081CC + +#define mmTPC0_QM_CQ_PTR_LO_STS_3 0xE081D0 + +#define mmTPC0_QM_CQ_PTR_LO_STS_4 0xE081D4 + +#define mmTPC0_QM_CQ_PTR_HI_STS_0 0xE081D8 + +#define mmTPC0_QM_CQ_PTR_HI_STS_1 0xE081DC + +#define mmTPC0_QM_CQ_PTR_HI_STS_2 0xE081E0 + +#define mmTPC0_QM_CQ_PTR_HI_STS_3 0xE081E4 + +#define mmTPC0_QM_CQ_PTR_HI_STS_4 0xE081E8 + +#define mmTPC0_QM_CQ_TSIZE_STS_0 0xE081EC + +#define mmTPC0_QM_CQ_TSIZE_STS_1 0xE081F0 + +#define mmTPC0_QM_CQ_TSIZE_STS_2 0xE081F4 + +#define mmTPC0_QM_CQ_TSIZE_STS_3 0xE081F8 + +#define mmTPC0_QM_CQ_TSIZE_STS_4 0xE081FC + +#define mmTPC0_QM_CQ_CTL_STS_0 0xE08200 + +#define mmTPC0_QM_CQ_CTL_STS_1 0xE08204 + +#define mmTPC0_QM_CQ_CTL_STS_2 0xE08208 + +#define mmTPC0_QM_CQ_CTL_STS_3 0xE0820C + +#define mmTPC0_QM_CQ_CTL_STS_4 0xE08210 + +#define mmTPC0_QM_CQ_IFIFO_CNT_0 0xE08214 + +#define mmTPC0_QM_CQ_IFIFO_CNT_1 0xE08218 + +#define mmTPC0_QM_CQ_IFIFO_CNT_2 0xE0821C + +#define mmTPC0_QM_CQ_IFIFO_CNT_3 0xE08220 + +#define mmTPC0_QM_CQ_IFIFO_CNT_4 0xE08224 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_0 0xE08228 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_1 0xE0822C + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_2 0xE08230 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_3 0xE08234 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_4 0xE08238 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_0 0xE0823C + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_1 0xE08240 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_2 0xE08244 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_3 0xE08248 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_4 0xE0824C + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_0 0xE08250 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_1 0xE08254 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_2 0xE08258 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_3 0xE0825C + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_4 0xE08260 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_0 0xE08264 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_1 0xE08268 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_2 0xE0826C + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_3 0xE08270 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_4 0xE08274 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_0 0xE08278 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_1 0xE0827C + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_2 0xE08280 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_3 0xE08284 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_4 0xE08288 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_0 0xE0828C + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_1 0xE08290 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_2 0xE08294 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_3 0xE08298 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_4 0xE0829C + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_0 0xE082A0 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_1 0xE082A4 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_2 0xE082A8 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_3 0xE082AC + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_4 0xE082B0 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_0 0xE082B4 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_1 0xE082B8 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_2 0xE082BC + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_3 0xE082C0 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_4 0xE082C4 + +#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 0xE082C8 + +#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_1 0xE082CC + +#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_2 0xE082D0 + +#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_3 0xE082D4 + +#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_4 0xE082D8 + +#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xE082E0 + +#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xE082E4 + +#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xE082E8 + +#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xE082EC + +#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xE082F0 + +#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xE082F4 + +#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xE082F8 + +#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xE082FC + +#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xE08300 + +#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xE08304 + +#define mmTPC0_QM_CP_FENCE0_RDATA_0 0xE08308 + +#define mmTPC0_QM_CP_FENCE0_RDATA_1 0xE0830C + +#define mmTPC0_QM_CP_FENCE0_RDATA_2 0xE08310 + +#define mmTPC0_QM_CP_FENCE0_RDATA_3 0xE08314 + +#define mmTPC0_QM_CP_FENCE0_RDATA_4 0xE08318 + +#define mmTPC0_QM_CP_FENCE1_RDATA_0 0xE0831C + +#define mmTPC0_QM_CP_FENCE1_RDATA_1 0xE08320 + +#define mmTPC0_QM_CP_FENCE1_RDATA_2 0xE08324 + +#define mmTPC0_QM_CP_FENCE1_RDATA_3 0xE08328 + +#define mmTPC0_QM_CP_FENCE1_RDATA_4 0xE0832C + +#define mmTPC0_QM_CP_FENCE2_RDATA_0 0xE08330 + +#define mmTPC0_QM_CP_FENCE2_RDATA_1 0xE08334 + +#define mmTPC0_QM_CP_FENCE2_RDATA_2 0xE08338 + +#define mmTPC0_QM_CP_FENCE2_RDATA_3 0xE0833C + +#define mmTPC0_QM_CP_FENCE2_RDATA_4 0xE08340 + +#define mmTPC0_QM_CP_FENCE3_RDATA_0 0xE08344 + +#define mmTPC0_QM_CP_FENCE3_RDATA_1 0xE08348 + +#define mmTPC0_QM_CP_FENCE3_RDATA_2 0xE0834C + +#define mmTPC0_QM_CP_FENCE3_RDATA_3 0xE08350 + +#define mmTPC0_QM_CP_FENCE3_RDATA_4 0xE08354 + +#define mmTPC0_QM_CP_FENCE0_CNT_0 0xE08358 + +#define mmTPC0_QM_CP_FENCE0_CNT_1 0xE0835C + +#define mmTPC0_QM_CP_FENCE0_CNT_2 0xE08360 + +#define mmTPC0_QM_CP_FENCE0_CNT_3 0xE08364 + +#define mmTPC0_QM_CP_FENCE0_CNT_4 0xE08368 + +#define mmTPC0_QM_CP_FENCE1_CNT_0 0xE0836C + +#define mmTPC0_QM_CP_FENCE1_CNT_1 0xE08370 + +#define mmTPC0_QM_CP_FENCE1_CNT_2 0xE08374 + +#define mmTPC0_QM_CP_FENCE1_CNT_3 0xE08378 + +#define mmTPC0_QM_CP_FENCE1_CNT_4 0xE0837C + +#define mmTPC0_QM_CP_FENCE2_CNT_0 0xE08380 + +#define mmTPC0_QM_CP_FENCE2_CNT_1 0xE08384 + +#define mmTPC0_QM_CP_FENCE2_CNT_2 0xE08388 + +#define mmTPC0_QM_CP_FENCE2_CNT_3 0xE0838C + +#define mmTPC0_QM_CP_FENCE2_CNT_4 0xE08390 + +#define mmTPC0_QM_CP_FENCE3_CNT_0 0xE08394 + +#define mmTPC0_QM_CP_FENCE3_CNT_1 0xE08398 + +#define mmTPC0_QM_CP_FENCE3_CNT_2 0xE0839C + +#define mmTPC0_QM_CP_FENCE3_CNT_3 0xE083A0 + +#define mmTPC0_QM_CP_FENCE3_CNT_4 0xE083A4 + +#define mmTPC0_QM_CP_STS_0 0xE083A8 + +#define mmTPC0_QM_CP_STS_1 0xE083AC + +#define mmTPC0_QM_CP_STS_2 0xE083B0 + +#define mmTPC0_QM_CP_STS_3 0xE083B4 + +#define mmTPC0_QM_CP_STS_4 0xE083B8 + +#define mmTPC0_QM_CP_CURRENT_INST_LO_0 0xE083BC + +#define mmTPC0_QM_CP_CURRENT_INST_LO_1 0xE083C0 + +#define mmTPC0_QM_CP_CURRENT_INST_LO_2 0xE083C4 + +#define mmTPC0_QM_CP_CURRENT_INST_LO_3 0xE083C8 + +#define mmTPC0_QM_CP_CURRENT_INST_LO_4 0xE083CC + +#define mmTPC0_QM_CP_CURRENT_INST_HI_0 0xE083D0 + +#define mmTPC0_QM_CP_CURRENT_INST_HI_1 0xE083D4 + +#define mmTPC0_QM_CP_CURRENT_INST_HI_2 0xE083D8 + +#define mmTPC0_QM_CP_CURRENT_INST_HI_3 0xE083DC + +#define mmTPC0_QM_CP_CURRENT_INST_HI_4 0xE083E0 + +#define mmTPC0_QM_CP_BARRIER_CFG_0 0xE083F4 + +#define mmTPC0_QM_CP_BARRIER_CFG_1 0xE083F8 + +#define mmTPC0_QM_CP_BARRIER_CFG_2 0xE083FC + +#define mmTPC0_QM_CP_BARRIER_CFG_3 0xE08400 + +#define mmTPC0_QM_CP_BARRIER_CFG_4 0xE08404 + +#define mmTPC0_QM_CP_DBG_0_0 0xE08408 + +#define mmTPC0_QM_CP_DBG_0_1 0xE0840C + +#define mmTPC0_QM_CP_DBG_0_2 0xE08410 + +#define mmTPC0_QM_CP_DBG_0_3 0xE08414 + +#define mmTPC0_QM_CP_DBG_0_4 0xE08418 + +#define mmTPC0_QM_CP_ARUSER_31_11_0 0xE0841C + +#define mmTPC0_QM_CP_ARUSER_31_11_1 0xE08420 + +#define mmTPC0_QM_CP_ARUSER_31_11_2 0xE08424 + +#define mmTPC0_QM_CP_ARUSER_31_11_3 0xE08428 + +#define mmTPC0_QM_CP_ARUSER_31_11_4 0xE0842C + +#define mmTPC0_QM_CP_AWUSER_31_11_0 0xE08430 + +#define mmTPC0_QM_CP_AWUSER_31_11_1 0xE08434 + +#define mmTPC0_QM_CP_AWUSER_31_11_2 0xE08438 + +#define mmTPC0_QM_CP_AWUSER_31_11_3 0xE0843C + +#define mmTPC0_QM_CP_AWUSER_31_11_4 0xE08440 + +#define mmTPC0_QM_ARB_CFG_0 0xE08A00 + +#define mmTPC0_QM_ARB_CHOISE_Q_PUSH 0xE08A04 + +#define mmTPC0_QM_ARB_WRR_WEIGHT_0 0xE08A08 + +#define mmTPC0_QM_ARB_WRR_WEIGHT_1 0xE08A0C + +#define mmTPC0_QM_ARB_WRR_WEIGHT_2 0xE08A10 + +#define mmTPC0_QM_ARB_WRR_WEIGHT_3 0xE08A14 + +#define mmTPC0_QM_ARB_CFG_1 0xE08A18 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_0 0xE08A20 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_1 0xE08A24 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_2 0xE08A28 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_3 0xE08A2C + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_4 0xE08A30 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_5 0xE08A34 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_6 0xE08A38 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_7 0xE08A3C + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_8 0xE08A40 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_9 0xE08A44 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_10 0xE08A48 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_11 0xE08A4C + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_12 0xE08A50 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_13 0xE08A54 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_14 0xE08A58 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_15 0xE08A5C + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_16 0xE08A60 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_17 0xE08A64 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_18 0xE08A68 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_19 0xE08A6C + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_20 0xE08A70 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_21 0xE08A74 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_22 0xE08A78 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_23 0xE08A7C + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_24 0xE08A80 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_25 0xE08A84 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_26 0xE08A88 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_27 0xE08A8C + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_28 0xE08A90 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_29 0xE08A94 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_30 0xE08A98 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_31 0xE08A9C + +#define mmTPC0_QM_ARB_MST_CRED_INC 0xE08AA0 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xE08AA4 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xE08AA8 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xE08AAC + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xE08AB0 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xE08AB4 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xE08AB8 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xE08ABC + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xE08AC0 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xE08AC4 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xE08AC8 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xE08ACC + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xE08AD0 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xE08AD4 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xE08AD8 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xE08ADC + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xE08AE0 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xE08AE4 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xE08AE8 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xE08AEC + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xE08AF0 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xE08AF4 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xE08AF8 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xE08AFC + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xE08B00 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xE08B04 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xE08B08 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xE08B0C + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xE08B10 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xE08B14 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xE08B18 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xE08B1C + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xE08B20 + +#define mmTPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xE08B28 + +#define mmTPC0_QM_ARB_MST_SLAVE_EN 0xE08B2C + +#define mmTPC0_QM_ARB_MST_QUIET_PER 0xE08B34 + +#define mmTPC0_QM_ARB_SLV_CHOISE_WDT 0xE08B38 + +#define mmTPC0_QM_ARB_SLV_ID 0xE08B3C + +#define mmTPC0_QM_ARB_MSG_MAX_INFLIGHT 0xE08B44 + +#define mmTPC0_QM_ARB_MSG_AWUSER_31_11 0xE08B48 + +#define mmTPC0_QM_ARB_MSG_AWUSER_SEC_PROP 0xE08B4C + +#define mmTPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xE08B50 + +#define mmTPC0_QM_ARB_BASE_LO 0xE08B54 + +#define mmTPC0_QM_ARB_BASE_HI 0xE08B58 + +#define mmTPC0_QM_ARB_STATE_STS 0xE08B80 + +#define mmTPC0_QM_ARB_CHOISE_FULLNESS_STS 0xE08B84 + +#define mmTPC0_QM_ARB_MSG_STS 0xE08B88 + +#define mmTPC0_QM_ARB_SLV_CHOISE_Q_HEAD 0xE08B8C + +#define mmTPC0_QM_ARB_ERR_CAUSE 0xE08B9C + +#define mmTPC0_QM_ARB_ERR_MSG_EN 0xE08BA0 + +#define mmTPC0_QM_ARB_ERR_STS_DRP 0xE08BA8 + +#define mmTPC0_QM_ARB_MST_CRED_STS_0 0xE08BB0 + +#define mmTPC0_QM_ARB_MST_CRED_STS_1 0xE08BB4 + +#define mmTPC0_QM_ARB_MST_CRED_STS_2 0xE08BB8 + +#define mmTPC0_QM_ARB_MST_CRED_STS_3 0xE08BBC + +#define mmTPC0_QM_ARB_MST_CRED_STS_4 0xE08BC0 + +#define mmTPC0_QM_ARB_MST_CRED_STS_5 0xE08BC4 + +#define mmTPC0_QM_ARB_MST_CRED_STS_6 0xE08BC8 + +#define mmTPC0_QM_ARB_MST_CRED_STS_7 0xE08BCC + +#define mmTPC0_QM_ARB_MST_CRED_STS_8 0xE08BD0 + +#define mmTPC0_QM_ARB_MST_CRED_STS_9 0xE08BD4 + +#define mmTPC0_QM_ARB_MST_CRED_STS_10 0xE08BD8 + +#define mmTPC0_QM_ARB_MST_CRED_STS_11 0xE08BDC + +#define mmTPC0_QM_ARB_MST_CRED_STS_12 0xE08BE0 + +#define mmTPC0_QM_ARB_MST_CRED_STS_13 0xE08BE4 + +#define mmTPC0_QM_ARB_MST_CRED_STS_14 0xE08BE8 + +#define mmTPC0_QM_ARB_MST_CRED_STS_15 0xE08BEC + +#define mmTPC0_QM_ARB_MST_CRED_STS_16 0xE08BF0 + +#define mmTPC0_QM_ARB_MST_CRED_STS_17 0xE08BF4 + +#define mmTPC0_QM_ARB_MST_CRED_STS_18 0xE08BF8 + +#define mmTPC0_QM_ARB_MST_CRED_STS_19 0xE08BFC + +#define mmTPC0_QM_ARB_MST_CRED_STS_20 0xE08C00 + +#define mmTPC0_QM_ARB_MST_CRED_STS_21 0xE08C04 + +#define mmTPC0_QM_ARB_MST_CRED_STS_22 0xE08C08 + +#define mmTPC0_QM_ARB_MST_CRED_STS_23 0xE08C0C + +#define mmTPC0_QM_ARB_MST_CRED_STS_24 0xE08C10 + +#define mmTPC0_QM_ARB_MST_CRED_STS_25 0xE08C14 + +#define mmTPC0_QM_ARB_MST_CRED_STS_26 0xE08C18 + +#define mmTPC0_QM_ARB_MST_CRED_STS_27 0xE08C1C + +#define mmTPC0_QM_ARB_MST_CRED_STS_28 0xE08C20 + +#define mmTPC0_QM_ARB_MST_CRED_STS_29 0xE08C24 + +#define mmTPC0_QM_ARB_MST_CRED_STS_30 0xE08C28 + +#define mmTPC0_QM_ARB_MST_CRED_STS_31 0xE08C2C + +#define mmTPC0_QM_CGM_CFG 0xE08C70 + +#define mmTPC0_QM_CGM_STS 0xE08C74 + +#define mmTPC0_QM_CGM_CFG1 0xE08C78 + +#define mmTPC0_QM_LOCAL_RANGE_BASE 0xE08C80 + +#define mmTPC0_QM_LOCAL_RANGE_SIZE 0xE08C84 + +#define mmTPC0_QM_CSMR_STRICT_PRIO_CFG 0xE08C90 + +#define mmTPC0_QM_HBW_RD_RATE_LIM_CFG_1 0xE08C94 + +#define mmTPC0_QM_LBW_WR_RATE_LIM_CFG_0 0xE08C98 + +#define mmTPC0_QM_LBW_WR_RATE_LIM_CFG_1 0xE08C9C + +#define mmTPC0_QM_HBW_RD_RATE_LIM_CFG_0 0xE08CA0 + +#define mmTPC0_QM_GLBL_AXCACHE 0xE08CA4 + +#define mmTPC0_QM_IND_GW_APB_CFG 0xE08CB0 + +#define mmTPC0_QM_IND_GW_APB_WDATA 0xE08CB4 + +#define mmTPC0_QM_IND_GW_APB_RDATA 0xE08CB8 + +#define mmTPC0_QM_IND_GW_APB_STATUS 0xE08CBC + +#define mmTPC0_QM_GLBL_ERR_ADDR_LO 0xE08CD0 + +#define mmTPC0_QM_GLBL_ERR_ADDR_HI 0xE08CD4 + +#define mmTPC0_QM_GLBL_ERR_WDATA 0xE08CD8 + +#define mmTPC0_QM_GLBL_MEM_INIT_BUSY 0xE08D00 + +#endif /* ASIC_REG_TPC0_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc1_cfg_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc1_cfg_regs.h new file mode 100644 index 000000000000..6736c476d979 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc1_cfg_regs.h @@ -0,0 +1,1226 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC1_CFG_REGS_H_ +#define ASIC_REG_TPC1_CFG_REGS_H_ + +/* + ***************************************** + * TPC1_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC1_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE46400 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE46404 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE46408 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE4640C + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE46410 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE46414 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE46418 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE4641C + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE46420 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE46424 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE46428 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE4642C + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE46430 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE46434 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE46438 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE4643C + +#define mmTPC1_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE46440 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE46444 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE46448 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE4644C + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE46450 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE46454 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE46458 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE4645C + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE46460 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE46464 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE46468 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE4646C + +#define mmTPC1_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE46470 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE46474 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE46478 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE4647C + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE46480 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE46484 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE46488 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE4648C + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE46490 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE46494 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE46498 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE4649C + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE464A0 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE464A4 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE464A8 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE464AC + +#define mmTPC1_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE464B0 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE464B4 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE464B8 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE464BC + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE464C0 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE464C4 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE464C8 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE464CC + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE464D0 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE464D4 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE464D8 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE464DC + +#define mmTPC1_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE464E0 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE464E4 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE464E8 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE464EC + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE464F0 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE464F4 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE464F8 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE464FC + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE46500 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE46504 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE46508 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE4650C + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE46510 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE46514 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE46518 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE4651C + +#define mmTPC1_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE46520 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE46524 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE46528 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE4652C + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE46530 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE46534 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE46538 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE4653C + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE46540 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE46544 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE46548 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE4654C + +#define mmTPC1_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE46550 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE46554 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE46558 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE4655C + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE46560 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE46564 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE46568 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE4656C + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE46570 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE46574 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE46578 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE4657C + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE46580 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE46584 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE46588 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE4658C + +#define mmTPC1_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE46590 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE46594 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE46598 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE4659C + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE465A0 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE465A4 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE465A8 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE465AC + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE465B0 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE465B4 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE465B8 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE465BC + +#define mmTPC1_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xE465C0 + +#define mmTPC1_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xE465C4 + +#define mmTPC1_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xE465C8 + +#define mmTPC1_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xE465CC + +#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xE465D0 + +#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xE465D4 + +#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xE465D8 + +#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xE465DC + +#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xE465E0 + +#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xE465E4 + +#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xE465E8 + +#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xE465EC + +#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xE465F0 + +#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xE465F4 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xE465F8 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xE465FC + +#define mmTPC1_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xE46600 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xE46604 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xE46608 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xE4660C + +#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xE46610 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xE46614 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xE46618 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xE4661C + +#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xE46620 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xE46624 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xE46628 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xE4662C + +#define mmTPC1_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xE46630 + +#define mmTPC1_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xE46634 + +#define mmTPC1_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xE46638 + +#define mmTPC1_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xE4663C + +#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xE46640 + +#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xE46644 + +#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xE46648 + +#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xE4664C + +#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xE46650 + +#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xE46654 + +#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xE46658 + +#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xE4665C + +#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xE46660 + +#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xE46664 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xE46668 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xE4666C + +#define mmTPC1_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xE46670 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xE46674 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xE46678 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xE4667C + +#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xE46680 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xE46684 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xE46688 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xE4668C + +#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xE46690 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xE46694 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xE46698 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xE4669C + +#define mmTPC1_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xE466A0 + +#define mmTPC1_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xE466A4 + +#define mmTPC1_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xE466A8 + +#define mmTPC1_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xE466AC + +#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xE466B0 + +#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xE466B4 + +#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xE466B8 + +#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xE466BC + +#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xE466C0 + +#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xE466C4 + +#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xE466C8 + +#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xE466CC + +#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xE466D0 + +#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xE466D4 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xE466D8 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xE466DC + +#define mmTPC1_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xE466E0 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xE466E4 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xE466E8 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xE466EC + +#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xE466F0 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xE466F4 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xE466F8 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xE466FC + +#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xE46700 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xE46704 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xE46708 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xE4670C + +#define mmTPC1_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xE46710 + +#define mmTPC1_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xE46714 + +#define mmTPC1_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xE46718 + +#define mmTPC1_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xE4671C + +#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xE46720 + +#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xE46724 + +#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xE46728 + +#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xE4672C + +#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xE46730 + +#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xE46734 + +#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xE46738 + +#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xE4673C + +#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xE46740 + +#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xE46744 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xE46748 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xE4674C + +#define mmTPC1_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xE46750 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xE46754 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xE46758 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xE4675C + +#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xE46760 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xE46764 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xE46768 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xE4676C + +#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xE46770 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xE46774 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xE46778 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xE4677C + +#define mmTPC1_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE46780 + +#define mmTPC1_CFG_KERNEL_SYNC_OBJECT_ADDR 0xE46784 + +#define mmTPC1_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE46788 + +#define mmTPC1_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE4678C + +#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_0 0xE46790 + +#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_0 0xE46794 + +#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_1 0xE46798 + +#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_1 0xE4679C + +#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_2 0xE467A0 + +#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_2 0xE467A4 + +#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_3 0xE467A8 + +#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_3 0xE467AC + +#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_4 0xE467B0 + +#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_4 0xE467B4 + +#define mmTPC1_CFG_KERNEL_KERNEL_CONFIG 0xE467B8 + +#define mmTPC1_CFG_KERNEL_KERNEL_ID 0xE467BC + +#define mmTPC1_CFG_KERNEL_SRF_0 0xE467C0 + +#define mmTPC1_CFG_KERNEL_SRF_1 0xE467C4 + +#define mmTPC1_CFG_KERNEL_SRF_2 0xE467C8 + +#define mmTPC1_CFG_KERNEL_SRF_3 0xE467CC + +#define mmTPC1_CFG_KERNEL_SRF_4 0xE467D0 + +#define mmTPC1_CFG_KERNEL_SRF_5 0xE467D4 + +#define mmTPC1_CFG_KERNEL_SRF_6 0xE467D8 + +#define mmTPC1_CFG_KERNEL_SRF_7 0xE467DC + +#define mmTPC1_CFG_KERNEL_SRF_8 0xE467E0 + +#define mmTPC1_CFG_KERNEL_SRF_9 0xE467E4 + +#define mmTPC1_CFG_KERNEL_SRF_10 0xE467E8 + +#define mmTPC1_CFG_KERNEL_SRF_11 0xE467EC + +#define mmTPC1_CFG_KERNEL_SRF_12 0xE467F0 + +#define mmTPC1_CFG_KERNEL_SRF_13 0xE467F4 + +#define mmTPC1_CFG_KERNEL_SRF_14 0xE467F8 + +#define mmTPC1_CFG_KERNEL_SRF_15 0xE467FC + +#define mmTPC1_CFG_KERNEL_SRF_16 0xE46800 + +#define mmTPC1_CFG_KERNEL_SRF_17 0xE46804 + +#define mmTPC1_CFG_KERNEL_SRF_18 0xE46808 + +#define mmTPC1_CFG_KERNEL_SRF_19 0xE4680C + +#define mmTPC1_CFG_KERNEL_SRF_20 0xE46810 + +#define mmTPC1_CFG_KERNEL_SRF_21 0xE46814 + +#define mmTPC1_CFG_KERNEL_SRF_22 0xE46818 + +#define mmTPC1_CFG_KERNEL_SRF_23 0xE4681C + +#define mmTPC1_CFG_KERNEL_SRF_24 0xE46820 + +#define mmTPC1_CFG_KERNEL_SRF_25 0xE46824 + +#define mmTPC1_CFG_KERNEL_SRF_26 0xE46828 + +#define mmTPC1_CFG_KERNEL_SRF_27 0xE4682C + +#define mmTPC1_CFG_KERNEL_SRF_28 0xE46830 + +#define mmTPC1_CFG_KERNEL_SRF_29 0xE46834 + +#define mmTPC1_CFG_KERNEL_SRF_30 0xE46838 + +#define mmTPC1_CFG_KERNEL_SRF_31 0xE4683C + +#define mmTPC1_CFG_ROUND_CSR 0xE468FC + +#define mmTPC1_CFG_PROT 0xE46900 + +#define mmTPC1_CFG_SEMAPHORE 0xE46908 + +#define mmTPC1_CFG_VFLAGS 0xE4690C + +#define mmTPC1_CFG_SFLAGS 0xE46910 + +#define mmTPC1_CFG_LFSR_POLYNOM 0xE46918 + +#define mmTPC1_CFG_STATUS 0xE4691C + +#define mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH 0xE46920 + +#define mmTPC1_CFG_CFG_SUBTRACT_VALUE 0xE46924 + +#define mmTPC1_CFG_SM_BASE_ADDRESS_HIGH 0xE4692C + +#define mmTPC1_CFG_TPC_CMD 0xE46930 + +#define mmTPC1_CFG_TPC_EXECUTE 0xE46938 + +#define mmTPC1_CFG_TPC_STALL 0xE4693C + +#define mmTPC1_CFG_ICACHE_BASE_ADDERESS_LOW 0xE46940 + +#define mmTPC1_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE46944 + +#define mmTPC1_CFG_RD_RATE_LIMIT 0xE46948 + +#define mmTPC1_CFG_WR_RATE_LIMIT 0xE46950 + +#define mmTPC1_CFG_MSS_CONFIG 0xE46954 + +#define mmTPC1_CFG_TPC_INTR_CAUSE 0xE46958 + +#define mmTPC1_CFG_TPC_INTR_MASK 0xE4695C + +#define mmTPC1_CFG_WQ_CREDITS 0xE46960 + +#define mmTPC1_CFG_ARUSER_LO 0xE46964 + +#define mmTPC1_CFG_ARUSER_HI 0xE46968 + +#define mmTPC1_CFG_AWUSER_LO 0xE4696C + +#define mmTPC1_CFG_AWUSER_HI 0xE46970 + +#define mmTPC1_CFG_OPCODE_EXEC 0xE46974 + +#define mmTPC1_CFG_LUT_FUNC32_BASE_ADDR_LO 0xE46978 + +#define mmTPC1_CFG_LUT_FUNC32_BASE_ADDR_HI 0xE4697C + +#define mmTPC1_CFG_LUT_FUNC64_BASE_ADDR_LO 0xE46980 + +#define mmTPC1_CFG_LUT_FUNC64_BASE_ADDR_HI 0xE46984 + +#define mmTPC1_CFG_LUT_FUNC128_BASE_ADDR_LO 0xE46988 + +#define mmTPC1_CFG_LUT_FUNC128_BASE_ADDR_HI 0xE4698C + +#define mmTPC1_CFG_LUT_FUNC256_BASE_ADDR_LO 0xE46990 + +#define mmTPC1_CFG_LUT_FUNC256_BASE_ADDR_HI 0xE46994 + +#define mmTPC1_CFG_TSB_CFG_MAX_SIZE 0xE46998 + +#define mmTPC1_CFG_TSB_CFG 0xE4699C + +#define mmTPC1_CFG_DBGMEM_ADD 0xE469A0 + +#define mmTPC1_CFG_DBGMEM_DATA_WR 0xE469A4 + +#define mmTPC1_CFG_DBGMEM_DATA_RD 0xE469A8 + +#define mmTPC1_CFG_DBGMEM_CTRL 0xE469AC + +#define mmTPC1_CFG_DBGMEM_RC 0xE469B0 + +#define mmTPC1_CFG_TSB_INFLIGHT_CNTR 0xE469B4 + +#define mmTPC1_CFG_WQ_INFLIGHT_CNTR 0xE469B8 + +#define mmTPC1_CFG_WQ_LBW_TOTAL_CNTR 0xE469BC + +#define mmTPC1_CFG_WQ_HBW_TOTAL_CNTR 0xE469C0 + +#define mmTPC1_CFG_IRQ_OCCOUPY_CNTR 0xE469C4 + +#define mmTPC1_CFG_FUNC_MBIST_CNTRL 0xE469D0 + +#define mmTPC1_CFG_FUNC_MBIST_PAT 0xE469D4 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_0 0xE469D8 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_1 0xE469DC + +#define mmTPC1_CFG_FUNC_MBIST_MEM_2 0xE469E0 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_3 0xE469E4 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_4 0xE469E8 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_5 0xE469EC + +#define mmTPC1_CFG_FUNC_MBIST_MEM_6 0xE469F0 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_7 0xE469F4 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_8 0xE469F8 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_9 0xE469FC + +#define mmTPC1_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE46A00 + +#define mmTPC1_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE46A04 + +#define mmTPC1_CFG_QM_TENSOR_0_PADDING_VALUE 0xE46A08 + +#define mmTPC1_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE46A0C + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE46A10 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE46A14 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE46A18 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE46A1C + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE46A20 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE46A24 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE46A28 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE46A2C + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE46A30 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE46A34 + +#define mmTPC1_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE46A38 + +#define mmTPC1_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE46A3C + +#define mmTPC1_CFG_QM_TENSOR_1_PADDING_VALUE 0xE46A40 + +#define mmTPC1_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE46A44 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE46A48 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE46A4C + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE46A50 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE46A54 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE46A58 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE46A5C + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE46A60 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE46A64 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE46A68 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE46A6C + +#define mmTPC1_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE46A70 + +#define mmTPC1_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE46A74 + +#define mmTPC1_CFG_QM_TENSOR_2_PADDING_VALUE 0xE46A78 + +#define mmTPC1_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE46A7C + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE46A80 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE46A84 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE46A88 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE46A8C + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE46A90 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE46A94 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE46A98 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE46A9C + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE46AA0 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE46AA4 + +#define mmTPC1_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE46AA8 + +#define mmTPC1_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE46AAC + +#define mmTPC1_CFG_QM_TENSOR_3_PADDING_VALUE 0xE46AB0 + +#define mmTPC1_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE46AB4 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE46AB8 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE46ABC + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE46AC0 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE46AC4 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE46AC8 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE46ACC + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE46AD0 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE46AD4 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE46AD8 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE46ADC + +#define mmTPC1_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE46AE0 + +#define mmTPC1_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE46AE4 + +#define mmTPC1_CFG_QM_TENSOR_4_PADDING_VALUE 0xE46AE8 + +#define mmTPC1_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE46AEC + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE46AF0 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE46AF4 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE46AF8 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE46AFC + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE46B00 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE46B04 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE46B08 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE46B0C + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE46B10 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE46B14 + +#define mmTPC1_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE46B18 + +#define mmTPC1_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE46B1C + +#define mmTPC1_CFG_QM_TENSOR_5_PADDING_VALUE 0xE46B20 + +#define mmTPC1_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE46B24 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE46B28 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE46B2C + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE46B30 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE46B34 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE46B38 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE46B3C + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE46B40 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE46B44 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE46B48 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE46B4C + +#define mmTPC1_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE46B50 + +#define mmTPC1_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE46B54 + +#define mmTPC1_CFG_QM_TENSOR_6_PADDING_VALUE 0xE46B58 + +#define mmTPC1_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE46B5C + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE46B60 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE46B64 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE46B68 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE46B6C + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE46B70 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE46B74 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE46B78 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE46B7C + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE46B80 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE46B84 + +#define mmTPC1_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE46B88 + +#define mmTPC1_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE46B8C + +#define mmTPC1_CFG_QM_TENSOR_7_PADDING_VALUE 0xE46B90 + +#define mmTPC1_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE46B94 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE46B98 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE46B9C + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE46BA0 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE46BA4 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE46BA8 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE46BAC + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE46BB0 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE46BB4 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE46BB8 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE46BBC + +#define mmTPC1_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xE46BC0 + +#define mmTPC1_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xE46BC4 + +#define mmTPC1_CFG_QM_TENSOR_8_PADDING_VALUE 0xE46BC8 + +#define mmTPC1_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xE46BCC + +#define mmTPC1_CFG_QM_TENSOR_8_DIM_0_SIZE 0xE46BD0 + +#define mmTPC1_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xE46BD4 + +#define mmTPC1_CFG_QM_TENSOR_8_DIM_1_SIZE 0xE46BD8 + +#define mmTPC1_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xE46BDC + +#define mmTPC1_CFG_QM_TENSOR_8_DIM_2_SIZE 0xE46BE0 + +#define mmTPC1_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xE46BE4 + +#define mmTPC1_CFG_QM_TENSOR_8_DIM_3_SIZE 0xE46BE8 + +#define mmTPC1_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xE46BEC + +#define mmTPC1_CFG_QM_TENSOR_8_DIM_4_SIZE 0xE46BF0 + +#define mmTPC1_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xE46BF4 + +#define mmTPC1_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xE46BF8 + +#define mmTPC1_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xE46BFC + +#define mmTPC1_CFG_QM_TENSOR_9_PADDING_VALUE 0xE46C00 + +#define mmTPC1_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xE46C04 + +#define mmTPC1_CFG_QM_TENSOR_9_DIM_0_SIZE 0xE46C08 + +#define mmTPC1_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xE46C0C + +#define mmTPC1_CFG_QM_TENSOR_9_DIM_1_SIZE 0xE46C10 + +#define mmTPC1_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xE46C14 + +#define mmTPC1_CFG_QM_TENSOR_9_DIM_2_SIZE 0xE46C18 + +#define mmTPC1_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xE46C1C + +#define mmTPC1_CFG_QM_TENSOR_9_DIM_3_SIZE 0xE46C20 + +#define mmTPC1_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xE46C24 + +#define mmTPC1_CFG_QM_TENSOR_9_DIM_4_SIZE 0xE46C28 + +#define mmTPC1_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xE46C2C + +#define mmTPC1_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xE46C30 + +#define mmTPC1_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xE46C34 + +#define mmTPC1_CFG_QM_TENSOR_10_PADDING_VALUE 0xE46C38 + +#define mmTPC1_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xE46C3C + +#define mmTPC1_CFG_QM_TENSOR_10_DIM_0_SIZE 0xE46C40 + +#define mmTPC1_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xE46C44 + +#define mmTPC1_CFG_QM_TENSOR_10_DIM_1_SIZE 0xE46C48 + +#define mmTPC1_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xE46C4C + +#define mmTPC1_CFG_QM_TENSOR_10_DIM_2_SIZE 0xE46C50 + +#define mmTPC1_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xE46C54 + +#define mmTPC1_CFG_QM_TENSOR_10_DIM_3_SIZE 0xE46C58 + +#define mmTPC1_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xE46C5C + +#define mmTPC1_CFG_QM_TENSOR_10_DIM_4_SIZE 0xE46C60 + +#define mmTPC1_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xE46C64 + +#define mmTPC1_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xE46C68 + +#define mmTPC1_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xE46C6C + +#define mmTPC1_CFG_QM_TENSOR_11_PADDING_VALUE 0xE46C70 + +#define mmTPC1_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xE46C74 + +#define mmTPC1_CFG_QM_TENSOR_11_DIM_0_SIZE 0xE46C78 + +#define mmTPC1_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xE46C7C + +#define mmTPC1_CFG_QM_TENSOR_11_DIM_1_SIZE 0xE46C80 + +#define mmTPC1_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xE46C84 + +#define mmTPC1_CFG_QM_TENSOR_11_DIM_2_SIZE 0xE46C88 + +#define mmTPC1_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xE46C8C + +#define mmTPC1_CFG_QM_TENSOR_11_DIM_3_SIZE 0xE46C90 + +#define mmTPC1_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xE46C94 + +#define mmTPC1_CFG_QM_TENSOR_11_DIM_4_SIZE 0xE46C98 + +#define mmTPC1_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xE46C9C + +#define mmTPC1_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xE46CA0 + +#define mmTPC1_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xE46CA4 + +#define mmTPC1_CFG_QM_TENSOR_12_PADDING_VALUE 0xE46CA8 + +#define mmTPC1_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xE46CAC + +#define mmTPC1_CFG_QM_TENSOR_12_DIM_0_SIZE 0xE46CB0 + +#define mmTPC1_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xE46CB4 + +#define mmTPC1_CFG_QM_TENSOR_12_DIM_1_SIZE 0xE46CB8 + +#define mmTPC1_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xE46CBC + +#define mmTPC1_CFG_QM_TENSOR_12_DIM_2_SIZE 0xE46CC0 + +#define mmTPC1_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xE46CC4 + +#define mmTPC1_CFG_QM_TENSOR_12_DIM_3_SIZE 0xE46CC8 + +#define mmTPC1_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xE46CCC + +#define mmTPC1_CFG_QM_TENSOR_12_DIM_4_SIZE 0xE46CD0 + +#define mmTPC1_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xE46CD4 + +#define mmTPC1_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xE46CD8 + +#define mmTPC1_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xE46CDC + +#define mmTPC1_CFG_QM_TENSOR_13_PADDING_VALUE 0xE46CE0 + +#define mmTPC1_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xE46CE4 + +#define mmTPC1_CFG_QM_TENSOR_13_DIM_0_SIZE 0xE46CE8 + +#define mmTPC1_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xE46CEC + +#define mmTPC1_CFG_QM_TENSOR_13_DIM_1_SIZE 0xE46CF0 + +#define mmTPC1_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xE46CF4 + +#define mmTPC1_CFG_QM_TENSOR_13_DIM_2_SIZE 0xE46CF8 + +#define mmTPC1_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xE46CFC + +#define mmTPC1_CFG_QM_TENSOR_13_DIM_3_SIZE 0xE46D00 + +#define mmTPC1_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xE46D04 + +#define mmTPC1_CFG_QM_TENSOR_13_DIM_4_SIZE 0xE46D08 + +#define mmTPC1_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xE46D0C + +#define mmTPC1_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xE46D10 + +#define mmTPC1_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xE46D14 + +#define mmTPC1_CFG_QM_TENSOR_14_PADDING_VALUE 0xE46D18 + +#define mmTPC1_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xE46D1C + +#define mmTPC1_CFG_QM_TENSOR_14_DIM_0_SIZE 0xE46D20 + +#define mmTPC1_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xE46D24 + +#define mmTPC1_CFG_QM_TENSOR_14_DIM_1_SIZE 0xE46D28 + +#define mmTPC1_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xE46D2C + +#define mmTPC1_CFG_QM_TENSOR_14_DIM_2_SIZE 0xE46D30 + +#define mmTPC1_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xE46D34 + +#define mmTPC1_CFG_QM_TENSOR_14_DIM_3_SIZE 0xE46D38 + +#define mmTPC1_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xE46D3C + +#define mmTPC1_CFG_QM_TENSOR_14_DIM_4_SIZE 0xE46D40 + +#define mmTPC1_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xE46D44 + +#define mmTPC1_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xE46D48 + +#define mmTPC1_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xE46D4C + +#define mmTPC1_CFG_QM_TENSOR_15_PADDING_VALUE 0xE46D50 + +#define mmTPC1_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xE46D54 + +#define mmTPC1_CFG_QM_TENSOR_15_DIM_0_SIZE 0xE46D58 + +#define mmTPC1_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xE46D5C + +#define mmTPC1_CFG_QM_TENSOR_15_DIM_1_SIZE 0xE46D60 + +#define mmTPC1_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xE46D64 + +#define mmTPC1_CFG_QM_TENSOR_15_DIM_2_SIZE 0xE46D68 + +#define mmTPC1_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xE46D6C + +#define mmTPC1_CFG_QM_TENSOR_15_DIM_3_SIZE 0xE46D70 + +#define mmTPC1_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xE46D74 + +#define mmTPC1_CFG_QM_TENSOR_15_DIM_4_SIZE 0xE46D78 + +#define mmTPC1_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xE46D7C + +#define mmTPC1_CFG_QM_SYNC_OBJECT_MESSAGE 0xE46D80 + +#define mmTPC1_CFG_QM_SYNC_OBJECT_ADDR 0xE46D84 + +#define mmTPC1_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE46D88 + +#define mmTPC1_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE46D8C + +#define mmTPC1_CFG_QM_TID_BASE_DIM_0 0xE46D90 + +#define mmTPC1_CFG_QM_TID_SIZE_DIM_0 0xE46D94 + +#define mmTPC1_CFG_QM_TID_BASE_DIM_1 0xE46D98 + +#define mmTPC1_CFG_QM_TID_SIZE_DIM_1 0xE46D9C + +#define mmTPC1_CFG_QM_TID_BASE_DIM_2 0xE46DA0 + +#define mmTPC1_CFG_QM_TID_SIZE_DIM_2 0xE46DA4 + +#define mmTPC1_CFG_QM_TID_BASE_DIM_3 0xE46DA8 + +#define mmTPC1_CFG_QM_TID_SIZE_DIM_3 0xE46DAC + +#define mmTPC1_CFG_QM_TID_BASE_DIM_4 0xE46DB0 + +#define mmTPC1_CFG_QM_TID_SIZE_DIM_4 0xE46DB4 + +#define mmTPC1_CFG_QM_KERNEL_CONFIG 0xE46DB8 + +#define mmTPC1_CFG_QM_KERNEL_ID 0xE46DBC + +#define mmTPC1_CFG_QM_SRF_0 0xE46DC0 + +#define mmTPC1_CFG_QM_SRF_1 0xE46DC4 + +#define mmTPC1_CFG_QM_SRF_2 0xE46DC8 + +#define mmTPC1_CFG_QM_SRF_3 0xE46DCC + +#define mmTPC1_CFG_QM_SRF_4 0xE46DD0 + +#define mmTPC1_CFG_QM_SRF_5 0xE46DD4 + +#define mmTPC1_CFG_QM_SRF_6 0xE46DD8 + +#define mmTPC1_CFG_QM_SRF_7 0xE46DDC + +#define mmTPC1_CFG_QM_SRF_8 0xE46DE0 + +#define mmTPC1_CFG_QM_SRF_9 0xE46DE4 + +#define mmTPC1_CFG_QM_SRF_10 0xE46DE8 + +#define mmTPC1_CFG_QM_SRF_11 0xE46DEC + +#define mmTPC1_CFG_QM_SRF_12 0xE46DF0 + +#define mmTPC1_CFG_QM_SRF_13 0xE46DF4 + +#define mmTPC1_CFG_QM_SRF_14 0xE46DF8 + +#define mmTPC1_CFG_QM_SRF_15 0xE46DFC + +#define mmTPC1_CFG_QM_SRF_16 0xE46E00 + +#define mmTPC1_CFG_QM_SRF_17 0xE46E04 + +#define mmTPC1_CFG_QM_SRF_18 0xE46E08 + +#define mmTPC1_CFG_QM_SRF_19 0xE46E0C + +#define mmTPC1_CFG_QM_SRF_20 0xE46E10 + +#define mmTPC1_CFG_QM_SRF_21 0xE46E14 + +#define mmTPC1_CFG_QM_SRF_22 0xE46E18 + +#define mmTPC1_CFG_QM_SRF_23 0xE46E1C + +#define mmTPC1_CFG_QM_SRF_24 0xE46E20 + +#define mmTPC1_CFG_QM_SRF_25 0xE46E24 + +#define mmTPC1_CFG_QM_SRF_26 0xE46E28 + +#define mmTPC1_CFG_QM_SRF_27 0xE46E2C + +#define mmTPC1_CFG_QM_SRF_28 0xE46E30 + +#define mmTPC1_CFG_QM_SRF_29 0xE46E34 + +#define mmTPC1_CFG_QM_SRF_30 0xE46E38 + +#define mmTPC1_CFG_QM_SRF_31 0xE46E3C + +#endif /* ASIC_REG_TPC1_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc1_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc1_qm_regs.h new file mode 100644 index 000000000000..af10ef7a87d9 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc1_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC1_QM_REGS_H_ +#define ASIC_REG_TPC1_QM_REGS_H_ + +/* + ***************************************** + * TPC1_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC1_QM_GLBL_CFG0 0xE48000 + +#define mmTPC1_QM_GLBL_CFG1 0xE48004 + +#define mmTPC1_QM_GLBL_PROT 0xE48008 + +#define mmTPC1_QM_GLBL_ERR_CFG 0xE4800C + +#define mmTPC1_QM_GLBL_SECURE_PROPS_0 0xE48010 + +#define mmTPC1_QM_GLBL_SECURE_PROPS_1 0xE48014 + +#define mmTPC1_QM_GLBL_SECURE_PROPS_2 0xE48018 + +#define mmTPC1_QM_GLBL_SECURE_PROPS_3 0xE4801C + +#define mmTPC1_QM_GLBL_SECURE_PROPS_4 0xE48020 + +#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_0 0xE48024 + +#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_1 0xE48028 + +#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_2 0xE4802C + +#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_3 0xE48030 + +#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_4 0xE48034 + +#define mmTPC1_QM_GLBL_STS0 0xE48038 + +#define mmTPC1_QM_GLBL_STS1_0 0xE48040 + +#define mmTPC1_QM_GLBL_STS1_1 0xE48044 + +#define mmTPC1_QM_GLBL_STS1_2 0xE48048 + +#define mmTPC1_QM_GLBL_STS1_3 0xE4804C + +#define mmTPC1_QM_GLBL_STS1_4 0xE48050 + +#define mmTPC1_QM_GLBL_MSG_EN_0 0xE48054 + +#define mmTPC1_QM_GLBL_MSG_EN_1 0xE48058 + +#define mmTPC1_QM_GLBL_MSG_EN_2 0xE4805C + +#define mmTPC1_QM_GLBL_MSG_EN_3 0xE48060 + +#define mmTPC1_QM_GLBL_MSG_EN_4 0xE48068 + +#define mmTPC1_QM_PQ_BASE_LO_0 0xE48070 + +#define mmTPC1_QM_PQ_BASE_LO_1 0xE48074 + +#define mmTPC1_QM_PQ_BASE_LO_2 0xE48078 + +#define mmTPC1_QM_PQ_BASE_LO_3 0xE4807C + +#define mmTPC1_QM_PQ_BASE_HI_0 0xE48080 + +#define mmTPC1_QM_PQ_BASE_HI_1 0xE48084 + +#define mmTPC1_QM_PQ_BASE_HI_2 0xE48088 + +#define mmTPC1_QM_PQ_BASE_HI_3 0xE4808C + +#define mmTPC1_QM_PQ_SIZE_0 0xE48090 + +#define mmTPC1_QM_PQ_SIZE_1 0xE48094 + +#define mmTPC1_QM_PQ_SIZE_2 0xE48098 + +#define mmTPC1_QM_PQ_SIZE_3 0xE4809C + +#define mmTPC1_QM_PQ_PI_0 0xE480A0 + +#define mmTPC1_QM_PQ_PI_1 0xE480A4 + +#define mmTPC1_QM_PQ_PI_2 0xE480A8 + +#define mmTPC1_QM_PQ_PI_3 0xE480AC + +#define mmTPC1_QM_PQ_CI_0 0xE480B0 + +#define mmTPC1_QM_PQ_CI_1 0xE480B4 + +#define mmTPC1_QM_PQ_CI_2 0xE480B8 + +#define mmTPC1_QM_PQ_CI_3 0xE480BC + +#define mmTPC1_QM_PQ_CFG0_0 0xE480C0 + +#define mmTPC1_QM_PQ_CFG0_1 0xE480C4 + +#define mmTPC1_QM_PQ_CFG0_2 0xE480C8 + +#define mmTPC1_QM_PQ_CFG0_3 0xE480CC + +#define mmTPC1_QM_PQ_CFG1_0 0xE480D0 + +#define mmTPC1_QM_PQ_CFG1_1 0xE480D4 + +#define mmTPC1_QM_PQ_CFG1_2 0xE480D8 + +#define mmTPC1_QM_PQ_CFG1_3 0xE480DC + +#define mmTPC1_QM_PQ_ARUSER_31_11_0 0xE480E0 + +#define mmTPC1_QM_PQ_ARUSER_31_11_1 0xE480E4 + +#define mmTPC1_QM_PQ_ARUSER_31_11_2 0xE480E8 + +#define mmTPC1_QM_PQ_ARUSER_31_11_3 0xE480EC + +#define mmTPC1_QM_PQ_STS0_0 0xE480F0 + +#define mmTPC1_QM_PQ_STS0_1 0xE480F4 + +#define mmTPC1_QM_PQ_STS0_2 0xE480F8 + +#define mmTPC1_QM_PQ_STS0_3 0xE480FC + +#define mmTPC1_QM_PQ_STS1_0 0xE48100 + +#define mmTPC1_QM_PQ_STS1_1 0xE48104 + +#define mmTPC1_QM_PQ_STS1_2 0xE48108 + +#define mmTPC1_QM_PQ_STS1_3 0xE4810C + +#define mmTPC1_QM_CQ_CFG0_0 0xE48110 + +#define mmTPC1_QM_CQ_CFG0_1 0xE48114 + +#define mmTPC1_QM_CQ_CFG0_2 0xE48118 + +#define mmTPC1_QM_CQ_CFG0_3 0xE4811C + +#define mmTPC1_QM_CQ_CFG0_4 0xE48120 + +#define mmTPC1_QM_CQ_CFG1_0 0xE48124 + +#define mmTPC1_QM_CQ_CFG1_1 0xE48128 + +#define mmTPC1_QM_CQ_CFG1_2 0xE4812C + +#define mmTPC1_QM_CQ_CFG1_3 0xE48130 + +#define mmTPC1_QM_CQ_CFG1_4 0xE48134 + +#define mmTPC1_QM_CQ_ARUSER_31_11_0 0xE48138 + +#define mmTPC1_QM_CQ_ARUSER_31_11_1 0xE4813C + +#define mmTPC1_QM_CQ_ARUSER_31_11_2 0xE48140 + +#define mmTPC1_QM_CQ_ARUSER_31_11_3 0xE48144 + +#define mmTPC1_QM_CQ_ARUSER_31_11_4 0xE48148 + +#define mmTPC1_QM_CQ_STS0_0 0xE4814C + +#define mmTPC1_QM_CQ_STS0_1 0xE48150 + +#define mmTPC1_QM_CQ_STS0_2 0xE48154 + +#define mmTPC1_QM_CQ_STS0_3 0xE48158 + +#define mmTPC1_QM_CQ_STS0_4 0xE4815C + +#define mmTPC1_QM_CQ_STS1_0 0xE48160 + +#define mmTPC1_QM_CQ_STS1_1 0xE48164 + +#define mmTPC1_QM_CQ_STS1_2 0xE48168 + +#define mmTPC1_QM_CQ_STS1_3 0xE4816C + +#define mmTPC1_QM_CQ_STS1_4 0xE48170 + +#define mmTPC1_QM_CQ_PTR_LO_0 0xE48174 + +#define mmTPC1_QM_CQ_PTR_HI_0 0xE48178 + +#define mmTPC1_QM_CQ_TSIZE_0 0xE4817C + +#define mmTPC1_QM_CQ_CTL_0 0xE48180 + +#define mmTPC1_QM_CQ_PTR_LO_1 0xE48184 + +#define mmTPC1_QM_CQ_PTR_HI_1 0xE48188 + +#define mmTPC1_QM_CQ_TSIZE_1 0xE4818C + +#define mmTPC1_QM_CQ_CTL_1 0xE48190 + +#define mmTPC1_QM_CQ_PTR_LO_2 0xE48194 + +#define mmTPC1_QM_CQ_PTR_HI_2 0xE48198 + +#define mmTPC1_QM_CQ_TSIZE_2 0xE4819C + +#define mmTPC1_QM_CQ_CTL_2 0xE481A0 + +#define mmTPC1_QM_CQ_PTR_LO_3 0xE481A4 + +#define mmTPC1_QM_CQ_PTR_HI_3 0xE481A8 + +#define mmTPC1_QM_CQ_TSIZE_3 0xE481AC + +#define mmTPC1_QM_CQ_CTL_3 0xE481B0 + +#define mmTPC1_QM_CQ_PTR_LO_4 0xE481B4 + +#define mmTPC1_QM_CQ_PTR_HI_4 0xE481B8 + +#define mmTPC1_QM_CQ_TSIZE_4 0xE481BC + +#define mmTPC1_QM_CQ_CTL_4 0xE481C0 + +#define mmTPC1_QM_CQ_PTR_LO_STS_0 0xE481C4 + +#define mmTPC1_QM_CQ_PTR_LO_STS_1 0xE481C8 + +#define mmTPC1_QM_CQ_PTR_LO_STS_2 0xE481CC + +#define mmTPC1_QM_CQ_PTR_LO_STS_3 0xE481D0 + +#define mmTPC1_QM_CQ_PTR_LO_STS_4 0xE481D4 + +#define mmTPC1_QM_CQ_PTR_HI_STS_0 0xE481D8 + +#define mmTPC1_QM_CQ_PTR_HI_STS_1 0xE481DC + +#define mmTPC1_QM_CQ_PTR_HI_STS_2 0xE481E0 + +#define mmTPC1_QM_CQ_PTR_HI_STS_3 0xE481E4 + +#define mmTPC1_QM_CQ_PTR_HI_STS_4 0xE481E8 + +#define mmTPC1_QM_CQ_TSIZE_STS_0 0xE481EC + +#define mmTPC1_QM_CQ_TSIZE_STS_1 0xE481F0 + +#define mmTPC1_QM_CQ_TSIZE_STS_2 0xE481F4 + +#define mmTPC1_QM_CQ_TSIZE_STS_3 0xE481F8 + +#define mmTPC1_QM_CQ_TSIZE_STS_4 0xE481FC + +#define mmTPC1_QM_CQ_CTL_STS_0 0xE48200 + +#define mmTPC1_QM_CQ_CTL_STS_1 0xE48204 + +#define mmTPC1_QM_CQ_CTL_STS_2 0xE48208 + +#define mmTPC1_QM_CQ_CTL_STS_3 0xE4820C + +#define mmTPC1_QM_CQ_CTL_STS_4 0xE48210 + +#define mmTPC1_QM_CQ_IFIFO_CNT_0 0xE48214 + +#define mmTPC1_QM_CQ_IFIFO_CNT_1 0xE48218 + +#define mmTPC1_QM_CQ_IFIFO_CNT_2 0xE4821C + +#define mmTPC1_QM_CQ_IFIFO_CNT_3 0xE48220 + +#define mmTPC1_QM_CQ_IFIFO_CNT_4 0xE48224 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_0 0xE48228 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_1 0xE4822C + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_2 0xE48230 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_3 0xE48234 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_4 0xE48238 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_0 0xE4823C + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_1 0xE48240 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_2 0xE48244 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_3 0xE48248 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_4 0xE4824C + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_0 0xE48250 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_1 0xE48254 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_2 0xE48258 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_3 0xE4825C + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_4 0xE48260 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_0 0xE48264 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_1 0xE48268 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_2 0xE4826C + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_3 0xE48270 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_4 0xE48274 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_0 0xE48278 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_1 0xE4827C + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_2 0xE48280 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_3 0xE48284 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_4 0xE48288 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_0 0xE4828C + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_1 0xE48290 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_2 0xE48294 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_3 0xE48298 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_4 0xE4829C + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_0 0xE482A0 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_1 0xE482A4 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_2 0xE482A8 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_3 0xE482AC + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_4 0xE482B0 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_0 0xE482B4 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_1 0xE482B8 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_2 0xE482BC + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_3 0xE482C0 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_4 0xE482C4 + +#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_0 0xE482C8 + +#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_1 0xE482CC + +#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_2 0xE482D0 + +#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_3 0xE482D4 + +#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_4 0xE482D8 + +#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xE482E0 + +#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xE482E4 + +#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xE482E8 + +#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xE482EC + +#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xE482F0 + +#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xE482F4 + +#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xE482F8 + +#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xE482FC + +#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xE48300 + +#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xE48304 + +#define mmTPC1_QM_CP_FENCE0_RDATA_0 0xE48308 + +#define mmTPC1_QM_CP_FENCE0_RDATA_1 0xE4830C + +#define mmTPC1_QM_CP_FENCE0_RDATA_2 0xE48310 + +#define mmTPC1_QM_CP_FENCE0_RDATA_3 0xE48314 + +#define mmTPC1_QM_CP_FENCE0_RDATA_4 0xE48318 + +#define mmTPC1_QM_CP_FENCE1_RDATA_0 0xE4831C + +#define mmTPC1_QM_CP_FENCE1_RDATA_1 0xE48320 + +#define mmTPC1_QM_CP_FENCE1_RDATA_2 0xE48324 + +#define mmTPC1_QM_CP_FENCE1_RDATA_3 0xE48328 + +#define mmTPC1_QM_CP_FENCE1_RDATA_4 0xE4832C + +#define mmTPC1_QM_CP_FENCE2_RDATA_0 0xE48330 + +#define mmTPC1_QM_CP_FENCE2_RDATA_1 0xE48334 + +#define mmTPC1_QM_CP_FENCE2_RDATA_2 0xE48338 + +#define mmTPC1_QM_CP_FENCE2_RDATA_3 0xE4833C + +#define mmTPC1_QM_CP_FENCE2_RDATA_4 0xE48340 + +#define mmTPC1_QM_CP_FENCE3_RDATA_0 0xE48344 + +#define mmTPC1_QM_CP_FENCE3_RDATA_1 0xE48348 + +#define mmTPC1_QM_CP_FENCE3_RDATA_2 0xE4834C + +#define mmTPC1_QM_CP_FENCE3_RDATA_3 0xE48350 + +#define mmTPC1_QM_CP_FENCE3_RDATA_4 0xE48354 + +#define mmTPC1_QM_CP_FENCE0_CNT_0 0xE48358 + +#define mmTPC1_QM_CP_FENCE0_CNT_1 0xE4835C + +#define mmTPC1_QM_CP_FENCE0_CNT_2 0xE48360 + +#define mmTPC1_QM_CP_FENCE0_CNT_3 0xE48364 + +#define mmTPC1_QM_CP_FENCE0_CNT_4 0xE48368 + +#define mmTPC1_QM_CP_FENCE1_CNT_0 0xE4836C + +#define mmTPC1_QM_CP_FENCE1_CNT_1 0xE48370 + +#define mmTPC1_QM_CP_FENCE1_CNT_2 0xE48374 + +#define mmTPC1_QM_CP_FENCE1_CNT_3 0xE48378 + +#define mmTPC1_QM_CP_FENCE1_CNT_4 0xE4837C + +#define mmTPC1_QM_CP_FENCE2_CNT_0 0xE48380 + +#define mmTPC1_QM_CP_FENCE2_CNT_1 0xE48384 + +#define mmTPC1_QM_CP_FENCE2_CNT_2 0xE48388 + +#define mmTPC1_QM_CP_FENCE2_CNT_3 0xE4838C + +#define mmTPC1_QM_CP_FENCE2_CNT_4 0xE48390 + +#define mmTPC1_QM_CP_FENCE3_CNT_0 0xE48394 + +#define mmTPC1_QM_CP_FENCE3_CNT_1 0xE48398 + +#define mmTPC1_QM_CP_FENCE3_CNT_2 0xE4839C + +#define mmTPC1_QM_CP_FENCE3_CNT_3 0xE483A0 + +#define mmTPC1_QM_CP_FENCE3_CNT_4 0xE483A4 + +#define mmTPC1_QM_CP_STS_0 0xE483A8 + +#define mmTPC1_QM_CP_STS_1 0xE483AC + +#define mmTPC1_QM_CP_STS_2 0xE483B0 + +#define mmTPC1_QM_CP_STS_3 0xE483B4 + +#define mmTPC1_QM_CP_STS_4 0xE483B8 + +#define mmTPC1_QM_CP_CURRENT_INST_LO_0 0xE483BC + +#define mmTPC1_QM_CP_CURRENT_INST_LO_1 0xE483C0 + +#define mmTPC1_QM_CP_CURRENT_INST_LO_2 0xE483C4 + +#define mmTPC1_QM_CP_CURRENT_INST_LO_3 0xE483C8 + +#define mmTPC1_QM_CP_CURRENT_INST_LO_4 0xE483CC + +#define mmTPC1_QM_CP_CURRENT_INST_HI_0 0xE483D0 + +#define mmTPC1_QM_CP_CURRENT_INST_HI_1 0xE483D4 + +#define mmTPC1_QM_CP_CURRENT_INST_HI_2 0xE483D8 + +#define mmTPC1_QM_CP_CURRENT_INST_HI_3 0xE483DC + +#define mmTPC1_QM_CP_CURRENT_INST_HI_4 0xE483E0 + +#define mmTPC1_QM_CP_BARRIER_CFG_0 0xE483F4 + +#define mmTPC1_QM_CP_BARRIER_CFG_1 0xE483F8 + +#define mmTPC1_QM_CP_BARRIER_CFG_2 0xE483FC + +#define mmTPC1_QM_CP_BARRIER_CFG_3 0xE48400 + +#define mmTPC1_QM_CP_BARRIER_CFG_4 0xE48404 + +#define mmTPC1_QM_CP_DBG_0_0 0xE48408 + +#define mmTPC1_QM_CP_DBG_0_1 0xE4840C + +#define mmTPC1_QM_CP_DBG_0_2 0xE48410 + +#define mmTPC1_QM_CP_DBG_0_3 0xE48414 + +#define mmTPC1_QM_CP_DBG_0_4 0xE48418 + +#define mmTPC1_QM_CP_ARUSER_31_11_0 0xE4841C + +#define mmTPC1_QM_CP_ARUSER_31_11_1 0xE48420 + +#define mmTPC1_QM_CP_ARUSER_31_11_2 0xE48424 + +#define mmTPC1_QM_CP_ARUSER_31_11_3 0xE48428 + +#define mmTPC1_QM_CP_ARUSER_31_11_4 0xE4842C + +#define mmTPC1_QM_CP_AWUSER_31_11_0 0xE48430 + +#define mmTPC1_QM_CP_AWUSER_31_11_1 0xE48434 + +#define mmTPC1_QM_CP_AWUSER_31_11_2 0xE48438 + +#define mmTPC1_QM_CP_AWUSER_31_11_3 0xE4843C + +#define mmTPC1_QM_CP_AWUSER_31_11_4 0xE48440 + +#define mmTPC1_QM_ARB_CFG_0 0xE48A00 + +#define mmTPC1_QM_ARB_CHOISE_Q_PUSH 0xE48A04 + +#define mmTPC1_QM_ARB_WRR_WEIGHT_0 0xE48A08 + +#define mmTPC1_QM_ARB_WRR_WEIGHT_1 0xE48A0C + +#define mmTPC1_QM_ARB_WRR_WEIGHT_2 0xE48A10 + +#define mmTPC1_QM_ARB_WRR_WEIGHT_3 0xE48A14 + +#define mmTPC1_QM_ARB_CFG_1 0xE48A18 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_0 0xE48A20 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_1 0xE48A24 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_2 0xE48A28 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_3 0xE48A2C + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_4 0xE48A30 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_5 0xE48A34 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_6 0xE48A38 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_7 0xE48A3C + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_8 0xE48A40 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_9 0xE48A44 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_10 0xE48A48 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_11 0xE48A4C + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_12 0xE48A50 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_13 0xE48A54 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_14 0xE48A58 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_15 0xE48A5C + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_16 0xE48A60 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_17 0xE48A64 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_18 0xE48A68 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_19 0xE48A6C + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_20 0xE48A70 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_21 0xE48A74 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_22 0xE48A78 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_23 0xE48A7C + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_24 0xE48A80 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_25 0xE48A84 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_26 0xE48A88 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_27 0xE48A8C + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_28 0xE48A90 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_29 0xE48A94 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_30 0xE48A98 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_31 0xE48A9C + +#define mmTPC1_QM_ARB_MST_CRED_INC 0xE48AA0 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xE48AA4 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xE48AA8 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xE48AAC + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xE48AB0 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xE48AB4 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xE48AB8 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xE48ABC + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xE48AC0 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xE48AC4 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xE48AC8 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xE48ACC + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xE48AD0 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xE48AD4 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xE48AD8 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xE48ADC + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xE48AE0 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xE48AE4 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xE48AE8 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xE48AEC + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xE48AF0 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xE48AF4 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xE48AF8 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xE48AFC + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xE48B00 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xE48B04 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xE48B08 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xE48B0C + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xE48B10 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xE48B14 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xE48B18 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xE48B1C + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xE48B20 + +#define mmTPC1_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xE48B28 + +#define mmTPC1_QM_ARB_MST_SLAVE_EN 0xE48B2C + +#define mmTPC1_QM_ARB_MST_QUIET_PER 0xE48B34 + +#define mmTPC1_QM_ARB_SLV_CHOISE_WDT 0xE48B38 + +#define mmTPC1_QM_ARB_SLV_ID 0xE48B3C + +#define mmTPC1_QM_ARB_MSG_MAX_INFLIGHT 0xE48B44 + +#define mmTPC1_QM_ARB_MSG_AWUSER_31_11 0xE48B48 + +#define mmTPC1_QM_ARB_MSG_AWUSER_SEC_PROP 0xE48B4C + +#define mmTPC1_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xE48B50 + +#define mmTPC1_QM_ARB_BASE_LO 0xE48B54 + +#define mmTPC1_QM_ARB_BASE_HI 0xE48B58 + +#define mmTPC1_QM_ARB_STATE_STS 0xE48B80 + +#define mmTPC1_QM_ARB_CHOISE_FULLNESS_STS 0xE48B84 + +#define mmTPC1_QM_ARB_MSG_STS 0xE48B88 + +#define mmTPC1_QM_ARB_SLV_CHOISE_Q_HEAD 0xE48B8C + +#define mmTPC1_QM_ARB_ERR_CAUSE 0xE48B9C + +#define mmTPC1_QM_ARB_ERR_MSG_EN 0xE48BA0 + +#define mmTPC1_QM_ARB_ERR_STS_DRP 0xE48BA8 + +#define mmTPC1_QM_ARB_MST_CRED_STS_0 0xE48BB0 + +#define mmTPC1_QM_ARB_MST_CRED_STS_1 0xE48BB4 + +#define mmTPC1_QM_ARB_MST_CRED_STS_2 0xE48BB8 + +#define mmTPC1_QM_ARB_MST_CRED_STS_3 0xE48BBC + +#define mmTPC1_QM_ARB_MST_CRED_STS_4 0xE48BC0 + +#define mmTPC1_QM_ARB_MST_CRED_STS_5 0xE48BC4 + +#define mmTPC1_QM_ARB_MST_CRED_STS_6 0xE48BC8 + +#define mmTPC1_QM_ARB_MST_CRED_STS_7 0xE48BCC + +#define mmTPC1_QM_ARB_MST_CRED_STS_8 0xE48BD0 + +#define mmTPC1_QM_ARB_MST_CRED_STS_9 0xE48BD4 + +#define mmTPC1_QM_ARB_MST_CRED_STS_10 0xE48BD8 + +#define mmTPC1_QM_ARB_MST_CRED_STS_11 0xE48BDC + +#define mmTPC1_QM_ARB_MST_CRED_STS_12 0xE48BE0 + +#define mmTPC1_QM_ARB_MST_CRED_STS_13 0xE48BE4 + +#define mmTPC1_QM_ARB_MST_CRED_STS_14 0xE48BE8 + +#define mmTPC1_QM_ARB_MST_CRED_STS_15 0xE48BEC + +#define mmTPC1_QM_ARB_MST_CRED_STS_16 0xE48BF0 + +#define mmTPC1_QM_ARB_MST_CRED_STS_17 0xE48BF4 + +#define mmTPC1_QM_ARB_MST_CRED_STS_18 0xE48BF8 + +#define mmTPC1_QM_ARB_MST_CRED_STS_19 0xE48BFC + +#define mmTPC1_QM_ARB_MST_CRED_STS_20 0xE48C00 + +#define mmTPC1_QM_ARB_MST_CRED_STS_21 0xE48C04 + +#define mmTPC1_QM_ARB_MST_CRED_STS_22 0xE48C08 + +#define mmTPC1_QM_ARB_MST_CRED_STS_23 0xE48C0C + +#define mmTPC1_QM_ARB_MST_CRED_STS_24 0xE48C10 + +#define mmTPC1_QM_ARB_MST_CRED_STS_25 0xE48C14 + +#define mmTPC1_QM_ARB_MST_CRED_STS_26 0xE48C18 + +#define mmTPC1_QM_ARB_MST_CRED_STS_27 0xE48C1C + +#define mmTPC1_QM_ARB_MST_CRED_STS_28 0xE48C20 + +#define mmTPC1_QM_ARB_MST_CRED_STS_29 0xE48C24 + +#define mmTPC1_QM_ARB_MST_CRED_STS_30 0xE48C28 + +#define mmTPC1_QM_ARB_MST_CRED_STS_31 0xE48C2C + +#define mmTPC1_QM_CGM_CFG 0xE48C70 + +#define mmTPC1_QM_CGM_STS 0xE48C74 + +#define mmTPC1_QM_CGM_CFG1 0xE48C78 + +#define mmTPC1_QM_LOCAL_RANGE_BASE 0xE48C80 + +#define mmTPC1_QM_LOCAL_RANGE_SIZE 0xE48C84 + +#define mmTPC1_QM_CSMR_STRICT_PRIO_CFG 0xE48C90 + +#define mmTPC1_QM_HBW_RD_RATE_LIM_CFG_1 0xE48C94 + +#define mmTPC1_QM_LBW_WR_RATE_LIM_CFG_0 0xE48C98 + +#define mmTPC1_QM_LBW_WR_RATE_LIM_CFG_1 0xE48C9C + +#define mmTPC1_QM_HBW_RD_RATE_LIM_CFG_0 0xE48CA0 + +#define mmTPC1_QM_GLBL_AXCACHE 0xE48CA4 + +#define mmTPC1_QM_IND_GW_APB_CFG 0xE48CB0 + +#define mmTPC1_QM_IND_GW_APB_WDATA 0xE48CB4 + +#define mmTPC1_QM_IND_GW_APB_RDATA 0xE48CB8 + +#define mmTPC1_QM_IND_GW_APB_STATUS 0xE48CBC + +#define mmTPC1_QM_GLBL_ERR_ADDR_LO 0xE48CD0 + +#define mmTPC1_QM_GLBL_ERR_ADDR_HI 0xE48CD4 + +#define mmTPC1_QM_GLBL_ERR_WDATA 0xE48CD8 + +#define mmTPC1_QM_GLBL_MEM_INIT_BUSY 0xE48D00 + +#endif /* ASIC_REG_TPC1_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc2_cfg_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc2_cfg_regs.h new file mode 100644 index 000000000000..3e77c37952bc --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc2_cfg_regs.h @@ -0,0 +1,1226 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC2_CFG_REGS_H_ +#define ASIC_REG_TPC2_CFG_REGS_H_ + +/* + ***************************************** + * TPC2_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC2_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE86400 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE86404 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE86408 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE8640C + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE86410 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE86414 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE86418 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE8641C + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE86420 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE86424 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE86428 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE8642C + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE86430 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE86434 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE86438 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE8643C + +#define mmTPC2_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE86440 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE86444 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE86448 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE8644C + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE86450 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE86454 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE86458 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE8645C + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE86460 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE86464 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE86468 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE8646C + +#define mmTPC2_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE86470 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE86474 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE86478 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE8647C + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE86480 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE86484 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE86488 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE8648C + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE86490 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE86494 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE86498 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE8649C + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE864A0 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE864A4 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE864A8 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE864AC + +#define mmTPC2_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE864B0 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE864B4 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE864B8 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE864BC + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE864C0 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE864C4 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE864C8 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE864CC + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE864D0 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE864D4 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE864D8 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE864DC + +#define mmTPC2_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE864E0 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE864E4 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE864E8 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE864EC + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE864F0 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE864F4 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE864F8 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE864FC + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE86500 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE86504 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE86508 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE8650C + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE86510 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE86514 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE86518 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE8651C + +#define mmTPC2_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE86520 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE86524 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE86528 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE8652C + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE86530 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE86534 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE86538 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE8653C + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE86540 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE86544 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE86548 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE8654C + +#define mmTPC2_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE86550 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE86554 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE86558 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE8655C + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE86560 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE86564 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE86568 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE8656C + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE86570 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE86574 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE86578 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE8657C + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE86580 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE86584 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE86588 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE8658C + +#define mmTPC2_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE86590 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE86594 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE86598 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE8659C + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE865A0 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE865A4 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE865A8 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE865AC + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE865B0 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE865B4 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE865B8 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE865BC + +#define mmTPC2_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xE865C0 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xE865C4 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xE865C8 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xE865CC + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xE865D0 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xE865D4 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xE865D8 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xE865DC + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xE865E0 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xE865E4 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xE865E8 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xE865EC + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xE865F0 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xE865F4 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xE865F8 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xE865FC + +#define mmTPC2_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xE86600 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xE86604 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xE86608 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xE8660C + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xE86610 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xE86614 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xE86618 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xE8661C + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xE86620 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xE86624 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xE86628 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xE8662C + +#define mmTPC2_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xE86630 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xE86634 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xE86638 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xE8663C + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xE86640 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xE86644 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xE86648 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xE8664C + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xE86650 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xE86654 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xE86658 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xE8665C + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xE86660 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xE86664 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xE86668 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xE8666C + +#define mmTPC2_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xE86670 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xE86674 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xE86678 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xE8667C + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xE86680 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xE86684 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xE86688 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xE8668C + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xE86690 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xE86694 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xE86698 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xE8669C + +#define mmTPC2_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xE866A0 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xE866A4 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xE866A8 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xE866AC + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xE866B0 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xE866B4 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xE866B8 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xE866BC + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xE866C0 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xE866C4 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xE866C8 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xE866CC + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xE866D0 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xE866D4 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xE866D8 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xE866DC + +#define mmTPC2_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xE866E0 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xE866E4 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xE866E8 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xE866EC + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xE866F0 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xE866F4 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xE866F8 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xE866FC + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xE86700 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xE86704 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xE86708 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xE8670C + +#define mmTPC2_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xE86710 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xE86714 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xE86718 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xE8671C + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xE86720 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xE86724 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xE86728 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xE8672C + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xE86730 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xE86734 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xE86738 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xE8673C + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xE86740 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xE86744 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xE86748 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xE8674C + +#define mmTPC2_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xE86750 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xE86754 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xE86758 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xE8675C + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xE86760 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xE86764 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xE86768 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xE8676C + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xE86770 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xE86774 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xE86778 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xE8677C + +#define mmTPC2_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE86780 + +#define mmTPC2_CFG_KERNEL_SYNC_OBJECT_ADDR 0xE86784 + +#define mmTPC2_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE86788 + +#define mmTPC2_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE8678C + +#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_0 0xE86790 + +#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_0 0xE86794 + +#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_1 0xE86798 + +#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_1 0xE8679C + +#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_2 0xE867A0 + +#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_2 0xE867A4 + +#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_3 0xE867A8 + +#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_3 0xE867AC + +#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_4 0xE867B0 + +#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_4 0xE867B4 + +#define mmTPC2_CFG_KERNEL_KERNEL_CONFIG 0xE867B8 + +#define mmTPC2_CFG_KERNEL_KERNEL_ID 0xE867BC + +#define mmTPC2_CFG_KERNEL_SRF_0 0xE867C0 + +#define mmTPC2_CFG_KERNEL_SRF_1 0xE867C4 + +#define mmTPC2_CFG_KERNEL_SRF_2 0xE867C8 + +#define mmTPC2_CFG_KERNEL_SRF_3 0xE867CC + +#define mmTPC2_CFG_KERNEL_SRF_4 0xE867D0 + +#define mmTPC2_CFG_KERNEL_SRF_5 0xE867D4 + +#define mmTPC2_CFG_KERNEL_SRF_6 0xE867D8 + +#define mmTPC2_CFG_KERNEL_SRF_7 0xE867DC + +#define mmTPC2_CFG_KERNEL_SRF_8 0xE867E0 + +#define mmTPC2_CFG_KERNEL_SRF_9 0xE867E4 + +#define mmTPC2_CFG_KERNEL_SRF_10 0xE867E8 + +#define mmTPC2_CFG_KERNEL_SRF_11 0xE867EC + +#define mmTPC2_CFG_KERNEL_SRF_12 0xE867F0 + +#define mmTPC2_CFG_KERNEL_SRF_13 0xE867F4 + +#define mmTPC2_CFG_KERNEL_SRF_14 0xE867F8 + +#define mmTPC2_CFG_KERNEL_SRF_15 0xE867FC + +#define mmTPC2_CFG_KERNEL_SRF_16 0xE86800 + +#define mmTPC2_CFG_KERNEL_SRF_17 0xE86804 + +#define mmTPC2_CFG_KERNEL_SRF_18 0xE86808 + +#define mmTPC2_CFG_KERNEL_SRF_19 0xE8680C + +#define mmTPC2_CFG_KERNEL_SRF_20 0xE86810 + +#define mmTPC2_CFG_KERNEL_SRF_21 0xE86814 + +#define mmTPC2_CFG_KERNEL_SRF_22 0xE86818 + +#define mmTPC2_CFG_KERNEL_SRF_23 0xE8681C + +#define mmTPC2_CFG_KERNEL_SRF_24 0xE86820 + +#define mmTPC2_CFG_KERNEL_SRF_25 0xE86824 + +#define mmTPC2_CFG_KERNEL_SRF_26 0xE86828 + +#define mmTPC2_CFG_KERNEL_SRF_27 0xE8682C + +#define mmTPC2_CFG_KERNEL_SRF_28 0xE86830 + +#define mmTPC2_CFG_KERNEL_SRF_29 0xE86834 + +#define mmTPC2_CFG_KERNEL_SRF_30 0xE86838 + +#define mmTPC2_CFG_KERNEL_SRF_31 0xE8683C + +#define mmTPC2_CFG_ROUND_CSR 0xE868FC + +#define mmTPC2_CFG_PROT 0xE86900 + +#define mmTPC2_CFG_SEMAPHORE 0xE86908 + +#define mmTPC2_CFG_VFLAGS 0xE8690C + +#define mmTPC2_CFG_SFLAGS 0xE86910 + +#define mmTPC2_CFG_LFSR_POLYNOM 0xE86918 + +#define mmTPC2_CFG_STATUS 0xE8691C + +#define mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH 0xE86920 + +#define mmTPC2_CFG_CFG_SUBTRACT_VALUE 0xE86924 + +#define mmTPC2_CFG_SM_BASE_ADDRESS_HIGH 0xE8692C + +#define mmTPC2_CFG_TPC_CMD 0xE86930 + +#define mmTPC2_CFG_TPC_EXECUTE 0xE86938 + +#define mmTPC2_CFG_TPC_STALL 0xE8693C + +#define mmTPC2_CFG_ICACHE_BASE_ADDERESS_LOW 0xE86940 + +#define mmTPC2_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE86944 + +#define mmTPC2_CFG_RD_RATE_LIMIT 0xE86948 + +#define mmTPC2_CFG_WR_RATE_LIMIT 0xE86950 + +#define mmTPC2_CFG_MSS_CONFIG 0xE86954 + +#define mmTPC2_CFG_TPC_INTR_CAUSE 0xE86958 + +#define mmTPC2_CFG_TPC_INTR_MASK 0xE8695C + +#define mmTPC2_CFG_WQ_CREDITS 0xE86960 + +#define mmTPC2_CFG_ARUSER_LO 0xE86964 + +#define mmTPC2_CFG_ARUSER_HI 0xE86968 + +#define mmTPC2_CFG_AWUSER_LO 0xE8696C + +#define mmTPC2_CFG_AWUSER_HI 0xE86970 + +#define mmTPC2_CFG_OPCODE_EXEC 0xE86974 + +#define mmTPC2_CFG_LUT_FUNC32_BASE_ADDR_LO 0xE86978 + +#define mmTPC2_CFG_LUT_FUNC32_BASE_ADDR_HI 0xE8697C + +#define mmTPC2_CFG_LUT_FUNC64_BASE_ADDR_LO 0xE86980 + +#define mmTPC2_CFG_LUT_FUNC64_BASE_ADDR_HI 0xE86984 + +#define mmTPC2_CFG_LUT_FUNC128_BASE_ADDR_LO 0xE86988 + +#define mmTPC2_CFG_LUT_FUNC128_BASE_ADDR_HI 0xE8698C + +#define mmTPC2_CFG_LUT_FUNC256_BASE_ADDR_LO 0xE86990 + +#define mmTPC2_CFG_LUT_FUNC256_BASE_ADDR_HI 0xE86994 + +#define mmTPC2_CFG_TSB_CFG_MAX_SIZE 0xE86998 + +#define mmTPC2_CFG_TSB_CFG 0xE8699C + +#define mmTPC2_CFG_DBGMEM_ADD 0xE869A0 + +#define mmTPC2_CFG_DBGMEM_DATA_WR 0xE869A4 + +#define mmTPC2_CFG_DBGMEM_DATA_RD 0xE869A8 + +#define mmTPC2_CFG_DBGMEM_CTRL 0xE869AC + +#define mmTPC2_CFG_DBGMEM_RC 0xE869B0 + +#define mmTPC2_CFG_TSB_INFLIGHT_CNTR 0xE869B4 + +#define mmTPC2_CFG_WQ_INFLIGHT_CNTR 0xE869B8 + +#define mmTPC2_CFG_WQ_LBW_TOTAL_CNTR 0xE869BC + +#define mmTPC2_CFG_WQ_HBW_TOTAL_CNTR 0xE869C0 + +#define mmTPC2_CFG_IRQ_OCCOUPY_CNTR 0xE869C4 + +#define mmTPC2_CFG_FUNC_MBIST_CNTRL 0xE869D0 + +#define mmTPC2_CFG_FUNC_MBIST_PAT 0xE869D4 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_0 0xE869D8 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_1 0xE869DC + +#define mmTPC2_CFG_FUNC_MBIST_MEM_2 0xE869E0 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_3 0xE869E4 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_4 0xE869E8 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_5 0xE869EC + +#define mmTPC2_CFG_FUNC_MBIST_MEM_6 0xE869F0 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_7 0xE869F4 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_8 0xE869F8 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_9 0xE869FC + +#define mmTPC2_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE86A00 + +#define mmTPC2_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE86A04 + +#define mmTPC2_CFG_QM_TENSOR_0_PADDING_VALUE 0xE86A08 + +#define mmTPC2_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE86A0C + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE86A10 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE86A14 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE86A18 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE86A1C + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE86A20 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE86A24 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE86A28 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE86A2C + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE86A30 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE86A34 + +#define mmTPC2_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE86A38 + +#define mmTPC2_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE86A3C + +#define mmTPC2_CFG_QM_TENSOR_1_PADDING_VALUE 0xE86A40 + +#define mmTPC2_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE86A44 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE86A48 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE86A4C + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE86A50 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE86A54 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE86A58 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE86A5C + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE86A60 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE86A64 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE86A68 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE86A6C + +#define mmTPC2_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE86A70 + +#define mmTPC2_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE86A74 + +#define mmTPC2_CFG_QM_TENSOR_2_PADDING_VALUE 0xE86A78 + +#define mmTPC2_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE86A7C + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE86A80 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE86A84 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE86A88 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE86A8C + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE86A90 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE86A94 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE86A98 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE86A9C + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE86AA0 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE86AA4 + +#define mmTPC2_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE86AA8 + +#define mmTPC2_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE86AAC + +#define mmTPC2_CFG_QM_TENSOR_3_PADDING_VALUE 0xE86AB0 + +#define mmTPC2_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE86AB4 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE86AB8 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE86ABC + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE86AC0 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE86AC4 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE86AC8 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE86ACC + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE86AD0 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE86AD4 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE86AD8 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE86ADC + +#define mmTPC2_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE86AE0 + +#define mmTPC2_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE86AE4 + +#define mmTPC2_CFG_QM_TENSOR_4_PADDING_VALUE 0xE86AE8 + +#define mmTPC2_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE86AEC + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE86AF0 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE86AF4 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE86AF8 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE86AFC + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE86B00 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE86B04 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE86B08 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE86B0C + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE86B10 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE86B14 + +#define mmTPC2_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE86B18 + +#define mmTPC2_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE86B1C + +#define mmTPC2_CFG_QM_TENSOR_5_PADDING_VALUE 0xE86B20 + +#define mmTPC2_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE86B24 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE86B28 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE86B2C + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE86B30 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE86B34 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE86B38 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE86B3C + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE86B40 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE86B44 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE86B48 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE86B4C + +#define mmTPC2_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE86B50 + +#define mmTPC2_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE86B54 + +#define mmTPC2_CFG_QM_TENSOR_6_PADDING_VALUE 0xE86B58 + +#define mmTPC2_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE86B5C + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE86B60 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE86B64 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE86B68 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE86B6C + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE86B70 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE86B74 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE86B78 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE86B7C + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE86B80 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE86B84 + +#define mmTPC2_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE86B88 + +#define mmTPC2_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE86B8C + +#define mmTPC2_CFG_QM_TENSOR_7_PADDING_VALUE 0xE86B90 + +#define mmTPC2_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE86B94 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE86B98 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE86B9C + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE86BA0 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE86BA4 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE86BA8 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE86BAC + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE86BB0 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE86BB4 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE86BB8 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE86BBC + +#define mmTPC2_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xE86BC0 + +#define mmTPC2_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xE86BC4 + +#define mmTPC2_CFG_QM_TENSOR_8_PADDING_VALUE 0xE86BC8 + +#define mmTPC2_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xE86BCC + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_0_SIZE 0xE86BD0 + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xE86BD4 + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_1_SIZE 0xE86BD8 + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xE86BDC + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_2_SIZE 0xE86BE0 + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xE86BE4 + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_3_SIZE 0xE86BE8 + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xE86BEC + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_4_SIZE 0xE86BF0 + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xE86BF4 + +#define mmTPC2_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xE86BF8 + +#define mmTPC2_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xE86BFC + +#define mmTPC2_CFG_QM_TENSOR_9_PADDING_VALUE 0xE86C00 + +#define mmTPC2_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xE86C04 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_0_SIZE 0xE86C08 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xE86C0C + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_1_SIZE 0xE86C10 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xE86C14 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_2_SIZE 0xE86C18 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xE86C1C + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_3_SIZE 0xE86C20 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xE86C24 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_4_SIZE 0xE86C28 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xE86C2C + +#define mmTPC2_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xE86C30 + +#define mmTPC2_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xE86C34 + +#define mmTPC2_CFG_QM_TENSOR_10_PADDING_VALUE 0xE86C38 + +#define mmTPC2_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xE86C3C + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_0_SIZE 0xE86C40 + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xE86C44 + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_1_SIZE 0xE86C48 + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xE86C4C + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_2_SIZE 0xE86C50 + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xE86C54 + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_3_SIZE 0xE86C58 + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xE86C5C + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_4_SIZE 0xE86C60 + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xE86C64 + +#define mmTPC2_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xE86C68 + +#define mmTPC2_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xE86C6C + +#define mmTPC2_CFG_QM_TENSOR_11_PADDING_VALUE 0xE86C70 + +#define mmTPC2_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xE86C74 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_0_SIZE 0xE86C78 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xE86C7C + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_1_SIZE 0xE86C80 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xE86C84 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_2_SIZE 0xE86C88 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xE86C8C + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_3_SIZE 0xE86C90 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xE86C94 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_4_SIZE 0xE86C98 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xE86C9C + +#define mmTPC2_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xE86CA0 + +#define mmTPC2_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xE86CA4 + +#define mmTPC2_CFG_QM_TENSOR_12_PADDING_VALUE 0xE86CA8 + +#define mmTPC2_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xE86CAC + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_0_SIZE 0xE86CB0 + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xE86CB4 + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_1_SIZE 0xE86CB8 + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xE86CBC + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_2_SIZE 0xE86CC0 + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xE86CC4 + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_3_SIZE 0xE86CC8 + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xE86CCC + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_4_SIZE 0xE86CD0 + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xE86CD4 + +#define mmTPC2_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xE86CD8 + +#define mmTPC2_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xE86CDC + +#define mmTPC2_CFG_QM_TENSOR_13_PADDING_VALUE 0xE86CE0 + +#define mmTPC2_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xE86CE4 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_0_SIZE 0xE86CE8 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xE86CEC + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_1_SIZE 0xE86CF0 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xE86CF4 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_2_SIZE 0xE86CF8 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xE86CFC + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_3_SIZE 0xE86D00 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xE86D04 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_4_SIZE 0xE86D08 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xE86D0C + +#define mmTPC2_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xE86D10 + +#define mmTPC2_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xE86D14 + +#define mmTPC2_CFG_QM_TENSOR_14_PADDING_VALUE 0xE86D18 + +#define mmTPC2_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xE86D1C + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_0_SIZE 0xE86D20 + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xE86D24 + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_1_SIZE 0xE86D28 + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xE86D2C + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_2_SIZE 0xE86D30 + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xE86D34 + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_3_SIZE 0xE86D38 + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xE86D3C + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_4_SIZE 0xE86D40 + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xE86D44 + +#define mmTPC2_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xE86D48 + +#define mmTPC2_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xE86D4C + +#define mmTPC2_CFG_QM_TENSOR_15_PADDING_VALUE 0xE86D50 + +#define mmTPC2_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xE86D54 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_0_SIZE 0xE86D58 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xE86D5C + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_1_SIZE 0xE86D60 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xE86D64 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_2_SIZE 0xE86D68 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xE86D6C + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_3_SIZE 0xE86D70 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xE86D74 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_4_SIZE 0xE86D78 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xE86D7C + +#define mmTPC2_CFG_QM_SYNC_OBJECT_MESSAGE 0xE86D80 + +#define mmTPC2_CFG_QM_SYNC_OBJECT_ADDR 0xE86D84 + +#define mmTPC2_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE86D88 + +#define mmTPC2_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE86D8C + +#define mmTPC2_CFG_QM_TID_BASE_DIM_0 0xE86D90 + +#define mmTPC2_CFG_QM_TID_SIZE_DIM_0 0xE86D94 + +#define mmTPC2_CFG_QM_TID_BASE_DIM_1 0xE86D98 + +#define mmTPC2_CFG_QM_TID_SIZE_DIM_1 0xE86D9C + +#define mmTPC2_CFG_QM_TID_BASE_DIM_2 0xE86DA0 + +#define mmTPC2_CFG_QM_TID_SIZE_DIM_2 0xE86DA4 + +#define mmTPC2_CFG_QM_TID_BASE_DIM_3 0xE86DA8 + +#define mmTPC2_CFG_QM_TID_SIZE_DIM_3 0xE86DAC + +#define mmTPC2_CFG_QM_TID_BASE_DIM_4 0xE86DB0 + +#define mmTPC2_CFG_QM_TID_SIZE_DIM_4 0xE86DB4 + +#define mmTPC2_CFG_QM_KERNEL_CONFIG 0xE86DB8 + +#define mmTPC2_CFG_QM_KERNEL_ID 0xE86DBC + +#define mmTPC2_CFG_QM_SRF_0 0xE86DC0 + +#define mmTPC2_CFG_QM_SRF_1 0xE86DC4 + +#define mmTPC2_CFG_QM_SRF_2 0xE86DC8 + +#define mmTPC2_CFG_QM_SRF_3 0xE86DCC + +#define mmTPC2_CFG_QM_SRF_4 0xE86DD0 + +#define mmTPC2_CFG_QM_SRF_5 0xE86DD4 + +#define mmTPC2_CFG_QM_SRF_6 0xE86DD8 + +#define mmTPC2_CFG_QM_SRF_7 0xE86DDC + +#define mmTPC2_CFG_QM_SRF_8 0xE86DE0 + +#define mmTPC2_CFG_QM_SRF_9 0xE86DE4 + +#define mmTPC2_CFG_QM_SRF_10 0xE86DE8 + +#define mmTPC2_CFG_QM_SRF_11 0xE86DEC + +#define mmTPC2_CFG_QM_SRF_12 0xE86DF0 + +#define mmTPC2_CFG_QM_SRF_13 0xE86DF4 + +#define mmTPC2_CFG_QM_SRF_14 0xE86DF8 + +#define mmTPC2_CFG_QM_SRF_15 0xE86DFC + +#define mmTPC2_CFG_QM_SRF_16 0xE86E00 + +#define mmTPC2_CFG_QM_SRF_17 0xE86E04 + +#define mmTPC2_CFG_QM_SRF_18 0xE86E08 + +#define mmTPC2_CFG_QM_SRF_19 0xE86E0C + +#define mmTPC2_CFG_QM_SRF_20 0xE86E10 + +#define mmTPC2_CFG_QM_SRF_21 0xE86E14 + +#define mmTPC2_CFG_QM_SRF_22 0xE86E18 + +#define mmTPC2_CFG_QM_SRF_23 0xE86E1C + +#define mmTPC2_CFG_QM_SRF_24 0xE86E20 + +#define mmTPC2_CFG_QM_SRF_25 0xE86E24 + +#define mmTPC2_CFG_QM_SRF_26 0xE86E28 + +#define mmTPC2_CFG_QM_SRF_27 0xE86E2C + +#define mmTPC2_CFG_QM_SRF_28 0xE86E30 + +#define mmTPC2_CFG_QM_SRF_29 0xE86E34 + +#define mmTPC2_CFG_QM_SRF_30 0xE86E38 + +#define mmTPC2_CFG_QM_SRF_31 0xE86E3C + +#endif /* ASIC_REG_TPC2_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc2_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc2_qm_regs.h new file mode 100644 index 000000000000..2919e2fa58f8 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc2_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC2_QM_REGS_H_ +#define ASIC_REG_TPC2_QM_REGS_H_ + +/* + ***************************************** + * TPC2_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC2_QM_GLBL_CFG0 0xE88000 + +#define mmTPC2_QM_GLBL_CFG1 0xE88004 + +#define mmTPC2_QM_GLBL_PROT 0xE88008 + +#define mmTPC2_QM_GLBL_ERR_CFG 0xE8800C + +#define mmTPC2_QM_GLBL_SECURE_PROPS_0 0xE88010 + +#define mmTPC2_QM_GLBL_SECURE_PROPS_1 0xE88014 + +#define mmTPC2_QM_GLBL_SECURE_PROPS_2 0xE88018 + +#define mmTPC2_QM_GLBL_SECURE_PROPS_3 0xE8801C + +#define mmTPC2_QM_GLBL_SECURE_PROPS_4 0xE88020 + +#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_0 0xE88024 + +#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_1 0xE88028 + +#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_2 0xE8802C + +#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_3 0xE88030 + +#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_4 0xE88034 + +#define mmTPC2_QM_GLBL_STS0 0xE88038 + +#define mmTPC2_QM_GLBL_STS1_0 0xE88040 + +#define mmTPC2_QM_GLBL_STS1_1 0xE88044 + +#define mmTPC2_QM_GLBL_STS1_2 0xE88048 + +#define mmTPC2_QM_GLBL_STS1_3 0xE8804C + +#define mmTPC2_QM_GLBL_STS1_4 0xE88050 + +#define mmTPC2_QM_GLBL_MSG_EN_0 0xE88054 + +#define mmTPC2_QM_GLBL_MSG_EN_1 0xE88058 + +#define mmTPC2_QM_GLBL_MSG_EN_2 0xE8805C + +#define mmTPC2_QM_GLBL_MSG_EN_3 0xE88060 + +#define mmTPC2_QM_GLBL_MSG_EN_4 0xE88068 + +#define mmTPC2_QM_PQ_BASE_LO_0 0xE88070 + +#define mmTPC2_QM_PQ_BASE_LO_1 0xE88074 + +#define mmTPC2_QM_PQ_BASE_LO_2 0xE88078 + +#define mmTPC2_QM_PQ_BASE_LO_3 0xE8807C + +#define mmTPC2_QM_PQ_BASE_HI_0 0xE88080 + +#define mmTPC2_QM_PQ_BASE_HI_1 0xE88084 + +#define mmTPC2_QM_PQ_BASE_HI_2 0xE88088 + +#define mmTPC2_QM_PQ_BASE_HI_3 0xE8808C + +#define mmTPC2_QM_PQ_SIZE_0 0xE88090 + +#define mmTPC2_QM_PQ_SIZE_1 0xE88094 + +#define mmTPC2_QM_PQ_SIZE_2 0xE88098 + +#define mmTPC2_QM_PQ_SIZE_3 0xE8809C + +#define mmTPC2_QM_PQ_PI_0 0xE880A0 + +#define mmTPC2_QM_PQ_PI_1 0xE880A4 + +#define mmTPC2_QM_PQ_PI_2 0xE880A8 + +#define mmTPC2_QM_PQ_PI_3 0xE880AC + +#define mmTPC2_QM_PQ_CI_0 0xE880B0 + +#define mmTPC2_QM_PQ_CI_1 0xE880B4 + +#define mmTPC2_QM_PQ_CI_2 0xE880B8 + +#define mmTPC2_QM_PQ_CI_3 0xE880BC + +#define mmTPC2_QM_PQ_CFG0_0 0xE880C0 + +#define mmTPC2_QM_PQ_CFG0_1 0xE880C4 + +#define mmTPC2_QM_PQ_CFG0_2 0xE880C8 + +#define mmTPC2_QM_PQ_CFG0_3 0xE880CC + +#define mmTPC2_QM_PQ_CFG1_0 0xE880D0 + +#define mmTPC2_QM_PQ_CFG1_1 0xE880D4 + +#define mmTPC2_QM_PQ_CFG1_2 0xE880D8 + +#define mmTPC2_QM_PQ_CFG1_3 0xE880DC + +#define mmTPC2_QM_PQ_ARUSER_31_11_0 0xE880E0 + +#define mmTPC2_QM_PQ_ARUSER_31_11_1 0xE880E4 + +#define mmTPC2_QM_PQ_ARUSER_31_11_2 0xE880E8 + +#define mmTPC2_QM_PQ_ARUSER_31_11_3 0xE880EC + +#define mmTPC2_QM_PQ_STS0_0 0xE880F0 + +#define mmTPC2_QM_PQ_STS0_1 0xE880F4 + +#define mmTPC2_QM_PQ_STS0_2 0xE880F8 + +#define mmTPC2_QM_PQ_STS0_3 0xE880FC + +#define mmTPC2_QM_PQ_STS1_0 0xE88100 + +#define mmTPC2_QM_PQ_STS1_1 0xE88104 + +#define mmTPC2_QM_PQ_STS1_2 0xE88108 + +#define mmTPC2_QM_PQ_STS1_3 0xE8810C + +#define mmTPC2_QM_CQ_CFG0_0 0xE88110 + +#define mmTPC2_QM_CQ_CFG0_1 0xE88114 + +#define mmTPC2_QM_CQ_CFG0_2 0xE88118 + +#define mmTPC2_QM_CQ_CFG0_3 0xE8811C + +#define mmTPC2_QM_CQ_CFG0_4 0xE88120 + +#define mmTPC2_QM_CQ_CFG1_0 0xE88124 + +#define mmTPC2_QM_CQ_CFG1_1 0xE88128 + +#define mmTPC2_QM_CQ_CFG1_2 0xE8812C + +#define mmTPC2_QM_CQ_CFG1_3 0xE88130 + +#define mmTPC2_QM_CQ_CFG1_4 0xE88134 + +#define mmTPC2_QM_CQ_ARUSER_31_11_0 0xE88138 + +#define mmTPC2_QM_CQ_ARUSER_31_11_1 0xE8813C + +#define mmTPC2_QM_CQ_ARUSER_31_11_2 0xE88140 + +#define mmTPC2_QM_CQ_ARUSER_31_11_3 0xE88144 + +#define mmTPC2_QM_CQ_ARUSER_31_11_4 0xE88148 + +#define mmTPC2_QM_CQ_STS0_0 0xE8814C + +#define mmTPC2_QM_CQ_STS0_1 0xE88150 + +#define mmTPC2_QM_CQ_STS0_2 0xE88154 + +#define mmTPC2_QM_CQ_STS0_3 0xE88158 + +#define mmTPC2_QM_CQ_STS0_4 0xE8815C + +#define mmTPC2_QM_CQ_STS1_0 0xE88160 + +#define mmTPC2_QM_CQ_STS1_1 0xE88164 + +#define mmTPC2_QM_CQ_STS1_2 0xE88168 + +#define mmTPC2_QM_CQ_STS1_3 0xE8816C + +#define mmTPC2_QM_CQ_STS1_4 0xE88170 + +#define mmTPC2_QM_CQ_PTR_LO_0 0xE88174 + +#define mmTPC2_QM_CQ_PTR_HI_0 0xE88178 + +#define mmTPC2_QM_CQ_TSIZE_0 0xE8817C + +#define mmTPC2_QM_CQ_CTL_0 0xE88180 + +#define mmTPC2_QM_CQ_PTR_LO_1 0xE88184 + +#define mmTPC2_QM_CQ_PTR_HI_1 0xE88188 + +#define mmTPC2_QM_CQ_TSIZE_1 0xE8818C + +#define mmTPC2_QM_CQ_CTL_1 0xE88190 + +#define mmTPC2_QM_CQ_PTR_LO_2 0xE88194 + +#define mmTPC2_QM_CQ_PTR_HI_2 0xE88198 + +#define mmTPC2_QM_CQ_TSIZE_2 0xE8819C + +#define mmTPC2_QM_CQ_CTL_2 0xE881A0 + +#define mmTPC2_QM_CQ_PTR_LO_3 0xE881A4 + +#define mmTPC2_QM_CQ_PTR_HI_3 0xE881A8 + +#define mmTPC2_QM_CQ_TSIZE_3 0xE881AC + +#define mmTPC2_QM_CQ_CTL_3 0xE881B0 + +#define mmTPC2_QM_CQ_PTR_LO_4 0xE881B4 + +#define mmTPC2_QM_CQ_PTR_HI_4 0xE881B8 + +#define mmTPC2_QM_CQ_TSIZE_4 0xE881BC + +#define mmTPC2_QM_CQ_CTL_4 0xE881C0 + +#define mmTPC2_QM_CQ_PTR_LO_STS_0 0xE881C4 + +#define mmTPC2_QM_CQ_PTR_LO_STS_1 0xE881C8 + +#define mmTPC2_QM_CQ_PTR_LO_STS_2 0xE881CC + +#define mmTPC2_QM_CQ_PTR_LO_STS_3 0xE881D0 + +#define mmTPC2_QM_CQ_PTR_LO_STS_4 0xE881D4 + +#define mmTPC2_QM_CQ_PTR_HI_STS_0 0xE881D8 + +#define mmTPC2_QM_CQ_PTR_HI_STS_1 0xE881DC + +#define mmTPC2_QM_CQ_PTR_HI_STS_2 0xE881E0 + +#define mmTPC2_QM_CQ_PTR_HI_STS_3 0xE881E4 + +#define mmTPC2_QM_CQ_PTR_HI_STS_4 0xE881E8 + +#define mmTPC2_QM_CQ_TSIZE_STS_0 0xE881EC + +#define mmTPC2_QM_CQ_TSIZE_STS_1 0xE881F0 + +#define mmTPC2_QM_CQ_TSIZE_STS_2 0xE881F4 + +#define mmTPC2_QM_CQ_TSIZE_STS_3 0xE881F8 + +#define mmTPC2_QM_CQ_TSIZE_STS_4 0xE881FC + +#define mmTPC2_QM_CQ_CTL_STS_0 0xE88200 + +#define mmTPC2_QM_CQ_CTL_STS_1 0xE88204 + +#define mmTPC2_QM_CQ_CTL_STS_2 0xE88208 + +#define mmTPC2_QM_CQ_CTL_STS_3 0xE8820C + +#define mmTPC2_QM_CQ_CTL_STS_4 0xE88210 + +#define mmTPC2_QM_CQ_IFIFO_CNT_0 0xE88214 + +#define mmTPC2_QM_CQ_IFIFO_CNT_1 0xE88218 + +#define mmTPC2_QM_CQ_IFIFO_CNT_2 0xE8821C + +#define mmTPC2_QM_CQ_IFIFO_CNT_3 0xE88220 + +#define mmTPC2_QM_CQ_IFIFO_CNT_4 0xE88224 + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_0 0xE88228 + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_1 0xE8822C + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_2 0xE88230 + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_3 0xE88234 + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_4 0xE88238 + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_0 0xE8823C + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_1 0xE88240 + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_2 0xE88244 + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_3 0xE88248 + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_4 0xE8824C + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_0 0xE88250 + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_1 0xE88254 + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_2 0xE88258 + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_3 0xE8825C + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_4 0xE88260 + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_0 0xE88264 + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_1 0xE88268 + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_2 0xE8826C + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_3 0xE88270 + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_4 0xE88274 + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_0 0xE88278 + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_1 0xE8827C + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_2 0xE88280 + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_3 0xE88284 + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_4 0xE88288 + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_0 0xE8828C + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_1 0xE88290 + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_2 0xE88294 + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_3 0xE88298 + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_4 0xE8829C + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_0 0xE882A0 + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_1 0xE882A4 + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_2 0xE882A8 + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_3 0xE882AC + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_4 0xE882B0 + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_0 0xE882B4 + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_1 0xE882B8 + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_2 0xE882BC + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_3 0xE882C0 + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_4 0xE882C4 + +#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_0 0xE882C8 + +#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_1 0xE882CC + +#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_2 0xE882D0 + +#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_3 0xE882D4 + +#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_4 0xE882D8 + +#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xE882E0 + +#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xE882E4 + +#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xE882E8 + +#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xE882EC + +#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xE882F0 + +#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xE882F4 + +#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xE882F8 + +#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xE882FC + +#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xE88300 + +#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xE88304 + +#define mmTPC2_QM_CP_FENCE0_RDATA_0 0xE88308 + +#define mmTPC2_QM_CP_FENCE0_RDATA_1 0xE8830C + +#define mmTPC2_QM_CP_FENCE0_RDATA_2 0xE88310 + +#define mmTPC2_QM_CP_FENCE0_RDATA_3 0xE88314 + +#define mmTPC2_QM_CP_FENCE0_RDATA_4 0xE88318 + +#define mmTPC2_QM_CP_FENCE1_RDATA_0 0xE8831C + +#define mmTPC2_QM_CP_FENCE1_RDATA_1 0xE88320 + +#define mmTPC2_QM_CP_FENCE1_RDATA_2 0xE88324 + +#define mmTPC2_QM_CP_FENCE1_RDATA_3 0xE88328 + +#define mmTPC2_QM_CP_FENCE1_RDATA_4 0xE8832C + +#define mmTPC2_QM_CP_FENCE2_RDATA_0 0xE88330 + +#define mmTPC2_QM_CP_FENCE2_RDATA_1 0xE88334 + +#define mmTPC2_QM_CP_FENCE2_RDATA_2 0xE88338 + +#define mmTPC2_QM_CP_FENCE2_RDATA_3 0xE8833C + +#define mmTPC2_QM_CP_FENCE2_RDATA_4 0xE88340 + +#define mmTPC2_QM_CP_FENCE3_RDATA_0 0xE88344 + +#define mmTPC2_QM_CP_FENCE3_RDATA_1 0xE88348 + +#define mmTPC2_QM_CP_FENCE3_RDATA_2 0xE8834C + +#define mmTPC2_QM_CP_FENCE3_RDATA_3 0xE88350 + +#define mmTPC2_QM_CP_FENCE3_RDATA_4 0xE88354 + +#define mmTPC2_QM_CP_FENCE0_CNT_0 0xE88358 + +#define mmTPC2_QM_CP_FENCE0_CNT_1 0xE8835C + +#define mmTPC2_QM_CP_FENCE0_CNT_2 0xE88360 + +#define mmTPC2_QM_CP_FENCE0_CNT_3 0xE88364 + +#define mmTPC2_QM_CP_FENCE0_CNT_4 0xE88368 + +#define mmTPC2_QM_CP_FENCE1_CNT_0 0xE8836C + +#define mmTPC2_QM_CP_FENCE1_CNT_1 0xE88370 + +#define mmTPC2_QM_CP_FENCE1_CNT_2 0xE88374 + +#define mmTPC2_QM_CP_FENCE1_CNT_3 0xE88378 + +#define mmTPC2_QM_CP_FENCE1_CNT_4 0xE8837C + +#define mmTPC2_QM_CP_FENCE2_CNT_0 0xE88380 + +#define mmTPC2_QM_CP_FENCE2_CNT_1 0xE88384 + +#define mmTPC2_QM_CP_FENCE2_CNT_2 0xE88388 + +#define mmTPC2_QM_CP_FENCE2_CNT_3 0xE8838C + +#define mmTPC2_QM_CP_FENCE2_CNT_4 0xE88390 + +#define mmTPC2_QM_CP_FENCE3_CNT_0 0xE88394 + +#define mmTPC2_QM_CP_FENCE3_CNT_1 0xE88398 + +#define mmTPC2_QM_CP_FENCE3_CNT_2 0xE8839C + +#define mmTPC2_QM_CP_FENCE3_CNT_3 0xE883A0 + +#define mmTPC2_QM_CP_FENCE3_CNT_4 0xE883A4 + +#define mmTPC2_QM_CP_STS_0 0xE883A8 + +#define mmTPC2_QM_CP_STS_1 0xE883AC + +#define mmTPC2_QM_CP_STS_2 0xE883B0 + +#define mmTPC2_QM_CP_STS_3 0xE883B4 + +#define mmTPC2_QM_CP_STS_4 0xE883B8 + +#define mmTPC2_QM_CP_CURRENT_INST_LO_0 0xE883BC + +#define mmTPC2_QM_CP_CURRENT_INST_LO_1 0xE883C0 + +#define mmTPC2_QM_CP_CURRENT_INST_LO_2 0xE883C4 + +#define mmTPC2_QM_CP_CURRENT_INST_LO_3 0xE883C8 + +#define mmTPC2_QM_CP_CURRENT_INST_LO_4 0xE883CC + +#define mmTPC2_QM_CP_CURRENT_INST_HI_0 0xE883D0 + +#define mmTPC2_QM_CP_CURRENT_INST_HI_1 0xE883D4 + +#define mmTPC2_QM_CP_CURRENT_INST_HI_2 0xE883D8 + +#define mmTPC2_QM_CP_CURRENT_INST_HI_3 0xE883DC + +#define mmTPC2_QM_CP_CURRENT_INST_HI_4 0xE883E0 + +#define mmTPC2_QM_CP_BARRIER_CFG_0 0xE883F4 + +#define mmTPC2_QM_CP_BARRIER_CFG_1 0xE883F8 + +#define mmTPC2_QM_CP_BARRIER_CFG_2 0xE883FC + +#define mmTPC2_QM_CP_BARRIER_CFG_3 0xE88400 + +#define mmTPC2_QM_CP_BARRIER_CFG_4 0xE88404 + +#define mmTPC2_QM_CP_DBG_0_0 0xE88408 + +#define mmTPC2_QM_CP_DBG_0_1 0xE8840C + +#define mmTPC2_QM_CP_DBG_0_2 0xE88410 + +#define mmTPC2_QM_CP_DBG_0_3 0xE88414 + +#define mmTPC2_QM_CP_DBG_0_4 0xE88418 + +#define mmTPC2_QM_CP_ARUSER_31_11_0 0xE8841C + +#define mmTPC2_QM_CP_ARUSER_31_11_1 0xE88420 + +#define mmTPC2_QM_CP_ARUSER_31_11_2 0xE88424 + +#define mmTPC2_QM_CP_ARUSER_31_11_3 0xE88428 + +#define mmTPC2_QM_CP_ARUSER_31_11_4 0xE8842C + +#define mmTPC2_QM_CP_AWUSER_31_11_0 0xE88430 + +#define mmTPC2_QM_CP_AWUSER_31_11_1 0xE88434 + +#define mmTPC2_QM_CP_AWUSER_31_11_2 0xE88438 + +#define mmTPC2_QM_CP_AWUSER_31_11_3 0xE8843C + +#define mmTPC2_QM_CP_AWUSER_31_11_4 0xE88440 + +#define mmTPC2_QM_ARB_CFG_0 0xE88A00 + +#define mmTPC2_QM_ARB_CHOISE_Q_PUSH 0xE88A04 + +#define mmTPC2_QM_ARB_WRR_WEIGHT_0 0xE88A08 + +#define mmTPC2_QM_ARB_WRR_WEIGHT_1 0xE88A0C + +#define mmTPC2_QM_ARB_WRR_WEIGHT_2 0xE88A10 + +#define mmTPC2_QM_ARB_WRR_WEIGHT_3 0xE88A14 + +#define mmTPC2_QM_ARB_CFG_1 0xE88A18 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_0 0xE88A20 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_1 0xE88A24 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_2 0xE88A28 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_3 0xE88A2C + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_4 0xE88A30 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_5 0xE88A34 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_6 0xE88A38 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_7 0xE88A3C + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_8 0xE88A40 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_9 0xE88A44 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_10 0xE88A48 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_11 0xE88A4C + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_12 0xE88A50 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_13 0xE88A54 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_14 0xE88A58 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_15 0xE88A5C + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_16 0xE88A60 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_17 0xE88A64 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_18 0xE88A68 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_19 0xE88A6C + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_20 0xE88A70 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_21 0xE88A74 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_22 0xE88A78 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_23 0xE88A7C + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_24 0xE88A80 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_25 0xE88A84 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_26 0xE88A88 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_27 0xE88A8C + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_28 0xE88A90 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_29 0xE88A94 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_30 0xE88A98 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_31 0xE88A9C + +#define mmTPC2_QM_ARB_MST_CRED_INC 0xE88AA0 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xE88AA4 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xE88AA8 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xE88AAC + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xE88AB0 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xE88AB4 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xE88AB8 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xE88ABC + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xE88AC0 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xE88AC4 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xE88AC8 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xE88ACC + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xE88AD0 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xE88AD4 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xE88AD8 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xE88ADC + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xE88AE0 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xE88AE4 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xE88AE8 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xE88AEC + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xE88AF0 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xE88AF4 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xE88AF8 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xE88AFC + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xE88B00 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xE88B04 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xE88B08 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xE88B0C + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xE88B10 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xE88B14 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xE88B18 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xE88B1C + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xE88B20 + +#define mmTPC2_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xE88B28 + +#define mmTPC2_QM_ARB_MST_SLAVE_EN 0xE88B2C + +#define mmTPC2_QM_ARB_MST_QUIET_PER 0xE88B34 + +#define mmTPC2_QM_ARB_SLV_CHOISE_WDT 0xE88B38 + +#define mmTPC2_QM_ARB_SLV_ID 0xE88B3C + +#define mmTPC2_QM_ARB_MSG_MAX_INFLIGHT 0xE88B44 + +#define mmTPC2_QM_ARB_MSG_AWUSER_31_11 0xE88B48 + +#define mmTPC2_QM_ARB_MSG_AWUSER_SEC_PROP 0xE88B4C + +#define mmTPC2_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xE88B50 + +#define mmTPC2_QM_ARB_BASE_LO 0xE88B54 + +#define mmTPC2_QM_ARB_BASE_HI 0xE88B58 + +#define mmTPC2_QM_ARB_STATE_STS 0xE88B80 + +#define mmTPC2_QM_ARB_CHOISE_FULLNESS_STS 0xE88B84 + +#define mmTPC2_QM_ARB_MSG_STS 0xE88B88 + +#define mmTPC2_QM_ARB_SLV_CHOISE_Q_HEAD 0xE88B8C + +#define mmTPC2_QM_ARB_ERR_CAUSE 0xE88B9C + +#define mmTPC2_QM_ARB_ERR_MSG_EN 0xE88BA0 + +#define mmTPC2_QM_ARB_ERR_STS_DRP 0xE88BA8 + +#define mmTPC2_QM_ARB_MST_CRED_STS_0 0xE88BB0 + +#define mmTPC2_QM_ARB_MST_CRED_STS_1 0xE88BB4 + +#define mmTPC2_QM_ARB_MST_CRED_STS_2 0xE88BB8 + +#define mmTPC2_QM_ARB_MST_CRED_STS_3 0xE88BBC + +#define mmTPC2_QM_ARB_MST_CRED_STS_4 0xE88BC0 + +#define mmTPC2_QM_ARB_MST_CRED_STS_5 0xE88BC4 + +#define mmTPC2_QM_ARB_MST_CRED_STS_6 0xE88BC8 + +#define mmTPC2_QM_ARB_MST_CRED_STS_7 0xE88BCC + +#define mmTPC2_QM_ARB_MST_CRED_STS_8 0xE88BD0 + +#define mmTPC2_QM_ARB_MST_CRED_STS_9 0xE88BD4 + +#define mmTPC2_QM_ARB_MST_CRED_STS_10 0xE88BD8 + +#define mmTPC2_QM_ARB_MST_CRED_STS_11 0xE88BDC + +#define mmTPC2_QM_ARB_MST_CRED_STS_12 0xE88BE0 + +#define mmTPC2_QM_ARB_MST_CRED_STS_13 0xE88BE4 + +#define mmTPC2_QM_ARB_MST_CRED_STS_14 0xE88BE8 + +#define mmTPC2_QM_ARB_MST_CRED_STS_15 0xE88BEC + +#define mmTPC2_QM_ARB_MST_CRED_STS_16 0xE88BF0 + +#define mmTPC2_QM_ARB_MST_CRED_STS_17 0xE88BF4 + +#define mmTPC2_QM_ARB_MST_CRED_STS_18 0xE88BF8 + +#define mmTPC2_QM_ARB_MST_CRED_STS_19 0xE88BFC + +#define mmTPC2_QM_ARB_MST_CRED_STS_20 0xE88C00 + +#define mmTPC2_QM_ARB_MST_CRED_STS_21 0xE88C04 + +#define mmTPC2_QM_ARB_MST_CRED_STS_22 0xE88C08 + +#define mmTPC2_QM_ARB_MST_CRED_STS_23 0xE88C0C + +#define mmTPC2_QM_ARB_MST_CRED_STS_24 0xE88C10 + +#define mmTPC2_QM_ARB_MST_CRED_STS_25 0xE88C14 + +#define mmTPC2_QM_ARB_MST_CRED_STS_26 0xE88C18 + +#define mmTPC2_QM_ARB_MST_CRED_STS_27 0xE88C1C + +#define mmTPC2_QM_ARB_MST_CRED_STS_28 0xE88C20 + +#define mmTPC2_QM_ARB_MST_CRED_STS_29 0xE88C24 + +#define mmTPC2_QM_ARB_MST_CRED_STS_30 0xE88C28 + +#define mmTPC2_QM_ARB_MST_CRED_STS_31 0xE88C2C + +#define mmTPC2_QM_CGM_CFG 0xE88C70 + +#define mmTPC2_QM_CGM_STS 0xE88C74 + +#define mmTPC2_QM_CGM_CFG1 0xE88C78 + +#define mmTPC2_QM_LOCAL_RANGE_BASE 0xE88C80 + +#define mmTPC2_QM_LOCAL_RANGE_SIZE 0xE88C84 + +#define mmTPC2_QM_CSMR_STRICT_PRIO_CFG 0xE88C90 + +#define mmTPC2_QM_HBW_RD_RATE_LIM_CFG_1 0xE88C94 + +#define mmTPC2_QM_LBW_WR_RATE_LIM_CFG_0 0xE88C98 + +#define mmTPC2_QM_LBW_WR_RATE_LIM_CFG_1 0xE88C9C + +#define mmTPC2_QM_HBW_RD_RATE_LIM_CFG_0 0xE88CA0 + +#define mmTPC2_QM_GLBL_AXCACHE 0xE88CA4 + +#define mmTPC2_QM_IND_GW_APB_CFG 0xE88CB0 + +#define mmTPC2_QM_IND_GW_APB_WDATA 0xE88CB4 + +#define mmTPC2_QM_IND_GW_APB_RDATA 0xE88CB8 + +#define mmTPC2_QM_IND_GW_APB_STATUS 0xE88CBC + +#define mmTPC2_QM_GLBL_ERR_ADDR_LO 0xE88CD0 + +#define mmTPC2_QM_GLBL_ERR_ADDR_HI 0xE88CD4 + +#define mmTPC2_QM_GLBL_ERR_WDATA 0xE88CD8 + +#define mmTPC2_QM_GLBL_MEM_INIT_BUSY 0xE88D00 + +#endif /* ASIC_REG_TPC2_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc3_cfg_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc3_cfg_regs.h new file mode 100644 index 000000000000..6d42469659f1 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc3_cfg_regs.h @@ -0,0 +1,1226 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC3_CFG_REGS_H_ +#define ASIC_REG_TPC3_CFG_REGS_H_ + +/* + ***************************************** + * TPC3_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC3_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xEC6400 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xEC6404 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xEC6408 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xEC640C + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xEC6410 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xEC6414 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xEC6418 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xEC641C + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xEC6420 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xEC6424 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xEC6428 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xEC642C + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xEC6430 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xEC6434 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xEC6438 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xEC643C + +#define mmTPC3_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xEC6440 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xEC6444 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xEC6448 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xEC644C + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xEC6450 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xEC6454 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xEC6458 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xEC645C + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xEC6460 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xEC6464 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xEC6468 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xEC646C + +#define mmTPC3_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xEC6470 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xEC6474 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xEC6478 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xEC647C + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xEC6480 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xEC6484 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xEC6488 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xEC648C + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xEC6490 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xEC6494 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xEC6498 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xEC649C + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xEC64A0 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xEC64A4 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xEC64A8 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xEC64AC + +#define mmTPC3_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xEC64B0 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xEC64B4 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xEC64B8 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xEC64BC + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xEC64C0 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xEC64C4 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xEC64C8 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xEC64CC + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xEC64D0 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xEC64D4 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xEC64D8 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xEC64DC + +#define mmTPC3_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xEC64E0 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xEC64E4 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xEC64E8 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xEC64EC + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xEC64F0 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xEC64F4 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xEC64F8 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xEC64FC + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xEC6500 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xEC6504 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xEC6508 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xEC650C + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xEC6510 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xEC6514 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xEC6518 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xEC651C + +#define mmTPC3_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xEC6520 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xEC6524 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xEC6528 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xEC652C + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xEC6530 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xEC6534 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xEC6538 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xEC653C + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xEC6540 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xEC6544 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xEC6548 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xEC654C + +#define mmTPC3_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xEC6550 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xEC6554 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xEC6558 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xEC655C + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xEC6560 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xEC6564 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xEC6568 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xEC656C + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xEC6570 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xEC6574 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xEC6578 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xEC657C + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xEC6580 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xEC6584 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xEC6588 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xEC658C + +#define mmTPC3_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xEC6590 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xEC6594 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xEC6598 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xEC659C + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xEC65A0 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xEC65A4 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xEC65A8 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xEC65AC + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xEC65B0 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xEC65B4 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xEC65B8 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xEC65BC + +#define mmTPC3_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xEC65C0 + +#define mmTPC3_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xEC65C4 + +#define mmTPC3_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xEC65C8 + +#define mmTPC3_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xEC65CC + +#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xEC65D0 + +#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xEC65D4 + +#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xEC65D8 + +#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xEC65DC + +#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xEC65E0 + +#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xEC65E4 + +#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xEC65E8 + +#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xEC65EC + +#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xEC65F0 + +#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xEC65F4 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xEC65F8 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xEC65FC + +#define mmTPC3_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xEC6600 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xEC6604 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xEC6608 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xEC660C + +#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xEC6610 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xEC6614 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xEC6618 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xEC661C + +#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xEC6620 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xEC6624 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xEC6628 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xEC662C + +#define mmTPC3_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xEC6630 + +#define mmTPC3_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xEC6634 + +#define mmTPC3_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xEC6638 + +#define mmTPC3_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xEC663C + +#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xEC6640 + +#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xEC6644 + +#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xEC6648 + +#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xEC664C + +#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xEC6650 + +#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xEC6654 + +#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xEC6658 + +#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xEC665C + +#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xEC6660 + +#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xEC6664 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xEC6668 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xEC666C + +#define mmTPC3_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xEC6670 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xEC6674 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xEC6678 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xEC667C + +#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xEC6680 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xEC6684 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xEC6688 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xEC668C + +#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xEC6690 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xEC6694 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xEC6698 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xEC669C + +#define mmTPC3_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xEC66A0 + +#define mmTPC3_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xEC66A4 + +#define mmTPC3_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xEC66A8 + +#define mmTPC3_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xEC66AC + +#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xEC66B0 + +#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xEC66B4 + +#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xEC66B8 + +#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xEC66BC + +#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xEC66C0 + +#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xEC66C4 + +#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xEC66C8 + +#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xEC66CC + +#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xEC66D0 + +#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xEC66D4 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xEC66D8 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xEC66DC + +#define mmTPC3_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xEC66E0 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xEC66E4 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xEC66E8 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xEC66EC + +#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xEC66F0 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xEC66F4 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xEC66F8 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xEC66FC + +#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xEC6700 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xEC6704 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xEC6708 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xEC670C + +#define mmTPC3_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xEC6710 + +#define mmTPC3_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xEC6714 + +#define mmTPC3_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xEC6718 + +#define mmTPC3_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xEC671C + +#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xEC6720 + +#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xEC6724 + +#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xEC6728 + +#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xEC672C + +#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xEC6730 + +#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xEC6734 + +#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xEC6738 + +#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xEC673C + +#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xEC6740 + +#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xEC6744 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xEC6748 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xEC674C + +#define mmTPC3_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xEC6750 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xEC6754 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xEC6758 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xEC675C + +#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xEC6760 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xEC6764 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xEC6768 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xEC676C + +#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xEC6770 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xEC6774 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xEC6778 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xEC677C + +#define mmTPC3_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xEC6780 + +#define mmTPC3_CFG_KERNEL_SYNC_OBJECT_ADDR 0xEC6784 + +#define mmTPC3_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xEC6788 + +#define mmTPC3_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xEC678C + +#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_0 0xEC6790 + +#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_0 0xEC6794 + +#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_1 0xEC6798 + +#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_1 0xEC679C + +#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_2 0xEC67A0 + +#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_2 0xEC67A4 + +#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_3 0xEC67A8 + +#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_3 0xEC67AC + +#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_4 0xEC67B0 + +#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_4 0xEC67B4 + +#define mmTPC3_CFG_KERNEL_KERNEL_CONFIG 0xEC67B8 + +#define mmTPC3_CFG_KERNEL_KERNEL_ID 0xEC67BC + +#define mmTPC3_CFG_KERNEL_SRF_0 0xEC67C0 + +#define mmTPC3_CFG_KERNEL_SRF_1 0xEC67C4 + +#define mmTPC3_CFG_KERNEL_SRF_2 0xEC67C8 + +#define mmTPC3_CFG_KERNEL_SRF_3 0xEC67CC + +#define mmTPC3_CFG_KERNEL_SRF_4 0xEC67D0 + +#define mmTPC3_CFG_KERNEL_SRF_5 0xEC67D4 + +#define mmTPC3_CFG_KERNEL_SRF_6 0xEC67D8 + +#define mmTPC3_CFG_KERNEL_SRF_7 0xEC67DC + +#define mmTPC3_CFG_KERNEL_SRF_8 0xEC67E0 + +#define mmTPC3_CFG_KERNEL_SRF_9 0xEC67E4 + +#define mmTPC3_CFG_KERNEL_SRF_10 0xEC67E8 + +#define mmTPC3_CFG_KERNEL_SRF_11 0xEC67EC + +#define mmTPC3_CFG_KERNEL_SRF_12 0xEC67F0 + +#define mmTPC3_CFG_KERNEL_SRF_13 0xEC67F4 + +#define mmTPC3_CFG_KERNEL_SRF_14 0xEC67F8 + +#define mmTPC3_CFG_KERNEL_SRF_15 0xEC67FC + +#define mmTPC3_CFG_KERNEL_SRF_16 0xEC6800 + +#define mmTPC3_CFG_KERNEL_SRF_17 0xEC6804 + +#define mmTPC3_CFG_KERNEL_SRF_18 0xEC6808 + +#define mmTPC3_CFG_KERNEL_SRF_19 0xEC680C + +#define mmTPC3_CFG_KERNEL_SRF_20 0xEC6810 + +#define mmTPC3_CFG_KERNEL_SRF_21 0xEC6814 + +#define mmTPC3_CFG_KERNEL_SRF_22 0xEC6818 + +#define mmTPC3_CFG_KERNEL_SRF_23 0xEC681C + +#define mmTPC3_CFG_KERNEL_SRF_24 0xEC6820 + +#define mmTPC3_CFG_KERNEL_SRF_25 0xEC6824 + +#define mmTPC3_CFG_KERNEL_SRF_26 0xEC6828 + +#define mmTPC3_CFG_KERNEL_SRF_27 0xEC682C + +#define mmTPC3_CFG_KERNEL_SRF_28 0xEC6830 + +#define mmTPC3_CFG_KERNEL_SRF_29 0xEC6834 + +#define mmTPC3_CFG_KERNEL_SRF_30 0xEC6838 + +#define mmTPC3_CFG_KERNEL_SRF_31 0xEC683C + +#define mmTPC3_CFG_ROUND_CSR 0xEC68FC + +#define mmTPC3_CFG_PROT 0xEC6900 + +#define mmTPC3_CFG_SEMAPHORE 0xEC6908 + +#define mmTPC3_CFG_VFLAGS 0xEC690C + +#define mmTPC3_CFG_SFLAGS 0xEC6910 + +#define mmTPC3_CFG_LFSR_POLYNOM 0xEC6918 + +#define mmTPC3_CFG_STATUS 0xEC691C + +#define mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH 0xEC6920 + +#define mmTPC3_CFG_CFG_SUBTRACT_VALUE 0xEC6924 + +#define mmTPC3_CFG_SM_BASE_ADDRESS_HIGH 0xEC692C + +#define mmTPC3_CFG_TPC_CMD 0xEC6930 + +#define mmTPC3_CFG_TPC_EXECUTE 0xEC6938 + +#define mmTPC3_CFG_TPC_STALL 0xEC693C + +#define mmTPC3_CFG_ICACHE_BASE_ADDERESS_LOW 0xEC6940 + +#define mmTPC3_CFG_ICACHE_BASE_ADDERESS_HIGH 0xEC6944 + +#define mmTPC3_CFG_RD_RATE_LIMIT 0xEC6948 + +#define mmTPC3_CFG_WR_RATE_LIMIT 0xEC6950 + +#define mmTPC3_CFG_MSS_CONFIG 0xEC6954 + +#define mmTPC3_CFG_TPC_INTR_CAUSE 0xEC6958 + +#define mmTPC3_CFG_TPC_INTR_MASK 0xEC695C + +#define mmTPC3_CFG_WQ_CREDITS 0xEC6960 + +#define mmTPC3_CFG_ARUSER_LO 0xEC6964 + +#define mmTPC3_CFG_ARUSER_HI 0xEC6968 + +#define mmTPC3_CFG_AWUSER_LO 0xEC696C + +#define mmTPC3_CFG_AWUSER_HI 0xEC6970 + +#define mmTPC3_CFG_OPCODE_EXEC 0xEC6974 + +#define mmTPC3_CFG_LUT_FUNC32_BASE_ADDR_LO 0xEC6978 + +#define mmTPC3_CFG_LUT_FUNC32_BASE_ADDR_HI 0xEC697C + +#define mmTPC3_CFG_LUT_FUNC64_BASE_ADDR_LO 0xEC6980 + +#define mmTPC3_CFG_LUT_FUNC64_BASE_ADDR_HI 0xEC6984 + +#define mmTPC3_CFG_LUT_FUNC128_BASE_ADDR_LO 0xEC6988 + +#define mmTPC3_CFG_LUT_FUNC128_BASE_ADDR_HI 0xEC698C + +#define mmTPC3_CFG_LUT_FUNC256_BASE_ADDR_LO 0xEC6990 + +#define mmTPC3_CFG_LUT_FUNC256_BASE_ADDR_HI 0xEC6994 + +#define mmTPC3_CFG_TSB_CFG_MAX_SIZE 0xEC6998 + +#define mmTPC3_CFG_TSB_CFG 0xEC699C + +#define mmTPC3_CFG_DBGMEM_ADD 0xEC69A0 + +#define mmTPC3_CFG_DBGMEM_DATA_WR 0xEC69A4 + +#define mmTPC3_CFG_DBGMEM_DATA_RD 0xEC69A8 + +#define mmTPC3_CFG_DBGMEM_CTRL 0xEC69AC + +#define mmTPC3_CFG_DBGMEM_RC 0xEC69B0 + +#define mmTPC3_CFG_TSB_INFLIGHT_CNTR 0xEC69B4 + +#define mmTPC3_CFG_WQ_INFLIGHT_CNTR 0xEC69B8 + +#define mmTPC3_CFG_WQ_LBW_TOTAL_CNTR 0xEC69BC + +#define mmTPC3_CFG_WQ_HBW_TOTAL_CNTR 0xEC69C0 + +#define mmTPC3_CFG_IRQ_OCCOUPY_CNTR 0xEC69C4 + +#define mmTPC3_CFG_FUNC_MBIST_CNTRL 0xEC69D0 + +#define mmTPC3_CFG_FUNC_MBIST_PAT 0xEC69D4 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_0 0xEC69D8 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_1 0xEC69DC + +#define mmTPC3_CFG_FUNC_MBIST_MEM_2 0xEC69E0 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_3 0xEC69E4 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_4 0xEC69E8 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_5 0xEC69EC + +#define mmTPC3_CFG_FUNC_MBIST_MEM_6 0xEC69F0 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_7 0xEC69F4 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_8 0xEC69F8 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_9 0xEC69FC + +#define mmTPC3_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xEC6A00 + +#define mmTPC3_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xEC6A04 + +#define mmTPC3_CFG_QM_TENSOR_0_PADDING_VALUE 0xEC6A08 + +#define mmTPC3_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xEC6A0C + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_0_SIZE 0xEC6A10 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xEC6A14 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_1_SIZE 0xEC6A18 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xEC6A1C + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_2_SIZE 0xEC6A20 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xEC6A24 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_3_SIZE 0xEC6A28 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xEC6A2C + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_4_SIZE 0xEC6A30 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xEC6A34 + +#define mmTPC3_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xEC6A38 + +#define mmTPC3_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xEC6A3C + +#define mmTPC3_CFG_QM_TENSOR_1_PADDING_VALUE 0xEC6A40 + +#define mmTPC3_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xEC6A44 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_0_SIZE 0xEC6A48 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xEC6A4C + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_1_SIZE 0xEC6A50 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xEC6A54 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_2_SIZE 0xEC6A58 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xEC6A5C + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_3_SIZE 0xEC6A60 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xEC6A64 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_4_SIZE 0xEC6A68 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xEC6A6C + +#define mmTPC3_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xEC6A70 + +#define mmTPC3_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xEC6A74 + +#define mmTPC3_CFG_QM_TENSOR_2_PADDING_VALUE 0xEC6A78 + +#define mmTPC3_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xEC6A7C + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_0_SIZE 0xEC6A80 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xEC6A84 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_1_SIZE 0xEC6A88 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xEC6A8C + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_2_SIZE 0xEC6A90 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xEC6A94 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_3_SIZE 0xEC6A98 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xEC6A9C + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_4_SIZE 0xEC6AA0 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xEC6AA4 + +#define mmTPC3_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xEC6AA8 + +#define mmTPC3_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xEC6AAC + +#define mmTPC3_CFG_QM_TENSOR_3_PADDING_VALUE 0xEC6AB0 + +#define mmTPC3_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xEC6AB4 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_0_SIZE 0xEC6AB8 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xEC6ABC + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_1_SIZE 0xEC6AC0 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xEC6AC4 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_2_SIZE 0xEC6AC8 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xEC6ACC + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_3_SIZE 0xEC6AD0 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xEC6AD4 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_4_SIZE 0xEC6AD8 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xEC6ADC + +#define mmTPC3_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xEC6AE0 + +#define mmTPC3_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xEC6AE4 + +#define mmTPC3_CFG_QM_TENSOR_4_PADDING_VALUE 0xEC6AE8 + +#define mmTPC3_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xEC6AEC + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_0_SIZE 0xEC6AF0 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xEC6AF4 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_1_SIZE 0xEC6AF8 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xEC6AFC + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_2_SIZE 0xEC6B00 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xEC6B04 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_3_SIZE 0xEC6B08 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xEC6B0C + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_4_SIZE 0xEC6B10 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xEC6B14 + +#define mmTPC3_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xEC6B18 + +#define mmTPC3_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xEC6B1C + +#define mmTPC3_CFG_QM_TENSOR_5_PADDING_VALUE 0xEC6B20 + +#define mmTPC3_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xEC6B24 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_0_SIZE 0xEC6B28 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xEC6B2C + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_1_SIZE 0xEC6B30 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xEC6B34 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_2_SIZE 0xEC6B38 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xEC6B3C + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_3_SIZE 0xEC6B40 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xEC6B44 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_4_SIZE 0xEC6B48 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xEC6B4C + +#define mmTPC3_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xEC6B50 + +#define mmTPC3_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xEC6B54 + +#define mmTPC3_CFG_QM_TENSOR_6_PADDING_VALUE 0xEC6B58 + +#define mmTPC3_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xEC6B5C + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_0_SIZE 0xEC6B60 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xEC6B64 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_1_SIZE 0xEC6B68 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xEC6B6C + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_2_SIZE 0xEC6B70 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xEC6B74 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_3_SIZE 0xEC6B78 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xEC6B7C + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_4_SIZE 0xEC6B80 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xEC6B84 + +#define mmTPC3_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xEC6B88 + +#define mmTPC3_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xEC6B8C + +#define mmTPC3_CFG_QM_TENSOR_7_PADDING_VALUE 0xEC6B90 + +#define mmTPC3_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xEC6B94 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_0_SIZE 0xEC6B98 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xEC6B9C + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_1_SIZE 0xEC6BA0 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xEC6BA4 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_2_SIZE 0xEC6BA8 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xEC6BAC + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_3_SIZE 0xEC6BB0 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xEC6BB4 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_4_SIZE 0xEC6BB8 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xEC6BBC + +#define mmTPC3_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xEC6BC0 + +#define mmTPC3_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xEC6BC4 + +#define mmTPC3_CFG_QM_TENSOR_8_PADDING_VALUE 0xEC6BC8 + +#define mmTPC3_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xEC6BCC + +#define mmTPC3_CFG_QM_TENSOR_8_DIM_0_SIZE 0xEC6BD0 + +#define mmTPC3_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xEC6BD4 + +#define mmTPC3_CFG_QM_TENSOR_8_DIM_1_SIZE 0xEC6BD8 + +#define mmTPC3_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xEC6BDC + +#define mmTPC3_CFG_QM_TENSOR_8_DIM_2_SIZE 0xEC6BE0 + +#define mmTPC3_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xEC6BE4 + +#define mmTPC3_CFG_QM_TENSOR_8_DIM_3_SIZE 0xEC6BE8 + +#define mmTPC3_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xEC6BEC + +#define mmTPC3_CFG_QM_TENSOR_8_DIM_4_SIZE 0xEC6BF0 + +#define mmTPC3_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xEC6BF4 + +#define mmTPC3_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xEC6BF8 + +#define mmTPC3_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xEC6BFC + +#define mmTPC3_CFG_QM_TENSOR_9_PADDING_VALUE 0xEC6C00 + +#define mmTPC3_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xEC6C04 + +#define mmTPC3_CFG_QM_TENSOR_9_DIM_0_SIZE 0xEC6C08 + +#define mmTPC3_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xEC6C0C + +#define mmTPC3_CFG_QM_TENSOR_9_DIM_1_SIZE 0xEC6C10 + +#define mmTPC3_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xEC6C14 + +#define mmTPC3_CFG_QM_TENSOR_9_DIM_2_SIZE 0xEC6C18 + +#define mmTPC3_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xEC6C1C + +#define mmTPC3_CFG_QM_TENSOR_9_DIM_3_SIZE 0xEC6C20 + +#define mmTPC3_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xEC6C24 + +#define mmTPC3_CFG_QM_TENSOR_9_DIM_4_SIZE 0xEC6C28 + +#define mmTPC3_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xEC6C2C + +#define mmTPC3_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xEC6C30 + +#define mmTPC3_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xEC6C34 + +#define mmTPC3_CFG_QM_TENSOR_10_PADDING_VALUE 0xEC6C38 + +#define mmTPC3_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xEC6C3C + +#define mmTPC3_CFG_QM_TENSOR_10_DIM_0_SIZE 0xEC6C40 + +#define mmTPC3_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xEC6C44 + +#define mmTPC3_CFG_QM_TENSOR_10_DIM_1_SIZE 0xEC6C48 + +#define mmTPC3_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xEC6C4C + +#define mmTPC3_CFG_QM_TENSOR_10_DIM_2_SIZE 0xEC6C50 + +#define mmTPC3_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xEC6C54 + +#define mmTPC3_CFG_QM_TENSOR_10_DIM_3_SIZE 0xEC6C58 + +#define mmTPC3_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xEC6C5C + +#define mmTPC3_CFG_QM_TENSOR_10_DIM_4_SIZE 0xEC6C60 + +#define mmTPC3_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xEC6C64 + +#define mmTPC3_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xEC6C68 + +#define mmTPC3_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xEC6C6C + +#define mmTPC3_CFG_QM_TENSOR_11_PADDING_VALUE 0xEC6C70 + +#define mmTPC3_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xEC6C74 + +#define mmTPC3_CFG_QM_TENSOR_11_DIM_0_SIZE 0xEC6C78 + +#define mmTPC3_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xEC6C7C + +#define mmTPC3_CFG_QM_TENSOR_11_DIM_1_SIZE 0xEC6C80 + +#define mmTPC3_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xEC6C84 + +#define mmTPC3_CFG_QM_TENSOR_11_DIM_2_SIZE 0xEC6C88 + +#define mmTPC3_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xEC6C8C + +#define mmTPC3_CFG_QM_TENSOR_11_DIM_3_SIZE 0xEC6C90 + +#define mmTPC3_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xEC6C94 + +#define mmTPC3_CFG_QM_TENSOR_11_DIM_4_SIZE 0xEC6C98 + +#define mmTPC3_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xEC6C9C + +#define mmTPC3_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xEC6CA0 + +#define mmTPC3_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xEC6CA4 + +#define mmTPC3_CFG_QM_TENSOR_12_PADDING_VALUE 0xEC6CA8 + +#define mmTPC3_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xEC6CAC + +#define mmTPC3_CFG_QM_TENSOR_12_DIM_0_SIZE 0xEC6CB0 + +#define mmTPC3_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xEC6CB4 + +#define mmTPC3_CFG_QM_TENSOR_12_DIM_1_SIZE 0xEC6CB8 + +#define mmTPC3_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xEC6CBC + +#define mmTPC3_CFG_QM_TENSOR_12_DIM_2_SIZE 0xEC6CC0 + +#define mmTPC3_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xEC6CC4 + +#define mmTPC3_CFG_QM_TENSOR_12_DIM_3_SIZE 0xEC6CC8 + +#define mmTPC3_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xEC6CCC + +#define mmTPC3_CFG_QM_TENSOR_12_DIM_4_SIZE 0xEC6CD0 + +#define mmTPC3_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xEC6CD4 + +#define mmTPC3_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xEC6CD8 + +#define mmTPC3_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xEC6CDC + +#define mmTPC3_CFG_QM_TENSOR_13_PADDING_VALUE 0xEC6CE0 + +#define mmTPC3_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xEC6CE4 + +#define mmTPC3_CFG_QM_TENSOR_13_DIM_0_SIZE 0xEC6CE8 + +#define mmTPC3_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xEC6CEC + +#define mmTPC3_CFG_QM_TENSOR_13_DIM_1_SIZE 0xEC6CF0 + +#define mmTPC3_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xEC6CF4 + +#define mmTPC3_CFG_QM_TENSOR_13_DIM_2_SIZE 0xEC6CF8 + +#define mmTPC3_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xEC6CFC + +#define mmTPC3_CFG_QM_TENSOR_13_DIM_3_SIZE 0xEC6D00 + +#define mmTPC3_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xEC6D04 + +#define mmTPC3_CFG_QM_TENSOR_13_DIM_4_SIZE 0xEC6D08 + +#define mmTPC3_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xEC6D0C + +#define mmTPC3_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xEC6D10 + +#define mmTPC3_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xEC6D14 + +#define mmTPC3_CFG_QM_TENSOR_14_PADDING_VALUE 0xEC6D18 + +#define mmTPC3_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xEC6D1C + +#define mmTPC3_CFG_QM_TENSOR_14_DIM_0_SIZE 0xEC6D20 + +#define mmTPC3_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xEC6D24 + +#define mmTPC3_CFG_QM_TENSOR_14_DIM_1_SIZE 0xEC6D28 + +#define mmTPC3_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xEC6D2C + +#define mmTPC3_CFG_QM_TENSOR_14_DIM_2_SIZE 0xEC6D30 + +#define mmTPC3_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xEC6D34 + +#define mmTPC3_CFG_QM_TENSOR_14_DIM_3_SIZE 0xEC6D38 + +#define mmTPC3_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xEC6D3C + +#define mmTPC3_CFG_QM_TENSOR_14_DIM_4_SIZE 0xEC6D40 + +#define mmTPC3_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xEC6D44 + +#define mmTPC3_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xEC6D48 + +#define mmTPC3_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xEC6D4C + +#define mmTPC3_CFG_QM_TENSOR_15_PADDING_VALUE 0xEC6D50 + +#define mmTPC3_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xEC6D54 + +#define mmTPC3_CFG_QM_TENSOR_15_DIM_0_SIZE 0xEC6D58 + +#define mmTPC3_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xEC6D5C + +#define mmTPC3_CFG_QM_TENSOR_15_DIM_1_SIZE 0xEC6D60 + +#define mmTPC3_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xEC6D64 + +#define mmTPC3_CFG_QM_TENSOR_15_DIM_2_SIZE 0xEC6D68 + +#define mmTPC3_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xEC6D6C + +#define mmTPC3_CFG_QM_TENSOR_15_DIM_3_SIZE 0xEC6D70 + +#define mmTPC3_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xEC6D74 + +#define mmTPC3_CFG_QM_TENSOR_15_DIM_4_SIZE 0xEC6D78 + +#define mmTPC3_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xEC6D7C + +#define mmTPC3_CFG_QM_SYNC_OBJECT_MESSAGE 0xEC6D80 + +#define mmTPC3_CFG_QM_SYNC_OBJECT_ADDR 0xEC6D84 + +#define mmTPC3_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xEC6D88 + +#define mmTPC3_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xEC6D8C + +#define mmTPC3_CFG_QM_TID_BASE_DIM_0 0xEC6D90 + +#define mmTPC3_CFG_QM_TID_SIZE_DIM_0 0xEC6D94 + +#define mmTPC3_CFG_QM_TID_BASE_DIM_1 0xEC6D98 + +#define mmTPC3_CFG_QM_TID_SIZE_DIM_1 0xEC6D9C + +#define mmTPC3_CFG_QM_TID_BASE_DIM_2 0xEC6DA0 + +#define mmTPC3_CFG_QM_TID_SIZE_DIM_2 0xEC6DA4 + +#define mmTPC3_CFG_QM_TID_BASE_DIM_3 0xEC6DA8 + +#define mmTPC3_CFG_QM_TID_SIZE_DIM_3 0xEC6DAC + +#define mmTPC3_CFG_QM_TID_BASE_DIM_4 0xEC6DB0 + +#define mmTPC3_CFG_QM_TID_SIZE_DIM_4 0xEC6DB4 + +#define mmTPC3_CFG_QM_KERNEL_CONFIG 0xEC6DB8 + +#define mmTPC3_CFG_QM_KERNEL_ID 0xEC6DBC + +#define mmTPC3_CFG_QM_SRF_0 0xEC6DC0 + +#define mmTPC3_CFG_QM_SRF_1 0xEC6DC4 + +#define mmTPC3_CFG_QM_SRF_2 0xEC6DC8 + +#define mmTPC3_CFG_QM_SRF_3 0xEC6DCC + +#define mmTPC3_CFG_QM_SRF_4 0xEC6DD0 + +#define mmTPC3_CFG_QM_SRF_5 0xEC6DD4 + +#define mmTPC3_CFG_QM_SRF_6 0xEC6DD8 + +#define mmTPC3_CFG_QM_SRF_7 0xEC6DDC + +#define mmTPC3_CFG_QM_SRF_8 0xEC6DE0 + +#define mmTPC3_CFG_QM_SRF_9 0xEC6DE4 + +#define mmTPC3_CFG_QM_SRF_10 0xEC6DE8 + +#define mmTPC3_CFG_QM_SRF_11 0xEC6DEC + +#define mmTPC3_CFG_QM_SRF_12 0xEC6DF0 + +#define mmTPC3_CFG_QM_SRF_13 0xEC6DF4 + +#define mmTPC3_CFG_QM_SRF_14 0xEC6DF8 + +#define mmTPC3_CFG_QM_SRF_15 0xEC6DFC + +#define mmTPC3_CFG_QM_SRF_16 0xEC6E00 + +#define mmTPC3_CFG_QM_SRF_17 0xEC6E04 + +#define mmTPC3_CFG_QM_SRF_18 0xEC6E08 + +#define mmTPC3_CFG_QM_SRF_19 0xEC6E0C + +#define mmTPC3_CFG_QM_SRF_20 0xEC6E10 + +#define mmTPC3_CFG_QM_SRF_21 0xEC6E14 + +#define mmTPC3_CFG_QM_SRF_22 0xEC6E18 + +#define mmTPC3_CFG_QM_SRF_23 0xEC6E1C + +#define mmTPC3_CFG_QM_SRF_24 0xEC6E20 + +#define mmTPC3_CFG_QM_SRF_25 0xEC6E24 + +#define mmTPC3_CFG_QM_SRF_26 0xEC6E28 + +#define mmTPC3_CFG_QM_SRF_27 0xEC6E2C + +#define mmTPC3_CFG_QM_SRF_28 0xEC6E30 + +#define mmTPC3_CFG_QM_SRF_29 0xEC6E34 + +#define mmTPC3_CFG_QM_SRF_30 0xEC6E38 + +#define mmTPC3_CFG_QM_SRF_31 0xEC6E3C + +#endif /* ASIC_REG_TPC3_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc3_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc3_qm_regs.h new file mode 100644 index 000000000000..5f2a0fd86c9e --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc3_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC3_QM_REGS_H_ +#define ASIC_REG_TPC3_QM_REGS_H_ + +/* + ***************************************** + * TPC3_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC3_QM_GLBL_CFG0 0xEC8000 + +#define mmTPC3_QM_GLBL_CFG1 0xEC8004 + +#define mmTPC3_QM_GLBL_PROT 0xEC8008 + +#define mmTPC3_QM_GLBL_ERR_CFG 0xEC800C + +#define mmTPC3_QM_GLBL_SECURE_PROPS_0 0xEC8010 + +#define mmTPC3_QM_GLBL_SECURE_PROPS_1 0xEC8014 + +#define mmTPC3_QM_GLBL_SECURE_PROPS_2 0xEC8018 + +#define mmTPC3_QM_GLBL_SECURE_PROPS_3 0xEC801C + +#define mmTPC3_QM_GLBL_SECURE_PROPS_4 0xEC8020 + +#define mmTPC3_QM_GLBL_NON_SECURE_PROPS_0 0xEC8024 + +#define mmTPC3_QM_GLBL_NON_SECURE_PROPS_1 0xEC8028 + +#define mmTPC3_QM_GLBL_NON_SECURE_PROPS_2 0xEC802C + +#define mmTPC3_QM_GLBL_NON_SECURE_PROPS_3 0xEC8030 + +#define mmTPC3_QM_GLBL_NON_SECURE_PROPS_4 0xEC8034 + +#define mmTPC3_QM_GLBL_STS0 0xEC8038 + +#define mmTPC3_QM_GLBL_STS1_0 0xEC8040 + +#define mmTPC3_QM_GLBL_STS1_1 0xEC8044 + +#define mmTPC3_QM_GLBL_STS1_2 0xEC8048 + +#define mmTPC3_QM_GLBL_STS1_3 0xEC804C + +#define mmTPC3_QM_GLBL_STS1_4 0xEC8050 + +#define mmTPC3_QM_GLBL_MSG_EN_0 0xEC8054 + +#define mmTPC3_QM_GLBL_MSG_EN_1 0xEC8058 + +#define mmTPC3_QM_GLBL_MSG_EN_2 0xEC805C + +#define mmTPC3_QM_GLBL_MSG_EN_3 0xEC8060 + +#define mmTPC3_QM_GLBL_MSG_EN_4 0xEC8068 + +#define mmTPC3_QM_PQ_BASE_LO_0 0xEC8070 + +#define mmTPC3_QM_PQ_BASE_LO_1 0xEC8074 + +#define mmTPC3_QM_PQ_BASE_LO_2 0xEC8078 + +#define mmTPC3_QM_PQ_BASE_LO_3 0xEC807C + +#define mmTPC3_QM_PQ_BASE_HI_0 0xEC8080 + +#define mmTPC3_QM_PQ_BASE_HI_1 0xEC8084 + +#define mmTPC3_QM_PQ_BASE_HI_2 0xEC8088 + +#define mmTPC3_QM_PQ_BASE_HI_3 0xEC808C + +#define mmTPC3_QM_PQ_SIZE_0 0xEC8090 + +#define mmTPC3_QM_PQ_SIZE_1 0xEC8094 + +#define mmTPC3_QM_PQ_SIZE_2 0xEC8098 + +#define mmTPC3_QM_PQ_SIZE_3 0xEC809C + +#define mmTPC3_QM_PQ_PI_0 0xEC80A0 + +#define mmTPC3_QM_PQ_PI_1 0xEC80A4 + +#define mmTPC3_QM_PQ_PI_2 0xEC80A8 + +#define mmTPC3_QM_PQ_PI_3 0xEC80AC + +#define mmTPC3_QM_PQ_CI_0 0xEC80B0 + +#define mmTPC3_QM_PQ_CI_1 0xEC80B4 + +#define mmTPC3_QM_PQ_CI_2 0xEC80B8 + +#define mmTPC3_QM_PQ_CI_3 0xEC80BC + +#define mmTPC3_QM_PQ_CFG0_0 0xEC80C0 + +#define mmTPC3_QM_PQ_CFG0_1 0xEC80C4 + +#define mmTPC3_QM_PQ_CFG0_2 0xEC80C8 + +#define mmTPC3_QM_PQ_CFG0_3 0xEC80CC + +#define mmTPC3_QM_PQ_CFG1_0 0xEC80D0 + +#define mmTPC3_QM_PQ_CFG1_1 0xEC80D4 + +#define mmTPC3_QM_PQ_CFG1_2 0xEC80D8 + +#define mmTPC3_QM_PQ_CFG1_3 0xEC80DC + +#define mmTPC3_QM_PQ_ARUSER_31_11_0 0xEC80E0 + +#define mmTPC3_QM_PQ_ARUSER_31_11_1 0xEC80E4 + +#define mmTPC3_QM_PQ_ARUSER_31_11_2 0xEC80E8 + +#define mmTPC3_QM_PQ_ARUSER_31_11_3 0xEC80EC + +#define mmTPC3_QM_PQ_STS0_0 0xEC80F0 + +#define mmTPC3_QM_PQ_STS0_1 0xEC80F4 + +#define mmTPC3_QM_PQ_STS0_2 0xEC80F8 + +#define mmTPC3_QM_PQ_STS0_3 0xEC80FC + +#define mmTPC3_QM_PQ_STS1_0 0xEC8100 + +#define mmTPC3_QM_PQ_STS1_1 0xEC8104 + +#define mmTPC3_QM_PQ_STS1_2 0xEC8108 + +#define mmTPC3_QM_PQ_STS1_3 0xEC810C + +#define mmTPC3_QM_CQ_CFG0_0 0xEC8110 + +#define mmTPC3_QM_CQ_CFG0_1 0xEC8114 + +#define mmTPC3_QM_CQ_CFG0_2 0xEC8118 + +#define mmTPC3_QM_CQ_CFG0_3 0xEC811C + +#define mmTPC3_QM_CQ_CFG0_4 0xEC8120 + +#define mmTPC3_QM_CQ_CFG1_0 0xEC8124 + +#define mmTPC3_QM_CQ_CFG1_1 0xEC8128 + +#define mmTPC3_QM_CQ_CFG1_2 0xEC812C + +#define mmTPC3_QM_CQ_CFG1_3 0xEC8130 + +#define mmTPC3_QM_CQ_CFG1_4 0xEC8134 + +#define mmTPC3_QM_CQ_ARUSER_31_11_0 0xEC8138 + +#define mmTPC3_QM_CQ_ARUSER_31_11_1 0xEC813C + +#define mmTPC3_QM_CQ_ARUSER_31_11_2 0xEC8140 + +#define mmTPC3_QM_CQ_ARUSER_31_11_3 0xEC8144 + +#define mmTPC3_QM_CQ_ARUSER_31_11_4 0xEC8148 + +#define mmTPC3_QM_CQ_STS0_0 0xEC814C + +#define mmTPC3_QM_CQ_STS0_1 0xEC8150 + +#define mmTPC3_QM_CQ_STS0_2 0xEC8154 + +#define mmTPC3_QM_CQ_STS0_3 0xEC8158 + +#define mmTPC3_QM_CQ_STS0_4 0xEC815C + +#define mmTPC3_QM_CQ_STS1_0 0xEC8160 + +#define mmTPC3_QM_CQ_STS1_1 0xEC8164 + +#define mmTPC3_QM_CQ_STS1_2 0xEC8168 + +#define mmTPC3_QM_CQ_STS1_3 0xEC816C + +#define mmTPC3_QM_CQ_STS1_4 0xEC8170 + +#define mmTPC3_QM_CQ_PTR_LO_0 0xEC8174 + +#define mmTPC3_QM_CQ_PTR_HI_0 0xEC8178 + +#define mmTPC3_QM_CQ_TSIZE_0 0xEC817C + +#define mmTPC3_QM_CQ_CTL_0 0xEC8180 + +#define mmTPC3_QM_CQ_PTR_LO_1 0xEC8184 + +#define mmTPC3_QM_CQ_PTR_HI_1 0xEC8188 + +#define mmTPC3_QM_CQ_TSIZE_1 0xEC818C + +#define mmTPC3_QM_CQ_CTL_1 0xEC8190 + +#define mmTPC3_QM_CQ_PTR_LO_2 0xEC8194 + +#define mmTPC3_QM_CQ_PTR_HI_2 0xEC8198 + +#define mmTPC3_QM_CQ_TSIZE_2 0xEC819C + +#define mmTPC3_QM_CQ_CTL_2 0xEC81A0 + +#define mmTPC3_QM_CQ_PTR_LO_3 0xEC81A4 + +#define mmTPC3_QM_CQ_PTR_HI_3 0xEC81A8 + +#define mmTPC3_QM_CQ_TSIZE_3 0xEC81AC + +#define mmTPC3_QM_CQ_CTL_3 0xEC81B0 + +#define mmTPC3_QM_CQ_PTR_LO_4 0xEC81B4 + +#define mmTPC3_QM_CQ_PTR_HI_4 0xEC81B8 + +#define mmTPC3_QM_CQ_TSIZE_4 0xEC81BC + +#define mmTPC3_QM_CQ_CTL_4 0xEC81C0 + +#define mmTPC3_QM_CQ_PTR_LO_STS_0 0xEC81C4 + +#define mmTPC3_QM_CQ_PTR_LO_STS_1 0xEC81C8 + +#define mmTPC3_QM_CQ_PTR_LO_STS_2 0xEC81CC + +#define mmTPC3_QM_CQ_PTR_LO_STS_3 0xEC81D0 + +#define mmTPC3_QM_CQ_PTR_LO_STS_4 0xEC81D4 + +#define mmTPC3_QM_CQ_PTR_HI_STS_0 0xEC81D8 + +#define mmTPC3_QM_CQ_PTR_HI_STS_1 0xEC81DC + +#define mmTPC3_QM_CQ_PTR_HI_STS_2 0xEC81E0 + +#define mmTPC3_QM_CQ_PTR_HI_STS_3 0xEC81E4 + +#define mmTPC3_QM_CQ_PTR_HI_STS_4 0xEC81E8 + +#define mmTPC3_QM_CQ_TSIZE_STS_0 0xEC81EC + +#define mmTPC3_QM_CQ_TSIZE_STS_1 0xEC81F0 + +#define mmTPC3_QM_CQ_TSIZE_STS_2 0xEC81F4 + +#define mmTPC3_QM_CQ_TSIZE_STS_3 0xEC81F8 + +#define mmTPC3_QM_CQ_TSIZE_STS_4 0xEC81FC + +#define mmTPC3_QM_CQ_CTL_STS_0 0xEC8200 + +#define mmTPC3_QM_CQ_CTL_STS_1 0xEC8204 + +#define mmTPC3_QM_CQ_CTL_STS_2 0xEC8208 + +#define mmTPC3_QM_CQ_CTL_STS_3 0xEC820C + +#define mmTPC3_QM_CQ_CTL_STS_4 0xEC8210 + +#define mmTPC3_QM_CQ_IFIFO_CNT_0 0xEC8214 + +#define mmTPC3_QM_CQ_IFIFO_CNT_1 0xEC8218 + +#define mmTPC3_QM_CQ_IFIFO_CNT_2 0xEC821C + +#define mmTPC3_QM_CQ_IFIFO_CNT_3 0xEC8220 + +#define mmTPC3_QM_CQ_IFIFO_CNT_4 0xEC8224 + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_0 0xEC8228 + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_1 0xEC822C + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_2 0xEC8230 + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_3 0xEC8234 + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_4 0xEC8238 + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_0 0xEC823C + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_1 0xEC8240 + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_2 0xEC8244 + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_3 0xEC8248 + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_4 0xEC824C + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_0 0xEC8250 + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_1 0xEC8254 + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_2 0xEC8258 + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_3 0xEC825C + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_4 0xEC8260 + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_0 0xEC8264 + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_1 0xEC8268 + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_2 0xEC826C + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_3 0xEC8270 + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_4 0xEC8274 + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_0 0xEC8278 + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_1 0xEC827C + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_2 0xEC8280 + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_3 0xEC8284 + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_4 0xEC8288 + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_0 0xEC828C + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_1 0xEC8290 + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_2 0xEC8294 + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_3 0xEC8298 + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_4 0xEC829C + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_0 0xEC82A0 + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_1 0xEC82A4 + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_2 0xEC82A8 + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_3 0xEC82AC + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_4 0xEC82B0 + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_0 0xEC82B4 + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_1 0xEC82B8 + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_2 0xEC82BC + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_3 0xEC82C0 + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_4 0xEC82C4 + +#define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_0 0xEC82C8 + +#define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_1 0xEC82CC + +#define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_2 0xEC82D0 + +#define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_3 0xEC82D4 + +#define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_4 0xEC82D8 + +#define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xEC82E0 + +#define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xEC82E4 + +#define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xEC82E8 + +#define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xEC82EC + +#define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xEC82F0 + +#define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xEC82F4 + +#define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xEC82F8 + +#define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xEC82FC + +#define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xEC8300 + +#define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xEC8304 + +#define mmTPC3_QM_CP_FENCE0_RDATA_0 0xEC8308 + +#define mmTPC3_QM_CP_FENCE0_RDATA_1 0xEC830C + +#define mmTPC3_QM_CP_FENCE0_RDATA_2 0xEC8310 + +#define mmTPC3_QM_CP_FENCE0_RDATA_3 0xEC8314 + +#define mmTPC3_QM_CP_FENCE0_RDATA_4 0xEC8318 + +#define mmTPC3_QM_CP_FENCE1_RDATA_0 0xEC831C + +#define mmTPC3_QM_CP_FENCE1_RDATA_1 0xEC8320 + +#define mmTPC3_QM_CP_FENCE1_RDATA_2 0xEC8324 + +#define mmTPC3_QM_CP_FENCE1_RDATA_3 0xEC8328 + +#define mmTPC3_QM_CP_FENCE1_RDATA_4 0xEC832C + +#define mmTPC3_QM_CP_FENCE2_RDATA_0 0xEC8330 + +#define mmTPC3_QM_CP_FENCE2_RDATA_1 0xEC8334 + +#define mmTPC3_QM_CP_FENCE2_RDATA_2 0xEC8338 + +#define mmTPC3_QM_CP_FENCE2_RDATA_3 0xEC833C + +#define mmTPC3_QM_CP_FENCE2_RDATA_4 0xEC8340 + +#define mmTPC3_QM_CP_FENCE3_RDATA_0 0xEC8344 + +#define mmTPC3_QM_CP_FENCE3_RDATA_1 0xEC8348 + +#define mmTPC3_QM_CP_FENCE3_RDATA_2 0xEC834C + +#define mmTPC3_QM_CP_FENCE3_RDATA_3 0xEC8350 + +#define mmTPC3_QM_CP_FENCE3_RDATA_4 0xEC8354 + +#define mmTPC3_QM_CP_FENCE0_CNT_0 0xEC8358 + +#define mmTPC3_QM_CP_FENCE0_CNT_1 0xEC835C + +#define mmTPC3_QM_CP_FENCE0_CNT_2 0xEC8360 + +#define mmTPC3_QM_CP_FENCE0_CNT_3 0xEC8364 + +#define mmTPC3_QM_CP_FENCE0_CNT_4 0xEC8368 + +#define mmTPC3_QM_CP_FENCE1_CNT_0 0xEC836C + +#define mmTPC3_QM_CP_FENCE1_CNT_1 0xEC8370 + +#define mmTPC3_QM_CP_FENCE1_CNT_2 0xEC8374 + +#define mmTPC3_QM_CP_FENCE1_CNT_3 0xEC8378 + +#define mmTPC3_QM_CP_FENCE1_CNT_4 0xEC837C + +#define mmTPC3_QM_CP_FENCE2_CNT_0 0xEC8380 + +#define mmTPC3_QM_CP_FENCE2_CNT_1 0xEC8384 + +#define mmTPC3_QM_CP_FENCE2_CNT_2 0xEC8388 + +#define mmTPC3_QM_CP_FENCE2_CNT_3 0xEC838C + +#define mmTPC3_QM_CP_FENCE2_CNT_4 0xEC8390 + +#define mmTPC3_QM_CP_FENCE3_CNT_0 0xEC8394 + +#define mmTPC3_QM_CP_FENCE3_CNT_1 0xEC8398 + +#define mmTPC3_QM_CP_FENCE3_CNT_2 0xEC839C + +#define mmTPC3_QM_CP_FENCE3_CNT_3 0xEC83A0 + +#define mmTPC3_QM_CP_FENCE3_CNT_4 0xEC83A4 + +#define mmTPC3_QM_CP_STS_0 0xEC83A8 + +#define mmTPC3_QM_CP_STS_1 0xEC83AC + +#define mmTPC3_QM_CP_STS_2 0xEC83B0 + +#define mmTPC3_QM_CP_STS_3 0xEC83B4 + +#define mmTPC3_QM_CP_STS_4 0xEC83B8 + +#define mmTPC3_QM_CP_CURRENT_INST_LO_0 0xEC83BC + +#define mmTPC3_QM_CP_CURRENT_INST_LO_1 0xEC83C0 + +#define mmTPC3_QM_CP_CURRENT_INST_LO_2 0xEC83C4 + +#define mmTPC3_QM_CP_CURRENT_INST_LO_3 0xEC83C8 + +#define mmTPC3_QM_CP_CURRENT_INST_LO_4 0xEC83CC + +#define mmTPC3_QM_CP_CURRENT_INST_HI_0 0xEC83D0 + +#define mmTPC3_QM_CP_CURRENT_INST_HI_1 0xEC83D4 + +#define mmTPC3_QM_CP_CURRENT_INST_HI_2 0xEC83D8 + +#define mmTPC3_QM_CP_CURRENT_INST_HI_3 0xEC83DC + +#define mmTPC3_QM_CP_CURRENT_INST_HI_4 0xEC83E0 + +#define mmTPC3_QM_CP_BARRIER_CFG_0 0xEC83F4 + +#define mmTPC3_QM_CP_BARRIER_CFG_1 0xEC83F8 + +#define mmTPC3_QM_CP_BARRIER_CFG_2 0xEC83FC + +#define mmTPC3_QM_CP_BARRIER_CFG_3 0xEC8400 + +#define mmTPC3_QM_CP_BARRIER_CFG_4 0xEC8404 + +#define mmTPC3_QM_CP_DBG_0_0 0xEC8408 + +#define mmTPC3_QM_CP_DBG_0_1 0xEC840C + +#define mmTPC3_QM_CP_DBG_0_2 0xEC8410 + +#define mmTPC3_QM_CP_DBG_0_3 0xEC8414 + +#define mmTPC3_QM_CP_DBG_0_4 0xEC8418 + +#define mmTPC3_QM_CP_ARUSER_31_11_0 0xEC841C + +#define mmTPC3_QM_CP_ARUSER_31_11_1 0xEC8420 + +#define mmTPC3_QM_CP_ARUSER_31_11_2 0xEC8424 + +#define mmTPC3_QM_CP_ARUSER_31_11_3 0xEC8428 + +#define mmTPC3_QM_CP_ARUSER_31_11_4 0xEC842C + +#define mmTPC3_QM_CP_AWUSER_31_11_0 0xEC8430 + +#define mmTPC3_QM_CP_AWUSER_31_11_1 0xEC8434 + +#define mmTPC3_QM_CP_AWUSER_31_11_2 0xEC8438 + +#define mmTPC3_QM_CP_AWUSER_31_11_3 0xEC843C + +#define mmTPC3_QM_CP_AWUSER_31_11_4 0xEC8440 + +#define mmTPC3_QM_ARB_CFG_0 0xEC8A00 + +#define mmTPC3_QM_ARB_CHOISE_Q_PUSH 0xEC8A04 + +#define mmTPC3_QM_ARB_WRR_WEIGHT_0 0xEC8A08 + +#define mmTPC3_QM_ARB_WRR_WEIGHT_1 0xEC8A0C + +#define mmTPC3_QM_ARB_WRR_WEIGHT_2 0xEC8A10 + +#define mmTPC3_QM_ARB_WRR_WEIGHT_3 0xEC8A14 + +#define mmTPC3_QM_ARB_CFG_1 0xEC8A18 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_0 0xEC8A20 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_1 0xEC8A24 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_2 0xEC8A28 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_3 0xEC8A2C + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_4 0xEC8A30 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_5 0xEC8A34 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_6 0xEC8A38 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_7 0xEC8A3C + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_8 0xEC8A40 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_9 0xEC8A44 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_10 0xEC8A48 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_11 0xEC8A4C + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_12 0xEC8A50 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_13 0xEC8A54 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_14 0xEC8A58 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_15 0xEC8A5C + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_16 0xEC8A60 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_17 0xEC8A64 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_18 0xEC8A68 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_19 0xEC8A6C + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_20 0xEC8A70 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_21 0xEC8A74 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_22 0xEC8A78 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_23 0xEC8A7C + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_24 0xEC8A80 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_25 0xEC8A84 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_26 0xEC8A88 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_27 0xEC8A8C + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_28 0xEC8A90 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_29 0xEC8A94 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_30 0xEC8A98 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_31 0xEC8A9C + +#define mmTPC3_QM_ARB_MST_CRED_INC 0xEC8AA0 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xEC8AA4 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xEC8AA8 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xEC8AAC + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xEC8AB0 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xEC8AB4 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xEC8AB8 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xEC8ABC + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xEC8AC0 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xEC8AC4 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xEC8AC8 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xEC8ACC + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xEC8AD0 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xEC8AD4 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xEC8AD8 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xEC8ADC + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xEC8AE0 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xEC8AE4 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xEC8AE8 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xEC8AEC + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xEC8AF0 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xEC8AF4 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xEC8AF8 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xEC8AFC + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xEC8B00 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xEC8B04 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xEC8B08 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xEC8B0C + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xEC8B10 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xEC8B14 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xEC8B18 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xEC8B1C + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xEC8B20 + +#define mmTPC3_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xEC8B28 + +#define mmTPC3_QM_ARB_MST_SLAVE_EN 0xEC8B2C + +#define mmTPC3_QM_ARB_MST_QUIET_PER 0xEC8B34 + +#define mmTPC3_QM_ARB_SLV_CHOISE_WDT 0xEC8B38 + +#define mmTPC3_QM_ARB_SLV_ID 0xEC8B3C + +#define mmTPC3_QM_ARB_MSG_MAX_INFLIGHT 0xEC8B44 + +#define mmTPC3_QM_ARB_MSG_AWUSER_31_11 0xEC8B48 + +#define mmTPC3_QM_ARB_MSG_AWUSER_SEC_PROP 0xEC8B4C + +#define mmTPC3_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xEC8B50 + +#define mmTPC3_QM_ARB_BASE_LO 0xEC8B54 + +#define mmTPC3_QM_ARB_BASE_HI 0xEC8B58 + +#define mmTPC3_QM_ARB_STATE_STS 0xEC8B80 + +#define mmTPC3_QM_ARB_CHOISE_FULLNESS_STS 0xEC8B84 + +#define mmTPC3_QM_ARB_MSG_STS 0xEC8B88 + +#define mmTPC3_QM_ARB_SLV_CHOISE_Q_HEAD 0xEC8B8C + +#define mmTPC3_QM_ARB_ERR_CAUSE 0xEC8B9C + +#define mmTPC3_QM_ARB_ERR_MSG_EN 0xEC8BA0 + +#define mmTPC3_QM_ARB_ERR_STS_DRP 0xEC8BA8 + +#define mmTPC3_QM_ARB_MST_CRED_STS_0 0xEC8BB0 + +#define mmTPC3_QM_ARB_MST_CRED_STS_1 0xEC8BB4 + +#define mmTPC3_QM_ARB_MST_CRED_STS_2 0xEC8BB8 + +#define mmTPC3_QM_ARB_MST_CRED_STS_3 0xEC8BBC + +#define mmTPC3_QM_ARB_MST_CRED_STS_4 0xEC8BC0 + +#define mmTPC3_QM_ARB_MST_CRED_STS_5 0xEC8BC4 + +#define mmTPC3_QM_ARB_MST_CRED_STS_6 0xEC8BC8 + +#define mmTPC3_QM_ARB_MST_CRED_STS_7 0xEC8BCC + +#define mmTPC3_QM_ARB_MST_CRED_STS_8 0xEC8BD0 + +#define mmTPC3_QM_ARB_MST_CRED_STS_9 0xEC8BD4 + +#define mmTPC3_QM_ARB_MST_CRED_STS_10 0xEC8BD8 + +#define mmTPC3_QM_ARB_MST_CRED_STS_11 0xEC8BDC + +#define mmTPC3_QM_ARB_MST_CRED_STS_12 0xEC8BE0 + +#define mmTPC3_QM_ARB_MST_CRED_STS_13 0xEC8BE4 + +#define mmTPC3_QM_ARB_MST_CRED_STS_14 0xEC8BE8 + +#define mmTPC3_QM_ARB_MST_CRED_STS_15 0xEC8BEC + +#define mmTPC3_QM_ARB_MST_CRED_STS_16 0xEC8BF0 + +#define mmTPC3_QM_ARB_MST_CRED_STS_17 0xEC8BF4 + +#define mmTPC3_QM_ARB_MST_CRED_STS_18 0xEC8BF8 + +#define mmTPC3_QM_ARB_MST_CRED_STS_19 0xEC8BFC + +#define mmTPC3_QM_ARB_MST_CRED_STS_20 0xEC8C00 + +#define mmTPC3_QM_ARB_MST_CRED_STS_21 0xEC8C04 + +#define mmTPC3_QM_ARB_MST_CRED_STS_22 0xEC8C08 + +#define mmTPC3_QM_ARB_MST_CRED_STS_23 0xEC8C0C + +#define mmTPC3_QM_ARB_MST_CRED_STS_24 0xEC8C10 + +#define mmTPC3_QM_ARB_MST_CRED_STS_25 0xEC8C14 + +#define mmTPC3_QM_ARB_MST_CRED_STS_26 0xEC8C18 + +#define mmTPC3_QM_ARB_MST_CRED_STS_27 0xEC8C1C + +#define mmTPC3_QM_ARB_MST_CRED_STS_28 0xEC8C20 + +#define mmTPC3_QM_ARB_MST_CRED_STS_29 0xEC8C24 + +#define mmTPC3_QM_ARB_MST_CRED_STS_30 0xEC8C28 + +#define mmTPC3_QM_ARB_MST_CRED_STS_31 0xEC8C2C + +#define mmTPC3_QM_CGM_CFG 0xEC8C70 + +#define mmTPC3_QM_CGM_STS 0xEC8C74 + +#define mmTPC3_QM_CGM_CFG1 0xEC8C78 + +#define mmTPC3_QM_LOCAL_RANGE_BASE 0xEC8C80 + +#define mmTPC3_QM_LOCAL_RANGE_SIZE 0xEC8C84 + +#define mmTPC3_QM_CSMR_STRICT_PRIO_CFG 0xEC8C90 + +#define mmTPC3_QM_HBW_RD_RATE_LIM_CFG_1 0xEC8C94 + +#define mmTPC3_QM_LBW_WR_RATE_LIM_CFG_0 0xEC8C98 + +#define mmTPC3_QM_LBW_WR_RATE_LIM_CFG_1 0xEC8C9C + +#define mmTPC3_QM_HBW_RD_RATE_LIM_CFG_0 0xEC8CA0 + +#define mmTPC3_QM_GLBL_AXCACHE 0xEC8CA4 + +#define mmTPC3_QM_IND_GW_APB_CFG 0xEC8CB0 + +#define mmTPC3_QM_IND_GW_APB_WDATA 0xEC8CB4 + +#define mmTPC3_QM_IND_GW_APB_RDATA 0xEC8CB8 + +#define mmTPC3_QM_IND_GW_APB_STATUS 0xEC8CBC + +#define mmTPC3_QM_GLBL_ERR_ADDR_LO 0xEC8CD0 + +#define mmTPC3_QM_GLBL_ERR_ADDR_HI 0xEC8CD4 + +#define mmTPC3_QM_GLBL_ERR_WDATA 0xEC8CD8 + +#define mmTPC3_QM_GLBL_MEM_INIT_BUSY 0xEC8D00 + +#endif /* ASIC_REG_TPC3_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc4_cfg_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc4_cfg_regs.h new file mode 100644 index 000000000000..7a9447f39a74 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc4_cfg_regs.h @@ -0,0 +1,1226 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC4_CFG_REGS_H_ +#define ASIC_REG_TPC4_CFG_REGS_H_ + +/* + ***************************************** + * TPC4_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC4_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF06400 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF06404 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF06408 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF0640C + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF06410 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF06414 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF06418 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF0641C + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF06420 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF06424 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF06428 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF0642C + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF06430 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF06434 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF06438 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF0643C + +#define mmTPC4_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF06440 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF06444 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF06448 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF0644C + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF06450 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF06454 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF06458 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF0645C + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF06460 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF06464 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF06468 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF0646C + +#define mmTPC4_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF06470 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF06474 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF06478 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF0647C + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF06480 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF06484 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF06488 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF0648C + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF06490 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF06494 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF06498 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF0649C + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF064A0 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF064A4 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF064A8 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF064AC + +#define mmTPC4_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF064B0 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF064B4 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF064B8 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF064BC + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF064C0 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF064C4 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF064C8 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF064CC + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF064D0 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF064D4 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF064D8 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF064DC + +#define mmTPC4_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF064E0 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF064E4 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF064E8 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF064EC + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF064F0 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF064F4 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF064F8 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF064FC + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF06500 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF06504 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF06508 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF0650C + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF06510 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF06514 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF06518 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF0651C + +#define mmTPC4_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF06520 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF06524 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF06528 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF0652C + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF06530 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF06534 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF06538 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF0653C + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF06540 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF06544 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF06548 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF0654C + +#define mmTPC4_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF06550 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF06554 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF06558 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF0655C + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF06560 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF06564 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF06568 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF0656C + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF06570 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF06574 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF06578 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF0657C + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF06580 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF06584 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF06588 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF0658C + +#define mmTPC4_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF06590 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF06594 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF06598 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF0659C + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF065A0 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF065A4 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF065A8 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF065AC + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF065B0 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF065B4 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF065B8 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF065BC + +#define mmTPC4_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xF065C0 + +#define mmTPC4_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xF065C4 + +#define mmTPC4_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xF065C8 + +#define mmTPC4_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xF065CC + +#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xF065D0 + +#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xF065D4 + +#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xF065D8 + +#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xF065DC + +#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xF065E0 + +#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xF065E4 + +#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xF065E8 + +#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xF065EC + +#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xF065F0 + +#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xF065F4 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xF065F8 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xF065FC + +#define mmTPC4_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xF06600 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xF06604 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xF06608 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xF0660C + +#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xF06610 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xF06614 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xF06618 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xF0661C + +#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xF06620 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xF06624 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xF06628 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xF0662C + +#define mmTPC4_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xF06630 + +#define mmTPC4_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xF06634 + +#define mmTPC4_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xF06638 + +#define mmTPC4_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xF0663C + +#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xF06640 + +#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xF06644 + +#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xF06648 + +#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xF0664C + +#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xF06650 + +#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xF06654 + +#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xF06658 + +#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xF0665C + +#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xF06660 + +#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xF06664 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xF06668 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xF0666C + +#define mmTPC4_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xF06670 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xF06674 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xF06678 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xF0667C + +#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xF06680 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xF06684 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xF06688 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xF0668C + +#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xF06690 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xF06694 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xF06698 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xF0669C + +#define mmTPC4_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xF066A0 + +#define mmTPC4_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xF066A4 + +#define mmTPC4_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xF066A8 + +#define mmTPC4_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xF066AC + +#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xF066B0 + +#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xF066B4 + +#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xF066B8 + +#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xF066BC + +#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xF066C0 + +#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xF066C4 + +#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xF066C8 + +#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xF066CC + +#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xF066D0 + +#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xF066D4 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xF066D8 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xF066DC + +#define mmTPC4_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xF066E0 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xF066E4 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xF066E8 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xF066EC + +#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xF066F0 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xF066F4 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xF066F8 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xF066FC + +#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xF06700 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xF06704 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xF06708 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xF0670C + +#define mmTPC4_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xF06710 + +#define mmTPC4_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xF06714 + +#define mmTPC4_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xF06718 + +#define mmTPC4_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xF0671C + +#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xF06720 + +#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xF06724 + +#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xF06728 + +#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xF0672C + +#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xF06730 + +#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xF06734 + +#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xF06738 + +#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xF0673C + +#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xF06740 + +#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xF06744 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xF06748 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xF0674C + +#define mmTPC4_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xF06750 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xF06754 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xF06758 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xF0675C + +#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xF06760 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xF06764 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xF06768 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xF0676C + +#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xF06770 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xF06774 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xF06778 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xF0677C + +#define mmTPC4_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF06780 + +#define mmTPC4_CFG_KERNEL_SYNC_OBJECT_ADDR 0xF06784 + +#define mmTPC4_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF06788 + +#define mmTPC4_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF0678C + +#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_0 0xF06790 + +#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_0 0xF06794 + +#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_1 0xF06798 + +#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_1 0xF0679C + +#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_2 0xF067A0 + +#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_2 0xF067A4 + +#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_3 0xF067A8 + +#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_3 0xF067AC + +#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_4 0xF067B0 + +#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_4 0xF067B4 + +#define mmTPC4_CFG_KERNEL_KERNEL_CONFIG 0xF067B8 + +#define mmTPC4_CFG_KERNEL_KERNEL_ID 0xF067BC + +#define mmTPC4_CFG_KERNEL_SRF_0 0xF067C0 + +#define mmTPC4_CFG_KERNEL_SRF_1 0xF067C4 + +#define mmTPC4_CFG_KERNEL_SRF_2 0xF067C8 + +#define mmTPC4_CFG_KERNEL_SRF_3 0xF067CC + +#define mmTPC4_CFG_KERNEL_SRF_4 0xF067D0 + +#define mmTPC4_CFG_KERNEL_SRF_5 0xF067D4 + +#define mmTPC4_CFG_KERNEL_SRF_6 0xF067D8 + +#define mmTPC4_CFG_KERNEL_SRF_7 0xF067DC + +#define mmTPC4_CFG_KERNEL_SRF_8 0xF067E0 + +#define mmTPC4_CFG_KERNEL_SRF_9 0xF067E4 + +#define mmTPC4_CFG_KERNEL_SRF_10 0xF067E8 + +#define mmTPC4_CFG_KERNEL_SRF_11 0xF067EC + +#define mmTPC4_CFG_KERNEL_SRF_12 0xF067F0 + +#define mmTPC4_CFG_KERNEL_SRF_13 0xF067F4 + +#define mmTPC4_CFG_KERNEL_SRF_14 0xF067F8 + +#define mmTPC4_CFG_KERNEL_SRF_15 0xF067FC + +#define mmTPC4_CFG_KERNEL_SRF_16 0xF06800 + +#define mmTPC4_CFG_KERNEL_SRF_17 0xF06804 + +#define mmTPC4_CFG_KERNEL_SRF_18 0xF06808 + +#define mmTPC4_CFG_KERNEL_SRF_19 0xF0680C + +#define mmTPC4_CFG_KERNEL_SRF_20 0xF06810 + +#define mmTPC4_CFG_KERNEL_SRF_21 0xF06814 + +#define mmTPC4_CFG_KERNEL_SRF_22 0xF06818 + +#define mmTPC4_CFG_KERNEL_SRF_23 0xF0681C + +#define mmTPC4_CFG_KERNEL_SRF_24 0xF06820 + +#define mmTPC4_CFG_KERNEL_SRF_25 0xF06824 + +#define mmTPC4_CFG_KERNEL_SRF_26 0xF06828 + +#define mmTPC4_CFG_KERNEL_SRF_27 0xF0682C + +#define mmTPC4_CFG_KERNEL_SRF_28 0xF06830 + +#define mmTPC4_CFG_KERNEL_SRF_29 0xF06834 + +#define mmTPC4_CFG_KERNEL_SRF_30 0xF06838 + +#define mmTPC4_CFG_KERNEL_SRF_31 0xF0683C + +#define mmTPC4_CFG_ROUND_CSR 0xF068FC + +#define mmTPC4_CFG_PROT 0xF06900 + +#define mmTPC4_CFG_SEMAPHORE 0xF06908 + +#define mmTPC4_CFG_VFLAGS 0xF0690C + +#define mmTPC4_CFG_SFLAGS 0xF06910 + +#define mmTPC4_CFG_LFSR_POLYNOM 0xF06918 + +#define mmTPC4_CFG_STATUS 0xF0691C + +#define mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH 0xF06920 + +#define mmTPC4_CFG_CFG_SUBTRACT_VALUE 0xF06924 + +#define mmTPC4_CFG_SM_BASE_ADDRESS_HIGH 0xF0692C + +#define mmTPC4_CFG_TPC_CMD 0xF06930 + +#define mmTPC4_CFG_TPC_EXECUTE 0xF06938 + +#define mmTPC4_CFG_TPC_STALL 0xF0693C + +#define mmTPC4_CFG_ICACHE_BASE_ADDERESS_LOW 0xF06940 + +#define mmTPC4_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF06944 + +#define mmTPC4_CFG_RD_RATE_LIMIT 0xF06948 + +#define mmTPC4_CFG_WR_RATE_LIMIT 0xF06950 + +#define mmTPC4_CFG_MSS_CONFIG 0xF06954 + +#define mmTPC4_CFG_TPC_INTR_CAUSE 0xF06958 + +#define mmTPC4_CFG_TPC_INTR_MASK 0xF0695C + +#define mmTPC4_CFG_WQ_CREDITS 0xF06960 + +#define mmTPC4_CFG_ARUSER_LO 0xF06964 + +#define mmTPC4_CFG_ARUSER_HI 0xF06968 + +#define mmTPC4_CFG_AWUSER_LO 0xF0696C + +#define mmTPC4_CFG_AWUSER_HI 0xF06970 + +#define mmTPC4_CFG_OPCODE_EXEC 0xF06974 + +#define mmTPC4_CFG_LUT_FUNC32_BASE_ADDR_LO 0xF06978 + +#define mmTPC4_CFG_LUT_FUNC32_BASE_ADDR_HI 0xF0697C + +#define mmTPC4_CFG_LUT_FUNC64_BASE_ADDR_LO 0xF06980 + +#define mmTPC4_CFG_LUT_FUNC64_BASE_ADDR_HI 0xF06984 + +#define mmTPC4_CFG_LUT_FUNC128_BASE_ADDR_LO 0xF06988 + +#define mmTPC4_CFG_LUT_FUNC128_BASE_ADDR_HI 0xF0698C + +#define mmTPC4_CFG_LUT_FUNC256_BASE_ADDR_LO 0xF06990 + +#define mmTPC4_CFG_LUT_FUNC256_BASE_ADDR_HI 0xF06994 + +#define mmTPC4_CFG_TSB_CFG_MAX_SIZE 0xF06998 + +#define mmTPC4_CFG_TSB_CFG 0xF0699C + +#define mmTPC4_CFG_DBGMEM_ADD 0xF069A0 + +#define mmTPC4_CFG_DBGMEM_DATA_WR 0xF069A4 + +#define mmTPC4_CFG_DBGMEM_DATA_RD 0xF069A8 + +#define mmTPC4_CFG_DBGMEM_CTRL 0xF069AC + +#define mmTPC4_CFG_DBGMEM_RC 0xF069B0 + +#define mmTPC4_CFG_TSB_INFLIGHT_CNTR 0xF069B4 + +#define mmTPC4_CFG_WQ_INFLIGHT_CNTR 0xF069B8 + +#define mmTPC4_CFG_WQ_LBW_TOTAL_CNTR 0xF069BC + +#define mmTPC4_CFG_WQ_HBW_TOTAL_CNTR 0xF069C0 + +#define mmTPC4_CFG_IRQ_OCCOUPY_CNTR 0xF069C4 + +#define mmTPC4_CFG_FUNC_MBIST_CNTRL 0xF069D0 + +#define mmTPC4_CFG_FUNC_MBIST_PAT 0xF069D4 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_0 0xF069D8 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_1 0xF069DC + +#define mmTPC4_CFG_FUNC_MBIST_MEM_2 0xF069E0 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_3 0xF069E4 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_4 0xF069E8 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_5 0xF069EC + +#define mmTPC4_CFG_FUNC_MBIST_MEM_6 0xF069F0 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_7 0xF069F4 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_8 0xF069F8 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_9 0xF069FC + +#define mmTPC4_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF06A00 + +#define mmTPC4_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF06A04 + +#define mmTPC4_CFG_QM_TENSOR_0_PADDING_VALUE 0xF06A08 + +#define mmTPC4_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF06A0C + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF06A10 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF06A14 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF06A18 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF06A1C + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF06A20 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF06A24 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF06A28 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF06A2C + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF06A30 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF06A34 + +#define mmTPC4_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF06A38 + +#define mmTPC4_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF06A3C + +#define mmTPC4_CFG_QM_TENSOR_1_PADDING_VALUE 0xF06A40 + +#define mmTPC4_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF06A44 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF06A48 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF06A4C + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF06A50 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF06A54 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF06A58 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF06A5C + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF06A60 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF06A64 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF06A68 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF06A6C + +#define mmTPC4_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF06A70 + +#define mmTPC4_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF06A74 + +#define mmTPC4_CFG_QM_TENSOR_2_PADDING_VALUE 0xF06A78 + +#define mmTPC4_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF06A7C + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF06A80 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF06A84 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF06A88 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF06A8C + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF06A90 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF06A94 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF06A98 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF06A9C + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF06AA0 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF06AA4 + +#define mmTPC4_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF06AA8 + +#define mmTPC4_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF06AAC + +#define mmTPC4_CFG_QM_TENSOR_3_PADDING_VALUE 0xF06AB0 + +#define mmTPC4_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF06AB4 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF06AB8 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF06ABC + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF06AC0 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF06AC4 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF06AC8 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF06ACC + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF06AD0 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF06AD4 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF06AD8 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF06ADC + +#define mmTPC4_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF06AE0 + +#define mmTPC4_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF06AE4 + +#define mmTPC4_CFG_QM_TENSOR_4_PADDING_VALUE 0xF06AE8 + +#define mmTPC4_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF06AEC + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF06AF0 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF06AF4 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF06AF8 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF06AFC + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF06B00 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF06B04 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF06B08 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF06B0C + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF06B10 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF06B14 + +#define mmTPC4_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF06B18 + +#define mmTPC4_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF06B1C + +#define mmTPC4_CFG_QM_TENSOR_5_PADDING_VALUE 0xF06B20 + +#define mmTPC4_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF06B24 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF06B28 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF06B2C + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF06B30 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF06B34 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF06B38 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF06B3C + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF06B40 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF06B44 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF06B48 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF06B4C + +#define mmTPC4_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF06B50 + +#define mmTPC4_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF06B54 + +#define mmTPC4_CFG_QM_TENSOR_6_PADDING_VALUE 0xF06B58 + +#define mmTPC4_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF06B5C + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF06B60 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF06B64 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF06B68 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF06B6C + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF06B70 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF06B74 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF06B78 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF06B7C + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF06B80 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF06B84 + +#define mmTPC4_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF06B88 + +#define mmTPC4_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF06B8C + +#define mmTPC4_CFG_QM_TENSOR_7_PADDING_VALUE 0xF06B90 + +#define mmTPC4_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF06B94 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF06B98 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF06B9C + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF06BA0 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF06BA4 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF06BA8 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF06BAC + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF06BB0 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF06BB4 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF06BB8 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF06BBC + +#define mmTPC4_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xF06BC0 + +#define mmTPC4_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xF06BC4 + +#define mmTPC4_CFG_QM_TENSOR_8_PADDING_VALUE 0xF06BC8 + +#define mmTPC4_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xF06BCC + +#define mmTPC4_CFG_QM_TENSOR_8_DIM_0_SIZE 0xF06BD0 + +#define mmTPC4_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xF06BD4 + +#define mmTPC4_CFG_QM_TENSOR_8_DIM_1_SIZE 0xF06BD8 + +#define mmTPC4_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xF06BDC + +#define mmTPC4_CFG_QM_TENSOR_8_DIM_2_SIZE 0xF06BE0 + +#define mmTPC4_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xF06BE4 + +#define mmTPC4_CFG_QM_TENSOR_8_DIM_3_SIZE 0xF06BE8 + +#define mmTPC4_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xF06BEC + +#define mmTPC4_CFG_QM_TENSOR_8_DIM_4_SIZE 0xF06BF0 + +#define mmTPC4_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xF06BF4 + +#define mmTPC4_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xF06BF8 + +#define mmTPC4_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xF06BFC + +#define mmTPC4_CFG_QM_TENSOR_9_PADDING_VALUE 0xF06C00 + +#define mmTPC4_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xF06C04 + +#define mmTPC4_CFG_QM_TENSOR_9_DIM_0_SIZE 0xF06C08 + +#define mmTPC4_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xF06C0C + +#define mmTPC4_CFG_QM_TENSOR_9_DIM_1_SIZE 0xF06C10 + +#define mmTPC4_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xF06C14 + +#define mmTPC4_CFG_QM_TENSOR_9_DIM_2_SIZE 0xF06C18 + +#define mmTPC4_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xF06C1C + +#define mmTPC4_CFG_QM_TENSOR_9_DIM_3_SIZE 0xF06C20 + +#define mmTPC4_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xF06C24 + +#define mmTPC4_CFG_QM_TENSOR_9_DIM_4_SIZE 0xF06C28 + +#define mmTPC4_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xF06C2C + +#define mmTPC4_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xF06C30 + +#define mmTPC4_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xF06C34 + +#define mmTPC4_CFG_QM_TENSOR_10_PADDING_VALUE 0xF06C38 + +#define mmTPC4_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xF06C3C + +#define mmTPC4_CFG_QM_TENSOR_10_DIM_0_SIZE 0xF06C40 + +#define mmTPC4_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xF06C44 + +#define mmTPC4_CFG_QM_TENSOR_10_DIM_1_SIZE 0xF06C48 + +#define mmTPC4_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xF06C4C + +#define mmTPC4_CFG_QM_TENSOR_10_DIM_2_SIZE 0xF06C50 + +#define mmTPC4_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xF06C54 + +#define mmTPC4_CFG_QM_TENSOR_10_DIM_3_SIZE 0xF06C58 + +#define mmTPC4_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xF06C5C + +#define mmTPC4_CFG_QM_TENSOR_10_DIM_4_SIZE 0xF06C60 + +#define mmTPC4_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xF06C64 + +#define mmTPC4_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xF06C68 + +#define mmTPC4_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xF06C6C + +#define mmTPC4_CFG_QM_TENSOR_11_PADDING_VALUE 0xF06C70 + +#define mmTPC4_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xF06C74 + +#define mmTPC4_CFG_QM_TENSOR_11_DIM_0_SIZE 0xF06C78 + +#define mmTPC4_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xF06C7C + +#define mmTPC4_CFG_QM_TENSOR_11_DIM_1_SIZE 0xF06C80 + +#define mmTPC4_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xF06C84 + +#define mmTPC4_CFG_QM_TENSOR_11_DIM_2_SIZE 0xF06C88 + +#define mmTPC4_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xF06C8C + +#define mmTPC4_CFG_QM_TENSOR_11_DIM_3_SIZE 0xF06C90 + +#define mmTPC4_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xF06C94 + +#define mmTPC4_CFG_QM_TENSOR_11_DIM_4_SIZE 0xF06C98 + +#define mmTPC4_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xF06C9C + +#define mmTPC4_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xF06CA0 + +#define mmTPC4_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xF06CA4 + +#define mmTPC4_CFG_QM_TENSOR_12_PADDING_VALUE 0xF06CA8 + +#define mmTPC4_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xF06CAC + +#define mmTPC4_CFG_QM_TENSOR_12_DIM_0_SIZE 0xF06CB0 + +#define mmTPC4_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xF06CB4 + +#define mmTPC4_CFG_QM_TENSOR_12_DIM_1_SIZE 0xF06CB8 + +#define mmTPC4_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xF06CBC + +#define mmTPC4_CFG_QM_TENSOR_12_DIM_2_SIZE 0xF06CC0 + +#define mmTPC4_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xF06CC4 + +#define mmTPC4_CFG_QM_TENSOR_12_DIM_3_SIZE 0xF06CC8 + +#define mmTPC4_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xF06CCC + +#define mmTPC4_CFG_QM_TENSOR_12_DIM_4_SIZE 0xF06CD0 + +#define mmTPC4_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xF06CD4 + +#define mmTPC4_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xF06CD8 + +#define mmTPC4_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xF06CDC + +#define mmTPC4_CFG_QM_TENSOR_13_PADDING_VALUE 0xF06CE0 + +#define mmTPC4_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xF06CE4 + +#define mmTPC4_CFG_QM_TENSOR_13_DIM_0_SIZE 0xF06CE8 + +#define mmTPC4_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xF06CEC + +#define mmTPC4_CFG_QM_TENSOR_13_DIM_1_SIZE 0xF06CF0 + +#define mmTPC4_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xF06CF4 + +#define mmTPC4_CFG_QM_TENSOR_13_DIM_2_SIZE 0xF06CF8 + +#define mmTPC4_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xF06CFC + +#define mmTPC4_CFG_QM_TENSOR_13_DIM_3_SIZE 0xF06D00 + +#define mmTPC4_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xF06D04 + +#define mmTPC4_CFG_QM_TENSOR_13_DIM_4_SIZE 0xF06D08 + +#define mmTPC4_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xF06D0C + +#define mmTPC4_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xF06D10 + +#define mmTPC4_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xF06D14 + +#define mmTPC4_CFG_QM_TENSOR_14_PADDING_VALUE 0xF06D18 + +#define mmTPC4_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xF06D1C + +#define mmTPC4_CFG_QM_TENSOR_14_DIM_0_SIZE 0xF06D20 + +#define mmTPC4_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xF06D24 + +#define mmTPC4_CFG_QM_TENSOR_14_DIM_1_SIZE 0xF06D28 + +#define mmTPC4_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xF06D2C + +#define mmTPC4_CFG_QM_TENSOR_14_DIM_2_SIZE 0xF06D30 + +#define mmTPC4_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xF06D34 + +#define mmTPC4_CFG_QM_TENSOR_14_DIM_3_SIZE 0xF06D38 + +#define mmTPC4_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xF06D3C + +#define mmTPC4_CFG_QM_TENSOR_14_DIM_4_SIZE 0xF06D40 + +#define mmTPC4_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xF06D44 + +#define mmTPC4_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xF06D48 + +#define mmTPC4_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xF06D4C + +#define mmTPC4_CFG_QM_TENSOR_15_PADDING_VALUE 0xF06D50 + +#define mmTPC4_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xF06D54 + +#define mmTPC4_CFG_QM_TENSOR_15_DIM_0_SIZE 0xF06D58 + +#define mmTPC4_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xF06D5C + +#define mmTPC4_CFG_QM_TENSOR_15_DIM_1_SIZE 0xF06D60 + +#define mmTPC4_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xF06D64 + +#define mmTPC4_CFG_QM_TENSOR_15_DIM_2_SIZE 0xF06D68 + +#define mmTPC4_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xF06D6C + +#define mmTPC4_CFG_QM_TENSOR_15_DIM_3_SIZE 0xF06D70 + +#define mmTPC4_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xF06D74 + +#define mmTPC4_CFG_QM_TENSOR_15_DIM_4_SIZE 0xF06D78 + +#define mmTPC4_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xF06D7C + +#define mmTPC4_CFG_QM_SYNC_OBJECT_MESSAGE 0xF06D80 + +#define mmTPC4_CFG_QM_SYNC_OBJECT_ADDR 0xF06D84 + +#define mmTPC4_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF06D88 + +#define mmTPC4_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF06D8C + +#define mmTPC4_CFG_QM_TID_BASE_DIM_0 0xF06D90 + +#define mmTPC4_CFG_QM_TID_SIZE_DIM_0 0xF06D94 + +#define mmTPC4_CFG_QM_TID_BASE_DIM_1 0xF06D98 + +#define mmTPC4_CFG_QM_TID_SIZE_DIM_1 0xF06D9C + +#define mmTPC4_CFG_QM_TID_BASE_DIM_2 0xF06DA0 + +#define mmTPC4_CFG_QM_TID_SIZE_DIM_2 0xF06DA4 + +#define mmTPC4_CFG_QM_TID_BASE_DIM_3 0xF06DA8 + +#define mmTPC4_CFG_QM_TID_SIZE_DIM_3 0xF06DAC + +#define mmTPC4_CFG_QM_TID_BASE_DIM_4 0xF06DB0 + +#define mmTPC4_CFG_QM_TID_SIZE_DIM_4 0xF06DB4 + +#define mmTPC4_CFG_QM_KERNEL_CONFIG 0xF06DB8 + +#define mmTPC4_CFG_QM_KERNEL_ID 0xF06DBC + +#define mmTPC4_CFG_QM_SRF_0 0xF06DC0 + +#define mmTPC4_CFG_QM_SRF_1 0xF06DC4 + +#define mmTPC4_CFG_QM_SRF_2 0xF06DC8 + +#define mmTPC4_CFG_QM_SRF_3 0xF06DCC + +#define mmTPC4_CFG_QM_SRF_4 0xF06DD0 + +#define mmTPC4_CFG_QM_SRF_5 0xF06DD4 + +#define mmTPC4_CFG_QM_SRF_6 0xF06DD8 + +#define mmTPC4_CFG_QM_SRF_7 0xF06DDC + +#define mmTPC4_CFG_QM_SRF_8 0xF06DE0 + +#define mmTPC4_CFG_QM_SRF_9 0xF06DE4 + +#define mmTPC4_CFG_QM_SRF_10 0xF06DE8 + +#define mmTPC4_CFG_QM_SRF_11 0xF06DEC + +#define mmTPC4_CFG_QM_SRF_12 0xF06DF0 + +#define mmTPC4_CFG_QM_SRF_13 0xF06DF4 + +#define mmTPC4_CFG_QM_SRF_14 0xF06DF8 + +#define mmTPC4_CFG_QM_SRF_15 0xF06DFC + +#define mmTPC4_CFG_QM_SRF_16 0xF06E00 + +#define mmTPC4_CFG_QM_SRF_17 0xF06E04 + +#define mmTPC4_CFG_QM_SRF_18 0xF06E08 + +#define mmTPC4_CFG_QM_SRF_19 0xF06E0C + +#define mmTPC4_CFG_QM_SRF_20 0xF06E10 + +#define mmTPC4_CFG_QM_SRF_21 0xF06E14 + +#define mmTPC4_CFG_QM_SRF_22 0xF06E18 + +#define mmTPC4_CFG_QM_SRF_23 0xF06E1C + +#define mmTPC4_CFG_QM_SRF_24 0xF06E20 + +#define mmTPC4_CFG_QM_SRF_25 0xF06E24 + +#define mmTPC4_CFG_QM_SRF_26 0xF06E28 + +#define mmTPC4_CFG_QM_SRF_27 0xF06E2C + +#define mmTPC4_CFG_QM_SRF_28 0xF06E30 + +#define mmTPC4_CFG_QM_SRF_29 0xF06E34 + +#define mmTPC4_CFG_QM_SRF_30 0xF06E38 + +#define mmTPC4_CFG_QM_SRF_31 0xF06E3C + +#endif /* ASIC_REG_TPC4_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc4_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc4_qm_regs.h new file mode 100644 index 000000000000..80e63402f6e0 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc4_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC4_QM_REGS_H_ +#define ASIC_REG_TPC4_QM_REGS_H_ + +/* + ***************************************** + * TPC4_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC4_QM_GLBL_CFG0 0xF08000 + +#define mmTPC4_QM_GLBL_CFG1 0xF08004 + +#define mmTPC4_QM_GLBL_PROT 0xF08008 + +#define mmTPC4_QM_GLBL_ERR_CFG 0xF0800C + +#define mmTPC4_QM_GLBL_SECURE_PROPS_0 0xF08010 + +#define mmTPC4_QM_GLBL_SECURE_PROPS_1 0xF08014 + +#define mmTPC4_QM_GLBL_SECURE_PROPS_2 0xF08018 + +#define mmTPC4_QM_GLBL_SECURE_PROPS_3 0xF0801C + +#define mmTPC4_QM_GLBL_SECURE_PROPS_4 0xF08020 + +#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_0 0xF08024 + +#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_1 0xF08028 + +#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_2 0xF0802C + +#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_3 0xF08030 + +#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_4 0xF08034 + +#define mmTPC4_QM_GLBL_STS0 0xF08038 + +#define mmTPC4_QM_GLBL_STS1_0 0xF08040 + +#define mmTPC4_QM_GLBL_STS1_1 0xF08044 + +#define mmTPC4_QM_GLBL_STS1_2 0xF08048 + +#define mmTPC4_QM_GLBL_STS1_3 0xF0804C + +#define mmTPC4_QM_GLBL_STS1_4 0xF08050 + +#define mmTPC4_QM_GLBL_MSG_EN_0 0xF08054 + +#define mmTPC4_QM_GLBL_MSG_EN_1 0xF08058 + +#define mmTPC4_QM_GLBL_MSG_EN_2 0xF0805C + +#define mmTPC4_QM_GLBL_MSG_EN_3 0xF08060 + +#define mmTPC4_QM_GLBL_MSG_EN_4 0xF08068 + +#define mmTPC4_QM_PQ_BASE_LO_0 0xF08070 + +#define mmTPC4_QM_PQ_BASE_LO_1 0xF08074 + +#define mmTPC4_QM_PQ_BASE_LO_2 0xF08078 + +#define mmTPC4_QM_PQ_BASE_LO_3 0xF0807C + +#define mmTPC4_QM_PQ_BASE_HI_0 0xF08080 + +#define mmTPC4_QM_PQ_BASE_HI_1 0xF08084 + +#define mmTPC4_QM_PQ_BASE_HI_2 0xF08088 + +#define mmTPC4_QM_PQ_BASE_HI_3 0xF0808C + +#define mmTPC4_QM_PQ_SIZE_0 0xF08090 + +#define mmTPC4_QM_PQ_SIZE_1 0xF08094 + +#define mmTPC4_QM_PQ_SIZE_2 0xF08098 + +#define mmTPC4_QM_PQ_SIZE_3 0xF0809C + +#define mmTPC4_QM_PQ_PI_0 0xF080A0 + +#define mmTPC4_QM_PQ_PI_1 0xF080A4 + +#define mmTPC4_QM_PQ_PI_2 0xF080A8 + +#define mmTPC4_QM_PQ_PI_3 0xF080AC + +#define mmTPC4_QM_PQ_CI_0 0xF080B0 + +#define mmTPC4_QM_PQ_CI_1 0xF080B4 + +#define mmTPC4_QM_PQ_CI_2 0xF080B8 + +#define mmTPC4_QM_PQ_CI_3 0xF080BC + +#define mmTPC4_QM_PQ_CFG0_0 0xF080C0 + +#define mmTPC4_QM_PQ_CFG0_1 0xF080C4 + +#define mmTPC4_QM_PQ_CFG0_2 0xF080C8 + +#define mmTPC4_QM_PQ_CFG0_3 0xF080CC + +#define mmTPC4_QM_PQ_CFG1_0 0xF080D0 + +#define mmTPC4_QM_PQ_CFG1_1 0xF080D4 + +#define mmTPC4_QM_PQ_CFG1_2 0xF080D8 + +#define mmTPC4_QM_PQ_CFG1_3 0xF080DC + +#define mmTPC4_QM_PQ_ARUSER_31_11_0 0xF080E0 + +#define mmTPC4_QM_PQ_ARUSER_31_11_1 0xF080E4 + +#define mmTPC4_QM_PQ_ARUSER_31_11_2 0xF080E8 + +#define mmTPC4_QM_PQ_ARUSER_31_11_3 0xF080EC + +#define mmTPC4_QM_PQ_STS0_0 0xF080F0 + +#define mmTPC4_QM_PQ_STS0_1 0xF080F4 + +#define mmTPC4_QM_PQ_STS0_2 0xF080F8 + +#define mmTPC4_QM_PQ_STS0_3 0xF080FC + +#define mmTPC4_QM_PQ_STS1_0 0xF08100 + +#define mmTPC4_QM_PQ_STS1_1 0xF08104 + +#define mmTPC4_QM_PQ_STS1_2 0xF08108 + +#define mmTPC4_QM_PQ_STS1_3 0xF0810C + +#define mmTPC4_QM_CQ_CFG0_0 0xF08110 + +#define mmTPC4_QM_CQ_CFG0_1 0xF08114 + +#define mmTPC4_QM_CQ_CFG0_2 0xF08118 + +#define mmTPC4_QM_CQ_CFG0_3 0xF0811C + +#define mmTPC4_QM_CQ_CFG0_4 0xF08120 + +#define mmTPC4_QM_CQ_CFG1_0 0xF08124 + +#define mmTPC4_QM_CQ_CFG1_1 0xF08128 + +#define mmTPC4_QM_CQ_CFG1_2 0xF0812C + +#define mmTPC4_QM_CQ_CFG1_3 0xF08130 + +#define mmTPC4_QM_CQ_CFG1_4 0xF08134 + +#define mmTPC4_QM_CQ_ARUSER_31_11_0 0xF08138 + +#define mmTPC4_QM_CQ_ARUSER_31_11_1 0xF0813C + +#define mmTPC4_QM_CQ_ARUSER_31_11_2 0xF08140 + +#define mmTPC4_QM_CQ_ARUSER_31_11_3 0xF08144 + +#define mmTPC4_QM_CQ_ARUSER_31_11_4 0xF08148 + +#define mmTPC4_QM_CQ_STS0_0 0xF0814C + +#define mmTPC4_QM_CQ_STS0_1 0xF08150 + +#define mmTPC4_QM_CQ_STS0_2 0xF08154 + +#define mmTPC4_QM_CQ_STS0_3 0xF08158 + +#define mmTPC4_QM_CQ_STS0_4 0xF0815C + +#define mmTPC4_QM_CQ_STS1_0 0xF08160 + +#define mmTPC4_QM_CQ_STS1_1 0xF08164 + +#define mmTPC4_QM_CQ_STS1_2 0xF08168 + +#define mmTPC4_QM_CQ_STS1_3 0xF0816C + +#define mmTPC4_QM_CQ_STS1_4 0xF08170 + +#define mmTPC4_QM_CQ_PTR_LO_0 0xF08174 + +#define mmTPC4_QM_CQ_PTR_HI_0 0xF08178 + +#define mmTPC4_QM_CQ_TSIZE_0 0xF0817C + +#define mmTPC4_QM_CQ_CTL_0 0xF08180 + +#define mmTPC4_QM_CQ_PTR_LO_1 0xF08184 + +#define mmTPC4_QM_CQ_PTR_HI_1 0xF08188 + +#define mmTPC4_QM_CQ_TSIZE_1 0xF0818C + +#define mmTPC4_QM_CQ_CTL_1 0xF08190 + +#define mmTPC4_QM_CQ_PTR_LO_2 0xF08194 + +#define mmTPC4_QM_CQ_PTR_HI_2 0xF08198 + +#define mmTPC4_QM_CQ_TSIZE_2 0xF0819C + +#define mmTPC4_QM_CQ_CTL_2 0xF081A0 + +#define mmTPC4_QM_CQ_PTR_LO_3 0xF081A4 + +#define mmTPC4_QM_CQ_PTR_HI_3 0xF081A8 + +#define mmTPC4_QM_CQ_TSIZE_3 0xF081AC + +#define mmTPC4_QM_CQ_CTL_3 0xF081B0 + +#define mmTPC4_QM_CQ_PTR_LO_4 0xF081B4 + +#define mmTPC4_QM_CQ_PTR_HI_4 0xF081B8 + +#define mmTPC4_QM_CQ_TSIZE_4 0xF081BC + +#define mmTPC4_QM_CQ_CTL_4 0xF081C0 + +#define mmTPC4_QM_CQ_PTR_LO_STS_0 0xF081C4 + +#define mmTPC4_QM_CQ_PTR_LO_STS_1 0xF081C8 + +#define mmTPC4_QM_CQ_PTR_LO_STS_2 0xF081CC + +#define mmTPC4_QM_CQ_PTR_LO_STS_3 0xF081D0 + +#define mmTPC4_QM_CQ_PTR_LO_STS_4 0xF081D4 + +#define mmTPC4_QM_CQ_PTR_HI_STS_0 0xF081D8 + +#define mmTPC4_QM_CQ_PTR_HI_STS_1 0xF081DC + +#define mmTPC4_QM_CQ_PTR_HI_STS_2 0xF081E0 + +#define mmTPC4_QM_CQ_PTR_HI_STS_3 0xF081E4 + +#define mmTPC4_QM_CQ_PTR_HI_STS_4 0xF081E8 + +#define mmTPC4_QM_CQ_TSIZE_STS_0 0xF081EC + +#define mmTPC4_QM_CQ_TSIZE_STS_1 0xF081F0 + +#define mmTPC4_QM_CQ_TSIZE_STS_2 0xF081F4 + +#define mmTPC4_QM_CQ_TSIZE_STS_3 0xF081F8 + +#define mmTPC4_QM_CQ_TSIZE_STS_4 0xF081FC + +#define mmTPC4_QM_CQ_CTL_STS_0 0xF08200 + +#define mmTPC4_QM_CQ_CTL_STS_1 0xF08204 + +#define mmTPC4_QM_CQ_CTL_STS_2 0xF08208 + +#define mmTPC4_QM_CQ_CTL_STS_3 0xF0820C + +#define mmTPC4_QM_CQ_CTL_STS_4 0xF08210 + +#define mmTPC4_QM_CQ_IFIFO_CNT_0 0xF08214 + +#define mmTPC4_QM_CQ_IFIFO_CNT_1 0xF08218 + +#define mmTPC4_QM_CQ_IFIFO_CNT_2 0xF0821C + +#define mmTPC4_QM_CQ_IFIFO_CNT_3 0xF08220 + +#define mmTPC4_QM_CQ_IFIFO_CNT_4 0xF08224 + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_0 0xF08228 + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_1 0xF0822C + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_2 0xF08230 + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_3 0xF08234 + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_4 0xF08238 + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_0 0xF0823C + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_1 0xF08240 + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_2 0xF08244 + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_3 0xF08248 + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_4 0xF0824C + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_0 0xF08250 + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_1 0xF08254 + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_2 0xF08258 + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_3 0xF0825C + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_4 0xF08260 + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_0 0xF08264 + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_1 0xF08268 + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_2 0xF0826C + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_3 0xF08270 + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_4 0xF08274 + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_0 0xF08278 + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_1 0xF0827C + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_2 0xF08280 + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_3 0xF08284 + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_4 0xF08288 + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_0 0xF0828C + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_1 0xF08290 + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_2 0xF08294 + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_3 0xF08298 + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_4 0xF0829C + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_0 0xF082A0 + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_1 0xF082A4 + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_2 0xF082A8 + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_3 0xF082AC + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_4 0xF082B0 + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_0 0xF082B4 + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_1 0xF082B8 + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_2 0xF082BC + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_3 0xF082C0 + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_4 0xF082C4 + +#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_0 0xF082C8 + +#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_1 0xF082CC + +#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_2 0xF082D0 + +#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_3 0xF082D4 + +#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_4 0xF082D8 + +#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xF082E0 + +#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xF082E4 + +#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xF082E8 + +#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xF082EC + +#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xF082F0 + +#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xF082F4 + +#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xF082F8 + +#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xF082FC + +#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xF08300 + +#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xF08304 + +#define mmTPC4_QM_CP_FENCE0_RDATA_0 0xF08308 + +#define mmTPC4_QM_CP_FENCE0_RDATA_1 0xF0830C + +#define mmTPC4_QM_CP_FENCE0_RDATA_2 0xF08310 + +#define mmTPC4_QM_CP_FENCE0_RDATA_3 0xF08314 + +#define mmTPC4_QM_CP_FENCE0_RDATA_4 0xF08318 + +#define mmTPC4_QM_CP_FENCE1_RDATA_0 0xF0831C + +#define mmTPC4_QM_CP_FENCE1_RDATA_1 0xF08320 + +#define mmTPC4_QM_CP_FENCE1_RDATA_2 0xF08324 + +#define mmTPC4_QM_CP_FENCE1_RDATA_3 0xF08328 + +#define mmTPC4_QM_CP_FENCE1_RDATA_4 0xF0832C + +#define mmTPC4_QM_CP_FENCE2_RDATA_0 0xF08330 + +#define mmTPC4_QM_CP_FENCE2_RDATA_1 0xF08334 + +#define mmTPC4_QM_CP_FENCE2_RDATA_2 0xF08338 + +#define mmTPC4_QM_CP_FENCE2_RDATA_3 0xF0833C + +#define mmTPC4_QM_CP_FENCE2_RDATA_4 0xF08340 + +#define mmTPC4_QM_CP_FENCE3_RDATA_0 0xF08344 + +#define mmTPC4_QM_CP_FENCE3_RDATA_1 0xF08348 + +#define mmTPC4_QM_CP_FENCE3_RDATA_2 0xF0834C + +#define mmTPC4_QM_CP_FENCE3_RDATA_3 0xF08350 + +#define mmTPC4_QM_CP_FENCE3_RDATA_4 0xF08354 + +#define mmTPC4_QM_CP_FENCE0_CNT_0 0xF08358 + +#define mmTPC4_QM_CP_FENCE0_CNT_1 0xF0835C + +#define mmTPC4_QM_CP_FENCE0_CNT_2 0xF08360 + +#define mmTPC4_QM_CP_FENCE0_CNT_3 0xF08364 + +#define mmTPC4_QM_CP_FENCE0_CNT_4 0xF08368 + +#define mmTPC4_QM_CP_FENCE1_CNT_0 0xF0836C + +#define mmTPC4_QM_CP_FENCE1_CNT_1 0xF08370 + +#define mmTPC4_QM_CP_FENCE1_CNT_2 0xF08374 + +#define mmTPC4_QM_CP_FENCE1_CNT_3 0xF08378 + +#define mmTPC4_QM_CP_FENCE1_CNT_4 0xF0837C + +#define mmTPC4_QM_CP_FENCE2_CNT_0 0xF08380 + +#define mmTPC4_QM_CP_FENCE2_CNT_1 0xF08384 + +#define mmTPC4_QM_CP_FENCE2_CNT_2 0xF08388 + +#define mmTPC4_QM_CP_FENCE2_CNT_3 0xF0838C + +#define mmTPC4_QM_CP_FENCE2_CNT_4 0xF08390 + +#define mmTPC4_QM_CP_FENCE3_CNT_0 0xF08394 + +#define mmTPC4_QM_CP_FENCE3_CNT_1 0xF08398 + +#define mmTPC4_QM_CP_FENCE3_CNT_2 0xF0839C + +#define mmTPC4_QM_CP_FENCE3_CNT_3 0xF083A0 + +#define mmTPC4_QM_CP_FENCE3_CNT_4 0xF083A4 + +#define mmTPC4_QM_CP_STS_0 0xF083A8 + +#define mmTPC4_QM_CP_STS_1 0xF083AC + +#define mmTPC4_QM_CP_STS_2 0xF083B0 + +#define mmTPC4_QM_CP_STS_3 0xF083B4 + +#define mmTPC4_QM_CP_STS_4 0xF083B8 + +#define mmTPC4_QM_CP_CURRENT_INST_LO_0 0xF083BC + +#define mmTPC4_QM_CP_CURRENT_INST_LO_1 0xF083C0 + +#define mmTPC4_QM_CP_CURRENT_INST_LO_2 0xF083C4 + +#define mmTPC4_QM_CP_CURRENT_INST_LO_3 0xF083C8 + +#define mmTPC4_QM_CP_CURRENT_INST_LO_4 0xF083CC + +#define mmTPC4_QM_CP_CURRENT_INST_HI_0 0xF083D0 + +#define mmTPC4_QM_CP_CURRENT_INST_HI_1 0xF083D4 + +#define mmTPC4_QM_CP_CURRENT_INST_HI_2 0xF083D8 + +#define mmTPC4_QM_CP_CURRENT_INST_HI_3 0xF083DC + +#define mmTPC4_QM_CP_CURRENT_INST_HI_4 0xF083E0 + +#define mmTPC4_QM_CP_BARRIER_CFG_0 0xF083F4 + +#define mmTPC4_QM_CP_BARRIER_CFG_1 0xF083F8 + +#define mmTPC4_QM_CP_BARRIER_CFG_2 0xF083FC + +#define mmTPC4_QM_CP_BARRIER_CFG_3 0xF08400 + +#define mmTPC4_QM_CP_BARRIER_CFG_4 0xF08404 + +#define mmTPC4_QM_CP_DBG_0_0 0xF08408 + +#define mmTPC4_QM_CP_DBG_0_1 0xF0840C + +#define mmTPC4_QM_CP_DBG_0_2 0xF08410 + +#define mmTPC4_QM_CP_DBG_0_3 0xF08414 + +#define mmTPC4_QM_CP_DBG_0_4 0xF08418 + +#define mmTPC4_QM_CP_ARUSER_31_11_0 0xF0841C + +#define mmTPC4_QM_CP_ARUSER_31_11_1 0xF08420 + +#define mmTPC4_QM_CP_ARUSER_31_11_2 0xF08424 + +#define mmTPC4_QM_CP_ARUSER_31_11_3 0xF08428 + +#define mmTPC4_QM_CP_ARUSER_31_11_4 0xF0842C + +#define mmTPC4_QM_CP_AWUSER_31_11_0 0xF08430 + +#define mmTPC4_QM_CP_AWUSER_31_11_1 0xF08434 + +#define mmTPC4_QM_CP_AWUSER_31_11_2 0xF08438 + +#define mmTPC4_QM_CP_AWUSER_31_11_3 0xF0843C + +#define mmTPC4_QM_CP_AWUSER_31_11_4 0xF08440 + +#define mmTPC4_QM_ARB_CFG_0 0xF08A00 + +#define mmTPC4_QM_ARB_CHOISE_Q_PUSH 0xF08A04 + +#define mmTPC4_QM_ARB_WRR_WEIGHT_0 0xF08A08 + +#define mmTPC4_QM_ARB_WRR_WEIGHT_1 0xF08A0C + +#define mmTPC4_QM_ARB_WRR_WEIGHT_2 0xF08A10 + +#define mmTPC4_QM_ARB_WRR_WEIGHT_3 0xF08A14 + +#define mmTPC4_QM_ARB_CFG_1 0xF08A18 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_0 0xF08A20 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_1 0xF08A24 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_2 0xF08A28 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_3 0xF08A2C + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_4 0xF08A30 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_5 0xF08A34 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_6 0xF08A38 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_7 0xF08A3C + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_8 0xF08A40 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_9 0xF08A44 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_10 0xF08A48 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_11 0xF08A4C + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_12 0xF08A50 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_13 0xF08A54 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_14 0xF08A58 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_15 0xF08A5C + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_16 0xF08A60 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_17 0xF08A64 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_18 0xF08A68 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_19 0xF08A6C + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_20 0xF08A70 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_21 0xF08A74 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_22 0xF08A78 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_23 0xF08A7C + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_24 0xF08A80 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_25 0xF08A84 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_26 0xF08A88 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_27 0xF08A8C + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_28 0xF08A90 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_29 0xF08A94 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_30 0xF08A98 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_31 0xF08A9C + +#define mmTPC4_QM_ARB_MST_CRED_INC 0xF08AA0 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xF08AA4 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xF08AA8 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xF08AAC + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xF08AB0 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xF08AB4 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xF08AB8 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xF08ABC + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xF08AC0 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xF08AC4 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xF08AC8 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xF08ACC + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xF08AD0 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xF08AD4 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xF08AD8 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xF08ADC + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xF08AE0 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xF08AE4 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xF08AE8 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xF08AEC + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xF08AF0 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xF08AF4 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xF08AF8 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xF08AFC + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xF08B00 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xF08B04 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xF08B08 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xF08B0C + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xF08B10 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xF08B14 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xF08B18 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xF08B1C + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xF08B20 + +#define mmTPC4_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xF08B28 + +#define mmTPC4_QM_ARB_MST_SLAVE_EN 0xF08B2C + +#define mmTPC4_QM_ARB_MST_QUIET_PER 0xF08B34 + +#define mmTPC4_QM_ARB_SLV_CHOISE_WDT 0xF08B38 + +#define mmTPC4_QM_ARB_SLV_ID 0xF08B3C + +#define mmTPC4_QM_ARB_MSG_MAX_INFLIGHT 0xF08B44 + +#define mmTPC4_QM_ARB_MSG_AWUSER_31_11 0xF08B48 + +#define mmTPC4_QM_ARB_MSG_AWUSER_SEC_PROP 0xF08B4C + +#define mmTPC4_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xF08B50 + +#define mmTPC4_QM_ARB_BASE_LO 0xF08B54 + +#define mmTPC4_QM_ARB_BASE_HI 0xF08B58 + +#define mmTPC4_QM_ARB_STATE_STS 0xF08B80 + +#define mmTPC4_QM_ARB_CHOISE_FULLNESS_STS 0xF08B84 + +#define mmTPC4_QM_ARB_MSG_STS 0xF08B88 + +#define mmTPC4_QM_ARB_SLV_CHOISE_Q_HEAD 0xF08B8C + +#define mmTPC4_QM_ARB_ERR_CAUSE 0xF08B9C + +#define mmTPC4_QM_ARB_ERR_MSG_EN 0xF08BA0 + +#define mmTPC4_QM_ARB_ERR_STS_DRP 0xF08BA8 + +#define mmTPC4_QM_ARB_MST_CRED_STS_0 0xF08BB0 + +#define mmTPC4_QM_ARB_MST_CRED_STS_1 0xF08BB4 + +#define mmTPC4_QM_ARB_MST_CRED_STS_2 0xF08BB8 + +#define mmTPC4_QM_ARB_MST_CRED_STS_3 0xF08BBC + +#define mmTPC4_QM_ARB_MST_CRED_STS_4 0xF08BC0 + +#define mmTPC4_QM_ARB_MST_CRED_STS_5 0xF08BC4 + +#define mmTPC4_QM_ARB_MST_CRED_STS_6 0xF08BC8 + +#define mmTPC4_QM_ARB_MST_CRED_STS_7 0xF08BCC + +#define mmTPC4_QM_ARB_MST_CRED_STS_8 0xF08BD0 + +#define mmTPC4_QM_ARB_MST_CRED_STS_9 0xF08BD4 + +#define mmTPC4_QM_ARB_MST_CRED_STS_10 0xF08BD8 + +#define mmTPC4_QM_ARB_MST_CRED_STS_11 0xF08BDC + +#define mmTPC4_QM_ARB_MST_CRED_STS_12 0xF08BE0 + +#define mmTPC4_QM_ARB_MST_CRED_STS_13 0xF08BE4 + +#define mmTPC4_QM_ARB_MST_CRED_STS_14 0xF08BE8 + +#define mmTPC4_QM_ARB_MST_CRED_STS_15 0xF08BEC + +#define mmTPC4_QM_ARB_MST_CRED_STS_16 0xF08BF0 + +#define mmTPC4_QM_ARB_MST_CRED_STS_17 0xF08BF4 + +#define mmTPC4_QM_ARB_MST_CRED_STS_18 0xF08BF8 + +#define mmTPC4_QM_ARB_MST_CRED_STS_19 0xF08BFC + +#define mmTPC4_QM_ARB_MST_CRED_STS_20 0xF08C00 + +#define mmTPC4_QM_ARB_MST_CRED_STS_21 0xF08C04 + +#define mmTPC4_QM_ARB_MST_CRED_STS_22 0xF08C08 + +#define mmTPC4_QM_ARB_MST_CRED_STS_23 0xF08C0C + +#define mmTPC4_QM_ARB_MST_CRED_STS_24 0xF08C10 + +#define mmTPC4_QM_ARB_MST_CRED_STS_25 0xF08C14 + +#define mmTPC4_QM_ARB_MST_CRED_STS_26 0xF08C18 + +#define mmTPC4_QM_ARB_MST_CRED_STS_27 0xF08C1C + +#define mmTPC4_QM_ARB_MST_CRED_STS_28 0xF08C20 + +#define mmTPC4_QM_ARB_MST_CRED_STS_29 0xF08C24 + +#define mmTPC4_QM_ARB_MST_CRED_STS_30 0xF08C28 + +#define mmTPC4_QM_ARB_MST_CRED_STS_31 0xF08C2C + +#define mmTPC4_QM_CGM_CFG 0xF08C70 + +#define mmTPC4_QM_CGM_STS 0xF08C74 + +#define mmTPC4_QM_CGM_CFG1 0xF08C78 + +#define mmTPC4_QM_LOCAL_RANGE_BASE 0xF08C80 + +#define mmTPC4_QM_LOCAL_RANGE_SIZE 0xF08C84 + +#define mmTPC4_QM_CSMR_STRICT_PRIO_CFG 0xF08C90 + +#define mmTPC4_QM_HBW_RD_RATE_LIM_CFG_1 0xF08C94 + +#define mmTPC4_QM_LBW_WR_RATE_LIM_CFG_0 0xF08C98 + +#define mmTPC4_QM_LBW_WR_RATE_LIM_CFG_1 0xF08C9C + +#define mmTPC4_QM_HBW_RD_RATE_LIM_CFG_0 0xF08CA0 + +#define mmTPC4_QM_GLBL_AXCACHE 0xF08CA4 + +#define mmTPC4_QM_IND_GW_APB_CFG 0xF08CB0 + +#define mmTPC4_QM_IND_GW_APB_WDATA 0xF08CB4 + +#define mmTPC4_QM_IND_GW_APB_RDATA 0xF08CB8 + +#define mmTPC4_QM_IND_GW_APB_STATUS 0xF08CBC + +#define mmTPC4_QM_GLBL_ERR_ADDR_LO 0xF08CD0 + +#define mmTPC4_QM_GLBL_ERR_ADDR_HI 0xF08CD4 + +#define mmTPC4_QM_GLBL_ERR_WDATA 0xF08CD8 + +#define mmTPC4_QM_GLBL_MEM_INIT_BUSY 0xF08D00 + +#endif /* ASIC_REG_TPC4_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc5_cfg_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc5_cfg_regs.h new file mode 100644 index 000000000000..f428f891935a --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc5_cfg_regs.h @@ -0,0 +1,1226 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC5_CFG_REGS_H_ +#define ASIC_REG_TPC5_CFG_REGS_H_ + +/* + ***************************************** + * TPC5_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC5_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF46400 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF46404 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF46408 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF4640C + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF46410 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF46414 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF46418 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF4641C + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF46420 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF46424 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF46428 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF4642C + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF46430 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF46434 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF46438 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF4643C + +#define mmTPC5_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF46440 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF46444 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF46448 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF4644C + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF46450 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF46454 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF46458 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF4645C + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF46460 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF46464 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF46468 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF4646C + +#define mmTPC5_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF46470 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF46474 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF46478 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF4647C + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF46480 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF46484 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF46488 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF4648C + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF46490 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF46494 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF46498 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF4649C + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF464A0 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF464A4 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF464A8 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF464AC + +#define mmTPC5_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF464B0 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF464B4 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF464B8 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF464BC + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF464C0 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF464C4 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF464C8 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF464CC + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF464D0 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF464D4 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF464D8 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF464DC + +#define mmTPC5_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF464E0 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF464E4 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF464E8 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF464EC + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF464F0 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF464F4 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF464F8 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF464FC + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF46500 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF46504 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF46508 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF4650C + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF46510 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF46514 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF46518 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF4651C + +#define mmTPC5_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF46520 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF46524 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF46528 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF4652C + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF46530 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF46534 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF46538 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF4653C + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF46540 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF46544 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF46548 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF4654C + +#define mmTPC5_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF46550 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF46554 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF46558 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF4655C + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF46560 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF46564 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF46568 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF4656C + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF46570 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF46574 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF46578 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF4657C + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF46580 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF46584 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF46588 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF4658C + +#define mmTPC5_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF46590 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF46594 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF46598 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF4659C + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF465A0 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF465A4 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF465A8 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF465AC + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF465B0 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF465B4 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF465B8 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF465BC + +#define mmTPC5_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xF465C0 + +#define mmTPC5_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xF465C4 + +#define mmTPC5_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xF465C8 + +#define mmTPC5_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xF465CC + +#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xF465D0 + +#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xF465D4 + +#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xF465D8 + +#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xF465DC + +#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xF465E0 + +#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xF465E4 + +#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xF465E8 + +#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xF465EC + +#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xF465F0 + +#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xF465F4 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xF465F8 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xF465FC + +#define mmTPC5_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xF46600 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xF46604 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xF46608 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xF4660C + +#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xF46610 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xF46614 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xF46618 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xF4661C + +#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xF46620 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xF46624 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xF46628 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xF4662C + +#define mmTPC5_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xF46630 + +#define mmTPC5_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xF46634 + +#define mmTPC5_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xF46638 + +#define mmTPC5_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xF4663C + +#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xF46640 + +#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xF46644 + +#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xF46648 + +#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xF4664C + +#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xF46650 + +#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xF46654 + +#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xF46658 + +#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xF4665C + +#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xF46660 + +#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xF46664 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xF46668 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xF4666C + +#define mmTPC5_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xF46670 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xF46674 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xF46678 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xF4667C + +#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xF46680 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xF46684 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xF46688 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xF4668C + +#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xF46690 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xF46694 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xF46698 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xF4669C + +#define mmTPC5_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xF466A0 + +#define mmTPC5_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xF466A4 + +#define mmTPC5_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xF466A8 + +#define mmTPC5_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xF466AC + +#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xF466B0 + +#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xF466B4 + +#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xF466B8 + +#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xF466BC + +#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xF466C0 + +#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xF466C4 + +#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xF466C8 + +#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xF466CC + +#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xF466D0 + +#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xF466D4 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xF466D8 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xF466DC + +#define mmTPC5_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xF466E0 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xF466E4 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xF466E8 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xF466EC + +#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xF466F0 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xF466F4 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xF466F8 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xF466FC + +#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xF46700 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xF46704 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xF46708 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xF4670C + +#define mmTPC5_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xF46710 + +#define mmTPC5_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xF46714 + +#define mmTPC5_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xF46718 + +#define mmTPC5_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xF4671C + +#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xF46720 + +#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xF46724 + +#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xF46728 + +#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xF4672C + +#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xF46730 + +#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xF46734 + +#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xF46738 + +#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xF4673C + +#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xF46740 + +#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xF46744 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xF46748 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xF4674C + +#define mmTPC5_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xF46750 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xF46754 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xF46758 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xF4675C + +#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xF46760 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xF46764 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xF46768 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xF4676C + +#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xF46770 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xF46774 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xF46778 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xF4677C + +#define mmTPC5_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF46780 + +#define mmTPC5_CFG_KERNEL_SYNC_OBJECT_ADDR 0xF46784 + +#define mmTPC5_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF46788 + +#define mmTPC5_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF4678C + +#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_0 0xF46790 + +#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_0 0xF46794 + +#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_1 0xF46798 + +#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_1 0xF4679C + +#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_2 0xF467A0 + +#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_2 0xF467A4 + +#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_3 0xF467A8 + +#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_3 0xF467AC + +#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_4 0xF467B0 + +#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_4 0xF467B4 + +#define mmTPC5_CFG_KERNEL_KERNEL_CONFIG 0xF467B8 + +#define mmTPC5_CFG_KERNEL_KERNEL_ID 0xF467BC + +#define mmTPC5_CFG_KERNEL_SRF_0 0xF467C0 + +#define mmTPC5_CFG_KERNEL_SRF_1 0xF467C4 + +#define mmTPC5_CFG_KERNEL_SRF_2 0xF467C8 + +#define mmTPC5_CFG_KERNEL_SRF_3 0xF467CC + +#define mmTPC5_CFG_KERNEL_SRF_4 0xF467D0 + +#define mmTPC5_CFG_KERNEL_SRF_5 0xF467D4 + +#define mmTPC5_CFG_KERNEL_SRF_6 0xF467D8 + +#define mmTPC5_CFG_KERNEL_SRF_7 0xF467DC + +#define mmTPC5_CFG_KERNEL_SRF_8 0xF467E0 + +#define mmTPC5_CFG_KERNEL_SRF_9 0xF467E4 + +#define mmTPC5_CFG_KERNEL_SRF_10 0xF467E8 + +#define mmTPC5_CFG_KERNEL_SRF_11 0xF467EC + +#define mmTPC5_CFG_KERNEL_SRF_12 0xF467F0 + +#define mmTPC5_CFG_KERNEL_SRF_13 0xF467F4 + +#define mmTPC5_CFG_KERNEL_SRF_14 0xF467F8 + +#define mmTPC5_CFG_KERNEL_SRF_15 0xF467FC + +#define mmTPC5_CFG_KERNEL_SRF_16 0xF46800 + +#define mmTPC5_CFG_KERNEL_SRF_17 0xF46804 + +#define mmTPC5_CFG_KERNEL_SRF_18 0xF46808 + +#define mmTPC5_CFG_KERNEL_SRF_19 0xF4680C + +#define mmTPC5_CFG_KERNEL_SRF_20 0xF46810 + +#define mmTPC5_CFG_KERNEL_SRF_21 0xF46814 + +#define mmTPC5_CFG_KERNEL_SRF_22 0xF46818 + +#define mmTPC5_CFG_KERNEL_SRF_23 0xF4681C + +#define mmTPC5_CFG_KERNEL_SRF_24 0xF46820 + +#define mmTPC5_CFG_KERNEL_SRF_25 0xF46824 + +#define mmTPC5_CFG_KERNEL_SRF_26 0xF46828 + +#define mmTPC5_CFG_KERNEL_SRF_27 0xF4682C + +#define mmTPC5_CFG_KERNEL_SRF_28 0xF46830 + +#define mmTPC5_CFG_KERNEL_SRF_29 0xF46834 + +#define mmTPC5_CFG_KERNEL_SRF_30 0xF46838 + +#define mmTPC5_CFG_KERNEL_SRF_31 0xF4683C + +#define mmTPC5_CFG_ROUND_CSR 0xF468FC + +#define mmTPC5_CFG_PROT 0xF46900 + +#define mmTPC5_CFG_SEMAPHORE 0xF46908 + +#define mmTPC5_CFG_VFLAGS 0xF4690C + +#define mmTPC5_CFG_SFLAGS 0xF46910 + +#define mmTPC5_CFG_LFSR_POLYNOM 0xF46918 + +#define mmTPC5_CFG_STATUS 0xF4691C + +#define mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH 0xF46920 + +#define mmTPC5_CFG_CFG_SUBTRACT_VALUE 0xF46924 + +#define mmTPC5_CFG_SM_BASE_ADDRESS_HIGH 0xF4692C + +#define mmTPC5_CFG_TPC_CMD 0xF46930 + +#define mmTPC5_CFG_TPC_EXECUTE 0xF46938 + +#define mmTPC5_CFG_TPC_STALL 0xF4693C + +#define mmTPC5_CFG_ICACHE_BASE_ADDERESS_LOW 0xF46940 + +#define mmTPC5_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF46944 + +#define mmTPC5_CFG_RD_RATE_LIMIT 0xF46948 + +#define mmTPC5_CFG_WR_RATE_LIMIT 0xF46950 + +#define mmTPC5_CFG_MSS_CONFIG 0xF46954 + +#define mmTPC5_CFG_TPC_INTR_CAUSE 0xF46958 + +#define mmTPC5_CFG_TPC_INTR_MASK 0xF4695C + +#define mmTPC5_CFG_WQ_CREDITS 0xF46960 + +#define mmTPC5_CFG_ARUSER_LO 0xF46964 + +#define mmTPC5_CFG_ARUSER_HI 0xF46968 + +#define mmTPC5_CFG_AWUSER_LO 0xF4696C + +#define mmTPC5_CFG_AWUSER_HI 0xF46970 + +#define mmTPC5_CFG_OPCODE_EXEC 0xF46974 + +#define mmTPC5_CFG_LUT_FUNC32_BASE_ADDR_LO 0xF46978 + +#define mmTPC5_CFG_LUT_FUNC32_BASE_ADDR_HI 0xF4697C + +#define mmTPC5_CFG_LUT_FUNC64_BASE_ADDR_LO 0xF46980 + +#define mmTPC5_CFG_LUT_FUNC64_BASE_ADDR_HI 0xF46984 + +#define mmTPC5_CFG_LUT_FUNC128_BASE_ADDR_LO 0xF46988 + +#define mmTPC5_CFG_LUT_FUNC128_BASE_ADDR_HI 0xF4698C + +#define mmTPC5_CFG_LUT_FUNC256_BASE_ADDR_LO 0xF46990 + +#define mmTPC5_CFG_LUT_FUNC256_BASE_ADDR_HI 0xF46994 + +#define mmTPC5_CFG_TSB_CFG_MAX_SIZE 0xF46998 + +#define mmTPC5_CFG_TSB_CFG 0xF4699C + +#define mmTPC5_CFG_DBGMEM_ADD 0xF469A0 + +#define mmTPC5_CFG_DBGMEM_DATA_WR 0xF469A4 + +#define mmTPC5_CFG_DBGMEM_DATA_RD 0xF469A8 + +#define mmTPC5_CFG_DBGMEM_CTRL 0xF469AC + +#define mmTPC5_CFG_DBGMEM_RC 0xF469B0 + +#define mmTPC5_CFG_TSB_INFLIGHT_CNTR 0xF469B4 + +#define mmTPC5_CFG_WQ_INFLIGHT_CNTR 0xF469B8 + +#define mmTPC5_CFG_WQ_LBW_TOTAL_CNTR 0xF469BC + +#define mmTPC5_CFG_WQ_HBW_TOTAL_CNTR 0xF469C0 + +#define mmTPC5_CFG_IRQ_OCCOUPY_CNTR 0xF469C4 + +#define mmTPC5_CFG_FUNC_MBIST_CNTRL 0xF469D0 + +#define mmTPC5_CFG_FUNC_MBIST_PAT 0xF469D4 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_0 0xF469D8 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_1 0xF469DC + +#define mmTPC5_CFG_FUNC_MBIST_MEM_2 0xF469E0 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_3 0xF469E4 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_4 0xF469E8 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_5 0xF469EC + +#define mmTPC5_CFG_FUNC_MBIST_MEM_6 0xF469F0 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_7 0xF469F4 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_8 0xF469F8 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_9 0xF469FC + +#define mmTPC5_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF46A00 + +#define mmTPC5_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF46A04 + +#define mmTPC5_CFG_QM_TENSOR_0_PADDING_VALUE 0xF46A08 + +#define mmTPC5_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF46A0C + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF46A10 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF46A14 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF46A18 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF46A1C + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF46A20 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF46A24 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF46A28 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF46A2C + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF46A30 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF46A34 + +#define mmTPC5_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF46A38 + +#define mmTPC5_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF46A3C + +#define mmTPC5_CFG_QM_TENSOR_1_PADDING_VALUE 0xF46A40 + +#define mmTPC5_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF46A44 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF46A48 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF46A4C + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF46A50 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF46A54 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF46A58 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF46A5C + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF46A60 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF46A64 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF46A68 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF46A6C + +#define mmTPC5_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF46A70 + +#define mmTPC5_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF46A74 + +#define mmTPC5_CFG_QM_TENSOR_2_PADDING_VALUE 0xF46A78 + +#define mmTPC5_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF46A7C + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF46A80 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF46A84 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF46A88 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF46A8C + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF46A90 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF46A94 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF46A98 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF46A9C + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF46AA0 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF46AA4 + +#define mmTPC5_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF46AA8 + +#define mmTPC5_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF46AAC + +#define mmTPC5_CFG_QM_TENSOR_3_PADDING_VALUE 0xF46AB0 + +#define mmTPC5_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF46AB4 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF46AB8 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF46ABC + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF46AC0 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF46AC4 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF46AC8 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF46ACC + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF46AD0 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF46AD4 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF46AD8 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF46ADC + +#define mmTPC5_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF46AE0 + +#define mmTPC5_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF46AE4 + +#define mmTPC5_CFG_QM_TENSOR_4_PADDING_VALUE 0xF46AE8 + +#define mmTPC5_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF46AEC + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF46AF0 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF46AF4 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF46AF8 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF46AFC + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF46B00 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF46B04 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF46B08 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF46B0C + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF46B10 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF46B14 + +#define mmTPC5_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF46B18 + +#define mmTPC5_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF46B1C + +#define mmTPC5_CFG_QM_TENSOR_5_PADDING_VALUE 0xF46B20 + +#define mmTPC5_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF46B24 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF46B28 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF46B2C + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF46B30 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF46B34 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF46B38 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF46B3C + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF46B40 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF46B44 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF46B48 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF46B4C + +#define mmTPC5_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF46B50 + +#define mmTPC5_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF46B54 + +#define mmTPC5_CFG_QM_TENSOR_6_PADDING_VALUE 0xF46B58 + +#define mmTPC5_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF46B5C + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF46B60 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF46B64 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF46B68 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF46B6C + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF46B70 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF46B74 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF46B78 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF46B7C + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF46B80 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF46B84 + +#define mmTPC5_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF46B88 + +#define mmTPC5_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF46B8C + +#define mmTPC5_CFG_QM_TENSOR_7_PADDING_VALUE 0xF46B90 + +#define mmTPC5_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF46B94 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF46B98 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF46B9C + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF46BA0 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF46BA4 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF46BA8 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF46BAC + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF46BB0 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF46BB4 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF46BB8 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF46BBC + +#define mmTPC5_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xF46BC0 + +#define mmTPC5_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xF46BC4 + +#define mmTPC5_CFG_QM_TENSOR_8_PADDING_VALUE 0xF46BC8 + +#define mmTPC5_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xF46BCC + +#define mmTPC5_CFG_QM_TENSOR_8_DIM_0_SIZE 0xF46BD0 + +#define mmTPC5_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xF46BD4 + +#define mmTPC5_CFG_QM_TENSOR_8_DIM_1_SIZE 0xF46BD8 + +#define mmTPC5_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xF46BDC + +#define mmTPC5_CFG_QM_TENSOR_8_DIM_2_SIZE 0xF46BE0 + +#define mmTPC5_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xF46BE4 + +#define mmTPC5_CFG_QM_TENSOR_8_DIM_3_SIZE 0xF46BE8 + +#define mmTPC5_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xF46BEC + +#define mmTPC5_CFG_QM_TENSOR_8_DIM_4_SIZE 0xF46BF0 + +#define mmTPC5_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xF46BF4 + +#define mmTPC5_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xF46BF8 + +#define mmTPC5_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xF46BFC + +#define mmTPC5_CFG_QM_TENSOR_9_PADDING_VALUE 0xF46C00 + +#define mmTPC5_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xF46C04 + +#define mmTPC5_CFG_QM_TENSOR_9_DIM_0_SIZE 0xF46C08 + +#define mmTPC5_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xF46C0C + +#define mmTPC5_CFG_QM_TENSOR_9_DIM_1_SIZE 0xF46C10 + +#define mmTPC5_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xF46C14 + +#define mmTPC5_CFG_QM_TENSOR_9_DIM_2_SIZE 0xF46C18 + +#define mmTPC5_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xF46C1C + +#define mmTPC5_CFG_QM_TENSOR_9_DIM_3_SIZE 0xF46C20 + +#define mmTPC5_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xF46C24 + +#define mmTPC5_CFG_QM_TENSOR_9_DIM_4_SIZE 0xF46C28 + +#define mmTPC5_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xF46C2C + +#define mmTPC5_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xF46C30 + +#define mmTPC5_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xF46C34 + +#define mmTPC5_CFG_QM_TENSOR_10_PADDING_VALUE 0xF46C38 + +#define mmTPC5_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xF46C3C + +#define mmTPC5_CFG_QM_TENSOR_10_DIM_0_SIZE 0xF46C40 + +#define mmTPC5_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xF46C44 + +#define mmTPC5_CFG_QM_TENSOR_10_DIM_1_SIZE 0xF46C48 + +#define mmTPC5_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xF46C4C + +#define mmTPC5_CFG_QM_TENSOR_10_DIM_2_SIZE 0xF46C50 + +#define mmTPC5_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xF46C54 + +#define mmTPC5_CFG_QM_TENSOR_10_DIM_3_SIZE 0xF46C58 + +#define mmTPC5_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xF46C5C + +#define mmTPC5_CFG_QM_TENSOR_10_DIM_4_SIZE 0xF46C60 + +#define mmTPC5_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xF46C64 + +#define mmTPC5_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xF46C68 + +#define mmTPC5_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xF46C6C + +#define mmTPC5_CFG_QM_TENSOR_11_PADDING_VALUE 0xF46C70 + +#define mmTPC5_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xF46C74 + +#define mmTPC5_CFG_QM_TENSOR_11_DIM_0_SIZE 0xF46C78 + +#define mmTPC5_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xF46C7C + +#define mmTPC5_CFG_QM_TENSOR_11_DIM_1_SIZE 0xF46C80 + +#define mmTPC5_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xF46C84 + +#define mmTPC5_CFG_QM_TENSOR_11_DIM_2_SIZE 0xF46C88 + +#define mmTPC5_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xF46C8C + +#define mmTPC5_CFG_QM_TENSOR_11_DIM_3_SIZE 0xF46C90 + +#define mmTPC5_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xF46C94 + +#define mmTPC5_CFG_QM_TENSOR_11_DIM_4_SIZE 0xF46C98 + +#define mmTPC5_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xF46C9C + +#define mmTPC5_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xF46CA0 + +#define mmTPC5_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xF46CA4 + +#define mmTPC5_CFG_QM_TENSOR_12_PADDING_VALUE 0xF46CA8 + +#define mmTPC5_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xF46CAC + +#define mmTPC5_CFG_QM_TENSOR_12_DIM_0_SIZE 0xF46CB0 + +#define mmTPC5_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xF46CB4 + +#define mmTPC5_CFG_QM_TENSOR_12_DIM_1_SIZE 0xF46CB8 + +#define mmTPC5_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xF46CBC + +#define mmTPC5_CFG_QM_TENSOR_12_DIM_2_SIZE 0xF46CC0 + +#define mmTPC5_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xF46CC4 + +#define mmTPC5_CFG_QM_TENSOR_12_DIM_3_SIZE 0xF46CC8 + +#define mmTPC5_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xF46CCC + +#define mmTPC5_CFG_QM_TENSOR_12_DIM_4_SIZE 0xF46CD0 + +#define mmTPC5_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xF46CD4 + +#define mmTPC5_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xF46CD8 + +#define mmTPC5_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xF46CDC + +#define mmTPC5_CFG_QM_TENSOR_13_PADDING_VALUE 0xF46CE0 + +#define mmTPC5_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xF46CE4 + +#define mmTPC5_CFG_QM_TENSOR_13_DIM_0_SIZE 0xF46CE8 + +#define mmTPC5_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xF46CEC + +#define mmTPC5_CFG_QM_TENSOR_13_DIM_1_SIZE 0xF46CF0 + +#define mmTPC5_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xF46CF4 + +#define mmTPC5_CFG_QM_TENSOR_13_DIM_2_SIZE 0xF46CF8 + +#define mmTPC5_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xF46CFC + +#define mmTPC5_CFG_QM_TENSOR_13_DIM_3_SIZE 0xF46D00 + +#define mmTPC5_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xF46D04 + +#define mmTPC5_CFG_QM_TENSOR_13_DIM_4_SIZE 0xF46D08 + +#define mmTPC5_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xF46D0C + +#define mmTPC5_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xF46D10 + +#define mmTPC5_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xF46D14 + +#define mmTPC5_CFG_QM_TENSOR_14_PADDING_VALUE 0xF46D18 + +#define mmTPC5_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xF46D1C + +#define mmTPC5_CFG_QM_TENSOR_14_DIM_0_SIZE 0xF46D20 + +#define mmTPC5_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xF46D24 + +#define mmTPC5_CFG_QM_TENSOR_14_DIM_1_SIZE 0xF46D28 + +#define mmTPC5_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xF46D2C + +#define mmTPC5_CFG_QM_TENSOR_14_DIM_2_SIZE 0xF46D30 + +#define mmTPC5_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xF46D34 + +#define mmTPC5_CFG_QM_TENSOR_14_DIM_3_SIZE 0xF46D38 + +#define mmTPC5_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xF46D3C + +#define mmTPC5_CFG_QM_TENSOR_14_DIM_4_SIZE 0xF46D40 + +#define mmTPC5_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xF46D44 + +#define mmTPC5_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xF46D48 + +#define mmTPC5_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xF46D4C + +#define mmTPC5_CFG_QM_TENSOR_15_PADDING_VALUE 0xF46D50 + +#define mmTPC5_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xF46D54 + +#define mmTPC5_CFG_QM_TENSOR_15_DIM_0_SIZE 0xF46D58 + +#define mmTPC5_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xF46D5C + +#define mmTPC5_CFG_QM_TENSOR_15_DIM_1_SIZE 0xF46D60 + +#define mmTPC5_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xF46D64 + +#define mmTPC5_CFG_QM_TENSOR_15_DIM_2_SIZE 0xF46D68 + +#define mmTPC5_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xF46D6C + +#define mmTPC5_CFG_QM_TENSOR_15_DIM_3_SIZE 0xF46D70 + +#define mmTPC5_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xF46D74 + +#define mmTPC5_CFG_QM_TENSOR_15_DIM_4_SIZE 0xF46D78 + +#define mmTPC5_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xF46D7C + +#define mmTPC5_CFG_QM_SYNC_OBJECT_MESSAGE 0xF46D80 + +#define mmTPC5_CFG_QM_SYNC_OBJECT_ADDR 0xF46D84 + +#define mmTPC5_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF46D88 + +#define mmTPC5_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF46D8C + +#define mmTPC5_CFG_QM_TID_BASE_DIM_0 0xF46D90 + +#define mmTPC5_CFG_QM_TID_SIZE_DIM_0 0xF46D94 + +#define mmTPC5_CFG_QM_TID_BASE_DIM_1 0xF46D98 + +#define mmTPC5_CFG_QM_TID_SIZE_DIM_1 0xF46D9C + +#define mmTPC5_CFG_QM_TID_BASE_DIM_2 0xF46DA0 + +#define mmTPC5_CFG_QM_TID_SIZE_DIM_2 0xF46DA4 + +#define mmTPC5_CFG_QM_TID_BASE_DIM_3 0xF46DA8 + +#define mmTPC5_CFG_QM_TID_SIZE_DIM_3 0xF46DAC + +#define mmTPC5_CFG_QM_TID_BASE_DIM_4 0xF46DB0 + +#define mmTPC5_CFG_QM_TID_SIZE_DIM_4 0xF46DB4 + +#define mmTPC5_CFG_QM_KERNEL_CONFIG 0xF46DB8 + +#define mmTPC5_CFG_QM_KERNEL_ID 0xF46DBC + +#define mmTPC5_CFG_QM_SRF_0 0xF46DC0 + +#define mmTPC5_CFG_QM_SRF_1 0xF46DC4 + +#define mmTPC5_CFG_QM_SRF_2 0xF46DC8 + +#define mmTPC5_CFG_QM_SRF_3 0xF46DCC + +#define mmTPC5_CFG_QM_SRF_4 0xF46DD0 + +#define mmTPC5_CFG_QM_SRF_5 0xF46DD4 + +#define mmTPC5_CFG_QM_SRF_6 0xF46DD8 + +#define mmTPC5_CFG_QM_SRF_7 0xF46DDC + +#define mmTPC5_CFG_QM_SRF_8 0xF46DE0 + +#define mmTPC5_CFG_QM_SRF_9 0xF46DE4 + +#define mmTPC5_CFG_QM_SRF_10 0xF46DE8 + +#define mmTPC5_CFG_QM_SRF_11 0xF46DEC + +#define mmTPC5_CFG_QM_SRF_12 0xF46DF0 + +#define mmTPC5_CFG_QM_SRF_13 0xF46DF4 + +#define mmTPC5_CFG_QM_SRF_14 0xF46DF8 + +#define mmTPC5_CFG_QM_SRF_15 0xF46DFC + +#define mmTPC5_CFG_QM_SRF_16 0xF46E00 + +#define mmTPC5_CFG_QM_SRF_17 0xF46E04 + +#define mmTPC5_CFG_QM_SRF_18 0xF46E08 + +#define mmTPC5_CFG_QM_SRF_19 0xF46E0C + +#define mmTPC5_CFG_QM_SRF_20 0xF46E10 + +#define mmTPC5_CFG_QM_SRF_21 0xF46E14 + +#define mmTPC5_CFG_QM_SRF_22 0xF46E18 + +#define mmTPC5_CFG_QM_SRF_23 0xF46E1C + +#define mmTPC5_CFG_QM_SRF_24 0xF46E20 + +#define mmTPC5_CFG_QM_SRF_25 0xF46E24 + +#define mmTPC5_CFG_QM_SRF_26 0xF46E28 + +#define mmTPC5_CFG_QM_SRF_27 0xF46E2C + +#define mmTPC5_CFG_QM_SRF_28 0xF46E30 + +#define mmTPC5_CFG_QM_SRF_29 0xF46E34 + +#define mmTPC5_CFG_QM_SRF_30 0xF46E38 + +#define mmTPC5_CFG_QM_SRF_31 0xF46E3C + +#endif /* ASIC_REG_TPC5_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc5_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc5_qm_regs.h new file mode 100644 index 000000000000..cd3a810ff4c4 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc5_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC5_QM_REGS_H_ +#define ASIC_REG_TPC5_QM_REGS_H_ + +/* + ***************************************** + * TPC5_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC5_QM_GLBL_CFG0 0xF48000 + +#define mmTPC5_QM_GLBL_CFG1 0xF48004 + +#define mmTPC5_QM_GLBL_PROT 0xF48008 + +#define mmTPC5_QM_GLBL_ERR_CFG 0xF4800C + +#define mmTPC5_QM_GLBL_SECURE_PROPS_0 0xF48010 + +#define mmTPC5_QM_GLBL_SECURE_PROPS_1 0xF48014 + +#define mmTPC5_QM_GLBL_SECURE_PROPS_2 0xF48018 + +#define mmTPC5_QM_GLBL_SECURE_PROPS_3 0xF4801C + +#define mmTPC5_QM_GLBL_SECURE_PROPS_4 0xF48020 + +#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_0 0xF48024 + +#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_1 0xF48028 + +#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_2 0xF4802C + +#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_3 0xF48030 + +#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_4 0xF48034 + +#define mmTPC5_QM_GLBL_STS0 0xF48038 + +#define mmTPC5_QM_GLBL_STS1_0 0xF48040 + +#define mmTPC5_QM_GLBL_STS1_1 0xF48044 + +#define mmTPC5_QM_GLBL_STS1_2 0xF48048 + +#define mmTPC5_QM_GLBL_STS1_3 0xF4804C + +#define mmTPC5_QM_GLBL_STS1_4 0xF48050 + +#define mmTPC5_QM_GLBL_MSG_EN_0 0xF48054 + +#define mmTPC5_QM_GLBL_MSG_EN_1 0xF48058 + +#define mmTPC5_QM_GLBL_MSG_EN_2 0xF4805C + +#define mmTPC5_QM_GLBL_MSG_EN_3 0xF48060 + +#define mmTPC5_QM_GLBL_MSG_EN_4 0xF48068 + +#define mmTPC5_QM_PQ_BASE_LO_0 0xF48070 + +#define mmTPC5_QM_PQ_BASE_LO_1 0xF48074 + +#define mmTPC5_QM_PQ_BASE_LO_2 0xF48078 + +#define mmTPC5_QM_PQ_BASE_LO_3 0xF4807C + +#define mmTPC5_QM_PQ_BASE_HI_0 0xF48080 + +#define mmTPC5_QM_PQ_BASE_HI_1 0xF48084 + +#define mmTPC5_QM_PQ_BASE_HI_2 0xF48088 + +#define mmTPC5_QM_PQ_BASE_HI_3 0xF4808C + +#define mmTPC5_QM_PQ_SIZE_0 0xF48090 + +#define mmTPC5_QM_PQ_SIZE_1 0xF48094 + +#define mmTPC5_QM_PQ_SIZE_2 0xF48098 + +#define mmTPC5_QM_PQ_SIZE_3 0xF4809C + +#define mmTPC5_QM_PQ_PI_0 0xF480A0 + +#define mmTPC5_QM_PQ_PI_1 0xF480A4 + +#define mmTPC5_QM_PQ_PI_2 0xF480A8 + +#define mmTPC5_QM_PQ_PI_3 0xF480AC + +#define mmTPC5_QM_PQ_CI_0 0xF480B0 + +#define mmTPC5_QM_PQ_CI_1 0xF480B4 + +#define mmTPC5_QM_PQ_CI_2 0xF480B8 + +#define mmTPC5_QM_PQ_CI_3 0xF480BC + +#define mmTPC5_QM_PQ_CFG0_0 0xF480C0 + +#define mmTPC5_QM_PQ_CFG0_1 0xF480C4 + +#define mmTPC5_QM_PQ_CFG0_2 0xF480C8 + +#define mmTPC5_QM_PQ_CFG0_3 0xF480CC + +#define mmTPC5_QM_PQ_CFG1_0 0xF480D0 + +#define mmTPC5_QM_PQ_CFG1_1 0xF480D4 + +#define mmTPC5_QM_PQ_CFG1_2 0xF480D8 + +#define mmTPC5_QM_PQ_CFG1_3 0xF480DC + +#define mmTPC5_QM_PQ_ARUSER_31_11_0 0xF480E0 + +#define mmTPC5_QM_PQ_ARUSER_31_11_1 0xF480E4 + +#define mmTPC5_QM_PQ_ARUSER_31_11_2 0xF480E8 + +#define mmTPC5_QM_PQ_ARUSER_31_11_3 0xF480EC + +#define mmTPC5_QM_PQ_STS0_0 0xF480F0 + +#define mmTPC5_QM_PQ_STS0_1 0xF480F4 + +#define mmTPC5_QM_PQ_STS0_2 0xF480F8 + +#define mmTPC5_QM_PQ_STS0_3 0xF480FC + +#define mmTPC5_QM_PQ_STS1_0 0xF48100 + +#define mmTPC5_QM_PQ_STS1_1 0xF48104 + +#define mmTPC5_QM_PQ_STS1_2 0xF48108 + +#define mmTPC5_QM_PQ_STS1_3 0xF4810C + +#define mmTPC5_QM_CQ_CFG0_0 0xF48110 + +#define mmTPC5_QM_CQ_CFG0_1 0xF48114 + +#define mmTPC5_QM_CQ_CFG0_2 0xF48118 + +#define mmTPC5_QM_CQ_CFG0_3 0xF4811C + +#define mmTPC5_QM_CQ_CFG0_4 0xF48120 + +#define mmTPC5_QM_CQ_CFG1_0 0xF48124 + +#define mmTPC5_QM_CQ_CFG1_1 0xF48128 + +#define mmTPC5_QM_CQ_CFG1_2 0xF4812C + +#define mmTPC5_QM_CQ_CFG1_3 0xF48130 + +#define mmTPC5_QM_CQ_CFG1_4 0xF48134 + +#define mmTPC5_QM_CQ_ARUSER_31_11_0 0xF48138 + +#define mmTPC5_QM_CQ_ARUSER_31_11_1 0xF4813C + +#define mmTPC5_QM_CQ_ARUSER_31_11_2 0xF48140 + +#define mmTPC5_QM_CQ_ARUSER_31_11_3 0xF48144 + +#define mmTPC5_QM_CQ_ARUSER_31_11_4 0xF48148 + +#define mmTPC5_QM_CQ_STS0_0 0xF4814C + +#define mmTPC5_QM_CQ_STS0_1 0xF48150 + +#define mmTPC5_QM_CQ_STS0_2 0xF48154 + +#define mmTPC5_QM_CQ_STS0_3 0xF48158 + +#define mmTPC5_QM_CQ_STS0_4 0xF4815C + +#define mmTPC5_QM_CQ_STS1_0 0xF48160 + +#define mmTPC5_QM_CQ_STS1_1 0xF48164 + +#define mmTPC5_QM_CQ_STS1_2 0xF48168 + +#define mmTPC5_QM_CQ_STS1_3 0xF4816C + +#define mmTPC5_QM_CQ_STS1_4 0xF48170 + +#define mmTPC5_QM_CQ_PTR_LO_0 0xF48174 + +#define mmTPC5_QM_CQ_PTR_HI_0 0xF48178 + +#define mmTPC5_QM_CQ_TSIZE_0 0xF4817C + +#define mmTPC5_QM_CQ_CTL_0 0xF48180 + +#define mmTPC5_QM_CQ_PTR_LO_1 0xF48184 + +#define mmTPC5_QM_CQ_PTR_HI_1 0xF48188 + +#define mmTPC5_QM_CQ_TSIZE_1 0xF4818C + +#define mmTPC5_QM_CQ_CTL_1 0xF48190 + +#define mmTPC5_QM_CQ_PTR_LO_2 0xF48194 + +#define mmTPC5_QM_CQ_PTR_HI_2 0xF48198 + +#define mmTPC5_QM_CQ_TSIZE_2 0xF4819C + +#define mmTPC5_QM_CQ_CTL_2 0xF481A0 + +#define mmTPC5_QM_CQ_PTR_LO_3 0xF481A4 + +#define mmTPC5_QM_CQ_PTR_HI_3 0xF481A8 + +#define mmTPC5_QM_CQ_TSIZE_3 0xF481AC + +#define mmTPC5_QM_CQ_CTL_3 0xF481B0 + +#define mmTPC5_QM_CQ_PTR_LO_4 0xF481B4 + +#define mmTPC5_QM_CQ_PTR_HI_4 0xF481B8 + +#define mmTPC5_QM_CQ_TSIZE_4 0xF481BC + +#define mmTPC5_QM_CQ_CTL_4 0xF481C0 + +#define mmTPC5_QM_CQ_PTR_LO_STS_0 0xF481C4 + +#define mmTPC5_QM_CQ_PTR_LO_STS_1 0xF481C8 + +#define mmTPC5_QM_CQ_PTR_LO_STS_2 0xF481CC + +#define mmTPC5_QM_CQ_PTR_LO_STS_3 0xF481D0 + +#define mmTPC5_QM_CQ_PTR_LO_STS_4 0xF481D4 + +#define mmTPC5_QM_CQ_PTR_HI_STS_0 0xF481D8 + +#define mmTPC5_QM_CQ_PTR_HI_STS_1 0xF481DC + +#define mmTPC5_QM_CQ_PTR_HI_STS_2 0xF481E0 + +#define mmTPC5_QM_CQ_PTR_HI_STS_3 0xF481E4 + +#define mmTPC5_QM_CQ_PTR_HI_STS_4 0xF481E8 + +#define mmTPC5_QM_CQ_TSIZE_STS_0 0xF481EC + +#define mmTPC5_QM_CQ_TSIZE_STS_1 0xF481F0 + +#define mmTPC5_QM_CQ_TSIZE_STS_2 0xF481F4 + +#define mmTPC5_QM_CQ_TSIZE_STS_3 0xF481F8 + +#define mmTPC5_QM_CQ_TSIZE_STS_4 0xF481FC + +#define mmTPC5_QM_CQ_CTL_STS_0 0xF48200 + +#define mmTPC5_QM_CQ_CTL_STS_1 0xF48204 + +#define mmTPC5_QM_CQ_CTL_STS_2 0xF48208 + +#define mmTPC5_QM_CQ_CTL_STS_3 0xF4820C + +#define mmTPC5_QM_CQ_CTL_STS_4 0xF48210 + +#define mmTPC5_QM_CQ_IFIFO_CNT_0 0xF48214 + +#define mmTPC5_QM_CQ_IFIFO_CNT_1 0xF48218 + +#define mmTPC5_QM_CQ_IFIFO_CNT_2 0xF4821C + +#define mmTPC5_QM_CQ_IFIFO_CNT_3 0xF48220 + +#define mmTPC5_QM_CQ_IFIFO_CNT_4 0xF48224 + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_0 0xF48228 + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_1 0xF4822C + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_2 0xF48230 + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_3 0xF48234 + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_4 0xF48238 + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_0 0xF4823C + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_1 0xF48240 + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_2 0xF48244 + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_3 0xF48248 + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_4 0xF4824C + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_0 0xF48250 + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_1 0xF48254 + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_2 0xF48258 + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_3 0xF4825C + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_4 0xF48260 + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_0 0xF48264 + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_1 0xF48268 + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_2 0xF4826C + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_3 0xF48270 + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_4 0xF48274 + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_0 0xF48278 + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_1 0xF4827C + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_2 0xF48280 + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_3 0xF48284 + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_4 0xF48288 + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_0 0xF4828C + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_1 0xF48290 + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_2 0xF48294 + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_3 0xF48298 + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_4 0xF4829C + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_0 0xF482A0 + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_1 0xF482A4 + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_2 0xF482A8 + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_3 0xF482AC + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_4 0xF482B0 + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_0 0xF482B4 + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_1 0xF482B8 + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_2 0xF482BC + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_3 0xF482C0 + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_4 0xF482C4 + +#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_0 0xF482C8 + +#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_1 0xF482CC + +#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_2 0xF482D0 + +#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_3 0xF482D4 + +#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_4 0xF482D8 + +#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xF482E0 + +#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xF482E4 + +#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xF482E8 + +#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xF482EC + +#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xF482F0 + +#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xF482F4 + +#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xF482F8 + +#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xF482FC + +#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xF48300 + +#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xF48304 + +#define mmTPC5_QM_CP_FENCE0_RDATA_0 0xF48308 + +#define mmTPC5_QM_CP_FENCE0_RDATA_1 0xF4830C + +#define mmTPC5_QM_CP_FENCE0_RDATA_2 0xF48310 + +#define mmTPC5_QM_CP_FENCE0_RDATA_3 0xF48314 + +#define mmTPC5_QM_CP_FENCE0_RDATA_4 0xF48318 + +#define mmTPC5_QM_CP_FENCE1_RDATA_0 0xF4831C + +#define mmTPC5_QM_CP_FENCE1_RDATA_1 0xF48320 + +#define mmTPC5_QM_CP_FENCE1_RDATA_2 0xF48324 + +#define mmTPC5_QM_CP_FENCE1_RDATA_3 0xF48328 + +#define mmTPC5_QM_CP_FENCE1_RDATA_4 0xF4832C + +#define mmTPC5_QM_CP_FENCE2_RDATA_0 0xF48330 + +#define mmTPC5_QM_CP_FENCE2_RDATA_1 0xF48334 + +#define mmTPC5_QM_CP_FENCE2_RDATA_2 0xF48338 + +#define mmTPC5_QM_CP_FENCE2_RDATA_3 0xF4833C + +#define mmTPC5_QM_CP_FENCE2_RDATA_4 0xF48340 + +#define mmTPC5_QM_CP_FENCE3_RDATA_0 0xF48344 + +#define mmTPC5_QM_CP_FENCE3_RDATA_1 0xF48348 + +#define mmTPC5_QM_CP_FENCE3_RDATA_2 0xF4834C + +#define mmTPC5_QM_CP_FENCE3_RDATA_3 0xF48350 + +#define mmTPC5_QM_CP_FENCE3_RDATA_4 0xF48354 + +#define mmTPC5_QM_CP_FENCE0_CNT_0 0xF48358 + +#define mmTPC5_QM_CP_FENCE0_CNT_1 0xF4835C + +#define mmTPC5_QM_CP_FENCE0_CNT_2 0xF48360 + +#define mmTPC5_QM_CP_FENCE0_CNT_3 0xF48364 + +#define mmTPC5_QM_CP_FENCE0_CNT_4 0xF48368 + +#define mmTPC5_QM_CP_FENCE1_CNT_0 0xF4836C + +#define mmTPC5_QM_CP_FENCE1_CNT_1 0xF48370 + +#define mmTPC5_QM_CP_FENCE1_CNT_2 0xF48374 + +#define mmTPC5_QM_CP_FENCE1_CNT_3 0xF48378 + +#define mmTPC5_QM_CP_FENCE1_CNT_4 0xF4837C + +#define mmTPC5_QM_CP_FENCE2_CNT_0 0xF48380 + +#define mmTPC5_QM_CP_FENCE2_CNT_1 0xF48384 + +#define mmTPC5_QM_CP_FENCE2_CNT_2 0xF48388 + +#define mmTPC5_QM_CP_FENCE2_CNT_3 0xF4838C + +#define mmTPC5_QM_CP_FENCE2_CNT_4 0xF48390 + +#define mmTPC5_QM_CP_FENCE3_CNT_0 0xF48394 + +#define mmTPC5_QM_CP_FENCE3_CNT_1 0xF48398 + +#define mmTPC5_QM_CP_FENCE3_CNT_2 0xF4839C + +#define mmTPC5_QM_CP_FENCE3_CNT_3 0xF483A0 + +#define mmTPC5_QM_CP_FENCE3_CNT_4 0xF483A4 + +#define mmTPC5_QM_CP_STS_0 0xF483A8 + +#define mmTPC5_QM_CP_STS_1 0xF483AC + +#define mmTPC5_QM_CP_STS_2 0xF483B0 + +#define mmTPC5_QM_CP_STS_3 0xF483B4 + +#define mmTPC5_QM_CP_STS_4 0xF483B8 + +#define mmTPC5_QM_CP_CURRENT_INST_LO_0 0xF483BC + +#define mmTPC5_QM_CP_CURRENT_INST_LO_1 0xF483C0 + +#define mmTPC5_QM_CP_CURRENT_INST_LO_2 0xF483C4 + +#define mmTPC5_QM_CP_CURRENT_INST_LO_3 0xF483C8 + +#define mmTPC5_QM_CP_CURRENT_INST_LO_4 0xF483CC + +#define mmTPC5_QM_CP_CURRENT_INST_HI_0 0xF483D0 + +#define mmTPC5_QM_CP_CURRENT_INST_HI_1 0xF483D4 + +#define mmTPC5_QM_CP_CURRENT_INST_HI_2 0xF483D8 + +#define mmTPC5_QM_CP_CURRENT_INST_HI_3 0xF483DC + +#define mmTPC5_QM_CP_CURRENT_INST_HI_4 0xF483E0 + +#define mmTPC5_QM_CP_BARRIER_CFG_0 0xF483F4 + +#define mmTPC5_QM_CP_BARRIER_CFG_1 0xF483F8 + +#define mmTPC5_QM_CP_BARRIER_CFG_2 0xF483FC + +#define mmTPC5_QM_CP_BARRIER_CFG_3 0xF48400 + +#define mmTPC5_QM_CP_BARRIER_CFG_4 0xF48404 + +#define mmTPC5_QM_CP_DBG_0_0 0xF48408 + +#define mmTPC5_QM_CP_DBG_0_1 0xF4840C + +#define mmTPC5_QM_CP_DBG_0_2 0xF48410 + +#define mmTPC5_QM_CP_DBG_0_3 0xF48414 + +#define mmTPC5_QM_CP_DBG_0_4 0xF48418 + +#define mmTPC5_QM_CP_ARUSER_31_11_0 0xF4841C + +#define mmTPC5_QM_CP_ARUSER_31_11_1 0xF48420 + +#define mmTPC5_QM_CP_ARUSER_31_11_2 0xF48424 + +#define mmTPC5_QM_CP_ARUSER_31_11_3 0xF48428 + +#define mmTPC5_QM_CP_ARUSER_31_11_4 0xF4842C + +#define mmTPC5_QM_CP_AWUSER_31_11_0 0xF48430 + +#define mmTPC5_QM_CP_AWUSER_31_11_1 0xF48434 + +#define mmTPC5_QM_CP_AWUSER_31_11_2 0xF48438 + +#define mmTPC5_QM_CP_AWUSER_31_11_3 0xF4843C + +#define mmTPC5_QM_CP_AWUSER_31_11_4 0xF48440 + +#define mmTPC5_QM_ARB_CFG_0 0xF48A00 + +#define mmTPC5_QM_ARB_CHOISE_Q_PUSH 0xF48A04 + +#define mmTPC5_QM_ARB_WRR_WEIGHT_0 0xF48A08 + +#define mmTPC5_QM_ARB_WRR_WEIGHT_1 0xF48A0C + +#define mmTPC5_QM_ARB_WRR_WEIGHT_2 0xF48A10 + +#define mmTPC5_QM_ARB_WRR_WEIGHT_3 0xF48A14 + +#define mmTPC5_QM_ARB_CFG_1 0xF48A18 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_0 0xF48A20 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_1 0xF48A24 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_2 0xF48A28 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_3 0xF48A2C + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_4 0xF48A30 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_5 0xF48A34 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_6 0xF48A38 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_7 0xF48A3C + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_8 0xF48A40 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_9 0xF48A44 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_10 0xF48A48 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_11 0xF48A4C + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_12 0xF48A50 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_13 0xF48A54 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_14 0xF48A58 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_15 0xF48A5C + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_16 0xF48A60 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_17 0xF48A64 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_18 0xF48A68 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_19 0xF48A6C + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_20 0xF48A70 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_21 0xF48A74 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_22 0xF48A78 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_23 0xF48A7C + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_24 0xF48A80 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_25 0xF48A84 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_26 0xF48A88 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_27 0xF48A8C + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_28 0xF48A90 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_29 0xF48A94 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_30 0xF48A98 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_31 0xF48A9C + +#define mmTPC5_QM_ARB_MST_CRED_INC 0xF48AA0 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xF48AA4 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xF48AA8 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xF48AAC + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xF48AB0 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xF48AB4 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xF48AB8 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xF48ABC + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xF48AC0 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xF48AC4 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xF48AC8 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xF48ACC + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xF48AD0 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xF48AD4 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xF48AD8 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xF48ADC + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xF48AE0 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xF48AE4 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xF48AE8 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xF48AEC + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xF48AF0 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xF48AF4 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xF48AF8 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xF48AFC + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xF48B00 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xF48B04 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xF48B08 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xF48B0C + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xF48B10 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xF48B14 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xF48B18 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xF48B1C + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xF48B20 + +#define mmTPC5_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xF48B28 + +#define mmTPC5_QM_ARB_MST_SLAVE_EN 0xF48B2C + +#define mmTPC5_QM_ARB_MST_QUIET_PER 0xF48B34 + +#define mmTPC5_QM_ARB_SLV_CHOISE_WDT 0xF48B38 + +#define mmTPC5_QM_ARB_SLV_ID 0xF48B3C + +#define mmTPC5_QM_ARB_MSG_MAX_INFLIGHT 0xF48B44 + +#define mmTPC5_QM_ARB_MSG_AWUSER_31_11 0xF48B48 + +#define mmTPC5_QM_ARB_MSG_AWUSER_SEC_PROP 0xF48B4C + +#define mmTPC5_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xF48B50 + +#define mmTPC5_QM_ARB_BASE_LO 0xF48B54 + +#define mmTPC5_QM_ARB_BASE_HI 0xF48B58 + +#define mmTPC5_QM_ARB_STATE_STS 0xF48B80 + +#define mmTPC5_QM_ARB_CHOISE_FULLNESS_STS 0xF48B84 + +#define mmTPC5_QM_ARB_MSG_STS 0xF48B88 + +#define mmTPC5_QM_ARB_SLV_CHOISE_Q_HEAD 0xF48B8C + +#define mmTPC5_QM_ARB_ERR_CAUSE 0xF48B9C + +#define mmTPC5_QM_ARB_ERR_MSG_EN 0xF48BA0 + +#define mmTPC5_QM_ARB_ERR_STS_DRP 0xF48BA8 + +#define mmTPC5_QM_ARB_MST_CRED_STS_0 0xF48BB0 + +#define mmTPC5_QM_ARB_MST_CRED_STS_1 0xF48BB4 + +#define mmTPC5_QM_ARB_MST_CRED_STS_2 0xF48BB8 + +#define mmTPC5_QM_ARB_MST_CRED_STS_3 0xF48BBC + +#define mmTPC5_QM_ARB_MST_CRED_STS_4 0xF48BC0 + +#define mmTPC5_QM_ARB_MST_CRED_STS_5 0xF48BC4 + +#define mmTPC5_QM_ARB_MST_CRED_STS_6 0xF48BC8 + +#define mmTPC5_QM_ARB_MST_CRED_STS_7 0xF48BCC + +#define mmTPC5_QM_ARB_MST_CRED_STS_8 0xF48BD0 + +#define mmTPC5_QM_ARB_MST_CRED_STS_9 0xF48BD4 + +#define mmTPC5_QM_ARB_MST_CRED_STS_10 0xF48BD8 + +#define mmTPC5_QM_ARB_MST_CRED_STS_11 0xF48BDC + +#define mmTPC5_QM_ARB_MST_CRED_STS_12 0xF48BE0 + +#define mmTPC5_QM_ARB_MST_CRED_STS_13 0xF48BE4 + +#define mmTPC5_QM_ARB_MST_CRED_STS_14 0xF48BE8 + +#define mmTPC5_QM_ARB_MST_CRED_STS_15 0xF48BEC + +#define mmTPC5_QM_ARB_MST_CRED_STS_16 0xF48BF0 + +#define mmTPC5_QM_ARB_MST_CRED_STS_17 0xF48BF4 + +#define mmTPC5_QM_ARB_MST_CRED_STS_18 0xF48BF8 + +#define mmTPC5_QM_ARB_MST_CRED_STS_19 0xF48BFC + +#define mmTPC5_QM_ARB_MST_CRED_STS_20 0xF48C00 + +#define mmTPC5_QM_ARB_MST_CRED_STS_21 0xF48C04 + +#define mmTPC5_QM_ARB_MST_CRED_STS_22 0xF48C08 + +#define mmTPC5_QM_ARB_MST_CRED_STS_23 0xF48C0C + +#define mmTPC5_QM_ARB_MST_CRED_STS_24 0xF48C10 + +#define mmTPC5_QM_ARB_MST_CRED_STS_25 0xF48C14 + +#define mmTPC5_QM_ARB_MST_CRED_STS_26 0xF48C18 + +#define mmTPC5_QM_ARB_MST_CRED_STS_27 0xF48C1C + +#define mmTPC5_QM_ARB_MST_CRED_STS_28 0xF48C20 + +#define mmTPC5_QM_ARB_MST_CRED_STS_29 0xF48C24 + +#define mmTPC5_QM_ARB_MST_CRED_STS_30 0xF48C28 + +#define mmTPC5_QM_ARB_MST_CRED_STS_31 0xF48C2C + +#define mmTPC5_QM_CGM_CFG 0xF48C70 + +#define mmTPC5_QM_CGM_STS 0xF48C74 + +#define mmTPC5_QM_CGM_CFG1 0xF48C78 + +#define mmTPC5_QM_LOCAL_RANGE_BASE 0xF48C80 + +#define mmTPC5_QM_LOCAL_RANGE_SIZE 0xF48C84 + +#define mmTPC5_QM_CSMR_STRICT_PRIO_CFG 0xF48C90 + +#define mmTPC5_QM_HBW_RD_RATE_LIM_CFG_1 0xF48C94 + +#define mmTPC5_QM_LBW_WR_RATE_LIM_CFG_0 0xF48C98 + +#define mmTPC5_QM_LBW_WR_RATE_LIM_CFG_1 0xF48C9C + +#define mmTPC5_QM_HBW_RD_RATE_LIM_CFG_0 0xF48CA0 + +#define mmTPC5_QM_GLBL_AXCACHE 0xF48CA4 + +#define mmTPC5_QM_IND_GW_APB_CFG 0xF48CB0 + +#define mmTPC5_QM_IND_GW_APB_WDATA 0xF48CB4 + +#define mmTPC5_QM_IND_GW_APB_RDATA 0xF48CB8 + +#define mmTPC5_QM_IND_GW_APB_STATUS 0xF48CBC + +#define mmTPC5_QM_GLBL_ERR_ADDR_LO 0xF48CD0 + +#define mmTPC5_QM_GLBL_ERR_ADDR_HI 0xF48CD4 + +#define mmTPC5_QM_GLBL_ERR_WDATA 0xF48CD8 + +#define mmTPC5_QM_GLBL_MEM_INIT_BUSY 0xF48D00 + +#endif /* ASIC_REG_TPC5_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc6_cfg_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc6_cfg_regs.h new file mode 100644 index 000000000000..eb251e72813f --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc6_cfg_regs.h @@ -0,0 +1,1226 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC6_CFG_REGS_H_ +#define ASIC_REG_TPC6_CFG_REGS_H_ + +/* + ***************************************** + * TPC6_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC6_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF86400 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF86404 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF86408 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF8640C + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF86410 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF86414 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF86418 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF8641C + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF86420 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF86424 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF86428 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF8642C + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF86430 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF86434 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF86438 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF8643C + +#define mmTPC6_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF86440 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF86444 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF86448 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF8644C + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF86450 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF86454 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF86458 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF8645C + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF86460 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF86464 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF86468 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF8646C + +#define mmTPC6_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF86470 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF86474 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF86478 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF8647C + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF86480 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF86484 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF86488 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF8648C + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF86490 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF86494 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF86498 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF8649C + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF864A0 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF864A4 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF864A8 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF864AC + +#define mmTPC6_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF864B0 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF864B4 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF864B8 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF864BC + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF864C0 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF864C4 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF864C8 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF864CC + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF864D0 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF864D4 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF864D8 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF864DC + +#define mmTPC6_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF864E0 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF864E4 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF864E8 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF864EC + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF864F0 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF864F4 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF864F8 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF864FC + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF86500 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF86504 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF86508 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF8650C + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF86510 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF86514 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF86518 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF8651C + +#define mmTPC6_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF86520 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF86524 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF86528 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF8652C + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF86530 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF86534 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF86538 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF8653C + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF86540 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF86544 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF86548 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF8654C + +#define mmTPC6_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF86550 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF86554 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF86558 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF8655C + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF86560 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF86564 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF86568 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF8656C + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF86570 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF86574 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF86578 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF8657C + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF86580 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF86584 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF86588 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF8658C + +#define mmTPC6_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF86590 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF86594 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF86598 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF8659C + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF865A0 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF865A4 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF865A8 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF865AC + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF865B0 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF865B4 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF865B8 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF865BC + +#define mmTPC6_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xF865C0 + +#define mmTPC6_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xF865C4 + +#define mmTPC6_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xF865C8 + +#define mmTPC6_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xF865CC + +#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xF865D0 + +#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xF865D4 + +#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xF865D8 + +#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xF865DC + +#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xF865E0 + +#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xF865E4 + +#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xF865E8 + +#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xF865EC + +#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xF865F0 + +#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xF865F4 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xF865F8 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xF865FC + +#define mmTPC6_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xF86600 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xF86604 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xF86608 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xF8660C + +#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xF86610 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xF86614 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xF86618 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xF8661C + +#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xF86620 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xF86624 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xF86628 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xF8662C + +#define mmTPC6_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xF86630 + +#define mmTPC6_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xF86634 + +#define mmTPC6_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xF86638 + +#define mmTPC6_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xF8663C + +#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xF86640 + +#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xF86644 + +#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xF86648 + +#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xF8664C + +#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xF86650 + +#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xF86654 + +#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xF86658 + +#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xF8665C + +#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xF86660 + +#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xF86664 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xF86668 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xF8666C + +#define mmTPC6_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xF86670 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xF86674 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xF86678 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xF8667C + +#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xF86680 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xF86684 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xF86688 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xF8668C + +#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xF86690 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xF86694 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xF86698 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xF8669C + +#define mmTPC6_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xF866A0 + +#define mmTPC6_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xF866A4 + +#define mmTPC6_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xF866A8 + +#define mmTPC6_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xF866AC + +#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xF866B0 + +#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xF866B4 + +#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xF866B8 + +#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xF866BC + +#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xF866C0 + +#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xF866C4 + +#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xF866C8 + +#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xF866CC + +#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xF866D0 + +#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xF866D4 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xF866D8 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xF866DC + +#define mmTPC6_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xF866E0 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xF866E4 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xF866E8 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xF866EC + +#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xF866F0 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xF866F4 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xF866F8 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xF866FC + +#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xF86700 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xF86704 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xF86708 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xF8670C + +#define mmTPC6_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xF86710 + +#define mmTPC6_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xF86714 + +#define mmTPC6_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xF86718 + +#define mmTPC6_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xF8671C + +#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xF86720 + +#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xF86724 + +#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xF86728 + +#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xF8672C + +#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xF86730 + +#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xF86734 + +#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xF86738 + +#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xF8673C + +#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xF86740 + +#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xF86744 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xF86748 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xF8674C + +#define mmTPC6_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xF86750 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xF86754 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xF86758 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xF8675C + +#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xF86760 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xF86764 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xF86768 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xF8676C + +#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xF86770 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xF86774 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xF86778 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xF8677C + +#define mmTPC6_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF86780 + +#define mmTPC6_CFG_KERNEL_SYNC_OBJECT_ADDR 0xF86784 + +#define mmTPC6_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF86788 + +#define mmTPC6_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF8678C + +#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_0 0xF86790 + +#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_0 0xF86794 + +#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_1 0xF86798 + +#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_1 0xF8679C + +#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_2 0xF867A0 + +#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_2 0xF867A4 + +#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_3 0xF867A8 + +#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_3 0xF867AC + +#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_4 0xF867B0 + +#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_4 0xF867B4 + +#define mmTPC6_CFG_KERNEL_KERNEL_CONFIG 0xF867B8 + +#define mmTPC6_CFG_KERNEL_KERNEL_ID 0xF867BC + +#define mmTPC6_CFG_KERNEL_SRF_0 0xF867C0 + +#define mmTPC6_CFG_KERNEL_SRF_1 0xF867C4 + +#define mmTPC6_CFG_KERNEL_SRF_2 0xF867C8 + +#define mmTPC6_CFG_KERNEL_SRF_3 0xF867CC + +#define mmTPC6_CFG_KERNEL_SRF_4 0xF867D0 + +#define mmTPC6_CFG_KERNEL_SRF_5 0xF867D4 + +#define mmTPC6_CFG_KERNEL_SRF_6 0xF867D8 + +#define mmTPC6_CFG_KERNEL_SRF_7 0xF867DC + +#define mmTPC6_CFG_KERNEL_SRF_8 0xF867E0 + +#define mmTPC6_CFG_KERNEL_SRF_9 0xF867E4 + +#define mmTPC6_CFG_KERNEL_SRF_10 0xF867E8 + +#define mmTPC6_CFG_KERNEL_SRF_11 0xF867EC + +#define mmTPC6_CFG_KERNEL_SRF_12 0xF867F0 + +#define mmTPC6_CFG_KERNEL_SRF_13 0xF867F4 + +#define mmTPC6_CFG_KERNEL_SRF_14 0xF867F8 + +#define mmTPC6_CFG_KERNEL_SRF_15 0xF867FC + +#define mmTPC6_CFG_KERNEL_SRF_16 0xF86800 + +#define mmTPC6_CFG_KERNEL_SRF_17 0xF86804 + +#define mmTPC6_CFG_KERNEL_SRF_18 0xF86808 + +#define mmTPC6_CFG_KERNEL_SRF_19 0xF8680C + +#define mmTPC6_CFG_KERNEL_SRF_20 0xF86810 + +#define mmTPC6_CFG_KERNEL_SRF_21 0xF86814 + +#define mmTPC6_CFG_KERNEL_SRF_22 0xF86818 + +#define mmTPC6_CFG_KERNEL_SRF_23 0xF8681C + +#define mmTPC6_CFG_KERNEL_SRF_24 0xF86820 + +#define mmTPC6_CFG_KERNEL_SRF_25 0xF86824 + +#define mmTPC6_CFG_KERNEL_SRF_26 0xF86828 + +#define mmTPC6_CFG_KERNEL_SRF_27 0xF8682C + +#define mmTPC6_CFG_KERNEL_SRF_28 0xF86830 + +#define mmTPC6_CFG_KERNEL_SRF_29 0xF86834 + +#define mmTPC6_CFG_KERNEL_SRF_30 0xF86838 + +#define mmTPC6_CFG_KERNEL_SRF_31 0xF8683C + +#define mmTPC6_CFG_ROUND_CSR 0xF868FC + +#define mmTPC6_CFG_PROT 0xF86900 + +#define mmTPC6_CFG_SEMAPHORE 0xF86908 + +#define mmTPC6_CFG_VFLAGS 0xF8690C + +#define mmTPC6_CFG_SFLAGS 0xF86910 + +#define mmTPC6_CFG_LFSR_POLYNOM 0xF86918 + +#define mmTPC6_CFG_STATUS 0xF8691C + +#define mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH 0xF86920 + +#define mmTPC6_CFG_CFG_SUBTRACT_VALUE 0xF86924 + +#define mmTPC6_CFG_SM_BASE_ADDRESS_HIGH 0xF8692C + +#define mmTPC6_CFG_TPC_CMD 0xF86930 + +#define mmTPC6_CFG_TPC_EXECUTE 0xF86938 + +#define mmTPC6_CFG_TPC_STALL 0xF8693C + +#define mmTPC6_CFG_ICACHE_BASE_ADDERESS_LOW 0xF86940 + +#define mmTPC6_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF86944 + +#define mmTPC6_CFG_RD_RATE_LIMIT 0xF86948 + +#define mmTPC6_CFG_WR_RATE_LIMIT 0xF86950 + +#define mmTPC6_CFG_MSS_CONFIG 0xF86954 + +#define mmTPC6_CFG_TPC_INTR_CAUSE 0xF86958 + +#define mmTPC6_CFG_TPC_INTR_MASK 0xF8695C + +#define mmTPC6_CFG_WQ_CREDITS 0xF86960 + +#define mmTPC6_CFG_ARUSER_LO 0xF86964 + +#define mmTPC6_CFG_ARUSER_HI 0xF86968 + +#define mmTPC6_CFG_AWUSER_LO 0xF8696C + +#define mmTPC6_CFG_AWUSER_HI 0xF86970 + +#define mmTPC6_CFG_OPCODE_EXEC 0xF86974 + +#define mmTPC6_CFG_LUT_FUNC32_BASE_ADDR_LO 0xF86978 + +#define mmTPC6_CFG_LUT_FUNC32_BASE_ADDR_HI 0xF8697C + +#define mmTPC6_CFG_LUT_FUNC64_BASE_ADDR_LO 0xF86980 + +#define mmTPC6_CFG_LUT_FUNC64_BASE_ADDR_HI 0xF86984 + +#define mmTPC6_CFG_LUT_FUNC128_BASE_ADDR_LO 0xF86988 + +#define mmTPC6_CFG_LUT_FUNC128_BASE_ADDR_HI 0xF8698C + +#define mmTPC6_CFG_LUT_FUNC256_BASE_ADDR_LO 0xF86990 + +#define mmTPC6_CFG_LUT_FUNC256_BASE_ADDR_HI 0xF86994 + +#define mmTPC6_CFG_TSB_CFG_MAX_SIZE 0xF86998 + +#define mmTPC6_CFG_TSB_CFG 0xF8699C + +#define mmTPC6_CFG_DBGMEM_ADD 0xF869A0 + +#define mmTPC6_CFG_DBGMEM_DATA_WR 0xF869A4 + +#define mmTPC6_CFG_DBGMEM_DATA_RD 0xF869A8 + +#define mmTPC6_CFG_DBGMEM_CTRL 0xF869AC + +#define mmTPC6_CFG_DBGMEM_RC 0xF869B0 + +#define mmTPC6_CFG_TSB_INFLIGHT_CNTR 0xF869B4 + +#define mmTPC6_CFG_WQ_INFLIGHT_CNTR 0xF869B8 + +#define mmTPC6_CFG_WQ_LBW_TOTAL_CNTR 0xF869BC + +#define mmTPC6_CFG_WQ_HBW_TOTAL_CNTR 0xF869C0 + +#define mmTPC6_CFG_IRQ_OCCOUPY_CNTR 0xF869C4 + +#define mmTPC6_CFG_FUNC_MBIST_CNTRL 0xF869D0 + +#define mmTPC6_CFG_FUNC_MBIST_PAT 0xF869D4 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_0 0xF869D8 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_1 0xF869DC + +#define mmTPC6_CFG_FUNC_MBIST_MEM_2 0xF869E0 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_3 0xF869E4 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_4 0xF869E8 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_5 0xF869EC + +#define mmTPC6_CFG_FUNC_MBIST_MEM_6 0xF869F0 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_7 0xF869F4 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_8 0xF869F8 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_9 0xF869FC + +#define mmTPC6_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF86A00 + +#define mmTPC6_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF86A04 + +#define mmTPC6_CFG_QM_TENSOR_0_PADDING_VALUE 0xF86A08 + +#define mmTPC6_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF86A0C + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF86A10 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF86A14 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF86A18 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF86A1C + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF86A20 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF86A24 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF86A28 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF86A2C + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF86A30 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF86A34 + +#define mmTPC6_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF86A38 + +#define mmTPC6_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF86A3C + +#define mmTPC6_CFG_QM_TENSOR_1_PADDING_VALUE 0xF86A40 + +#define mmTPC6_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF86A44 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF86A48 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF86A4C + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF86A50 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF86A54 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF86A58 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF86A5C + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF86A60 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF86A64 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF86A68 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF86A6C + +#define mmTPC6_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF86A70 + +#define mmTPC6_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF86A74 + +#define mmTPC6_CFG_QM_TENSOR_2_PADDING_VALUE 0xF86A78 + +#define mmTPC6_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF86A7C + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF86A80 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF86A84 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF86A88 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF86A8C + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF86A90 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF86A94 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF86A98 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF86A9C + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF86AA0 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF86AA4 + +#define mmTPC6_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF86AA8 + +#define mmTPC6_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF86AAC + +#define mmTPC6_CFG_QM_TENSOR_3_PADDING_VALUE 0xF86AB0 + +#define mmTPC6_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF86AB4 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF86AB8 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF86ABC + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF86AC0 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF86AC4 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF86AC8 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF86ACC + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF86AD0 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF86AD4 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF86AD8 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF86ADC + +#define mmTPC6_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF86AE0 + +#define mmTPC6_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF86AE4 + +#define mmTPC6_CFG_QM_TENSOR_4_PADDING_VALUE 0xF86AE8 + +#define mmTPC6_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF86AEC + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF86AF0 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF86AF4 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF86AF8 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF86AFC + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF86B00 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF86B04 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF86B08 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF86B0C + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF86B10 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF86B14 + +#define mmTPC6_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF86B18 + +#define mmTPC6_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF86B1C + +#define mmTPC6_CFG_QM_TENSOR_5_PADDING_VALUE 0xF86B20 + +#define mmTPC6_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF86B24 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF86B28 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF86B2C + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF86B30 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF86B34 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF86B38 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF86B3C + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF86B40 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF86B44 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF86B48 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF86B4C + +#define mmTPC6_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF86B50 + +#define mmTPC6_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF86B54 + +#define mmTPC6_CFG_QM_TENSOR_6_PADDING_VALUE 0xF86B58 + +#define mmTPC6_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF86B5C + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF86B60 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF86B64 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF86B68 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF86B6C + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF86B70 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF86B74 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF86B78 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF86B7C + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF86B80 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF86B84 + +#define mmTPC6_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF86B88 + +#define mmTPC6_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF86B8C + +#define mmTPC6_CFG_QM_TENSOR_7_PADDING_VALUE 0xF86B90 + +#define mmTPC6_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF86B94 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF86B98 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF86B9C + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF86BA0 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF86BA4 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF86BA8 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF86BAC + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF86BB0 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF86BB4 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF86BB8 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF86BBC + +#define mmTPC6_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xF86BC0 + +#define mmTPC6_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xF86BC4 + +#define mmTPC6_CFG_QM_TENSOR_8_PADDING_VALUE 0xF86BC8 + +#define mmTPC6_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xF86BCC + +#define mmTPC6_CFG_QM_TENSOR_8_DIM_0_SIZE 0xF86BD0 + +#define mmTPC6_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xF86BD4 + +#define mmTPC6_CFG_QM_TENSOR_8_DIM_1_SIZE 0xF86BD8 + +#define mmTPC6_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xF86BDC + +#define mmTPC6_CFG_QM_TENSOR_8_DIM_2_SIZE 0xF86BE0 + +#define mmTPC6_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xF86BE4 + +#define mmTPC6_CFG_QM_TENSOR_8_DIM_3_SIZE 0xF86BE8 + +#define mmTPC6_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xF86BEC + +#define mmTPC6_CFG_QM_TENSOR_8_DIM_4_SIZE 0xF86BF0 + +#define mmTPC6_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xF86BF4 + +#define mmTPC6_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xF86BF8 + +#define mmTPC6_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xF86BFC + +#define mmTPC6_CFG_QM_TENSOR_9_PADDING_VALUE 0xF86C00 + +#define mmTPC6_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xF86C04 + +#define mmTPC6_CFG_QM_TENSOR_9_DIM_0_SIZE 0xF86C08 + +#define mmTPC6_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xF86C0C + +#define mmTPC6_CFG_QM_TENSOR_9_DIM_1_SIZE 0xF86C10 + +#define mmTPC6_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xF86C14 + +#define mmTPC6_CFG_QM_TENSOR_9_DIM_2_SIZE 0xF86C18 + +#define mmTPC6_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xF86C1C + +#define mmTPC6_CFG_QM_TENSOR_9_DIM_3_SIZE 0xF86C20 + +#define mmTPC6_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xF86C24 + +#define mmTPC6_CFG_QM_TENSOR_9_DIM_4_SIZE 0xF86C28 + +#define mmTPC6_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xF86C2C + +#define mmTPC6_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xF86C30 + +#define mmTPC6_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xF86C34 + +#define mmTPC6_CFG_QM_TENSOR_10_PADDING_VALUE 0xF86C38 + +#define mmTPC6_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xF86C3C + +#define mmTPC6_CFG_QM_TENSOR_10_DIM_0_SIZE 0xF86C40 + +#define mmTPC6_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xF86C44 + +#define mmTPC6_CFG_QM_TENSOR_10_DIM_1_SIZE 0xF86C48 + +#define mmTPC6_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xF86C4C + +#define mmTPC6_CFG_QM_TENSOR_10_DIM_2_SIZE 0xF86C50 + +#define mmTPC6_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xF86C54 + +#define mmTPC6_CFG_QM_TENSOR_10_DIM_3_SIZE 0xF86C58 + +#define mmTPC6_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xF86C5C + +#define mmTPC6_CFG_QM_TENSOR_10_DIM_4_SIZE 0xF86C60 + +#define mmTPC6_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xF86C64 + +#define mmTPC6_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xF86C68 + +#define mmTPC6_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xF86C6C + +#define mmTPC6_CFG_QM_TENSOR_11_PADDING_VALUE 0xF86C70 + +#define mmTPC6_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xF86C74 + +#define mmTPC6_CFG_QM_TENSOR_11_DIM_0_SIZE 0xF86C78 + +#define mmTPC6_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xF86C7C + +#define mmTPC6_CFG_QM_TENSOR_11_DIM_1_SIZE 0xF86C80 + +#define mmTPC6_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xF86C84 + +#define mmTPC6_CFG_QM_TENSOR_11_DIM_2_SIZE 0xF86C88 + +#define mmTPC6_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xF86C8C + +#define mmTPC6_CFG_QM_TENSOR_11_DIM_3_SIZE 0xF86C90 + +#define mmTPC6_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xF86C94 + +#define mmTPC6_CFG_QM_TENSOR_11_DIM_4_SIZE 0xF86C98 + +#define mmTPC6_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xF86C9C + +#define mmTPC6_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xF86CA0 + +#define mmTPC6_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xF86CA4 + +#define mmTPC6_CFG_QM_TENSOR_12_PADDING_VALUE 0xF86CA8 + +#define mmTPC6_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xF86CAC + +#define mmTPC6_CFG_QM_TENSOR_12_DIM_0_SIZE 0xF86CB0 + +#define mmTPC6_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xF86CB4 + +#define mmTPC6_CFG_QM_TENSOR_12_DIM_1_SIZE 0xF86CB8 + +#define mmTPC6_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xF86CBC + +#define mmTPC6_CFG_QM_TENSOR_12_DIM_2_SIZE 0xF86CC0 + +#define mmTPC6_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xF86CC4 + +#define mmTPC6_CFG_QM_TENSOR_12_DIM_3_SIZE 0xF86CC8 + +#define mmTPC6_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xF86CCC + +#define mmTPC6_CFG_QM_TENSOR_12_DIM_4_SIZE 0xF86CD0 + +#define mmTPC6_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xF86CD4 + +#define mmTPC6_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xF86CD8 + +#define mmTPC6_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xF86CDC + +#define mmTPC6_CFG_QM_TENSOR_13_PADDING_VALUE 0xF86CE0 + +#define mmTPC6_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xF86CE4 + +#define mmTPC6_CFG_QM_TENSOR_13_DIM_0_SIZE 0xF86CE8 + +#define mmTPC6_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xF86CEC + +#define mmTPC6_CFG_QM_TENSOR_13_DIM_1_SIZE 0xF86CF0 + +#define mmTPC6_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xF86CF4 + +#define mmTPC6_CFG_QM_TENSOR_13_DIM_2_SIZE 0xF86CF8 + +#define mmTPC6_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xF86CFC + +#define mmTPC6_CFG_QM_TENSOR_13_DIM_3_SIZE 0xF86D00 + +#define mmTPC6_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xF86D04 + +#define mmTPC6_CFG_QM_TENSOR_13_DIM_4_SIZE 0xF86D08 + +#define mmTPC6_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xF86D0C + +#define mmTPC6_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xF86D10 + +#define mmTPC6_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xF86D14 + +#define mmTPC6_CFG_QM_TENSOR_14_PADDING_VALUE 0xF86D18 + +#define mmTPC6_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xF86D1C + +#define mmTPC6_CFG_QM_TENSOR_14_DIM_0_SIZE 0xF86D20 + +#define mmTPC6_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xF86D24 + +#define mmTPC6_CFG_QM_TENSOR_14_DIM_1_SIZE 0xF86D28 + +#define mmTPC6_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xF86D2C + +#define mmTPC6_CFG_QM_TENSOR_14_DIM_2_SIZE 0xF86D30 + +#define mmTPC6_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xF86D34 + +#define mmTPC6_CFG_QM_TENSOR_14_DIM_3_SIZE 0xF86D38 + +#define mmTPC6_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xF86D3C + +#define mmTPC6_CFG_QM_TENSOR_14_DIM_4_SIZE 0xF86D40 + +#define mmTPC6_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xF86D44 + +#define mmTPC6_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xF86D48 + +#define mmTPC6_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xF86D4C + +#define mmTPC6_CFG_QM_TENSOR_15_PADDING_VALUE 0xF86D50 + +#define mmTPC6_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xF86D54 + +#define mmTPC6_CFG_QM_TENSOR_15_DIM_0_SIZE 0xF86D58 + +#define mmTPC6_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xF86D5C + +#define mmTPC6_CFG_QM_TENSOR_15_DIM_1_SIZE 0xF86D60 + +#define mmTPC6_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xF86D64 + +#define mmTPC6_CFG_QM_TENSOR_15_DIM_2_SIZE 0xF86D68 + +#define mmTPC6_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xF86D6C + +#define mmTPC6_CFG_QM_TENSOR_15_DIM_3_SIZE 0xF86D70 + +#define mmTPC6_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xF86D74 + +#define mmTPC6_CFG_QM_TENSOR_15_DIM_4_SIZE 0xF86D78 + +#define mmTPC6_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xF86D7C + +#define mmTPC6_CFG_QM_SYNC_OBJECT_MESSAGE 0xF86D80 + +#define mmTPC6_CFG_QM_SYNC_OBJECT_ADDR 0xF86D84 + +#define mmTPC6_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF86D88 + +#define mmTPC6_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF86D8C + +#define mmTPC6_CFG_QM_TID_BASE_DIM_0 0xF86D90 + +#define mmTPC6_CFG_QM_TID_SIZE_DIM_0 0xF86D94 + +#define mmTPC6_CFG_QM_TID_BASE_DIM_1 0xF86D98 + +#define mmTPC6_CFG_QM_TID_SIZE_DIM_1 0xF86D9C + +#define mmTPC6_CFG_QM_TID_BASE_DIM_2 0xF86DA0 + +#define mmTPC6_CFG_QM_TID_SIZE_DIM_2 0xF86DA4 + +#define mmTPC6_CFG_QM_TID_BASE_DIM_3 0xF86DA8 + +#define mmTPC6_CFG_QM_TID_SIZE_DIM_3 0xF86DAC + +#define mmTPC6_CFG_QM_TID_BASE_DIM_4 0xF86DB0 + +#define mmTPC6_CFG_QM_TID_SIZE_DIM_4 0xF86DB4 + +#define mmTPC6_CFG_QM_KERNEL_CONFIG 0xF86DB8 + +#define mmTPC6_CFG_QM_KERNEL_ID 0xF86DBC + +#define mmTPC6_CFG_QM_SRF_0 0xF86DC0 + +#define mmTPC6_CFG_QM_SRF_1 0xF86DC4 + +#define mmTPC6_CFG_QM_SRF_2 0xF86DC8 + +#define mmTPC6_CFG_QM_SRF_3 0xF86DCC + +#define mmTPC6_CFG_QM_SRF_4 0xF86DD0 + +#define mmTPC6_CFG_QM_SRF_5 0xF86DD4 + +#define mmTPC6_CFG_QM_SRF_6 0xF86DD8 + +#define mmTPC6_CFG_QM_SRF_7 0xF86DDC + +#define mmTPC6_CFG_QM_SRF_8 0xF86DE0 + +#define mmTPC6_CFG_QM_SRF_9 0xF86DE4 + +#define mmTPC6_CFG_QM_SRF_10 0xF86DE8 + +#define mmTPC6_CFG_QM_SRF_11 0xF86DEC + +#define mmTPC6_CFG_QM_SRF_12 0xF86DF0 + +#define mmTPC6_CFG_QM_SRF_13 0xF86DF4 + +#define mmTPC6_CFG_QM_SRF_14 0xF86DF8 + +#define mmTPC6_CFG_QM_SRF_15 0xF86DFC + +#define mmTPC6_CFG_QM_SRF_16 0xF86E00 + +#define mmTPC6_CFG_QM_SRF_17 0xF86E04 + +#define mmTPC6_CFG_QM_SRF_18 0xF86E08 + +#define mmTPC6_CFG_QM_SRF_19 0xF86E0C + +#define mmTPC6_CFG_QM_SRF_20 0xF86E10 + +#define mmTPC6_CFG_QM_SRF_21 0xF86E14 + +#define mmTPC6_CFG_QM_SRF_22 0xF86E18 + +#define mmTPC6_CFG_QM_SRF_23 0xF86E1C + +#define mmTPC6_CFG_QM_SRF_24 0xF86E20 + +#define mmTPC6_CFG_QM_SRF_25 0xF86E24 + +#define mmTPC6_CFG_QM_SRF_26 0xF86E28 + +#define mmTPC6_CFG_QM_SRF_27 0xF86E2C + +#define mmTPC6_CFG_QM_SRF_28 0xF86E30 + +#define mmTPC6_CFG_QM_SRF_29 0xF86E34 + +#define mmTPC6_CFG_QM_SRF_30 0xF86E38 + +#define mmTPC6_CFG_QM_SRF_31 0xF86E3C + +#endif /* ASIC_REG_TPC6_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc6_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc6_qm_regs.h new file mode 100644 index 000000000000..e35ef7fd8b1c --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc6_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC6_QM_REGS_H_ +#define ASIC_REG_TPC6_QM_REGS_H_ + +/* + ***************************************** + * TPC6_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC6_QM_GLBL_CFG0 0xF88000 + +#define mmTPC6_QM_GLBL_CFG1 0xF88004 + +#define mmTPC6_QM_GLBL_PROT 0xF88008 + +#define mmTPC6_QM_GLBL_ERR_CFG 0xF8800C + +#define mmTPC6_QM_GLBL_SECURE_PROPS_0 0xF88010 + +#define mmTPC6_QM_GLBL_SECURE_PROPS_1 0xF88014 + +#define mmTPC6_QM_GLBL_SECURE_PROPS_2 0xF88018 + +#define mmTPC6_QM_GLBL_SECURE_PROPS_3 0xF8801C + +#define mmTPC6_QM_GLBL_SECURE_PROPS_4 0xF88020 + +#define mmTPC6_QM_GLBL_NON_SECURE_PROPS_0 0xF88024 + +#define mmTPC6_QM_GLBL_NON_SECURE_PROPS_1 0xF88028 + +#define mmTPC6_QM_GLBL_NON_SECURE_PROPS_2 0xF8802C + +#define mmTPC6_QM_GLBL_NON_SECURE_PROPS_3 0xF88030 + +#define mmTPC6_QM_GLBL_NON_SECURE_PROPS_4 0xF88034 + +#define mmTPC6_QM_GLBL_STS0 0xF88038 + +#define mmTPC6_QM_GLBL_STS1_0 0xF88040 + +#define mmTPC6_QM_GLBL_STS1_1 0xF88044 + +#define mmTPC6_QM_GLBL_STS1_2 0xF88048 + +#define mmTPC6_QM_GLBL_STS1_3 0xF8804C + +#define mmTPC6_QM_GLBL_STS1_4 0xF88050 + +#define mmTPC6_QM_GLBL_MSG_EN_0 0xF88054 + +#define mmTPC6_QM_GLBL_MSG_EN_1 0xF88058 + +#define mmTPC6_QM_GLBL_MSG_EN_2 0xF8805C + +#define mmTPC6_QM_GLBL_MSG_EN_3 0xF88060 + +#define mmTPC6_QM_GLBL_MSG_EN_4 0xF88068 + +#define mmTPC6_QM_PQ_BASE_LO_0 0xF88070 + +#define mmTPC6_QM_PQ_BASE_LO_1 0xF88074 + +#define mmTPC6_QM_PQ_BASE_LO_2 0xF88078 + +#define mmTPC6_QM_PQ_BASE_LO_3 0xF8807C + +#define mmTPC6_QM_PQ_BASE_HI_0 0xF88080 + +#define mmTPC6_QM_PQ_BASE_HI_1 0xF88084 + +#define mmTPC6_QM_PQ_BASE_HI_2 0xF88088 + +#define mmTPC6_QM_PQ_BASE_HI_3 0xF8808C + +#define mmTPC6_QM_PQ_SIZE_0 0xF88090 + +#define mmTPC6_QM_PQ_SIZE_1 0xF88094 + +#define mmTPC6_QM_PQ_SIZE_2 0xF88098 + +#define mmTPC6_QM_PQ_SIZE_3 0xF8809C + +#define mmTPC6_QM_PQ_PI_0 0xF880A0 + +#define mmTPC6_QM_PQ_PI_1 0xF880A4 + +#define mmTPC6_QM_PQ_PI_2 0xF880A8 + +#define mmTPC6_QM_PQ_PI_3 0xF880AC + +#define mmTPC6_QM_PQ_CI_0 0xF880B0 + +#define mmTPC6_QM_PQ_CI_1 0xF880B4 + +#define mmTPC6_QM_PQ_CI_2 0xF880B8 + +#define mmTPC6_QM_PQ_CI_3 0xF880BC + +#define mmTPC6_QM_PQ_CFG0_0 0xF880C0 + +#define mmTPC6_QM_PQ_CFG0_1 0xF880C4 + +#define mmTPC6_QM_PQ_CFG0_2 0xF880C8 + +#define mmTPC6_QM_PQ_CFG0_3 0xF880CC + +#define mmTPC6_QM_PQ_CFG1_0 0xF880D0 + +#define mmTPC6_QM_PQ_CFG1_1 0xF880D4 + +#define mmTPC6_QM_PQ_CFG1_2 0xF880D8 + +#define mmTPC6_QM_PQ_CFG1_3 0xF880DC + +#define mmTPC6_QM_PQ_ARUSER_31_11_0 0xF880E0 + +#define mmTPC6_QM_PQ_ARUSER_31_11_1 0xF880E4 + +#define mmTPC6_QM_PQ_ARUSER_31_11_2 0xF880E8 + +#define mmTPC6_QM_PQ_ARUSER_31_11_3 0xF880EC + +#define mmTPC6_QM_PQ_STS0_0 0xF880F0 + +#define mmTPC6_QM_PQ_STS0_1 0xF880F4 + +#define mmTPC6_QM_PQ_STS0_2 0xF880F8 + +#define mmTPC6_QM_PQ_STS0_3 0xF880FC + +#define mmTPC6_QM_PQ_STS1_0 0xF88100 + +#define mmTPC6_QM_PQ_STS1_1 0xF88104 + +#define mmTPC6_QM_PQ_STS1_2 0xF88108 + +#define mmTPC6_QM_PQ_STS1_3 0xF8810C + +#define mmTPC6_QM_CQ_CFG0_0 0xF88110 + +#define mmTPC6_QM_CQ_CFG0_1 0xF88114 + +#define mmTPC6_QM_CQ_CFG0_2 0xF88118 + +#define mmTPC6_QM_CQ_CFG0_3 0xF8811C + +#define mmTPC6_QM_CQ_CFG0_4 0xF88120 + +#define mmTPC6_QM_CQ_CFG1_0 0xF88124 + +#define mmTPC6_QM_CQ_CFG1_1 0xF88128 + +#define mmTPC6_QM_CQ_CFG1_2 0xF8812C + +#define mmTPC6_QM_CQ_CFG1_3 0xF88130 + +#define mmTPC6_QM_CQ_CFG1_4 0xF88134 + +#define mmTPC6_QM_CQ_ARUSER_31_11_0 0xF88138 + +#define mmTPC6_QM_CQ_ARUSER_31_11_1 0xF8813C + +#define mmTPC6_QM_CQ_ARUSER_31_11_2 0xF88140 + +#define mmTPC6_QM_CQ_ARUSER_31_11_3 0xF88144 + +#define mmTPC6_QM_CQ_ARUSER_31_11_4 0xF88148 + +#define mmTPC6_QM_CQ_STS0_0 0xF8814C + +#define mmTPC6_QM_CQ_STS0_1 0xF88150 + +#define mmTPC6_QM_CQ_STS0_2 0xF88154 + +#define mmTPC6_QM_CQ_STS0_3 0xF88158 + +#define mmTPC6_QM_CQ_STS0_4 0xF8815C + +#define mmTPC6_QM_CQ_STS1_0 0xF88160 + +#define mmTPC6_QM_CQ_STS1_1 0xF88164 + +#define mmTPC6_QM_CQ_STS1_2 0xF88168 + +#define mmTPC6_QM_CQ_STS1_3 0xF8816C + +#define mmTPC6_QM_CQ_STS1_4 0xF88170 + +#define mmTPC6_QM_CQ_PTR_LO_0 0xF88174 + +#define mmTPC6_QM_CQ_PTR_HI_0 0xF88178 + +#define mmTPC6_QM_CQ_TSIZE_0 0xF8817C + +#define mmTPC6_QM_CQ_CTL_0 0xF88180 + +#define mmTPC6_QM_CQ_PTR_LO_1 0xF88184 + +#define mmTPC6_QM_CQ_PTR_HI_1 0xF88188 + +#define mmTPC6_QM_CQ_TSIZE_1 0xF8818C + +#define mmTPC6_QM_CQ_CTL_1 0xF88190 + +#define mmTPC6_QM_CQ_PTR_LO_2 0xF88194 + +#define mmTPC6_QM_CQ_PTR_HI_2 0xF88198 + +#define mmTPC6_QM_CQ_TSIZE_2 0xF8819C + +#define mmTPC6_QM_CQ_CTL_2 0xF881A0 + +#define mmTPC6_QM_CQ_PTR_LO_3 0xF881A4 + +#define mmTPC6_QM_CQ_PTR_HI_3 0xF881A8 + +#define mmTPC6_QM_CQ_TSIZE_3 0xF881AC + +#define mmTPC6_QM_CQ_CTL_3 0xF881B0 + +#define mmTPC6_QM_CQ_PTR_LO_4 0xF881B4 + +#define mmTPC6_QM_CQ_PTR_HI_4 0xF881B8 + +#define mmTPC6_QM_CQ_TSIZE_4 0xF881BC + +#define mmTPC6_QM_CQ_CTL_4 0xF881C0 + +#define mmTPC6_QM_CQ_PTR_LO_STS_0 0xF881C4 + +#define mmTPC6_QM_CQ_PTR_LO_STS_1 0xF881C8 + +#define mmTPC6_QM_CQ_PTR_LO_STS_2 0xF881CC + +#define mmTPC6_QM_CQ_PTR_LO_STS_3 0xF881D0 + +#define mmTPC6_QM_CQ_PTR_LO_STS_4 0xF881D4 + +#define mmTPC6_QM_CQ_PTR_HI_STS_0 0xF881D8 + +#define mmTPC6_QM_CQ_PTR_HI_STS_1 0xF881DC + +#define mmTPC6_QM_CQ_PTR_HI_STS_2 0xF881E0 + +#define mmTPC6_QM_CQ_PTR_HI_STS_3 0xF881E4 + +#define mmTPC6_QM_CQ_PTR_HI_STS_4 0xF881E8 + +#define mmTPC6_QM_CQ_TSIZE_STS_0 0xF881EC + +#define mmTPC6_QM_CQ_TSIZE_STS_1 0xF881F0 + +#define mmTPC6_QM_CQ_TSIZE_STS_2 0xF881F4 + +#define mmTPC6_QM_CQ_TSIZE_STS_3 0xF881F8 + +#define mmTPC6_QM_CQ_TSIZE_STS_4 0xF881FC + +#define mmTPC6_QM_CQ_CTL_STS_0 0xF88200 + +#define mmTPC6_QM_CQ_CTL_STS_1 0xF88204 + +#define mmTPC6_QM_CQ_CTL_STS_2 0xF88208 + +#define mmTPC6_QM_CQ_CTL_STS_3 0xF8820C + +#define mmTPC6_QM_CQ_CTL_STS_4 0xF88210 + +#define mmTPC6_QM_CQ_IFIFO_CNT_0 0xF88214 + +#define mmTPC6_QM_CQ_IFIFO_CNT_1 0xF88218 + +#define mmTPC6_QM_CQ_IFIFO_CNT_2 0xF8821C + +#define mmTPC6_QM_CQ_IFIFO_CNT_3 0xF88220 + +#define mmTPC6_QM_CQ_IFIFO_CNT_4 0xF88224 + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_0 0xF88228 + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_1 0xF8822C + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_2 0xF88230 + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_3 0xF88234 + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_4 0xF88238 + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_0 0xF8823C + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_1 0xF88240 + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_2 0xF88244 + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_3 0xF88248 + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_4 0xF8824C + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_0 0xF88250 + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_1 0xF88254 + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_2 0xF88258 + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_3 0xF8825C + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_4 0xF88260 + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_0 0xF88264 + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_1 0xF88268 + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_2 0xF8826C + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_3 0xF88270 + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_4 0xF88274 + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_0 0xF88278 + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_1 0xF8827C + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_2 0xF88280 + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_3 0xF88284 + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_4 0xF88288 + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_0 0xF8828C + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_1 0xF88290 + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_2 0xF88294 + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_3 0xF88298 + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_4 0xF8829C + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_0 0xF882A0 + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_1 0xF882A4 + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_2 0xF882A8 + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_3 0xF882AC + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_4 0xF882B0 + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_0 0xF882B4 + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_1 0xF882B8 + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_2 0xF882BC + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_3 0xF882C0 + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_4 0xF882C4 + +#define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_0 0xF882C8 + +#define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_1 0xF882CC + +#define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_2 0xF882D0 + +#define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_3 0xF882D4 + +#define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_4 0xF882D8 + +#define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xF882E0 + +#define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xF882E4 + +#define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xF882E8 + +#define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xF882EC + +#define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xF882F0 + +#define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xF882F4 + +#define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xF882F8 + +#define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xF882FC + +#define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xF88300 + +#define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xF88304 + +#define mmTPC6_QM_CP_FENCE0_RDATA_0 0xF88308 + +#define mmTPC6_QM_CP_FENCE0_RDATA_1 0xF8830C + +#define mmTPC6_QM_CP_FENCE0_RDATA_2 0xF88310 + +#define mmTPC6_QM_CP_FENCE0_RDATA_3 0xF88314 + +#define mmTPC6_QM_CP_FENCE0_RDATA_4 0xF88318 + +#define mmTPC6_QM_CP_FENCE1_RDATA_0 0xF8831C + +#define mmTPC6_QM_CP_FENCE1_RDATA_1 0xF88320 + +#define mmTPC6_QM_CP_FENCE1_RDATA_2 0xF88324 + +#define mmTPC6_QM_CP_FENCE1_RDATA_3 0xF88328 + +#define mmTPC6_QM_CP_FENCE1_RDATA_4 0xF8832C + +#define mmTPC6_QM_CP_FENCE2_RDATA_0 0xF88330 + +#define mmTPC6_QM_CP_FENCE2_RDATA_1 0xF88334 + +#define mmTPC6_QM_CP_FENCE2_RDATA_2 0xF88338 + +#define mmTPC6_QM_CP_FENCE2_RDATA_3 0xF8833C + +#define mmTPC6_QM_CP_FENCE2_RDATA_4 0xF88340 + +#define mmTPC6_QM_CP_FENCE3_RDATA_0 0xF88344 + +#define mmTPC6_QM_CP_FENCE3_RDATA_1 0xF88348 + +#define mmTPC6_QM_CP_FENCE3_RDATA_2 0xF8834C + +#define mmTPC6_QM_CP_FENCE3_RDATA_3 0xF88350 + +#define mmTPC6_QM_CP_FENCE3_RDATA_4 0xF88354 + +#define mmTPC6_QM_CP_FENCE0_CNT_0 0xF88358 + +#define mmTPC6_QM_CP_FENCE0_CNT_1 0xF8835C + +#define mmTPC6_QM_CP_FENCE0_CNT_2 0xF88360 + +#define mmTPC6_QM_CP_FENCE0_CNT_3 0xF88364 + +#define mmTPC6_QM_CP_FENCE0_CNT_4 0xF88368 + +#define mmTPC6_QM_CP_FENCE1_CNT_0 0xF8836C + +#define mmTPC6_QM_CP_FENCE1_CNT_1 0xF88370 + +#define mmTPC6_QM_CP_FENCE1_CNT_2 0xF88374 + +#define mmTPC6_QM_CP_FENCE1_CNT_3 0xF88378 + +#define mmTPC6_QM_CP_FENCE1_CNT_4 0xF8837C + +#define mmTPC6_QM_CP_FENCE2_CNT_0 0xF88380 + +#define mmTPC6_QM_CP_FENCE2_CNT_1 0xF88384 + +#define mmTPC6_QM_CP_FENCE2_CNT_2 0xF88388 + +#define mmTPC6_QM_CP_FENCE2_CNT_3 0xF8838C + +#define mmTPC6_QM_CP_FENCE2_CNT_4 0xF88390 + +#define mmTPC6_QM_CP_FENCE3_CNT_0 0xF88394 + +#define mmTPC6_QM_CP_FENCE3_CNT_1 0xF88398 + +#define mmTPC6_QM_CP_FENCE3_CNT_2 0xF8839C + +#define mmTPC6_QM_CP_FENCE3_CNT_3 0xF883A0 + +#define mmTPC6_QM_CP_FENCE3_CNT_4 0xF883A4 + +#define mmTPC6_QM_CP_STS_0 0xF883A8 + +#define mmTPC6_QM_CP_STS_1 0xF883AC + +#define mmTPC6_QM_CP_STS_2 0xF883B0 + +#define mmTPC6_QM_CP_STS_3 0xF883B4 + +#define mmTPC6_QM_CP_STS_4 0xF883B8 + +#define mmTPC6_QM_CP_CURRENT_INST_LO_0 0xF883BC + +#define mmTPC6_QM_CP_CURRENT_INST_LO_1 0xF883C0 + +#define mmTPC6_QM_CP_CURRENT_INST_LO_2 0xF883C4 + +#define mmTPC6_QM_CP_CURRENT_INST_LO_3 0xF883C8 + +#define mmTPC6_QM_CP_CURRENT_INST_LO_4 0xF883CC + +#define mmTPC6_QM_CP_CURRENT_INST_HI_0 0xF883D0 + +#define mmTPC6_QM_CP_CURRENT_INST_HI_1 0xF883D4 + +#define mmTPC6_QM_CP_CURRENT_INST_HI_2 0xF883D8 + +#define mmTPC6_QM_CP_CURRENT_INST_HI_3 0xF883DC + +#define mmTPC6_QM_CP_CURRENT_INST_HI_4 0xF883E0 + +#define mmTPC6_QM_CP_BARRIER_CFG_0 0xF883F4 + +#define mmTPC6_QM_CP_BARRIER_CFG_1 0xF883F8 + +#define mmTPC6_QM_CP_BARRIER_CFG_2 0xF883FC + +#define mmTPC6_QM_CP_BARRIER_CFG_3 0xF88400 + +#define mmTPC6_QM_CP_BARRIER_CFG_4 0xF88404 + +#define mmTPC6_QM_CP_DBG_0_0 0xF88408 + +#define mmTPC6_QM_CP_DBG_0_1 0xF8840C + +#define mmTPC6_QM_CP_DBG_0_2 0xF88410 + +#define mmTPC6_QM_CP_DBG_0_3 0xF88414 + +#define mmTPC6_QM_CP_DBG_0_4 0xF88418 + +#define mmTPC6_QM_CP_ARUSER_31_11_0 0xF8841C + +#define mmTPC6_QM_CP_ARUSER_31_11_1 0xF88420 + +#define mmTPC6_QM_CP_ARUSER_31_11_2 0xF88424 + +#define mmTPC6_QM_CP_ARUSER_31_11_3 0xF88428 + +#define mmTPC6_QM_CP_ARUSER_31_11_4 0xF8842C + +#define mmTPC6_QM_CP_AWUSER_31_11_0 0xF88430 + +#define mmTPC6_QM_CP_AWUSER_31_11_1 0xF88434 + +#define mmTPC6_QM_CP_AWUSER_31_11_2 0xF88438 + +#define mmTPC6_QM_CP_AWUSER_31_11_3 0xF8843C + +#define mmTPC6_QM_CP_AWUSER_31_11_4 0xF88440 + +#define mmTPC6_QM_ARB_CFG_0 0xF88A00 + +#define mmTPC6_QM_ARB_CHOISE_Q_PUSH 0xF88A04 + +#define mmTPC6_QM_ARB_WRR_WEIGHT_0 0xF88A08 + +#define mmTPC6_QM_ARB_WRR_WEIGHT_1 0xF88A0C + +#define mmTPC6_QM_ARB_WRR_WEIGHT_2 0xF88A10 + +#define mmTPC6_QM_ARB_WRR_WEIGHT_3 0xF88A14 + +#define mmTPC6_QM_ARB_CFG_1 0xF88A18 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_0 0xF88A20 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_1 0xF88A24 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_2 0xF88A28 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_3 0xF88A2C + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_4 0xF88A30 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_5 0xF88A34 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_6 0xF88A38 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_7 0xF88A3C + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_8 0xF88A40 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_9 0xF88A44 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_10 0xF88A48 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_11 0xF88A4C + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_12 0xF88A50 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_13 0xF88A54 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_14 0xF88A58 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_15 0xF88A5C + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_16 0xF88A60 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_17 0xF88A64 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_18 0xF88A68 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_19 0xF88A6C + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_20 0xF88A70 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_21 0xF88A74 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_22 0xF88A78 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_23 0xF88A7C + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_24 0xF88A80 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_25 0xF88A84 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_26 0xF88A88 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_27 0xF88A8C + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_28 0xF88A90 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_29 0xF88A94 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_30 0xF88A98 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_31 0xF88A9C + +#define mmTPC6_QM_ARB_MST_CRED_INC 0xF88AA0 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xF88AA4 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xF88AA8 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xF88AAC + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xF88AB0 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xF88AB4 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xF88AB8 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xF88ABC + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xF88AC0 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xF88AC4 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xF88AC8 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xF88ACC + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xF88AD0 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xF88AD4 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xF88AD8 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xF88ADC + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xF88AE0 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xF88AE4 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xF88AE8 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xF88AEC + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xF88AF0 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xF88AF4 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xF88AF8 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xF88AFC + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xF88B00 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xF88B04 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xF88B08 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xF88B0C + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xF88B10 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xF88B14 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xF88B18 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xF88B1C + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xF88B20 + +#define mmTPC6_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xF88B28 + +#define mmTPC6_QM_ARB_MST_SLAVE_EN 0xF88B2C + +#define mmTPC6_QM_ARB_MST_QUIET_PER 0xF88B34 + +#define mmTPC6_QM_ARB_SLV_CHOISE_WDT 0xF88B38 + +#define mmTPC6_QM_ARB_SLV_ID 0xF88B3C + +#define mmTPC6_QM_ARB_MSG_MAX_INFLIGHT 0xF88B44 + +#define mmTPC6_QM_ARB_MSG_AWUSER_31_11 0xF88B48 + +#define mmTPC6_QM_ARB_MSG_AWUSER_SEC_PROP 0xF88B4C + +#define mmTPC6_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xF88B50 + +#define mmTPC6_QM_ARB_BASE_LO 0xF88B54 + +#define mmTPC6_QM_ARB_BASE_HI 0xF88B58 + +#define mmTPC6_QM_ARB_STATE_STS 0xF88B80 + +#define mmTPC6_QM_ARB_CHOISE_FULLNESS_STS 0xF88B84 + +#define mmTPC6_QM_ARB_MSG_STS 0xF88B88 + +#define mmTPC6_QM_ARB_SLV_CHOISE_Q_HEAD 0xF88B8C + +#define mmTPC6_QM_ARB_ERR_CAUSE 0xF88B9C + +#define mmTPC6_QM_ARB_ERR_MSG_EN 0xF88BA0 + +#define mmTPC6_QM_ARB_ERR_STS_DRP 0xF88BA8 + +#define mmTPC6_QM_ARB_MST_CRED_STS_0 0xF88BB0 + +#define mmTPC6_QM_ARB_MST_CRED_STS_1 0xF88BB4 + +#define mmTPC6_QM_ARB_MST_CRED_STS_2 0xF88BB8 + +#define mmTPC6_QM_ARB_MST_CRED_STS_3 0xF88BBC + +#define mmTPC6_QM_ARB_MST_CRED_STS_4 0xF88BC0 + +#define mmTPC6_QM_ARB_MST_CRED_STS_5 0xF88BC4 + +#define mmTPC6_QM_ARB_MST_CRED_STS_6 0xF88BC8 + +#define mmTPC6_QM_ARB_MST_CRED_STS_7 0xF88BCC + +#define mmTPC6_QM_ARB_MST_CRED_STS_8 0xF88BD0 + +#define mmTPC6_QM_ARB_MST_CRED_STS_9 0xF88BD4 + +#define mmTPC6_QM_ARB_MST_CRED_STS_10 0xF88BD8 + +#define mmTPC6_QM_ARB_MST_CRED_STS_11 0xF88BDC + +#define mmTPC6_QM_ARB_MST_CRED_STS_12 0xF88BE0 + +#define mmTPC6_QM_ARB_MST_CRED_STS_13 0xF88BE4 + +#define mmTPC6_QM_ARB_MST_CRED_STS_14 0xF88BE8 + +#define mmTPC6_QM_ARB_MST_CRED_STS_15 0xF88BEC + +#define mmTPC6_QM_ARB_MST_CRED_STS_16 0xF88BF0 + +#define mmTPC6_QM_ARB_MST_CRED_STS_17 0xF88BF4 + +#define mmTPC6_QM_ARB_MST_CRED_STS_18 0xF88BF8 + +#define mmTPC6_QM_ARB_MST_CRED_STS_19 0xF88BFC + +#define mmTPC6_QM_ARB_MST_CRED_STS_20 0xF88C00 + +#define mmTPC6_QM_ARB_MST_CRED_STS_21 0xF88C04 + +#define mmTPC6_QM_ARB_MST_CRED_STS_22 0xF88C08 + +#define mmTPC6_QM_ARB_MST_CRED_STS_23 0xF88C0C + +#define mmTPC6_QM_ARB_MST_CRED_STS_24 0xF88C10 + +#define mmTPC6_QM_ARB_MST_CRED_STS_25 0xF88C14 + +#define mmTPC6_QM_ARB_MST_CRED_STS_26 0xF88C18 + +#define mmTPC6_QM_ARB_MST_CRED_STS_27 0xF88C1C + +#define mmTPC6_QM_ARB_MST_CRED_STS_28 0xF88C20 + +#define mmTPC6_QM_ARB_MST_CRED_STS_29 0xF88C24 + +#define mmTPC6_QM_ARB_MST_CRED_STS_30 0xF88C28 + +#define mmTPC6_QM_ARB_MST_CRED_STS_31 0xF88C2C + +#define mmTPC6_QM_CGM_CFG 0xF88C70 + +#define mmTPC6_QM_CGM_STS 0xF88C74 + +#define mmTPC6_QM_CGM_CFG1 0xF88C78 + +#define mmTPC6_QM_LOCAL_RANGE_BASE 0xF88C80 + +#define mmTPC6_QM_LOCAL_RANGE_SIZE 0xF88C84 + +#define mmTPC6_QM_CSMR_STRICT_PRIO_CFG 0xF88C90 + +#define mmTPC6_QM_HBW_RD_RATE_LIM_CFG_1 0xF88C94 + +#define mmTPC6_QM_LBW_WR_RATE_LIM_CFG_0 0xF88C98 + +#define mmTPC6_QM_LBW_WR_RATE_LIM_CFG_1 0xF88C9C + +#define mmTPC6_QM_HBW_RD_RATE_LIM_CFG_0 0xF88CA0 + +#define mmTPC6_QM_GLBL_AXCACHE 0xF88CA4 + +#define mmTPC6_QM_IND_GW_APB_CFG 0xF88CB0 + +#define mmTPC6_QM_IND_GW_APB_WDATA 0xF88CB4 + +#define mmTPC6_QM_IND_GW_APB_RDATA 0xF88CB8 + +#define mmTPC6_QM_IND_GW_APB_STATUS 0xF88CBC + +#define mmTPC6_QM_GLBL_ERR_ADDR_LO 0xF88CD0 + +#define mmTPC6_QM_GLBL_ERR_ADDR_HI 0xF88CD4 + +#define mmTPC6_QM_GLBL_ERR_WDATA 0xF88CD8 + +#define mmTPC6_QM_GLBL_MEM_INIT_BUSY 0xF88D00 + +#endif /* ASIC_REG_TPC6_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc7_cfg_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc7_cfg_regs.h new file mode 100644 index 000000000000..1887b10e58e2 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc7_cfg_regs.h @@ -0,0 +1,1226 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC7_CFG_REGS_H_ +#define ASIC_REG_TPC7_CFG_REGS_H_ + +/* + ***************************************** + * TPC7_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC7_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xFC6400 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xFC6404 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xFC6408 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xFC640C + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xFC6410 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xFC6414 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xFC6418 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xFC641C + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xFC6420 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xFC6424 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xFC6428 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xFC642C + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xFC6430 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xFC6434 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xFC6438 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xFC643C + +#define mmTPC7_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xFC6440 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xFC6444 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xFC6448 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xFC644C + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xFC6450 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xFC6454 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xFC6458 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xFC645C + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xFC6460 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xFC6464 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xFC6468 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xFC646C + +#define mmTPC7_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xFC6470 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xFC6474 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xFC6478 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xFC647C + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xFC6480 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xFC6484 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xFC6488 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xFC648C + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xFC6490 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xFC6494 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xFC6498 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xFC649C + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xFC64A0 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xFC64A4 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xFC64A8 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xFC64AC + +#define mmTPC7_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xFC64B0 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xFC64B4 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xFC64B8 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xFC64BC + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xFC64C0 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xFC64C4 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xFC64C8 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xFC64CC + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xFC64D0 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xFC64D4 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xFC64D8 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xFC64DC + +#define mmTPC7_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xFC64E0 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xFC64E4 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xFC64E8 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xFC64EC + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xFC64F0 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xFC64F4 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xFC64F8 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xFC64FC + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xFC6500 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xFC6504 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xFC6508 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xFC650C + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xFC6510 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xFC6514 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xFC6518 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xFC651C + +#define mmTPC7_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xFC6520 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xFC6524 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xFC6528 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xFC652C + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xFC6530 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xFC6534 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xFC6538 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xFC653C + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xFC6540 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xFC6544 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xFC6548 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xFC654C + +#define mmTPC7_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xFC6550 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xFC6554 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xFC6558 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xFC655C + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xFC6560 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xFC6564 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xFC6568 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xFC656C + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xFC6570 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xFC6574 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xFC6578 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xFC657C + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xFC6580 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xFC6584 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xFC6588 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xFC658C + +#define mmTPC7_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xFC6590 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xFC6594 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xFC6598 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xFC659C + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xFC65A0 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xFC65A4 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xFC65A8 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xFC65AC + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xFC65B0 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xFC65B4 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xFC65B8 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xFC65BC + +#define mmTPC7_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xFC65C0 + +#define mmTPC7_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xFC65C4 + +#define mmTPC7_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xFC65C8 + +#define mmTPC7_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xFC65CC + +#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xFC65D0 + +#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xFC65D4 + +#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xFC65D8 + +#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xFC65DC + +#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xFC65E0 + +#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xFC65E4 + +#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xFC65E8 + +#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xFC65EC + +#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xFC65F0 + +#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xFC65F4 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xFC65F8 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xFC65FC + +#define mmTPC7_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xFC6600 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xFC6604 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xFC6608 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xFC660C + +#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xFC6610 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xFC6614 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xFC6618 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xFC661C + +#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xFC6620 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xFC6624 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xFC6628 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xFC662C + +#define mmTPC7_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xFC6630 + +#define mmTPC7_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xFC6634 + +#define mmTPC7_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xFC6638 + +#define mmTPC7_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xFC663C + +#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xFC6640 + +#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xFC6644 + +#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xFC6648 + +#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xFC664C + +#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xFC6650 + +#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xFC6654 + +#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xFC6658 + +#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xFC665C + +#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xFC6660 + +#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xFC6664 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xFC6668 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xFC666C + +#define mmTPC7_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xFC6670 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xFC6674 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xFC6678 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xFC667C + +#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xFC6680 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xFC6684 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xFC6688 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xFC668C + +#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xFC6690 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xFC6694 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xFC6698 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xFC669C + +#define mmTPC7_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xFC66A0 + +#define mmTPC7_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xFC66A4 + +#define mmTPC7_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xFC66A8 + +#define mmTPC7_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xFC66AC + +#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xFC66B0 + +#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xFC66B4 + +#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xFC66B8 + +#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xFC66BC + +#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xFC66C0 + +#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xFC66C4 + +#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xFC66C8 + +#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xFC66CC + +#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xFC66D0 + +#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xFC66D4 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xFC66D8 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xFC66DC + +#define mmTPC7_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xFC66E0 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xFC66E4 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xFC66E8 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xFC66EC + +#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xFC66F0 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xFC66F4 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xFC66F8 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xFC66FC + +#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xFC6700 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xFC6704 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xFC6708 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xFC670C + +#define mmTPC7_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xFC6710 + +#define mmTPC7_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xFC6714 + +#define mmTPC7_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xFC6718 + +#define mmTPC7_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xFC671C + +#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xFC6720 + +#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xFC6724 + +#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xFC6728 + +#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xFC672C + +#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xFC6730 + +#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xFC6734 + +#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xFC6738 + +#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xFC673C + +#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xFC6740 + +#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xFC6744 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xFC6748 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xFC674C + +#define mmTPC7_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xFC6750 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xFC6754 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xFC6758 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xFC675C + +#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xFC6760 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xFC6764 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xFC6768 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xFC676C + +#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xFC6770 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xFC6774 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xFC6778 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xFC677C + +#define mmTPC7_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xFC6780 + +#define mmTPC7_CFG_KERNEL_SYNC_OBJECT_ADDR 0xFC6784 + +#define mmTPC7_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xFC6788 + +#define mmTPC7_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xFC678C + +#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_0 0xFC6790 + +#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_0 0xFC6794 + +#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_1 0xFC6798 + +#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_1 0xFC679C + +#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_2 0xFC67A0 + +#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_2 0xFC67A4 + +#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_3 0xFC67A8 + +#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_3 0xFC67AC + +#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_4 0xFC67B0 + +#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_4 0xFC67B4 + +#define mmTPC7_CFG_KERNEL_KERNEL_CONFIG 0xFC67B8 + +#define mmTPC7_CFG_KERNEL_KERNEL_ID 0xFC67BC + +#define mmTPC7_CFG_KERNEL_SRF_0 0xFC67C0 + +#define mmTPC7_CFG_KERNEL_SRF_1 0xFC67C4 + +#define mmTPC7_CFG_KERNEL_SRF_2 0xFC67C8 + +#define mmTPC7_CFG_KERNEL_SRF_3 0xFC67CC + +#define mmTPC7_CFG_KERNEL_SRF_4 0xFC67D0 + +#define mmTPC7_CFG_KERNEL_SRF_5 0xFC67D4 + +#define mmTPC7_CFG_KERNEL_SRF_6 0xFC67D8 + +#define mmTPC7_CFG_KERNEL_SRF_7 0xFC67DC + +#define mmTPC7_CFG_KERNEL_SRF_8 0xFC67E0 + +#define mmTPC7_CFG_KERNEL_SRF_9 0xFC67E4 + +#define mmTPC7_CFG_KERNEL_SRF_10 0xFC67E8 + +#define mmTPC7_CFG_KERNEL_SRF_11 0xFC67EC + +#define mmTPC7_CFG_KERNEL_SRF_12 0xFC67F0 + +#define mmTPC7_CFG_KERNEL_SRF_13 0xFC67F4 + +#define mmTPC7_CFG_KERNEL_SRF_14 0xFC67F8 + +#define mmTPC7_CFG_KERNEL_SRF_15 0xFC67FC + +#define mmTPC7_CFG_KERNEL_SRF_16 0xFC6800 + +#define mmTPC7_CFG_KERNEL_SRF_17 0xFC6804 + +#define mmTPC7_CFG_KERNEL_SRF_18 0xFC6808 + +#define mmTPC7_CFG_KERNEL_SRF_19 0xFC680C + +#define mmTPC7_CFG_KERNEL_SRF_20 0xFC6810 + +#define mmTPC7_CFG_KERNEL_SRF_21 0xFC6814 + +#define mmTPC7_CFG_KERNEL_SRF_22 0xFC6818 + +#define mmTPC7_CFG_KERNEL_SRF_23 0xFC681C + +#define mmTPC7_CFG_KERNEL_SRF_24 0xFC6820 + +#define mmTPC7_CFG_KERNEL_SRF_25 0xFC6824 + +#define mmTPC7_CFG_KERNEL_SRF_26 0xFC6828 + +#define mmTPC7_CFG_KERNEL_SRF_27 0xFC682C + +#define mmTPC7_CFG_KERNEL_SRF_28 0xFC6830 + +#define mmTPC7_CFG_KERNEL_SRF_29 0xFC6834 + +#define mmTPC7_CFG_KERNEL_SRF_30 0xFC6838 + +#define mmTPC7_CFG_KERNEL_SRF_31 0xFC683C + +#define mmTPC7_CFG_ROUND_CSR 0xFC68FC + +#define mmTPC7_CFG_PROT 0xFC6900 + +#define mmTPC7_CFG_SEMAPHORE 0xFC6908 + +#define mmTPC7_CFG_VFLAGS 0xFC690C + +#define mmTPC7_CFG_SFLAGS 0xFC6910 + +#define mmTPC7_CFG_LFSR_POLYNOM 0xFC6918 + +#define mmTPC7_CFG_STATUS 0xFC691C + +#define mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH 0xFC6920 + +#define mmTPC7_CFG_CFG_SUBTRACT_VALUE 0xFC6924 + +#define mmTPC7_CFG_SM_BASE_ADDRESS_HIGH 0xFC692C + +#define mmTPC7_CFG_TPC_CMD 0xFC6930 + +#define mmTPC7_CFG_TPC_EXECUTE 0xFC6938 + +#define mmTPC7_CFG_TPC_STALL 0xFC693C + +#define mmTPC7_CFG_ICACHE_BASE_ADDERESS_LOW 0xFC6940 + +#define mmTPC7_CFG_ICACHE_BASE_ADDERESS_HIGH 0xFC6944 + +#define mmTPC7_CFG_RD_RATE_LIMIT 0xFC6948 + +#define mmTPC7_CFG_WR_RATE_LIMIT 0xFC6950 + +#define mmTPC7_CFG_MSS_CONFIG 0xFC6954 + +#define mmTPC7_CFG_TPC_INTR_CAUSE 0xFC6958 + +#define mmTPC7_CFG_TPC_INTR_MASK 0xFC695C + +#define mmTPC7_CFG_WQ_CREDITS 0xFC6960 + +#define mmTPC7_CFG_ARUSER_LO 0xFC6964 + +#define mmTPC7_CFG_ARUSER_HI 0xFC6968 + +#define mmTPC7_CFG_AWUSER_LO 0xFC696C + +#define mmTPC7_CFG_AWUSER_HI 0xFC6970 + +#define mmTPC7_CFG_OPCODE_EXEC 0xFC6974 + +#define mmTPC7_CFG_LUT_FUNC32_BASE_ADDR_LO 0xFC6978 + +#define mmTPC7_CFG_LUT_FUNC32_BASE_ADDR_HI 0xFC697C + +#define mmTPC7_CFG_LUT_FUNC64_BASE_ADDR_LO 0xFC6980 + +#define mmTPC7_CFG_LUT_FUNC64_BASE_ADDR_HI 0xFC6984 + +#define mmTPC7_CFG_LUT_FUNC128_BASE_ADDR_LO 0xFC6988 + +#define mmTPC7_CFG_LUT_FUNC128_BASE_ADDR_HI 0xFC698C + +#define mmTPC7_CFG_LUT_FUNC256_BASE_ADDR_LO 0xFC6990 + +#define mmTPC7_CFG_LUT_FUNC256_BASE_ADDR_HI 0xFC6994 + +#define mmTPC7_CFG_TSB_CFG_MAX_SIZE 0xFC6998 + +#define mmTPC7_CFG_TSB_CFG 0xFC699C + +#define mmTPC7_CFG_DBGMEM_ADD 0xFC69A0 + +#define mmTPC7_CFG_DBGMEM_DATA_WR 0xFC69A4 + +#define mmTPC7_CFG_DBGMEM_DATA_RD 0xFC69A8 + +#define mmTPC7_CFG_DBGMEM_CTRL 0xFC69AC + +#define mmTPC7_CFG_DBGMEM_RC 0xFC69B0 + +#define mmTPC7_CFG_TSB_INFLIGHT_CNTR 0xFC69B4 + +#define mmTPC7_CFG_WQ_INFLIGHT_CNTR 0xFC69B8 + +#define mmTPC7_CFG_WQ_LBW_TOTAL_CNTR 0xFC69BC + +#define mmTPC7_CFG_WQ_HBW_TOTAL_CNTR 0xFC69C0 + +#define mmTPC7_CFG_IRQ_OCCOUPY_CNTR 0xFC69C4 + +#define mmTPC7_CFG_FUNC_MBIST_CNTRL 0xFC69D0 + +#define mmTPC7_CFG_FUNC_MBIST_PAT 0xFC69D4 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_0 0xFC69D8 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_1 0xFC69DC + +#define mmTPC7_CFG_FUNC_MBIST_MEM_2 0xFC69E0 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_3 0xFC69E4 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_4 0xFC69E8 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_5 0xFC69EC + +#define mmTPC7_CFG_FUNC_MBIST_MEM_6 0xFC69F0 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_7 0xFC69F4 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_8 0xFC69F8 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_9 0xFC69FC + +#define mmTPC7_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xFC6A00 + +#define mmTPC7_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xFC6A04 + +#define mmTPC7_CFG_QM_TENSOR_0_PADDING_VALUE 0xFC6A08 + +#define mmTPC7_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xFC6A0C + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_0_SIZE 0xFC6A10 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xFC6A14 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_1_SIZE 0xFC6A18 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xFC6A1C + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_2_SIZE 0xFC6A20 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xFC6A24 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_3_SIZE 0xFC6A28 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xFC6A2C + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_4_SIZE 0xFC6A30 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xFC6A34 + +#define mmTPC7_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xFC6A38 + +#define mmTPC7_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xFC6A3C + +#define mmTPC7_CFG_QM_TENSOR_1_PADDING_VALUE 0xFC6A40 + +#define mmTPC7_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xFC6A44 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_0_SIZE 0xFC6A48 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xFC6A4C + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_1_SIZE 0xFC6A50 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xFC6A54 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_2_SIZE 0xFC6A58 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xFC6A5C + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_3_SIZE 0xFC6A60 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xFC6A64 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_4_SIZE 0xFC6A68 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xFC6A6C + +#define mmTPC7_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xFC6A70 + +#define mmTPC7_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xFC6A74 + +#define mmTPC7_CFG_QM_TENSOR_2_PADDING_VALUE 0xFC6A78 + +#define mmTPC7_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xFC6A7C + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_0_SIZE 0xFC6A80 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xFC6A84 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_1_SIZE 0xFC6A88 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xFC6A8C + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_2_SIZE 0xFC6A90 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xFC6A94 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_3_SIZE 0xFC6A98 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xFC6A9C + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_4_SIZE 0xFC6AA0 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xFC6AA4 + +#define mmTPC7_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xFC6AA8 + +#define mmTPC7_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xFC6AAC + +#define mmTPC7_CFG_QM_TENSOR_3_PADDING_VALUE 0xFC6AB0 + +#define mmTPC7_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xFC6AB4 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_0_SIZE 0xFC6AB8 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xFC6ABC + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_1_SIZE 0xFC6AC0 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xFC6AC4 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_2_SIZE 0xFC6AC8 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xFC6ACC + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_3_SIZE 0xFC6AD0 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xFC6AD4 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_4_SIZE 0xFC6AD8 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xFC6ADC + +#define mmTPC7_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xFC6AE0 + +#define mmTPC7_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xFC6AE4 + +#define mmTPC7_CFG_QM_TENSOR_4_PADDING_VALUE 0xFC6AE8 + +#define mmTPC7_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xFC6AEC + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_0_SIZE 0xFC6AF0 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xFC6AF4 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_1_SIZE 0xFC6AF8 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xFC6AFC + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_2_SIZE 0xFC6B00 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xFC6B04 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_3_SIZE 0xFC6B08 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xFC6B0C + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_4_SIZE 0xFC6B10 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xFC6B14 + +#define mmTPC7_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xFC6B18 + +#define mmTPC7_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xFC6B1C + +#define mmTPC7_CFG_QM_TENSOR_5_PADDING_VALUE 0xFC6B20 + +#define mmTPC7_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xFC6B24 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_0_SIZE 0xFC6B28 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xFC6B2C + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_1_SIZE 0xFC6B30 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xFC6B34 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_2_SIZE 0xFC6B38 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xFC6B3C + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_3_SIZE 0xFC6B40 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xFC6B44 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_4_SIZE 0xFC6B48 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xFC6B4C + +#define mmTPC7_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xFC6B50 + +#define mmTPC7_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xFC6B54 + +#define mmTPC7_CFG_QM_TENSOR_6_PADDING_VALUE 0xFC6B58 + +#define mmTPC7_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xFC6B5C + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_0_SIZE 0xFC6B60 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xFC6B64 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_1_SIZE 0xFC6B68 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xFC6B6C + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_2_SIZE 0xFC6B70 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xFC6B74 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_3_SIZE 0xFC6B78 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xFC6B7C + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_4_SIZE 0xFC6B80 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xFC6B84 + +#define mmTPC7_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xFC6B88 + +#define mmTPC7_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xFC6B8C + +#define mmTPC7_CFG_QM_TENSOR_7_PADDING_VALUE 0xFC6B90 + +#define mmTPC7_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xFC6B94 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_0_SIZE 0xFC6B98 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xFC6B9C + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_1_SIZE 0xFC6BA0 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xFC6BA4 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_2_SIZE 0xFC6BA8 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xFC6BAC + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_3_SIZE 0xFC6BB0 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xFC6BB4 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_4_SIZE 0xFC6BB8 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xFC6BBC + +#define mmTPC7_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xFC6BC0 + +#define mmTPC7_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xFC6BC4 + +#define mmTPC7_CFG_QM_TENSOR_8_PADDING_VALUE 0xFC6BC8 + +#define mmTPC7_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xFC6BCC + +#define mmTPC7_CFG_QM_TENSOR_8_DIM_0_SIZE 0xFC6BD0 + +#define mmTPC7_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xFC6BD4 + +#define mmTPC7_CFG_QM_TENSOR_8_DIM_1_SIZE 0xFC6BD8 + +#define mmTPC7_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xFC6BDC + +#define mmTPC7_CFG_QM_TENSOR_8_DIM_2_SIZE 0xFC6BE0 + +#define mmTPC7_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xFC6BE4 + +#define mmTPC7_CFG_QM_TENSOR_8_DIM_3_SIZE 0xFC6BE8 + +#define mmTPC7_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xFC6BEC + +#define mmTPC7_CFG_QM_TENSOR_8_DIM_4_SIZE 0xFC6BF0 + +#define mmTPC7_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xFC6BF4 + +#define mmTPC7_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xFC6BF8 + +#define mmTPC7_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xFC6BFC + +#define mmTPC7_CFG_QM_TENSOR_9_PADDING_VALUE 0xFC6C00 + +#define mmTPC7_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xFC6C04 + +#define mmTPC7_CFG_QM_TENSOR_9_DIM_0_SIZE 0xFC6C08 + +#define mmTPC7_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xFC6C0C + +#define mmTPC7_CFG_QM_TENSOR_9_DIM_1_SIZE 0xFC6C10 + +#define mmTPC7_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xFC6C14 + +#define mmTPC7_CFG_QM_TENSOR_9_DIM_2_SIZE 0xFC6C18 + +#define mmTPC7_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xFC6C1C + +#define mmTPC7_CFG_QM_TENSOR_9_DIM_3_SIZE 0xFC6C20 + +#define mmTPC7_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xFC6C24 + +#define mmTPC7_CFG_QM_TENSOR_9_DIM_4_SIZE 0xFC6C28 + +#define mmTPC7_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xFC6C2C + +#define mmTPC7_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xFC6C30 + +#define mmTPC7_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xFC6C34 + +#define mmTPC7_CFG_QM_TENSOR_10_PADDING_VALUE 0xFC6C38 + +#define mmTPC7_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xFC6C3C + +#define mmTPC7_CFG_QM_TENSOR_10_DIM_0_SIZE 0xFC6C40 + +#define mmTPC7_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xFC6C44 + +#define mmTPC7_CFG_QM_TENSOR_10_DIM_1_SIZE 0xFC6C48 + +#define mmTPC7_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xFC6C4C + +#define mmTPC7_CFG_QM_TENSOR_10_DIM_2_SIZE 0xFC6C50 + +#define mmTPC7_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xFC6C54 + +#define mmTPC7_CFG_QM_TENSOR_10_DIM_3_SIZE 0xFC6C58 + +#define mmTPC7_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xFC6C5C + +#define mmTPC7_CFG_QM_TENSOR_10_DIM_4_SIZE 0xFC6C60 + +#define mmTPC7_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xFC6C64 + +#define mmTPC7_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xFC6C68 + +#define mmTPC7_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xFC6C6C + +#define mmTPC7_CFG_QM_TENSOR_11_PADDING_VALUE 0xFC6C70 + +#define mmTPC7_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xFC6C74 + +#define mmTPC7_CFG_QM_TENSOR_11_DIM_0_SIZE 0xFC6C78 + +#define mmTPC7_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xFC6C7C + +#define mmTPC7_CFG_QM_TENSOR_11_DIM_1_SIZE 0xFC6C80 + +#define mmTPC7_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xFC6C84 + +#define mmTPC7_CFG_QM_TENSOR_11_DIM_2_SIZE 0xFC6C88 + +#define mmTPC7_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xFC6C8C + +#define mmTPC7_CFG_QM_TENSOR_11_DIM_3_SIZE 0xFC6C90 + +#define mmTPC7_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xFC6C94 + +#define mmTPC7_CFG_QM_TENSOR_11_DIM_4_SIZE 0xFC6C98 + +#define mmTPC7_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xFC6C9C + +#define mmTPC7_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xFC6CA0 + +#define mmTPC7_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xFC6CA4 + +#define mmTPC7_CFG_QM_TENSOR_12_PADDING_VALUE 0xFC6CA8 + +#define mmTPC7_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xFC6CAC + +#define mmTPC7_CFG_QM_TENSOR_12_DIM_0_SIZE 0xFC6CB0 + +#define mmTPC7_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xFC6CB4 + +#define mmTPC7_CFG_QM_TENSOR_12_DIM_1_SIZE 0xFC6CB8 + +#define mmTPC7_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xFC6CBC + +#define mmTPC7_CFG_QM_TENSOR_12_DIM_2_SIZE 0xFC6CC0 + +#define mmTPC7_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xFC6CC4 + +#define mmTPC7_CFG_QM_TENSOR_12_DIM_3_SIZE 0xFC6CC8 + +#define mmTPC7_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xFC6CCC + +#define mmTPC7_CFG_QM_TENSOR_12_DIM_4_SIZE 0xFC6CD0 + +#define mmTPC7_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xFC6CD4 + +#define mmTPC7_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xFC6CD8 + +#define mmTPC7_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xFC6CDC + +#define mmTPC7_CFG_QM_TENSOR_13_PADDING_VALUE 0xFC6CE0 + +#define mmTPC7_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xFC6CE4 + +#define mmTPC7_CFG_QM_TENSOR_13_DIM_0_SIZE 0xFC6CE8 + +#define mmTPC7_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xFC6CEC + +#define mmTPC7_CFG_QM_TENSOR_13_DIM_1_SIZE 0xFC6CF0 + +#define mmTPC7_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xFC6CF4 + +#define mmTPC7_CFG_QM_TENSOR_13_DIM_2_SIZE 0xFC6CF8 + +#define mmTPC7_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xFC6CFC + +#define mmTPC7_CFG_QM_TENSOR_13_DIM_3_SIZE 0xFC6D00 + +#define mmTPC7_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xFC6D04 + +#define mmTPC7_CFG_QM_TENSOR_13_DIM_4_SIZE 0xFC6D08 + +#define mmTPC7_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xFC6D0C + +#define mmTPC7_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xFC6D10 + +#define mmTPC7_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xFC6D14 + +#define mmTPC7_CFG_QM_TENSOR_14_PADDING_VALUE 0xFC6D18 + +#define mmTPC7_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xFC6D1C + +#define mmTPC7_CFG_QM_TENSOR_14_DIM_0_SIZE 0xFC6D20 + +#define mmTPC7_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xFC6D24 + +#define mmTPC7_CFG_QM_TENSOR_14_DIM_1_SIZE 0xFC6D28 + +#define mmTPC7_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xFC6D2C + +#define mmTPC7_CFG_QM_TENSOR_14_DIM_2_SIZE 0xFC6D30 + +#define mmTPC7_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xFC6D34 + +#define mmTPC7_CFG_QM_TENSOR_14_DIM_3_SIZE 0xFC6D38 + +#define mmTPC7_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xFC6D3C + +#define mmTPC7_CFG_QM_TENSOR_14_DIM_4_SIZE 0xFC6D40 + +#define mmTPC7_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xFC6D44 + +#define mmTPC7_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xFC6D48 + +#define mmTPC7_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xFC6D4C + +#define mmTPC7_CFG_QM_TENSOR_15_PADDING_VALUE 0xFC6D50 + +#define mmTPC7_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xFC6D54 + +#define mmTPC7_CFG_QM_TENSOR_15_DIM_0_SIZE 0xFC6D58 + +#define mmTPC7_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xFC6D5C + +#define mmTPC7_CFG_QM_TENSOR_15_DIM_1_SIZE 0xFC6D60 + +#define mmTPC7_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xFC6D64 + +#define mmTPC7_CFG_QM_TENSOR_15_DIM_2_SIZE 0xFC6D68 + +#define mmTPC7_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xFC6D6C + +#define mmTPC7_CFG_QM_TENSOR_15_DIM_3_SIZE 0xFC6D70 + +#define mmTPC7_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xFC6D74 + +#define mmTPC7_CFG_QM_TENSOR_15_DIM_4_SIZE 0xFC6D78 + +#define mmTPC7_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xFC6D7C + +#define mmTPC7_CFG_QM_SYNC_OBJECT_MESSAGE 0xFC6D80 + +#define mmTPC7_CFG_QM_SYNC_OBJECT_ADDR 0xFC6D84 + +#define mmTPC7_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xFC6D88 + +#define mmTPC7_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xFC6D8C + +#define mmTPC7_CFG_QM_TID_BASE_DIM_0 0xFC6D90 + +#define mmTPC7_CFG_QM_TID_SIZE_DIM_0 0xFC6D94 + +#define mmTPC7_CFG_QM_TID_BASE_DIM_1 0xFC6D98 + +#define mmTPC7_CFG_QM_TID_SIZE_DIM_1 0xFC6D9C + +#define mmTPC7_CFG_QM_TID_BASE_DIM_2 0xFC6DA0 + +#define mmTPC7_CFG_QM_TID_SIZE_DIM_2 0xFC6DA4 + +#define mmTPC7_CFG_QM_TID_BASE_DIM_3 0xFC6DA8 + +#define mmTPC7_CFG_QM_TID_SIZE_DIM_3 0xFC6DAC + +#define mmTPC7_CFG_QM_TID_BASE_DIM_4 0xFC6DB0 + +#define mmTPC7_CFG_QM_TID_SIZE_DIM_4 0xFC6DB4 + +#define mmTPC7_CFG_QM_KERNEL_CONFIG 0xFC6DB8 + +#define mmTPC7_CFG_QM_KERNEL_ID 0xFC6DBC + +#define mmTPC7_CFG_QM_SRF_0 0xFC6DC0 + +#define mmTPC7_CFG_QM_SRF_1 0xFC6DC4 + +#define mmTPC7_CFG_QM_SRF_2 0xFC6DC8 + +#define mmTPC7_CFG_QM_SRF_3 0xFC6DCC + +#define mmTPC7_CFG_QM_SRF_4 0xFC6DD0 + +#define mmTPC7_CFG_QM_SRF_5 0xFC6DD4 + +#define mmTPC7_CFG_QM_SRF_6 0xFC6DD8 + +#define mmTPC7_CFG_QM_SRF_7 0xFC6DDC + +#define mmTPC7_CFG_QM_SRF_8 0xFC6DE0 + +#define mmTPC7_CFG_QM_SRF_9 0xFC6DE4 + +#define mmTPC7_CFG_QM_SRF_10 0xFC6DE8 + +#define mmTPC7_CFG_QM_SRF_11 0xFC6DEC + +#define mmTPC7_CFG_QM_SRF_12 0xFC6DF0 + +#define mmTPC7_CFG_QM_SRF_13 0xFC6DF4 + +#define mmTPC7_CFG_QM_SRF_14 0xFC6DF8 + +#define mmTPC7_CFG_QM_SRF_15 0xFC6DFC + +#define mmTPC7_CFG_QM_SRF_16 0xFC6E00 + +#define mmTPC7_CFG_QM_SRF_17 0xFC6E04 + +#define mmTPC7_CFG_QM_SRF_18 0xFC6E08 + +#define mmTPC7_CFG_QM_SRF_19 0xFC6E0C + +#define mmTPC7_CFG_QM_SRF_20 0xFC6E10 + +#define mmTPC7_CFG_QM_SRF_21 0xFC6E14 + +#define mmTPC7_CFG_QM_SRF_22 0xFC6E18 + +#define mmTPC7_CFG_QM_SRF_23 0xFC6E1C + +#define mmTPC7_CFG_QM_SRF_24 0xFC6E20 + +#define mmTPC7_CFG_QM_SRF_25 0xFC6E24 + +#define mmTPC7_CFG_QM_SRF_26 0xFC6E28 + +#define mmTPC7_CFG_QM_SRF_27 0xFC6E2C + +#define mmTPC7_CFG_QM_SRF_28 0xFC6E30 + +#define mmTPC7_CFG_QM_SRF_29 0xFC6E34 + +#define mmTPC7_CFG_QM_SRF_30 0xFC6E38 + +#define mmTPC7_CFG_QM_SRF_31 0xFC6E3C + +#endif /* ASIC_REG_TPC7_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc7_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc7_qm_regs.h new file mode 100644 index 000000000000..5c36c972c027 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc7_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC7_QM_REGS_H_ +#define ASIC_REG_TPC7_QM_REGS_H_ + +/* + ***************************************** + * TPC7_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC7_QM_GLBL_CFG0 0xFC8000 + +#define mmTPC7_QM_GLBL_CFG1 0xFC8004 + +#define mmTPC7_QM_GLBL_PROT 0xFC8008 + +#define mmTPC7_QM_GLBL_ERR_CFG 0xFC800C + +#define mmTPC7_QM_GLBL_SECURE_PROPS_0 0xFC8010 + +#define mmTPC7_QM_GLBL_SECURE_PROPS_1 0xFC8014 + +#define mmTPC7_QM_GLBL_SECURE_PROPS_2 0xFC8018 + +#define mmTPC7_QM_GLBL_SECURE_PROPS_3 0xFC801C + +#define mmTPC7_QM_GLBL_SECURE_PROPS_4 0xFC8020 + +#define mmTPC7_QM_GLBL_NON_SECURE_PROPS_0 0xFC8024 + +#define mmTPC7_QM_GLBL_NON_SECURE_PROPS_1 0xFC8028 + +#define mmTPC7_QM_GLBL_NON_SECURE_PROPS_2 0xFC802C + +#define mmTPC7_QM_GLBL_NON_SECURE_PROPS_3 0xFC8030 + +#define mmTPC7_QM_GLBL_NON_SECURE_PROPS_4 0xFC8034 + +#define mmTPC7_QM_GLBL_STS0 0xFC8038 + +#define mmTPC7_QM_GLBL_STS1_0 0xFC8040 + +#define mmTPC7_QM_GLBL_STS1_1 0xFC8044 + +#define mmTPC7_QM_GLBL_STS1_2 0xFC8048 + +#define mmTPC7_QM_GLBL_STS1_3 0xFC804C + +#define mmTPC7_QM_GLBL_STS1_4 0xFC8050 + +#define mmTPC7_QM_GLBL_MSG_EN_0 0xFC8054 + +#define mmTPC7_QM_GLBL_MSG_EN_1 0xFC8058 + +#define mmTPC7_QM_GLBL_MSG_EN_2 0xFC805C + +#define mmTPC7_QM_GLBL_MSG_EN_3 0xFC8060 + +#define mmTPC7_QM_GLBL_MSG_EN_4 0xFC8068 + +#define mmTPC7_QM_PQ_BASE_LO_0 0xFC8070 + +#define mmTPC7_QM_PQ_BASE_LO_1 0xFC8074 + +#define mmTPC7_QM_PQ_BASE_LO_2 0xFC8078 + +#define mmTPC7_QM_PQ_BASE_LO_3 0xFC807C + +#define mmTPC7_QM_PQ_BASE_HI_0 0xFC8080 + +#define mmTPC7_QM_PQ_BASE_HI_1 0xFC8084 + +#define mmTPC7_QM_PQ_BASE_HI_2 0xFC8088 + +#define mmTPC7_QM_PQ_BASE_HI_3 0xFC808C + +#define mmTPC7_QM_PQ_SIZE_0 0xFC8090 + +#define mmTPC7_QM_PQ_SIZE_1 0xFC8094 + +#define mmTPC7_QM_PQ_SIZE_2 0xFC8098 + +#define mmTPC7_QM_PQ_SIZE_3 0xFC809C + +#define mmTPC7_QM_PQ_PI_0 0xFC80A0 + +#define mmTPC7_QM_PQ_PI_1 0xFC80A4 + +#define mmTPC7_QM_PQ_PI_2 0xFC80A8 + +#define mmTPC7_QM_PQ_PI_3 0xFC80AC + +#define mmTPC7_QM_PQ_CI_0 0xFC80B0 + +#define mmTPC7_QM_PQ_CI_1 0xFC80B4 + +#define mmTPC7_QM_PQ_CI_2 0xFC80B8 + +#define mmTPC7_QM_PQ_CI_3 0xFC80BC + +#define mmTPC7_QM_PQ_CFG0_0 0xFC80C0 + +#define mmTPC7_QM_PQ_CFG0_1 0xFC80C4 + +#define mmTPC7_QM_PQ_CFG0_2 0xFC80C8 + +#define mmTPC7_QM_PQ_CFG0_3 0xFC80CC + +#define mmTPC7_QM_PQ_CFG1_0 0xFC80D0 + +#define mmTPC7_QM_PQ_CFG1_1 0xFC80D4 + +#define mmTPC7_QM_PQ_CFG1_2 0xFC80D8 + +#define mmTPC7_QM_PQ_CFG1_3 0xFC80DC + +#define mmTPC7_QM_PQ_ARUSER_31_11_0 0xFC80E0 + +#define mmTPC7_QM_PQ_ARUSER_31_11_1 0xFC80E4 + +#define mmTPC7_QM_PQ_ARUSER_31_11_2 0xFC80E8 + +#define mmTPC7_QM_PQ_ARUSER_31_11_3 0xFC80EC + +#define mmTPC7_QM_PQ_STS0_0 0xFC80F0 + +#define mmTPC7_QM_PQ_STS0_1 0xFC80F4 + +#define mmTPC7_QM_PQ_STS0_2 0xFC80F8 + +#define mmTPC7_QM_PQ_STS0_3 0xFC80FC + +#define mmTPC7_QM_PQ_STS1_0 0xFC8100 + +#define mmTPC7_QM_PQ_STS1_1 0xFC8104 + +#define mmTPC7_QM_PQ_STS1_2 0xFC8108 + +#define mmTPC7_QM_PQ_STS1_3 0xFC810C + +#define mmTPC7_QM_CQ_CFG0_0 0xFC8110 + +#define mmTPC7_QM_CQ_CFG0_1 0xFC8114 + +#define mmTPC7_QM_CQ_CFG0_2 0xFC8118 + +#define mmTPC7_QM_CQ_CFG0_3 0xFC811C + +#define mmTPC7_QM_CQ_CFG0_4 0xFC8120 + +#define mmTPC7_QM_CQ_CFG1_0 0xFC8124 + +#define mmTPC7_QM_CQ_CFG1_1 0xFC8128 + +#define mmTPC7_QM_CQ_CFG1_2 0xFC812C + +#define mmTPC7_QM_CQ_CFG1_3 0xFC8130 + +#define mmTPC7_QM_CQ_CFG1_4 0xFC8134 + +#define mmTPC7_QM_CQ_ARUSER_31_11_0 0xFC8138 + +#define mmTPC7_QM_CQ_ARUSER_31_11_1 0xFC813C + +#define mmTPC7_QM_CQ_ARUSER_31_11_2 0xFC8140 + +#define mmTPC7_QM_CQ_ARUSER_31_11_3 0xFC8144 + +#define mmTPC7_QM_CQ_ARUSER_31_11_4 0xFC8148 + +#define mmTPC7_QM_CQ_STS0_0 0xFC814C + +#define mmTPC7_QM_CQ_STS0_1 0xFC8150 + +#define mmTPC7_QM_CQ_STS0_2 0xFC8154 + +#define mmTPC7_QM_CQ_STS0_3 0xFC8158 + +#define mmTPC7_QM_CQ_STS0_4 0xFC815C + +#define mmTPC7_QM_CQ_STS1_0 0xFC8160 + +#define mmTPC7_QM_CQ_STS1_1 0xFC8164 + +#define mmTPC7_QM_CQ_STS1_2 0xFC8168 + +#define mmTPC7_QM_CQ_STS1_3 0xFC816C + +#define mmTPC7_QM_CQ_STS1_4 0xFC8170 + +#define mmTPC7_QM_CQ_PTR_LO_0 0xFC8174 + +#define mmTPC7_QM_CQ_PTR_HI_0 0xFC8178 + +#define mmTPC7_QM_CQ_TSIZE_0 0xFC817C + +#define mmTPC7_QM_CQ_CTL_0 0xFC8180 + +#define mmTPC7_QM_CQ_PTR_LO_1 0xFC8184 + +#define mmTPC7_QM_CQ_PTR_HI_1 0xFC8188 + +#define mmTPC7_QM_CQ_TSIZE_1 0xFC818C + +#define mmTPC7_QM_CQ_CTL_1 0xFC8190 + +#define mmTPC7_QM_CQ_PTR_LO_2 0xFC8194 + +#define mmTPC7_QM_CQ_PTR_HI_2 0xFC8198 + +#define mmTPC7_QM_CQ_TSIZE_2 0xFC819C + +#define mmTPC7_QM_CQ_CTL_2 0xFC81A0 + +#define mmTPC7_QM_CQ_PTR_LO_3 0xFC81A4 + +#define mmTPC7_QM_CQ_PTR_HI_3 0xFC81A8 + +#define mmTPC7_QM_CQ_TSIZE_3 0xFC81AC + +#define mmTPC7_QM_CQ_CTL_3 0xFC81B0 + +#define mmTPC7_QM_CQ_PTR_LO_4 0xFC81B4 + +#define mmTPC7_QM_CQ_PTR_HI_4 0xFC81B8 + +#define mmTPC7_QM_CQ_TSIZE_4 0xFC81BC + +#define mmTPC7_QM_CQ_CTL_4 0xFC81C0 + +#define mmTPC7_QM_CQ_PTR_LO_STS_0 0xFC81C4 + +#define mmTPC7_QM_CQ_PTR_LO_STS_1 0xFC81C8 + +#define mmTPC7_QM_CQ_PTR_LO_STS_2 0xFC81CC + +#define mmTPC7_QM_CQ_PTR_LO_STS_3 0xFC81D0 + +#define mmTPC7_QM_CQ_PTR_LO_STS_4 0xFC81D4 + +#define mmTPC7_QM_CQ_PTR_HI_STS_0 0xFC81D8 + +#define mmTPC7_QM_CQ_PTR_HI_STS_1 0xFC81DC + +#define mmTPC7_QM_CQ_PTR_HI_STS_2 0xFC81E0 + +#define mmTPC7_QM_CQ_PTR_HI_STS_3 0xFC81E4 + +#define mmTPC7_QM_CQ_PTR_HI_STS_4 0xFC81E8 + +#define mmTPC7_QM_CQ_TSIZE_STS_0 0xFC81EC + +#define mmTPC7_QM_CQ_TSIZE_STS_1 0xFC81F0 + +#define mmTPC7_QM_CQ_TSIZE_STS_2 0xFC81F4 + +#define mmTPC7_QM_CQ_TSIZE_STS_3 0xFC81F8 + +#define mmTPC7_QM_CQ_TSIZE_STS_4 0xFC81FC + +#define mmTPC7_QM_CQ_CTL_STS_0 0xFC8200 + +#define mmTPC7_QM_CQ_CTL_STS_1 0xFC8204 + +#define mmTPC7_QM_CQ_CTL_STS_2 0xFC8208 + +#define mmTPC7_QM_CQ_CTL_STS_3 0xFC820C + +#define mmTPC7_QM_CQ_CTL_STS_4 0xFC8210 + +#define mmTPC7_QM_CQ_IFIFO_CNT_0 0xFC8214 + +#define mmTPC7_QM_CQ_IFIFO_CNT_1 0xFC8218 + +#define mmTPC7_QM_CQ_IFIFO_CNT_2 0xFC821C + +#define mmTPC7_QM_CQ_IFIFO_CNT_3 0xFC8220 + +#define mmTPC7_QM_CQ_IFIFO_CNT_4 0xFC8224 + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_0 0xFC8228 + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_1 0xFC822C + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_2 0xFC8230 + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_3 0xFC8234 + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_4 0xFC8238 + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_0 0xFC823C + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_1 0xFC8240 + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_2 0xFC8244 + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_3 0xFC8248 + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_4 0xFC824C + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_0 0xFC8250 + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_1 0xFC8254 + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_2 0xFC8258 + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_3 0xFC825C + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_4 0xFC8260 + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_0 0xFC8264 + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_1 0xFC8268 + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_2 0xFC826C + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_3 0xFC8270 + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_4 0xFC8274 + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_0 0xFC8278 + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_1 0xFC827C + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_2 0xFC8280 + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_3 0xFC8284 + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_4 0xFC8288 + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_0 0xFC828C + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_1 0xFC8290 + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_2 0xFC8294 + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_3 0xFC8298 + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_4 0xFC829C + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_0 0xFC82A0 + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_1 0xFC82A4 + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_2 0xFC82A8 + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_3 0xFC82AC + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_4 0xFC82B0 + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_0 0xFC82B4 + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_1 0xFC82B8 + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_2 0xFC82BC + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_3 0xFC82C0 + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_4 0xFC82C4 + +#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_0 0xFC82C8 + +#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_1 0xFC82CC + +#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_2 0xFC82D0 + +#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_3 0xFC82D4 + +#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_4 0xFC82D8 + +#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xFC82E0 + +#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xFC82E4 + +#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xFC82E8 + +#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xFC82EC + +#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xFC82F0 + +#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xFC82F4 + +#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xFC82F8 + +#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xFC82FC + +#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xFC8300 + +#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xFC8304 + +#define mmTPC7_QM_CP_FENCE0_RDATA_0 0xFC8308 + +#define mmTPC7_QM_CP_FENCE0_RDATA_1 0xFC830C + +#define mmTPC7_QM_CP_FENCE0_RDATA_2 0xFC8310 + +#define mmTPC7_QM_CP_FENCE0_RDATA_3 0xFC8314 + +#define mmTPC7_QM_CP_FENCE0_RDATA_4 0xFC8318 + +#define mmTPC7_QM_CP_FENCE1_RDATA_0 0xFC831C + +#define mmTPC7_QM_CP_FENCE1_RDATA_1 0xFC8320 + +#define mmTPC7_QM_CP_FENCE1_RDATA_2 0xFC8324 + +#define mmTPC7_QM_CP_FENCE1_RDATA_3 0xFC8328 + +#define mmTPC7_QM_CP_FENCE1_RDATA_4 0xFC832C + +#define mmTPC7_QM_CP_FENCE2_RDATA_0 0xFC8330 + +#define mmTPC7_QM_CP_FENCE2_RDATA_1 0xFC8334 + +#define mmTPC7_QM_CP_FENCE2_RDATA_2 0xFC8338 + +#define mmTPC7_QM_CP_FENCE2_RDATA_3 0xFC833C + +#define mmTPC7_QM_CP_FENCE2_RDATA_4 0xFC8340 + +#define mmTPC7_QM_CP_FENCE3_RDATA_0 0xFC8344 + +#define mmTPC7_QM_CP_FENCE3_RDATA_1 0xFC8348 + +#define mmTPC7_QM_CP_FENCE3_RDATA_2 0xFC834C + +#define mmTPC7_QM_CP_FENCE3_RDATA_3 0xFC8350 + +#define mmTPC7_QM_CP_FENCE3_RDATA_4 0xFC8354 + +#define mmTPC7_QM_CP_FENCE0_CNT_0 0xFC8358 + +#define mmTPC7_QM_CP_FENCE0_CNT_1 0xFC835C + +#define mmTPC7_QM_CP_FENCE0_CNT_2 0xFC8360 + +#define mmTPC7_QM_CP_FENCE0_CNT_3 0xFC8364 + +#define mmTPC7_QM_CP_FENCE0_CNT_4 0xFC8368 + +#define mmTPC7_QM_CP_FENCE1_CNT_0 0xFC836C + +#define mmTPC7_QM_CP_FENCE1_CNT_1 0xFC8370 + +#define mmTPC7_QM_CP_FENCE1_CNT_2 0xFC8374 + +#define mmTPC7_QM_CP_FENCE1_CNT_3 0xFC8378 + +#define mmTPC7_QM_CP_FENCE1_CNT_4 0xFC837C + +#define mmTPC7_QM_CP_FENCE2_CNT_0 0xFC8380 + +#define mmTPC7_QM_CP_FENCE2_CNT_1 0xFC8384 + +#define mmTPC7_QM_CP_FENCE2_CNT_2 0xFC8388 + +#define mmTPC7_QM_CP_FENCE2_CNT_3 0xFC838C + +#define mmTPC7_QM_CP_FENCE2_CNT_4 0xFC8390 + +#define mmTPC7_QM_CP_FENCE3_CNT_0 0xFC8394 + +#define mmTPC7_QM_CP_FENCE3_CNT_1 0xFC8398 + +#define mmTPC7_QM_CP_FENCE3_CNT_2 0xFC839C + +#define mmTPC7_QM_CP_FENCE3_CNT_3 0xFC83A0 + +#define mmTPC7_QM_CP_FENCE3_CNT_4 0xFC83A4 + +#define mmTPC7_QM_CP_STS_0 0xFC83A8 + +#define mmTPC7_QM_CP_STS_1 0xFC83AC + +#define mmTPC7_QM_CP_STS_2 0xFC83B0 + +#define mmTPC7_QM_CP_STS_3 0xFC83B4 + +#define mmTPC7_QM_CP_STS_4 0xFC83B8 + +#define mmTPC7_QM_CP_CURRENT_INST_LO_0 0xFC83BC + +#define mmTPC7_QM_CP_CURRENT_INST_LO_1 0xFC83C0 + +#define mmTPC7_QM_CP_CURRENT_INST_LO_2 0xFC83C4 + +#define mmTPC7_QM_CP_CURRENT_INST_LO_3 0xFC83C8 + +#define mmTPC7_QM_CP_CURRENT_INST_LO_4 0xFC83CC + +#define mmTPC7_QM_CP_CURRENT_INST_HI_0 0xFC83D0 + +#define mmTPC7_QM_CP_CURRENT_INST_HI_1 0xFC83D4 + +#define mmTPC7_QM_CP_CURRENT_INST_HI_2 0xFC83D8 + +#define mmTPC7_QM_CP_CURRENT_INST_HI_3 0xFC83DC + +#define mmTPC7_QM_CP_CURRENT_INST_HI_4 0xFC83E0 + +#define mmTPC7_QM_CP_BARRIER_CFG_0 0xFC83F4 + +#define mmTPC7_QM_CP_BARRIER_CFG_1 0xFC83F8 + +#define mmTPC7_QM_CP_BARRIER_CFG_2 0xFC83FC + +#define mmTPC7_QM_CP_BARRIER_CFG_3 0xFC8400 + +#define mmTPC7_QM_CP_BARRIER_CFG_4 0xFC8404 + +#define mmTPC7_QM_CP_DBG_0_0 0xFC8408 + +#define mmTPC7_QM_CP_DBG_0_1 0xFC840C + +#define mmTPC7_QM_CP_DBG_0_2 0xFC8410 + +#define mmTPC7_QM_CP_DBG_0_3 0xFC8414 + +#define mmTPC7_QM_CP_DBG_0_4 0xFC8418 + +#define mmTPC7_QM_CP_ARUSER_31_11_0 0xFC841C + +#define mmTPC7_QM_CP_ARUSER_31_11_1 0xFC8420 + +#define mmTPC7_QM_CP_ARUSER_31_11_2 0xFC8424 + +#define mmTPC7_QM_CP_ARUSER_31_11_3 0xFC8428 + +#define mmTPC7_QM_CP_ARUSER_31_11_4 0xFC842C + +#define mmTPC7_QM_CP_AWUSER_31_11_0 0xFC8430 + +#define mmTPC7_QM_CP_AWUSER_31_11_1 0xFC8434 + +#define mmTPC7_QM_CP_AWUSER_31_11_2 0xFC8438 + +#define mmTPC7_QM_CP_AWUSER_31_11_3 0xFC843C + +#define mmTPC7_QM_CP_AWUSER_31_11_4 0xFC8440 + +#define mmTPC7_QM_ARB_CFG_0 0xFC8A00 + +#define mmTPC7_QM_ARB_CHOISE_Q_PUSH 0xFC8A04 + +#define mmTPC7_QM_ARB_WRR_WEIGHT_0 0xFC8A08 + +#define mmTPC7_QM_ARB_WRR_WEIGHT_1 0xFC8A0C + +#define mmTPC7_QM_ARB_WRR_WEIGHT_2 0xFC8A10 + +#define mmTPC7_QM_ARB_WRR_WEIGHT_3 0xFC8A14 + +#define mmTPC7_QM_ARB_CFG_1 0xFC8A18 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_0 0xFC8A20 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_1 0xFC8A24 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_2 0xFC8A28 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_3 0xFC8A2C + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_4 0xFC8A30 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_5 0xFC8A34 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_6 0xFC8A38 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_7 0xFC8A3C + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_8 0xFC8A40 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_9 0xFC8A44 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_10 0xFC8A48 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_11 0xFC8A4C + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_12 0xFC8A50 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_13 0xFC8A54 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_14 0xFC8A58 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_15 0xFC8A5C + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_16 0xFC8A60 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_17 0xFC8A64 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_18 0xFC8A68 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_19 0xFC8A6C + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_20 0xFC8A70 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_21 0xFC8A74 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_22 0xFC8A78 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_23 0xFC8A7C + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_24 0xFC8A80 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_25 0xFC8A84 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_26 0xFC8A88 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_27 0xFC8A8C + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_28 0xFC8A90 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_29 0xFC8A94 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_30 0xFC8A98 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_31 0xFC8A9C + +#define mmTPC7_QM_ARB_MST_CRED_INC 0xFC8AA0 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xFC8AA4 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xFC8AA8 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xFC8AAC + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xFC8AB0 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xFC8AB4 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xFC8AB8 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xFC8ABC + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xFC8AC0 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xFC8AC4 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xFC8AC8 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xFC8ACC + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xFC8AD0 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xFC8AD4 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xFC8AD8 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xFC8ADC + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xFC8AE0 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xFC8AE4 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xFC8AE8 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xFC8AEC + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xFC8AF0 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xFC8AF4 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xFC8AF8 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xFC8AFC + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xFC8B00 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xFC8B04 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xFC8B08 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xFC8B0C + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xFC8B10 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xFC8B14 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xFC8B18 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xFC8B1C + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xFC8B20 + +#define mmTPC7_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xFC8B28 + +#define mmTPC7_QM_ARB_MST_SLAVE_EN 0xFC8B2C + +#define mmTPC7_QM_ARB_MST_QUIET_PER 0xFC8B34 + +#define mmTPC7_QM_ARB_SLV_CHOISE_WDT 0xFC8B38 + +#define mmTPC7_QM_ARB_SLV_ID 0xFC8B3C + +#define mmTPC7_QM_ARB_MSG_MAX_INFLIGHT 0xFC8B44 + +#define mmTPC7_QM_ARB_MSG_AWUSER_31_11 0xFC8B48 + +#define mmTPC7_QM_ARB_MSG_AWUSER_SEC_PROP 0xFC8B4C + +#define mmTPC7_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xFC8B50 + +#define mmTPC7_QM_ARB_BASE_LO 0xFC8B54 + +#define mmTPC7_QM_ARB_BASE_HI 0xFC8B58 + +#define mmTPC7_QM_ARB_STATE_STS 0xFC8B80 + +#define mmTPC7_QM_ARB_CHOISE_FULLNESS_STS 0xFC8B84 + +#define mmTPC7_QM_ARB_MSG_STS 0xFC8B88 + +#define mmTPC7_QM_ARB_SLV_CHOISE_Q_HEAD 0xFC8B8C + +#define mmTPC7_QM_ARB_ERR_CAUSE 0xFC8B9C + +#define mmTPC7_QM_ARB_ERR_MSG_EN 0xFC8BA0 + +#define mmTPC7_QM_ARB_ERR_STS_DRP 0xFC8BA8 + +#define mmTPC7_QM_ARB_MST_CRED_STS_0 0xFC8BB0 + +#define mmTPC7_QM_ARB_MST_CRED_STS_1 0xFC8BB4 + +#define mmTPC7_QM_ARB_MST_CRED_STS_2 0xFC8BB8 + +#define mmTPC7_QM_ARB_MST_CRED_STS_3 0xFC8BBC + +#define mmTPC7_QM_ARB_MST_CRED_STS_4 0xFC8BC0 + +#define mmTPC7_QM_ARB_MST_CRED_STS_5 0xFC8BC4 + +#define mmTPC7_QM_ARB_MST_CRED_STS_6 0xFC8BC8 + +#define mmTPC7_QM_ARB_MST_CRED_STS_7 0xFC8BCC + +#define mmTPC7_QM_ARB_MST_CRED_STS_8 0xFC8BD0 + +#define mmTPC7_QM_ARB_MST_CRED_STS_9 0xFC8BD4 + +#define mmTPC7_QM_ARB_MST_CRED_STS_10 0xFC8BD8 + +#define mmTPC7_QM_ARB_MST_CRED_STS_11 0xFC8BDC + +#define mmTPC7_QM_ARB_MST_CRED_STS_12 0xFC8BE0 + +#define mmTPC7_QM_ARB_MST_CRED_STS_13 0xFC8BE4 + +#define mmTPC7_QM_ARB_MST_CRED_STS_14 0xFC8BE8 + +#define mmTPC7_QM_ARB_MST_CRED_STS_15 0xFC8BEC + +#define mmTPC7_QM_ARB_MST_CRED_STS_16 0xFC8BF0 + +#define mmTPC7_QM_ARB_MST_CRED_STS_17 0xFC8BF4 + +#define mmTPC7_QM_ARB_MST_CRED_STS_18 0xFC8BF8 + +#define mmTPC7_QM_ARB_MST_CRED_STS_19 0xFC8BFC + +#define mmTPC7_QM_ARB_MST_CRED_STS_20 0xFC8C00 + +#define mmTPC7_QM_ARB_MST_CRED_STS_21 0xFC8C04 + +#define mmTPC7_QM_ARB_MST_CRED_STS_22 0xFC8C08 + +#define mmTPC7_QM_ARB_MST_CRED_STS_23 0xFC8C0C + +#define mmTPC7_QM_ARB_MST_CRED_STS_24 0xFC8C10 + +#define mmTPC7_QM_ARB_MST_CRED_STS_25 0xFC8C14 + +#define mmTPC7_QM_ARB_MST_CRED_STS_26 0xFC8C18 + +#define mmTPC7_QM_ARB_MST_CRED_STS_27 0xFC8C1C + +#define mmTPC7_QM_ARB_MST_CRED_STS_28 0xFC8C20 + +#define mmTPC7_QM_ARB_MST_CRED_STS_29 0xFC8C24 + +#define mmTPC7_QM_ARB_MST_CRED_STS_30 0xFC8C28 + +#define mmTPC7_QM_ARB_MST_CRED_STS_31 0xFC8C2C + +#define mmTPC7_QM_CGM_CFG 0xFC8C70 + +#define mmTPC7_QM_CGM_STS 0xFC8C74 + +#define mmTPC7_QM_CGM_CFG1 0xFC8C78 + +#define mmTPC7_QM_LOCAL_RANGE_BASE 0xFC8C80 + +#define mmTPC7_QM_LOCAL_RANGE_SIZE 0xFC8C84 + +#define mmTPC7_QM_CSMR_STRICT_PRIO_CFG 0xFC8C90 + +#define mmTPC7_QM_HBW_RD_RATE_LIM_CFG_1 0xFC8C94 + +#define mmTPC7_QM_LBW_WR_RATE_LIM_CFG_0 0xFC8C98 + +#define mmTPC7_QM_LBW_WR_RATE_LIM_CFG_1 0xFC8C9C + +#define mmTPC7_QM_HBW_RD_RATE_LIM_CFG_0 0xFC8CA0 + +#define mmTPC7_QM_GLBL_AXCACHE 0xFC8CA4 + +#define mmTPC7_QM_IND_GW_APB_CFG 0xFC8CB0 + +#define mmTPC7_QM_IND_GW_APB_WDATA 0xFC8CB4 + +#define mmTPC7_QM_IND_GW_APB_RDATA 0xFC8CB8 + +#define mmTPC7_QM_IND_GW_APB_STATUS 0xFC8CBC + +#define mmTPC7_QM_GLBL_ERR_ADDR_LO 0xFC8CD0 + +#define mmTPC7_QM_GLBL_ERR_ADDR_HI 0xFC8CD4 + +#define mmTPC7_QM_GLBL_ERR_WDATA 0xFC8CD8 + +#define mmTPC7_QM_GLBL_MEM_INIT_BUSY 0xFC8D00 + +#endif /* ASIC_REG_TPC7_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/gaudi.h b/drivers/misc/habanalabs/include/gaudi/gaudi.h new file mode 100644 index 000000000000..8829891d3eef --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/gaudi.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2018-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDI_H +#define GAUDI_H + +#define SRAM_BAR_ID 0 +#define CFG_BAR_ID 2 +#define HBM_BAR_ID 4 + +#define SRAM_BAR_SIZE 0x4000000ull /* 64MB */ +#define CFG_BAR_SIZE 0x8000000ull /* 128MB */ + +#define CFG_BASE 0x7FFC000000ull +#define CFG_SIZE 0x4000000 /* 32MB CFG + 32MB DBG*/ + +#define SRAM_BASE_ADDR 0x7FF0000000ull +#define SRAM_SIZE 0x1400000 /* 20MB */ + +#define SPI_FLASH_BASE_ADDR 0x7FF8000000ull + +#define PSOC_SCRATCHPAD_ADDR 0x7FFBFE0000ull +#define PSOC_SCRATCHPAD_SIZE 0x10000 /* 64KB */ + +#define PCIE_FW_SRAM_ADDR 0x7FFBFF0000ull +#define PCIE_FW_SRAM_SIZE 0x8000 /* 32KB */ + +#define DRAM_PHYS_BASE 0x0ull + +#define HOST_PHYS_BASE 0x8000000000ull /* 0.5TB */ +#define HOST_PHYS_SIZE 0x1000000000000ull /* 0.25PB (48 bits) */ + +#define GAUDI_MSI_ENTRIES 32 + +#define QMAN_PQ_ENTRY_SIZE 16 /* Bytes */ + +#define MAX_ASID 1024 + +#define PROT_BITS_OFFS 0xF80 + +#define MME_NUMBER_OF_MASTER_ENGINES 2 + +#define TPC_NUMBER_OF_ENGINES 8 + +#define DMA_NUMBER_OF_CHANNELS 8 + +#define NIC_NUMBER_OF_MACROS 5 + +#define NIC_NUMBER_OF_ENGINES (NIC_NUMBER_OF_MACROS * 2) + +#define NUMBER_OF_IF 8 + +#define DEVICE_CACHE_LINE_SIZE 128 + +#endif /* GAUDI_H */ diff --git a/drivers/misc/habanalabs/include/gaudi/gaudi_async_events.h b/drivers/misc/habanalabs/include/gaudi/gaudi_async_events.h new file mode 100644 index 000000000000..9ccba8437ec9 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/gaudi_async_events.h @@ -0,0 +1,310 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2018-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef __GAUDI_ASYNC_EVENTS_H_ +#define __GAUDI_ASYNC_EVENTS_H_ + +enum gaudi_async_event_id { + GAUDI_EVENT_PCIE_CORE_SERR = 32, + GAUDI_EVENT_PCIE_CORE_DERR = 33, + GAUDI_EVENT_PCIE_IF_SERR = 34, + GAUDI_EVENT_PCIE_IF_DERR = 35, + GAUDI_EVENT_PCIE_PHY_SERR = 36, + GAUDI_EVENT_PCIE_PHY_DERR = 37, + GAUDI_EVENT_TPC0_SERR = 38, + GAUDI_EVENT_TPC1_SERR = 39, + GAUDI_EVENT_TPC2_SERR = 40, + GAUDI_EVENT_TPC3_SERR = 41, + GAUDI_EVENT_TPC4_SERR = 42, + GAUDI_EVENT_TPC5_SERR = 43, + GAUDI_EVENT_TPC6_SERR = 44, + GAUDI_EVENT_TPC7_SERR = 45, + GAUDI_EVENT_TPC0_DERR = 46, + GAUDI_EVENT_TPC1_DERR = 47, + GAUDI_EVENT_TPC2_DERR = 48, + GAUDI_EVENT_TPC3_DERR = 49, + GAUDI_EVENT_TPC4_DERR = 50, + GAUDI_EVENT_TPC5_DERR = 51, + GAUDI_EVENT_TPC6_DERR = 52, + GAUDI_EVENT_TPC7_DERR = 53, + GAUDI_EVENT_MME0_ACC_SERR = 54, + GAUDI_EVENT_MME0_ACC_DERR = 55, + GAUDI_EVENT_MME0_SBAB_SERR = 56, + GAUDI_EVENT_MME0_SBAB_DERR = 57, + GAUDI_EVENT_MME1_ACC_SERR = 58, + GAUDI_EVENT_MME1_ACC_DERR = 59, + GAUDI_EVENT_MME1_SBAB_SERR = 60, + GAUDI_EVENT_MME1_SBAB_DERR = 61, + GAUDI_EVENT_MME2_ACC_SERR = 62, + GAUDI_EVENT_MME2_ACC_DERR = 63, + GAUDI_EVENT_MME2_SBAB_SERR = 64, + GAUDI_EVENT_MME2_SBAB_DERR = 65, + GAUDI_EVENT_MME3_ACC_SERR = 66, + GAUDI_EVENT_MME3_ACC_DERR = 67, + GAUDI_EVENT_MME3_SBAB_SERR = 68, + GAUDI_EVENT_MME3_SBAB_DERR = 69, + GAUDI_EVENT_DMA0_SERR_ECC = 70, + GAUDI_EVENT_DMA1_SERR_ECC = 71, + GAUDI_EVENT_DMA2_SERR_ECC = 72, + GAUDI_EVENT_DMA3_SERR_ECC = 73, + GAUDI_EVENT_DMA4_SERR_ECC = 74, + GAUDI_EVENT_DMA5_SERR_ECC = 75, + GAUDI_EVENT_DMA6_SERR_ECC = 76, + GAUDI_EVENT_DMA7_SERR_ECC = 77, + GAUDI_EVENT_DMA0_DERR_ECC = 78, + GAUDI_EVENT_DMA1_DERR_ECC = 79, + GAUDI_EVENT_DMA2_DERR_ECC = 80, + GAUDI_EVENT_DMA3_DERR_ECC = 81, + GAUDI_EVENT_DMA4_DERR_ECC = 82, + GAUDI_EVENT_DMA5_DERR_ECC = 83, + GAUDI_EVENT_DMA6_DERR_ECC = 84, + GAUDI_EVENT_DMA7_DERR_ECC = 85, + GAUDI_EVENT_CPU_IF_ECC_SERR = 86, + GAUDI_EVENT_CPU_IF_ECC_DERR = 87, + GAUDI_EVENT_PSOC_MEM_SERR = 88, + GAUDI_EVENT_PSOC_CORESIGHT_SERR = 89, + GAUDI_EVENT_PSOC_MEM_DERR = 90, + GAUDI_EVENT_PSOC_CORESIGHT_DERR = 91, + GAUDI_EVENT_SRAM0_SERR = 92, + GAUDI_EVENT_SRAM1_SERR = 93, + GAUDI_EVENT_SRAM2_SERR = 94, + GAUDI_EVENT_SRAM3_SERR = 95, + GAUDI_EVENT_SRAM7_SERR = 96, + GAUDI_EVENT_SRAM6_SERR = 97, + GAUDI_EVENT_SRAM5_SERR = 98, + GAUDI_EVENT_SRAM4_SERR = 99, + GAUDI_EVENT_SRAM8_SERR = 100, + GAUDI_EVENT_SRAM9_SERR = 101, + GAUDI_EVENT_SRAM10_SERR = 102, + GAUDI_EVENT_SRAM11_SERR = 103, + GAUDI_EVENT_SRAM15_SERR = 104, + GAUDI_EVENT_SRAM14_SERR = 105, + GAUDI_EVENT_SRAM13_SERR = 106, + GAUDI_EVENT_SRAM12_SERR = 107, + GAUDI_EVENT_SRAM16_SERR = 108, + GAUDI_EVENT_SRAM17_SERR = 109, + GAUDI_EVENT_SRAM18_SERR = 110, + GAUDI_EVENT_SRAM19_SERR = 111, + GAUDI_EVENT_SRAM23_SERR = 112, + GAUDI_EVENT_SRAM22_SERR = 113, + GAUDI_EVENT_SRAM21_SERR = 114, + GAUDI_EVENT_SRAM20_SERR = 115, + GAUDI_EVENT_SRAM24_SERR = 116, + GAUDI_EVENT_SRAM25_SERR = 117, + GAUDI_EVENT_SRAM26_SERR = 118, + GAUDI_EVENT_SRAM27_SERR = 119, + GAUDI_EVENT_SRAM31_SERR = 120, + GAUDI_EVENT_SRAM30_SERR = 121, + GAUDI_EVENT_SRAM29_SERR = 122, + GAUDI_EVENT_SRAM28_SERR = 123, + GAUDI_EVENT_SRAM0_DERR = 124, + GAUDI_EVENT_SRAM1_DERR = 125, + GAUDI_EVENT_SRAM2_DERR = 126, + GAUDI_EVENT_SRAM3_DERR = 127, + GAUDI_EVENT_SRAM7_DERR = 128, + GAUDI_EVENT_SRAM6_DERR = 129, + GAUDI_EVENT_SRAM5_DERR = 130, + GAUDI_EVENT_SRAM4_DERR = 131, + GAUDI_EVENT_SRAM8_DERR = 132, + GAUDI_EVENT_SRAM9_DERR = 133, + GAUDI_EVENT_SRAM10_DERR = 134, + GAUDI_EVENT_SRAM11_DERR = 135, + GAUDI_EVENT_SRAM15_DERR = 136, + GAUDI_EVENT_SRAM14_DERR = 137, + GAUDI_EVENT_SRAM13_DERR = 138, + GAUDI_EVENT_SRAM12_DERR = 139, + GAUDI_EVENT_SRAM16_DERR = 140, + GAUDI_EVENT_SRAM17_DERR = 141, + GAUDI_EVENT_SRAM18_DERR = 142, + GAUDI_EVENT_SRAM19_DERR = 143, + GAUDI_EVENT_SRAM23_DERR = 144, + GAUDI_EVENT_SRAM22_DERR = 145, + GAUDI_EVENT_SRAM21_DERR = 146, + GAUDI_EVENT_SRAM20_DERR = 147, + GAUDI_EVENT_SRAM24_DERR = 148, + GAUDI_EVENT_SRAM25_DERR = 149, + GAUDI_EVENT_SRAM26_DERR = 150, + GAUDI_EVENT_SRAM27_DERR = 151, + GAUDI_EVENT_SRAM31_DERR = 152, + GAUDI_EVENT_SRAM30_DERR = 153, + GAUDI_EVENT_SRAM29_DERR = 154, + GAUDI_EVENT_SRAM28_DERR = 155, + GAUDI_EVENT_NIC0_SERR = 156, + GAUDI_EVENT_NIC1_SERR = 157, + GAUDI_EVENT_NIC2_SERR = 158, + GAUDI_EVENT_NIC3_SERR = 159, + GAUDI_EVENT_NIC4_SERR = 160, + GAUDI_EVENT_NIC0_DERR = 166, + GAUDI_EVENT_NIC1_DERR = 167, + GAUDI_EVENT_NIC2_DERR = 168, + GAUDI_EVENT_NIC3_DERR = 169, + GAUDI_EVENT_NIC4_DERR = 170, + GAUDI_EVENT_DMA_IF0_SERR = 176, + GAUDI_EVENT_DMA_IF1_SERR = 177, + GAUDI_EVENT_DMA_IF2_SERR = 178, + GAUDI_EVENT_DMA_IF3_SERR = 179, + GAUDI_EVENT_DMA_IF0_DERR = 180, + GAUDI_EVENT_DMA_IF1_DERR = 181, + GAUDI_EVENT_DMA_IF2_DERR = 182, + GAUDI_EVENT_DMA_IF3_DERR = 183, + GAUDI_EVENT_GIC500 = 184, + GAUDI_EVENT_HBM_0_SERR = 185, + GAUDI_EVENT_HBM_1_SERR = 186, + GAUDI_EVENT_HBM_2_SERR = 187, + GAUDI_EVENT_HBM_3_SERR = 188, + GAUDI_EVENT_HBM_0_DERR = 189, + GAUDI_EVENT_HBM_1_DERR = 190, + GAUDI_EVENT_HBM_2_DERR = 191, + GAUDI_EVENT_HBM_3_DERR = 192, + GAUDI_EVENT_MMU_SERR = 193, + GAUDI_EVENT_MMU_DERR = 194, + GAUDI_EVENT_PCIE_DEC = 200, + GAUDI_EVENT_TPC0_DEC = 201, + GAUDI_EVENT_TPC1_DEC = 203, + GAUDI_EVENT_TPC2_DEC = 205, + GAUDI_EVENT_TPC3_DEC = 207, + GAUDI_EVENT_TPC4_DEC = 209, + GAUDI_EVENT_TPC5_DEC = 211, + GAUDI_EVENT_TPC6_DEC = 213, + GAUDI_EVENT_TPC7_DEC = 215, + GAUDI_EVENT_AXI_ECC = 217, + GAUDI_EVENT_L2_RAM_ECC = 218, + GAUDI_EVENT_MME0_WBC_RSP = 219, + GAUDI_EVENT_MME0_SBAB0_RSP = 220, + GAUDI_EVENT_MME1_WBC_RSP = 224, + GAUDI_EVENT_MME1_SBAB0_RSP = 225, + GAUDI_EVENT_MME2_WBC_RSP = 229, + GAUDI_EVENT_MME2_SBAB0_RSP = 230, + GAUDI_EVENT_MME3_WBC_RSP = 234, + GAUDI_EVENT_MME3_SBAB0_RSP = 235, + GAUDI_EVENT_PLL0 = 239, + GAUDI_EVENT_PLL1 = 240, + GAUDI_EVENT_PLL2 = 241, + GAUDI_EVENT_PLL3 = 242, + GAUDI_EVENT_PLL4 = 243, + GAUDI_EVENT_PLL5 = 244, + GAUDI_EVENT_PLL6 = 245, + GAUDI_EVENT_PLL7 = 246, + GAUDI_EVENT_PLL8 = 247, + GAUDI_EVENT_PLL9 = 248, + GAUDI_EVENT_PLL10 = 249, + GAUDI_EVENT_PLL11 = 250, + GAUDI_EVENT_PLL12 = 251, + GAUDI_EVENT_PLL13 = 252, + GAUDI_EVENT_PLL14 = 253, + GAUDI_EVENT_PLL15 = 254, + GAUDI_EVENT_PLL16 = 255, + GAUDI_EVENT_PLL17 = 256, + GAUDI_EVENT_CPU_AXI_SPLITTER = 257, + GAUDI_EVENT_PSOC_AXI_DEC = 262, + GAUDI_EVENT_PSOC_PRSTN_FALL = 263, + GAUDI_EVENT_NIC_SEI_0 = 264, + GAUDI_EVENT_NIC_SEI_1 = 265, + GAUDI_EVENT_NIC_SEI_2 = 266, + GAUDI_EVENT_NIC_SEI_3 = 267, + GAUDI_EVENT_NIC_SEI_4 = 268, + GAUDI_EVENT_PCIE_FLR = 290, + GAUDI_EVENT_TPC0_BMON_SPMU = 300, + GAUDI_EVENT_TPC0_KRN_ERR = 301, + GAUDI_EVENT_TPC1_BMON_SPMU = 306, + GAUDI_EVENT_TPC1_KRN_ERR = 307, + GAUDI_EVENT_TPC2_BMON_SPMU = 312, + GAUDI_EVENT_TPC2_KRN_ERR = 313, + GAUDI_EVENT_TPC3_BMON_SPMU = 318, + GAUDI_EVENT_TPC3_KRN_ERR = 319, + GAUDI_EVENT_TPC4_BMON_SPMU = 324, + GAUDI_EVENT_TPC4_KRN_ERR = 325, + GAUDI_EVENT_TPC5_BMON_SPMU = 330, + GAUDI_EVENT_TPC5_KRN_ERR = 331, + GAUDI_EVENT_TPC6_BMON_SPMU = 336, + GAUDI_EVENT_TPC6_KRN_ERR = 337, + GAUDI_EVENT_TPC7_BMON_SPMU = 342, + GAUDI_EVENT_TPC7_KRN_ERR = 343, + GAUDI_EVENT_MMU_PAGE_FAULT = 380, + GAUDI_EVENT_MMU_WR_PERM = 381, + GAUDI_EVENT_DMA_BM_CH0 = 383, + GAUDI_EVENT_DMA_BM_CH1 = 384, + GAUDI_EVENT_DMA_BM_CH2 = 385, + GAUDI_EVENT_DMA_BM_CH3 = 386, + GAUDI_EVENT_DMA_BM_CH4 = 387, + GAUDI_EVENT_DMA_BM_CH5 = 388, + GAUDI_EVENT_DMA_BM_CH6 = 389, + GAUDI_EVENT_DMA_BM_CH7 = 390, + GAUDI_EVENT_HBM0_SPI_0 = 395, + GAUDI_EVENT_HBM0_SPI_1 = 396, + GAUDI_EVENT_HBM1_SPI_0 = 399, + GAUDI_EVENT_HBM1_SPI_1 = 400, + GAUDI_EVENT_HBM2_SPI_0 = 403, + GAUDI_EVENT_HBM2_SPI_1 = 404, + GAUDI_EVENT_HBM3_SPI_0 = 407, + GAUDI_EVENT_HBM3_SPI_1 = 408, + GAUDI_EVENT_PSOC_GPIO_U16_0 = 421, + GAUDI_EVENT_PI_UPDATE = 484, + GAUDI_EVENT_HALT_MACHINE = 485, + GAUDI_EVENT_INTS_REGISTER = 486, + GAUDI_EVENT_SOFT_RESET = 487, + GAUDI_EVENT_RAZWI_OR_ADC = 548, + GAUDI_EVENT_TPC0_QM = 572, + GAUDI_EVENT_TPC1_QM = 573, + GAUDI_EVENT_TPC2_QM = 574, + GAUDI_EVENT_TPC3_QM = 575, + GAUDI_EVENT_TPC4_QM = 576, + GAUDI_EVENT_TPC5_QM = 577, + GAUDI_EVENT_TPC6_QM = 578, + GAUDI_EVENT_TPC7_QM = 579, + GAUDI_EVENT_MME0_QM = 581, + GAUDI_EVENT_MME2_QM = 582, + GAUDI_EVENT_DMA0_QM = 583, + GAUDI_EVENT_DMA1_QM = 584, + GAUDI_EVENT_DMA2_QM = 585, + GAUDI_EVENT_DMA3_QM = 586, + GAUDI_EVENT_DMA4_QM = 587, + GAUDI_EVENT_DMA5_QM = 588, + GAUDI_EVENT_DMA6_QM = 589, + GAUDI_EVENT_DMA7_QM = 590, + GAUDI_EVENT_NIC0_QM0 = 594, + GAUDI_EVENT_NIC0_QM1 = 595, + GAUDI_EVENT_NIC1_QM0 = 596, + GAUDI_EVENT_NIC1_QM1 = 597, + GAUDI_EVENT_NIC2_QM0 = 598, + GAUDI_EVENT_NIC2_QM1 = 599, + GAUDI_EVENT_NIC3_QM0 = 600, + GAUDI_EVENT_NIC3_QM1 = 601, + GAUDI_EVENT_NIC4_QM0 = 602, + GAUDI_EVENT_NIC4_QM1 = 603, + GAUDI_EVENT_DMA0_CORE = 604, + GAUDI_EVENT_DMA1_CORE = 605, + GAUDI_EVENT_DMA2_CORE = 606, + GAUDI_EVENT_DMA3_CORE = 607, + GAUDI_EVENT_DMA4_CORE = 608, + GAUDI_EVENT_DMA5_CORE = 609, + GAUDI_EVENT_DMA6_CORE = 610, + GAUDI_EVENT_DMA7_CORE = 611, + GAUDI_EVENT_NIC0_QP0 = 612, + GAUDI_EVENT_NIC0_QP1 = 613, + GAUDI_EVENT_NIC1_QP0 = 614, + GAUDI_EVENT_NIC1_QP1 = 615, + GAUDI_EVENT_NIC2_QP0 = 616, + GAUDI_EVENT_NIC2_QP1 = 617, + GAUDI_EVENT_NIC3_QP0 = 618, + GAUDI_EVENT_NIC3_QP1 = 619, + GAUDI_EVENT_NIC4_QP0 = 620, + GAUDI_EVENT_NIC4_QP1 = 621, + GAUDI_EVENT_FIX_POWER_ENV_S = 658, + GAUDI_EVENT_FIX_POWER_ENV_E = 659, + GAUDI_EVENT_FIX_THERMAL_ENV_S = 660, + GAUDI_EVENT_FIX_THERMAL_ENV_E = 661, + GAUDI_EVENT_RAZWI_OR_ADC_SW = 662, + GAUDI_EVENT_SIZE, +}; + +#endif /* __GAUDI_ASYNC_EVENTS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/gaudi_async_ids_map_extended.h b/drivers/misc/habanalabs/include/gaudi/gaudi_async_ids_map_extended.h new file mode 100644 index 000000000000..737176ba06fb --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/gaudi_async_ids_map_extended.h @@ -0,0 +1,694 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2018-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef __GAUDI_ASYNC_IDS_MAP_EVENTS_EXT_H_ +#define __GAUDI_ASYNC_IDS_MAP_EVENTS_EXT_H_ + +struct gaudi_async_events_ids_map { + int fc_id; + int cpu_id; + int valid; + char name[64]; +}; + +static struct gaudi_async_events_ids_map gaudi_irq_map_table[] = { + { .fc_id = 0, .cpu_id = 0, .valid = 0, .name = "" }, + { .fc_id = 1, .cpu_id = 1, .valid = 0, .name = "" }, + { .fc_id = 2, .cpu_id = 2, .valid = 0, .name = "" }, + { .fc_id = 3, .cpu_id = 3, .valid = 0, .name = "" }, + { .fc_id = 4, .cpu_id = 4, .valid = 0, .name = "" }, + { .fc_id = 5, .cpu_id = 5, .valid = 0, .name = "" }, + { .fc_id = 6, .cpu_id = 6, .valid = 0, .name = "" }, + { .fc_id = 7, .cpu_id = 7, .valid = 0, .name = "" }, + { .fc_id = 8, .cpu_id = 8, .valid = 0, .name = "" }, + { .fc_id = 9, .cpu_id = 9, .valid = 0, .name = "" }, + { .fc_id = 10, .cpu_id = 10, .valid = 0, .name = "" }, + { .fc_id = 11, .cpu_id = 11, .valid = 0, .name = "" }, + { .fc_id = 12, .cpu_id = 12, .valid = 0, .name = "" }, + { .fc_id = 13, .cpu_id = 13, .valid = 0, .name = "" }, + { .fc_id = 14, .cpu_id = 14, .valid = 0, .name = "" }, + { .fc_id = 15, .cpu_id = 15, .valid = 0, .name = "" }, + { .fc_id = 16, .cpu_id = 16, .valid = 0, .name = "" }, + { .fc_id = 17, .cpu_id = 17, .valid = 0, .name = "" }, + { .fc_id = 18, .cpu_id = 18, .valid = 0, .name = "" }, + { .fc_id = 19, .cpu_id = 19, .valid = 0, .name = "" }, + { .fc_id = 20, .cpu_id = 20, .valid = 0, .name = "" }, + { .fc_id = 21, .cpu_id = 21, .valid = 0, .name = "" }, + { .fc_id = 22, .cpu_id = 22, .valid = 0, .name = "" }, + { .fc_id = 23, .cpu_id = 23, .valid = 0, .name = "" }, + { .fc_id = 24, .cpu_id = 24, .valid = 0, .name = "" }, + { .fc_id = 25, .cpu_id = 25, .valid = 0, .name = "" }, + { .fc_id = 26, .cpu_id = 26, .valid = 0, .name = "" }, + { .fc_id = 27, .cpu_id = 27, .valid = 0, .name = "" }, + { .fc_id = 28, .cpu_id = 28, .valid = 0, .name = "" }, + { .fc_id = 29, .cpu_id = 29, .valid = 0, .name = "" }, + { .fc_id = 30, .cpu_id = 30, .valid = 0, .name = "" }, + { .fc_id = 31, .cpu_id = 31, .valid = 0, .name = "" }, + { .fc_id = 32, .cpu_id = 32, .valid = 1, .name = "PCIE_CORE_SERR" }, + { .fc_id = 33, .cpu_id = 33, .valid = 1, .name = "PCIE_CORE_DERR" }, + { .fc_id = 34, .cpu_id = 34, .valid = 1, .name = "PCIE_IF_SERR" }, + { .fc_id = 35, .cpu_id = 35, .valid = 1, .name = "PCIE_IF_DERR" }, + { .fc_id = 36, .cpu_id = 36, .valid = 1, .name = "PCIE_PHY_SERR" }, + { .fc_id = 37, .cpu_id = 37, .valid = 1, .name = "PCIE_PHY_DERR" }, + { .fc_id = 38, .cpu_id = 38, .valid = 1, .name = "TPC0_SERR" }, + { .fc_id = 39, .cpu_id = 38, .valid = 1, .name = "TPC1_SERR" }, + { .fc_id = 40, .cpu_id = 38, .valid = 1, .name = "TPC2_SERR" }, + { .fc_id = 41, .cpu_id = 38, .valid = 1, .name = "TPC3_SERR" }, + { .fc_id = 42, .cpu_id = 38, .valid = 1, .name = "TPC4_SERR" }, + { .fc_id = 43, .cpu_id = 38, .valid = 1, .name = "TPC5_SERR" }, + { .fc_id = 44, .cpu_id = 38, .valid = 1, .name = "TPC6_SERR" }, + { .fc_id = 45, .cpu_id = 38, .valid = 1, .name = "TPC7_SERR" }, + { .fc_id = 46, .cpu_id = 39, .valid = 1, .name = "TPC0_DERR" }, + { .fc_id = 47, .cpu_id = 39, .valid = 1, .name = "TPC1_DERR" }, + { .fc_id = 48, .cpu_id = 39, .valid = 1, .name = "TPC2_DERR" }, + { .fc_id = 49, .cpu_id = 39, .valid = 1, .name = "TPC3_DERR" }, + { .fc_id = 50, .cpu_id = 39, .valid = 1, .name = "TPC4_DERR" }, + { .fc_id = 51, .cpu_id = 39, .valid = 1, .name = "TPC5_DERR" }, + { .fc_id = 52, .cpu_id = 39, .valid = 1, .name = "TPC6_DERR" }, + { .fc_id = 53, .cpu_id = 39, .valid = 1, .name = "TPC7_DERR" }, + { .fc_id = 54, .cpu_id = 40, .valid = 1, .name = "MME0_ACC_SERR" }, + { .fc_id = 55, .cpu_id = 41, .valid = 1, .name = "MME0_ACC_DERR" }, + { .fc_id = 56, .cpu_id = 42, .valid = 1, .name = "MME0_SBAB_SERR" }, + { .fc_id = 57, .cpu_id = 43, .valid = 1, .name = "MME0_SBAB_DERR" }, + { .fc_id = 58, .cpu_id = 44, .valid = 1, .name = "MME1_ACC_SERR" }, + { .fc_id = 59, .cpu_id = 45, .valid = 1, .name = "MME1_ACC_DERR" }, + { .fc_id = 60, .cpu_id = 46, .valid = 1, .name = "MME1_SBAB_SERR" }, + { .fc_id = 61, .cpu_id = 47, .valid = 1, .name = "MME1_SBAB_DERR" }, + { .fc_id = 62, .cpu_id = 48, .valid = 1, .name = "MME2_ACC_SERR" }, + { .fc_id = 63, .cpu_id = 49, .valid = 1, .name = "MME2_ACC_DERR" }, + { .fc_id = 64, .cpu_id = 50, .valid = 1, .name = "MME2_SBAB_SERR" }, + { .fc_id = 65, .cpu_id = 51, .valid = 1, .name = "MME2_SBAB_DERR" }, + { .fc_id = 66, .cpu_id = 52, .valid = 1, .name = "MME3_ACC_SERR" }, + { .fc_id = 67, .cpu_id = 53, .valid = 1, .name = "MME3_ACC_DERR" }, + { .fc_id = 68, .cpu_id = 54, .valid = 1, .name = "MME3_SBAB_SERR" }, + { .fc_id = 69, .cpu_id = 55, .valid = 1, .name = "MME3_SBAB_DERR" }, + { .fc_id = 70, .cpu_id = 56, .valid = 1, .name = "DMA0_SERR_ECC" }, + { .fc_id = 71, .cpu_id = 56, .valid = 1, .name = "DMA1_SERR_ECC" }, + { .fc_id = 72, .cpu_id = 56, .valid = 1, .name = "DMA2_SERR_ECC" }, + { .fc_id = 73, .cpu_id = 56, .valid = 1, .name = "DMA3_SERR_ECC" }, + { .fc_id = 74, .cpu_id = 56, .valid = 1, .name = "DMA4_SERR_ECC" }, + { .fc_id = 75, .cpu_id = 56, .valid = 1, .name = "DMA5_SERR_ECC" }, + { .fc_id = 76, .cpu_id = 56, .valid = 1, .name = "DMA6_SERR_ECC" }, + { .fc_id = 77, .cpu_id = 56, .valid = 1, .name = "DMA7_SERR_ECC" }, + { .fc_id = 78, .cpu_id = 57, .valid = 1, .name = "DMA0_DERR_ECC" }, + { .fc_id = 79, .cpu_id = 57, .valid = 1, .name = "DMA1_DERR_ECC" }, + { .fc_id = 80, .cpu_id = 57, .valid = 1, .name = "DMA2_DERR_ECC" }, + { .fc_id = 81, .cpu_id = 57, .valid = 1, .name = "DMA3_DERR_ECC" }, + { .fc_id = 82, .cpu_id = 57, .valid = 1, .name = "DMA4_DERR_ECC" }, + { .fc_id = 83, .cpu_id = 57, .valid = 1, .name = "DMA5_DERR_ECC" }, + { .fc_id = 84, .cpu_id = 57, .valid = 1, .name = "DMA6_DERR_ECC" }, + { .fc_id = 85, .cpu_id = 57, .valid = 1, .name = "DMA7_DERR_ECC" }, + { .fc_id = 86, .cpu_id = 58, .valid = 1, .name = "CPU_IF_ECC_SERR" }, + { .fc_id = 87, .cpu_id = 59, .valid = 1, .name = "CPU_IF_ECC_DERR" }, + { .fc_id = 88, .cpu_id = 60, .valid = 1, .name = "PSOC_MEM_SERR" }, + { .fc_id = 89, .cpu_id = 61, .valid = 1, + .name = "PSOC_CORESIGHT_SERR" }, + { .fc_id = 90, .cpu_id = 62, .valid = 1, .name = "PSOC_MEM_DERR" }, + { .fc_id = 91, .cpu_id = 63, .valid = 1, + .name = "PSOC_CORESIGHT_DERR" }, + { .fc_id = 92, .cpu_id = 64, .valid = 1, .name = "SRAM0_SERR" }, + { .fc_id = 93, .cpu_id = 64, .valid = 1, .name = "SRAM1_SERR" }, + { .fc_id = 94, .cpu_id = 64, .valid = 1, .name = "SRAM2_SERR" }, + { .fc_id = 95, .cpu_id = 64, .valid = 1, .name = "SRAM3_SERR" }, + { .fc_id = 96, .cpu_id = 64, .valid = 1, .name = "SRAM7_SERR" }, + { .fc_id = 97, .cpu_id = 64, .valid = 1, .name = "SRAM6_SERR" }, + { .fc_id = 98, .cpu_id = 64, .valid = 1, .name = "SRAM5_SERR" }, + { .fc_id = 99, .cpu_id = 64, .valid = 1, .name = "SRAM4_SERR" }, + { .fc_id = 100, .cpu_id = 64, .valid = 1, .name = "SRAM8_SERR" }, + { .fc_id = 101, .cpu_id = 64, .valid = 1, .name = "SRAM9_SERR" }, + { .fc_id = 102, .cpu_id = 64, .valid = 1, .name = "SRAM10_SERR" }, + { .fc_id = 103, .cpu_id = 64, .valid = 1, .name = "SRAM11_SERR" }, + { .fc_id = 104, .cpu_id = 64, .valid = 1, .name = "SRAM15_SERR" }, + { .fc_id = 105, .cpu_id = 64, .valid = 1, .name = "SRAM14_SERR" }, + { .fc_id = 106, .cpu_id = 64, .valid = 1, .name = "SRAM13_SERR" }, + { .fc_id = 107, .cpu_id = 64, .valid = 1, .name = "SRAM12_SERR" }, + { .fc_id = 108, .cpu_id = 64, .valid = 1, .name = "SRAM16_SERR" }, + { .fc_id = 109, .cpu_id = 64, .valid = 1, .name = "SRAM17_SERR" }, + { .fc_id = 110, .cpu_id = 64, .valid = 1, .name = "SRAM18_SERR" }, + { .fc_id = 111, .cpu_id = 64, .valid = 1, .name = "SRAM19_SERR" }, + { .fc_id = 112, .cpu_id = 64, .valid = 1, .name = "SRAM23_SERR" }, + { .fc_id = 113, .cpu_id = 64, .valid = 1, .name = "SRAM22_SERR" }, + { .fc_id = 114, .cpu_id = 64, .valid = 1, .name = "SRAM21_SERR" }, + { .fc_id = 115, .cpu_id = 64, .valid = 1, .name = "SRAM20_SERR" }, + { .fc_id = 116, .cpu_id = 64, .valid = 1, .name = "SRAM24_SERR" }, + { .fc_id = 117, .cpu_id = 64, .valid = 1, .name = "SRAM25_SERR" }, + { .fc_id = 118, .cpu_id = 64, .valid = 1, .name = "SRAM26_SERR" }, + { .fc_id = 119, .cpu_id = 64, .valid = 1, .name = "SRAM27_SERR" }, + { .fc_id = 120, .cpu_id = 64, .valid = 1, .name = "SRAM31_SERR" }, + { .fc_id = 121, .cpu_id = 64, .valid = 1, .name = "SRAM30_SERR" }, + { .fc_id = 122, .cpu_id = 64, .valid = 1, .name = "SRAM29_SERR" }, + { .fc_id = 123, .cpu_id = 64, .valid = 1, .name = "SRAM28_SERR" }, + { .fc_id = 124, .cpu_id = 65, .valid = 1, .name = "SRAM0_DERR" }, + { .fc_id = 125, .cpu_id = 65, .valid = 1, .name = "SRAM1_DERR" }, + { .fc_id = 126, .cpu_id = 65, .valid = 1, .name = "SRAM2_DERR" }, + { .fc_id = 127, .cpu_id = 65, .valid = 1, .name = "SRAM3_DERR" }, + { .fc_id = 128, .cpu_id = 65, .valid = 1, .name = "SRAM7_DERR" }, + { .fc_id = 129, .cpu_id = 65, .valid = 1, .name = "SRAM6_DERR" }, + { .fc_id = 130, .cpu_id = 65, .valid = 1, .name = "SRAM5_DERR" }, + { .fc_id = 131, .cpu_id = 65, .valid = 1, .name = "SRAM4_DERR" }, + { .fc_id = 132, .cpu_id = 65, .valid = 1, .name = "SRAM8_DERR" }, + { .fc_id = 133, .cpu_id = 65, .valid = 1, .name = "SRAM9_DERR" }, + { .fc_id = 134, .cpu_id = 65, .valid = 1, .name = "SRAM10_DERR" }, + { .fc_id = 135, .cpu_id = 65, .valid = 1, .name = "SRAM11_DERR" }, + { .fc_id = 136, .cpu_id = 65, .valid = 1, .name = "SRAM15_DERR" }, + { .fc_id = 137, .cpu_id = 65, .valid = 1, .name = "SRAM14_DERR" }, + { .fc_id = 138, .cpu_id = 65, .valid = 1, .name = "SRAM13_DERR" }, + { .fc_id = 139, .cpu_id = 65, .valid = 1, .name = "SRAM12_DERR" }, + { .fc_id = 140, .cpu_id = 65, .valid = 1, .name = "SRAM16_DERR" }, + { .fc_id = 141, .cpu_id = 65, .valid = 1, .name = "SRAM17_DERR" }, + { .fc_id = 142, .cpu_id = 65, .valid = 1, .name = "SRAM18_DERR" }, + { .fc_id = 143, .cpu_id = 65, .valid = 1, .name = "SRAM19_DERR" }, + { .fc_id = 144, .cpu_id = 65, .valid = 1, .name = "SRAM23_DERR" }, + { .fc_id = 145, .cpu_id = 65, .valid = 1, .name = "SRAM22_DERR" }, + { .fc_id = 146, .cpu_id = 65, .valid = 1, .name = "SRAM21_DERR" }, + { .fc_id = 147, .cpu_id = 65, .valid = 1, .name = "SRAM20_DERR" }, + { .fc_id = 148, .cpu_id = 65, .valid = 1, .name = "SRAM24_DERR" }, + { .fc_id = 149, .cpu_id = 65, .valid = 1, .name = "SRAM25_DERR" }, + { .fc_id = 150, .cpu_id = 65, .valid = 1, .name = "SRAM26_DERR" }, + { .fc_id = 151, .cpu_id = 65, .valid = 1, .name = "SRAM27_DERR" }, + { .fc_id = 152, .cpu_id = 65, .valid = 1, .name = "SRAM31_DERR" }, + { .fc_id = 153, .cpu_id = 65, .valid = 1, .name = "SRAM30_DERR" }, + { .fc_id = 154, .cpu_id = 65, .valid = 1, .name = "SRAM29_DERR" }, + { .fc_id = 155, .cpu_id = 65, .valid = 1, .name = "SRAM28_DERR" }, + { .fc_id = 156, .cpu_id = 66, .valid = 1, .name = "NIC0_SERR" }, + { .fc_id = 157, .cpu_id = 66, .valid = 1, .name = "NIC1_SERR" }, + { .fc_id = 158, .cpu_id = 66, .valid = 1, .name = "NIC2_SERR" }, + { .fc_id = 159, .cpu_id = 66, .valid = 1, .name = "NIC3_SERR" }, + { .fc_id = 160, .cpu_id = 66, .valid = 1, .name = "NIC4_SERR" }, + { .fc_id = 161, .cpu_id = 66, .valid = 0, .name = "" }, + { .fc_id = 162, .cpu_id = 66, .valid = 0, .name = "" }, + { .fc_id = 163, .cpu_id = 66, .valid = 0, .name = "" }, + { .fc_id = 164, .cpu_id = 66, .valid = 0, .name = "" }, + { .fc_id = 165, .cpu_id = 66, .valid = 0, .name = "" }, + { .fc_id = 166, .cpu_id = 67, .valid = 1, .name = "NIC0_DERR" }, + { .fc_id = 167, .cpu_id = 67, .valid = 1, .name = "NIC1_DERR" }, + { .fc_id = 168, .cpu_id = 67, .valid = 1, .name = "NIC2_DERR" }, + { .fc_id = 169, .cpu_id = 67, .valid = 1, .name = "NIC3_DERR" }, + { .fc_id = 170, .cpu_id = 67, .valid = 1, .name = "NIC4_DERR" }, + { .fc_id = 171, .cpu_id = 67, .valid = 0, .name = "" }, + { .fc_id = 172, .cpu_id = 67, .valid = 0, .name = "" }, + { .fc_id = 173, .cpu_id = 67, .valid = 0, .name = "" }, + { .fc_id = 174, .cpu_id = 67, .valid = 0, .name = "" }, + { .fc_id = 175, .cpu_id = 67, .valid = 0, .name = "" }, + { .fc_id = 176, .cpu_id = 68, .valid = 1, .name = "DMA_IF0_SERR" }, + { .fc_id = 177, .cpu_id = 68, .valid = 1, .name = "DMA_IF1_SERR" }, + { .fc_id = 178, .cpu_id = 68, .valid = 1, .name = "DMA_IF2_SERR" }, + { .fc_id = 179, .cpu_id = 68, .valid = 1, .name = "DMA_IF3_SERR" }, + { .fc_id = 180, .cpu_id = 69, .valid = 1, .name = "DMA_IF0_DERR" }, + { .fc_id = 181, .cpu_id = 69, .valid = 1, .name = "DMA_IF1_DERR" }, + { .fc_id = 182, .cpu_id = 69, .valid = 1, .name = "DMA_IF2_DERR" }, + { .fc_id = 183, .cpu_id = 69, .valid = 1, .name = "DMA_IF3_DERR" }, + { .fc_id = 184, .cpu_id = 70, .valid = 1, .name = "GIC500" }, + { .fc_id = 185, .cpu_id = 71, .valid = 1, .name = "HBM_0_SERR" }, + { .fc_id = 186, .cpu_id = 71, .valid = 1, .name = "HBM_1_SERR" }, + { .fc_id = 187, .cpu_id = 71, .valid = 1, .name = "HBM_2_SERR" }, + { .fc_id = 188, .cpu_id = 71, .valid = 1, .name = "HBM_3_SERR" }, + { .fc_id = 189, .cpu_id = 72, .valid = 1, .name = "HBM_0_DERR" }, + { .fc_id = 190, .cpu_id = 72, .valid = 1, .name = "HBM_1_DERR" }, + { .fc_id = 191, .cpu_id = 72, .valid = 1, .name = "HBM_2_DERR" }, + { .fc_id = 192, .cpu_id = 72, .valid = 1, .name = "HBM_3_DERR" }, + { .fc_id = 193, .cpu_id = 73, .valid = 1, .name = "MMU_SERR" }, + { .fc_id = 194, .cpu_id = 74, .valid = 1, .name = "MMU_DERR" }, + { .fc_id = 195, .cpu_id = 75, .valid = 0, .name = "" }, + { .fc_id = 196, .cpu_id = 76, .valid = 0, .name = "" }, + { .fc_id = 197, .cpu_id = 77, .valid = 0, .name = "" }, + { .fc_id = 198, .cpu_id = 78, .valid = 0, .name = "" }, + { .fc_id = 199, .cpu_id = 79, .valid = 0, .name = "" }, + { .fc_id = 200, .cpu_id = 80, .valid = 1, .name = "PCIE_DEC" }, + { .fc_id = 201, .cpu_id = 81, .valid = 1, .name = "TPC0_DEC" }, + { .fc_id = 202, .cpu_id = 82, .valid = 0, .name = "" }, + { .fc_id = 203, .cpu_id = 83, .valid = 1, .name = "TPC1_DEC" }, + { .fc_id = 204, .cpu_id = 84, .valid = 0, .name = "" }, + { .fc_id = 205, .cpu_id = 85, .valid = 1, .name = "TPC2_DEC" }, + { .fc_id = 206, .cpu_id = 86, .valid = 0, .name = "" }, + { .fc_id = 207, .cpu_id = 87, .valid = 1, .name = "TPC3_DEC" }, + { .fc_id = 208, .cpu_id = 88, .valid = 0, .name = "" }, + { .fc_id = 209, .cpu_id = 89, .valid = 1, .name = "TPC4_DEC" }, + { .fc_id = 210, .cpu_id = 90, .valid = 0, .name = "" }, + { .fc_id = 211, .cpu_id = 91, .valid = 1, .name = "TPC5_DEC" }, + { .fc_id = 212, .cpu_id = 92, .valid = 0, .name = "" }, + { .fc_id = 213, .cpu_id = 93, .valid = 1, .name = "TPC6_DEC" }, + { .fc_id = 214, .cpu_id = 94, .valid = 0, .name = "" }, + { .fc_id = 215, .cpu_id = 95, .valid = 1, .name = "TPC7_DEC" }, + { .fc_id = 216, .cpu_id = 96, .valid = 0, .name = "" }, + { .fc_id = 217, .cpu_id = 97, .valid = 1, .name = "AXI_ECC" }, + { .fc_id = 218, .cpu_id = 98, .valid = 1, .name = "L2_RAM_ECC" }, + { .fc_id = 219, .cpu_id = 99, .valid = 1, .name = "MME0_WBC_RSP" }, + { .fc_id = 220, .cpu_id = 100, .valid = 1, .name = "MME0_SBAB0_RSP" }, + { .fc_id = 221, .cpu_id = 101, .valid = 0, .name = "" }, + { .fc_id = 222, .cpu_id = 102, .valid = 0, .name = "" }, + { .fc_id = 223, .cpu_id = 103, .valid = 0, .name = "" }, + { .fc_id = 224, .cpu_id = 104, .valid = 1, .name = "MME1_WBC_RSP" }, + { .fc_id = 225, .cpu_id = 105, .valid = 1, .name = "MME1_SBAB0_RSP" }, + { .fc_id = 226, .cpu_id = 106, .valid = 0, .name = "" }, + { .fc_id = 227, .cpu_id = 107, .valid = 0, .name = "" }, + { .fc_id = 228, .cpu_id = 108, .valid = 0, .name = "" }, + { .fc_id = 229, .cpu_id = 109, .valid = 1, .name = "MME2_WBC_RSP" }, + { .fc_id = 230, .cpu_id = 110, .valid = 1, .name = "MME2_SBAB0_RSP" }, + { .fc_id = 231, .cpu_id = 111, .valid = 0, .name = "" }, + { .fc_id = 232, .cpu_id = 112, .valid = 0, .name = "" }, + { .fc_id = 233, .cpu_id = 113, .valid = 0, .name = "" }, + { .fc_id = 234, .cpu_id = 114, .valid = 1, .name = "MME3_WBC_RSP" }, + { .fc_id = 235, .cpu_id = 115, .valid = 1, .name = "MME3_SBAB0_RSP" }, + { .fc_id = 236, .cpu_id = 116, .valid = 0, .name = "" }, + { .fc_id = 237, .cpu_id = 117, .valid = 0, .name = "" }, + { .fc_id = 238, .cpu_id = 118, .valid = 0, .name = "" }, + { .fc_id = 239, .cpu_id = 119, .valid = 1, .name = "PLL0" }, + { .fc_id = 240, .cpu_id = 119, .valid = 1, .name = "PLL1" }, + { .fc_id = 241, .cpu_id = 119, .valid = 1, .name = "PLL2" }, + { .fc_id = 242, .cpu_id = 119, .valid = 1, .name = "PLL3" }, + { .fc_id = 243, .cpu_id = 119, .valid = 1, .name = "PLL4" }, + { .fc_id = 244, .cpu_id = 119, .valid = 1, .name = "PLL5" }, + { .fc_id = 245, .cpu_id = 119, .valid = 1, .name = "PLL6" }, + { .fc_id = 246, .cpu_id = 119, .valid = 1, .name = "PLL7" }, + { .fc_id = 247, .cpu_id = 119, .valid = 1, .name = "PLL8" }, + { .fc_id = 248, .cpu_id = 119, .valid = 1, .name = "PLL9" }, + { .fc_id = 249, .cpu_id = 119, .valid = 1, .name = "PLL10" }, + { .fc_id = 250, .cpu_id = 119, .valid = 1, .name = "PLL11" }, + { .fc_id = 251, .cpu_id = 119, .valid = 1, .name = "PLL12" }, + { .fc_id = 252, .cpu_id = 119, .valid = 1, .name = "PLL13" }, + { .fc_id = 253, .cpu_id = 119, .valid = 1, .name = "PLL14" }, + { .fc_id = 254, .cpu_id = 119, .valid = 1, .name = "PLL15" }, + { .fc_id = 255, .cpu_id = 119, .valid = 1, .name = "PLL16" }, + { .fc_id = 256, .cpu_id = 119, .valid = 1, .name = "PLL17" }, + { .fc_id = 257, .cpu_id = 120, .valid = 1, + .name = "CPU_AXI_SPLITTER" }, + { .fc_id = 258, .cpu_id = 121, .valid = 0, .name = "" }, + { .fc_id = 259, .cpu_id = 122, .valid = 0, .name = "" }, + { .fc_id = 260, .cpu_id = 123, .valid = 0, .name = "" }, + { .fc_id = 261, .cpu_id = 124, .valid = 0, .name = "" }, + { .fc_id = 262, .cpu_id = 125, .valid = 1, .name = "PSOC_AXI_DEC" }, + { .fc_id = 263, .cpu_id = 126, .valid = 1, .name = "PSOC_PRSTN_FALL" }, + { .fc_id = 264, .cpu_id = 127, .valid = 1, .name = "NIC_SEI_0" }, + { .fc_id = 265, .cpu_id = 127, .valid = 1, .name = "NIC_SEI_1" }, + { .fc_id = 266, .cpu_id = 127, .valid = 1, .name = "NIC_SEI_2" }, + { .fc_id = 267, .cpu_id = 127, .valid = 1, .name = "NIC_SEI_3" }, + { .fc_id = 268, .cpu_id = 127, .valid = 1, .name = "NIC_SEI_4" }, + { .fc_id = 269, .cpu_id = 128, .valid = 0, .name = "" }, + { .fc_id = 270, .cpu_id = 128, .valid = 0, .name = "" }, + { .fc_id = 271, .cpu_id = 128, .valid = 0, .name = "" }, + { .fc_id = 272, .cpu_id = 128, .valid = 0, .name = "" }, + { .fc_id = 273, .cpu_id = 128, .valid = 0, .name = "" }, + { .fc_id = 274, .cpu_id = 128, .valid = 0, .name = "" }, + { .fc_id = 275, .cpu_id = 128, .valid = 0, .name = "" }, + { .fc_id = 276, .cpu_id = 128, .valid = 0, .name = "" }, + { .fc_id = 277, .cpu_id = 129, .valid = 0, .name = "" }, + { .fc_id = 278, .cpu_id = 129, .valid = 0, .name = "" }, + { .fc_id = 279, .cpu_id = 129, .valid = 0, .name = "" }, + { .fc_id = 280, .cpu_id = 129, .valid = 0, .name = "" }, + { .fc_id = 281, .cpu_id = 130, .valid = 0, .name = "" }, + { .fc_id = 282, .cpu_id = 131, .valid = 0, .name = "" }, + { .fc_id = 283, .cpu_id = 132, .valid = 0, .name = "" }, + { .fc_id = 284, .cpu_id = 133, .valid = 0, .name = "" }, + { .fc_id = 285, .cpu_id = 134, .valid = 0, .name = "" }, + { .fc_id = 286, .cpu_id = 135, .valid = 0, .name = "" }, + { .fc_id = 287, .cpu_id = 136, .valid = 0, .name = "" }, + { .fc_id = 288, .cpu_id = 137, .valid = 0, .name = "" }, + { .fc_id = 289, .cpu_id = 138, .valid = 0, .name = "" }, + { .fc_id = 290, .cpu_id = 139, .valid = 1, .name = "PCIE_FLR" }, + { .fc_id = 291, .cpu_id = 140, .valid = 0, .name = "" }, + { .fc_id = 292, .cpu_id = 141, .valid = 0, .name = "" }, + { .fc_id = 293, .cpu_id = 142, .valid = 0, .name = "" }, + { .fc_id = 294, .cpu_id = 143, .valid = 0, .name = "" }, + { .fc_id = 295, .cpu_id = 144, .valid = 0, .name = "" }, + { .fc_id = 296, .cpu_id = 145, .valid = 0, .name = "" }, + { .fc_id = 297, .cpu_id = 146, .valid = 0, .name = "" }, + { .fc_id = 298, .cpu_id = 147, .valid = 0, .name = "" }, + { .fc_id = 299, .cpu_id = 148, .valid = 0, .name = "" }, + { .fc_id = 300, .cpu_id = 149, .valid = 1, .name = "TPC0_BMON_SPMU" }, + { .fc_id = 301, .cpu_id = 150, .valid = 1, .name = "TPC0_KRN_ERR" }, + { .fc_id = 302, .cpu_id = 151, .valid = 0, .name = "" }, + { .fc_id = 303, .cpu_id = 152, .valid = 0, .name = "" }, + { .fc_id = 304, .cpu_id = 153, .valid = 0, .name = "" }, + { .fc_id = 305, .cpu_id = 154, .valid = 0, .name = "" }, + { .fc_id = 306, .cpu_id = 155, .valid = 1, .name = "TPC1_BMON_SPMU" }, + { .fc_id = 307, .cpu_id = 156, .valid = 1, .name = "TPC1_KRN_ERR" }, + { .fc_id = 308, .cpu_id = 157, .valid = 0, .name = "" }, + { .fc_id = 309, .cpu_id = 158, .valid = 0, .name = "" }, + { .fc_id = 310, .cpu_id = 159, .valid = 0, .name = "" }, + { .fc_id = 311, .cpu_id = 160, .valid = 0, .name = "" }, + { .fc_id = 312, .cpu_id = 161, .valid = 1, .name = "TPC2_BMON_SPMU" }, + { .fc_id = 313, .cpu_id = 162, .valid = 1, .name = "TPC2_KRN_ERR" }, + { .fc_id = 314, .cpu_id = 163, .valid = 0, .name = "" }, + { .fc_id = 315, .cpu_id = 164, .valid = 0, .name = "" }, + { .fc_id = 316, .cpu_id = 165, .valid = 0, .name = "" }, + { .fc_id = 317, .cpu_id = 166, .valid = 0, .name = "" }, + { .fc_id = 318, .cpu_id = 167, .valid = 1, .name = "TPC3_BMON_SPMU" }, + { .fc_id = 319, .cpu_id = 168, .valid = 1, .name = "TPC3_KRN_ERR" }, + { .fc_id = 320, .cpu_id = 169, .valid = 0, .name = "" }, + { .fc_id = 321, .cpu_id = 170, .valid = 0, .name = "" }, + { .fc_id = 322, .cpu_id = 171, .valid = 0, .name = "" }, + { .fc_id = 323, .cpu_id = 172, .valid = 0, .name = "" }, + { .fc_id = 324, .cpu_id = 173, .valid = 1, .name = "TPC4_BMON_SPMU" }, + { .fc_id = 325, .cpu_id = 174, .valid = 1, .name = "TPC4_KRN_ERR" }, + { .fc_id = 326, .cpu_id = 175, .valid = 0, .name = "" }, + { .fc_id = 327, .cpu_id = 176, .valid = 0, .name = "" }, + { .fc_id = 328, .cpu_id = 177, .valid = 0, .name = "" }, + { .fc_id = 329, .cpu_id = 178, .valid = 0, .name = "" }, + { .fc_id = 330, .cpu_id = 179, .valid = 1, .name = "TPC5_BMON_SPMU" }, + { .fc_id = 331, .cpu_id = 180, .valid = 1, .name = "TPC5_KRN_ERR" }, + { .fc_id = 332, .cpu_id = 181, .valid = 0, .name = "" }, + { .fc_id = 333, .cpu_id = 182, .valid = 0, .name = "" }, + { .fc_id = 334, .cpu_id = 183, .valid = 0, .name = "" }, + { .fc_id = 335, .cpu_id = 184, .valid = 0, .name = "" }, + { .fc_id = 336, .cpu_id = 185, .valid = 1, .name = "TPC6_BMON_SPMU" }, + { .fc_id = 337, .cpu_id = 186, .valid = 1, .name = "TPC6_KRN_ERR" }, + { .fc_id = 338, .cpu_id = 187, .valid = 0, .name = "" }, + { .fc_id = 339, .cpu_id = 188, .valid = 0, .name = "" }, + { .fc_id = 340, .cpu_id = 189, .valid = 0, .name = "" }, + { .fc_id = 341, .cpu_id = 190, .valid = 0, .name = "" }, + { .fc_id = 342, .cpu_id = 191, .valid = 1, .name = "TPC7_BMON_SPMU" }, + { .fc_id = 343, .cpu_id = 192, .valid = 1, .name = "TPC7_KRN_ERR" }, + { .fc_id = 344, .cpu_id = 193, .valid = 0, .name = "" }, + { .fc_id = 345, .cpu_id = 194, .valid = 0, .name = "" }, + { .fc_id = 346, .cpu_id = 195, .valid = 0, .name = "" }, + { .fc_id = 347, .cpu_id = 196, .valid = 0, .name = "" }, + { .fc_id = 348, .cpu_id = 197, .valid = 0, .name = "" }, + { .fc_id = 349, .cpu_id = 198, .valid = 0, .name = "" }, + { .fc_id = 350, .cpu_id = 199, .valid = 0, .name = "" }, + { .fc_id = 351, .cpu_id = 200, .valid = 0, .name = "" }, + { .fc_id = 352, .cpu_id = 201, .valid = 0, .name = "" }, + { .fc_id = 353, .cpu_id = 202, .valid = 0, .name = "" }, + { .fc_id = 354, .cpu_id = 203, .valid = 0, .name = "" }, + { .fc_id = 355, .cpu_id = 204, .valid = 0, .name = "" }, + { .fc_id = 356, .cpu_id = 205, .valid = 0, .name = "" }, + { .fc_id = 357, .cpu_id = 206, .valid = 0, .name = "" }, + { .fc_id = 358, .cpu_id = 207, .valid = 0, .name = "" }, + { .fc_id = 359, .cpu_id = 208, .valid = 0, .name = "" }, + { .fc_id = 360, .cpu_id = 209, .valid = 0, .name = "" }, + { .fc_id = 361, .cpu_id = 210, .valid = 0, .name = "" }, + { .fc_id = 362, .cpu_id = 211, .valid = 0, .name = "" }, + { .fc_id = 363, .cpu_id = 212, .valid = 0, .name = "" }, + { .fc_id = 364, .cpu_id = 213, .valid = 0, .name = "" }, + { .fc_id = 365, .cpu_id = 214, .valid = 0, .name = "" }, + { .fc_id = 366, .cpu_id = 215, .valid = 0, .name = "" }, + { .fc_id = 367, .cpu_id = 216, .valid = 0, .name = "" }, + { .fc_id = 368, .cpu_id = 217, .valid = 0, .name = "" }, + { .fc_id = 369, .cpu_id = 218, .valid = 0, .name = "" }, + { .fc_id = 370, .cpu_id = 219, .valid = 0, .name = "" }, + { .fc_id = 371, .cpu_id = 220, .valid = 0, .name = "" }, + { .fc_id = 372, .cpu_id = 221, .valid = 0, .name = "" }, + { .fc_id = 373, .cpu_id = 222, .valid = 0, .name = "" }, + { .fc_id = 374, .cpu_id = 223, .valid = 0, .name = "" }, + { .fc_id = 375, .cpu_id = 224, .valid = 0, .name = "" }, + { .fc_id = 376, .cpu_id = 225, .valid = 0, .name = "" }, + { .fc_id = 377, .cpu_id = 226, .valid = 0, .name = "" }, + { .fc_id = 378, .cpu_id = 227, .valid = 0, .name = "" }, + { .fc_id = 379, .cpu_id = 228, .valid = 0, .name = "" }, + { .fc_id = 380, .cpu_id = 229, .valid = 1, .name = "MMU_PAGE_FAULT" }, + { .fc_id = 381, .cpu_id = 230, .valid = 1, .name = "MMU_WR_PERM" }, + { .fc_id = 382, .cpu_id = 231, .valid = 0, .name = "" }, + { .fc_id = 383, .cpu_id = 232, .valid = 1, .name = "DMA_BM_CH0" }, + { .fc_id = 384, .cpu_id = 233, .valid = 1, .name = "DMA_BM_CH1" }, + { .fc_id = 385, .cpu_id = 234, .valid = 1, .name = "DMA_BM_CH2" }, + { .fc_id = 386, .cpu_id = 235, .valid = 1, .name = "DMA_BM_CH3" }, + { .fc_id = 387, .cpu_id = 236, .valid = 1, .name = "DMA_BM_CH4" }, + { .fc_id = 388, .cpu_id = 237, .valid = 1, .name = "DMA_BM_CH5" }, + { .fc_id = 389, .cpu_id = 238, .valid = 1, .name = "DMA_BM_CH6" }, + { .fc_id = 390, .cpu_id = 239, .valid = 1, .name = "DMA_BM_CH7" }, + { .fc_id = 391, .cpu_id = 240, .valid = 0, .name = "" }, + { .fc_id = 392, .cpu_id = 241, .valid = 0, .name = "" }, + { .fc_id = 393, .cpu_id = 242, .valid = 0, .name = "" }, + { .fc_id = 394, .cpu_id = 243, .valid = 0, .name = "" }, + { .fc_id = 395, .cpu_id = 244, .valid = 1, .name = "HBM0_SPI_0" }, + { .fc_id = 396, .cpu_id = 245, .valid = 1, .name = "HBM0_SPI_1" }, + { .fc_id = 397, .cpu_id = 246, .valid = 0, .name = "" }, + { .fc_id = 398, .cpu_id = 247, .valid = 0, .name = "" }, + { .fc_id = 399, .cpu_id = 248, .valid = 1, .name = "HBM1_SPI_0" }, + { .fc_id = 400, .cpu_id = 249, .valid = 1, .name = "HBM1_SPI_1" }, + { .fc_id = 401, .cpu_id = 250, .valid = 0, .name = "" }, + { .fc_id = 402, .cpu_id = 251, .valid = 0, .name = "" }, + { .fc_id = 403, .cpu_id = 252, .valid = 1, .name = "HBM2_SPI_0" }, + { .fc_id = 404, .cpu_id = 253, .valid = 1, .name = "HBM2_SPI_1" }, + { .fc_id = 405, .cpu_id = 254, .valid = 0, .name = "" }, + { .fc_id = 406, .cpu_id = 255, .valid = 0, .name = "" }, + { .fc_id = 407, .cpu_id = 256, .valid = 1, .name = "HBM3_SPI_0" }, + { .fc_id = 408, .cpu_id = 257, .valid = 1, .name = "HBM3_SPI_1" }, + { .fc_id = 409, .cpu_id = 258, .valid = 0, .name = "" }, + { .fc_id = 410, .cpu_id = 259, .valid = 0, .name = "" }, + { .fc_id = 411, .cpu_id = 260, .valid = 0, .name = "" }, + { .fc_id = 412, .cpu_id = 261, .valid = 0, .name = "" }, + { .fc_id = 413, .cpu_id = 262, .valid = 0, .name = "" }, + { .fc_id = 414, .cpu_id = 263, .valid = 0, .name = "" }, + { .fc_id = 415, .cpu_id = 264, .valid = 0, .name = "" }, + { .fc_id = 416, .cpu_id = 265, .valid = 0, .name = "" }, + { .fc_id = 417, .cpu_id = 266, .valid = 0, .name = "" }, + { .fc_id = 418, .cpu_id = 267, .valid = 0, .name = "" }, + { .fc_id = 419, .cpu_id = 268, .valid = 0, .name = "" }, + { .fc_id = 420, .cpu_id = 269, .valid = 0, .name = "" }, + { .fc_id = 421, .cpu_id = 270, .valid = 1, .name = "PSOC_GPIO_U16_0" }, + { .fc_id = 422, .cpu_id = 271, .valid = 0, .name = "" }, + { .fc_id = 423, .cpu_id = 272, .valid = 0, .name = "" }, + { .fc_id = 424, .cpu_id = 273, .valid = 0, .name = "" }, + { .fc_id = 425, .cpu_id = 274, .valid = 0, .name = "" }, + { .fc_id = 426, .cpu_id = 275, .valid = 0, .name = "" }, + { .fc_id = 427, .cpu_id = 276, .valid = 0, .name = "" }, + { .fc_id = 428, .cpu_id = 277, .valid = 0, .name = "" }, + { .fc_id = 429, .cpu_id = 278, .valid = 0, .name = "" }, + { .fc_id = 430, .cpu_id = 279, .valid = 0, .name = "" }, + { .fc_id = 431, .cpu_id = 280, .valid = 0, .name = "" }, + { .fc_id = 432, .cpu_id = 281, .valid = 0, .name = "" }, + { .fc_id = 433, .cpu_id = 282, .valid = 0, .name = "" }, + { .fc_id = 434, .cpu_id = 283, .valid = 0, .name = "" }, + { .fc_id = 435, .cpu_id = 284, .valid = 0, .name = "" }, + { .fc_id = 436, .cpu_id = 285, .valid = 0, .name = "" }, + { .fc_id = 437, .cpu_id = 286, .valid = 0, .name = "" }, + { .fc_id = 438, .cpu_id = 287, .valid = 0, .name = "" }, + { .fc_id = 439, .cpu_id = 288, .valid = 0, .name = "" }, + { .fc_id = 440, .cpu_id = 289, .valid = 0, .name = "" }, + { .fc_id = 441, .cpu_id = 290, .valid = 0, .name = "" }, + { .fc_id = 442, .cpu_id = 291, .valid = 0, .name = "" }, + { .fc_id = 443, .cpu_id = 292, .valid = 0, .name = "" }, + { .fc_id = 444, .cpu_id = 293, .valid = 0, .name = "" }, + { .fc_id = 445, .cpu_id = 294, .valid = 0, .name = "" }, + { .fc_id = 446, .cpu_id = 295, .valid = 0, .name = "" }, + { .fc_id = 447, .cpu_id = 296, .valid = 0, .name = "" }, + { .fc_id = 448, .cpu_id = 297, .valid = 0, .name = "" }, + { .fc_id = 449, .cpu_id = 298, .valid = 0, .name = "" }, + { .fc_id = 450, .cpu_id = 299, .valid = 0, .name = "" }, + { .fc_id = 451, .cpu_id = 300, .valid = 0, .name = "" }, + { .fc_id = 452, .cpu_id = 301, .valid = 0, .name = "" }, + { .fc_id = 453, .cpu_id = 302, .valid = 0, .name = "" }, + { .fc_id = 454, .cpu_id = 303, .valid = 0, .name = "" }, + { .fc_id = 455, .cpu_id = 304, .valid = 0, .name = "" }, + { .fc_id = 456, .cpu_id = 305, .valid = 0, .name = "" }, + { .fc_id = 457, .cpu_id = 306, .valid = 0, .name = "" }, + { .fc_id = 458, .cpu_id = 307, .valid = 0, .name = "" }, + { .fc_id = 459, .cpu_id = 308, .valid = 0, .name = "" }, + { .fc_id = 460, .cpu_id = 309, .valid = 0, .name = "" }, + { .fc_id = 461, .cpu_id = 310, .valid = 0, .name = "" }, + { .fc_id = 462, .cpu_id = 311, .valid = 0, .name = "" }, + { .fc_id = 463, .cpu_id = 312, .valid = 0, .name = "" }, + { .fc_id = 464, .cpu_id = 313, .valid = 0, .name = "" }, + { .fc_id = 465, .cpu_id = 314, .valid = 0, .name = "" }, + { .fc_id = 466, .cpu_id = 315, .valid = 0, .name = "" }, + { .fc_id = 467, .cpu_id = 316, .valid = 0, .name = "" }, + { .fc_id = 468, .cpu_id = 317, .valid = 0, .name = "" }, + { .fc_id = 469, .cpu_id = 318, .valid = 0, .name = "" }, + { .fc_id = 470, .cpu_id = 319, .valid = 0, .name = "" }, + { .fc_id = 471, .cpu_id = 320, .valid = 0, .name = "" }, + { .fc_id = 472, .cpu_id = 321, .valid = 0, .name = "" }, + { .fc_id = 473, .cpu_id = 322, .valid = 0, .name = "" }, + { .fc_id = 474, .cpu_id = 323, .valid = 0, .name = "" }, + { .fc_id = 475, .cpu_id = 324, .valid = 0, .name = "" }, + { .fc_id = 476, .cpu_id = 325, .valid = 0, .name = "" }, + { .fc_id = 477, .cpu_id = 326, .valid = 0, .name = "" }, + { .fc_id = 478, .cpu_id = 327, .valid = 0, .name = "" }, + { .fc_id = 479, .cpu_id = 328, .valid = 0, .name = "" }, + { .fc_id = 480, .cpu_id = 329, .valid = 0, .name = "" }, + { .fc_id = 481, .cpu_id = 330, .valid = 0, .name = "" }, + { .fc_id = 482, .cpu_id = 331, .valid = 0, .name = "" }, + { .fc_id = 483, .cpu_id = 332, .valid = 0, .name = "" }, + { .fc_id = 484, .cpu_id = 333, .valid = 1, .name = "PI_UPDATE" }, + { .fc_id = 485, .cpu_id = 334, .valid = 1, .name = "HALT_MACHINE" }, + { .fc_id = 486, .cpu_id = 335, .valid = 1, .name = "INTS_REGISTER" }, + { .fc_id = 487, .cpu_id = 336, .valid = 1, .name = "SOFT_RESET" }, + { .fc_id = 488, .cpu_id = 337, .valid = 0, .name = "" }, + { .fc_id = 489, .cpu_id = 338, .valid = 0, .name = "" }, + { .fc_id = 490, .cpu_id = 339, .valid = 0, .name = "" }, + { .fc_id = 491, .cpu_id = 340, .valid = 0, .name = "" }, + { .fc_id = 492, .cpu_id = 341, .valid = 0, .name = "" }, + { .fc_id = 493, .cpu_id = 342, .valid = 0, .name = "" }, + { .fc_id = 494, .cpu_id = 343, .valid = 0, .name = "" }, + { .fc_id = 495, .cpu_id = 344, .valid = 0, .name = "" }, + { .fc_id = 496, .cpu_id = 345, .valid = 0, .name = "" }, + { .fc_id = 497, .cpu_id = 346, .valid = 0, .name = "" }, + { .fc_id = 498, .cpu_id = 347, .valid = 0, .name = "" }, + { .fc_id = 499, .cpu_id = 348, .valid = 0, .name = "" }, + { .fc_id = 500, .cpu_id = 349, .valid = 0, .name = "" }, + { .fc_id = 501, .cpu_id = 350, .valid = 0, .name = "" }, + { .fc_id = 502, .cpu_id = 351, .valid = 0, .name = "" }, + { .fc_id = 503, .cpu_id = 352, .valid = 0, .name = "" }, + { .fc_id = 504, .cpu_id = 353, .valid = 0, .name = "" }, + { .fc_id = 505, .cpu_id = 354, .valid = 0, .name = "" }, + { .fc_id = 506, .cpu_id = 355, .valid = 0, .name = "" }, + { .fc_id = 507, .cpu_id = 356, .valid = 0, .name = "" }, + { .fc_id = 508, .cpu_id = 357, .valid = 0, .name = "" }, + { .fc_id = 509, .cpu_id = 358, .valid = 0, .name = "" }, + { .fc_id = 510, .cpu_id = 359, .valid = 0, .name = "" }, + { .fc_id = 511, .cpu_id = 360, .valid = 0, .name = "" }, + { .fc_id = 512, .cpu_id = 361, .valid = 0, .name = "" }, + { .fc_id = 513, .cpu_id = 362, .valid = 0, .name = "" }, + { .fc_id = 514, .cpu_id = 363, .valid = 0, .name = "" }, + { .fc_id = 515, .cpu_id = 364, .valid = 0, .name = "" }, + { .fc_id = 516, .cpu_id = 365, .valid = 0, .name = "" }, + { .fc_id = 517, .cpu_id = 366, .valid = 0, .name = "" }, + { .fc_id = 518, .cpu_id = 367, .valid = 0, .name = "" }, + { .fc_id = 519, .cpu_id = 368, .valid = 0, .name = "" }, + { .fc_id = 520, .cpu_id = 369, .valid = 0, .name = "" }, + { .fc_id = 521, .cpu_id = 370, .valid = 0, .name = "" }, + { .fc_id = 522, .cpu_id = 371, .valid = 0, .name = "" }, + { .fc_id = 523, .cpu_id = 372, .valid = 0, .name = "" }, + { .fc_id = 524, .cpu_id = 373, .valid = 0, .name = "" }, + { .fc_id = 525, .cpu_id = 374, .valid = 0, .name = "" }, + { .fc_id = 526, .cpu_id = 375, .valid = 0, .name = "" }, + { .fc_id = 527, .cpu_id = 376, .valid = 0, .name = "" }, + { .fc_id = 528, .cpu_id = 377, .valid = 0, .name = "" }, + { .fc_id = 529, .cpu_id = 378, .valid = 0, .name = "" }, + { .fc_id = 530, .cpu_id = 379, .valid = 0, .name = "" }, + { .fc_id = 531, .cpu_id = 380, .valid = 0, .name = "" }, + { .fc_id = 532, .cpu_id = 381, .valid = 0, .name = "" }, + { .fc_id = 533, .cpu_id = 382, .valid = 0, .name = "" }, + { .fc_id = 534, .cpu_id = 383, .valid = 0, .name = "" }, + { .fc_id = 535, .cpu_id = 384, .valid = 0, .name = "" }, + { .fc_id = 536, .cpu_id = 385, .valid = 0, .name = "" }, + { .fc_id = 537, .cpu_id = 386, .valid = 0, .name = "" }, + { .fc_id = 538, .cpu_id = 387, .valid = 0, .name = "" }, + { .fc_id = 539, .cpu_id = 388, .valid = 0, .name = "" }, + { .fc_id = 540, .cpu_id = 389, .valid = 0, .name = "" }, + { .fc_id = 541, .cpu_id = 390, .valid = 0, .name = "" }, + { .fc_id = 542, .cpu_id = 391, .valid = 0, .name = "" }, + { .fc_id = 543, .cpu_id = 392, .valid = 0, .name = "" }, + { .fc_id = 544, .cpu_id = 393, .valid = 0, .name = "" }, + { .fc_id = 545, .cpu_id = 394, .valid = 0, .name = "" }, + { .fc_id = 546, .cpu_id = 395, .valid = 0, .name = "" }, + { .fc_id = 547, .cpu_id = 396, .valid = 0, .name = "" }, + { .fc_id = 548, .cpu_id = 397, .valid = 1, .name = "RAZWI_OR_ADC" }, + { .fc_id = 549, .cpu_id = 398, .valid = 0, .name = "" }, + { .fc_id = 550, .cpu_id = 399, .valid = 0, .name = "" }, + { .fc_id = 551, .cpu_id = 400, .valid = 0, .name = "" }, + { .fc_id = 552, .cpu_id = 401, .valid = 0, .name = "" }, + { .fc_id = 553, .cpu_id = 402, .valid = 0, .name = "" }, + { .fc_id = 554, .cpu_id = 403, .valid = 0, .name = "" }, + { .fc_id = 555, .cpu_id = 404, .valid = 0, .name = "" }, + { .fc_id = 556, .cpu_id = 405, .valid = 0, .name = "" }, + { .fc_id = 557, .cpu_id = 406, .valid = 0, .name = "" }, + { .fc_id = 558, .cpu_id = 407, .valid = 0, .name = "" }, + { .fc_id = 559, .cpu_id = 408, .valid = 0, .name = "" }, + { .fc_id = 560, .cpu_id = 409, .valid = 0, .name = "" }, + { .fc_id = 561, .cpu_id = 410, .valid = 0, .name = "" }, + { .fc_id = 562, .cpu_id = 411, .valid = 0, .name = "" }, + { .fc_id = 563, .cpu_id = 412, .valid = 0, .name = "" }, + { .fc_id = 564, .cpu_id = 413, .valid = 0, .name = "" }, + { .fc_id = 565, .cpu_id = 414, .valid = 0, .name = "" }, + { .fc_id = 566, .cpu_id = 415, .valid = 0, .name = "" }, + { .fc_id = 567, .cpu_id = 416, .valid = 0, .name = "" }, + { .fc_id = 568, .cpu_id = 417, .valid = 0, .name = "" }, + { .fc_id = 569, .cpu_id = 418, .valid = 0, .name = "" }, + { .fc_id = 570, .cpu_id = 419, .valid = 0, .name = "" }, + { .fc_id = 571, .cpu_id = 420, .valid = 0, .name = "" }, + { .fc_id = 572, .cpu_id = 421, .valid = 1, .name = "TPC0_QM" }, + { .fc_id = 573, .cpu_id = 422, .valid = 1, .name = "TPC1_QM" }, + { .fc_id = 574, .cpu_id = 423, .valid = 1, .name = "TPC2_QM" }, + { .fc_id = 575, .cpu_id = 424, .valid = 1, .name = "TPC3_QM" }, + { .fc_id = 576, .cpu_id = 425, .valid = 1, .name = "TPC4_QM" }, + { .fc_id = 577, .cpu_id = 426, .valid = 1, .name = "TPC5_QM" }, + { .fc_id = 578, .cpu_id = 427, .valid = 1, .name = "TPC6_QM" }, + { .fc_id = 579, .cpu_id = 428, .valid = 1, .name = "TPC7_QM" }, + { .fc_id = 580, .cpu_id = 429, .valid = 0, .name = "" }, + { .fc_id = 581, .cpu_id = 430, .valid = 1, .name = "MME0_QM" }, + { .fc_id = 582, .cpu_id = 431, .valid = 1, .name = "MME2_QM" }, + { .fc_id = 583, .cpu_id = 432, .valid = 1, .name = "DMA0_QM" }, + { .fc_id = 584, .cpu_id = 433, .valid = 1, .name = "DMA1_QM" }, + { .fc_id = 585, .cpu_id = 434, .valid = 1, .name = "DMA2_QM" }, + { .fc_id = 586, .cpu_id = 435, .valid = 1, .name = "DMA3_QM" }, + { .fc_id = 587, .cpu_id = 436, .valid = 1, .name = "DMA4_QM" }, + { .fc_id = 588, .cpu_id = 437, .valid = 1, .name = "DMA5_QM" }, + { .fc_id = 589, .cpu_id = 438, .valid = 1, .name = "DMA6_QM" }, + { .fc_id = 590, .cpu_id = 439, .valid = 1, .name = "DMA7_QM" }, + { .fc_id = 591, .cpu_id = 440, .valid = 0, .name = "" }, + { .fc_id = 592, .cpu_id = 441, .valid = 0, .name = "" }, + { .fc_id = 593, .cpu_id = 442, .valid = 0, .name = "" }, + { .fc_id = 594, .cpu_id = 443, .valid = 1, .name = "NIC0_QM0" }, + { .fc_id = 595, .cpu_id = 444, .valid = 1, .name = "NIC0_QM1" }, + { .fc_id = 596, .cpu_id = 445, .valid = 1, .name = "NIC1_QM0" }, + { .fc_id = 597, .cpu_id = 446, .valid = 1, .name = "NIC1_QM1" }, + { .fc_id = 598, .cpu_id = 447, .valid = 1, .name = "NIC2_QM0" }, + { .fc_id = 599, .cpu_id = 448, .valid = 1, .name = "NIC2_QM1" }, + { .fc_id = 600, .cpu_id = 449, .valid = 1, .name = "NIC3_QM0" }, + { .fc_id = 601, .cpu_id = 450, .valid = 1, .name = "NIC3_QM1" }, + { .fc_id = 602, .cpu_id = 451, .valid = 1, .name = "NIC4_QM0" }, + { .fc_id = 603, .cpu_id = 452, .valid = 1, .name = "NIC4_QM1" }, + { .fc_id = 604, .cpu_id = 453, .valid = 1, .name = "DMA0_CORE" }, + { .fc_id = 605, .cpu_id = 454, .valid = 1, .name = "DMA1_CORE" }, + { .fc_id = 606, .cpu_id = 455, .valid = 1, .name = "DMA2_CORE" }, + { .fc_id = 607, .cpu_id = 456, .valid = 1, .name = "DMA3_CORE" }, + { .fc_id = 608, .cpu_id = 457, .valid = 1, .name = "DMA4_CORE" }, + { .fc_id = 609, .cpu_id = 458, .valid = 1, .name = "DMA5_CORE" }, + { .fc_id = 610, .cpu_id = 459, .valid = 1, .name = "DMA6_CORE" }, + { .fc_id = 611, .cpu_id = 460, .valid = 1, .name = "DMA7_CORE" }, + { .fc_id = 612, .cpu_id = 461, .valid = 1, .name = "NIC0_QP0" }, + { .fc_id = 613, .cpu_id = 462, .valid = 1, .name = "NIC0_QP1" }, + { .fc_id = 614, .cpu_id = 463, .valid = 1, .name = "NIC1_QP0" }, + { .fc_id = 615, .cpu_id = 464, .valid = 1, .name = "NIC1_QP1" }, + { .fc_id = 616, .cpu_id = 465, .valid = 1, .name = "NIC2_QP0" }, + { .fc_id = 617, .cpu_id = 466, .valid = 1, .name = "NIC2_QP1" }, + { .fc_id = 618, .cpu_id = 467, .valid = 1, .name = "NIC3_QP0" }, + { .fc_id = 619, .cpu_id = 468, .valid = 1, .name = "NIC3_QP1" }, + { .fc_id = 620, .cpu_id = 469, .valid = 1, .name = "NIC4_QP0" }, + { .fc_id = 621, .cpu_id = 470, .valid = 1, .name = "NIC4_QP1" }, + { .fc_id = 622, .cpu_id = 471, .valid = 0, .name = "" }, + { .fc_id = 623, .cpu_id = 472, .valid = 0, .name = "" }, + { .fc_id = 624, .cpu_id = 473, .valid = 0, .name = "" }, + { .fc_id = 625, .cpu_id = 474, .valid = 0, .name = "" }, + { .fc_id = 626, .cpu_id = 475, .valid = 0, .name = "" }, + { .fc_id = 627, .cpu_id = 476, .valid = 0, .name = "" }, + { .fc_id = 628, .cpu_id = 477, .valid = 0, .name = "" }, + { .fc_id = 629, .cpu_id = 478, .valid = 0, .name = "" }, + { .fc_id = 630, .cpu_id = 479, .valid = 0, .name = "" }, + { .fc_id = 631, .cpu_id = 480, .valid = 0, .name = "" }, + { .fc_id = 632, .cpu_id = 481, .valid = 0, .name = "" }, + { .fc_id = 633, .cpu_id = 482, .valid = 0, .name = "" }, + { .fc_id = 634, .cpu_id = 483, .valid = 0, .name = "" }, + { .fc_id = 635, .cpu_id = 484, .valid = 0, .name = "" }, + { .fc_id = 636, .cpu_id = 485, .valid = 0, .name = "" }, + { .fc_id = 637, .cpu_id = 486, .valid = 0, .name = "" }, + { .fc_id = 638, .cpu_id = 487, .valid = 0, .name = "" }, + { .fc_id = 639, .cpu_id = 488, .valid = 0, .name = "" }, + { .fc_id = 640, .cpu_id = 489, .valid = 0, .name = "" }, + { .fc_id = 641, .cpu_id = 490, .valid = 0, .name = "" }, + { .fc_id = 642, .cpu_id = 491, .valid = 0, .name = "" }, + { .fc_id = 643, .cpu_id = 492, .valid = 0, .name = "" }, + { .fc_id = 644, .cpu_id = 493, .valid = 0, .name = "" }, + { .fc_id = 645, .cpu_id = 494, .valid = 0, .name = "" }, + { .fc_id = 646, .cpu_id = 495, .valid = 0, .name = "" }, + { .fc_id = 647, .cpu_id = 496, .valid = 0, .name = "" }, + { .fc_id = 648, .cpu_id = 497, .valid = 0, .name = "" }, + { .fc_id = 649, .cpu_id = 498, .valid = 0, .name = "" }, + { .fc_id = 650, .cpu_id = 499, .valid = 0, .name = "" }, + { .fc_id = 651, .cpu_id = 500, .valid = 0, .name = "" }, + { .fc_id = 652, .cpu_id = 501, .valid = 0, .name = "" }, + { .fc_id = 653, .cpu_id = 502, .valid = 0, .name = "" }, + { .fc_id = 654, .cpu_id = 503, .valid = 0, .name = "" }, + { .fc_id = 655, .cpu_id = 504, .valid = 0, .name = "" }, + { .fc_id = 656, .cpu_id = 505, .valid = 0, .name = "" }, + { .fc_id = 657, .cpu_id = 506, .valid = 0, .name = "" }, + { .fc_id = 658, .cpu_id = 507, .valid = 1, .name = "FIX_POWER_ENV_S" }, + { .fc_id = 659, .cpu_id = 508, .valid = 1, .name = "FIX_POWER_ENV_E" }, + { .fc_id = 660, .cpu_id = 509, .valid = 1, + .name = "FIX_THERMAL_ENV_S" }, + { .fc_id = 661, .cpu_id = 510, .valid = 1, + .name = "FIX_THERMAL_ENV_E" }, + { .fc_id = 662, .cpu_id = 511, .valid = 1, .name = "RAZWI_OR_ADC_SW" }, +}; + +#endif /* __GAUDI_ASYNC_IDS_MAP_EVENTS_EXT_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/gaudi_coresight.h b/drivers/misc/habanalabs/include/gaudi/gaudi_coresight.h new file mode 100644 index 000000000000..c45cc7f4d4d7 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/gaudi_coresight.h @@ -0,0 +1,367 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDI_CORESIGHT_H +#define GAUDI_CORESIGHT_H + +enum gaudi_debug_stm_regs_index { + GAUDI_STM_FIRST = 0, + GAUDI_STM_MME0_ACC = GAUDI_STM_FIRST, + GAUDI_STM_MME0_SBAB, + GAUDI_STM_MME0_CTRL, + GAUDI_STM_MME1_ACC, + GAUDI_STM_MME1_SBAB, + GAUDI_STM_MME1_CTRL, + GAUDI_STM_MME2_ACC, + GAUDI_STM_MME2_SBAB, + GAUDI_STM_MME2_CTRL, + GAUDI_STM_MME3_ACC, + GAUDI_STM_MME3_SBAB, + GAUDI_STM_MME3_CTRL, + GAUDI_STM_DMA_IF_W_S, + GAUDI_STM_DMA_IF_E_S, + GAUDI_STM_DMA_IF_W_N, + GAUDI_STM_DMA_IF_E_N, + GAUDI_STM_CPU, + GAUDI_STM_DMA_CH_0_CS, + GAUDI_STM_DMA_CH_1_CS, + GAUDI_STM_DMA_CH_2_CS, + GAUDI_STM_DMA_CH_3_CS, + GAUDI_STM_DMA_CH_4_CS, + GAUDI_STM_DMA_CH_5_CS, + GAUDI_STM_DMA_CH_6_CS, + GAUDI_STM_DMA_CH_7_CS, + GAUDI_STM_PCIE, + GAUDI_STM_MMU_CS, + GAUDI_STM_PSOC, + GAUDI_STM_NIC0_0, + GAUDI_STM_NIC0_1, + GAUDI_STM_NIC1_0, + GAUDI_STM_NIC1_1, + GAUDI_STM_NIC2_0, + GAUDI_STM_NIC2_1, + GAUDI_STM_NIC3_0, + GAUDI_STM_NIC3_1, + GAUDI_STM_NIC4_0, + GAUDI_STM_NIC4_1, + GAUDI_STM_TPC0_EML, + GAUDI_STM_TPC1_EML, + GAUDI_STM_TPC2_EML, + GAUDI_STM_TPC3_EML, + GAUDI_STM_TPC4_EML, + GAUDI_STM_TPC5_EML, + GAUDI_STM_TPC6_EML, + GAUDI_STM_TPC7_EML, + GAUDI_STM_LAST = GAUDI_STM_TPC7_EML +}; + +enum gaudi_debug_etf_regs_index { + GAUDI_ETF_FIRST = 0, + GAUDI_ETF_MME0_ACC = GAUDI_ETF_FIRST, + GAUDI_ETF_MME0_SBAB, + GAUDI_ETF_MME0_CTRL, + GAUDI_ETF_MME1_ACC, + GAUDI_ETF_MME1_SBAB, + GAUDI_ETF_MME1_CTRL, + GAUDI_ETF_MME2_ACC, + GAUDI_ETF_MME2_SBAB, + GAUDI_ETF_MME2_CTRL, + GAUDI_ETF_MME3_ACC, + GAUDI_ETF_MME3_SBAB, + GAUDI_ETF_MME3_CTRL, + GAUDI_ETF_DMA_IF_W_S, + GAUDI_ETF_DMA_IF_E_S, + GAUDI_ETF_DMA_IF_W_N, + GAUDI_ETF_DMA_IF_E_N, + GAUDI_ETF_CPU_0, + GAUDI_ETF_CPU_1, + GAUDI_ETF_CPU_TRACE, + GAUDI_ETF_DMA_CH_0_CS, + GAUDI_ETF_DMA_CH_1_CS, + GAUDI_ETF_DMA_CH_2_CS, + GAUDI_ETF_DMA_CH_3_CS, + GAUDI_ETF_DMA_CH_4_CS, + GAUDI_ETF_DMA_CH_5_CS, + GAUDI_ETF_DMA_CH_6_CS, + GAUDI_ETF_DMA_CH_7_CS, + GAUDI_ETF_PCIE, + GAUDI_ETF_MMU_CS, + GAUDI_ETF_PSOC, + GAUDI_ETF_NIC0_0, + GAUDI_ETF_NIC0_1, + GAUDI_ETF_NIC1_0, + GAUDI_ETF_NIC1_1, + GAUDI_ETF_NIC2_0, + GAUDI_ETF_NIC2_1, + GAUDI_ETF_NIC3_0, + GAUDI_ETF_NIC3_1, + GAUDI_ETF_NIC4_0, + GAUDI_ETF_NIC4_1, + GAUDI_ETF_TPC0_EML, + GAUDI_ETF_TPC1_EML, + GAUDI_ETF_TPC2_EML, + GAUDI_ETF_TPC3_EML, + GAUDI_ETF_TPC4_EML, + GAUDI_ETF_TPC5_EML, + GAUDI_ETF_TPC6_EML, + GAUDI_ETF_TPC7_EML, + GAUDI_ETF_LAST = GAUDI_ETF_TPC7_EML +}; + +enum gaudi_debug_funnel_regs_index { + GAUDI_FUNNEL_FIRST = 0, + GAUDI_FUNNEL_MME0_ACC = GAUDI_FUNNEL_FIRST, + GAUDI_FUNNEL_MME1_ACC, + GAUDI_FUNNEL_MME2_ACC, + GAUDI_FUNNEL_MME3_ACC, + GAUDI_FUNNEL_SRAM_Y0_X0, + GAUDI_FUNNEL_SRAM_Y0_X1, + GAUDI_FUNNEL_SRAM_Y0_X2, + GAUDI_FUNNEL_SRAM_Y0_X3, + GAUDI_FUNNEL_SRAM_Y0_X4, + GAUDI_FUNNEL_SRAM_Y0_X5, + GAUDI_FUNNEL_SRAM_Y0_X6, + GAUDI_FUNNEL_SRAM_Y0_X7, + GAUDI_FUNNEL_SRAM_Y1_X0, + GAUDI_FUNNEL_SRAM_Y1_X1, + GAUDI_FUNNEL_SRAM_Y1_X2, + GAUDI_FUNNEL_SRAM_Y1_X3, + GAUDI_FUNNEL_SRAM_Y1_X4, + GAUDI_FUNNEL_SRAM_Y1_X5, + GAUDI_FUNNEL_SRAM_Y1_X6, + GAUDI_FUNNEL_SRAM_Y1_X7, + GAUDI_FUNNEL_SRAM_Y2_X0, + GAUDI_FUNNEL_SRAM_Y2_X1, + GAUDI_FUNNEL_SRAM_Y2_X2, + GAUDI_FUNNEL_SRAM_Y2_X3, + GAUDI_FUNNEL_SRAM_Y2_X4, + GAUDI_FUNNEL_SRAM_Y2_X5, + GAUDI_FUNNEL_SRAM_Y2_X6, + GAUDI_FUNNEL_SRAM_Y2_X7, + GAUDI_FUNNEL_SRAM_Y3_X0, + GAUDI_FUNNEL_SRAM_Y3_X1, + GAUDI_FUNNEL_SRAM_Y3_X2, + GAUDI_FUNNEL_SRAM_Y3_X4, + GAUDI_FUNNEL_SRAM_Y3_X3, + GAUDI_FUNNEL_SRAM_Y3_X5, + GAUDI_FUNNEL_SRAM_Y3_X6, + GAUDI_FUNNEL_SRAM_Y3_X7, + GAUDI_FUNNEL_SIF_0, + GAUDI_FUNNEL_SIF_1, + GAUDI_FUNNEL_SIF_2, + GAUDI_FUNNEL_SIF_3, + GAUDI_FUNNEL_SIF_4, + GAUDI_FUNNEL_SIF_5, + GAUDI_FUNNEL_SIF_6, + GAUDI_FUNNEL_SIF_7, + GAUDI_FUNNEL_NIF_0, + GAUDI_FUNNEL_NIF_1, + GAUDI_FUNNEL_NIF_2, + GAUDI_FUNNEL_NIF_3, + GAUDI_FUNNEL_NIF_4, + GAUDI_FUNNEL_NIF_5, + GAUDI_FUNNEL_NIF_6, + GAUDI_FUNNEL_NIF_7, + GAUDI_FUNNEL_DMA_IF_W_S, + GAUDI_FUNNEL_DMA_IF_E_S, + GAUDI_FUNNEL_DMA_IF_W_N, + GAUDI_FUNNEL_DMA_IF_E_N, + GAUDI_FUNNEL_CPU, + GAUDI_FUNNEL_NIC_TPC_W_S, + GAUDI_FUNNEL_NIC_TPC_E_S, + GAUDI_FUNNEL_NIC_TPC_W_N, + GAUDI_FUNNEL_NIC_TPC_E_N, + GAUDI_FUNNEL_PCIE, + GAUDI_FUNNEL_PSOC, + GAUDI_FUNNEL_NIC0, + GAUDI_FUNNEL_NIC1, + GAUDI_FUNNEL_NIC2, + GAUDI_FUNNEL_NIC3, + GAUDI_FUNNEL_NIC4, + GAUDI_FUNNEL_TPC0_EML, + GAUDI_FUNNEL_TPC1_EML, + GAUDI_FUNNEL_TPC2_EML, + GAUDI_FUNNEL_TPC3_EML, + GAUDI_FUNNEL_TPC4_EML, + GAUDI_FUNNEL_TPC5_EML, + GAUDI_FUNNEL_TPC6_EML, + GAUDI_FUNNEL_TPC7_EML, + GAUDI_FUNNEL_LAST = GAUDI_FUNNEL_TPC7_EML +}; + +enum gaudi_debug_bmon_regs_index { + GAUDI_BMON_FIRST = 0, + GAUDI_BMON_MME0_ACC_0 = GAUDI_BMON_FIRST, + GAUDI_BMON_MME0_SBAB_0, + GAUDI_BMON_MME0_SBAB_1, + GAUDI_BMON_MME0_CTRL_0, + GAUDI_BMON_MME0_CTRL_1, + GAUDI_BMON_MME1_ACC_0, + GAUDI_BMON_MME1_SBAB_0, + GAUDI_BMON_MME1_SBAB_1, + GAUDI_BMON_MME1_CTRL_0, + GAUDI_BMON_MME1_CTRL_1, + GAUDI_BMON_MME2_ACC_0, + GAUDI_BMON_MME2_SBAB_0, + GAUDI_BMON_MME2_SBAB_1, + GAUDI_BMON_MME2_CTRL_0, + GAUDI_BMON_MME2_CTRL_1, + GAUDI_BMON_MME3_ACC_0, + GAUDI_BMON_MME3_SBAB_0, + GAUDI_BMON_MME3_SBAB_1, + GAUDI_BMON_MME3_CTRL_0, + GAUDI_BMON_MME3_CTRL_1, + GAUDI_BMON_DMA_IF_W_S_SOB_WR, + GAUDI_BMON_DMA_IF_W_S_0_WR, + GAUDI_BMON_DMA_IF_W_S_0_RD, + GAUDI_BMON_DMA_IF_W_S_1_WR, + GAUDI_BMON_DMA_IF_W_S_1_RD, + GAUDI_BMON_DMA_IF_E_S_SOB_WR, + GAUDI_BMON_DMA_IF_E_S_0_WR, + GAUDI_BMON_DMA_IF_E_S_0_RD, + GAUDI_BMON_DMA_IF_E_S_1_WR, + GAUDI_BMON_DMA_IF_E_S_1_RD, + GAUDI_BMON_DMA_IF_W_N_SOB_WR, + GAUDI_BMON_DMA_IF_W_N_HBM0_WR, + GAUDI_BMON_DMA_IF_W_N_HBM0_RD, + GAUDI_BMON_DMA_IF_W_N_HBM1_WR, + GAUDI_BMON_DMA_IF_W_N_HBM1_RD, + GAUDI_BMON_DMA_IF_E_N_SOB_WR, + GAUDI_BMON_DMA_IF_E_N_HBM0_WR, + GAUDI_BMON_DMA_IF_E_N_HBM0_RD, + GAUDI_BMON_DMA_IF_E_N_HBM1_WR, + GAUDI_BMON_DMA_IF_E_N_HBM1_RD, + GAUDI_BMON_CPU_WR, + GAUDI_BMON_CPU_RD, + GAUDI_BMON_DMA_CH_0_0, + GAUDI_BMON_DMA_CH_0_1, + GAUDI_BMON_DMA_CH_1_0, + GAUDI_BMON_DMA_CH_1_1, + GAUDI_BMON_DMA_CH_2_0, + GAUDI_BMON_DMA_CH_2_1, + GAUDI_BMON_DMA_CH_3_0, + GAUDI_BMON_DMA_CH_3_1, + GAUDI_BMON_DMA_CH_4_0, + GAUDI_BMON_DMA_CH_4_1, + GAUDI_BMON_DMA_CH_5_0, + GAUDI_BMON_DMA_CH_5_1, + GAUDI_BMON_DMA_CH_6_0, + GAUDI_BMON_DMA_CH_6_1, + GAUDI_BMON_DMA_CH_7_0, + GAUDI_BMON_DMA_CH_7_1, + GAUDI_BMON_PCIE_MSTR_WR, + GAUDI_BMON_PCIE_MSTR_RD, + GAUDI_BMON_PCIE_SLV_WR, + GAUDI_BMON_PCIE_SLV_RD, + GAUDI_BMON_MMU_0, + GAUDI_BMON_MMU_1, + GAUDI_BMON_NIC0_0, + GAUDI_BMON_NIC0_1, + GAUDI_BMON_NIC0_2, + GAUDI_BMON_NIC0_3, + GAUDI_BMON_NIC0_4, + GAUDI_BMON_NIC1_0, + GAUDI_BMON_NIC1_1, + GAUDI_BMON_NIC1_2, + GAUDI_BMON_NIC1_3, + GAUDI_BMON_NIC1_4, + GAUDI_BMON_NIC2_0, + GAUDI_BMON_NIC2_1, + GAUDI_BMON_NIC2_2, + GAUDI_BMON_NIC2_3, + GAUDI_BMON_NIC2_4, + GAUDI_BMON_NIC3_0, + GAUDI_BMON_NIC3_1, + GAUDI_BMON_NIC3_2, + GAUDI_BMON_NIC3_3, + GAUDI_BMON_NIC3_4, + GAUDI_BMON_NIC4_0, + GAUDI_BMON_NIC4_1, + GAUDI_BMON_NIC4_2, + GAUDI_BMON_NIC4_3, + GAUDI_BMON_NIC4_4, + GAUDI_BMON_TPC0_EML_0, + GAUDI_BMON_TPC0_EML_1, + GAUDI_BMON_TPC0_EML_2, + GAUDI_BMON_TPC0_EML_3, + GAUDI_BMON_TPC1_EML_0, + GAUDI_BMON_TPC1_EML_1, + GAUDI_BMON_TPC1_EML_2, + GAUDI_BMON_TPC1_EML_3, + GAUDI_BMON_TPC2_EML_0, + GAUDI_BMON_TPC2_EML_1, + GAUDI_BMON_TPC2_EML_2, + GAUDI_BMON_TPC2_EML_3, + GAUDI_BMON_TPC3_EML_0, + GAUDI_BMON_TPC3_EML_1, + GAUDI_BMON_TPC3_EML_2, + GAUDI_BMON_TPC3_EML_3, + GAUDI_BMON_TPC4_EML_0, + GAUDI_BMON_TPC4_EML_1, + GAUDI_BMON_TPC4_EML_2, + GAUDI_BMON_TPC4_EML_3, + GAUDI_BMON_TPC5_EML_0, + GAUDI_BMON_TPC5_EML_1, + GAUDI_BMON_TPC5_EML_2, + GAUDI_BMON_TPC5_EML_3, + GAUDI_BMON_TPC6_EML_0, + GAUDI_BMON_TPC6_EML_1, + GAUDI_BMON_TPC6_EML_2, + GAUDI_BMON_TPC6_EML_3, + GAUDI_BMON_TPC7_EML_0, + GAUDI_BMON_TPC7_EML_1, + GAUDI_BMON_TPC7_EML_2, + GAUDI_BMON_TPC7_EML_3, + GAUDI_BMON_LAST = GAUDI_BMON_TPC7_EML_3 +}; + +enum gaudi_debug_spmu_regs_index { + GAUDI_SPMU_FIRST = 0, + GAUDI_SPMU_MME0_ACC = GAUDI_SPMU_FIRST, + GAUDI_SPMU_MME0_SBAB, + GAUDI_SPMU_MME0_CTRL, + GAUDI_SPMU_MME1_ACC, + GAUDI_SPMU_MME1_SBAB, + GAUDI_SPMU_MME1_CTRL, + GAUDI_SPMU_MME2_MME2_ACC, + GAUDI_SPMU_MME2_SBAB, + GAUDI_SPMU_MME2_CTRL, + GAUDI_SPMU_MME3_ACC, + GAUDI_SPMU_MME3_SBAB, + GAUDI_SPMU_MME3_CTRL, + GAUDI_SPMU_DMA_CH_0_CS, + GAUDI_SPMU_DMA_CH_1_CS, + GAUDI_SPMU_DMA_CH_2_CS, + GAUDI_SPMU_DMA_CH_3_CS, + GAUDI_SPMU_DMA_CH_4_CS, + GAUDI_SPMU_DMA_CH_5_CS, + GAUDI_SPMU_DMA_CH_6_CS, + GAUDI_SPMU_DMA_CH_7_CS, + GAUDI_SPMU_PCIE, + GAUDI_SPMU_MMU_CS, + GAUDI_SPMU_NIC0_0, + GAUDI_SPMU_NIC0_1, + GAUDI_SPMU_NIC1_0, + GAUDI_SPMU_NIC1_1, + GAUDI_SPMU_NIC2_0, + GAUDI_SPMU_NIC2_1, + GAUDI_SPMU_NIC3_0, + GAUDI_SPMU_NIC3_1, + GAUDI_SPMU_NIC4_0, + GAUDI_SPMU_NIC4_1, + GAUDI_SPMU_TPC0_EML, + GAUDI_SPMU_TPC1_EML, + GAUDI_SPMU_TPC2_EML, + GAUDI_SPMU_TPC3_EML, + GAUDI_SPMU_TPC4_EML, + GAUDI_SPMU_TPC5_EML, + GAUDI_SPMU_TPC6_EML, + GAUDI_SPMU_TPC7_EML, + GAUDI_SPMU_LAST = GAUDI_SPMU_TPC7_EML +}; + +#endif /* GAUDI_CORESIGHT_H */ diff --git a/drivers/misc/habanalabs/include/gaudi/gaudi_fw_if.h b/drivers/misc/habanalabs/include/gaudi/gaudi_fw_if.h new file mode 100644 index 000000000000..8aadc6357da1 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/gaudi_fw_if.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2019-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDI_FW_IF_H +#define GAUDI_FW_IF_H + +#define GAUDI_EVENT_QUEUE_MSI_IDX 8 +#define GAUDI_NIC_PORT1_MSI_IDX 10 +#define GAUDI_NIC_PORT3_MSI_IDX 12 +#define GAUDI_NIC_PORT5_MSI_IDX 14 +#define GAUDI_NIC_PORT7_MSI_IDX 16 +#define GAUDI_NIC_PORT9_MSI_IDX 18 + +#define UBOOT_FW_OFFSET 0x100000 /* 1MB in SRAM */ +#define LINUX_FW_OFFSET 0x800000 /* 8MB in HBM */ + +enum gaudi_pll_index { + CPU_PLL = 0, + PCI_PLL, + SRAM_PLL, + HBM_PLL, + NIC_PLL, + DMA_PLL, + MESH_PLL, + MME_PLL, + TPC_PLL, + IF_PLL +}; + +#define GAUDI_PLL_FREQ_LOW 200000000 /* 200 MHz */ + +#endif /* GAUDI_FW_IF_H */ diff --git a/drivers/misc/habanalabs/include/gaudi/gaudi_masks.h b/drivers/misc/habanalabs/include/gaudi/gaudi_masks.h new file mode 100644 index 000000000000..96f08050ef0f --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/gaudi_masks.h @@ -0,0 +1,458 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDI_MASKS_H_ +#define GAUDI_MASKS_H_ + +#include "asic_reg/gaudi_regs.h" + +/* Useful masks for bits in various registers */ +#define PCI_DMA_QMAN_ENABLE (\ + (0xF << DMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \ + (0xF << DMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \ + (0xF << DMA0_QM_GLBL_CFG0_CP_EN_SHIFT)) + +#define QMAN_EXTERNAL_MAKE_TRUSTED (\ + (0xF << DMA0_QM_GLBL_PROT_PQF_SHIFT) | \ + (0xF << DMA0_QM_GLBL_PROT_CQF_SHIFT) | \ + (0xF << DMA0_QM_GLBL_PROT_CP_SHIFT) | \ + (0x1 << DMA0_QM_GLBL_PROT_ERR_SHIFT)) + +#define QMAN_INTERNAL_MAKE_TRUSTED (\ + (0xF << DMA0_QM_GLBL_PROT_PQF_SHIFT) | \ + (0x1 << DMA0_QM_GLBL_PROT_ERR_SHIFT)) + +#define HBM_DMA_QMAN_ENABLE (\ + (0xF << DMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \ + (0x1F << DMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \ + (0x1F << DMA0_QM_GLBL_CFG0_CP_EN_SHIFT)) + +#define QMAN_MME_ENABLE (\ + (0xF << MME0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \ + (0x1F << MME0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \ + (0x1F << MME0_QM_GLBL_CFG0_CP_EN_SHIFT)) + +#define QMAN_TPC_ENABLE (\ + (0xF << TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \ + (0x1F << TPC0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \ + (0x1F << TPC0_QM_GLBL_CFG0_CP_EN_SHIFT)) + +#define QMAN_UPPER_CP_CGM_PWR_GATE_EN (\ + (0x20 << DMA0_QM_CGM_CFG_IDLE_TH_SHIFT) | \ + (0xA << DMA0_QM_CGM_CFG_G2F_TH_SHIFT) | \ + (0x10 << DMA0_QM_CGM_CFG_CP_IDLE_MASK_SHIFT) | \ + (1 << DMA0_QM_CGM_CFG_EN_SHIFT)) + +#define QMAN_COMMON_CP_CGM_PWR_GATE_EN (\ + (0x20 << DMA0_QM_CGM_CFG_IDLE_TH_SHIFT) | \ + (0xA << DMA0_QM_CGM_CFG_G2F_TH_SHIFT) | \ + (0xF << DMA0_QM_CGM_CFG_CP_IDLE_MASK_SHIFT) | \ + (1 << DMA0_QM_CGM_CFG_EN_SHIFT)) + +#define PCI_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\ + (0xF << DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \ + (0xF << DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \ + (0xF << DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT)) + +#define PCI_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\ + (0xF << DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ + (0xF << DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ + (0xF << DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT)) + +#define HBM_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\ + (0xF << DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \ + (0x1F << DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \ + (0x1F << DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT)) + +#define HBM_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\ + (0xF << DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ + (0x1F << DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ + (0x1F << DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT)) + +#define TPC_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\ + (0xF << TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \ + (0x1F << TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \ + (0x1F << TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT)) + +#define TPC_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\ + (0xF << TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ + (0x1F << TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ + (0x1F << TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT)) + +#define MME_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\ + (0xF << MME0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \ + (0x1F << MME0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \ + (0x1F << MME0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT)) + +#define MME_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\ + (0xF << MME0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ + (0x1F << MME0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ + (0x1F << MME0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT)) + +#define QMAN_CGM1_PWR_GATE_EN (0xA << DMA0_QM_CGM_CFG1_MASK_TH_SHIFT) + +/* RESET registers configuration */ +#define CFG_RST_L_PSOC_SHIFT 0 +#define CFG_RST_L_PCIE_SHIFT 1 +#define CFG_RST_L_PCIE_IF_SHIFT 2 +#define CFG_RST_L_HBM_S_PLL_SHIFT 3 +#define CFG_RST_L_TPC_S_PLL_SHIFT 4 +#define CFG_RST_L_MME_S_PLL_SHIFT 5 +#define CFG_RST_L_CPU_PLL_SHIFT 6 +#define CFG_RST_L_PCIE_PLL_SHIFT 7 +#define CFG_RST_L_NIC_S_PLL_SHIFT 8 +#define CFG_RST_L_HBM_N_PLL_SHIFT 9 +#define CFG_RST_L_TPC_N_PLL_SHIFT 10 +#define CFG_RST_L_MME_N_PLL_SHIFT 11 +#define CFG_RST_L_NIC_N_PLL_SHIFT 12 +#define CFG_RST_L_DMA_W_PLL_SHIFT 13 +#define CFG_RST_L_SIF_W_PLL_SHIFT 14 +#define CFG_RST_L_MESH_W_PLL_SHIFT 15 +#define CFG_RST_L_SRAM_W_PLL_SHIFT 16 +#define CFG_RST_L_DMA_E_PLL_SHIFT 17 +#define CFG_RST_L_SIF_E_PLL_SHIFT 18 +#define CFG_RST_L_MESH_E_PLL_SHIFT 19 +#define CFG_RST_L_SRAM_E_PLL_SHIFT 20 +#define CFG_RST_L_IF_1_SHIFT 21 +#define CFG_RST_L_IF_0_SHIFT 22 +#define CFG_RST_L_IF_2_SHIFT 23 +#define CFG_RST_L_IF_3_SHIFT 24 +#define CFG_RST_L_TPC_0_SHIFT 25 +#define CFG_RST_L_TPC_1_SHIFT 26 +#define CFG_RST_L_TPC_2_SHIFT 27 +#define CFG_RST_L_TPC_3_SHIFT 28 +#define CFG_RST_L_TPC_4_SHIFT 29 +#define CFG_RST_L_TPC_5_SHIFT 30 +#define CFG_RST_L_TPC_6_SHIFT 31 +#define CFG_RST_H_TPC_7_SHIFT 0 +#define CFG_RST_H_MME_0_SHIFT 1 +#define CFG_RST_H_MME_1_SHIFT 2 +#define CFG_RST_H_MME_2_SHIFT 3 +#define CFG_RST_H_MME_3_SHIFT 4 +#define CFG_RST_H_HBM_0_SHIFT 5 +#define CFG_RST_H_HBM_1_SHIFT 6 +#define CFG_RST_H_HBM_2_SHIFT 7 +#define CFG_RST_H_HBM_3_SHIFT 8 +#define CFG_RST_H_NIC_0_SHIFT 9 +#define CFG_RST_H_NIC_1_SHIFT 10 +#define CFG_RST_H_NIC_2_SHIFT 11 +#define CFG_RST_H_NIC_3_SHIFT 12 +#define CFG_RST_H_NIC_4_SHIFT 13 +#define CFG_RST_H_SM_0_SHIFT 14 +#define CFG_RST_H_SM_1_SHIFT 15 +#define CFG_RST_H_SM_2_SHIFT 16 +#define CFG_RST_H_SM_3_SHIFT 17 +#define CFG_RST_H_DMA_0_SHIFT 18 +#define CFG_RST_H_DMA_1_SHIFT 19 +#define CFG_RST_H_CPU_SHIFT 20 +#define CFG_RST_H_MMU_SHIFT 21 + + +#define CFG_RST_H_DMA_MASK ((1 << CFG_RST_H_DMA_0_SHIFT) | \ + (1 << CFG_RST_H_DMA_1_SHIFT)) + +#define CFG_RST_H_CPU_MASK (1 << CFG_RST_H_CPU_SHIFT) +#define CFG_RST_H_MMU_MASK (1 << CFG_RST_H_MMU_SHIFT) + +#define CFG_RST_H_HBM_MASK ((1 << CFG_RST_H_HBM_0_SHIFT) | \ + (1 << CFG_RST_H_HBM_1_SHIFT) | \ + (1 << CFG_RST_H_HBM_2_SHIFT) | \ + (1 << CFG_RST_H_HBM_3_SHIFT)) + +#define CFG_RST_H_NIC_MASK ((1 << CFG_RST_H_NIC_0_SHIFT) | \ + (1 << CFG_RST_H_NIC_1_SHIFT) | \ + (1 << CFG_RST_H_NIC_2_SHIFT) | \ + (1 << CFG_RST_H_NIC_3_SHIFT) | \ + (1 << CFG_RST_H_NIC_4_SHIFT)) + +#define CFG_RST_H_SM_MASK ((1 << CFG_RST_H_SM_0_SHIFT) | \ + (1 << CFG_RST_H_SM_1_SHIFT) | \ + (1 << CFG_RST_H_SM_2_SHIFT) | \ + (1 << CFG_RST_H_SM_3_SHIFT)) + +#define CFG_RST_H_MME_MASK ((1 << CFG_RST_H_MME_0_SHIFT) | \ + (1 << CFG_RST_H_MME_1_SHIFT) | \ + (1 << CFG_RST_H_MME_2_SHIFT) | \ + (1 << CFG_RST_H_MME_3_SHIFT)) + +#define CFG_RST_L_PSOC_MASK (1 << CFG_RST_L_PSOC_SHIFT) + +#define CFG_RST_L_IF_MASK ((1 << CFG_RST_L_IF_0_SHIFT) | \ + (1 << CFG_RST_L_IF_1_SHIFT) | \ + (1 << CFG_RST_L_IF_2_SHIFT) | \ + (1 << CFG_RST_L_IF_3_SHIFT)) + +#define CFG_RST_L_TPC_MASK ((1 << CFG_RST_L_TPC_0_SHIFT) | \ + (1 << CFG_RST_L_TPC_1_SHIFT) | \ + (1 << CFG_RST_L_TPC_2_SHIFT) | \ + (1 << CFG_RST_L_TPC_3_SHIFT) | \ + (1 << CFG_RST_L_TPC_4_SHIFT) | \ + (1 << CFG_RST_L_TPC_5_SHIFT) | \ + (1 << CFG_RST_L_TPC_6_SHIFT)) + +#define CFG_RST_H_TPC_MASK (1 << CFG_RST_H_TPC_7_SHIFT) + +#define CA53_RESET (1 << CFG_RST_H_CPU_SHIFT) + +#define UNIT_RST_L_PSOC_SHIFT 0 +#define UNIT_RST_L_PCIE_SHIFT 1 +#define UNIT_RST_L_PCIE_IF_SHIFT 2 +#define UNIT_RST_L_HBM_S_PLL_SHIFT 3 +#define UNIT_RST_L_TPC_S_PLL_SHIFT 4 +#define UNIT_RST_L_MME_S_PLL_SHIFT 5 +#define UNIT_RST_L_CPU_PLL_SHIFT 6 +#define UNIT_RST_L_PCIE_PLL_SHIFT 7 +#define UNIT_RST_L_NIC_S_PLL_SHIFT 8 +#define UNIT_RST_L_HBM_N_PLL_SHIFT 9 +#define UNIT_RST_L_TPC_N_PLL_SHIFT 10 +#define UNIT_RST_L_MME_N_PLL_SHIFT 11 +#define UNIT_RST_L_NIC_N_PLL_SHIFT 12 +#define UNIT_RST_L_DMA_W_PLL_SHIFT 13 +#define UNIT_RST_L_SIF_W_PLL_SHIFT 14 +#define UNIT_RST_L_MESH_W_PLL_SHIFT 15 +#define UNIT_RST_L_SRAM_W_PLL_SHIFT 16 +#define UNIT_RST_L_DMA_E_PLL_SHIFT 17 +#define UNIT_RST_L_SIF_E_PLL_SHIFT 18 +#define UNIT_RST_L_MESH_E_PLL_SHIFT 19 +#define UNIT_RST_L_SRAM_E_PLL_SHIFT 20 +#define UNIT_RST_L_TPC_0_SHIFT 21 +#define UNIT_RST_L_TPC_1_SHIFT 22 +#define UNIT_RST_L_TPC_2_SHIFT 23 +#define UNIT_RST_L_TPC_3_SHIFT 24 +#define UNIT_RST_L_TPC_4_SHIFT 25 +#define UNIT_RST_L_TPC_5_SHIFT 26 +#define UNIT_RST_L_TPC_6_SHIFT 27 +#define UNIT_RST_L_TPC_7_SHIFT 28 +#define UNIT_RST_L_MME_0_SHIFT 29 +#define UNIT_RST_L_MME_1_SHIFT 30 +#define UNIT_RST_L_MME_2_SHIFT 31 + +#define UNIT_RST_H_MME_3_SHIFT 0 +#define UNIT_RST_H_HBM_0_SHIFT 1 +#define UNIT_RST_H_HBM_1_SHIFT 2 +#define UNIT_RST_H_HBM_2_SHIFT 3 +#define UNIT_RST_H_HBM_3_SHIFT 4 +#define UNIT_RST_H_NIC_0_SHIFT 5 +#define UNIT_RST_H_NIC_1_SHIFT 6 +#define UNIT_RST_H_NIC_2_SHIFT 7 +#define UNIT_RST_H_NIC_3_SHIFT 8 +#define UNIT_RST_H_NIC_4_SHIFT 9 +#define UNIT_RST_H_SM_0_SHIFT 10 +#define UNIT_RST_H_SM_1_SHIFT 11 +#define UNIT_RST_H_SM_2_SHIFT 12 +#define UNIT_RST_H_SM_3_SHIFT 13 +#define UNIT_RST_H_IF_0_SHIFT 14 +#define UNIT_RST_H_IF_1_SHIFT 15 +#define UNIT_RST_H_IF_2_SHIFT 16 +#define UNIT_RST_H_IF_3_SHIFT 17 +#define UNIT_RST_H_DMA_0_SHIFT 18 +#define UNIT_RST_H_DMA_1_SHIFT 19 +#define UNIT_RST_H_CPU_SHIFT 20 +#define UNIT_RST_H_MMU_SHIFT 21 + +#define UNIT_RST_H_HBM_MASK ((1 << UNIT_RST_H_HBM_0_SHIFT) | \ + (1 << UNIT_RST_H_HBM_1_SHIFT) | \ + (1 << UNIT_RST_H_HBM_2_SHIFT) | \ + (1 << UNIT_RST_H_HBM_3_SHIFT)) + +#define UNIT_RST_H_NIC_MASK ((1 << UNIT_RST_H_NIC_0_SHIFT) | \ + (1 << UNIT_RST_H_NIC_1_SHIFT) | \ + (1 << UNIT_RST_H_NIC_2_SHIFT) | \ + (1 << UNIT_RST_H_NIC_3_SHIFT) | \ + (1 << UNIT_RST_H_NIC_4_SHIFT)) + +#define UNIT_RST_H_SM_MASK ((1 << UNIT_RST_H_SM_0_SHIFT) | \ + (1 << UNIT_RST_H_SM_1_SHIFT) | \ + (1 << UNIT_RST_H_SM_2_SHIFT) | \ + (1 << UNIT_RST_H_SM_3_SHIFT)) + +#define UNIT_RST_H_MME_MASK ((1 << UNIT_RST_H_MME_0_SHIFT) | \ + (1 << UNIT_RST_H_MME_1_SHIFT) | \ + (1 << UNIT_RST_H_MME_2_SHIFT)) + +#define UNIT_RST_L_MME_MASK (1 << UNIT_RST_L_MME_3_SHIFT) + +#define UNIT_RST_L_IF_MASK ((1 << UNIT_RST_L_IF_0_SHIFT) | \ + (1 << UNIT_RST_L_IF_1_SHIFT) | \ + (1 << UNIT_RST_L_IF_2_SHIFT) | \ + (1 << UNIT_RST_L_IF_3_SHIFT)) + +#define UNIT_RST_L_TPC_MASK ((1 << UNIT_RST_L_TPC_0_SHIFT) | \ + (1 << UNIT_RST_L_TPC_1_SHIFT) | \ + (1 << UNIT_RST_L_TPC_2_SHIFT) | \ + (1 << UNIT_RST_L_TPC_3_SHIFT) | \ + (1 << UNIT_RST_L_TPC_4_SHIFT) | \ + (1 << UNIT_RST_L_TPC_5_SHIFT) | \ + (1 << UNIT_RST_L_TPC_6_SHIFT) | \ + (1 << UNIT_RST_L_TPC_7_SHIFT)) + +/* CPU_CA53_CFG_ARM_RST_CONTROL */ +#define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT 0 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_MASK 0x3 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT 4 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_MASK 0x30 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT 8 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_MASK 0x100 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_SHIFT 12 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_MASK 0x1000 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT 16 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_MASK 0x10000 +#define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_SHIFT 20 +#define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_MASK 0x300000 + +#define CPU_RESET_ASSERT (\ + 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT) + +#define CPU_RESET_CORE0_DEASSERT (\ + 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT |\ + 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT |\ + 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT |\ + 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT) + +/* QM_IDLE_MASK is valid for all engines QM idle check */ +#define QM_IDLE_MASK (DMA0_QM_GLBL_STS0_PQF_IDLE_MASK | \ + DMA0_QM_GLBL_STS0_CQF_IDLE_MASK | \ + DMA0_QM_GLBL_STS0_CP_IDLE_MASK) + +/* CGM_IDLE_MASK is valid for all engines CGM idle check */ +#define CGM_IDLE_MASK DMA0_QM_CGM_STS_AGENT_IDLE_MASK + +#define TPC_IDLE_MASK ((1 << TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT) | \ + (1 << TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT) | \ + (1 << TPC0_CFG_STATUS_IQ_EMPTY_SHIFT) | \ + (1 << TPC0_CFG_STATUS_SB_EMPTY_SHIFT) | \ + (1 << TPC0_CFG_STATUS_QM_IDLE_SHIFT) | \ + (1 << TPC0_CFG_STATUS_QM_RDY_SHIFT)) + +#define MME0_CTRL_ARCH_STATUS_SB_A_EMPTY_MASK 0x80 +#define MME0_CTRL_ARCH_STATUS_SB_B_EMPTY_MASK 0x100 +#define MME0_CTRL_ARCH_STATUS_WBC_AXI_IDLE_MASK 0x1000 + +#define MME_ARCH_IDLE_MASK (MME0_CTRL_ARCH_STATUS_SB_A_EMPTY_MASK | \ + MME0_CTRL_ARCH_STATUS_SB_B_EMPTY_MASK | \ + MME0_CTRL_ARCH_STATUS_WBC_AXI_IDLE_MASK) + +#define IS_QM_IDLE(qm_glbl_sts0, qm_cgm_sts) \ + ((((qm_glbl_sts0) & QM_IDLE_MASK) == QM_IDLE_MASK) && \ + (((qm_cgm_sts) & CGM_IDLE_MASK) == CGM_IDLE_MASK)) + +#define IS_DMA_IDLE(dma_core_sts0) \ + !(dma_core_sts0 & DMA0_CORE_STS0_BUSY_MASK) + +#define IS_TPC_IDLE(tpc_cfg_sts) \ + (((tpc_cfg_sts) & TPC_IDLE_MASK) == TPC_IDLE_MASK) + +#define IS_MME_IDLE(mme_arch_sts) \ + (((mme_arch_sts) & MME_ARCH_IDLE_MASK) == MME_ARCH_IDLE_MASK) + +enum axi_id { + AXI_ID_MME, + AXI_ID_TPC, + AXI_ID_DMA, + AXI_ID_NIC, /* Local NIC */ + AXI_ID_PCI, + AXI_ID_CPU, + AXI_ID_PSOC, + AXI_ID_MMU, + AXI_ID_NIC_FT /* Feed-Through NIC */ +}; + +/* RAZWI initiator ID is built from the location in the chip and the AXI ID */ + +#define RAZWI_INITIATOR_AXI_ID_SHIFT 20 +#define RAZWI_INITIATOR_AXI_ID_MASK 0xF +#define RAZWI_INITIATOR_X_SHIFT 24 +#define RAZWI_INITIATOR_X_MASK 0xF +#define RAZWI_INITIATOR_Y_SHIFT 28 +#define RAZWI_INITIATOR_Y_MASK 0x7 + +#define RAZWI_INITIATOR_ID_AXI_ID(axi_id) \ + (((axi_id) & RAZWI_INITIATOR_AXI_ID_MASK) << \ + RAZWI_INITIATOR_AXI_ID_SHIFT) + +#define RAZWI_INITIATOR_ID_X_Y(x, y) \ + ((((y) & RAZWI_INITIATOR_Y_MASK) << RAZWI_INITIATOR_Y_SHIFT) | \ + (((x) & RAZWI_INITIATOR_X_MASK) << RAZWI_INITIATOR_X_SHIFT)) + +#define RAZWI_INITIATOR_ID_X_Y_TPC0_NIC0 RAZWI_INITIATOR_ID_X_Y(1, 0) +#define RAZWI_INITIATOR_ID_X_Y_TPC1 RAZWI_INITIATOR_ID_X_Y(2, 0) +#define RAZWI_INITIATOR_ID_X_Y_MME0_0 RAZWI_INITIATOR_ID_X_Y(3, 0) +#define RAZWI_INITIATOR_ID_X_Y_MME0_1 RAZWI_INITIATOR_ID_X_Y(4, 0) +#define RAZWI_INITIATOR_ID_X_Y_MME1_0 RAZWI_INITIATOR_ID_X_Y(5, 0) +#define RAZWI_INITIATOR_ID_X_Y_MME1_1 RAZWI_INITIATOR_ID_X_Y(6, 0) +#define RAZWI_INITIATOR_ID_X_Y_TPC2 RAZWI_INITIATOR_ID_X_Y(7, 0) +#define RAZWI_INITIATOR_ID_X_Y_TPC3_PCI_CPU_PSOC \ + RAZWI_INITIATOR_ID_X_Y(8, 0) +#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_0 RAZWI_INITIATOR_ID_X_Y(0, 1) +#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_0 RAZWI_INITIATOR_ID_X_Y(9, 1) +#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_1 RAZWI_INITIATOR_ID_X_Y(0, 2) +#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_1 RAZWI_INITIATOR_ID_X_Y(9, 2) +#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_0 RAZWI_INITIATOR_ID_X_Y(0, 3) +#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_0 RAZWI_INITIATOR_ID_X_Y(9, 3) +#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_1 RAZWI_INITIATOR_ID_X_Y(0, 4) +#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_1 RAZWI_INITIATOR_ID_X_Y(9, 4) +#define RAZWI_INITIATOR_ID_X_Y_TPC4_NIC1_NIC2 RAZWI_INITIATOR_ID_X_Y(1, 5) +#define RAZWI_INITIATOR_ID_X_Y_TPC5 RAZWI_INITIATOR_ID_X_Y(2, 5) +#define RAZWI_INITIATOR_ID_X_Y_MME2_0 RAZWI_INITIATOR_ID_X_Y(3, 5) +#define RAZWI_INITIATOR_ID_X_Y_MME2_1 RAZWI_INITIATOR_ID_X_Y(4, 5) +#define RAZWI_INITIATOR_ID_X_Y_MME3_0 RAZWI_INITIATOR_ID_X_Y(5, 5) +#define RAZWI_INITIATOR_ID_X_Y_MME3_1 RAZWI_INITIATOR_ID_X_Y(6, 5) +#define RAZWI_INITIATOR_ID_X_Y_TPC6 RAZWI_INITIATOR_ID_X_Y(7, 5) +#define RAZWI_INITIATOR_ID_X_Y_TPC7_NIC4_NIC5 RAZWI_INITIATOR_ID_X_Y(8, 5) + +#define PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT 1 + +/* STLB_CACHE_INV */ +#define STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0 +#define STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF +#define STLB_CACHE_INV_INDEX_MASK_SHIFT 8 +#define STLB_CACHE_INV_INDEX_MASK_MASK 0xFF00 + +#define MME_ACC_ACC_STALL_R_SHIFT 0 +#define MME_SBAB_SB_STALL_R_SHIFT 0 + +#define PCIE_WRAP_LBW_PROT_OVR_RD_EN_MASK 0x700 +#define PCIE_WRAP_LBW_PROT_OVR_WR_EN_MASK 0x7000 + +#define PCIE_WRAP_LBW_DRAIN_CFG_EN_SHIFT 0 +#define PCIE_WRAP_HBW_DRAIN_CFG_EN_SHIFT 0 + +/* DMA_IF_HBM_CRED_EN */ +#define DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT 0 +#define DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_MASK 0x1 +#define DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT 1 +#define DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_MASK 0x2 + +#define DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT 0 +#define DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT 0 +#define DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT 0 +#define DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT 0 + +#define IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT 0 +#define IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT 0 + +#define IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT 0 +#define IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT 0 + +/* MMU_UP_PAGE_ERROR_CAPTURE */ +#define MMU_UP_PAGE_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF +#define MMU_UP_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000 + +/* MMU_UP_ACCESS_ERROR_CAPTURE */ +#define MMU_UP_ACCESS_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF +#define MMU_UP_ACCESS_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000 + +#define QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1 +#define QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2 +#define QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4 + +#define QM_ARB_ERR_MSG_EN_MASK (\ + QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK |\ + QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK |\ + QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK) + +#endif /* GAUDI_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/gaudi_packets.h b/drivers/misc/habanalabs/include/gaudi/gaudi_packets.h new file mode 100644 index 000000000000..9a5800b0086b --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/gaudi_packets.h @@ -0,0 +1,212 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2017-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDI_PACKETS_H +#define GAUDI_PACKETS_H + +#include + +#define PACKET_HEADER_PACKET_ID_SHIFT 56 +#define PACKET_HEADER_PACKET_ID_MASK 0x1F00000000000000ull + +enum packet_id { + PACKET_WREG_32 = 0x1, + PACKET_WREG_BULK = 0x2, + PACKET_MSG_LONG = 0x3, + PACKET_MSG_SHORT = 0x4, + PACKET_CP_DMA = 0x5, + PACKET_REPEAT = 0x6, + PACKET_MSG_PROT = 0x7, + PACKET_FENCE = 0x8, + PACKET_LIN_DMA = 0x9, + PACKET_NOP = 0xA, + PACKET_STOP = 0xB, + PACKET_ARB_POINT = 0xC, + PACKET_WAIT = 0xD, + PACKET_LOAD_AND_EXE = 0xF, + MAX_PACKET_ID = (PACKET_HEADER_PACKET_ID_MASK >> + PACKET_HEADER_PACKET_ID_SHIFT) + 1 +}; + +#define GAUDI_PKT_CTL_OPCODE_SHIFT 24 +#define GAUDI_PKT_CTL_OPCODE_MASK 0x1F000000 + +#define GAUDI_PKT_CTL_EB_SHIFT 29 +#define GAUDI_PKT_CTL_EB_MASK 0x20000000 + +#define GAUDI_PKT_CTL_RB_SHIFT 30 +#define GAUDI_PKT_CTL_RB_MASK 0x40000000 + +#define GAUDI_PKT_CTL_MB_SHIFT 31 +#define GAUDI_PKT_CTL_MB_MASK 0x80000000 + +/* All packets have, at least, an 8-byte header, which contains + * the packet type. The kernel driver uses the packet header for packet + * validation and to perform any necessary required preparation before + * sending them off to the hardware. + */ +struct gaudi_packet { + __le64 header; + /* The rest of the packet data follows. Use the corresponding + * packet_XXX struct to deference the data, based on packet type + */ + u8 contents[0]; +}; + +struct packet_nop { + __le32 reserved; + __le32 ctl; +}; + +struct packet_stop { + __le32 reserved; + __le32 ctl; +}; + +struct packet_wreg32 { + __le32 value; + __le32 ctl; +}; + +struct packet_wreg_bulk { + __le32 size64; + __le32 ctl; + __le64 values[0]; /* data starts here */ +}; + +struct packet_msg_long { + __le32 value; + __le32 ctl; + __le64 addr; +}; + +#define GAUDI_PKT_SHORT_VAL_SOB_SYNC_VAL_SHIFT 0 +#define GAUDI_PKT_SHORT_VAL_SOB_SYNC_VAL_MASK 0x0000EFFF + +#define GAUDI_PKT_SHORT_VAL_SOB_MOD_SHIFT 31 +#define GAUDI_PKT_SHORT_VAL_SOB_MOD_MASK 0x80000000 + +#define GAUDI_PKT_SHORT_VAL_MON_SYNC_GID_SHIFT 0 +#define GAUDI_PKT_SHORT_VAL_MON_SYNC_GID_MASK 0x000000FF + +#define GAUDI_PKT_SHORT_VAL_MON_MASK_SHIFT 8 +#define GAUDI_PKT_SHORT_VAL_MON_MASK_MASK 0x0000FF00 + +#define GAUDI_PKT_SHORT_VAL_MON_MODE_SHIFT 16 +#define GAUDI_PKT_SHORT_VAL_MON_MODE_MASK 0x00010000 + +#define GAUDI_PKT_SHORT_VAL_MON_SYNC_VAL_SHIFT 17 +#define GAUDI_PKT_SHORT_VAL_MON_SYNC_VAL_MASK 0xFFFE0000 + +#define GAUDI_PKT_SHORT_CTL_ADDR_SHIFT 0 +#define GAUDI_PKT_SHORT_CTL_ADDR_MASK 0x0000FFFF + +#define GAUDI_PKT_SHORT_CTL_OP_SHIFT 20 +#define GAUDI_PKT_SHORT_CTL_OP_MASK 0x00300000 + +#define GAUDI_PKT_SHORT_CTL_BASE_SHIFT 22 +#define GAUDI_PKT_SHORT_CTL_BASE_MASK 0x00C00000 + +#define GAUDI_PKT_SHORT_CTL_OPCODE_SHIFT 24 +#define GAUDI_PKT_SHORT_CTL_OPCODE_MASK 0x1F000000 + +#define GAUDI_PKT_SHORT_CTL_EB_SHIFT 29 +#define GAUDI_PKT_SHORT_CTL_EB_MASK 0x20000000 + +#define GAUDI_PKT_SHORT_CTL_RB_SHIFT 30 +#define GAUDI_PKT_SHORT_CTL_RB_MASK 0x40000000 + +#define GAUDI_PKT_SHORT_CTL_MB_SHIFT 31 +#define GAUDI_PKT_SHORT_CTL_MB_MASK 0x80000000 + +struct packet_msg_short { + __le32 value; + __le32 ctl; +}; + +struct packet_msg_prot { + __le32 value; + __le32 ctl; + __le64 addr; +}; + +#define GAUDI_PKT_FENCE_CFG_DEC_VAL_SHIFT 0 +#define GAUDI_PKT_FENCE_CFG_DEC_VAL_MASK 0x0000000F + +#define GAUDI_PKT_FENCE_CFG_TARGET_VAL_SHIFT 16 +#define GAUDI_PKT_FENCE_CFG_TARGET_VAL_MASK 0x00FF0000 + +#define GAUDI_PKT_FENCE_CFG_ID_SHIFT 30 +#define GAUDI_PKT_FENCE_CFG_ID_MASK 0xC000000 + +#define GAUDI_PKT_FENCE_CTL_PRED_SHIFT 0 +#define GAUDI_PKT_FENCE_CTL_PRED_MASK 0x0000001F + +#define GAUDI_PKT_FENCE_CTL_OPCODE_SHIFT 24 +#define GAUDI_PKT_FENCE_CTL_OPCODE_MASK 0x1F000000 + +#define GAUDI_PKT_FENCE_CTL_EB_SHIFT 29 +#define GAUDI_PKT_FENCE_CTL_EB_MASK 0x20000000 + +#define GAUDI_PKT_FENCE_CTL_RB_SHIFT 30 +#define GAUDI_PKT_FENCE_CTL_RB_MASK 0x40000000 + +#define GAUDI_PKT_FENCE_CTL_MB_SHIFT 31 +#define GAUDI_PKT_FENCE_CTL_MB_MASK 0x80000000 + +struct packet_fence { + __le32 cfg; + __le32 ctl; +}; + +#define GAUDI_PKT_LIN_DMA_CTL_WRCOMP_EN_SHIFT 0 +#define GAUDI_PKT_LIN_DMA_CTL_WRCOMP_EN_MASK 0x00000001 + +#define GAUDI_PKT_LIN_DMA_CTL_LIN_SHIFT 3 +#define GAUDI_PKT_LIN_DMA_CTL_LIN_MASK 0x00000008 + +#define GAUDI_PKT_LIN_DMA_CTL_MEMSET_SHIFT 4 +#define GAUDI_PKT_LIN_DMA_CTL_MEMSET_MASK 0x00000010 + +#define GAUDI_PKT_LIN_DMA_DST_ADDR_SHIFT 0 +#define GAUDI_PKT_LIN_DMA_DST_ADDR_MASK 0x00FFFFFFFFFFFFFFull + +struct packet_lin_dma { + __le32 tsize; + __le32 ctl; + __le64 src_addr; + __le64 dst_addr; +}; + +struct packet_arb_point { + __le32 cfg; + __le32 ctl; +}; + +struct packet_repeat { + __le32 cfg; + __le32 ctl; +}; + +struct packet_wait { + __le32 cfg; + __le32 ctl; +}; + +struct packet_load_and_exe { + __le32 cfg; + __le32 ctl; + __le64 src_addr; +}; + +struct packet_cp_dma { + __le32 tsize; + __le32 ctl; + __le64 src_addr; +}; + +#endif /* GAUDI_PACKETS_H */ diff --git a/drivers/misc/habanalabs/include/gaudi/gaudi_reg_map.h b/drivers/misc/habanalabs/include/gaudi/gaudi_reg_map.h new file mode 100644 index 000000000000..f25c60a2c243 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/gaudi_reg_map.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2019-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDI_REG_MAP_H_ +#define GAUDI_REG_MAP_H_ + +/* + * PSOC scratch-pad registers + */ +#define mmHW_STATE mmPSOC_GLOBAL_CONF_SCRATCHPAD_0 +#define mmCPU_CMD_STATUS_TO_HOST mmPSOC_GLOBAL_CONF_SCRATCHPAD_23 +#define mmCPU_BOOT_ERR0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_24 +#define mmCPU_BOOT_ERR1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_25 +#define mmUPD_STS mmPSOC_GLOBAL_CONF_SCRATCHPAD_26 +#define mmUPD_CMD mmPSOC_GLOBAL_CONF_SCRATCHPAD_27 +#define mmPREBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_28 +#define mmUBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_29 +#define mmRDWR_TEST mmPSOC_GLOBAL_CONF_SCRATCHPAD_30 +#define mmBTL_ID mmPSOC_GLOBAL_CONF_SCRATCHPAD_31 +#define mmPREBOOT_PCIE_EN mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_1 +#define mmUPD_PENDING_STS mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_3 + +#endif /* GAUDI_REG_MAP_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/goya_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/goya_masks.h index 3c44ef3a23ed..067489bd048e 100644 --- a/drivers/misc/habanalabs/include/goya/asic_reg/goya_masks.h +++ b/drivers/misc/habanalabs/include/goya/asic_reg/goya_masks.h @@ -55,8 +55,7 @@ (1 << DMA_QM_0_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT) | \ (1 << DMA_QM_0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ (1 << DMA_QM_0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ - (1 << DMA_QM_0_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \ - (1 << DMA_QM_0_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT)) + (1 << DMA_QM_0_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT)) #define QMAN_MME_ENABLE (\ (1 << MME_QM_GLBL_CFG0_PQF_EN_SHIFT) | \ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/goya_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/goya_regs.h index fce490e6a231..ce65c9da5c60 100644 --- a/drivers/misc/habanalabs/include/goya/asic_reg/goya_regs.h +++ b/drivers/misc/habanalabs/include/goya/asic_reg/goya_regs.h @@ -18,6 +18,7 @@ #include "psoc_mme_pll_regs.h" #include "psoc_pci_pll_regs.h" #include "psoc_emmc_pll_regs.h" +#include "psoc_timestamp_regs.h" #include "cpu_if_regs.h" #include "cpu_ca53_cfg_regs.h" #include "cpu_pll_regs.h" diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/psoc_timestamp_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_timestamp_regs.h new file mode 100644 index 000000000000..9ce24597d4b0 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_timestamp_regs.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_TIMESTAMP_REGS_H_ +#define ASIC_REG_PSOC_TIMESTAMP_REGS_H_ + +/* + ***************************************** + * PSOC_TIMESTAMP (Prototype: TIMESTAMP) + ***************************************** + */ + +#define mmPSOC_TIMESTAMP_CNTCR 0xC49000 + +#define mmPSOC_TIMESTAMP_CNTSR 0xC49004 + +#define mmPSOC_TIMESTAMP_CNTCVL 0xC49008 + +#define mmPSOC_TIMESTAMP_CNTCVU 0xC4900C + +#define mmPSOC_TIMESTAMP_CNTFID0 0xC49020 + +#define mmPSOC_TIMESTAMP_PIDR4 0xC49FD0 + +#define mmPSOC_TIMESTAMP_PIDR5 0xC49FD4 + +#define mmPSOC_TIMESTAMP_PIDR6 0xC49FD8 + +#define mmPSOC_TIMESTAMP_PIDR7 0xC49FDC + +#define mmPSOC_TIMESTAMP_PIDR0 0xC49FE0 + +#define mmPSOC_TIMESTAMP_PIDR1 0xC49FE4 + +#define mmPSOC_TIMESTAMP_PIDR2 0xC49FE8 + +#define mmPSOC_TIMESTAMP_PIDR3 0xC49FEC + +#define mmPSOC_TIMESTAMP_CIDR0 0xC49FF0 + +#define mmPSOC_TIMESTAMP_CIDR1 0xC49FF4 + +#define mmPSOC_TIMESTAMP_CIDR2 0xC49FF8 + +#define mmPSOC_TIMESTAMP_CIDR3 0xC49FFC + +#endif /* ASIC_REG_PSOC_TIMESTAMP_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/goya_reg_map.h b/drivers/misc/habanalabs/include/goya/goya_reg_map.h index 08061282cd9c..0195f62d7254 100644 --- a/drivers/misc/habanalabs/include/goya/goya_reg_map.h +++ b/drivers/misc/habanalabs/include/goya/goya_reg_map.h @@ -11,27 +11,30 @@ /* * PSOC scratch-pad registers */ -#define mmCPU_PQ_BASE_ADDR_LOW mmPSOC_GLOBAL_CONF_SCRATCHPAD_0 -#define mmCPU_PQ_BASE_ADDR_HIGH mmPSOC_GLOBAL_CONF_SCRATCHPAD_1 -#define mmCPU_EQ_BASE_ADDR_LOW mmPSOC_GLOBAL_CONF_SCRATCHPAD_2 -#define mmCPU_EQ_BASE_ADDR_HIGH mmPSOC_GLOBAL_CONF_SCRATCHPAD_3 -#define mmCPU_EQ_LENGTH mmPSOC_GLOBAL_CONF_SCRATCHPAD_4 -#define mmCPU_PQ_LENGTH mmPSOC_GLOBAL_CONF_SCRATCHPAD_5 -#define mmCPU_EQ_CI mmPSOC_GLOBAL_CONF_SCRATCHPAD_6 -#define mmCPU_PQ_INIT_STATUS mmPSOC_GLOBAL_CONF_SCRATCHPAD_7 -#define mmCPU_CQ_BASE_ADDR_LOW mmPSOC_GLOBAL_CONF_SCRATCHPAD_8 -#define mmCPU_CQ_BASE_ADDR_HIGH mmPSOC_GLOBAL_CONF_SCRATCHPAD_9 -#define mmCPU_CQ_LENGTH mmPSOC_GLOBAL_CONF_SCRATCHPAD_10 -#define mmCPU_BOOT_ERR0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_24 -#define mmCPU_BOOT_ERR1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_25 -#define mmUPD_STS mmPSOC_GLOBAL_CONF_SCRATCHPAD_26 -#define mmUPD_CMD mmPSOC_GLOBAL_CONF_SCRATCHPAD_27 -#define mmPREBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_28 -#define mmUBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_29 -#define mmRDWR_TEST mmPSOC_GLOBAL_CONF_SCRATCHPAD_30 -#define mmBTL_ID mmPSOC_GLOBAL_CONF_SCRATCHPAD_31 +#define mmCPU_PQ_BASE_ADDR_LOW mmPSOC_GLOBAL_CONF_SCRATCHPAD_0 +#define mmCPU_PQ_BASE_ADDR_HIGH mmPSOC_GLOBAL_CONF_SCRATCHPAD_1 +#define mmCPU_EQ_BASE_ADDR_LOW mmPSOC_GLOBAL_CONF_SCRATCHPAD_2 +#define mmCPU_EQ_BASE_ADDR_HIGH mmPSOC_GLOBAL_CONF_SCRATCHPAD_3 +#define mmCPU_EQ_LENGTH mmPSOC_GLOBAL_CONF_SCRATCHPAD_4 +#define mmCPU_PQ_LENGTH mmPSOC_GLOBAL_CONF_SCRATCHPAD_5 +#define mmCPU_EQ_CI mmPSOC_GLOBAL_CONF_SCRATCHPAD_6 +#define mmCPU_PQ_INIT_STATUS mmPSOC_GLOBAL_CONF_SCRATCHPAD_7 +#define mmCPU_CQ_BASE_ADDR_LOW mmPSOC_GLOBAL_CONF_SCRATCHPAD_8 +#define mmCPU_CQ_BASE_ADDR_HIGH mmPSOC_GLOBAL_CONF_SCRATCHPAD_9 +#define mmCPU_CQ_LENGTH mmPSOC_GLOBAL_CONF_SCRATCHPAD_10 +#define mmCPU_CMD_STATUS_TO_HOST mmPSOC_GLOBAL_CONF_SCRATCHPAD_23 +#define mmCPU_BOOT_ERR0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_24 +#define mmCPU_BOOT_ERR1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_25 +#define mmUPD_STS mmPSOC_GLOBAL_CONF_SCRATCHPAD_26 +#define mmUPD_CMD mmPSOC_GLOBAL_CONF_SCRATCHPAD_27 +#define mmPREBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_28 +#define mmUBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_29 +#define mmRDWR_TEST mmPSOC_GLOBAL_CONF_SCRATCHPAD_30 +#define mmBTL_ID mmPSOC_GLOBAL_CONF_SCRATCHPAD_31 -#define mmHW_STATE mmPSOC_GLOBAL_CONF_APP_STATUS +#define mmHW_STATE mmPSOC_GLOBAL_CONF_APP_STATUS #define mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS mmPSOC_GLOBAL_CONF_WARM_REBOOT +#define mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU mmPSOC_GLOBAL_CONF_UBOOT_MAGIC +#define mmUPD_PENDING_STS mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_3 #endif /* GOYA_REG_MAP_H_ */ diff --git a/drivers/misc/habanalabs/include/hl_boot_if.h b/drivers/misc/habanalabs/include/hl_boot_if.h index f7992a69fd3a..c22d134e73af 100644 --- a/drivers/misc/habanalabs/include/hl_boot_if.h +++ b/drivers/misc/habanalabs/include/hl_boot_if.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright 2018 HabanaLabs, Ltd. + * Copyright 2018-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ @@ -9,8 +9,47 @@ #define HL_BOOT_IF_H #define LKD_HARD_RESET_MAGIC 0xED7BD694 +#define HL_POWER9_HOST_MAGIC 0x1DA30009 -/* CPU error bits in BOOT_ERROR registers */ +#define BOOT_FIT_SRAM_OFFSET 0x200000 + +/* + * CPU error bits in BOOT_ERROR registers + * + * CPU_BOOT_ERR0_DRAM_INIT_FAIL DRAM initialization failed. + * DRAM is not reliable to use. + * + * CPU_BOOT_ERR0_FIT_CORRUPTED FIT data integrity verification of the + * image provided by the host has failed. + * + * CPU_BOOT_ERR0_TS_INIT_FAIL Thermal Sensor initialization failed. + * Boot continues as usual, but keep in + * mind this is a warning. + * + * CPU_BOOT_ERR0_DRAM_SKIPPED DRAM initialization has been skipped. + * Skipping DRAM initialization has been + * requested (e.g. strap, command, etc.) + * and FW skipped the DRAM initialization. + * Host can initialize the DRAM. + * + * CPU_BOOT_ERR0_BMC_WAIT_SKIPPED Waiting for BMC data will be skipped. + * Meaning the BMC data might not be + * available until reset. + * + * CPU_BOOT_ERR0_NIC_DATA_NOT_RDY NIC data from BMC is not ready. + * BMC has not provided the NIC data yet. + * Once provided this bit will be cleared. + * + * CPU_BOOT_ERR0_NIC_FW_FAIL NIC FW loading failed. + * The NIC FW loading and initialization + * failed. This means NICs are not usable. + * + * CPU_BOOT_ERR0_ENABLED Error registers enabled. + * This is a main indication that the + * running FW populates the error + * registers. Meaning the error bits are + * not garbage, but actual error statuses. + */ #define CPU_BOOT_ERR0_DRAM_INIT_FAIL (1 << 0) #define CPU_BOOT_ERR0_FIT_CORRUPTED (1 << 1) #define CPU_BOOT_ERR0_TS_INIT_FAIL (1 << 2) @@ -27,22 +66,33 @@ enum cpu_boot_status { CPU_BOOT_STATUS_SRAM_AVAIL = 3, CPU_BOOT_STATUS_IN_BTL = 4, /* BTL is H/W FSM */ CPU_BOOT_STATUS_IN_PREBOOT = 5, - CPU_BOOT_STATUS_IN_SPL = 6, + CPU_BOOT_STATUS_IN_SPL, /* deprecated - not reported */ CPU_BOOT_STATUS_IN_UBOOT = 7, CPU_BOOT_STATUS_DRAM_INIT_FAIL, /* deprecated - will be removed */ CPU_BOOT_STATUS_FIT_CORRUPTED, /* deprecated - will be removed */ + /* U-Boot console prompt activated, commands are not processed */ CPU_BOOT_STATUS_UBOOT_NOT_READY = 10, + /* Finished NICs init, reported after DRAM and NICs */ CPU_BOOT_STATUS_NIC_FW_RDY = 11, CPU_BOOT_STATUS_TS_INIT_FAIL, /* deprecated - will be removed */ CPU_BOOT_STATUS_DRAM_SKIPPED, /* deprecated - will be removed */ CPU_BOOT_STATUS_BMC_WAITING_SKIPPED, /* deprecated - will be removed */ + /* Last boot loader progress status, ready to receive commands */ CPU_BOOT_STATUS_READY_TO_BOOT = 15, + CPU_BOOT_STATUS_WAITING_FOR_BOOT_FIT = 16, }; enum kmd_msg { KMD_MSG_NA = 0, KMD_MSG_GOTO_WFE, - KMD_MSG_FIT_RDY + KMD_MSG_FIT_RDY, + KMD_MSG_SKIP_BMC, +}; + +enum cpu_msg_status { + CPU_MSG_CLR = 0, + CPU_MSG_OK, + CPU_MSG_ERR, }; #endif /* HL_BOOT_IF_H */ diff --git a/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_general.h b/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_general.h index a6851a9d3f03..468bb045fbd1 100644 --- a/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_general.h +++ b/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_general.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright 2016-2018 HabanaLabs, Ltd. + * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ diff --git a/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_v1_1.h b/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_v1_1.h new file mode 100644 index 000000000000..b2a9570583ac --- /dev/null +++ b/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_v1_1.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef INCLUDE_MMU_V1_1_H_ +#define INCLUDE_MMU_V1_1_H_ + +#define MMU_ASID 0xC12004 +#define MMU_HOP0_PA43_12 0xC12008 +#define MMU_HOP0_PA49_44 0xC1200C +#define MMU_BUSY 0xC12000 + +#endif /* INCLUDE_MMU_V1_1_H_ */ diff --git a/drivers/misc/habanalabs/memory.c b/drivers/misc/habanalabs/memory.c index a72f766ca470..47da84a17719 100644 --- a/drivers/misc/habanalabs/memory.c +++ b/drivers/misc/habanalabs/memory.c @@ -886,6 +886,7 @@ static int map_device_va(struct hl_ctx *ctx, struct hl_mem_in *args, vm_type = (enum vm_type_t *) userptr; hint_addr = args->map_host.hint_addr; + handle = phys_pg_pack->handle; } else { handle = lower_32_bits(args->map_device.handle); @@ -954,10 +955,17 @@ static int map_device_va(struct hl_ctx *ctx, struct hl_mem_in *args, goto map_err; } - hdev->asic_funcs->mmu_invalidate_cache(hdev, false, *vm_type); + rc = hdev->asic_funcs->mmu_invalidate_cache(hdev, false, *vm_type); mutex_unlock(&ctx->mmu_lock); + if (rc) { + dev_err(hdev->dev, + "mapping handle %u failed due to MMU cache invalidation\n", + handle); + goto map_err; + } + ret_vaddr += phys_pg_pack->offset; hnode->ptr = vm_type; @@ -1015,7 +1023,7 @@ static int unmap_device_va(struct hl_ctx *ctx, u64 vaddr, bool ctx_free) struct hl_va_range *va_range; enum vm_type_t *vm_type; bool is_userptr; - int rc; + int rc = 0; /* protect from double entrance */ mutex_lock(&ctx->mem_hash_lock); @@ -1083,21 +1091,34 @@ static int unmap_device_va(struct hl_ctx *ctx, u64 vaddr, bool ctx_free) * at the loop end rather than for each iteration */ if (!ctx_free) - hdev->asic_funcs->mmu_invalidate_cache(hdev, true, *vm_type); + rc = hdev->asic_funcs->mmu_invalidate_cache(hdev, true, + *vm_type); mutex_unlock(&ctx->mmu_lock); /* - * No point in maintaining the free VA block list if the context is - * closing as the list will be freed anyway + * If the context is closing we don't need to check for the MMU cache + * invalidation return code and update the VA free list as in this flow + * we invalidate the MMU cache outside of this unmap function and the VA + * free list will be freed anyway. */ if (!ctx_free) { - rc = add_va_block(hdev, va_range, vaddr, - vaddr + phys_pg_pack->total_size - 1); + int tmp_rc; + if (rc) + dev_err(hdev->dev, + "unmapping vaddr 0x%llx failed due to MMU cache invalidation\n", + vaddr); + + tmp_rc = add_va_block(hdev, va_range, vaddr, + vaddr + phys_pg_pack->total_size - 1); + if (tmp_rc) { dev_warn(hdev->dev, "add va block failed for vaddr: 0x%llx\n", vaddr); + if (!rc) + rc = tmp_rc; + } } atomic_dec(&phys_pg_pack->mapping_cnt); @@ -1108,7 +1129,7 @@ static int unmap_device_va(struct hl_ctx *ctx, u64 vaddr, bool ctx_free) dma_unmap_host_va(hdev, userptr); } - return 0; + return rc; mapping_cnt_err: if (is_userptr) diff --git a/drivers/misc/habanalabs/pci.c b/drivers/misc/habanalabs/pci.c index c98d88c7a5c6..9f634ef6f5b3 100644 --- a/drivers/misc/habanalabs/pci.c +++ b/drivers/misc/habanalabs/pci.c @@ -267,6 +267,12 @@ int hl_pci_init_iatu(struct hl_device *hdev, u64 sram_base_address, /* Enable + Bar match + match enable */ rc |= hl_pci_iatu_write(hdev, 0x104, 0xC0080000); + /* Return the DBI window to the default location */ + rc |= hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0); + rc |= hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr + 4, 0); + + hdev->asic_funcs->set_dma_mask_from_fw(hdev); + /* Point to DRAM */ if (!hdev->asic_funcs->set_dram_bar_base) return -EINVAL; @@ -274,7 +280,6 @@ int hl_pci_init_iatu(struct hl_device *hdev, u64 sram_base_address, U64_MAX) return -EIO; - /* Outbound Region 0 - Point to Host */ host_phys_end_addr = host_phys_base_address + host_phys_size - 1; rc |= hl_pci_iatu_write(hdev, 0x008, @@ -283,7 +288,12 @@ int hl_pci_init_iatu(struct hl_device *hdev, u64 sram_base_address, upper_32_bits(host_phys_base_address)); rc |= hl_pci_iatu_write(hdev, 0x010, lower_32_bits(host_phys_end_addr)); rc |= hl_pci_iatu_write(hdev, 0x014, 0); - rc |= hl_pci_iatu_write(hdev, 0x018, 0); + + if ((hdev->power9_64bit_dma_enable) && (hdev->dma_mask == 64)) + rc |= hl_pci_iatu_write(hdev, 0x018, 0x08000000); + else + rc |= hl_pci_iatu_write(hdev, 0x018, 0); + rc |= hl_pci_iatu_write(hdev, 0x020, upper_32_bits(host_phys_end_addr)); /* Increase region size */ rc |= hl_pci_iatu_write(hdev, 0x000, 0x00002000); @@ -310,41 +320,25 @@ int hl_pci_init_iatu(struct hl_device *hdev, u64 sram_base_address, * * Return: 0 on success, non-zero for failure. */ -int hl_pci_set_dma_mask(struct hl_device *hdev, u8 dma_mask) +static int hl_pci_set_dma_mask(struct hl_device *hdev) { struct pci_dev *pdev = hdev->pdev; int rc; /* set DMA mask */ - rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(dma_mask)); + rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(hdev->dma_mask)); if (rc) { - dev_warn(hdev->dev, + dev_err(hdev->dev, "Failed to set pci dma mask to %d bits, error %d\n", - dma_mask, rc); - - dma_mask = hdev->dma_mask; - - rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(dma_mask)); - if (rc) { - dev_err(hdev->dev, - "Failed to set pci dma mask to %d bits, error %d\n", - dma_mask, rc); - return rc; - } + hdev->dma_mask, rc); + return rc; } - /* - * We managed to set the dma mask, so update the dma mask field. If - * the set to the coherent mask will fail with that mask, we will - * fail the entire function - */ - hdev->dma_mask = dma_mask; - - rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(dma_mask)); + rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(hdev->dma_mask)); if (rc) { dev_err(hdev->dev, "Failed to set pci consistent dma mask to %d bits, error %d\n", - dma_mask, rc); + hdev->dma_mask, rc); return rc; } @@ -354,21 +348,16 @@ int hl_pci_set_dma_mask(struct hl_device *hdev, u8 dma_mask) /** * hl_pci_init() - PCI initialization code. * @hdev: Pointer to hl_device structure. - * @dma_mask: number of bits for the requested dma mask. * * Set DMA masks, initialize the PCI controller and map the PCI BARs. * * Return: 0 on success, non-zero for failure. */ -int hl_pci_init(struct hl_device *hdev, u8 dma_mask) +int hl_pci_init(struct hl_device *hdev) { struct pci_dev *pdev = hdev->pdev; int rc; - rc = hl_pci_set_dma_mask(hdev, dma_mask); - if (rc) - return rc; - if (hdev->reset_pcilink) hl_pci_reset_link_through_bridge(hdev); @@ -380,17 +369,21 @@ int hl_pci_init(struct hl_device *hdev, u8 dma_mask) pci_set_master(pdev); + rc = hdev->asic_funcs->pci_bars_map(hdev); + if (rc) { + dev_err(hdev->dev, "Failed to initialize PCI BARs\n"); + goto disable_device; + } + rc = hdev->asic_funcs->init_iatu(hdev); if (rc) { dev_err(hdev->dev, "Failed to initialize iATU\n"); goto disable_device; } - rc = hdev->asic_funcs->pci_bars_map(hdev); - if (rc) { - dev_err(hdev->dev, "Failed to initialize PCI BARs\n"); + rc = hl_pci_set_dma_mask(hdev); + if (rc) goto disable_device; - } return 0; diff --git a/drivers/misc/habanalabs/sysfs.c b/drivers/misc/habanalabs/sysfs.c index 4cd622b017b9..5d78d5e1c782 100644 --- a/drivers/misc/habanalabs/sysfs.c +++ b/drivers/misc/habanalabs/sysfs.c @@ -183,6 +183,13 @@ static ssize_t soft_reset_store(struct device *dev, goto out; } + if (!hdev->supports_soft_reset) { + dev_err(hdev->dev, "Device does not support soft-reset\n"); + goto out; + } + + dev_warn(hdev->dev, "Soft-Reset requested through sysfs\n"); + hl_device_reset(hdev, false, false); out: @@ -204,6 +211,8 @@ static ssize_t hard_reset_store(struct device *dev, goto out; } + dev_warn(hdev->dev, "Hard-Reset requested through sysfs\n"); + hl_device_reset(hdev, true, false); out: @@ -220,6 +229,9 @@ static ssize_t device_type_show(struct device *dev, case ASIC_GOYA: str = "GOYA"; break; + case ASIC_GAUDI: + str = "GAUDI"; + break; default: dev_err(hdev->dev, "Unrecognized ASIC type %d\n", hdev->asic_type); @@ -406,7 +418,10 @@ int hl_sysfs_init(struct hl_device *hdev) { int rc; - hdev->pm_mng_profile = PM_AUTO; + if (hdev->asic_type == ASIC_GOYA) + hdev->pm_mng_profile = PM_AUTO; + else + hdev->pm_mng_profile = PM_MANUAL; hdev->max_power = hdev->asic_prop.max_power_default; hdev->asic_funcs->add_device_attr(hdev, &hl_dev_clks_attr_group); diff --git a/drivers/misc/lkdtm/bugs.c b/drivers/misc/lkdtm/bugs.c index 886459e0ddd9..736675f0a246 100644 --- a/drivers/misc/lkdtm/bugs.c +++ b/drivers/misc/lkdtm/bugs.c @@ -208,7 +208,7 @@ void lkdtm_OVERFLOW_UNSIGNED(void) ignored = value; } -/* Intentially using old-style flex array definition of 1 byte. */ +/* Intentionally using old-style flex array definition of 1 byte. */ struct array_bounds_flex_array { int one; int two; diff --git a/drivers/misc/mic/scif/scif_nodeqp.c b/drivers/misc/mic/scif/scif_nodeqp.c index fcd999f50d14..ea084626fe11 100644 --- a/drivers/misc/mic/scif/scif_nodeqp.c +++ b/drivers/misc/mic/scif/scif_nodeqp.c @@ -660,7 +660,7 @@ int scif_nodeqp_send(struct scif_dev *scifdev, struct scifmsg *msg) struct device *spdev = NULL; if (msg->uop > SCIF_EXIT_ACK) { - /* Dont send messages once the exit flow has begun */ + /* Don't send messages once the exit flow has begun */ if (OP_IDLE != scifdev->exit) return -ENODEV; spdev = scif_get_peer_dev(scifdev); diff --git a/drivers/misc/mic/scif/scif_rma.c b/drivers/misc/mic/scif/scif_rma.c index 01e27682ea30..406cd5abfa72 100644 --- a/drivers/misc/mic/scif/scif_rma.c +++ b/drivers/misc/mic/scif/scif_rma.c @@ -113,14 +113,17 @@ static int scif_destroy_pinned_pages(struct scif_pinned_pages *pin) int writeable = pin->prot & SCIF_PROT_WRITE; int kernel = SCIF_MAP_KERNEL & pin->map_flags; - for (j = 0; j < pin->nr_pages; j++) { - if (pin->pages[j] && !kernel) { - if (writeable) - SetPageDirty(pin->pages[j]); - put_page(pin->pages[j]); + if (kernel) { + for (j = 0; j < pin->nr_pages; j++) { + if (pin->pages[j] && !kernel) { + if (writeable) + set_page_dirty_lock(pin->pages[j]); + put_page(pin->pages[j]); + } } - } - + } else + unpin_user_pages_dirty_lock(pin->pages, pin->nr_pages, + writeable); scif_free(pin->pages, pin->nr_pages * sizeof(*pin->pages)); scif_free(pin, sizeof(*pin)); @@ -1375,7 +1378,7 @@ retry: } } - pinned_pages->nr_pages = get_user_pages_fast( + pinned_pages->nr_pages = pin_user_pages_fast( (u64)addr, nr_pages, (prot & SCIF_PROT_WRITE) ? FOLL_WRITE : 0, @@ -1385,11 +1388,8 @@ retry: if (ulimit) __scif_dec_pinned_vm_lock(mm, nr_pages); /* Roll back any pinned pages */ - for (i = 0; i < pinned_pages->nr_pages; i++) { - if (pinned_pages->pages[i]) - put_page( - pinned_pages->pages[i]); - } + unpin_user_pages(pinned_pages->pages, + pinned_pages->nr_pages); prot &= ~SCIF_PROT_WRITE; try_upgrade = false; goto retry; diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c index ef5a1af6bab7..41c40971979e 100644 --- a/drivers/misc/pci_endpoint_test.c +++ b/drivers/misc/pci_endpoint_test.c @@ -73,6 +73,8 @@ #define is_am654_pci_dev(pdev) \ ((pdev)->device == PCI_DEVICE_ID_TI_AM654) +#define PCI_DEVICE_ID_RENESAS_R8A774C0 0x002d + static DEFINE_IDA(pci_endpoint_test_ida); #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \ @@ -942,6 +944,8 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = { { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654), .driver_data = (kernel_ulong_t)&am654_data }, + { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0), + }, { } }; MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl); diff --git a/drivers/misc/sgi-xp/xpc_main.c b/drivers/misc/sgi-xp/xpc_main.c index 79a963105983..d5e097cd556d 100644 --- a/drivers/misc/sgi-xp/xpc_main.c +++ b/drivers/misc/sgi-xp/xpc_main.c @@ -59,16 +59,16 @@ /* define two XPC debug device structures to be used with dev_dbg() et al */ -struct device_driver xpc_dbg_name = { +static struct device_driver xpc_dbg_name = { .name = "xpc" }; -struct device xpc_part_dbg_subname = { +static struct device xpc_part_dbg_subname = { .init_name = "", /* set to "part" at xpc_init() time */ .driver = &xpc_dbg_name }; -struct device xpc_chan_dbg_subname = { +static struct device xpc_chan_dbg_subname = { .init_name = "", /* set to "chan" at xpc_init() time */ .driver = &xpc_dbg_name }; @@ -1217,7 +1217,7 @@ xpc_system_die(struct notifier_block *nb, unsigned long event, void *_die_args) return NOTIFY_DONE; } -int __init +static int __init xpc_init(void) { int ret; @@ -1319,7 +1319,7 @@ out_1: module_init(xpc_init); -void __exit +static void __exit xpc_exit(void) { xpc_do_exit(xpUnloading); diff --git a/drivers/misc/sgi-xp/xpnet.c b/drivers/misc/sgi-xp/xpnet.c index ada94e6a3c91..837d6c3fe69c 100644 --- a/drivers/misc/sgi-xp/xpnet.c +++ b/drivers/misc/sgi-xp/xpnet.c @@ -96,7 +96,7 @@ struct xpnet_pending_msg { atomic_t use_count; }; -struct net_device *xpnet_device; +static struct net_device *xpnet_device; /* * When we are notified of other partitions activating, we add them to @@ -131,16 +131,16 @@ static DEFINE_SPINLOCK(xpnet_broadcast_lock); /* Define the XPNET debug device structures to be used with dev_dbg() et al */ -struct device_driver xpnet_dbg_name = { +static struct device_driver xpnet_dbg_name = { .name = "xpnet" }; -struct device xpnet_dbg_subname = { +static struct device xpnet_dbg_subname = { .init_name = "", /* set to "" */ .driver = &xpnet_dbg_name }; -struct device *xpnet = &xpnet_dbg_subname; +static struct device *xpnet = &xpnet_dbg_subname; /* * Packet was recevied by XPC and forwarded to us. diff --git a/drivers/misc/xilinx_sdfec.c b/drivers/misc/xilinx_sdfec.c index 71bbaa56bdb5..92291292756a 100644 --- a/drivers/misc/xilinx_sdfec.c +++ b/drivers/misc/xilinx_sdfec.c @@ -602,10 +602,10 @@ static int xsdfec_table_write(struct xsdfec_dev *xsdfec, u32 offset, const u32 depth) { u32 reg = 0; - u32 res; - u32 n, i; + int res, i, nr_pages; + u32 n; u32 *addr = NULL; - struct page *page[MAX_NUM_PAGES]; + struct page *pages[MAX_NUM_PAGES]; /* * Writes that go beyond the length of @@ -622,15 +622,21 @@ static int xsdfec_table_write(struct xsdfec_dev *xsdfec, u32 offset, if ((len * XSDFEC_REG_WIDTH_JUMP) % PAGE_SIZE) n += 1; - res = get_user_pages_fast((unsigned long)src_ptr, n, 0, page); - if (res < n) { - for (i = 0; i < res; i++) - put_page(page[i]); + if (WARN_ON_ONCE(n > INT_MAX)) + return -EINVAL; + + nr_pages = n; + + res = pin_user_pages_fast((unsigned long)src_ptr, nr_pages, 0, pages); + if (res < nr_pages) { + if (res > 0) + unpin_user_pages(pages, res); + return -EINVAL; } - for (i = 0; i < n; i++) { - addr = kmap(page[i]); + for (i = 0; i < nr_pages; i++) { + addr = kmap(pages[i]); do { xsdfec_regwrite(xsdfec, base_addr + ((offset + reg) * @@ -639,9 +645,9 @@ static int xsdfec_table_write(struct xsdfec_dev *xsdfec, u32 offset, reg++; } while ((reg < len) && ((reg * XSDFEC_REG_WIDTH_JUMP) % PAGE_SIZE)); - put_page(page[i]); + unpin_user_page(pages[i]); } - return reg; + return 0; } static int xsdfec_add_ldpc(struct xsdfec_dev *xsdfec, void __user *arg) @@ -649,14 +655,9 @@ static int xsdfec_add_ldpc(struct xsdfec_dev *xsdfec, void __user *arg) struct xsdfec_ldpc_params *ldpc; int ret, n; - ldpc = kzalloc(sizeof(*ldpc), GFP_KERNEL); - if (!ldpc) - return -ENOMEM; - - if (copy_from_user(ldpc, arg, sizeof(*ldpc))) { - ret = -EFAULT; - goto err_out; - } + ldpc = memdup_user(arg, sizeof(*ldpc)); + if (IS_ERR(ldpc)) + return PTR_ERR(ldpc); if (xsdfec->config.code == XSDFEC_TURBO_CODE) { ret = -EIO; @@ -720,8 +721,6 @@ static int xsdfec_add_ldpc(struct xsdfec_dev *xsdfec, void __user *arg) ret = xsdfec_table_write(xsdfec, 4 * ldpc->qc_off, ldpc->qc_table, ldpc->nqc, XSDFEC_LDPC_QC_TABLE_ADDR_BASE, XSDFEC_QC_TABLE_DEPTH); - if (ret > 0) - ret = 0; err_out: kfree(ldpc); return ret; @@ -1484,25 +1483,7 @@ static struct platform_driver xsdfec_driver = { .remove = xsdfec_remove, }; -static int __init xsdfec_init(void) -{ - int err; - - err = platform_driver_register(&xsdfec_driver); - if (err < 0) { - pr_err("%s Unabled to register SDFEC driver", __func__); - return err; - } - return 0; -} - -static void __exit xsdfec_exit(void) -{ - platform_driver_unregister(&xsdfec_driver); -} - -module_init(xsdfec_init); -module_exit(xsdfec_exit); +module_platform_driver(xsdfec_driver); MODULE_AUTHOR("Xilinx, Inc"); MODULE_DESCRIPTION("Xilinx SD-FEC16 Driver"); diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c index 2a4c8a2f3e64..db9b544465cd 100644 --- a/drivers/mmc/host/sdhci-of-arasan.c +++ b/drivers/mmc/host/sdhci-of-arasan.c @@ -123,10 +123,6 @@ struct sdhci_arasan_clk_data { void *clk_of_data; }; -struct sdhci_arasan_zynqmp_clk_data { - const struct zynqmp_eemi_ops *eemi_ops; -}; - /** * struct sdhci_arasan_data - Arasan Controller Data * @@ -599,9 +595,6 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct clk_hw *hw, int degrees) struct sdhci_arasan_data *sdhci_arasan = container_of(clk_data, struct sdhci_arasan_data, clk_data); struct sdhci_host *host = sdhci_arasan->host; - struct sdhci_arasan_zynqmp_clk_data *zynqmp_clk_data = - clk_data->clk_of_data; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_clk_data->eemi_ops; const char *clk_name = clk_hw_get_name(hw); u32 node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1; u8 tap_delay, tap_max = 0; @@ -641,8 +634,7 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct clk_hw *hw, int degrees) tap_delay = (degrees * tap_max) / 360; /* Set the Clock Phase */ - ret = eemi_ops->ioctl(node_id, IOCTL_SET_SD_TAPDELAY, - PM_TAPDELAY_OUTPUT, tap_delay, NULL); + ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_OUTPUT, tap_delay); if (ret) pr_err("Error setting Output Tap Delay\n"); @@ -671,9 +663,6 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct clk_hw *hw, int degrees) struct sdhci_arasan_data *sdhci_arasan = container_of(clk_data, struct sdhci_arasan_data, clk_data); struct sdhci_host *host = sdhci_arasan->host; - struct sdhci_arasan_zynqmp_clk_data *zynqmp_clk_data = - clk_data->clk_of_data; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_clk_data->eemi_ops; const char *clk_name = clk_hw_get_name(hw); u32 node_id = !strcmp(clk_name, "clk_in_sd0") ? NODE_SD_0 : NODE_SD_1; u8 tap_delay, tap_max = 0; @@ -713,8 +702,7 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct clk_hw *hw, int degrees) tap_delay = (degrees * tap_max) / 360; /* Set the Clock Phase */ - ret = eemi_ops->ioctl(node_id, IOCTL_SET_SD_TAPDELAY, - PM_TAPDELAY_INPUT, tap_delay, NULL); + ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_INPUT, tap_delay); if (ret) pr_err("Error setting Input Tap Delay\n"); @@ -874,11 +862,6 @@ static const struct clk_ops versal_sampleclk_ops = { static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 deviceid) { - struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); - struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); - struct sdhci_arasan_zynqmp_clk_data *zynqmp_clk_data = - sdhci_arasan->clk_data.clk_of_data; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_clk_data->eemi_ops; u16 clk; clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); @@ -886,8 +869,7 @@ static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 deviceid) sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); /* Issue DLL Reset */ - eemi_ops->ioctl(deviceid, IOCTL_SD_DLL_RESET, - PM_DLL_RESET_PULSE, 0, NULL); + zynqmp_pm_sd_dll_reset(deviceid, PM_DLL_RESET_PULSE); clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); @@ -1617,20 +1599,6 @@ static int sdhci_arasan_probe(struct platform_device *pdev) goto clk_disable_all; if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) { - struct sdhci_arasan_zynqmp_clk_data *zynqmp_clk_data; - const struct zynqmp_eemi_ops *eemi_ops; - - zynqmp_clk_data = devm_kzalloc(&pdev->dev, - sizeof(*zynqmp_clk_data), - GFP_KERNEL); - eemi_ops = zynqmp_pm_get_eemi_ops(); - if (IS_ERR(eemi_ops)) { - ret = PTR_ERR(eemi_ops); - goto unreg_clk; - } - - zynqmp_clk_data->eemi_ops = eemi_ops; - sdhci_arasan->clk_data.clk_of_data = zynqmp_clk_data; host->mmc_host_ops.execute_tuning = arasan_zynqmp_execute_tuning; } diff --git a/drivers/ntb/core.c b/drivers/ntb/core.c index 2581ab724c34..f8f75a504a58 100644 --- a/drivers/ntb/core.c +++ b/drivers/ntb/core.c @@ -214,10 +214,8 @@ int ntb_default_port_number(struct ntb_dev *ntb) case NTB_TOPO_B2B_DSD: return NTB_PORT_SEC_DSD; default: - break; + return 0; } - - return -EINVAL; } EXPORT_SYMBOL(ntb_default_port_number); @@ -240,10 +238,8 @@ int ntb_default_peer_port_number(struct ntb_dev *ntb, int pidx) case NTB_TOPO_B2B_DSD: return NTB_PORT_PRI_USD; default: - break; + return 0; } - - return -EINVAL; } EXPORT_SYMBOL(ntb_default_peer_port_number); @@ -315,4 +311,3 @@ static void __exit ntb_driver_exit(void) bus_unregister(&ntb_bus); } module_exit(ntb_driver_exit); - diff --git a/drivers/ntb/hw/amd/ntb_hw_amd.c b/drivers/ntb/hw/amd/ntb_hw_amd.c index 9e310e1ad4d0..88e1db65be02 100644 --- a/drivers/ntb/hw/amd/ntb_hw_amd.c +++ b/drivers/ntb/hw/amd/ntb_hw_amd.c @@ -1191,10 +1191,6 @@ static int amd_ntb_init_pci(struct amd_ntb_dev *ndev, goto err_dma_mask; dev_warn(&pdev->dev, "Cannot DMA consistent highmem\n"); } - rc = dma_coerce_mask_and_coherent(&ndev->ntb.dev, - dma_get_mask(&pdev->dev)); - if (rc) - goto err_dma_mask; ndev->self_mmio = pci_iomap(pdev, 0, 0); if (!ndev->self_mmio) { diff --git a/drivers/ntb/hw/idt/ntb_hw_idt.c b/drivers/ntb/hw/idt/ntb_hw_idt.c index edae52384b8a..d54261f50851 100644 --- a/drivers/ntb/hw/idt/ntb_hw_idt.c +++ b/drivers/ntb/hw/idt/ntb_hw_idt.c @@ -2660,12 +2660,6 @@ static int idt_init_pci(struct idt_ntb_dev *ndev) dev_warn(&pdev->dev, "Cannot set consistent DMA highmem bit mask\n"); } - ret = dma_coerce_mask_and_coherent(&ndev->ntb.dev, - dma_get_mask(&pdev->dev)); - if (ret != 0) { - dev_err(&pdev->dev, "Failed to set NTB device DMA bit mask\n"); - return ret; - } /* * Enable the device advanced error reporting. It's not critical to diff --git a/drivers/ntb/hw/intel/Makefile b/drivers/ntb/hw/intel/Makefile index 60ec8a773eea..f80da0ba15b2 100644 --- a/drivers/ntb/hw/intel/Makefile +++ b/drivers/ntb/hw/intel/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_NTB_INTEL) += ntb_hw_intel.o -ntb_hw_intel-y := ntb_hw_gen1.o ntb_hw_gen3.o +ntb_hw_intel-y := ntb_hw_gen1.o ntb_hw_gen3.o ntb_hw_gen4.o diff --git a/drivers/ntb/hw/intel/ntb_hw_gen1.c b/drivers/ntb/hw/intel/ntb_hw_gen1.c index bb57ec239029..423f9b8fbbcf 100644 --- a/drivers/ntb/hw/intel/ntb_hw_gen1.c +++ b/drivers/ntb/hw/intel/ntb_hw_gen1.c @@ -60,6 +60,7 @@ #include "ntb_hw_intel.h" #include "ntb_hw_gen1.h" #include "ntb_hw_gen3.h" +#include "ntb_hw_gen4.h" #define NTB_NAME "ntb_hw_intel" #define NTB_DESC "Intel(R) PCI-E Non-Transparent Bridge Driver" @@ -762,6 +763,8 @@ static ssize_t ndev_debugfs_read(struct file *filp, char __user *ubuf, return ndev_ntb_debugfs_read(filp, ubuf, count, offp); else if (pdev_is_gen3(ndev->ntb.pdev)) return ndev_ntb3_debugfs_read(filp, ubuf, count, offp); + else if (pdev_is_gen4(ndev->ntb.pdev)) + return ndev_ntb4_debugfs_read(filp, ubuf, count, offp); return -ENXIO; } @@ -1783,10 +1786,6 @@ static int intel_ntb_init_pci(struct intel_ntb_dev *ndev, struct pci_dev *pdev) goto err_dma_mask; dev_warn(&pdev->dev, "Cannot DMA consistent highmem\n"); } - rc = dma_coerce_mask_and_coherent(&ndev->ntb.dev, - dma_get_mask(&pdev->dev)); - if (rc) - goto err_dma_mask; ndev->self_mmio = pci_iomap(pdev, 0, 0); if (!ndev->self_mmio) { @@ -1858,16 +1857,15 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev, int rc, node; node = dev_to_node(&pdev->dev); + ndev = kzalloc_node(sizeof(*ndev), GFP_KERNEL, node); + if (!ndev) { + rc = -ENOMEM; + goto err_ndev; + } + + ndev_init_struct(ndev, pdev); if (pdev_is_gen1(pdev)) { - ndev = kzalloc_node(sizeof(*ndev), GFP_KERNEL, node); - if (!ndev) { - rc = -ENOMEM; - goto err_ndev; - } - - ndev_init_struct(ndev, pdev); - rc = intel_ntb_init_pci(ndev, pdev); if (rc) goto err_init_pci; @@ -1875,17 +1873,8 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev, rc = xeon_init_dev(ndev); if (rc) goto err_init_dev; - } else if (pdev_is_gen3(pdev)) { - ndev = kzalloc_node(sizeof(*ndev), GFP_KERNEL, node); - if (!ndev) { - rc = -ENOMEM; - goto err_ndev; - } - - ndev_init_struct(ndev, pdev); ndev->ntb.ops = &intel_ntb3_ops; - rc = intel_ntb_init_pci(ndev, pdev); if (rc) goto err_init_pci; @@ -1893,7 +1882,15 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev, rc = gen3_init_dev(ndev); if (rc) goto err_init_dev; + } else if (pdev_is_gen4(pdev)) { + ndev->ntb.ops = &intel_ntb4_ops; + rc = intel_ntb_init_pci(ndev, pdev); + if (rc) + goto err_init_pci; + rc = gen4_init_dev(ndev); + if (rc) + goto err_init_dev; } else { rc = -EINVAL; goto err_ndev; @@ -1915,7 +1912,7 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev, err_register: ndev_deinit_debugfs(ndev); - if (pdev_is_gen1(pdev) || pdev_is_gen3(pdev)) + if (pdev_is_gen1(pdev) || pdev_is_gen3(pdev) || pdev_is_gen4(pdev)) xeon_deinit_dev(ndev); err_init_dev: intel_ntb_deinit_pci(ndev); @@ -1931,7 +1928,7 @@ static void intel_ntb_pci_remove(struct pci_dev *pdev) ntb_unregister_device(&ndev->ntb); ndev_deinit_debugfs(ndev); - if (pdev_is_gen1(pdev) || pdev_is_gen3(pdev)) + if (pdev_is_gen1(pdev) || pdev_is_gen3(pdev) || pdev_is_gen4(pdev)) xeon_deinit_dev(ndev); intel_ntb_deinit_pci(ndev); kfree(ndev); @@ -2036,6 +2033,7 @@ static const struct file_operations intel_ntb_debugfs_info = { }; static const struct pci_device_id intel_ntb_pci_tbl[] = { + /* GEN1 */ {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_JSF)}, {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_SNB)}, {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_IVT)}, @@ -2051,7 +2049,12 @@ static const struct pci_device_id intel_ntb_pci_tbl[] = { {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_IVT)}, {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_HSX)}, {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_BDX)}, + + /* GEN3 */ {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_SKX)}, + + /* GEN4 */ + {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_ICX)}, {0} }; MODULE_DEVICE_TABLE(pci, intel_ntb_pci_tbl); diff --git a/drivers/ntb/hw/intel/ntb_hw_gen1.h b/drivers/ntb/hw/intel/ntb_hw_gen1.h index 544cf5c06f4d..1b759942d8af 100644 --- a/drivers/ntb/hw/intel/ntb_hw_gen1.h +++ b/drivers/ntb/hw/intel/ntb_hw_gen1.h @@ -140,6 +140,7 @@ #define NTB_HWERR_SB01BASE_LOCKUP BIT_ULL(1) #define NTB_HWERR_B2BDOORBELL_BIT14 BIT_ULL(2) #define NTB_HWERR_MSIX_VECTOR32_BAD BIT_ULL(3) +#define NTB_HWERR_BAR_ALIGN BIT_ULL(4) extern struct intel_b2b_addr xeon_b2b_usd_addr; extern struct intel_b2b_addr xeon_b2b_dsd_addr; diff --git a/drivers/ntb/hw/intel/ntb_hw_gen3.c b/drivers/ntb/hw/intel/ntb_hw_gen3.c index c3397160db7f..ffcfc3e02c35 100644 --- a/drivers/ntb/hw/intel/ntb_hw_gen3.c +++ b/drivers/ntb/hw/intel/ntb_hw_gen3.c @@ -415,9 +415,8 @@ ssize_t ndev_ntb3_debugfs_read(struct file *filp, char __user *ubuf, return ret; } -static int intel_ntb3_link_enable(struct ntb_dev *ntb, - enum ntb_speed max_speed, - enum ntb_width max_width) +int intel_ntb3_link_enable(struct ntb_dev *ntb, enum ntb_speed max_speed, + enum ntb_width max_width) { struct intel_ntb_dev *ndev; u32 ntb_ctl; @@ -532,7 +531,7 @@ static int intel_ntb3_mw_set_trans(struct ntb_dev *ntb, int pidx, int idx, return 0; } -static int intel_ntb3_peer_db_addr(struct ntb_dev *ntb, phys_addr_t *db_addr, +int intel_ntb3_peer_db_addr(struct ntb_dev *ntb, phys_addr_t *db_addr, resource_size_t *db_size, u64 *db_data, int db_bit) { @@ -563,7 +562,7 @@ static int intel_ntb3_peer_db_addr(struct ntb_dev *ntb, phys_addr_t *db_addr, return 0; } -static int intel_ntb3_peer_db_set(struct ntb_dev *ntb, u64 db_bits) +int intel_ntb3_peer_db_set(struct ntb_dev *ntb, u64 db_bits) { struct intel_ntb_dev *ndev = ntb_ndev(ntb); int bit; @@ -581,7 +580,7 @@ static int intel_ntb3_peer_db_set(struct ntb_dev *ntb, u64 db_bits) return 0; } -static u64 intel_ntb3_db_read(struct ntb_dev *ntb) +u64 intel_ntb3_db_read(struct ntb_dev *ntb) { struct intel_ntb_dev *ndev = ntb_ndev(ntb); @@ -590,7 +589,7 @@ static u64 intel_ntb3_db_read(struct ntb_dev *ntb) ndev->self_reg->db_clear); } -static int intel_ntb3_db_clear(struct ntb_dev *ntb, u64 db_bits) +int intel_ntb3_db_clear(struct ntb_dev *ntb, u64 db_bits) { struct intel_ntb_dev *ndev = ntb_ndev(ntb); diff --git a/drivers/ntb/hw/intel/ntb_hw_gen3.h b/drivers/ntb/hw/intel/ntb_hw_gen3.h index 75fb86ca27bb..2bc5d8356045 100644 --- a/drivers/ntb/hw/intel/ntb_hw_gen3.h +++ b/drivers/ntb/hw/intel/ntb_hw_gen3.h @@ -104,6 +104,14 @@ static inline void gen3_db_iowrite(u64 bits, void __iomem *mmio) ssize_t ndev_ntb3_debugfs_read(struct file *filp, char __user *ubuf, size_t count, loff_t *offp); int gen3_init_dev(struct intel_ntb_dev *ndev); +int intel_ntb3_link_enable(struct ntb_dev *ntb, enum ntb_speed max_speed, + enum ntb_width max_width); +u64 intel_ntb3_db_read(struct ntb_dev *ntb); +int intel_ntb3_db_clear(struct ntb_dev *ntb, u64 db_bits); +int intel_ntb3_peer_db_set(struct ntb_dev *ntb, u64 db_bits); +int intel_ntb3_peer_db_addr(struct ntb_dev *ntb, phys_addr_t *db_addr, + resource_size_t *db_size, + u64 *db_data, int db_bit); extern const struct ntb_dev_ops intel_ntb3_ops; diff --git a/drivers/ntb/hw/intel/ntb_hw_gen4.c b/drivers/ntb/hw/intel/ntb_hw_gen4.c new file mode 100644 index 000000000000..bc4541cbf8c6 --- /dev/null +++ b/drivers/ntb/hw/intel/ntb_hw_gen4.c @@ -0,0 +1,552 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* Copyright(c) 2020 Intel Corporation. All rights reserved. */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ntb_hw_intel.h" +#include "ntb_hw_gen1.h" +#include "ntb_hw_gen3.h" +#include "ntb_hw_gen4.h" + +static int gen4_poll_link(struct intel_ntb_dev *ndev); +static int gen4_link_is_up(struct intel_ntb_dev *ndev); + +static const struct intel_ntb_reg gen4_reg = { + .poll_link = gen4_poll_link, + .link_is_up = gen4_link_is_up, + .db_ioread = gen3_db_ioread, + .db_iowrite = gen3_db_iowrite, + .db_size = sizeof(u32), + .ntb_ctl = GEN4_NTBCNTL_OFFSET, + .mw_bar = {2, 4}, +}; + +static const struct intel_ntb_alt_reg gen4_pri_reg = { + .db_clear = GEN4_IM_INT_STATUS_OFFSET, + .db_mask = GEN4_IM_INT_DISABLE_OFFSET, + .spad = GEN4_IM_SPAD_OFFSET, +}; + +static const struct intel_ntb_xlat_reg gen4_sec_xlat = { + .bar2_limit = GEN4_IM23XLMT_OFFSET, + .bar2_xlat = GEN4_IM23XBASE_OFFSET, + .bar2_idx = GEN4_IM23XBASEIDX_OFFSET, +}; + +static const struct intel_ntb_alt_reg gen4_b2b_reg = { + .db_bell = GEN4_IM_DOORBELL_OFFSET, + .spad = GEN4_EM_SPAD_OFFSET, +}; + +static int gen4_poll_link(struct intel_ntb_dev *ndev) +{ + u16 reg_val; + + /* + * We need to write to DLLSCS bit in the SLOTSTS before we + * can clear the hardware link interrupt on ICX NTB. + */ + iowrite16(GEN4_SLOTSTS_DLLSCS, ndev->self_mmio + GEN4_SLOTSTS); + ndev->reg->db_iowrite(ndev->db_link_mask, + ndev->self_mmio + + ndev->self_reg->db_clear); + + reg_val = ioread16(ndev->self_mmio + GEN4_LINK_STATUS_OFFSET); + if (reg_val == ndev->lnk_sta) + return 0; + + ndev->lnk_sta = reg_val; + + return 1; +} + +static int gen4_link_is_up(struct intel_ntb_dev *ndev) +{ + return NTB_LNK_STA_ACTIVE(ndev->lnk_sta); +} + +static int gen4_init_isr(struct intel_ntb_dev *ndev) +{ + int i; + + /* + * The MSIX vectors and the interrupt status bits are not lined up + * on Gen3 (Skylake) and Gen4. By default the link status bit is bit + * 32, however it is by default MSIX vector0. We need to fixup to + * line them up. The vectors at reset is 1-32,0. We need to reprogram + * to 0-32. + */ + for (i = 0; i < GEN4_DB_MSIX_VECTOR_COUNT; i++) + iowrite8(i, ndev->self_mmio + GEN4_INTVEC_OFFSET + i); + + return ndev_init_isr(ndev, GEN4_DB_MSIX_VECTOR_COUNT, + GEN4_DB_MSIX_VECTOR_COUNT, + GEN4_DB_MSIX_VECTOR_SHIFT, + GEN4_DB_TOTAL_SHIFT); +} + +static int gen4_setup_b2b_mw(struct intel_ntb_dev *ndev, + const struct intel_b2b_addr *addr, + const struct intel_b2b_addr *peer_addr) +{ + struct pci_dev *pdev; + void __iomem *mmio; + phys_addr_t bar_addr; + + pdev = ndev->ntb.pdev; + mmio = ndev->self_mmio; + + /* setup incoming bar limits == base addrs (zero length windows) */ + bar_addr = addr->bar2_addr64; + iowrite64(bar_addr, mmio + GEN4_IM23XLMT_OFFSET); + bar_addr = ioread64(mmio + GEN4_IM23XLMT_OFFSET); + dev_dbg(&pdev->dev, "IM23XLMT %#018llx\n", bar_addr); + + bar_addr = addr->bar4_addr64; + iowrite64(bar_addr, mmio + GEN4_IM45XLMT_OFFSET); + bar_addr = ioread64(mmio + GEN4_IM45XLMT_OFFSET); + dev_dbg(&pdev->dev, "IM45XLMT %#018llx\n", bar_addr); + + /* zero incoming translation addrs */ + iowrite64(0, mmio + GEN4_IM23XBASE_OFFSET); + iowrite64(0, mmio + GEN4_IM45XBASE_OFFSET); + + ndev->peer_mmio = ndev->self_mmio; + + return 0; +} + +static int gen4_init_ntb(struct intel_ntb_dev *ndev) +{ + int rc; + + + ndev->mw_count = XEON_MW_COUNT; + ndev->spad_count = GEN4_SPAD_COUNT; + ndev->db_count = GEN4_DB_COUNT; + ndev->db_link_mask = GEN4_DB_LINK_BIT; + + ndev->self_reg = &gen4_pri_reg; + ndev->xlat_reg = &gen4_sec_xlat; + ndev->peer_reg = &gen4_b2b_reg; + + if (ndev->ntb.topo == NTB_TOPO_B2B_USD) + rc = gen4_setup_b2b_mw(ndev, &xeon_b2b_dsd_addr, + &xeon_b2b_usd_addr); + else + rc = gen4_setup_b2b_mw(ndev, &xeon_b2b_usd_addr, + &xeon_b2b_dsd_addr); + if (rc) + return rc; + + ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1; + + ndev->reg->db_iowrite(ndev->db_valid_mask, + ndev->self_mmio + + ndev->self_reg->db_mask); + + return 0; +} + +static enum ntb_topo gen4_ppd_topo(struct intel_ntb_dev *ndev, u32 ppd) +{ + switch (ppd & GEN4_PPD_TOPO_MASK) { + case GEN4_PPD_TOPO_B2B_USD: + return NTB_TOPO_B2B_USD; + case GEN4_PPD_TOPO_B2B_DSD: + return NTB_TOPO_B2B_DSD; + } + + return NTB_TOPO_NONE; +} + +int gen4_init_dev(struct intel_ntb_dev *ndev) +{ + struct pci_dev *pdev = ndev->ntb.pdev; + u32 ppd1/*, ppd0*/; + u16 lnkctl; + int rc; + + ndev->reg = &gen4_reg; + + if (pdev_is_ICX(pdev)) + ndev->hwerr_flags |= NTB_HWERR_BAR_ALIGN; + + ppd1 = ioread32(ndev->self_mmio + GEN4_PPD1_OFFSET); + ndev->ntb.topo = gen4_ppd_topo(ndev, ppd1); + dev_dbg(&pdev->dev, "ppd %#x topo %s\n", ppd1, + ntb_topo_string(ndev->ntb.topo)); + if (ndev->ntb.topo == NTB_TOPO_NONE) + return -EINVAL; + + rc = gen4_init_ntb(ndev); + if (rc) + return rc; + + /* init link setup */ + lnkctl = ioread16(ndev->self_mmio + GEN4_LINK_CTRL_OFFSET); + lnkctl |= GEN4_LINK_CTRL_LINK_DISABLE; + iowrite16(lnkctl, ndev->self_mmio + GEN4_LINK_CTRL_OFFSET); + + return gen4_init_isr(ndev); +} + +ssize_t ndev_ntb4_debugfs_read(struct file *filp, char __user *ubuf, + size_t count, loff_t *offp) +{ + struct intel_ntb_dev *ndev; + void __iomem *mmio; + char *buf; + size_t buf_size; + ssize_t ret, off; + union { u64 v64; u32 v32; u16 v16; } u; + + ndev = filp->private_data; + mmio = ndev->self_mmio; + + buf_size = min(count, 0x800ul); + + buf = kmalloc(buf_size, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + off = 0; + + off += scnprintf(buf + off, buf_size - off, + "NTB Device Information:\n"); + + off += scnprintf(buf + off, buf_size - off, + "Connection Topology -\t%s\n", + ntb_topo_string(ndev->ntb.topo)); + + off += scnprintf(buf + off, buf_size - off, + "NTB CTL -\t\t%#06x\n", ndev->ntb_ctl); + off += scnprintf(buf + off, buf_size - off, + "LNK STA (cached) -\t\t%#06x\n", ndev->lnk_sta); + + if (!ndev->reg->link_is_up(ndev)) + off += scnprintf(buf + off, buf_size - off, + "Link Status -\t\tDown\n"); + else { + off += scnprintf(buf + off, buf_size - off, + "Link Status -\t\tUp\n"); + off += scnprintf(buf + off, buf_size - off, + "Link Speed -\t\tPCI-E Gen %u\n", + NTB_LNK_STA_SPEED(ndev->lnk_sta)); + off += scnprintf(buf + off, buf_size - off, + "Link Width -\t\tx%u\n", + NTB_LNK_STA_WIDTH(ndev->lnk_sta)); + } + + off += scnprintf(buf + off, buf_size - off, + "Memory Window Count -\t%u\n", ndev->mw_count); + off += scnprintf(buf + off, buf_size - off, + "Scratchpad Count -\t%u\n", ndev->spad_count); + off += scnprintf(buf + off, buf_size - off, + "Doorbell Count -\t%u\n", ndev->db_count); + off += scnprintf(buf + off, buf_size - off, + "Doorbell Vector Count -\t%u\n", ndev->db_vec_count); + off += scnprintf(buf + off, buf_size - off, + "Doorbell Vector Shift -\t%u\n", ndev->db_vec_shift); + + off += scnprintf(buf + off, buf_size - off, + "Doorbell Valid Mask -\t%#llx\n", ndev->db_valid_mask); + off += scnprintf(buf + off, buf_size - off, + "Doorbell Link Mask -\t%#llx\n", ndev->db_link_mask); + off += scnprintf(buf + off, buf_size - off, + "Doorbell Mask Cached -\t%#llx\n", ndev->db_mask); + + u.v64 = ndev_db_read(ndev, mmio + ndev->self_reg->db_mask); + off += scnprintf(buf + off, buf_size - off, + "Doorbell Mask -\t\t%#llx\n", u.v64); + + off += scnprintf(buf + off, buf_size - off, + "\nNTB Incoming XLAT:\n"); + + u.v64 = ioread64(mmio + GEN4_IM23XBASE_OFFSET); + off += scnprintf(buf + off, buf_size - off, + "IM23XBASE -\t\t%#018llx\n", u.v64); + + u.v64 = ioread64(mmio + GEN4_IM45XBASE_OFFSET); + off += scnprintf(buf + off, buf_size - off, + "IM45XBASE -\t\t%#018llx\n", u.v64); + + u.v64 = ioread64(mmio + GEN4_IM23XLMT_OFFSET); + off += scnprintf(buf + off, buf_size - off, + "IM23XLMT -\t\t\t%#018llx\n", u.v64); + + u.v64 = ioread64(mmio + GEN4_IM45XLMT_OFFSET); + off += scnprintf(buf + off, buf_size - off, + "IM45XLMT -\t\t\t%#018llx\n", u.v64); + + off += scnprintf(buf + off, buf_size - off, + "\nNTB Statistics:\n"); + + off += scnprintf(buf + off, buf_size - off, + "\nNTB Hardware Errors:\n"); + + if (!pci_read_config_word(ndev->ntb.pdev, + GEN4_DEVSTS_OFFSET, &u.v16)) + off += scnprintf(buf + off, buf_size - off, + "DEVSTS -\t\t%#06x\n", u.v16); + + u.v16 = ioread16(mmio + GEN4_LINK_STATUS_OFFSET); + off += scnprintf(buf + off, buf_size - off, + "LNKSTS -\t\t%#06x\n", u.v16); + + if (!pci_read_config_dword(ndev->ntb.pdev, + GEN4_UNCERRSTS_OFFSET, &u.v32)) + off += scnprintf(buf + off, buf_size - off, + "UNCERRSTS -\t\t%#06x\n", u.v32); + + if (!pci_read_config_dword(ndev->ntb.pdev, + GEN4_CORERRSTS_OFFSET, &u.v32)) + off += scnprintf(buf + off, buf_size - off, + "CORERRSTS -\t\t%#06x\n", u.v32); + + ret = simple_read_from_buffer(ubuf, count, offp, buf, off); + kfree(buf); + return ret; +} + +static int intel_ntb4_mw_set_trans(struct ntb_dev *ntb, int pidx, int idx, + dma_addr_t addr, resource_size_t size) +{ + struct intel_ntb_dev *ndev = ntb_ndev(ntb); + unsigned long xlat_reg, limit_reg, idx_reg; + unsigned short base_idx, reg_val16; + resource_size_t bar_size, mw_size; + void __iomem *mmio; + u64 base, limit, reg_val; + int bar; + + if (pidx != NTB_DEF_PEER_IDX) + return -EINVAL; + + if (idx >= ndev->b2b_idx && !ndev->b2b_off) + idx += 1; + + bar = ndev_mw_to_bar(ndev, idx); + if (bar < 0) + return bar; + + bar_size = pci_resource_len(ndev->ntb.pdev, bar); + + if (idx == ndev->b2b_idx) + mw_size = bar_size - ndev->b2b_off; + else + mw_size = bar_size; + + if (ndev->hwerr_flags & NTB_HWERR_BAR_ALIGN) { + /* hardware requires that addr is aligned to bar size */ + if (addr & (bar_size - 1)) + return -EINVAL; + } else { + if (addr & (PAGE_SIZE - 1)) + return -EINVAL; + } + + /* make sure the range fits in the usable mw size */ + if (size > mw_size) + return -EINVAL; + + mmio = ndev->self_mmio; + xlat_reg = ndev->xlat_reg->bar2_xlat + (idx * 0x10); + limit_reg = ndev->xlat_reg->bar2_limit + (idx * 0x10); + base = pci_resource_start(ndev->ntb.pdev, bar); + + /* Set the limit if supported, if size is not mw_size */ + if (limit_reg && size != mw_size) { + limit = base + size; + base_idx = __ilog2_u64(size); + } else { + limit = base + mw_size; + base_idx = __ilog2_u64(mw_size); + } + + + /* set and verify setting the translation address */ + iowrite64(addr, mmio + xlat_reg); + reg_val = ioread64(mmio + xlat_reg); + if (reg_val != addr) { + iowrite64(0, mmio + xlat_reg); + return -EIO; + } + + dev_dbg(&ntb->pdev->dev, "BAR %d IMXBASE: %#Lx\n", bar, reg_val); + + /* set and verify setting the limit */ + iowrite64(limit, mmio + limit_reg); + reg_val = ioread64(mmio + limit_reg); + if (reg_val != limit) { + iowrite64(base, mmio + limit_reg); + iowrite64(0, mmio + xlat_reg); + return -EIO; + } + + dev_dbg(&ntb->pdev->dev, "BAR %d IMXLMT: %#Lx\n", bar, reg_val); + + if (ndev->hwerr_flags & NTB_HWERR_BAR_ALIGN) { + idx_reg = ndev->xlat_reg->bar2_idx + (idx * 0x2); + iowrite16(base_idx, mmio + idx_reg); + reg_val16 = ioread16(mmio + idx_reg); + if (reg_val16 != base_idx) { + iowrite64(base, mmio + limit_reg); + iowrite64(0, mmio + xlat_reg); + iowrite16(0, mmio + idx_reg); + return -EIO; + } + dev_dbg(&ntb->pdev->dev, "BAR %d IMBASEIDX: %#x\n", bar, reg_val16); + } + + + return 0; +} + +static int intel_ntb4_link_enable(struct ntb_dev *ntb, + enum ntb_speed max_speed, enum ntb_width max_width) +{ + struct intel_ntb_dev *ndev; + u32 ntb_ctl, ppd0; + u16 lnkctl; + + ndev = container_of(ntb, struct intel_ntb_dev, ntb); + + dev_dbg(&ntb->pdev->dev, + "Enabling link with max_speed %d max_width %d\n", + max_speed, max_width); + + if (max_speed != NTB_SPEED_AUTO) + dev_dbg(&ntb->pdev->dev, + "ignoring max_speed %d\n", max_speed); + if (max_width != NTB_WIDTH_AUTO) + dev_dbg(&ntb->pdev->dev, + "ignoring max_width %d\n", max_width); + + ntb_ctl = NTB_CTL_E2I_BAR23_SNOOP | NTB_CTL_I2E_BAR23_SNOOP; + ntb_ctl |= NTB_CTL_E2I_BAR45_SNOOP | NTB_CTL_I2E_BAR45_SNOOP; + iowrite32(ntb_ctl, ndev->self_mmio + ndev->reg->ntb_ctl); + + lnkctl = ioread16(ndev->self_mmio + GEN4_LINK_CTRL_OFFSET); + lnkctl &= ~GEN4_LINK_CTRL_LINK_DISABLE; + iowrite16(lnkctl, ndev->self_mmio + GEN4_LINK_CTRL_OFFSET); + + /* start link training in PPD0 */ + ppd0 = ioread32(ndev->self_mmio + GEN4_PPD0_OFFSET); + ppd0 |= GEN4_PPD_LINKTRN; + iowrite32(ppd0, ndev->self_mmio + GEN4_PPD0_OFFSET); + + /* make sure link training has started */ + ppd0 = ioread32(ndev->self_mmio + GEN4_PPD0_OFFSET); + if (!(ppd0 & GEN4_PPD_LINKTRN)) { + dev_warn(&ntb->pdev->dev, "Link is not training\n"); + return -ENXIO; + } + + ndev->dev_up = 1; + + return 0; +} + +static int intel_ntb4_link_disable(struct ntb_dev *ntb) +{ + struct intel_ntb_dev *ndev; + u32 ntb_cntl; + u16 lnkctl; + + ndev = container_of(ntb, struct intel_ntb_dev, ntb); + + dev_dbg(&ntb->pdev->dev, "Disabling link\n"); + + /* clear the snoop bits */ + ntb_cntl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl); + ntb_cntl &= ~(NTB_CTL_E2I_BAR23_SNOOP | NTB_CTL_I2E_BAR23_SNOOP); + ntb_cntl &= ~(NTB_CTL_E2I_BAR45_SNOOP | NTB_CTL_I2E_BAR45_SNOOP); + iowrite32(ntb_cntl, ndev->self_mmio + ndev->reg->ntb_ctl); + + lnkctl = ioread16(ndev->self_mmio + GEN4_LINK_CTRL_OFFSET); + lnkctl |= GEN4_LINK_CTRL_LINK_DISABLE; + iowrite16(lnkctl, ndev->self_mmio + GEN4_LINK_CTRL_OFFSET); + + ndev->dev_up = 0; + + return 0; +} + +static int intel_ntb4_mw_get_align(struct ntb_dev *ntb, int pidx, int idx, + resource_size_t *addr_align, + resource_size_t *size_align, + resource_size_t *size_max) +{ + struct intel_ntb_dev *ndev = ntb_ndev(ntb); + resource_size_t bar_size, mw_size; + int bar; + + if (pidx != NTB_DEF_PEER_IDX) + return -EINVAL; + + if (idx >= ndev->b2b_idx && !ndev->b2b_off) + idx += 1; + + bar = ndev_mw_to_bar(ndev, idx); + if (bar < 0) + return bar; + + bar_size = pci_resource_len(ndev->ntb.pdev, bar); + + if (idx == ndev->b2b_idx) + mw_size = bar_size - ndev->b2b_off; + else + mw_size = bar_size; + + if (addr_align) { + if (ndev->hwerr_flags & NTB_HWERR_BAR_ALIGN) + *addr_align = pci_resource_len(ndev->ntb.pdev, bar); + else + *addr_align = PAGE_SIZE; + } + + if (size_align) + *size_align = 1; + + if (size_max) + *size_max = mw_size; + + return 0; +} + +const struct ntb_dev_ops intel_ntb4_ops = { + .mw_count = intel_ntb_mw_count, + .mw_get_align = intel_ntb4_mw_get_align, + .mw_set_trans = intel_ntb4_mw_set_trans, + .peer_mw_count = intel_ntb_peer_mw_count, + .peer_mw_get_addr = intel_ntb_peer_mw_get_addr, + .link_is_up = intel_ntb_link_is_up, + .link_enable = intel_ntb4_link_enable, + .link_disable = intel_ntb4_link_disable, + .db_valid_mask = intel_ntb_db_valid_mask, + .db_vector_count = intel_ntb_db_vector_count, + .db_vector_mask = intel_ntb_db_vector_mask, + .db_read = intel_ntb3_db_read, + .db_clear = intel_ntb3_db_clear, + .db_set_mask = intel_ntb_db_set_mask, + .db_clear_mask = intel_ntb_db_clear_mask, + .peer_db_addr = intel_ntb3_peer_db_addr, + .peer_db_set = intel_ntb3_peer_db_set, + .spad_is_unsafe = intel_ntb_spad_is_unsafe, + .spad_count = intel_ntb_spad_count, + .spad_read = intel_ntb_spad_read, + .spad_write = intel_ntb_spad_write, + .peer_spad_addr = intel_ntb_peer_spad_addr, + .peer_spad_read = intel_ntb_peer_spad_read, + .peer_spad_write = intel_ntb_peer_spad_write, +}; + diff --git a/drivers/ntb/hw/intel/ntb_hw_gen4.h b/drivers/ntb/hw/intel/ntb_hw_gen4.h new file mode 100644 index 000000000000..a868c788de02 --- /dev/null +++ b/drivers/ntb/hw/intel/ntb_hw_gen4.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ +/* Copyright(c) 2020 Intel Corporation. All rights reserved. */ +#ifndef _NTB_INTEL_GEN4_H_ +#define _NTB_INTEL_GEN4_H_ + +#include "ntb_hw_intel.h" + +/* Supported PCI device revision range for ICX */ +#define PCI_DEVICE_REVISION_ICX_MIN 0x2 +#define PCI_DEVICE_REVISION_ICX_MAX 0xF + +/* Intel Gen4 NTB hardware */ +/* PCIe config space */ +#define GEN4_IMBAR23SZ_OFFSET 0x00c4 +#define GEN4_IMBAR45SZ_OFFSET 0x00c5 +#define GEN4_EMBAR23SZ_OFFSET 0x00c6 +#define GEN4_EMBAR45SZ_OFFSET 0x00c7 +#define GEN4_DEVCTRL_OFFSET 0x0048 +#define GEN4_DEVSTS_OFFSET 0x004a +#define GEN4_UNCERRSTS_OFFSET 0x0104 +#define GEN4_CORERRSTS_OFFSET 0x0110 + +/* BAR0 MMIO */ +#define GEN4_NTBCNTL_OFFSET 0x0000 +#define GEN4_IM23XBASE_OFFSET 0x0010 /* IMBAR1XBASE */ +#define GEN4_IM23XLMT_OFFSET 0x0018 /* IMBAR1XLMT */ +#define GEN4_IM45XBASE_OFFSET 0x0020 /* IMBAR2XBASE */ +#define GEN4_IM45XLMT_OFFSET 0x0028 /* IMBAR2XLMT */ +#define GEN4_IM_INT_STATUS_OFFSET 0x0040 +#define GEN4_IM_INT_DISABLE_OFFSET 0x0048 +#define GEN4_INTVEC_OFFSET 0x0050 /* 0-32 vecs */ +#define GEN4_IM23XBASEIDX_OFFSET 0x0074 +#define GEN4_IM45XBASEIDX_OFFSET 0x0076 +#define GEN4_IM_SPAD_OFFSET 0x0080 /* 0-15 SPADs */ +#define GEN4_IM_SPAD_SEM_OFFSET 0x00c0 /* SPAD hw semaphore */ +#define GEN4_IM_SPAD_STICKY_OFFSET 0x00c4 /* sticky SPAD */ +#define GEN4_IM_DOORBELL_OFFSET 0x0100 /* 0-31 doorbells */ +#define GEN4_EM_SPAD_OFFSET 0x8080 +/* note, link status is now in MMIO and not config space for NTB */ +#define GEN4_LINK_CTRL_OFFSET 0xb050 +#define GEN4_LINK_STATUS_OFFSET 0xb052 +#define GEN4_PPD0_OFFSET 0xb0d4 +#define GEN4_PPD1_OFFSET 0xb4c0 +#define GEN4_LTSSMSTATEJMP 0xf040 + +#define GEN4_PPD_CLEAR_TRN 0x0001 +#define GEN4_PPD_LINKTRN 0x0008 +#define GEN4_PPD_CONN_MASK 0x0300 +#define GEN4_PPD_CONN_B2B 0x0200 +#define GEN4_PPD_DEV_MASK 0x1000 +#define GEN4_PPD_DEV_DSD 0x1000 +#define GEN4_PPD_DEV_USD 0x0000 +#define GEN4_LINK_CTRL_LINK_DISABLE 0x0010 + +#define GEN4_SLOTSTS 0xb05a +#define GEN4_SLOTSTS_DLLSCS 0x100 + +#define GEN4_PPD_TOPO_MASK (GEN4_PPD_CONN_MASK | GEN4_PPD_DEV_MASK) +#define GEN4_PPD_TOPO_B2B_USD (GEN4_PPD_CONN_B2B | GEN4_PPD_DEV_USD) +#define GEN4_PPD_TOPO_B2B_DSD (GEN4_PPD_CONN_B2B | GEN4_PPD_DEV_DSD) + +#define GEN4_DB_COUNT 32 +#define GEN4_DB_LINK 32 +#define GEN4_DB_LINK_BIT BIT_ULL(GEN4_DB_LINK) +#define GEN4_DB_MSIX_VECTOR_COUNT 33 +#define GEN4_DB_MSIX_VECTOR_SHIFT 1 +#define GEN4_DB_TOTAL_SHIFT 33 +#define GEN4_SPAD_COUNT 16 + +#define NTB_CTL_E2I_BAR23_SNOOP 0x000004 +#define NTB_CTL_E2I_BAR23_NOSNOOP 0x000008 +#define NTB_CTL_I2E_BAR23_SNOOP 0x000010 +#define NTB_CTL_I2E_BAR23_NOSNOOP 0x000020 +#define NTB_CTL_E2I_BAR45_SNOOP 0x000040 +#define NTB_CTL_E2I_BAR45_NOSNOO 0x000080 +#define NTB_CTL_I2E_BAR45_SNOOP 0x000100 +#define NTB_CTL_I2E_BAR45_NOSNOOP 0x000200 +#define NTB_CTL_BUSNO_DIS_INC 0x000400 +#define NTB_CTL_LINK_DOWN 0x010000 + +#define NTB_SJC_FORCEDETECT 0x000004 + +ssize_t ndev_ntb4_debugfs_read(struct file *filp, char __user *ubuf, + size_t count, loff_t *offp); +int gen4_init_dev(struct intel_ntb_dev *ndev); +ssize_t ndev_ntb4_debugfs_read(struct file *filp, char __user *ubuf, + size_t count, loff_t *offp); + +extern const struct ntb_dev_ops intel_ntb4_ops; + +static inline int pdev_is_ICX(struct pci_dev *pdev) +{ + if (pdev_is_gen4(pdev) && + pdev->revision >= PCI_DEVICE_REVISION_ICX_MIN && + pdev->revision <= PCI_DEVICE_REVISION_ICX_MAX) + return 1; + return 0; +} + +#endif diff --git a/drivers/ntb/hw/intel/ntb_hw_intel.h b/drivers/ntb/hw/intel/ntb_hw_intel.h index e071e28bca3f..d61fcd91714b 100644 --- a/drivers/ntb/hw/intel/ntb_hw_intel.h +++ b/drivers/ntb/hw/intel/ntb_hw_intel.h @@ -72,6 +72,7 @@ #define PCI_DEVICE_ID_INTEL_NTB_PS_BDX 0x6F0E #define PCI_DEVICE_ID_INTEL_NTB_SS_BDX 0x6F0F #define PCI_DEVICE_ID_INTEL_NTB_B2B_SKX 0x201C +#define PCI_DEVICE_ID_INTEL_NTB_B2B_ICX 0x347e /* Ntb control and link status */ #define NTB_CTL_CFG_LOCK BIT(0) @@ -120,6 +121,7 @@ struct intel_ntb_xlat_reg { unsigned long bar0_base; unsigned long bar2_xlat; unsigned long bar2_limit; + unsigned short bar2_idx; }; struct intel_b2b_addr { @@ -182,6 +184,9 @@ struct intel_ntb_dev { struct dentry *debugfs_dir; struct dentry *debugfs_info; + + /* gen4 entries */ + int dev_up; }; #define ntb_ndev(__ntb) container_of(__ntb, struct intel_ntb_dev, ntb) @@ -219,4 +224,11 @@ static inline int pdev_is_gen3(struct pci_dev *pdev) return 0; } +static inline int pdev_is_gen4(struct pci_dev *pdev) +{ + if (pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_ICX) + return 1; + + return 0; +} #endif diff --git a/drivers/ntb/test/ntb_perf.c b/drivers/ntb/test/ntb_perf.c index 972f6d984f6d..89df1350fefd 100644 --- a/drivers/ntb/test/ntb_perf.c +++ b/drivers/ntb/test/ntb_perf.c @@ -101,8 +101,8 @@ MODULE_DESCRIPTION("PCIe NTB Performance Measurement Tool"); #define DMA_MDELAY 10 #define MSG_TRIES 1000 -#define MSG_UDELAY_LOW 1000 -#define MSG_UDELAY_HIGH 2000 +#define MSG_UDELAY_LOW 1000000 +#define MSG_UDELAY_HIGH 2000000 #define PERF_BUF_LEN 1024 @@ -159,6 +159,8 @@ struct perf_peer { /* NTB connection setup service */ struct work_struct service; unsigned long sts; + + struct completion init_comp; }; #define to_peer_service(__work) \ container_of(__work, struct perf_peer, service) @@ -547,6 +549,7 @@ static int perf_setup_outbuf(struct perf_peer *peer) /* Initialization is finally done */ set_bit(PERF_STS_DONE, &peer->sts); + complete_all(&peer->init_comp); return 0; } @@ -557,7 +560,7 @@ static void perf_free_inbuf(struct perf_peer *peer) return; (void)ntb_mw_clear_trans(peer->perf->ntb, peer->pidx, peer->gidx); - dma_free_coherent(&peer->perf->ntb->dev, peer->inbuf_size, + dma_free_coherent(&peer->perf->ntb->pdev->dev, peer->inbuf_size, peer->inbuf, peer->inbuf_xlat); peer->inbuf = NULL; } @@ -586,8 +589,9 @@ static int perf_setup_inbuf(struct perf_peer *peer) perf_free_inbuf(peer); - peer->inbuf = dma_alloc_coherent(&perf->ntb->dev, peer->inbuf_size, - &peer->inbuf_xlat, GFP_KERNEL); + peer->inbuf = dma_alloc_coherent(&perf->ntb->pdev->dev, + peer->inbuf_size, &peer->inbuf_xlat, + GFP_KERNEL); if (!peer->inbuf) { dev_err(&perf->ntb->dev, "Failed to alloc inbuf of %pa\n", &peer->inbuf_size); @@ -637,6 +641,7 @@ static void perf_service_work(struct work_struct *work) perf_setup_outbuf(peer); if (test_and_clear_bit(PERF_CMD_CLEAR, &peer->sts)) { + init_completion(&peer->init_comp); clear_bit(PERF_STS_DONE, &peer->sts); if (test_bit(0, &peer->perf->busy_flag) && peer == peer->perf->test_peer) { @@ -653,7 +658,7 @@ static int perf_init_service(struct perf_ctx *perf) { u64 mask; - if (ntb_peer_mw_count(perf->ntb) < perf->pcnt + 1) { + if (ntb_peer_mw_count(perf->ntb) < perf->pcnt) { dev_err(&perf->ntb->dev, "Not enough memory windows\n"); return -EINVAL; } @@ -803,7 +808,7 @@ static int perf_copy_chunk(struct perf_thread *pthr, dst_vaddr = dst; dst_dma_addr = peer->dma_dst_addr + (dst_vaddr - vbase); - unmap = dmaengine_get_unmap_data(dma_dev, 2, GFP_NOWAIT); + unmap = dmaengine_get_unmap_data(dma_dev, 1, GFP_NOWAIT); if (!unmap) return -ENOMEM; @@ -816,15 +821,8 @@ static int perf_copy_chunk(struct perf_thread *pthr, } unmap->to_cnt = 1; - unmap->addr[1] = dst_dma_addr; - if (dma_mapping_error(dma_dev, unmap->addr[1])) { - ret = -EIO; - goto err_free_resource; - } - unmap->from_cnt = 1; - do { - tx = dmaengine_prep_dma_memcpy(pthr->dma_chan, unmap->addr[1], + tx = dmaengine_prep_dma_memcpy(pthr->dma_chan, dst_dma_addr, unmap->addr[0], len, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); if (!tx) msleep(DMA_MDELAY); @@ -1010,8 +1008,8 @@ static void perf_clear_test(struct perf_thread *pthr) pthr->perf->test_peer->dma_dst_addr, pthr->perf->test_peer->outbuf_size, DMA_FROM_DEVICE, 0); - if (pthr->dma_chan) - dma_release_channel(pthr->dma_chan); + + dma_release_channel(pthr->dma_chan); no_dma_notify: atomic_dec(&perf->tsync); @@ -1083,8 +1081,9 @@ static int perf_submit_test(struct perf_peer *peer) struct perf_thread *pthr; int tidx, ret; - if (!test_bit(PERF_STS_DONE, &peer->sts)) - return -ENOLINK; + ret = wait_for_completion_interruptible(&peer->init_comp); + if (ret < 0) + return ret; if (test_and_set_bit_lock(0, &perf->busy_flag)) return -EBUSY; @@ -1455,10 +1454,21 @@ static int perf_init_peers(struct perf_ctx *perf) peer->gidx = pidx; } INIT_WORK(&peer->service, perf_service_work); + init_completion(&peer->init_comp); } if (perf->gidx == -1) perf->gidx = pidx; + /* + * Hardware with only two ports may not have unique port + * numbers. In this case, the gidxs should all be zero. + */ + if (perf->pcnt == 1 && ntb_port_number(perf->ntb) == 0 && + ntb_peer_port_number(perf->ntb, 0) == 0) { + perf->gidx = 0; + perf->peers[0].gidx = 0; + } + for (pidx = 0; pidx < perf->pcnt; pidx++) { ret = perf_setup_peer_mw(&perf->peers[pidx]); if (ret) @@ -1554,4 +1564,3 @@ static void __exit perf_exit(void) destroy_workqueue(perf_wq); } module_exit(perf_exit); - diff --git a/drivers/ntb/test/ntb_pingpong.c b/drivers/ntb/test/ntb_pingpong.c index 04dd46647db3..2164e8492772 100644 --- a/drivers/ntb/test/ntb_pingpong.c +++ b/drivers/ntb/test/ntb_pingpong.c @@ -121,15 +121,14 @@ static int pp_find_next_peer(struct pp_ctx *pp) link = ntb_link_is_up(pp->ntb, NULL, NULL); /* Find next available peer */ - if (link & pp->nmask) { + if (link & pp->nmask) pidx = __ffs64(link & pp->nmask); - out_db = BIT_ULL(pidx + 1); - } else if (link & pp->pmask) { + else if (link & pp->pmask) pidx = __ffs64(link & pp->pmask); - out_db = BIT_ULL(pidx); - } else { + else return -ENODEV; - } + + out_db = BIT_ULL(ntb_peer_port_number(pp->ntb, pidx)); spin_lock(&pp->lock); pp->out_pidx = pidx; @@ -303,7 +302,7 @@ static void pp_init_flds(struct pp_ctx *pp) break; } - pp->in_db = BIT_ULL(pidx); + pp->in_db = BIT_ULL(lport); pp->pmask = GENMASK_ULL(pidx, 0) >> 1; pp->nmask = GENMASK_ULL(pcnt - 1, pidx); @@ -432,4 +431,3 @@ static void __exit pp_exit(void) debugfs_remove_recursive(pp_dbgfs_topdir); } module_exit(pp_exit); - diff --git a/drivers/ntb/test/ntb_tool.c b/drivers/ntb/test/ntb_tool.c index 69da758fe64c..b7bf3f863d79 100644 --- a/drivers/ntb/test/ntb_tool.c +++ b/drivers/ntb/test/ntb_tool.c @@ -504,7 +504,7 @@ static ssize_t tool_peer_link_read(struct file *filep, char __user *ubuf, buf[1] = '\n'; buf[2] = '\0'; - return simple_read_from_buffer(ubuf, size, offp, buf, 3); + return simple_read_from_buffer(ubuf, size, offp, buf, 2); } static TOOL_FOPS_RDWR(tool_peer_link_fops, @@ -590,7 +590,7 @@ static int tool_setup_mw(struct tool_ctx *tc, int pidx, int widx, inmw->size = min_t(resource_size_t, req_size, size); inmw->size = round_up(inmw->size, addr_align); inmw->size = round_up(inmw->size, size_align); - inmw->mm_base = dma_alloc_coherent(&tc->ntb->dev, inmw->size, + inmw->mm_base = dma_alloc_coherent(&tc->ntb->pdev->dev, inmw->size, &inmw->dma_base, GFP_KERNEL); if (!inmw->mm_base) return -ENOMEM; @@ -612,7 +612,7 @@ static int tool_setup_mw(struct tool_ctx *tc, int pidx, int widx, return 0; err_free_dma: - dma_free_coherent(&tc->ntb->dev, inmw->size, inmw->mm_base, + dma_free_coherent(&tc->ntb->pdev->dev, inmw->size, inmw->mm_base, inmw->dma_base); inmw->mm_base = NULL; inmw->dma_base = 0; @@ -629,7 +629,7 @@ static void tool_free_mw(struct tool_ctx *tc, int pidx, int widx) if (inmw->mm_base != NULL) { ntb_mw_clear_trans(tc->ntb, pidx, widx); - dma_free_coherent(&tc->ntb->dev, inmw->size, + dma_free_coherent(&tc->ntb->pdev->dev, inmw->size, inmw->mm_base, inmw->dma_base); } @@ -1690,4 +1690,3 @@ static void __exit tool_exit(void) debugfs_remove_recursive(tool_dbgfs_topdir); } module_exit(tool_exit); - diff --git a/drivers/nvmem/core.c b/drivers/nvmem/core.c index 05c6ae4b0b97..927eb5f6003f 100644 --- a/drivers/nvmem/core.c +++ b/drivers/nvmem/core.c @@ -66,6 +66,30 @@ static LIST_HEAD(nvmem_lookup_list); static BLOCKING_NOTIFIER_HEAD(nvmem_notifier); +static int nvmem_reg_read(struct nvmem_device *nvmem, unsigned int offset, + void *val, size_t bytes) +{ + if (nvmem->reg_read) + return nvmem->reg_read(nvmem->priv, offset, val, bytes); + + return -EINVAL; +} + +static int nvmem_reg_write(struct nvmem_device *nvmem, unsigned int offset, + void *val, size_t bytes) +{ + int ret; + + if (nvmem->reg_write) { + gpiod_set_value_cansleep(nvmem->wp_gpio, 0); + ret = nvmem->reg_write(nvmem->priv, offset, val, bytes); + gpiod_set_value_cansleep(nvmem->wp_gpio, 1); + return ret; + } + + return -EINVAL; +} + #ifdef CONFIG_NVMEM_SYSFS static const char * const nvmem_type_str[] = { [NVMEM_TYPE_UNKNOWN] = "Unknown", @@ -122,7 +146,7 @@ static ssize_t bin_attr_nvmem_read(struct file *filp, struct kobject *kobj, if (!nvmem->reg_read) return -EPERM; - rc = nvmem->reg_read(nvmem->priv, pos, buf, count); + rc = nvmem_reg_read(nvmem, pos, buf, count); if (rc) return rc; @@ -159,7 +183,7 @@ static ssize_t bin_attr_nvmem_write(struct file *filp, struct kobject *kobj, if (!nvmem->reg_write) return -EPERM; - rc = nvmem->reg_write(nvmem->priv, pos, buf, count); + rc = nvmem_reg_write(nvmem, pos, buf, count); if (rc) return rc; @@ -167,11 +191,8 @@ static ssize_t bin_attr_nvmem_write(struct file *filp, struct kobject *kobj, return count; } -static umode_t nvmem_bin_attr_is_visible(struct kobject *kobj, - struct bin_attribute *attr, int i) +static umode_t nvmem_bin_attr_get_umode(struct nvmem_device *nvmem) { - struct device *dev = container_of(kobj, struct device, kobj); - struct nvmem_device *nvmem = to_nvmem_device(dev); umode_t mode = 0400; if (!nvmem->root_only) @@ -189,6 +210,15 @@ static umode_t nvmem_bin_attr_is_visible(struct kobject *kobj, return mode; } +static umode_t nvmem_bin_attr_is_visible(struct kobject *kobj, + struct bin_attribute *attr, int i) +{ + struct device *dev = container_of(kobj, struct device, kobj); + struct nvmem_device *nvmem = to_nvmem_device(dev); + + return nvmem_bin_attr_get_umode(nvmem); +} + /* default read/write permissions */ static struct bin_attribute bin_attr_rw_nvmem = { .attr = { @@ -215,34 +245,14 @@ static const struct attribute_group *nvmem_dev_groups[] = { NULL, }; -/* read only permission */ -static struct bin_attribute bin_attr_ro_nvmem = { +static struct bin_attribute bin_attr_nvmem_eeprom_compat = { .attr = { - .name = "nvmem", - .mode = 0444, - }, - .read = bin_attr_nvmem_read, -}; - -/* default read/write permissions, root only */ -static struct bin_attribute bin_attr_rw_root_nvmem = { - .attr = { - .name = "nvmem", - .mode = 0600, + .name = "eeprom", }, .read = bin_attr_nvmem_read, .write = bin_attr_nvmem_write, }; -/* read only permission, root only */ -static struct bin_attribute bin_attr_ro_root_nvmem = { - .attr = { - .name = "nvmem", - .mode = 0400, - }, - .read = bin_attr_nvmem_read, -}; - /* * nvmem_setup_compat() - Create an additional binary entry in * drivers sys directory, to be backwards compatible with the older @@ -259,18 +269,8 @@ static int nvmem_sysfs_setup_compat(struct nvmem_device *nvmem, if (!config->base_dev) return -EINVAL; - if (nvmem->read_only) { - if (config->root_only) - nvmem->eeprom = bin_attr_ro_root_nvmem; - else - nvmem->eeprom = bin_attr_ro_nvmem; - } else { - if (config->root_only) - nvmem->eeprom = bin_attr_rw_root_nvmem; - else - nvmem->eeprom = bin_attr_rw_nvmem; - } - nvmem->eeprom.attr.name = "eeprom"; + nvmem->eeprom = bin_attr_nvmem_eeprom_compat; + nvmem->eeprom.attr.mode = nvmem_bin_attr_get_umode(nvmem); nvmem->eeprom.size = nvmem->size; #ifdef CONFIG_DEBUG_LOCK_ALLOC nvmem->eeprom.attr.key = &eeprom_lock_key; @@ -311,30 +311,6 @@ static void nvmem_sysfs_remove_compat(struct nvmem_device *nvmem, #endif /* CONFIG_NVMEM_SYSFS */ -static int nvmem_reg_read(struct nvmem_device *nvmem, unsigned int offset, - void *val, size_t bytes) -{ - if (nvmem->reg_read) - return nvmem->reg_read(nvmem->priv, offset, val, bytes); - - return -EINVAL; -} - -static int nvmem_reg_write(struct nvmem_device *nvmem, unsigned int offset, - void *val, size_t bytes) -{ - int ret; - - if (nvmem->reg_write) { - gpiod_set_value_cansleep(nvmem->wp_gpio, 0); - ret = nvmem->reg_write(nvmem->priv, offset, val, bytes); - gpiod_set_value_cansleep(nvmem->wp_gpio, 1); - return ret; - } - - return -EINVAL; -} - static void nvmem_release(struct device *dev) { struct nvmem_device *nvmem = to_nvmem_device(dev); diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c index 50bea2aadc1b..7a1ebd6fd08b 100644 --- a/drivers/nvmem/imx-ocotp.c +++ b/drivers/nvmem/imx-ocotp.c @@ -196,7 +196,6 @@ static int imx_ocotp_read(void *context, unsigned int offset, if (*(buf - 1) == IMX_OCOTP_READ_LOCKED_VAL) imx_ocotp_clr_err_if_set(priv); } - ret = 0; read_end: clk_disable_unprepare(priv->clk); @@ -435,17 +434,13 @@ static int imx_ocotp_write(void *context, unsigned int offset, void *val, priv->base + IMX_OCOTP_ADDR_CTRL_SET); ret = imx_ocotp_wait_for_busy(priv, priv->params->ctrl.bm_rel_shadows); - if (ret < 0) { + if (ret < 0) dev_err(priv->dev, "timeout during shadow register reload\n"); - goto write_end; - } write_end: clk_disable_unprepare(priv->clk); mutex_unlock(&ocotp_mutex); - if (ret < 0) - return ret; - return bytes; + return ret < 0 ? ret : bytes; } static struct nvmem_config imx_ocotp_nvmem_config = { diff --git a/drivers/nvmem/jz4780-efuse.c b/drivers/nvmem/jz4780-efuse.c index 512e1872ba36..0b01b840edd9 100644 --- a/drivers/nvmem/jz4780-efuse.c +++ b/drivers/nvmem/jz4780-efuse.c @@ -211,10 +211,8 @@ static int jz4780_efuse_probe(struct platform_device *pdev) cfg.priv = efuse; nvmem = devm_nvmem_register(dev, &cfg); - if (IS_ERR(nvmem)) - return PTR_ERR(nvmem); - return 0; + return PTR_ERR_OR_ZERO(nvmem); } static const struct of_device_id jz4780_efuse_match[] = { diff --git a/drivers/nvmem/qfprom.c b/drivers/nvmem/qfprom.c index d057f1bfb2e9..8a91717600be 100644 --- a/drivers/nvmem/qfprom.c +++ b/drivers/nvmem/qfprom.c @@ -27,25 +27,11 @@ static int qfprom_reg_read(void *context, return 0; } -static int qfprom_reg_write(void *context, - unsigned int reg, void *_val, size_t bytes) -{ - struct qfprom_priv *priv = context; - u8 *val = _val; - int i = 0, words = bytes; - - while (words--) - writeb(*val++, priv->base + reg + i++); - - return 0; -} - static struct nvmem_config econfig = { .name = "qfprom", .stride = 1, .word_size = 1, .reg_read = qfprom_reg_read, - .reg_write = qfprom_reg_write, }; static int qfprom_probe(struct platform_device *pdev) diff --git a/drivers/nvmem/zynqmp_nvmem.c b/drivers/nvmem/zynqmp_nvmem.c index 5893543918c8..e28d7b133e11 100644 --- a/drivers/nvmem/zynqmp_nvmem.c +++ b/drivers/nvmem/zynqmp_nvmem.c @@ -16,8 +16,6 @@ struct zynqmp_nvmem_data { struct nvmem_device *nvmem; }; -static const struct zynqmp_eemi_ops *eemi_ops; - static int zynqmp_nvmem_read(void *context, unsigned int offset, void *val, size_t bytes) { @@ -25,10 +23,7 @@ static int zynqmp_nvmem_read(void *context, unsigned int offset, int idcode, version; struct zynqmp_nvmem_data *priv = context; - if (!eemi_ops->get_chipid) - return -ENXIO; - - ret = eemi_ops->get_chipid(&idcode, &version); + ret = zynqmp_pm_get_chipid(&idcode, &version); if (ret < 0) return ret; @@ -61,10 +56,6 @@ static int zynqmp_nvmem_probe(struct platform_device *pdev) if (!priv) return -ENOMEM; - eemi_ops = zynqmp_pm_get_eemi_ops(); - if (IS_ERR(eemi_ops)) - return PTR_ERR(eemi_ops); - priv->dev = dev; econfig.dev = dev; econfig.reg_read = zynqmp_nvmem_read; diff --git a/drivers/of/platform.c b/drivers/of/platform.c index 3627fee60215..071f04da32c8 100644 --- a/drivers/of/platform.c +++ b/drivers/of/platform.c @@ -538,7 +538,9 @@ static int __init of_platform_default_populate_init(void) } /* Populate everything else. */ + fw_devlink_pause(); of_platform_default_populate(NULL, NULL, NULL); + fw_devlink_resume(); return 0; } diff --git a/drivers/parport/daisy.c b/drivers/parport/daisy.c index 3b00e2c8e2e9..6d78ec3a762f 100644 --- a/drivers/parport/daisy.c +++ b/drivers/parport/daisy.c @@ -30,12 +30,6 @@ #undef DEBUG -#ifdef DEBUG -#define DPRINTK(stuff...) printk(stuff) -#else -#define DPRINTK(stuff...) -#endif - static struct daisydev { struct daisydev *next; struct parport *port; @@ -145,8 +139,7 @@ again: ((num_ports = num_mux_ports(port)) == 2 || num_ports == 4)) { /* Leave original as port zero. */ port->muxport = 0; - printk(KERN_INFO - "%s: 1st (default) port of %d-way multiplexor\n", + pr_info("%s: 1st (default) port of %d-way multiplexor\n", port->name, num_ports); for (i = 1; i < num_ports; i++) { /* Clone the port. */ @@ -159,8 +152,7 @@ again: continue; } - printk(KERN_INFO - "%s: %d%s port of %d-way multiplexor on %s\n", + pr_info("%s: %d%s port of %d-way multiplexor on %s\n", extra->name, i + 1, th[i + 1], num_ports, port->name); @@ -323,8 +315,7 @@ static int cpp_daisy(struct parport *port, int cmd) | PARPORT_STATUS_PAPEROUT | PARPORT_STATUS_SELECT | PARPORT_STATUS_ERROR)) { - DPRINTK(KERN_DEBUG "%s: cpp_daisy: aa5500ff(%02x)\n", - port->name, s); + pr_debug("%s: cpp_daisy: aa5500ff(%02x)\n", port->name, s); return -ENXIO; } @@ -334,8 +325,7 @@ static int cpp_daisy(struct parport *port, int cmd) | PARPORT_STATUS_SELECT | PARPORT_STATUS_ERROR); if (s != (PARPORT_STATUS_SELECT | PARPORT_STATUS_ERROR)) { - DPRINTK(KERN_DEBUG "%s: cpp_daisy: aa5500ff87(%02x)\n", - port->name, s); + pr_debug("%s: cpp_daisy: aa5500ff87(%02x)\n", port->name, s); return -ENXIO; } @@ -370,7 +360,7 @@ static int cpp_mux(struct parport *port, int cmd) s = parport_read_status(port); if (!(s & PARPORT_STATUS_ACK)) { - DPRINTK(KERN_DEBUG "%s: cpp_mux: aa55f00f52ad%02x(%02x)\n", + pr_debug("%s: cpp_mux: aa55f00f52ad%02x(%02x)\n", port->name, cmd, s); return -EIO; } @@ -456,8 +446,7 @@ static int assign_addrs(struct parport *port) | PARPORT_STATUS_PAPEROUT | PARPORT_STATUS_SELECT | PARPORT_STATUS_ERROR)) { - DPRINTK(KERN_DEBUG "%s: assign_addrs: aa5500ff(%02x)\n", - port->name, s); + pr_debug("%s: assign_addrs: aa5500ff(%02x)\n", port->name, s); return 0; } @@ -467,8 +456,7 @@ static int assign_addrs(struct parport *port) | PARPORT_STATUS_SELECT | PARPORT_STATUS_ERROR); if (s != (PARPORT_STATUS_SELECT | PARPORT_STATUS_ERROR)) { - DPRINTK(KERN_DEBUG "%s: assign_addrs: aa5500ff87(%02x)\n", - port->name, s); + pr_debug("%s: assign_addrs: aa5500ff87(%02x)\n", port->name, s); return 0; } @@ -505,8 +493,7 @@ static int assign_addrs(struct parport *port) parport_write_data(port, 0xff); udelay(2); detected = numdevs - thisdev; - DPRINTK(KERN_DEBUG "%s: Found %d daisy-chained devices\n", port->name, - detected); + pr_debug("%s: Found %d daisy-chained devices\n", port->name, detected); /* Ask the new devices to introduce themselves. */ deviceid = kmalloc(1024, GFP_KERNEL); diff --git a/drivers/parport/ieee1284.c b/drivers/parport/ieee1284.c index 90fb73575495..f28d6a3c5a68 100644 --- a/drivers/parport/ieee1284.c +++ b/drivers/parport/ieee1284.c @@ -31,12 +31,6 @@ #undef DEBUG /* Don't want a garbled console */ #endif -#ifdef DEBUG -#define DPRINTK(stuff...) printk (stuff) -#else -#define DPRINTK(stuff...) -#endif - /* Make parport_wait_peripheral wake up. * It will be useful to call this from an interrupt handler. */ static void parport_ieee1284_wakeup (struct parport *port) @@ -258,12 +252,11 @@ static void parport_ieee1284_terminate (struct parport *port) PARPORT_STATUS_PAPEROUT, PARPORT_STATUS_PAPEROUT); if (r) - DPRINTK (KERN_INFO "%s: Timeout at event 49\n", + pr_debug("%s: Timeout at event 49\n", port->name); parport_data_forward (port); - DPRINTK (KERN_DEBUG "%s: ECP direction: forward\n", - port->name); + pr_debug("%s: ECP direction: forward\n", port->name); port->ieee1284.phase = IEEE1284_PH_FWD_IDLE; } @@ -281,8 +274,7 @@ static void parport_ieee1284_terminate (struct parport *port) /* Event 24: nAck goes low */ r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, 0); if (r) - DPRINTK (KERN_INFO "%s: Timeout at event 24\n", - port->name); + pr_debug("%s: Timeout at event 24\n", port->name); /* Event 25: Set nAutoFd low */ parport_frob_control (port, @@ -294,8 +286,7 @@ static void parport_ieee1284_terminate (struct parport *port) PARPORT_STATUS_ACK, PARPORT_STATUS_ACK); if (r) - DPRINTK (KERN_INFO "%s: Timeout at event 27\n", - port->name); + pr_debug("%s: Timeout at event 27\n", port->name); /* Event 29: Set nAutoFd high */ parport_frob_control (port, PARPORT_CONTROL_AUTOFD, 0); @@ -304,8 +295,7 @@ static void parport_ieee1284_terminate (struct parport *port) port->ieee1284.mode = IEEE1284_MODE_COMPAT; port->ieee1284.phase = IEEE1284_PH_FWD_IDLE; - DPRINTK (KERN_DEBUG "%s: In compatibility (forward idle) mode\n", - port->name); + pr_debug("%s: In compatibility (forward idle) mode\n", port->name); } #endif /* IEEE1284 support */ @@ -329,7 +319,7 @@ int parport_negotiate (struct parport *port, int mode) #ifndef CONFIG_PARPORT_1284 if (mode == IEEE1284_MODE_COMPAT) return 0; - printk (KERN_ERR "parport: IEEE1284 not supported in this kernel\n"); + pr_err("parport: IEEE1284 not supported in this kernel\n"); return -1; #else int m = mode & ~IEEE1284_ADDR; @@ -406,8 +396,7 @@ int parport_negotiate (struct parport *port, int mode) PARPORT_CONTROL_SELECT | PARPORT_CONTROL_AUTOFD, PARPORT_CONTROL_SELECT); - DPRINTK (KERN_DEBUG - "%s: Peripheral not IEEE1284 compliant (0x%02X)\n", + pr_debug("%s: Peripheral not IEEE1284 compliant (0x%02X)\n", port->name, parport_read_status (port)); port->ieee1284.phase = IEEE1284_PH_FWD_IDLE; return -1; /* Not IEEE1284 compliant */ @@ -430,8 +419,7 @@ int parport_negotiate (struct parport *port, int mode) PARPORT_STATUS_ACK, PARPORT_STATUS_ACK)) { /* This shouldn't really happen with a compliant device. */ - DPRINTK (KERN_DEBUG - "%s: Mode 0x%02x not supported? (0x%02x)\n", + pr_debug("%s: Mode 0x%02x not supported? (0x%02x)\n", port->name, mode, port->ops->read_status (port)); parport_ieee1284_terminate (port); return 1; @@ -442,7 +430,7 @@ int parport_negotiate (struct parport *port, int mode) /* xflag should be high for all modes other than nibble (0). */ if (mode && !xflag) { /* Mode not supported. */ - DPRINTK (KERN_DEBUG "%s: Mode 0x%02x rejected by peripheral\n", + pr_debug("%s: Mode 0x%02x rejected by peripheral\n", port->name, mode); parport_ieee1284_terminate (port); return 1; @@ -463,9 +451,7 @@ int parport_negotiate (struct parport *port, int mode) /* Event 52: nAck goes low */ if (parport_wait_peripheral (port, PARPORT_STATUS_ACK, 0)) { /* This peripheral is _very_ slow. */ - DPRINTK (KERN_DEBUG - "%s: Event 52 didn't happen\n", - port->name); + pr_debug("%s: Event 52 didn't happen\n", port->name); parport_ieee1284_terminate (port); return 1; } @@ -481,10 +467,9 @@ int parport_negotiate (struct parport *port, int mode) PARPORT_STATUS_ACK)) { /* This shouldn't really happen with a compliant * device. */ - DPRINTK (KERN_DEBUG - "%s: Mode 0x%02x not supported? (0x%02x)\n", + pr_debug("%s: Mode 0x%02x not supported? (0x%02x)\n", port->name, mode, - port->ops->read_status (port)); + port->ops->read_status(port)); parport_ieee1284_terminate (port); return 1; } @@ -495,8 +480,8 @@ int parport_negotiate (struct parport *port, int mode) /* xflag should be high. */ if (!xflag) { /* Extended mode not supported. */ - DPRINTK (KERN_DEBUG "%s: Extended mode 0x%02x not " - "supported\n", port->name, mode); + pr_debug("%s: Extended mode 0x%02x not supported\n", + port->name, mode); parport_ieee1284_terminate (port); return 1; } @@ -505,7 +490,7 @@ int parport_negotiate (struct parport *port, int mode) } /* Mode is supported */ - DPRINTK (KERN_DEBUG "%s: In mode 0x%02x\n", port->name, mode); + pr_debug("%s: In mode 0x%02x\n", port->name, mode); port->ieee1284.mode = mode; /* But ECP is special */ @@ -522,13 +507,11 @@ int parport_negotiate (struct parport *port, int mode) PARPORT_STATUS_PAPEROUT, PARPORT_STATUS_PAPEROUT); if (r) { - DPRINTK (KERN_INFO "%s: Timeout at event 31\n", - port->name); + pr_debug("%s: Timeout at event 31\n", port->name); } port->ieee1284.phase = IEEE1284_PH_FWD_IDLE; - DPRINTK (KERN_DEBUG "%s: ECP direction: forward\n", - port->name); + pr_debug("%s: ECP direction: forward\n", port->name); } else switch (mode) { case IEEE1284_MODE_NIBBLE: case IEEE1284_MODE_BYTE: @@ -573,7 +556,7 @@ void parport_ieee1284_interrupt (void *handle) if (port->ieee1284.phase == IEEE1284_PH_REV_IDLE) { /* An interrupt in this phase means that data * is now available. */ - DPRINTK (KERN_DEBUG "%s: Data available\n", port->name); + pr_debug("%s: Data available\n", port->name); parport_ieee1284_ack_data_avail (port); } #endif /* IEEE1284 support */ @@ -617,13 +600,12 @@ ssize_t parport_write (struct parport *port, const void *buffer, size_t len) parport_negotiate (port, IEEE1284_MODE_COMPAT); /* fall through */ case IEEE1284_MODE_COMPAT: - DPRINTK (KERN_DEBUG "%s: Using compatibility mode\n", - port->name); + pr_debug("%s: Using compatibility mode\n", port->name); fn = port->ops->compat_write_data; break; case IEEE1284_MODE_EPP: - DPRINTK (KERN_DEBUG "%s: Using EPP mode\n", port->name); + pr_debug("%s: Using EPP mode\n", port->name); if (addr) { fn = port->ops->epp_write_addr; } else { @@ -631,8 +613,7 @@ ssize_t parport_write (struct parport *port, const void *buffer, size_t len) } break; case IEEE1284_MODE_EPPSWE: - DPRINTK (KERN_DEBUG "%s: Using software-emulated EPP mode\n", - port->name); + pr_debug("%s: Using software-emulated EPP mode\n", port->name); if (addr) { fn = parport_ieee1284_epp_write_addr; } else { @@ -641,7 +622,7 @@ ssize_t parport_write (struct parport *port, const void *buffer, size_t len) break; case IEEE1284_MODE_ECP: case IEEE1284_MODE_ECPRLE: - DPRINTK (KERN_DEBUG "%s: Using ECP mode\n", port->name); + pr_debug("%s: Using ECP mode\n", port->name); if (addr) { fn = port->ops->ecp_write_addr; } else { @@ -650,8 +631,7 @@ ssize_t parport_write (struct parport *port, const void *buffer, size_t len) break; case IEEE1284_MODE_ECPSWE: - DPRINTK (KERN_DEBUG "%s: Using software-emulated ECP mode\n", - port->name); + pr_debug("%s: Using software-emulated ECP mode\n", port->name); /* The caller has specified that it must be emulated, * even if we have ECP hardware! */ if (addr) { @@ -662,13 +642,13 @@ ssize_t parport_write (struct parport *port, const void *buffer, size_t len) break; default: - DPRINTK (KERN_DEBUG "%s: Unknown mode 0x%02x\n", port->name, - port->ieee1284.mode); + pr_debug("%s: Unknown mode 0x%02x\n", + port->name, port->ieee1284.mode); return -ENOSYS; } retval = (*fn) (port, buffer, len, 0); - DPRINTK (KERN_DEBUG "%s: wrote %d/%d bytes\n", port->name, retval, len); + pr_debug("%s: wrote %zd/%zu bytes\n", port->name, retval, len); return retval; #endif /* IEEE1284 support */ } @@ -694,7 +674,7 @@ ssize_t parport_write (struct parport *port, const void *buffer, size_t len) ssize_t parport_read (struct parport *port, void *buffer, size_t len) { #ifndef CONFIG_PARPORT_1284 - printk (KERN_ERR "parport: IEEE1284 not supported in this kernel\n"); + pr_err("parport: IEEE1284 not supported in this kernel\n"); return -ENODEV; #else int mode = port->physport->ieee1284.mode; @@ -715,7 +695,7 @@ ssize_t parport_read (struct parport *port, void *buffer, size_t len) if ((port->physport->modes & PARPORT_MODE_TRISTATE) && !parport_negotiate (port, IEEE1284_MODE_BYTE)) { /* got into BYTE mode OK */ - DPRINTK (KERN_DEBUG "%s: Using byte mode\n", port->name); + pr_debug("%s: Using byte mode\n", port->name); fn = port->ops->byte_read_data; break; } @@ -724,17 +704,17 @@ ssize_t parport_read (struct parport *port, void *buffer, size_t len) } /* fall through - to NIBBLE */ case IEEE1284_MODE_NIBBLE: - DPRINTK (KERN_DEBUG "%s: Using nibble mode\n", port->name); + pr_debug("%s: Using nibble mode\n", port->name); fn = port->ops->nibble_read_data; break; case IEEE1284_MODE_BYTE: - DPRINTK (KERN_DEBUG "%s: Using byte mode\n", port->name); + pr_debug("%s: Using byte mode\n", port->name); fn = port->ops->byte_read_data; break; case IEEE1284_MODE_EPP: - DPRINTK (KERN_DEBUG "%s: Using EPP mode\n", port->name); + pr_debug("%s: Using EPP mode\n", port->name); if (addr) { fn = port->ops->epp_read_addr; } else { @@ -742,8 +722,7 @@ ssize_t parport_read (struct parport *port, void *buffer, size_t len) } break; case IEEE1284_MODE_EPPSWE: - DPRINTK (KERN_DEBUG "%s: Using software-emulated EPP mode\n", - port->name); + pr_debug("%s: Using software-emulated EPP mode\n", port->name); if (addr) { fn = parport_ieee1284_epp_read_addr; } else { @@ -752,19 +731,18 @@ ssize_t parport_read (struct parport *port, void *buffer, size_t len) break; case IEEE1284_MODE_ECP: case IEEE1284_MODE_ECPRLE: - DPRINTK (KERN_DEBUG "%s: Using ECP mode\n", port->name); + pr_debug("%s: Using ECP mode\n", port->name); fn = port->ops->ecp_read_data; break; case IEEE1284_MODE_ECPSWE: - DPRINTK (KERN_DEBUG "%s: Using software-emulated ECP mode\n", - port->name); + pr_debug("%s: Using software-emulated ECP mode\n", port->name); fn = parport_ieee1284_ecp_read_data; break; default: - DPRINTK (KERN_DEBUG "%s: Unknown mode 0x%02x\n", port->name, - port->physport->ieee1284.mode); + pr_debug("%s: Unknown mode 0x%02x\n", + port->name, port->physport->ieee1284.mode); return -ENOSYS; } diff --git a/drivers/parport/ieee1284_ops.c b/drivers/parport/ieee1284_ops.c index 5d41dda6da4e..2c11bd3fe1fd 100644 --- a/drivers/parport/ieee1284_ops.c +++ b/drivers/parport/ieee1284_ops.c @@ -27,12 +27,6 @@ #undef DEBUG /* Don't want a garbled console */ #endif -#ifdef DEBUG -#define DPRINTK(stuff...) printk (stuff) -#else -#define DPRINTK(stuff...) -#endif - /*** * * One-way data transfer functions. * * ***/ @@ -115,7 +109,7 @@ size_t parport_ieee1284_write_compat (struct parport *port, if (signal_pending (current)) break; - DPRINTK (KERN_DEBUG "%s: Timed out\n", port->name); + pr_debug("%s: Timed out\n", port->name); break; ready: @@ -178,9 +172,8 @@ size_t parport_ieee1284_read_nibble (struct parport *port, if (parport_wait_peripheral (port, PARPORT_STATUS_ACK, 0)) { /* Timeout -- no more data? */ - DPRINTK (KERN_DEBUG - "%s: Nibble timeout at event 9 (%d bytes)\n", - port->name, i/2); + pr_debug("%s: Nibble timeout at event 9 (%d bytes)\n", + port->name, i / 2); parport_frob_control (port, PARPORT_CONTROL_AUTOFD, 0); break; } @@ -201,8 +194,7 @@ size_t parport_ieee1284_read_nibble (struct parport *port, PARPORT_STATUS_ACK, PARPORT_STATUS_ACK)) { /* Timeout -- no more data? */ - DPRINTK (KERN_DEBUG - "%s: Nibble timeout at event 11\n", + pr_debug("%s: Nibble timeout at event 11\n", port->name); break; } @@ -219,9 +211,8 @@ size_t parport_ieee1284_read_nibble (struct parport *port, /* Read the last nibble without checking data avail. */ if (parport_read_status (port) & PARPORT_STATUS_ERROR) { end_of_data: - DPRINTK (KERN_DEBUG - "%s: No more nibble data (%d bytes)\n", - port->name, i/2); + pr_debug("%s: No more nibble data (%d bytes)\n", + port->name, i / 2); /* Go to reverse idle phase. */ parport_frob_control (port, @@ -272,8 +263,7 @@ size_t parport_ieee1284_read_byte (struct parport *port, /* Timeout -- no more data? */ parport_frob_control (port, PARPORT_CONTROL_AUTOFD, 0); - DPRINTK (KERN_DEBUG "%s: Byte timeout at event 9\n", - port->name); + pr_debug("%s: Byte timeout at event 9\n", port->name); break; } @@ -288,8 +278,7 @@ size_t parport_ieee1284_read_byte (struct parport *port, PARPORT_STATUS_ACK, PARPORT_STATUS_ACK)) { /* Timeout -- no more data? */ - DPRINTK (KERN_DEBUG "%s: Byte timeout at event 11\n", - port->name); + pr_debug("%s: Byte timeout at event 11\n", port->name); break; } @@ -307,8 +296,7 @@ size_t parport_ieee1284_read_byte (struct parport *port, /* Read the last byte without checking data avail. */ if (parport_read_status (port) & PARPORT_STATUS_ERROR) { end_of_data: - DPRINTK (KERN_DEBUG - "%s: No more byte data (%zd bytes)\n", + pr_debug("%s: No more byte data (%zd bytes)\n", port->name, count); /* Go to reverse idle phase. */ @@ -353,12 +341,10 @@ int ecp_forward_to_reverse (struct parport *port) PARPORT_STATUS_PAPEROUT, 0); if (!retval) { - DPRINTK (KERN_DEBUG "%s: ECP direction: reverse\n", - port->name); + pr_debug("%s: ECP direction: reverse\n", port->name); port->ieee1284.phase = IEEE1284_PH_REV_IDLE; } else { - DPRINTK (KERN_DEBUG "%s: ECP direction: failed to reverse\n", - port->name); + pr_debug("%s: ECP direction: failed to reverse\n", port->name); port->ieee1284.phase = IEEE1284_PH_ECP_DIR_UNKNOWN; } @@ -384,12 +370,10 @@ int ecp_reverse_to_forward (struct parport *port) if (!retval) { parport_data_forward (port); - DPRINTK (KERN_DEBUG "%s: ECP direction: forward\n", - port->name); + pr_debug("%s: ECP direction: forward\n", port->name); port->ieee1284.phase = IEEE1284_PH_FWD_IDLE; } else { - DPRINTK (KERN_DEBUG - "%s: ECP direction: failed to switch forward\n", + pr_debug("%s: ECP direction: failed to switch forward\n", port->name); port->ieee1284.phase = IEEE1284_PH_ECP_DIR_UNKNOWN; } @@ -450,7 +434,7 @@ size_t parport_ieee1284_ecp_write_data (struct parport *port, } /* Time for Host Transfer Recovery (page 41 of IEEE1284) */ - DPRINTK (KERN_DEBUG "%s: ECP transfer stalled!\n", port->name); + pr_debug("%s: ECP transfer stalled!\n", port->name); parport_frob_control (port, PARPORT_CONTROL_INIT, PARPORT_CONTROL_INIT); @@ -466,8 +450,7 @@ size_t parport_ieee1284_ecp_write_data (struct parport *port, if (!(parport_read_status (port) & PARPORT_STATUS_PAPEROUT)) break; - DPRINTK (KERN_DEBUG "%s: Host transfer recovered\n", - port->name); + pr_debug("%s: Host transfer recovered\n", port->name); if (time_after_eq (jiffies, expire)) break; goto try_again; @@ -565,23 +548,20 @@ size_t parport_ieee1284_ecp_read_data (struct parport *port, command or a normal data byte, don't accept it. */ if (command) { if (byte & 0x80) { - DPRINTK (KERN_DEBUG "%s: stopping short at " - "channel command (%02x)\n", + pr_debug("%s: stopping short at channel command (%02x)\n", port->name, byte); goto out; } else if (port->ieee1284.mode != IEEE1284_MODE_ECPRLE) - DPRINTK (KERN_DEBUG "%s: device illegally " - "using RLE; accepting anyway\n", + pr_debug("%s: device illegally using RLE; accepting anyway\n", port->name); rle_count = byte + 1; /* Are we allowed to read that many bytes? */ if (rle_count > (len - count)) { - DPRINTK (KERN_DEBUG "%s: leaving %d RLE bytes " - "for next time\n", port->name, - rle_count); + pr_debug("%s: leaving %d RLE bytes for next time\n", + port->name, rle_count); break; } @@ -596,11 +576,10 @@ size_t parport_ieee1284_ecp_read_data (struct parport *port, PARPORT_STATUS_ACK)) { /* It's gone wrong. Return what data we have to the caller. */ - DPRINTK (KERN_DEBUG "ECP read timed out at 45\n"); + pr_debug("ECP read timed out at 45\n"); if (command) - printk (KERN_WARNING - "%s: command ignored (%02x)\n", + pr_warn("%s: command ignored (%02x)\n", port->name, byte); break; @@ -620,7 +599,7 @@ size_t parport_ieee1284_ecp_read_data (struct parport *port, memset (buf, byte, rle_count); buf += rle_count; count += rle_count; - DPRINTK (KERN_DEBUG "%s: decompressed to %d bytes\n", + pr_debug("%s: decompressed to %d bytes\n", port->name, rle_count); } else { /* Normal data byte. */ @@ -686,7 +665,7 @@ size_t parport_ieee1284_ecp_write_addr (struct parport *port, } /* Time for Host Transfer Recovery (page 41 of IEEE1284) */ - DPRINTK (KERN_DEBUG "%s: ECP transfer stalled!\n", port->name); + pr_debug("%s: ECP transfer stalled!\n", port->name); parport_frob_control (port, PARPORT_CONTROL_INIT, PARPORT_CONTROL_INIT); @@ -702,8 +681,7 @@ size_t parport_ieee1284_ecp_write_addr (struct parport *port, if (!(parport_read_status (port) & PARPORT_STATUS_PAPEROUT)) break; - DPRINTK (KERN_DEBUG "%s: Host transfer recovered\n", - port->name); + pr_debug("%s: Host transfer recovered\n", port->name); if (time_after_eq (jiffies, expire)) break; goto try_again; diff --git a/drivers/parport/parport_amiga.c b/drivers/parport/parport_amiga.c index 3301861f69fa..1e88bcfe0d7b 100644 --- a/drivers/parport/parport_amiga.c +++ b/drivers/parport/parport_amiga.c @@ -28,16 +28,10 @@ #include #undef DEBUG -#ifdef DEBUG -#define DPRINTK printk -#else -#define DPRINTK(x...) do { } while (0) -#endif - static void amiga_write_data(struct parport *p, unsigned char data) { - DPRINTK(KERN_DEBUG "write_data %c\n",data); + pr_debug("write_data %c\n", data); /* Triggers also /STROBE. This behavior cannot be changed */ ciaa.prb = data; mb(); @@ -59,13 +53,13 @@ static unsigned char control_amiga_to_pc(unsigned char control) static void amiga_write_control(struct parport *p, unsigned char control) { - DPRINTK(KERN_DEBUG "write_control %02x\n",control); + pr_debug("write_control %02x\n", control); /* No implementation possible */ } static unsigned char amiga_read_control( struct parport *p) { - DPRINTK(KERN_DEBUG "read_control \n"); + pr_debug("read_control\n"); return control_amiga_to_pc(0); } @@ -73,7 +67,7 @@ static unsigned char amiga_frob_control( struct parport *p, unsigned char mask, { unsigned char old; - DPRINTK(KERN_DEBUG "frob_control mask %02x, value %02x\n",mask,val); + pr_debug("frob_control mask %02x, value %02x\n", mask, val); old = amiga_read_control(p); amiga_write_control(p, (old & ~mask) ^ val); return old; @@ -99,7 +93,7 @@ static unsigned char amiga_read_status(struct parport *p) unsigned char status; status = status_amiga_to_pc(ciab.pra & 7); - DPRINTK(KERN_DEBUG "read_status %02x\n", status); + pr_debug("read_status %02x\n", status); return status; } @@ -115,14 +109,14 @@ static void amiga_disable_irq(struct parport *p) static void amiga_data_forward(struct parport *p) { - DPRINTK(KERN_DEBUG "forward\n"); + pr_debug("forward\n"); ciaa.ddrb = 0xff; /* all pins output */ mb(); } static void amiga_data_reverse(struct parport *p) { - DPRINTK(KERN_DEBUG "reverse\n"); + pr_debug("reverse\n"); ciaa.ddrb = 0; /* all pins input */ mb(); } @@ -212,7 +206,7 @@ static int __init amiga_parallel_probe(struct platform_device *pdev) if (err) goto out_irq; - printk(KERN_INFO "%s: Amiga built-in port using irq\n", p->name); + pr_info("%s: Amiga built-in port using irq\n", p->name); /* XXX: set operating mode */ parport_announce_port(p); diff --git a/drivers/parport/parport_atari.c b/drivers/parport/parport_atari.c index f8dd368bfdbb..2ff0fe053e6e 100644 --- a/drivers/parport/parport_atari.c +++ b/drivers/parport/parport_atari.c @@ -200,7 +200,7 @@ static int __init parport_atari_init(void) } this_port = p; - printk(KERN_INFO "%s: Atari built-in port using irq\n", p->name); + pr_info("%s: Atari built-in port using irq\n", p->name); parport_announce_port (p); return 0; diff --git a/drivers/parport/parport_cs.c b/drivers/parport/parport_cs.c index e77044c2bf62..8e7e3ac4bb87 100644 --- a/drivers/parport/parport_cs.c +++ b/drivers/parport/parport_cs.c @@ -142,10 +142,8 @@ static int parport_config(struct pcmcia_device *link) link->irq, PARPORT_DMA_NONE, &link->dev, IRQF_SHARED); if (p == NULL) { - printk(KERN_NOTICE "parport_cs: parport_pc_probe_port() at " - "0x%3x, irq %u failed\n", - (unsigned int) link->resource[0]->start, - link->irq); + pr_notice("parport_cs: parport_pc_probe_port() at 0x%3x, irq %u failed\n", + (unsigned int)link->resource[0]->start, link->irq); goto failed; } diff --git a/drivers/parport/parport_gsc.c b/drivers/parport/parport_gsc.c index 922535a118ba..9228e8f90309 100644 --- a/drivers/parport/parport_gsc.c +++ b/drivers/parport/parport_gsc.c @@ -238,14 +238,14 @@ struct parport *parport_gsc_probe_port(unsigned long base, priv = kzalloc (sizeof (struct parport_gsc_private), GFP_KERNEL); if (!priv) { - printk (KERN_DEBUG "parport (0x%lx): no memory!\n", base); + printk(KERN_DEBUG "parport (0x%lx): no memory!\n", base); return NULL; } ops = kmemdup(&parport_gsc_ops, sizeof(struct parport_operations), GFP_KERNEL); if (!ops) { - printk (KERN_DEBUG "parport (0x%lx): no memory for ops!\n", - base); + printk(KERN_DEBUG "parport (0x%lx): no memory for ops!\n", + base); kfree (priv); return NULL; } @@ -282,7 +282,7 @@ struct parport *parport_gsc_probe_port(unsigned long base, p->size = (p->modes & PARPORT_MODE_EPP)?8:3; p->private_data = priv; - printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base); + pr_info("%s: PC-style at 0x%lx", p->name, p->base); p->irq = irq; if (p->irq == PARPORT_IRQ_AUTO) { p->irq = PARPORT_IRQ_NONE; @@ -299,12 +299,16 @@ struct parport *parport_gsc_probe_port(unsigned long base, p->dma = PARPORT_DMA_NONE; pr_cont(" ["); -#define printmode(x) {if(p->modes&PARPORT_MODE_##x){pr_cont("%s%s",f?",":"",#x);f++;}} +#define printmode(x) \ +do { \ + if (p->modes & PARPORT_MODE_##x) \ + pr_cont("%s%s", f++ ? "," : "", #x); \ +} while (0) { int f = 0; printmode(PCSPP); printmode(TRISTATE); - printmode(COMPAT) + printmode(COMPAT); printmode(EPP); // printmode(ECP); // printmode(DMA); @@ -315,8 +319,7 @@ struct parport *parport_gsc_probe_port(unsigned long base, if (p->irq != PARPORT_IRQ_NONE) { if (request_irq (p->irq, parport_irq_handler, 0, p->name, p)) { - printk (KERN_WARNING "%s: irq %d in use, " - "resorting to polled operation\n", + pr_warn("%s: irq %d in use, resorting to polled operation\n", p->name, p->irq); p->irq = PARPORT_IRQ_NONE; p->dma = PARPORT_DMA_NONE; @@ -347,7 +350,7 @@ static int __init parport_init_chip(struct parisc_device *dev) unsigned long port; if (!dev->irq) { - printk(KERN_WARNING "IRQ not found for parallel device at 0x%llx\n", + pr_warn("IRQ not found for parallel device at 0x%llx\n", (unsigned long long)dev->hpa.start); return -ENODEV; } @@ -360,11 +363,11 @@ static int __init parport_init_chip(struct parisc_device *dev) if (boot_cpu_data.cpu_type > pcxt && !pdc_add_valid(port+4)) { /* Initialize bidirectional-mode (0x10) & data-tranfer-mode #1 (0x20) */ - printk("%s: initialize bidirectional-mode.\n", __func__); + pr_info("%s: initialize bidirectional-mode\n", __func__); parport_writeb ( (0x10 + 0x20), port + 4); } else { - printk("%s: enhanced parport-modes not supported.\n", __func__); + pr_info("%s: enhanced parport-modes not supported\n", __func__); } p = parport_gsc_probe_port(port, 0, dev->irq, diff --git a/drivers/parport/parport_gsc.h b/drivers/parport/parport_gsc.h index 4c4d3c6cd77e..9301217edf12 100644 --- a/drivers/parport/parport_gsc.h +++ b/drivers/parport/parport_gsc.h @@ -71,7 +71,7 @@ struct parport_gsc_private { static inline void parport_gsc_write_data(struct parport *p, unsigned char d) { #ifdef DEBUG_PARPORT - printk (KERN_DEBUG "parport_gsc_write_data(%p,0x%02x)\n", p, d); + printk(KERN_DEBUG "%s(%p,0x%02x)\n", __func__, p, d); #endif parport_writeb(d, DATA(p)); } @@ -80,8 +80,7 @@ static inline unsigned char parport_gsc_read_data(struct parport *p) { unsigned char val = parport_readb (DATA (p)); #ifdef DEBUG_PARPORT - printk (KERN_DEBUG "parport_gsc_read_data(%p) = 0x%02x\n", - p, val); + printk(KERN_DEBUG "%s(%p) = 0x%02x\n", __func__, p, val); #endif return val; } @@ -95,9 +94,9 @@ static inline unsigned char __parport_gsc_frob_control(struct parport *p, struct parport_gsc_private *priv = p->physport->private_data; unsigned char ctr = priv->ctr; #ifdef DEBUG_PARPORT - printk (KERN_DEBUG - "__parport_gsc_frob_control(%02x,%02x): %02x -> %02x\n", - mask, val, ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable); + printk(KERN_DEBUG "%s(%02x,%02x): %02x -> %02x\n", + __func__, mask, val, + ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable); #endif ctr = (ctr & ~mask) ^ val; ctr &= priv->ctr_writable; /* only write writable bits. */ @@ -126,8 +125,8 @@ static inline void parport_gsc_write_control(struct parport *p, /* Take this out when drivers have adapted to newer interface. */ if (d & 0x20) { - printk (KERN_DEBUG "%s (%s): use data_reverse for this!\n", - p->name, p->cad->name); + printk(KERN_DEBUG "%s (%s): use data_reverse for this!\n", + p->name, p->cad->name); parport_gsc_data_reverse (p); } @@ -155,9 +154,9 @@ static inline unsigned char parport_gsc_frob_control(struct parport *p, /* Take this out when drivers have adapted to newer interface. */ if (mask & 0x20) { - printk (KERN_DEBUG "%s (%s): use data_%s for this!\n", - p->name, p->cad->name, - (val & 0x20) ? "reverse" : "forward"); + printk(KERN_DEBUG "%s (%s): use data_%s for this!\n", + p->name, p->cad->name, + (val & 0x20) ? "reverse" : "forward"); if (val & 0x20) parport_gsc_data_reverse (p); else diff --git a/drivers/parport/parport_ip32.c b/drivers/parport/parport_ip32.c index ab215b650f41..48b084e86dc6 100644 --- a/drivers/parport/parport_ip32.c +++ b/drivers/parport/parport_ip32.c @@ -328,19 +328,19 @@ static void parport_ip32_dump_state(struct parport *p, char *str, "TST", "CFG"}; unsigned int ecr = readb(priv->regs.ecr); printk(KERN_DEBUG PPIP32 " ecr=0x%02x", ecr); - printk(" %s", - ecr_modes[(ecr & ECR_MODE_MASK) >> ECR_MODE_SHIFT]); + pr_cont(" %s", + ecr_modes[(ecr & ECR_MODE_MASK) >> ECR_MODE_SHIFT]); if (ecr & ECR_nERRINTR) - printk(",nErrIntrEn"); + pr_cont(",nErrIntrEn"); if (ecr & ECR_DMAEN) - printk(",dmaEn"); + pr_cont(",dmaEn"); if (ecr & ECR_SERVINTR) - printk(",serviceIntr"); + pr_cont(",serviceIntr"); if (ecr & ECR_F_FULL) - printk(",f_full"); + pr_cont(",f_full"); if (ecr & ECR_F_EMPTY) - printk(",f_empty"); - printk("\n"); + pr_cont(",f_empty"); + pr_cont("\n"); } if (show_ecp_config) { unsigned int oecr, cnfgA, cnfgB; @@ -352,52 +352,53 @@ static void parport_ip32_dump_state(struct parport *p, char *str, writeb(ECR_MODE_PS2, priv->regs.ecr); writeb(oecr, priv->regs.ecr); printk(KERN_DEBUG PPIP32 " cnfgA=0x%02x", cnfgA); - printk(" ISA-%s", (cnfgA & CNFGA_IRQ) ? "Level" : "Pulses"); + pr_cont(" ISA-%s", (cnfgA & CNFGA_IRQ) ? "Level" : "Pulses"); switch (cnfgA & CNFGA_ID_MASK) { case CNFGA_ID_8: - printk(",8 bits"); + pr_cont(",8 bits"); break; case CNFGA_ID_16: - printk(",16 bits"); + pr_cont(",16 bits"); break; case CNFGA_ID_32: - printk(",32 bits"); + pr_cont(",32 bits"); break; default: - printk(",unknown ID"); + pr_cont(",unknown ID"); break; } if (!(cnfgA & CNFGA_nBYTEINTRANS)) - printk(",ByteInTrans"); + pr_cont(",ByteInTrans"); if ((cnfgA & CNFGA_ID_MASK) != CNFGA_ID_8) - printk(",%d byte%s left", cnfgA & CNFGA_PWORDLEFT, - ((cnfgA & CNFGA_PWORDLEFT) > 1) ? "s" : ""); - printk("\n"); + pr_cont(",%d byte%s left", + cnfgA & CNFGA_PWORDLEFT, + ((cnfgA & CNFGA_PWORDLEFT) > 1) ? "s" : ""); + pr_cont("\n"); printk(KERN_DEBUG PPIP32 " cnfgB=0x%02x", cnfgB); - printk(" irq=%u,dma=%u", - (cnfgB & CNFGB_IRQ_MASK) >> CNFGB_IRQ_SHIFT, - (cnfgB & CNFGB_DMA_MASK) >> CNFGB_DMA_SHIFT); - printk(",intrValue=%d", !!(cnfgB & CNFGB_INTRVAL)); + pr_cont(" irq=%u,dma=%u", + (cnfgB & CNFGB_IRQ_MASK) >> CNFGB_IRQ_SHIFT, + (cnfgB & CNFGB_DMA_MASK) >> CNFGB_DMA_SHIFT); + pr_cont(",intrValue=%d", !!(cnfgB & CNFGB_INTRVAL)); if (cnfgB & CNFGB_COMPRESS) - printk(",compress"); - printk("\n"); + pr_cont(",compress"); + pr_cont("\n"); } for (i = 0; i < 2; i++) { unsigned int dcr = i ? priv->dcr_cache : readb(priv->regs.dcr); printk(KERN_DEBUG PPIP32 " dcr(%s)=0x%02x", i ? "soft" : "hard", dcr); - printk(" %s", (dcr & DCR_DIR) ? "rev" : "fwd"); + pr_cont(" %s", (dcr & DCR_DIR) ? "rev" : "fwd"); if (dcr & DCR_IRQ) - printk(",ackIntEn"); + pr_cont(",ackIntEn"); if (!(dcr & DCR_SELECT)) - printk(",nSelectIn"); + pr_cont(",nSelectIn"); if (dcr & DCR_nINIT) - printk(",nInit"); + pr_cont(",nInit"); if (!(dcr & DCR_AUTOFD)) - printk(",nAutoFD"); + pr_cont(",nAutoFD"); if (!(dcr & DCR_STROBE)) - printk(",nStrobe"); - printk("\n"); + pr_cont(",nStrobe"); + pr_cont("\n"); } #define sep (f++ ? ',' : ' ') { @@ -405,20 +406,20 @@ static void parport_ip32_dump_state(struct parport *p, char *str, unsigned int dsr = readb(priv->regs.dsr); printk(KERN_DEBUG PPIP32 " dsr=0x%02x", dsr); if (!(dsr & DSR_nBUSY)) - printk("%cBusy", sep); + pr_cont("%cBusy", sep); if (dsr & DSR_nACK) - printk("%cnAck", sep); + pr_cont("%cnAck", sep); if (dsr & DSR_PERROR) - printk("%cPError", sep); + pr_cont("%cPError", sep); if (dsr & DSR_SELECT) - printk("%cSelect", sep); + pr_cont("%cSelect", sep); if (dsr & DSR_nFAULT) - printk("%cnFault", sep); + pr_cont("%cnFault", sep); if (!(dsr & DSR_nPRINT)) - printk("%c(Print)", sep); + pr_cont("%c(Print)", sep); if (dsr & DSR_TIMEOUT) - printk("%cTimeout", sep); - printk("\n"); + pr_cont("%cTimeout", sep); + pr_cont("\n"); } #undef sep } @@ -1337,9 +1338,8 @@ static unsigned int parport_ip32_fwp_wait_interrupt(struct parport *p) ecr = parport_ip32_read_econtrol(p); if ((ecr & ECR_F_EMPTY) && !(ecr & ECR_SERVINTR) && !lost_interrupt) { - printk(KERN_WARNING PPIP32 - "%s: lost interrupt in %s\n", - p->name, __func__); + pr_warn(PPIP32 "%s: lost interrupt in %s\n", + p->name, __func__); lost_interrupt = 1; } } @@ -1643,8 +1643,8 @@ static size_t parport_ip32_compat_write_data(struct parport *p, DSR_nBUSY | DSR_nFAULT)) { /* Avoid to flood the logs */ if (ready_before) - printk(KERN_INFO PPIP32 "%s: not ready in %s\n", - p->name, __func__); + pr_info(PPIP32 "%s: not ready in %s\n", + p->name, __func__); ready_before = 0; goto stop; } @@ -1704,7 +1704,7 @@ static size_t parport_ip32_ecp_write_data(struct parport *p, /* Event 49: PError goes high. */ if (parport_wait_peripheral(p, DSR_PERROR, DSR_PERROR)) { - printk(KERN_DEBUG PPIP32 "%s: PError timeout in %s", + printk(KERN_DEBUG PPIP32 "%s: PError timeout in %s\n", p->name, __func__); physport->ieee1284.phase = IEEE1284_PH_ECP_DIR_UNKNOWN; return 0; @@ -1724,8 +1724,8 @@ static size_t parport_ip32_ecp_write_data(struct parport *p, DSR_nBUSY | DSR_nFAULT)) { /* Avoid to flood the logs */ if (ready_before) - printk(KERN_INFO PPIP32 "%s: not ready in %s\n", - p->name, __func__); + pr_info(PPIP32 "%s: not ready in %s\n", + p->name, __func__); ready_before = 0; goto stop; } @@ -2064,8 +2064,7 @@ static __init struct parport *parport_ip32_probe_port(void) p->modes |= PARPORT_MODE_TRISTATE; if (!parport_ip32_fifo_supported(p)) { - printk(KERN_WARNING PPIP32 - "%s: error: FIFO disabled\n", p->name); + pr_warn(PPIP32 "%s: error: FIFO disabled\n", p->name); /* Disable hardware modes depending on a working FIFO. */ features &= ~PARPORT_IP32_ENABLE_SPP; features &= ~PARPORT_IP32_ENABLE_ECP; @@ -2077,8 +2076,7 @@ static __init struct parport *parport_ip32_probe_port(void) if (features & PARPORT_IP32_ENABLE_IRQ) { int irq = MACEISA_PARALLEL_IRQ; if (request_irq(irq, parport_ip32_interrupt, 0, p->name, p)) { - printk(KERN_WARNING PPIP32 - "%s: error: IRQ disabled\n", p->name); + pr_warn(PPIP32 "%s: error: IRQ disabled\n", p->name); /* DMA cannot work without interrupts. */ features &= ~PARPORT_IP32_ENABLE_DMA; } else { @@ -2091,8 +2089,7 @@ static __init struct parport *parport_ip32_probe_port(void) /* Allocate DMA resources */ if (features & PARPORT_IP32_ENABLE_DMA) { if (parport_ip32_dma_register()) - printk(KERN_WARNING PPIP32 - "%s: error: DMA disabled\n", p->name); + pr_warn(PPIP32 "%s: error: DMA disabled\n", p->name); else { pr_probe(p, "DMA support enabled\n"); p->dma = 0; /* arbitrary value != PARPORT_DMA_NONE */ @@ -2134,13 +2131,15 @@ static __init struct parport *parport_ip32_probe_port(void) parport_ip32_dump_state(p, "end init", 0); /* Print out what we found */ - printk(KERN_INFO "%s: SGI IP32 at 0x%lx (0x%lx)", - p->name, p->base, p->base_hi); + pr_info("%s: SGI IP32 at 0x%lx (0x%lx)", p->name, p->base, p->base_hi); if (p->irq != PARPORT_IRQ_NONE) - printk(", irq %d", p->irq); - printk(" ["); -#define printmode(x) if (p->modes & PARPORT_MODE_##x) \ - printk("%s%s", f++ ? "," : "", #x) + pr_cont(", irq %d", p->irq); + pr_cont(" ["); +#define printmode(x) \ +do { \ + if (p->modes & PARPORT_MODE_##x) \ + pr_cont("%s%s", f++ ? "," : "", #x); \ +} while (0) { unsigned int f = 0; printmode(PCSPP); @@ -2151,7 +2150,7 @@ static __init struct parport *parport_ip32_probe_port(void) printmode(DMA); } #undef printmode - printk("]\n"); + pr_cont("]\n"); parport_announce_port(p); return p; diff --git a/drivers/parport/parport_mfc3.c b/drivers/parport/parport_mfc3.c index 9f87faf939e3..d6bbe8446301 100644 --- a/drivers/parport/parport_mfc3.c +++ b/drivers/parport/parport_mfc3.c @@ -70,11 +70,6 @@ #define MAX_MFC 5 #undef DEBUG -#ifdef DEBUG -#define DPRINTK printk -#else -static inline int DPRINTK(void *nothing, ...) {return 0;} -#endif static struct parport *this_port[MAX_MFC] = {NULL, }; static volatile int dummy; /* for trigger readds */ @@ -84,7 +79,7 @@ static struct parport_operations pp_mfc3_ops; static void mfc3_write_data(struct parport *p, unsigned char data) { -DPRINTK(KERN_DEBUG "write_data %c\n",data); + pr_debug("write_data %c\n", data); dummy = pia(p)->pprb; /* clears irq bit */ /* Triggers also /STROBE.*/ @@ -128,13 +123,13 @@ static unsigned char control_mfc3_to_pc(unsigned char control) static void mfc3_write_control(struct parport *p, unsigned char control) { -DPRINTK(KERN_DEBUG "write_control %02x\n",control); + pr_debug("write_control %02x\n", control); pia(p)->ppra = (pia(p)->ppra & 0x1f) | control_pc_to_mfc3(control); } static unsigned char mfc3_read_control( struct parport *p) { -DPRINTK(KERN_DEBUG "read_control \n"); + pr_debug("read_control\n"); return control_mfc3_to_pc(pia(p)->ppra & 0xe0); } @@ -142,7 +137,7 @@ static unsigned char mfc3_frob_control( struct parport *p, unsigned char mask, u { unsigned char old; -DPRINTK(KERN_DEBUG "frob_control mask %02x, value %02x\n",mask,val); + pr_debug("frob_control mask %02x, value %02x\n", mask, val); old = mfc3_read_control(p); mfc3_write_control(p, (old & ~mask) ^ val); return old; @@ -171,7 +166,7 @@ static unsigned char mfc3_read_status(struct parport *p) unsigned char status; status = status_mfc3_to_pc(pia(p)->ppra & 0x1f); -DPRINTK(KERN_DEBUG "read_status %02x\n", status); + pr_debug("read_status %02x\n", status); return status; } @@ -202,7 +197,7 @@ static void mfc3_disable_irq(struct parport *p) static void mfc3_data_forward(struct parport *p) { - DPRINTK(KERN_DEBUG "forward\n"); + pr_debug("forward\n"); pia(p)->crb &= ~PIA_DDR; /* make data direction register visible */ pia(p)->pddrb = 255; /* all pins output */ pia(p)->crb |= PIA_DDR; /* make data register visible - default */ @@ -210,7 +205,7 @@ static void mfc3_data_forward(struct parport *p) static void mfc3_data_reverse(struct parport *p) { - DPRINTK(KERN_DEBUG "reverse\n"); + pr_debug("reverse\n"); pia(p)->crb &= ~PIA_DDR; /* make data direction register visible */ pia(p)->pddrb = 0; /* all pins input */ pia(p)->crb |= PIA_DDR; /* make data register visible - default */ @@ -325,7 +320,7 @@ static int __init parport_mfc3_init(void) p->dev = &z->dev; this_port[pias++] = p; - printk(KERN_INFO "%s: Multiface III port using irq\n", p->name); + pr_info("%s: Multiface III port using irq\n", p->name); /* XXX: set operating mode */ p->private_data = (void *)piabase; diff --git a/drivers/parport/parport_pc.c b/drivers/parport/parport_pc.c index 1f17a39eabe8..77e37e3cb3a0 100644 --- a/drivers/parport/parport_pc.c +++ b/drivers/parport/parport_pc.c @@ -87,13 +87,6 @@ #undef DEBUG -#ifdef DEBUG -#define DPRINTK printk -#else -#define DPRINTK(stuff...) -#endif - - #define NR_SUPERIOS 3 static struct superio_struct { /* For Super-IO chips autodetection */ int io; @@ -118,8 +111,8 @@ static void frob_econtrol(struct parport *pb, unsigned char m, if (m != 0xff) ectr = inb(ECONTROL(pb)); - DPRINTK(KERN_DEBUG "frob_econtrol(%02x,%02x): %02x -> %02x\n", - m, v, ectr, (ectr & ~m) ^ v); + pr_debug("frob_econtrol(%02x,%02x): %02x -> %02x\n", + m, v, ectr, (ectr & ~m) ^ v); outb((ectr & ~m) ^ v, ECONTROL(pb)); } @@ -142,7 +135,7 @@ static int change_mode(struct parport *p, int m) unsigned char oecr; int mode; - DPRINTK(KERN_INFO "parport change_mode ECP-ISA to mode 0x%02x\n", m); + pr_debug("parport change_mode ECP-ISA to mode 0x%02x\n", m); if (!priv->ecr) { printk(KERN_DEBUG "change_mode: but there's no ECR!\n"); @@ -298,8 +291,8 @@ static size_t parport_pc_epp_read_data(struct parport *port, void *buf, status = inb(STATUS(port)); if (status & 0x01) { /* EPP timeout should never occur... */ - printk(KERN_DEBUG -"%s: EPP timeout occurred while talking to w91284pic (should not have done)\n", port->name); + printk(KERN_DEBUG "%s: EPP timeout occurred while talking to w91284pic (should not have done)\n", + port->name); clear_epp_timeout(port); } } @@ -727,7 +720,7 @@ static size_t parport_pc_compat_write_block_pio(struct parport *port, r = change_mode(port, ECR_PPF); /* Parallel port FIFO */ if (r) printk(KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n", - port->name); + port->name); port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; @@ -770,9 +763,8 @@ static size_t parport_pc_compat_write_block_pio(struct parport *port, PARPORT_STATUS_BUSY, PARPORT_STATUS_BUSY); if (r) - printk(KERN_DEBUG - "%s: BUSY timeout (%d) in compat_write_block_pio\n", - port->name, r); + printk(KERN_DEBUG "%s: BUSY timeout (%d) in compat_write_block_pio\n", + port->name, r); port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; @@ -810,8 +802,8 @@ static size_t parport_pc_ecp_write_block_pio(struct parport *port, PARPORT_STATUS_PAPEROUT, PARPORT_STATUS_PAPEROUT); if (r) { - printk(KERN_DEBUG "%s: PError timeout (%d) " - "in ecp_write_block_pio\n", port->name, r); + printk(KERN_DEBUG "%s: PError timeout (%d) in ecp_write_block_pio\n", + port->name, r); } } @@ -824,7 +816,7 @@ static size_t parport_pc_ecp_write_block_pio(struct parport *port, r = change_mode(port, ECR_ECP); /* ECP FIFO */ if (r) printk(KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", - port->name); + port->name); port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; /* Write the data to the FIFO. */ @@ -867,8 +859,8 @@ static size_t parport_pc_ecp_write_block_pio(struct parport *port, parport_frob_control(port, PARPORT_CONTROL_INIT, 0); r = parport_wait_peripheral(port, PARPORT_STATUS_PAPEROUT, 0); if (r) - printk(KERN_DEBUG "%s: PE,1 timeout (%d) " - "in ecp_write_block_pio\n", port->name, r); + printk(KERN_DEBUG "%s: PE,1 timeout (%d) in ecp_write_block_pio\n", + port->name, r); parport_frob_control(port, PARPORT_CONTROL_INIT, @@ -877,17 +869,16 @@ static size_t parport_pc_ecp_write_block_pio(struct parport *port, PARPORT_STATUS_PAPEROUT, PARPORT_STATUS_PAPEROUT); if (r) - printk(KERN_DEBUG "%s: PE,2 timeout (%d) " - "in ecp_write_block_pio\n", port->name, r); + printk(KERN_DEBUG "%s: PE,2 timeout (%d) in ecp_write_block_pio\n", + port->name, r); } r = parport_wait_peripheral(port, PARPORT_STATUS_BUSY, PARPORT_STATUS_BUSY); if (r) - printk(KERN_DEBUG - "%s: BUSY timeout (%d) in ecp_write_block_pio\n", - port->name, r); + printk(KERN_DEBUG "%s: BUSY timeout (%d) in ecp_write_block_pio\n", + port->name, r); port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; @@ -982,28 +973,24 @@ static void show_parconfig_smsc37c669(int io, int key) outb(0xaa, io); if (verbose_probing) { - printk(KERN_INFO - "SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, " - "A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n", + pr_info("SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n", cr1, cr4, cra, cr23, cr26, cr27); /* The documentation calls DMA and IRQ-Lines by letters, so the board maker can/will wire them appropriately/randomly... G=reserved H=IDE-irq, */ - printk(KERN_INFO - "SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, fifo threshold=%d\n", - cr23 * 4, - (cr27 & 0x0f) ? 'A' - 1 + (cr27 & 0x0f) : '-', - (cr26 & 0x0f) ? 'A' - 1 + (cr26 & 0x0f) : '-', - cra & 0x0f); - printk(KERN_INFO "SMSC LPT Config: enabled=%s power=%s\n", - (cr23 * 4 >= 0x100) ? "yes" : "no", - (cr1 & 4) ? "yes" : "no"); - printk(KERN_INFO - "SMSC LPT Config: Port mode=%s, EPP version =%s\n", - (cr1 & 0x08) ? "Standard mode only (SPP)" - : modes[cr4 & 0x03], - (cr4 & 0x40) ? "1.7" : "1.9"); + pr_info("SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, fifo threshold=%d\n", + cr23 * 4, + (cr27 & 0x0f) ? 'A' - 1 + (cr27 & 0x0f) : '-', + (cr26 & 0x0f) ? 'A' - 1 + (cr26 & 0x0f) : '-', + cra & 0x0f); + pr_info("SMSC LPT Config: enabled=%s power=%s\n", + (cr23 * 4 >= 0x100) ? "yes" : "no", + (cr1 & 4) ? "yes" : "no"); + pr_info("SMSC LPT Config: Port mode=%s, EPP version =%s\n", + (cr1 & 0x08) ? "Standard mode only (SPP)" + : modes[cr4 & 0x03], + (cr4 & 0x40) ? "1.7" : "1.9"); } /* Heuristics ! BIOS setup for this mainboard device limits @@ -1013,7 +1000,7 @@ static void show_parconfig_smsc37c669(int io, int key) if (cr23 * 4 >= 0x100) { /* if active */ s = find_free_superio(); if (s == NULL) - printk(KERN_INFO "Super-IO: too many chips!\n"); + pr_info("Super-IO: too many chips!\n"); else { int d; switch (cr23 * 4) { @@ -1078,26 +1065,24 @@ static void show_parconfig_winbond(int io, int key) outb(0xaa, io); if (verbose_probing) { - printk(KERN_INFO - "Winbond LPT Config: cr_30=%02x 60,61=%02x%02x 70=%02x 74=%02x, f0=%02x\n", - cr30, cr60, cr61, cr70, cr74, crf0); - printk(KERN_INFO "Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ", - (cr30 & 0x01) ? "yes" : "no", cr60, cr61, cr70 & 0x0f); + pr_info("Winbond LPT Config: cr_30=%02x 60,61=%02x%02x 70=%02x 74=%02x, f0=%02x\n", + cr30, cr60, cr61, cr70, cr74, crf0); + pr_info("Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ", + (cr30 & 0x01) ? "yes" : "no", cr60, cr61, cr70 & 0x0f); if ((cr74 & 0x07) > 3) pr_cont("dma=none\n"); else pr_cont("dma=%d\n", cr74 & 0x07); - printk(KERN_INFO - "Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n", - irqtypes[crf0>>7], (crf0>>3)&0x0f); - printk(KERN_INFO "Winbond LPT Config: Port mode=%s\n", - modes[crf0 & 0x07]); + pr_info("Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n", + irqtypes[crf0 >> 7], (crf0 >> 3) & 0x0f); + pr_info("Winbond LPT Config: Port mode=%s\n", + modes[crf0 & 0x07]); } if (cr30 & 0x01) { /* the settings can be interrogated later ... */ s = find_free_superio(); if (s == NULL) - printk(KERN_INFO "Super-IO: too many chips!\n"); + pr_info("Super-IO: too many chips!\n"); else { s->io = (cr60 << 8) | cr61; s->irq = cr70 & 0x0f; @@ -1151,9 +1136,8 @@ static void decode_winbond(int efer, int key, int devid, int devrev, int oldid) progif = 0; if (verbose_probing) - printk(KERN_INFO "Winbond chip at EFER=0x%x key=0x%02x " - "devid=%02x devrev=%02x oldid=%02x type=%s\n", - efer, key, devid, devrev, oldid, type); + pr_info("Winbond chip at EFER=0x%x key=0x%02x devid=%02x devrev=%02x oldid=%02x type=%s\n", + efer, key, devid, devrev, oldid, type); if (progif == 2) show_parconfig_winbond(efer, key); @@ -1184,9 +1168,8 @@ static void decode_smsc(int efer, int key, int devid, int devrev) type = "37c666GT"; if (verbose_probing) - printk(KERN_INFO "SMSC chip at EFER=0x%x " - "key=0x%02x devid=%02x devrev=%02x type=%s\n", - efer, key, devid, devrev, type); + pr_info("SMSC chip at EFER=0x%x key=0x%02x devid=%02x devrev=%02x type=%s\n", + efer, key, devid, devrev, type); if (func) func(efer, key); @@ -1358,7 +1341,7 @@ static void detect_and_report_it87(void) dev |= inb(0x2f); if (dev == 0x8712 || dev == 0x8705 || dev == 0x8715 || dev == 0x8716 || dev == 0x8718 || dev == 0x8726) { - printk(KERN_INFO "IT%04X SuperIO detected.\n", dev); + pr_info("IT%04X SuperIO detected\n", dev); outb(0x07, 0x2E); /* Parallel Port */ outb(0x03, 0x2F); outb(0xF0, 0x2E); /* BOOT 0x80 off */ @@ -1445,8 +1428,8 @@ static int parport_SPP_supported(struct parport *pb) if (user_specified) /* That didn't work, but the user thinks there's a * port here. */ - printk(KERN_INFO "parport 0x%lx (WARNING): CTR: " - "wrote 0x%02x, read 0x%02x\n", pb->base, w, r); + pr_info("parport 0x%lx (WARNING): CTR: wrote 0x%02x, read 0x%02x\n", + pb->base, w, r); /* Try the data register. The data lines aren't tri-stated at * this stage, so we expect back what we wrote. */ @@ -1464,10 +1447,9 @@ static int parport_SPP_supported(struct parport *pb) if (user_specified) { /* Didn't work, but the user is convinced this is the * place. */ - printk(KERN_INFO "parport 0x%lx (WARNING): DATA: " - "wrote 0x%02x, read 0x%02x\n", pb->base, w, r); - printk(KERN_INFO "parport 0x%lx: You gave this address, " - "but there is probably no parallel port there!\n", + pr_info("parport 0x%lx (WARNING): DATA: wrote 0x%02x, read 0x%02x\n", + pb->base, w, r); + pr_info("parport 0x%lx: You gave this address, but there is probably no parallel port there!\n", pb->base); } @@ -1620,7 +1602,7 @@ static int parport_ECP_supported(struct parport *pb) if (i <= priv->fifo_depth) { if (verbose_probing) printk(KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n", - pb->base, i); + pb->base, i); } else /* Number of bytes we know we can write if we get an interrupt. */ @@ -1642,7 +1624,7 @@ static int parport_ECP_supported(struct parport *pb) if (i <= priv->fifo_depth) { if (verbose_probing) - printk(KERN_INFO "0x%lx: readIntrThreshold is %d\n", + pr_info("0x%lx: readIntrThreshold is %d\n", pb->base, i); } else /* Number of bytes we can read if we get an interrupt. */ @@ -1657,17 +1639,14 @@ static int parport_ECP_supported(struct parport *pb) switch (pword) { case 0: pword = 2; - printk(KERN_WARNING "0x%lx: Unsupported pword size!\n", - pb->base); + pr_warn("0x%lx: Unsupported pword size!\n", pb->base); break; case 2: pword = 4; - printk(KERN_WARNING "0x%lx: Unsupported pword size!\n", - pb->base); + pr_warn("0x%lx: Unsupported pword size!\n", pb->base); break; default: - printk(KERN_WARNING "0x%lx: Unknown implementation ID\n", - pb->base); + pr_warn("0x%lx: Unknown implementation ID\n", pb->base); /* Fall through - Assume 1 */ case 1: pword = 1; @@ -1676,14 +1655,14 @@ static int parport_ECP_supported(struct parport *pb) if (verbose_probing) { printk(KERN_DEBUG "0x%lx: PWord is %d bits\n", - pb->base, 8 * pword); + pb->base, 8 * pword); - printk(KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", pb->base, - config & 0x80 ? "Level" : "Pulses"); + printk(KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", + pb->base, config & 0x80 ? "Level" : "Pulses"); configb = inb(CONFIGB(pb)); printk(KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n", - pb->base, config, configb); + pb->base, config, configb); printk(KERN_DEBUG "0x%lx: ECP settings irq=", pb->base); if ((configb >> 3) & 0x07) pr_cont("%d", intrline[(configb >> 3) & 0x07]); @@ -2107,9 +2086,9 @@ struct parport *parport_pc_probe_port(unsigned long int base, p->size = (p->modes & PARPORT_MODE_EPP) ? 8 : 3; - printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base); + pr_info("%s: PC-style at 0x%lx", p->name, p->base); if (p->base_hi && priv->ecr) - printk(KERN_CONT " (0x%lx)", p->base_hi); + pr_cont(" (0x%lx)", p->base_hi); if (p->irq == PARPORT_IRQ_AUTO) { p->irq = PARPORT_IRQ_NONE; parport_irq_probe(p); @@ -2120,7 +2099,7 @@ struct parport *parport_pc_probe_port(unsigned long int base, p->irq = PARPORT_IRQ_NONE; } if (p->irq != PARPORT_IRQ_NONE) { - printk(KERN_CONT ", irq %d", p->irq); + pr_cont(", irq %d", p->irq); priv->ctr_writable |= 0x10; if (p->dma == PARPORT_DMA_AUTO) { @@ -2144,41 +2123,39 @@ struct parport *parport_pc_probe_port(unsigned long int base, /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */ #endif /* IEEE 1284 support */ if (p->dma != PARPORT_DMA_NONE) { - printk(KERN_CONT ", dma %d", p->dma); + pr_cont(", dma %d", p->dma); p->modes |= PARPORT_MODE_DMA; } else - printk(KERN_CONT ", using FIFO"); + pr_cont(", using FIFO"); } else /* We can't use the DMA channel after all. */ p->dma = PARPORT_DMA_NONE; #endif /* Allowed to use FIFO/DMA */ - printk(KERN_CONT " ["); + pr_cont(" ["); -#define printmode(x) \ - {\ - if (p->modes & PARPORT_MODE_##x) {\ - printk(KERN_CONT "%s%s", f ? "," : "", #x);\ - f++;\ - } \ - } +#define printmode(x) \ +do { \ + if (p->modes & PARPORT_MODE_##x) \ + pr_cont("%s%s", f++ ? "," : "", #x); \ +} while (0) { int f = 0; printmode(PCSPP); printmode(TRISTATE); - printmode(COMPAT) + printmode(COMPAT); printmode(EPP); printmode(ECP); printmode(DMA); } #undef printmode #ifndef CONFIG_PARPORT_1284 - printk(KERN_CONT "(,...)"); + pr_cont("(,...)"); #endif /* CONFIG_PARPORT_1284 */ - printk(KERN_CONT "]\n"); + pr_cont("]\n"); if (probedirq != PARPORT_IRQ_NONE) - printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq); + pr_info("%s: irq %d detected\n", p->name, probedirq); /* If No ECP release the ports grabbed above. */ if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) { @@ -2193,8 +2170,7 @@ struct parport *parport_pc_probe_port(unsigned long int base, if (p->irq != PARPORT_IRQ_NONE) { if (request_irq(p->irq, parport_irq_handler, irqflags, p->name, p)) { - printk(KERN_WARNING "%s: irq %d in use, " - "resorting to polled operation\n", + pr_warn("%s: irq %d in use, resorting to polled operation\n", p->name, p->irq); p->irq = PARPORT_IRQ_NONE; p->dma = PARPORT_DMA_NONE; @@ -2204,8 +2180,7 @@ struct parport *parport_pc_probe_port(unsigned long int base, #ifdef HAS_DMA if (p->dma != PARPORT_DMA_NONE) { if (request_dma(p->dma, p->name)) { - printk(KERN_WARNING "%s: dma %d in use, " - "resorting to PIO operation\n", + pr_warn("%s: dma %d in use, resorting to PIO operation\n", p->name, p->dma); p->dma = PARPORT_DMA_NONE; } else { @@ -2215,9 +2190,7 @@ struct parport *parport_pc_probe_port(unsigned long int base, &priv->dma_handle, GFP_KERNEL); if (!priv->dma_buf) { - printk(KERN_WARNING "%s: " - "cannot get buffer for DMA, " - "resorting to PIO operation\n", + pr_warn("%s: cannot get buffer for DMA, resorting to PIO operation\n", p->name); free_dma(p->dma); p->dma = PARPORT_DMA_NONE; @@ -2313,7 +2286,7 @@ static int sio_ite_8872_probe(struct pci_dev *pdev, int autoirq, int autodma, int irq; int i; - DPRINTK(KERN_DEBUG "sio_ite_8872_probe()\n"); + pr_debug("sio_ite_8872_probe()\n"); /* make sure which one chip */ for (i = 0; i < 5; i++) { @@ -2330,7 +2303,7 @@ static int sio_ite_8872_probe(struct pci_dev *pdev, int autoirq, int autodma, } } if (i >= 5) { - printk(KERN_INFO "parport_pc: cannot find ITE8872 INTA\n"); + pr_info("parport_pc: cannot find ITE8872 INTA\n"); return 0; } @@ -2339,29 +2312,28 @@ static int sio_ite_8872_probe(struct pci_dev *pdev, int autoirq, int autodma, switch (type) { case 0x2: - printk(KERN_INFO "parport_pc: ITE8871 found (1P)\n"); + pr_info("parport_pc: ITE8871 found (1P)\n"); ite8872set = 0x64200000; break; case 0xa: - printk(KERN_INFO "parport_pc: ITE8875 found (1P)\n"); + pr_info("parport_pc: ITE8875 found (1P)\n"); ite8872set = 0x64200000; break; case 0xe: - printk(KERN_INFO "parport_pc: ITE8872 found (2S1P)\n"); + pr_info("parport_pc: ITE8872 found (2S1P)\n"); ite8872set = 0x64e00000; break; case 0x6: - printk(KERN_INFO "parport_pc: ITE8873 found (1S)\n"); + pr_info("parport_pc: ITE8873 found (1S)\n"); release_region(inta_addr[i], 32); return 0; case 0x8: - printk(KERN_INFO "parport_pc: ITE8874 found (2S)\n"); + pr_info("parport_pc: ITE8874 found (2S)\n"); release_region(inta_addr[i], 32); return 0; default: - printk(KERN_INFO "parport_pc: unknown ITE887x\n"); - printk(KERN_INFO "parport_pc: please mail 'lspci -nvv' " - "output to Rich.Liu@ite.com.tw\n"); + pr_info("parport_pc: unknown ITE887x\n"); + pr_info("parport_pc: please mail 'lspci -nvv' output to Rich.Liu@ite.com.tw\n"); release_region(inta_addr[i], 32); return 0; } @@ -2379,11 +2351,9 @@ static int sio_ite_8872_probe(struct pci_dev *pdev, int autoirq, int autodma, pci_write_config_dword(pdev, 0x9c, ite8872set | (ite8872_irq * 0x11111)); - DPRINTK(KERN_DEBUG "ITE887x: The IRQ is %d.\n", ite8872_irq); - DPRINTK(KERN_DEBUG "ITE887x: The PARALLEL I/O port is 0x%x.\n", - ite8872_lpt); - DPRINTK(KERN_DEBUG "ITE887x: The PARALLEL I/O porthi is 0x%x.\n", - ite8872_lpthi); + pr_debug("ITE887x: The IRQ is %d\n", ite8872_irq); + pr_debug("ITE887x: The PARALLEL I/O port is 0x%x\n", ite8872_lpt); + pr_debug("ITE887x: The PARALLEL I/O porthi is 0x%x\n", ite8872_lpthi); /* Let the user (or defaults) steer us away from interrupts */ irq = ite8872_irq; @@ -2396,9 +2366,8 @@ static int sio_ite_8872_probe(struct pci_dev *pdev, int autoirq, int autodma, release_region(inta_addr[i], 32); if (parport_pc_probe_port(ite8872_lpt, ite8872_lpthi, irq, PARPORT_DMA_NONE, &pdev->dev, 0)) { - printk(KERN_INFO - "parport_pc: ITE 8872 parallel port: io=0x%X", - ite8872_lpt); + pr_info("parport_pc: ITE 8872 parallel port: io=0x%X", + ite8872_lpt); if (irq != PARPORT_IRQ_NONE) pr_cont(", irq=%d", irq); pr_cont("\n"); @@ -2471,8 +2440,7 @@ static int sio_via_probe(struct pci_dev *pdev, int autoirq, int autodma, have_epp = 1; break; default: - printk(KERN_DEBUG - "parport_pc: probing current configuration\n"); + printk(KERN_DEBUG "parport_pc: probing current configuration\n"); siofunc = VIA_FUNCTION_PROBE; break; } @@ -2508,12 +2476,11 @@ static int sio_via_probe(struct pci_dev *pdev, int autoirq, int autodma, port1 = inb(VIA_CONFIG_DATA) << 2; printk(KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n", - port1); + port1); if (port1 == 0x3BC && have_epp) { outb(via->viacfg_parport_base, VIA_CONFIG_INDEX); outb((0x378 >> 2), VIA_CONFIG_DATA); - printk(KERN_DEBUG - "parport_pc: Parallel port base changed to 0x378\n"); + printk(KERN_DEBUG "parport_pc: Parallel port base changed to 0x378\n"); port1 = 0x378; } @@ -2525,7 +2492,7 @@ static int sio_via_probe(struct pci_dev *pdev, int autoirq, int autodma, pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp); if (siofunc == VIA_FUNCTION_PARPORT_DISABLE) { - printk(KERN_INFO "parport_pc: VIA parallel port disabled in BIOS\n"); + pr_info("parport_pc: VIA parallel port disabled in BIOS\n"); return 0; } @@ -2558,9 +2525,8 @@ static int sio_via_probe(struct pci_dev *pdev, int autoirq, int autodma, case 0x278: port2 = 0x678; break; default: - printk(KERN_INFO - "parport_pc: Weird VIA parport base 0x%X, ignoring\n", - port1); + pr_info("parport_pc: Weird VIA parport base 0x%X, ignoring\n", + port1); return 0; } @@ -2579,8 +2545,7 @@ static int sio_via_probe(struct pci_dev *pdev, int autoirq, int autodma, /* finally, do the probe with values obtained */ if (parport_pc_probe_port(port1, port2, irq, dma, &pdev->dev, 0)) { - printk(KERN_INFO - "parport_pc: VIA parallel port: io=0x%X", port1); + pr_info("parport_pc: VIA parallel port: io=0x%X", port1); if (irq != PARPORT_IRQ_NONE) pr_cont(", irq=%d", irq); if (dma != PARPORT_DMA_NONE) @@ -2589,7 +2554,7 @@ static int sio_via_probe(struct pci_dev *pdev, int autoirq, int autodma, return 1; } - printk(KERN_WARNING "parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n", + pr_warn("parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n", port1, irq, dma); return 0; } @@ -2854,14 +2819,12 @@ static int parport_pc_pci_probe(struct pci_dev *dev, /* TODO: test if sharing interrupts works */ irq = dev->irq; if (irq == IRQ_NONE) { - printk(KERN_DEBUG - "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx)\n", - id->vendor, id->device, io_lo, io_hi); + printk(KERN_DEBUG "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx)\n", + id->vendor, id->device, io_lo, io_hi); irq = PARPORT_IRQ_NONE; } else { - printk(KERN_DEBUG - "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx), IRQ %d\n", - id->vendor, id->device, io_lo, io_hi, irq); + printk(KERN_DEBUG "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx), IRQ %d\n", + id->vendor, id->device, io_lo, io_hi, irq); } data->ports[count] = parport_pc_probe_port(io_lo, io_hi, irq, @@ -3111,7 +3074,7 @@ static int __init parport_parse_param(const char *s, int *val, if (ep != s) *val = r; else { - printk(KERN_ERR "parport: bad specifier `%s'\n", s); + pr_err("parport: bad specifier `%s'\n", s); return -1; } } @@ -3133,8 +3096,8 @@ static int __init parport_parse_dma(const char *dmastr, int *val) #ifdef CONFIG_PCI static int __init parport_init_mode_setup(char *str) { - printk(KERN_DEBUG - "parport_pc.c: Specified parameter parport_init_mode=%s\n", str); + printk(KERN_DEBUG "parport_pc.c: Specified parameter parport_init_mode=%s\n", + str); if (!strcmp(str, "spp")) parport_init_mode = 1; @@ -3201,10 +3164,7 @@ static int __init parse_parport_params(void) irqval[0] = val; break; default: - printk(KERN_WARNING - "parport_pc: irq specified " - "without base address. Use 'io=' " - "to specify one\n"); + pr_warn("parport_pc: irq specified without base address. Use 'io=' to specify one\n"); } if (dma[0] && !parport_parse_dma(dma[0], &val)) @@ -3214,10 +3174,7 @@ static int __init parse_parport_params(void) dmaval[0] = val; break; default: - printk(KERN_WARNING - "parport_pc: dma specified " - "without base address. Use 'io=' " - "to specify one\n"); + pr_warn("parport_pc: dma specified without base address. Use 'io=' to specify one\n"); } } return 0; @@ -3256,12 +3213,12 @@ static int __init parport_setup(char *str) val = simple_strtoul(str, &endptr, 0); if (endptr == str) { - printk(KERN_WARNING "parport=%s not understood\n", str); + pr_warn("parport=%s not understood\n", str); return 1; } if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) { - printk(KERN_ERR "parport=%s ignored, too many ports\n", str); + pr_err("parport=%s ignored, too many ports\n", str); return 1; } diff --git a/drivers/parport/parport_sunbpp.c b/drivers/parport/parport_sunbpp.c index d5a669b60c27..e840c1b5ab90 100644 --- a/drivers/parport/parport_sunbpp.c +++ b/drivers/parport/parport_sunbpp.c @@ -314,7 +314,7 @@ static int bpp_probe(struct platform_device *op) value_tcr &= ~P_TCR_DIR; sbus_writeb(value_tcr, ®s->p_tcr); - printk(KERN_INFO "%s: sunbpp at 0x%lx\n", p->name, p->base); + pr_info("%s: sunbpp at 0x%lx\n", p->name, p->base); dev_set_drvdata(&op->dev, p); diff --git a/drivers/parport/probe.c b/drivers/parport/probe.c index e5e6a463a941..7e6d713fa5ac 100644 --- a/drivers/parport/probe.c +++ b/drivers/parport/probe.c @@ -38,16 +38,16 @@ static void pretty_print(struct parport *port, int device) { struct parport_device_info *info = &port->probe_info[device + 1]; - printk(KERN_INFO "%s", port->name); + pr_info("%s", port->name); if (device >= 0) - printk (" (addr %d)", device); + pr_cont(" (addr %d)", device); - printk (": %s", classes[info->class].descr); + pr_cont(": %s", classes[info->class].descr); if (info->class) - printk(", %s %s", info->mfr, info->model); + pr_cont(", %s %s", info->mfr, info->model); - printk("\n"); + pr_cont("\n"); } static void parse_data(struct parport *port, int device, char *str) @@ -58,7 +58,7 @@ static void parse_data(struct parport *port, int device, char *str) struct parport_device_info *info = &port->probe_info[device + 1]; if (!txt) { - printk(KERN_WARNING "%s probe: memory squeeze\n", port->name); + pr_warn("%s probe: memory squeeze\n", port->name); return; } strcpy(txt, str); @@ -98,7 +98,8 @@ static void parse_data(struct parport *port, int device, char *str) goto rock_on; } } - printk(KERN_WARNING "%s probe: warning, class '%s' not understood.\n", port->name, sep); + pr_warn("%s probe: warning, class '%s' not understood\n", + port->name, sep); info->class = PARPORT_CLASS_OTHER; } else if (!strcmp(p, "CMD") || !strcmp(p, "COMMAND SET")) { @@ -177,9 +178,8 @@ static ssize_t parport_read_device_id (struct parport *port, char *buffer, * just return constant nibble forever. This catches * also those cases. */ if (idlens[0] == 0 || idlens[0] > 0xFFF) { - printk (KERN_DEBUG "%s: reported broken Device ID" - " length of %#zX bytes\n", - port->name, idlens[0]); + printk(KERN_DEBUG "%s: reported broken Device ID length of %#zX bytes\n", + port->name, idlens[0]); return -EIO; } numidlens = 2; @@ -201,10 +201,8 @@ static ssize_t parport_read_device_id (struct parport *port, char *buffer, if (port->physport->ieee1284.phase != IEEE1284_PH_HBUSY_DAVAIL) { if (belen != len) { - printk (KERN_DEBUG "%s: Device ID was %zd bytes" - " while device told it would be %d" - " bytes\n", - port->name, len, belen); + printk(KERN_DEBUG "%s: Device ID was %zd bytes while device told it would be %d bytes\n", + port->name, len, belen); } goto done; } @@ -214,11 +212,9 @@ static ssize_t parport_read_device_id (struct parport *port, char *buffer, * the first 256 bytes or so that we must have read so * far. */ if (buffer[len-1] == ';') { - printk (KERN_DEBUG "%s: Device ID reading stopped" - " before device told data not available. " - "Current idlen %u of %u, len bytes %02X %02X\n", - port->name, current_idlen, numidlens, - length[0], length[1]); + printk(KERN_DEBUG "%s: Device ID reading stopped before device told data not available. Current idlen %u of %u, len bytes %02X %02X\n", + port->name, current_idlen, numidlens, + length[0], length[1]); goto done; } } diff --git a/drivers/parport/procfs.c b/drivers/parport/procfs.c index ee7b5daabfd4..d740eba3c099 100644 --- a/drivers/parport/procfs.c +++ b/drivers/parport/procfs.c @@ -210,7 +210,11 @@ static int do_hardware_modes(struct ctl_table *table, int write, return -EACCES; { -#define printmode(x) {if(port->modes&PARPORT_MODE_##x){len+=sprintf(buffer+len,"%s%s",f?",":"",#x);f++;}} +#define printmode(x) \ +do { \ + if (port->modes & PARPORT_MODE_##x) \ + len += sprintf(buffer + len, "%s%s", f++ ? "," : "", #x); \ +} while (0) int f = 0; printmode(PCSPP); printmode(TRISTATE); diff --git a/drivers/parport/share.c b/drivers/parport/share.c index d6920ebeabcd..7fec4fefe151 100644 --- a/drivers/parport/share.c +++ b/drivers/parport/share.c @@ -278,46 +278,32 @@ static int port_detect(struct device *dev, void *dev_drv) int __parport_register_driver(struct parport_driver *drv, struct module *owner, const char *mod_name) { - if (drv->devmodel) { - /* using device model */ - int ret; + /* using device model */ + int ret; - /* initialize common driver fields */ - drv->driver.name = drv->name; - drv->driver.bus = &parport_bus_type; - drv->driver.owner = owner; - drv->driver.mod_name = mod_name; - ret = driver_register(&drv->driver); - if (ret) - return ret; + /* initialize common driver fields */ + drv->driver.name = drv->name; + drv->driver.bus = &parport_bus_type; + drv->driver.owner = owner; + drv->driver.mod_name = mod_name; + ret = driver_register(&drv->driver); + if (ret) + return ret; - /* - * check if bus has any parallel port registered, if - * none is found then load the lowlevel driver. - */ - ret = bus_for_each_dev(&parport_bus_type, NULL, NULL, - port_detect); - if (!ret) - get_lowlevel_driver(); + /* + * check if bus has any parallel port registered, if + * none is found then load the lowlevel driver. + */ + ret = bus_for_each_dev(&parport_bus_type, NULL, NULL, + port_detect); + if (!ret) + get_lowlevel_driver(); - mutex_lock(®istration_lock); - if (drv->match_port) - bus_for_each_dev(&parport_bus_type, NULL, drv, - port_check); - mutex_unlock(®istration_lock); - } else { - struct parport *port; - - drv->devmodel = false; - - if (list_empty(&portlist)) - get_lowlevel_driver(); - mutex_lock(®istration_lock); - list_for_each_entry(port, &portlist, list) - drv->attach(port); - list_add(&drv->list, &drivers); - mutex_unlock(®istration_lock); - } + mutex_lock(®istration_lock); + if (drv->match_port) + bus_for_each_dev(&parport_bus_type, NULL, drv, + port_check); + mutex_unlock(®istration_lock); return 0; } @@ -352,17 +338,9 @@ static int port_detach(struct device *dev, void *_drv) void parport_unregister_driver(struct parport_driver *drv) { - struct parport *port; - mutex_lock(®istration_lock); - if (drv->devmodel) { - bus_for_each_dev(&parport_bus_type, NULL, drv, port_detach); - driver_unregister(&drv->driver); - } else { - list_del_init(&drv->list); - list_for_each_entry(port, &portlist, list) - drv->detach(port); - } + bus_for_each_dev(&parport_bus_type, NULL, drv, port_detach); + driver_unregister(&drv->driver); mutex_unlock(®istration_lock); } EXPORT_SYMBOL(parport_unregister_driver); @@ -554,8 +532,8 @@ void parport_announce_port(struct parport *port) #endif if (!port->dev) - printk(KERN_WARNING "%s: fix this legacy no-device port driver!\n", - port->name); + pr_warn("%s: fix this legacy no-device port driver!\n", + port->name); parport_proc_register(port); mutex_lock(®istration_lock); @@ -641,47 +619,48 @@ void parport_remove_port(struct parport *port) } EXPORT_SYMBOL(parport_remove_port); +static void free_pardevice(struct device *dev) +{ + struct pardevice *par_dev = to_pardevice(dev); + + kfree(par_dev->name); + kfree(par_dev); +} + /** - * parport_register_device - register a device on a parallel port + * parport_register_dev_model - register a device on a parallel port * @port: port to which the device is attached * @name: a name to refer to the device - * @pf: preemption callback - * @kf: kick callback (wake-up) - * @irq_func: interrupt handler - * @flags: registration flags - * @handle: data for callback functions + * @par_dev_cb: struct containing callbacks + * @id: device number to be given to the device * * This function, called by parallel port device drivers, * declares that a device is connected to a port, and tells the * system all it needs to know. * - * The @name is allocated by the caller and must not be - * deallocated until the caller calls @parport_unregister_device - * for that device. + * The struct pardev_cb contains pointer to callbacks. preemption + * callback function, @preempt, is called when this device driver + * has claimed access to the port but another device driver wants + * to use it. It is given, @private, as its parameter, and should + * return zero if it is willing for the system to release the port + * to another driver on its behalf. If it wants to keep control of + * the port it should return non-zero, and no action will be taken. + * It is good manners for the driver to try to release the port at + * the earliest opportunity after its preemption callback rejects a + * preemption attempt. Note that if a preemption callback is happy + * for preemption to go ahead, there is no need to release the + * port; it is done automatically. This function may not block, as + * it may be called from interrupt context. If the device driver + * does not support preemption, @preempt can be %NULL. * - * The preemption callback function, @pf, is called when this - * device driver has claimed access to the port but another - * device driver wants to use it. It is given @handle as its - * parameter, and should return zero if it is willing for the - * system to release the port to another driver on its behalf. - * If it wants to keep control of the port it should return - * non-zero, and no action will be taken. It is good manners for - * the driver to try to release the port at the earliest - * opportunity after its preemption callback rejects a preemption - * attempt. Note that if a preemption callback is happy for - * preemption to go ahead, there is no need to release the port; - * it is done automatically. This function may not block, as it - * may be called from interrupt context. If the device driver - * does not support preemption, @pf can be %NULL. - * - * The wake-up ("kick") callback function, @kf, is called when + * The wake-up ("kick") callback function, @wakeup, is called when * the port is available to be claimed for exclusive access; that * is, parport_claim() is guaranteed to succeed when called from * inside the wake-up callback function. If the driver wants to * claim the port it should do so; otherwise, it need not take * any action. This function may not block, as it may be called * from interrupt context. If the device driver does not want to - * be explicitly invited to claim the port in this way, @kf can + * be explicitly invited to claim the port in this way, @wakeup can * be %NULL. * * The interrupt handler, @irq_func, is called when an interrupt @@ -710,138 +689,6 @@ EXPORT_SYMBOL(parport_remove_port); * to allocate space for that structure. **/ -struct pardevice * -parport_register_device(struct parport *port, const char *name, - int (*pf)(void *), void (*kf)(void *), - void (*irq_func)(void *), - int flags, void *handle) -{ - struct pardevice *tmp; - - if (port->physport->flags & PARPORT_FLAG_EXCL) { - /* An exclusive device is registered. */ - printk(KERN_DEBUG "%s: no more devices allowed\n", - port->name); - return NULL; - } - - if (flags & PARPORT_DEV_LURK) { - if (!pf || !kf) { - printk(KERN_INFO "%s: refused to register lurking device (%s) without callbacks\n", port->name, name); - return NULL; - } - } - - if (flags & PARPORT_DEV_EXCL) { - if (port->physport->devices) { - /* - * If a device is already registered and this new - * device wants exclusive access, then no need to - * continue as we can not grant exclusive access to - * this device. - */ - pr_err("%s: cannot grant exclusive access for device %s\n", - port->name, name); - return NULL; - } - } - - /* - * We up our own module reference count, and that of the port - * on which a device is to be registered, to ensure that - * neither of us gets unloaded while we sleep in (e.g.) - * kmalloc. - */ - if (!try_module_get(port->ops->owner)) - return NULL; - - parport_get_port(port); - - tmp = kmalloc(sizeof(struct pardevice), GFP_KERNEL); - if (!tmp) - goto out; - - tmp->state = kmalloc(sizeof(struct parport_state), GFP_KERNEL); - if (!tmp->state) - goto out_free_pardevice; - - tmp->name = name; - tmp->port = port; - tmp->daisy = -1; - tmp->preempt = pf; - tmp->wakeup = kf; - tmp->private = handle; - tmp->flags = flags; - tmp->irq_func = irq_func; - tmp->waiting = 0; - tmp->timeout = 5 * HZ; - tmp->devmodel = false; - - /* Chain this onto the list */ - tmp->prev = NULL; - /* - * This function must not run from an irq handler so we don' t need - * to clear irq on the local CPU. -arca - */ - spin_lock(&port->physport->pardevice_lock); - - if (flags & PARPORT_DEV_EXCL) { - if (port->physport->devices) { - spin_unlock(&port->physport->pardevice_lock); - printk(KERN_DEBUG - "%s: cannot grant exclusive access for device %s\n", - port->name, name); - goto out_free_all; - } - port->flags |= PARPORT_FLAG_EXCL; - } - - tmp->next = port->physport->devices; - wmb(); /* - * Make sure that tmp->next is written before it's - * added to the list; see comments marked 'no locking - * required' - */ - if (port->physport->devices) - port->physport->devices->prev = tmp; - port->physport->devices = tmp; - spin_unlock(&port->physport->pardevice_lock); - - init_waitqueue_head(&tmp->wait_q); - tmp->timeslice = parport_default_timeslice; - tmp->waitnext = tmp->waitprev = NULL; - - /* - * This has to be run as last thing since init_state may need other - * pardevice fields. -arca - */ - port->ops->init_state(tmp, tmp->state); - if (!test_and_set_bit(PARPORT_DEVPROC_REGISTERED, &port->devflags)) { - port->proc_device = tmp; - parport_device_proc_register(tmp); - } - return tmp; - - out_free_all: - kfree(tmp->state); - out_free_pardevice: - kfree(tmp); - out: - parport_put_port(port); - module_put(port->ops->owner); - - return NULL; -} -EXPORT_SYMBOL(parport_register_device); - -static void free_pardevice(struct device *dev) -{ - struct pardevice *par_dev = to_pardevice(dev); - - kfree(par_dev->name); - kfree(par_dev); -} - struct pardevice * parport_register_dev_model(struct parport *port, const char *name, const struct pardev_cb *par_dev_cb, int id) @@ -996,7 +843,7 @@ void parport_unregister_device(struct pardevice *dev) #ifdef PARPORT_PARANOID if (!dev) { - printk(KERN_ERR "parport_unregister_device: passed NULL\n"); + pr_err("%s: passed NULL\n", __func__); return; } #endif @@ -1046,10 +893,7 @@ void parport_unregister_device(struct pardevice *dev) spin_unlock_irq(&port->waitlist_lock); kfree(dev->state); - if (dev->devmodel) - device_unregister(&dev->dev); - else - kfree(dev); + device_unregister(&dev->dev); module_put(port->ops->owner); parport_put_port(port); @@ -1137,8 +981,7 @@ int parport_claim(struct pardevice *dev) unsigned long flags; if (port->cad == dev) { - printk(KERN_INFO "%s: %s already owner\n", - dev->port->name,dev->name); + pr_info("%s: %s already owner\n", dev->port->name, dev->name); return 0; } @@ -1158,9 +1001,8 @@ int parport_claim(struct pardevice *dev) * I think we'll actually deadlock rather than * get here, but just in case.. */ - printk(KERN_WARNING - "%s: %s released port when preempted!\n", - port->name, oldcad->name); + pr_warn("%s: %s released port when preempted!\n", + port->name, oldcad->name); if (port->cad) goto blocked; } @@ -1260,7 +1102,8 @@ int parport_claim_or_block(struct pardevice *dev) r = parport_claim(dev); if (r == -EAGAIN) { #ifdef PARPORT_DEBUG_SHARING - printk(KERN_DEBUG "%s: parport_claim() returned -EAGAIN\n", dev->name); + printk(KERN_DEBUG "%s: parport_claim() returned -EAGAIN\n", + dev->name); #endif /* * FIXME!!! Use the proper locking for dev->waiting, @@ -1293,7 +1136,7 @@ int parport_claim_or_block(struct pardevice *dev) if (dev->port->physport->cad != dev) printk(KERN_DEBUG "%s: exiting parport_claim_or_block but %s owns port!\n", dev->name, dev->port->physport->cad ? - dev->port->physport->cad->name:"nobody"); + dev->port->physport->cad->name : "nobody"); #endif } dev->waiting = 0; @@ -1320,8 +1163,8 @@ void parport_release(struct pardevice *dev) write_lock_irqsave(&port->cad_lock, flags); if (port->cad != dev) { write_unlock_irqrestore(&port->cad_lock, flags); - printk(KERN_WARNING "%s: %s tried to release parport when not owner\n", - port->name, dev->name); + pr_warn("%s: %s tried to release parport when not owner\n", + port->name, dev->name); return; } @@ -1361,7 +1204,8 @@ void parport_release(struct pardevice *dev) if (dev->port->cad) /* racy but no matter */ return; } else { - printk(KERN_ERR "%s: don't know how to wake %s\n", port->name, pd->name); + pr_err("%s: don't know how to wake %s\n", + port->name, pd->name); } } diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 834c59950d1c..8828613c4e0e 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -82,7 +82,7 @@ config PINCTRL_AT91 config PINCTRL_AT91PIO4 bool "AT91 PIO4 pinctrl driver" depends on OF - depends on ARCH_AT91 + depends on ARCH_AT91 || COMPILE_TEST select PINMUX select GENERIC_PINCONF select GPIOLIB @@ -95,6 +95,7 @@ config PINCTRL_AT91PIO4 config PINCTRL_AMD tristate "AMD GPIO pin control" depends on HAS_IOMEM + depends on ACPI || COMPILE_TEST select GPIOLIB select GPIOLIB_IRQCHIP select PINMUX @@ -172,15 +173,22 @@ config PINCTRL_GEMINI select GENERIC_PINCONF select MFD_SYSCON +config PINCTRL_MCP23S08_I2C + tristate + select REGMAP_I2C + +config PINCTRL_MCP23S08_SPI + tristate + select REGMAP_SPI + config PINCTRL_MCP23S08 tristate "Microchip MCP23xxx I/O expander" depends on SPI_MASTER || I2C - depends on I2C || I2C=n select GPIOLIB select GPIOLIB_IRQCHIP - select REGMAP_I2C if I2C - select REGMAP_SPI if SPI_MASTER select GENERIC_PINCONF + select PINCTRL_MCP23S08_I2C if I2C + select PINCTRL_MCP23S08_SPI if SPI_MASTER help SPI/I2C driver for Microchip MCP23S08 / MCP23S17 / MCP23S18 / MCP23008 / MCP23017 / MCP23018 I/O expanders. @@ -435,6 +443,7 @@ config PINCTRL_TB10X config PINCTRL_EQUILIBRIUM tristate "Generic pinctrl and GPIO driver for Intel Lightning Mountain SoC" depends on OF && HAS_IOMEM + depends on X86 || COMPILE_TEST select PINMUX select PINCONF select GPIOLIB diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 0b36a1cfca8a..1731b2154df9 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -21,6 +21,8 @@ obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o obj-$(CONFIG_PINCTRL_GEMINI) += pinctrl-gemini.o obj-$(CONFIG_PINCTRL_MAX77620) += pinctrl-max77620.o +obj-$(CONFIG_PINCTRL_MCP23S08_I2C) += pinctrl-mcp23s08_i2c.o +obj-$(CONFIG_PINCTRL_MCP23S08_SPI) += pinctrl-mcp23s08_spi.o obj-$(CONFIG_PINCTRL_MCP23S08) += pinctrl-mcp23s08.o obj-$(CONFIG_PINCTRL_MESON) += meson/ obj-$(CONFIG_PINCTRL_OXNAS) += pinctrl-oxnas.o diff --git a/drivers/pinctrl/bcm/pinctrl-bcm281xx.c b/drivers/pinctrl/bcm/pinctrl-bcm281xx.c index f690fc5cd688..71e666178300 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm281xx.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm281xx.c @@ -1406,7 +1406,7 @@ static int __init bcm281xx_pinctrl_probe(struct platform_device *pdev) pdata->reg_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pdata->reg_base)) { dev_err(&pdev->dev, "Failed to ioremap MEM resource\n"); - return -ENODEV; + return PTR_ERR(pdata->reg_base); } /* Initialize the dynamic part of pinctrl_desc */ diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c index 06bd2b70af3c..1d21129f7751 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -76,6 +77,7 @@ struct bcm2835_pinctrl { struct device *dev; void __iomem *base; + int *wake_irq; /* note: locking assumes each bank will have its own unsigned long */ unsigned long enabled_irq_map[BCM2835_NUM_BANKS]; @@ -435,6 +437,11 @@ static void bcm2835_gpio_irq_handler(struct irq_desc *desc) chained_irq_exit(host_chip, desc); } +static irqreturn_t bcm2835_gpio_wake_irq_handler(int irq, void *dev_id) +{ + return IRQ_HANDLED; +} + static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc, unsigned reg, unsigned offset, bool enable) { @@ -634,6 +641,34 @@ static void bcm2835_gpio_irq_ack(struct irq_data *data) bcm2835_gpio_set_bit(pc, GPEDS0, gpio); } +static int bcm2835_gpio_irq_set_wake(struct irq_data *data, unsigned int on) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); + unsigned gpio = irqd_to_hwirq(data); + unsigned int irqgroup; + int ret = -EINVAL; + + if (!pc->wake_irq) + return ret; + + if (gpio <= 27) + irqgroup = 0; + else if (gpio >= 28 && gpio <= 45) + irqgroup = 1; + else if (gpio >= 46 && gpio <= 57) + irqgroup = 2; + else + return ret; + + if (on) + ret = enable_irq_wake(pc->wake_irq[irqgroup]); + else + ret = disable_irq_wake(pc->wake_irq[irqgroup]); + + return ret; +} + static struct irq_chip bcm2835_gpio_irq_chip = { .name = MODULE_NAME, .irq_enable = bcm2835_gpio_irq_enable, @@ -642,6 +677,8 @@ static struct irq_chip bcm2835_gpio_irq_chip = { .irq_ack = bcm2835_gpio_irq_ack, .irq_mask = bcm2835_gpio_irq_disable, .irq_unmask = bcm2835_gpio_irq_enable, + .irq_set_wake = bcm2835_gpio_irq_set_wake, + .flags = IRQCHIP_MASK_ON_SUSPEND, }; static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev) @@ -1137,6 +1174,10 @@ static const struct of_device_id bcm2835_pinctrl_match[] = { .compatible = "brcm,bcm2711-gpio", .data = &bcm2711_plat_data, }, + { + .compatible = "brcm,bcm7211-gpio", + .data = &bcm2711_plat_data, + }, {} }; @@ -1150,6 +1191,7 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) struct resource iomem; int err, i; const struct of_device_id *match; + int is_7211 = 0; BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2711_NUM_GPIOS); BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2711_NUM_GPIOS); @@ -1176,6 +1218,7 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) return -EINVAL; pdata = match->data; + is_7211 = of_device_is_compatible(np, "brcm,bcm7211-gpio"); pc->gpio_chip = *pdata->gpio_chip; pc->gpio_chip.parent = dev; @@ -1210,6 +1253,15 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) GFP_KERNEL); if (!girq->parents) return -ENOMEM; + + if (is_7211) { + pc->wake_irq = devm_kcalloc(dev, BCM2835_NUM_IRQS, + sizeof(*pc->wake_irq), + GFP_KERNEL); + if (!pc->wake_irq) + return -ENOMEM; + } + /* * Use the same handler for all groups: this is necessary * since we use one gpiochip to cover all lines - the @@ -1217,8 +1269,34 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) * bank that was firing the IRQ and look up the per-group * and bank data. */ - for (i = 0; i < BCM2835_NUM_IRQS; i++) + for (i = 0; i < BCM2835_NUM_IRQS; i++) { + int len; + char *name; + girq->parents[i] = irq_of_parse_and_map(np, i); + if (!is_7211) + continue; + + /* Skip over the all banks interrupts */ + pc->wake_irq[i] = irq_of_parse_and_map(np, i + + BCM2835_NUM_IRQS + 1); + + len = strlen(dev_name(pc->dev)) + 16; + name = devm_kzalloc(pc->dev, len, GFP_KERNEL); + if (!name) + return -ENOMEM; + + snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i); + + /* These are optional interrupts */ + err = devm_request_irq(dev, pc->wake_irq[i], + bcm2835_gpio_wake_irq_handler, + IRQF_SHARED, name, pc); + if (err) + dev_warn(dev, "unable to request wake IRQ %d\n", + pc->wake_irq[i]); + } + girq->default_type = IRQ_TYPE_NONE; girq->handler = handle_level_irq; diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig index c784663b00ad..4ca44dd69e53 100644 --- a/drivers/pinctrl/freescale/Kconfig +++ b/drivers/pinctrl/freescale/Kconfig @@ -165,6 +165,13 @@ config PINCTRL_IMX8QXP help Say Y here to enable the imx8qxp pinctrl driver +config PINCTRL_IMX8DXL + bool "IMX8DXL pinctrl driver" + depends on IMX_SCU && ARCH_MXC && ARM64 + select PINCTRL_IMX_SCU + help + Say Y here to enable the imx8dxl pinctrl driver + config PINCTRL_VF610 bool "Freescale Vybrid VF610 pinctrl driver" depends on SOC_VF610 diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile index 0ebd3af21e4d..c61722565289 100644 --- a/drivers/pinctrl/freescale/Makefile +++ b/drivers/pinctrl/freescale/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_PINCTRL_IMX8MP) += pinctrl-imx8mp.o obj-$(CONFIG_PINCTRL_IMX8MQ) += pinctrl-imx8mq.o obj-$(CONFIG_PINCTRL_IMX8QM) += pinctrl-imx8qm.o obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o +obj-$(CONFIG_PINCTRL_IMX8DXL) += pinctrl-imx8dxl.o obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index 9f42036c5fbb..cb7e0f08d2cf 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -774,16 +774,6 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev, return 0; } -/* - * imx_free_resources() - free memory used by this driver - * @info: info driver instance - */ -static void imx_free_resources(struct imx_pinctrl *ipctl) -{ - if (ipctl->pctl) - pinctrl_unregister(ipctl->pctl); -} - int imx_pinctrl_probe(struct platform_device *pdev, const struct imx_pinctrl_soc_info *info) { @@ -834,12 +824,13 @@ int imx_pinctrl_probe(struct platform_device *pdev, return -EINVAL; } - ipctl->input_sel_base = of_iomap(np, 0); + ipctl->input_sel_base = devm_of_iomap(&pdev->dev, np, + 0, NULL); of_node_put(np); - if (!ipctl->input_sel_base) { + if (IS_ERR(ipctl->input_sel_base)) { dev_err(&pdev->dev, "iomuxc input select base address not found\n"); - return -ENOMEM; + return PTR_ERR(ipctl->input_sel_base); } } } @@ -874,23 +865,18 @@ int imx_pinctrl_probe(struct platform_device *pdev, &ipctl->pctl); if (ret) { dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); - goto free; + return ret; } ret = imx_pinctrl_probe_dt(pdev, ipctl); if (ret) { dev_err(&pdev->dev, "fail to probe dt properties\n"); - goto free; + return ret; } dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); return pinctrl_enable(ipctl->pctl); - -free: - imx_free_resources(ipctl); - - return ret; } static int __maybe_unused imx_pinctrl_suspend(struct device *dev) diff --git a/drivers/pinctrl/freescale/pinctrl-imx1-core.c b/drivers/pinctrl/freescale/pinctrl-imx1-core.c index c00d0022d311..08d110078c43 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx1-core.c +++ b/drivers/pinctrl/freescale/pinctrl-imx1-core.c @@ -60,7 +60,7 @@ struct imx1_pinctrl { /* * IMX1 IOMUXC manages the pins based on ports. Each port has 32 pins. IOMUX - * control register are seperated into function, output configuration, input + * control registers are separated into function, output configuration, input * configuration A, input configuration B, GPIO in use and data direction. * * Those controls that are represented by 1 bit have a direct mapping between @@ -638,7 +638,6 @@ int imx1_pinctrl_core_probe(struct platform_device *pdev, ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); if (ret) { - pinctrl_unregister(ipctl->pctl); dev_err(&pdev->dev, "Failed to populate subdevices\n"); return ret; } diff --git a/drivers/pinctrl/freescale/pinctrl-imx8dxl.c b/drivers/pinctrl/freescale/pinctrl-imx8dxl.c new file mode 100644 index 000000000000..7f32e57b7f6a --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx8dxl.c @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019~2020 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-imx.h" + +static const struct pinctrl_pin_desc imx8dxl_pinctrl_pads[] = { + IMX_PINCTRL_PIN(IMX8DXL_PCIE_CTRL0_PERST_B), + IMX_PINCTRL_PIN(IMX8DXL_PCIE_CTRL0_CLKREQ_B), + IMX_PINCTRL_PIN(IMX8DXL_PCIE_CTRL0_WAKE_B), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_PCIESEP), + IMX_PINCTRL_PIN(IMX8DXL_USB_SS3_TC0), + IMX_PINCTRL_PIN(IMX8DXL_USB_SS3_TC1), + IMX_PINCTRL_PIN(IMX8DXL_USB_SS3_TC2), + IMX_PINCTRL_PIN(IMX8DXL_USB_SS3_TC3), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_3V3_USB3IO), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_CLK), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_CMD), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA0), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA1), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA2), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA3), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA4), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA5), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA6), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA7), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_STROBE), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_RESET_B), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_SD1FIX0), + IMX_PINCTRL_PIN(IMX8DXL_USDHC1_RESET_B), + IMX_PINCTRL_PIN(IMX8DXL_USDHC1_VSELECT), + IMX_PINCTRL_PIN(IMX8DXL_CTL_NAND_RE_P_N), + IMX_PINCTRL_PIN(IMX8DXL_USDHC1_WP), + IMX_PINCTRL_PIN(IMX8DXL_USDHC1_CD_B), + IMX_PINCTRL_PIN(IMX8DXL_CTL_NAND_DQS_P_N), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_VSELSEP), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_TXC), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_TX_CTL), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_TXD0), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_TXD1), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_TXD2), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_TXD3), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_RXC), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_RX_CTL), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_RXD0), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_RXD1), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_RXD2), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_RXD3), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_REFCLK_125M_25M), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_MDIO), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_MDC), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_TXC), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_TXD2), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_TX_CTL), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_TXD3), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_RXC), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_RXD3), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_RXD2), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_RXD1), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_TXD0), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_TXD1), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_RXD0), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_RX_CTL), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_REFCLK_125M_25M), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB), + IMX_PINCTRL_PIN(IMX8DXL_SPI3_SCK), + IMX_PINCTRL_PIN(IMX8DXL_SPI3_SDO), + IMX_PINCTRL_PIN(IMX8DXL_SPI3_SDI), + IMX_PINCTRL_PIN(IMX8DXL_SPI3_CS0), + IMX_PINCTRL_PIN(IMX8DXL_SPI3_CS1), + IMX_PINCTRL_PIN(IMX8DXL_MCLK_IN1), + IMX_PINCTRL_PIN(IMX8DXL_MCLK_IN0), + IMX_PINCTRL_PIN(IMX8DXL_MCLK_OUT0), + IMX_PINCTRL_PIN(IMX8DXL_UART1_TX), + IMX_PINCTRL_PIN(IMX8DXL_UART1_RX), + IMX_PINCTRL_PIN(IMX8DXL_UART1_RTS_B), + IMX_PINCTRL_PIN(IMX8DXL_UART1_CTS_B), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK), + IMX_PINCTRL_PIN(IMX8DXL_SPI0_SCK), + IMX_PINCTRL_PIN(IMX8DXL_SPI0_SDI), + IMX_PINCTRL_PIN(IMX8DXL_SPI0_SDO), + IMX_PINCTRL_PIN(IMX8DXL_SPI0_CS1), + IMX_PINCTRL_PIN(IMX8DXL_SPI0_CS0), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHT), + IMX_PINCTRL_PIN(IMX8DXL_ADC_IN1), + IMX_PINCTRL_PIN(IMX8DXL_ADC_IN0), + IMX_PINCTRL_PIN(IMX8DXL_ADC_IN3), + IMX_PINCTRL_PIN(IMX8DXL_ADC_IN2), + IMX_PINCTRL_PIN(IMX8DXL_ADC_IN5), + IMX_PINCTRL_PIN(IMX8DXL_ADC_IN4), + IMX_PINCTRL_PIN(IMX8DXL_FLEXCAN0_RX), + IMX_PINCTRL_PIN(IMX8DXL_FLEXCAN0_TX), + IMX_PINCTRL_PIN(IMX8DXL_FLEXCAN1_RX), + IMX_PINCTRL_PIN(IMX8DXL_FLEXCAN1_TX), + IMX_PINCTRL_PIN(IMX8DXL_FLEXCAN2_RX), + IMX_PINCTRL_PIN(IMX8DXL_FLEXCAN2_TX), + IMX_PINCTRL_PIN(IMX8DXL_UART0_RX), + IMX_PINCTRL_PIN(IMX8DXL_UART0_TX), + IMX_PINCTRL_PIN(IMX8DXL_UART2_TX), + IMX_PINCTRL_PIN(IMX8DXL_UART2_RX), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOLH), + IMX_PINCTRL_PIN(IMX8DXL_JTAG_TRST_B), + IMX_PINCTRL_PIN(IMX8DXL_PMIC_I2C_SCL), + IMX_PINCTRL_PIN(IMX8DXL_PMIC_I2C_SDA), + IMX_PINCTRL_PIN(IMX8DXL_PMIC_INT_B), + IMX_PINCTRL_PIN(IMX8DXL_SCU_GPIO0_00), + IMX_PINCTRL_PIN(IMX8DXL_SCU_GPIO0_01), + IMX_PINCTRL_PIN(IMX8DXL_SCU_PMIC_STANDBY), + IMX_PINCTRL_PIN(IMX8DXL_SCU_BOOT_MODE1), + IMX_PINCTRL_PIN(IMX8DXL_SCU_BOOT_MODE0), + IMX_PINCTRL_PIN(IMX8DXL_SCU_BOOT_MODE2), + IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_OUT1), + IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_OUT2), + IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_OUT3), + IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_OUT4), + IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_IN0), + IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_IN1), + IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_IN2), + IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_IN3), + IMX_PINCTRL_PIN(IMX8DXL_SPI1_SCK), + IMX_PINCTRL_PIN(IMX8DXL_SPI1_SDO), + IMX_PINCTRL_PIN(IMX8DXL_SPI1_SDI), + IMX_PINCTRL_PIN(IMX8DXL_SPI1_CS0), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHD), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_DATA1), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_DATA0), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_DATA3), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_DATA2), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_SS0_B), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_DQS), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_SCLK), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0A), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_SCLK), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_DQS), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_DATA1), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_DATA0), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_DATA3), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_DATA2), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_SS0_B), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0B) +}; + + +static struct imx_pinctrl_soc_info imx8dxl_pinctrl_info = { + .pins = imx8dxl_pinctrl_pads, + .npins = ARRAY_SIZE(imx8dxl_pinctrl_pads), + .flags = IMX_USE_SCU, +}; + +static const struct of_device_id imx8dxl_pinctrl_of_match[] = { + { .compatible = "fsl,imx8dxl-iomuxc", }, + { /* sentinel */ } +}; + +static int imx8dxl_pinctrl_probe(struct platform_device *pdev) +{ + int ret; + + ret = imx_pinctrl_sc_ipc_init(pdev); + if (ret) + return ret; + + return imx_pinctrl_probe(pdev, &imx8dxl_pinctrl_info); +} + +static struct platform_driver imx8dxl_pinctrl_driver = { + .driver = { + .name = "fsl,imx8dxl-iomuxc", + .of_match_table = of_match_ptr(imx8dxl_pinctrl_of_match), + .suppress_bind_attrs = true, + }, + .probe = imx8dxl_pinctrl_probe, +}; + +static int __init imx8dxl_pinctrl_init(void) +{ + return platform_driver_register(&imx8dxl_pinctrl_driver); +} +arch_initcall(imx8dxl_pinctrl_init); diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig index ee440ec4c94c..787833e343a4 100644 --- a/drivers/pinctrl/intel/Kconfig +++ b/drivers/pinctrl/intel/Kconfig @@ -111,6 +111,14 @@ config PINCTRL_ICELAKE This pinctrl driver provides an interface that allows configuring of Intel Ice Lake PCH pins and using them as GPIOs. +config PINCTRL_JASPERLAKE + tristate "Intel Jasper Lake PCH pinctrl and GPIO driver" + depends on ACPI + select PINCTRL_INTEL + help + This pinctrl driver provides an interface that allows configuring + of Intel Jasper Lake PCH pins and using them as GPIOs. + config PINCTRL_LEWISBURG tristate "Intel Lewisburg pinctrl and GPIO driver" depends on ACPI diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile index f60f99cfa7aa..f6f63eb8100f 100644 --- a/drivers/pinctrl/intel/Makefile +++ b/drivers/pinctrl/intel/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_CEDARFORK) += pinctrl-cedarfork.o obj-$(CONFIG_PINCTRL_DENVERTON) += pinctrl-denverton.o obj-$(CONFIG_PINCTRL_GEMINILAKE) += pinctrl-geminilake.o obj-$(CONFIG_PINCTRL_ICELAKE) += pinctrl-icelake.o +obj-$(CONFIG_PINCTRL_JASPERLAKE) += pinctrl-jasperlake.o obj-$(CONFIG_PINCTRL_LEWISBURG) += pinctrl-lewisburg.o obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o obj-$(CONFIG_PINCTRL_TIGERLAKE) += pinctrl-tigerlake.o diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index 9b821c9cbd16..0ff7c55173da 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -1506,8 +1506,7 @@ static int byt_gpio_probe(struct intel_pinctrl *vg) { struct platform_device *pdev = to_platform_device(vg->dev); struct gpio_chip *gc; - struct resource *irq_rc; - int ret; + int irq, ret; /* Set up gpio chip */ vg->chip = byt_gpio_chip; @@ -1527,8 +1526,8 @@ static int byt_gpio_probe(struct intel_pinctrl *vg) #endif /* set up interrupts */ - irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (irq_rc && irq_rc->start) { + irq = platform_get_irq_optional(pdev, 0); + if (irq > 0) { struct gpio_irq_chip *girq; vg->irqchip.name = "BYT-GPIO", @@ -1548,7 +1547,7 @@ static int byt_gpio_probe(struct intel_pinctrl *vg) sizeof(*girq->parents), GFP_KERNEL); if (!girq->parents) return -ENOMEM; - girq->parents[0] = (unsigned int)irq_rc->start; + girq->parents[0] = irq; girq->default_type = IRQ_TYPE_NONE; girq->handler = handle_bad_irq; } diff --git a/drivers/pinctrl/intel/pinctrl-cannonlake.c b/drivers/pinctrl/intel/pinctrl-cannonlake.c index f51b27bbf9f1..515f57a0d180 100644 --- a/drivers/pinctrl/intel/pinctrl-cannonlake.c +++ b/drivers/pinctrl/intel/pinctrl-cannonlake.c @@ -30,8 +30,6 @@ .gpio_base = (g), \ } -#define CNL_NO_GPIO -1 - #define CNL_COMMUNITY(b, s, e, o, g) \ { \ .barno = (b), \ @@ -377,27 +375,27 @@ static const struct intel_padgroup cnlh_community0_gpps[] = { }; static const struct intel_padgroup cnlh_community1_gpps[] = { - CNL_GPP(0, 51, 74, 64), /* GPP_C */ - CNL_GPP(1, 75, 98, 96), /* GPP_D */ - CNL_GPP(2, 99, 106, 128), /* GPP_G */ - CNL_GPP(3, 107, 114, CNL_NO_GPIO), /* AZA */ - CNL_GPP(4, 115, 146, 160), /* vGPIO_0 */ - CNL_GPP(5, 147, 154, CNL_NO_GPIO), /* vGPIO_1 */ + CNL_GPP(0, 51, 74, 64), /* GPP_C */ + CNL_GPP(1, 75, 98, 96), /* GPP_D */ + CNL_GPP(2, 99, 106, 128), /* GPP_G */ + CNL_GPP(3, 107, 114, INTEL_GPIO_BASE_NOMAP), /* AZA */ + CNL_GPP(4, 115, 146, 160), /* vGPIO_0 */ + CNL_GPP(5, 147, 154, INTEL_GPIO_BASE_NOMAP), /* vGPIO_1 */ }; static const struct intel_padgroup cnlh_community3_gpps[] = { - CNL_GPP(0, 155, 178, 192), /* GPP_K */ - CNL_GPP(1, 179, 202, 224), /* GPP_H */ - CNL_GPP(2, 203, 215, 256), /* GPP_E */ - CNL_GPP(3, 216, 239, 288), /* GPP_F */ - CNL_GPP(4, 240, 248, CNL_NO_GPIO), /* SPI */ + CNL_GPP(0, 155, 178, 192), /* GPP_K */ + CNL_GPP(1, 179, 202, 224), /* GPP_H */ + CNL_GPP(2, 203, 215, 256), /* GPP_E */ + CNL_GPP(3, 216, 239, 288), /* GPP_F */ + CNL_GPP(4, 240, 248, INTEL_GPIO_BASE_NOMAP), /* SPI */ }; static const struct intel_padgroup cnlh_community4_gpps[] = { - CNL_GPP(0, 249, 259, CNL_NO_GPIO), /* CPU */ - CNL_GPP(1, 260, 268, CNL_NO_GPIO), /* JTAG */ - CNL_GPP(2, 269, 286, 320), /* GPP_I */ - CNL_GPP(3, 287, 298, 352), /* GPP_J */ + CNL_GPP(0, 249, 259, INTEL_GPIO_BASE_NOMAP), /* CPU */ + CNL_GPP(1, 260, 268, INTEL_GPIO_BASE_NOMAP), /* JTAG */ + CNL_GPP(2, 269, 286, 320), /* GPP_I */ + CNL_GPP(3, 287, 298, 352), /* GPP_J */ }; static const unsigned int cnlh_spi0_pins[] = { 40, 41, 42, 43 }; @@ -790,25 +788,25 @@ static const struct intel_function cnllp_functions[] = { }; static const struct intel_padgroup cnllp_community0_gpps[] = { - CNL_GPP(0, 0, 24, 0), /* GPP_A */ - CNL_GPP(1, 25, 50, 32), /* GPP_B */ - CNL_GPP(2, 51, 58, 64), /* GPP_G */ - CNL_GPP(3, 59, 67, CNL_NO_GPIO), /* SPI */ + CNL_GPP(0, 0, 24, 0), /* GPP_A */ + CNL_GPP(1, 25, 50, 32), /* GPP_B */ + CNL_GPP(2, 51, 58, 64), /* GPP_G */ + CNL_GPP(3, 59, 67, INTEL_GPIO_BASE_NOMAP), /* SPI */ }; static const struct intel_padgroup cnllp_community1_gpps[] = { - CNL_GPP(0, 68, 92, 96), /* GPP_D */ - CNL_GPP(1, 93, 116, 128), /* GPP_F */ - CNL_GPP(2, 117, 140, 160), /* GPP_H */ - CNL_GPP(3, 141, 172, 192), /* vGPIO */ - CNL_GPP(4, 173, 180, 224), /* vGPIO */ + CNL_GPP(0, 68, 92, 96), /* GPP_D */ + CNL_GPP(1, 93, 116, 128), /* GPP_F */ + CNL_GPP(2, 117, 140, 160), /* GPP_H */ + CNL_GPP(3, 141, 172, 192), /* vGPIO */ + CNL_GPP(4, 173, 180, 224), /* vGPIO */ }; static const struct intel_padgroup cnllp_community4_gpps[] = { - CNL_GPP(0, 181, 204, 256), /* GPP_C */ - CNL_GPP(1, 205, 228, 288), /* GPP_E */ - CNL_GPP(2, 229, 237, CNL_NO_GPIO), /* JTAG */ - CNL_GPP(3, 238, 243, CNL_NO_GPIO), /* HVCMOS */ + CNL_GPP(0, 181, 204, 256), /* GPP_C */ + CNL_GPP(1, 205, 228, 288), /* GPP_E */ + CNL_GPP(2, 229, 237, INTEL_GPIO_BASE_NOMAP), /* JTAG */ + CNL_GPP(3, 238, 243, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ }; static const struct intel_community cnllp_communities[] = { diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 1093a6105d40..8e3953a223d0 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -35,18 +35,18 @@ #define CHV_PADCTRL0 0x000 #define CHV_PADCTRL0_INTSEL_SHIFT 28 -#define CHV_PADCTRL0_INTSEL_MASK (0xf << CHV_PADCTRL0_INTSEL_SHIFT) +#define CHV_PADCTRL0_INTSEL_MASK GENMASK(31, 28) #define CHV_PADCTRL0_TERM_UP BIT(23) #define CHV_PADCTRL0_TERM_SHIFT 20 -#define CHV_PADCTRL0_TERM_MASK (7 << CHV_PADCTRL0_TERM_SHIFT) +#define CHV_PADCTRL0_TERM_MASK GENMASK(22, 20) #define CHV_PADCTRL0_TERM_20K 1 #define CHV_PADCTRL0_TERM_5K 2 #define CHV_PADCTRL0_TERM_1K 4 #define CHV_PADCTRL0_PMODE_SHIFT 16 -#define CHV_PADCTRL0_PMODE_MASK (0xf << CHV_PADCTRL0_PMODE_SHIFT) +#define CHV_PADCTRL0_PMODE_MASK GENMASK(19, 16) #define CHV_PADCTRL0_GPIOEN BIT(15) #define CHV_PADCTRL0_GPIOCFG_SHIFT 8 -#define CHV_PADCTRL0_GPIOCFG_MASK (7 << CHV_PADCTRL0_GPIOCFG_SHIFT) +#define CHV_PADCTRL0_GPIOCFG_MASK GENMASK(10, 8) #define CHV_PADCTRL0_GPIOCFG_GPIO 0 #define CHV_PADCTRL0_GPIOCFG_GPO 1 #define CHV_PADCTRL0_GPIOCFG_GPI 2 @@ -57,57 +57,16 @@ #define CHV_PADCTRL1 0x004 #define CHV_PADCTRL1_CFGLOCK BIT(31) #define CHV_PADCTRL1_INVRXTX_SHIFT 4 -#define CHV_PADCTRL1_INVRXTX_MASK (0xf << CHV_PADCTRL1_INVRXTX_SHIFT) -#define CHV_PADCTRL1_INVRXTX_TXENABLE (2 << CHV_PADCTRL1_INVRXTX_SHIFT) +#define CHV_PADCTRL1_INVRXTX_MASK GENMASK(7, 4) +#define CHV_PADCTRL1_INVRXTX_RXDATA BIT(6) +#define CHV_PADCTRL1_INVRXTX_TXENABLE BIT(5) #define CHV_PADCTRL1_ODEN BIT(3) -#define CHV_PADCTRL1_INVRXTX_RXDATA (4 << CHV_PADCTRL1_INVRXTX_SHIFT) -#define CHV_PADCTRL1_INTWAKECFG_MASK 7 +#define CHV_PADCTRL1_INTWAKECFG_MASK GENMASK(2, 0) #define CHV_PADCTRL1_INTWAKECFG_FALLING 1 #define CHV_PADCTRL1_INTWAKECFG_RISING 2 #define CHV_PADCTRL1_INTWAKECFG_BOTH 3 #define CHV_PADCTRL1_INTWAKECFG_LEVEL 4 -/** - * struct chv_alternate_function - A per group or per pin alternate function - * @pin: Pin number (only used in per pin configs) - * @mode: Mode the pin should be set in - * @invert_oe: Invert OE for this pin - */ -struct chv_alternate_function { - unsigned int pin; - u8 mode; - bool invert_oe; -}; - -/** - * struct chv_pincgroup - describes a CHV pin group - * @name: Name of the group - * @pins: An array of pins in this group - * @npins: Number of pins in this group - * @altfunc: Alternate function applied to all pins in this group - * @overrides: Alternate function override per pin or %NULL if not used - * @noverrides: Number of per pin alternate function overrides if - * @overrides != NULL. - */ -struct chv_pingroup { - const char *name; - const unsigned int *pins; - size_t npins; - struct chv_alternate_function altfunc; - const struct chv_alternate_function *overrides; - size_t noverrides; -}; - -/** - * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs - * @base: Start pin number - * @npins: Number of pins in this range - */ -struct chv_gpio_pinrange { - unsigned int base; - unsigned int npins; -}; - /** * struct chv_community - A community specific configuration * @uid: ACPI _UID used to match the community @@ -117,8 +76,8 @@ struct chv_gpio_pinrange { * @ngroups: Number of groups * @functions: All functions in this community * @nfunctions: Number of functions - * @gpio_ranges: An array of GPIO ranges in this community - * @ngpio_ranges: Number of GPIO ranges + * @gpps: Pad groups + * @ngpps: Number of pad groups in this community * @nirqs: Total number of IRQs this community can generate * @acpi_space_id: An address space ID for ACPI OpRegion handler */ @@ -126,12 +85,12 @@ struct chv_community { const char *uid; const struct pinctrl_pin_desc *pins; size_t npins; - const struct chv_pingroup *groups; + const struct intel_pingroup *groups; size_t ngroups; const struct intel_function *functions; size_t nfunctions; - const struct chv_gpio_pinrange *gpio_ranges; - size_t ngpio_ranges; + const struct intel_padgroup *gpps; + size_t ngpps; size_t nirqs; acpi_adr_space_type acpi_space_id; }; @@ -173,37 +132,14 @@ struct chv_pinctrl { struct chv_pin_context *saved_pin_context; }; -#define ALTERNATE_FUNCTION(p, m, i) \ - { \ - .pin = (p), \ - .mode = (m), \ - .invert_oe = (i), \ - } +#define PINMODE_INVERT_OE BIT(15) -#define PIN_GROUP_WITH_ALT(n, p, m, i) \ - { \ - .name = (n), \ - .pins = (p), \ - .npins = ARRAY_SIZE((p)), \ - .altfunc.mode = (m), \ - .altfunc.invert_oe = (i), \ - } +#define PINMODE(m, i) ((m) | ((i) * PINMODE_INVERT_OE)) -#define PIN_GROUP_WITH_OVERRIDE(n, p, m, i, o) \ - { \ - .name = (n), \ - .pins = (p), \ - .npins = ARRAY_SIZE((p)), \ - .altfunc.mode = (m), \ - .altfunc.invert_oe = (i), \ - .overrides = (o), \ - .noverrides = ARRAY_SIZE((o)), \ - } - -#define GPIO_PINRANGE(start, end) \ +#define CHV_GPP(start, end) \ { \ .base = (start), \ - .npins = (end) - (start) + 1, \ + .size = (end) - (start) + 1, \ } static const struct pinctrl_pin_desc southwest_pins[] = { @@ -288,40 +224,37 @@ static const unsigned southwest_i2c6_pins[] = { 47, 51 }; static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 }; static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 }; -/* LPE I2S TXD pins need to have invert_oe set */ -static const struct chv_alternate_function southwest_lpe_altfuncs[] = { - ALTERNATE_FUNCTION(30, 1, true), - ALTERNATE_FUNCTION(34, 1, true), - ALTERNATE_FUNCTION(97, 1, true), +/* Some of LPE I2S TXD pins need to have OE inversion set */ +static const unsigned int southwest_lpe_altfuncs[] = { + PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 30, 31, 32, 33 */ + PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 34, 35, 36, 37 */ + PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 1), /* 92, 94, 96, 97 */ }; /* * Two spi3 chipselects are available in different mode than the main spi3 - * functionality, which is using mode 1. + * functionality, which is using mode 2. */ -static const struct chv_alternate_function southwest_spi3_altfuncs[] = { - ALTERNATE_FUNCTION(76, 3, false), - ALTERNATE_FUNCTION(80, 3, false), +static const unsigned int southwest_spi3_altfuncs[] = { + PINMODE(3, 0), PINMODE(2, 0), PINMODE(3, 0), PINMODE(2, 0), /* 76, 79, 80, 81 */ + PINMODE(2, 0), /* 82 */ }; -static const struct chv_pingroup southwest_groups[] = { - PIN_GROUP_WITH_ALT("uart0_grp", southwest_uart0_pins, 2, false), - PIN_GROUP_WITH_ALT("uart1_grp", southwest_uart1_pins, 1, false), - PIN_GROUP_WITH_ALT("uart2_grp", southwest_uart2_pins, 1, false), - PIN_GROUP_WITH_ALT("hda_grp", southwest_hda_pins, 2, false), - PIN_GROUP_WITH_ALT("i2c0_grp", southwest_i2c0_pins, 1, true), - PIN_GROUP_WITH_ALT("i2c1_grp", southwest_i2c1_pins, 1, true), - PIN_GROUP_WITH_ALT("i2c2_grp", southwest_i2c2_pins, 1, true), - PIN_GROUP_WITH_ALT("i2c3_grp", southwest_i2c3_pins, 1, true), - PIN_GROUP_WITH_ALT("i2c4_grp", southwest_i2c4_pins, 1, true), - PIN_GROUP_WITH_ALT("i2c5_grp", southwest_i2c5_pins, 1, true), - PIN_GROUP_WITH_ALT("i2c6_grp", southwest_i2c6_pins, 1, true), - PIN_GROUP_WITH_ALT("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true), - - PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins, 1, false, - southwest_lpe_altfuncs), - PIN_GROUP_WITH_OVERRIDE("spi3_grp", southwest_spi3_pins, 2, false, - southwest_spi3_altfuncs), +static const struct intel_pingroup southwest_groups[] = { + PIN_GROUP("uart0_grp", southwest_uart0_pins, PINMODE(2, 0)), + PIN_GROUP("uart1_grp", southwest_uart1_pins, PINMODE(1, 0)), + PIN_GROUP("uart2_grp", southwest_uart2_pins, PINMODE(1, 0)), + PIN_GROUP("hda_grp", southwest_hda_pins, PINMODE(2, 0)), + PIN_GROUP("i2c0_grp", southwest_i2c0_pins, PINMODE(1, 1)), + PIN_GROUP("i2c1_grp", southwest_i2c1_pins, PINMODE(1, 1)), + PIN_GROUP("i2c2_grp", southwest_i2c2_pins, PINMODE(1, 1)), + PIN_GROUP("i2c3_grp", southwest_i2c3_pins, PINMODE(1, 1)), + PIN_GROUP("i2c4_grp", southwest_i2c4_pins, PINMODE(1, 1)), + PIN_GROUP("i2c5_grp", southwest_i2c5_pins, PINMODE(1, 1)), + PIN_GROUP("i2c6_grp", southwest_i2c6_pins, PINMODE(1, 1)), + PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, PINMODE(2, 1)), + PIN_GROUP("lpe_grp", southwest_lpe_pins, southwest_lpe_altfuncs), + PIN_GROUP("spi3_grp", southwest_spi3_pins, southwest_spi3_altfuncs), }; static const char * const southwest_uart0_groups[] = { "uart0_grp" }; @@ -360,14 +293,14 @@ static const struct intel_function southwest_functions[] = { FUNCTION("spi3", southwest_spi3_groups), }; -static const struct chv_gpio_pinrange southwest_gpio_ranges[] = { - GPIO_PINRANGE(0, 7), - GPIO_PINRANGE(15, 22), - GPIO_PINRANGE(30, 37), - GPIO_PINRANGE(45, 52), - GPIO_PINRANGE(60, 67), - GPIO_PINRANGE(75, 82), - GPIO_PINRANGE(90, 97), +static const struct intel_padgroup southwest_gpps[] = { + CHV_GPP(0, 7), + CHV_GPP(15, 22), + CHV_GPP(30, 37), + CHV_GPP(45, 52), + CHV_GPP(60, 67), + CHV_GPP(75, 82), + CHV_GPP(90, 97), }; static const struct chv_community southwest_community = { @@ -378,8 +311,8 @@ static const struct chv_community southwest_community = { .ngroups = ARRAY_SIZE(southwest_groups), .functions = southwest_functions, .nfunctions = ARRAY_SIZE(southwest_functions), - .gpio_ranges = southwest_gpio_ranges, - .ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges), + .gpps = southwest_gpps, + .ngpps = ARRAY_SIZE(southwest_gpps), /* * Southwest community can generate GPIO interrupts only for the * first 8 interrupts. The upper half (8-15) can only be used to @@ -455,20 +388,20 @@ static const struct pinctrl_pin_desc north_pins[] = { PINCTRL_PIN(72, "PANEL0_VDDEN"), }; -static const struct chv_gpio_pinrange north_gpio_ranges[] = { - GPIO_PINRANGE(0, 8), - GPIO_PINRANGE(15, 27), - GPIO_PINRANGE(30, 41), - GPIO_PINRANGE(45, 56), - GPIO_PINRANGE(60, 72), +static const struct intel_padgroup north_gpps[] = { + CHV_GPP(0, 8), + CHV_GPP(15, 27), + CHV_GPP(30, 41), + CHV_GPP(45, 56), + CHV_GPP(60, 72), }; static const struct chv_community north_community = { .uid = "2", .pins = north_pins, .npins = ARRAY_SIZE(north_pins), - .gpio_ranges = north_gpio_ranges, - .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges), + .gpps = north_gpps, + .ngpps = ARRAY_SIZE(north_gpps), /* * North community can generate GPIO interrupts only for the first * 8 interrupts. The upper half (8-15) can only be used to trigger @@ -506,17 +439,17 @@ static const struct pinctrl_pin_desc east_pins[] = { PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"), }; -static const struct chv_gpio_pinrange east_gpio_ranges[] = { - GPIO_PINRANGE(0, 11), - GPIO_PINRANGE(15, 26), +static const struct intel_padgroup east_gpps[] = { + CHV_GPP(0, 11), + CHV_GPP(15, 26), }; static const struct chv_community east_community = { .uid = "3", .pins = east_pins, .npins = ARRAY_SIZE(east_pins), - .gpio_ranges = east_gpio_ranges, - .ngpio_ranges = ARRAY_SIZE(east_gpio_ranges), + .gpps = east_gpps, + .ngpps = ARRAY_SIZE(east_gpps), .nirqs = 16, .acpi_space_id = 0x93, }; @@ -596,14 +529,14 @@ static const unsigned southeast_sdmmc3_pins[] = { static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 }; static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 }; -static const struct chv_pingroup southeast_groups[] = { - PIN_GROUP_WITH_ALT("pwm0_grp", southeast_pwm0_pins, 1, false), - PIN_GROUP_WITH_ALT("pwm1_grp", southeast_pwm1_pins, 1, false), - PIN_GROUP_WITH_ALT("sdmmc1_grp", southeast_sdmmc1_pins, 1, false), - PIN_GROUP_WITH_ALT("sdmmc2_grp", southeast_sdmmc2_pins, 1, false), - PIN_GROUP_WITH_ALT("sdmmc3_grp", southeast_sdmmc3_pins, 1, false), - PIN_GROUP_WITH_ALT("spi1_grp", southeast_spi1_pins, 1, false), - PIN_GROUP_WITH_ALT("spi2_grp", southeast_spi2_pins, 4, false), +static const struct intel_pingroup southeast_groups[] = { + PIN_GROUP("pwm0_grp", southeast_pwm0_pins, PINMODE(1, 0)), + PIN_GROUP("pwm1_grp", southeast_pwm1_pins, PINMODE(1, 0)), + PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, PINMODE(1, 0)), + PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, PINMODE(1, 0)), + PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, PINMODE(1, 0)), + PIN_GROUP("spi1_grp", southeast_spi1_pins, PINMODE(1, 0)), + PIN_GROUP("spi2_grp", southeast_spi2_pins, PINMODE(4, 0)), }; static const char * const southeast_pwm0_groups[] = { "pwm0_grp" }; @@ -624,13 +557,13 @@ static const struct intel_function southeast_functions[] = { FUNCTION("spi2", southeast_spi2_groups), }; -static const struct chv_gpio_pinrange southeast_gpio_ranges[] = { - GPIO_PINRANGE(0, 7), - GPIO_PINRANGE(15, 26), - GPIO_PINRANGE(30, 35), - GPIO_PINRANGE(45, 52), - GPIO_PINRANGE(60, 69), - GPIO_PINRANGE(75, 85), +static const struct intel_padgroup southeast_gpps[] = { + CHV_GPP(0, 7), + CHV_GPP(15, 26), + CHV_GPP(30, 35), + CHV_GPP(45, 52), + CHV_GPP(60, 69), + CHV_GPP(75, 85), }; static const struct chv_community southeast_community = { @@ -641,8 +574,8 @@ static const struct chv_community southeast_community = { .ngroups = ARRAY_SIZE(southeast_groups), .functions = southeast_functions, .nfunctions = ARRAY_SIZE(southeast_functions), - .gpio_ranges = southeast_gpio_ranges, - .ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges), + .gpps = southeast_gpps, + .ngpps = ARRAY_SIZE(southeast_gpps), .nirqs = 16, .acpi_space_id = 0x94, }; @@ -789,7 +722,7 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, unsigned int group) { struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - const struct chv_pingroup *grp; + const struct intel_pingroup *grp; unsigned long flags; int i; @@ -808,22 +741,21 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, } for (i = 0; i < grp->npins; i++) { - const struct chv_alternate_function *altfunc = &grp->altfunc; int pin = grp->pins[i]; void __iomem *reg; + unsigned int mode; + bool invert_oe; u32 value; /* Check if there is pin-specific config */ - if (grp->overrides) { - int j; + if (grp->modes) + mode = grp->modes[i]; + else + mode = grp->mode; - for (j = 0; j < grp->noverrides; j++) { - if (grp->overrides[j].pin == pin) { - altfunc = &grp->overrides[j]; - break; - } - } - } + /* Extract OE inversion */ + invert_oe = mode & PINMODE_INVERT_OE; + mode &= ~PINMODE_INVERT_OE; reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); value = readl(reg); @@ -831,18 +763,18 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, value &= ~CHV_PADCTRL0_GPIOEN; /* Set to desired mode */ value &= ~CHV_PADCTRL0_PMODE_MASK; - value |= altfunc->mode << CHV_PADCTRL0_PMODE_SHIFT; + value |= mode << CHV_PADCTRL0_PMODE_SHIFT; chv_writel(value, reg); /* Update for invert_oe */ reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK; - if (altfunc->invert_oe) + if (invert_oe) value |= CHV_PADCTRL1_INVRXTX_TXENABLE; chv_writel(value, reg); dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n", - pin, altfunc->mode, altfunc->invert_oe ? "" : "not "); + pin, mode, invert_oe ? "" : "not "); } raw_spin_unlock_irqrestore(&chv_lock, flags); @@ -1594,14 +1526,14 @@ static int chv_gpio_add_pin_ranges(struct gpio_chip *chip) { struct chv_pinctrl *pctrl = gpiochip_get_data(chip); const struct chv_community *community = pctrl->community; - const struct chv_gpio_pinrange *range; + const struct intel_padgroup *gpp; int ret, i; - for (i = 0; i < community->ngpio_ranges; i++) { - range = &community->gpio_ranges[i]; + for (i = 0; i < community->ngpps; i++) { + gpp = &community->gpps[i]; ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev), - range->base, range->base, - range->npins); + gpp->base, gpp->base, + gpp->size); if (ret) { dev_err(pctrl->dev, "failed to add GPIO pin range\n"); return ret; @@ -1613,7 +1545,7 @@ static int chv_gpio_add_pin_ranges(struct gpio_chip *chip) static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) { - const struct chv_gpio_pinrange *range; + const struct intel_padgroup *gpp; struct gpio_chip *chip = &pctrl->chip; bool need_valid_mask = !dmi_check_system(chv_no_valid_mask); const struct chv_community *community = pctrl->community; @@ -1661,12 +1593,12 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) } if (!need_valid_mask) { - for (i = 0; i < community->ngpio_ranges; i++) { - range = &community->gpio_ranges[i]; + for (i = 0; i < community->ngpps; i++) { + gpp = &community->gpps[i]; irq_domain_associate_many(chip->irq.domain, irq_base, - range->base, range->npins); - irq_base += range->npins; + gpp->base, gpp->size); + irq_base += gpp->size; } } diff --git a/drivers/pinctrl/intel/pinctrl-icelake.c b/drivers/pinctrl/intel/pinctrl-icelake.c index 6489e9bbb61f..429b5a83acf0 100644 --- a/drivers/pinctrl/intel/pinctrl-icelake.c +++ b/drivers/pinctrl/intel/pinctrl-icelake.c @@ -29,8 +29,6 @@ .gpio_base = (g), \ } -#define ICL_NO_GPIO -1 - #define ICL_COMMUNITY(b, s, e, g) \ { \ .barno = (b), \ @@ -305,29 +303,29 @@ static const struct pinctrl_pin_desc icllp_pins[] = { }; static const struct intel_padgroup icllp_community0_gpps[] = { - ICL_GPP(0, 0, 7, 0), /* GPP_G */ - ICL_GPP(1, 8, 33, 32), /* GPP_B */ - ICL_GPP(2, 34, 58, 64), /* GPP_A */ + ICL_GPP(0, 0, 7, 0), /* GPP_G */ + ICL_GPP(1, 8, 33, 32), /* GPP_B */ + ICL_GPP(2, 34, 58, 64), /* GPP_A */ }; static const struct intel_padgroup icllp_community1_gpps[] = { - ICL_GPP(0, 59, 82, 96), /* GPP_H */ - ICL_GPP(1, 83, 103, 128), /* GPP_D */ - ICL_GPP(2, 104, 123, 160), /* GPP_F */ - ICL_GPP(3, 124, 152, 192), /* vGPIO */ + ICL_GPP(0, 59, 82, 96), /* GPP_H */ + ICL_GPP(1, 83, 103, 128), /* GPP_D */ + ICL_GPP(2, 104, 123, 160), /* GPP_F */ + ICL_GPP(3, 124, 152, 192), /* vGPIO */ }; static const struct intel_padgroup icllp_community4_gpps[] = { - ICL_GPP(0, 153, 176, 224), /* GPP_C */ - ICL_GPP(1, 177, 182, ICL_NO_GPIO), /* HVCMOS */ - ICL_GPP(2, 183, 206, 256), /* GPP_E */ - ICL_GPP(3, 207, 215, ICL_NO_GPIO), /* JTAG */ + ICL_GPP(0, 153, 176, 224), /* GPP_C */ + ICL_GPP(1, 177, 182, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ + ICL_GPP(2, 183, 206, 256), /* GPP_E */ + ICL_GPP(3, 207, 215, INTEL_GPIO_BASE_NOMAP), /* JTAG */ }; static const struct intel_padgroup icllp_community5_gpps[] = { - ICL_GPP(0, 216, 223, 288), /* GPP_R */ - ICL_GPP(1, 224, 231, 320), /* GPP_S */ - ICL_GPP(2, 232, 240, ICL_NO_GPIO), /* SPI */ + ICL_GPP(0, 216, 223, 288), /* GPP_R */ + ICL_GPP(1, 224, 231, 320), /* GPP_S */ + ICL_GPP(2, 232, 240, INTEL_GPIO_BASE_NOMAP), /* SPI */ }; static const struct intel_community icllp_communities[] = { diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 74fdfd2b9ff5..6a274e20d926 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -798,7 +798,7 @@ static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset, for (j = 0; j < comm->ngpps; j++) { const struct intel_padgroup *pgrp = &comm->gpps[j]; - if (pgrp->gpio_base < 0) + if (pgrp->gpio_base == INTEL_GPIO_BASE_NOMAP) continue; if (offset >= pgrp->gpio_base && @@ -1138,7 +1138,7 @@ static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl, for (i = 0; i < community->ngpps; i++) { const struct intel_padgroup *gpp = &community->gpps[i]; - if (gpp->gpio_base < 0) + if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP) continue; ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), @@ -1180,7 +1180,7 @@ static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl) for (j = 0; j < community->ngpps; j++) { const struct intel_padgroup *gpp = &community->gpps[j]; - if (gpp->gpio_base < 0) + if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP) continue; if (gpp->gpio_base + gpp->size > ngpio) @@ -1276,8 +1276,18 @@ static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl, if (gpps[i].size > 32) return -EINVAL; - if (!gpps[i].gpio_base) - gpps[i].gpio_base = gpps[i].base; + /* Special treatment for GPIO base */ + switch (gpps[i].gpio_base) { + case INTEL_GPIO_BASE_MATCH: + gpps[i].gpio_base = gpps[i].base; + break; + case INTEL_GPIO_BASE_ZERO: + gpps[i].gpio_base = 0; + break; + case INTEL_GPIO_BASE_NOMAP: + default: + break; + } gpps[i].padown_num = padown_num; @@ -1596,7 +1606,7 @@ static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c, struct device *dev = pctrl->dev; u32 requested; - if (padgrp->gpio_base < 0) + if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP) return; requested = intel_gpio_is_requested(&pctrl->chip, padgrp->gpio_base, padgrp->size); diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h index c6f066f6d3fb..cc78c483518f 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.h +++ b/drivers/pinctrl/intel/pinctrl-intel.h @@ -53,8 +53,7 @@ struct intel_function { * @reg_num: GPI_IS register number * @base: Starting pin of this group * @size: Size of this group (maximum is 32). - * @gpio_base: Starting GPIO base of this group (%0 if matches with @base, - * and %-1 if no GPIO mapping should be created) + * @gpio_base: Starting GPIO base of this group * @padown_num: PAD_OWN register number (assigned by the core driver) * * If pad groups of a community are not the same size, use this structure @@ -68,6 +67,19 @@ struct intel_padgroup { unsigned int padown_num; }; +/** + * enum - Special treatment for GPIO base in pad group + * + * @INTEL_GPIO_BASE_ZERO: force GPIO base to be 0 + * @INTEL_GPIO_BASE_NOMAP: no GPIO mapping should be created + * @INTEL_GPIO_BASE_MATCH: matches with starting pin number + */ +enum { + INTEL_GPIO_BASE_ZERO = -2, + INTEL_GPIO_BASE_NOMAP = -1, + INTEL_GPIO_BASE_MATCH = 0, +}; + /** * struct intel_community - Intel pin community description * @barno: MMIO BAR number where registers for this community reside @@ -82,20 +94,20 @@ struct intel_padgroup { * @ie_offset: Register offset of GPI_IE from @regs. * @features: Additional features supported by the hardware * @pin_base: Starting pin of pins in this community + * @npins: Number of pins in this community * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK, - * HOSTSW_OWN, GPI_IS, GPI_IE, etc. Used when @gpps is %NULL. + * HOSTSW_OWN, GPI_IS, GPI_IE. Used when @gpps is %NULL. * @gpp_num_padown_regs: Number of pad registers each pad group consumes at * minimum. Use %0 if the number of registers can be * determined by the size of the group. - * @npins: Number of pins in this community * @gpps: Pad groups if the controller has variable size pad groups * @ngpps: Number of pad groups in this community * @pad_map: Optional non-linear mapping of the pads * @regs: Community specific common registers (reserved for core driver) * @pad_regs: Community specific pad registers (reserved for core driver) * - * Most Intel GPIO host controllers this driver supports each pad group is - * of equal size (except the last one). In that case the driver can just + * In some of Intel GPIO host controllers this driver supports each pad group + * is of equal size (except the last one). In that case the driver can just * fill in @gpp_size field and let the core driver to handle the rest. If * the controller has pad groups of variable size the client driver can * pass custom @gpps and @ngpps instead. @@ -109,12 +121,13 @@ struct intel_community { unsigned int ie_offset; unsigned int features; unsigned int pin_base; + size_t npins; unsigned int gpp_size; unsigned int gpp_num_padown_regs; - size_t npins; const struct intel_padgroup *gpps; size_t ngpps; const unsigned int *pad_map; + /* Reserved for the core driver */ void __iomem *regs; void __iomem *pad_regs; diff --git a/drivers/pinctrl/intel/pinctrl-jasperlake.c b/drivers/pinctrl/intel/pinctrl-jasperlake.c new file mode 100644 index 000000000000..9bd0e8e6310c --- /dev/null +++ b/drivers/pinctrl/intel/pinctrl-jasperlake.c @@ -0,0 +1,344 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Intel Jasper Lake PCH pinctrl/GPIO driver + * + * Copyright (C) 2020, Intel Corporation + * Author: Andy Shevchenko + */ + +#include +#include +#include + +#include + +#include "pinctrl-intel.h" + +#define JSL_PAD_OWN 0x020 +#define JSL_PADCFGLOCK 0x080 +#define JSL_HOSTSW_OWN 0x0b0 +#define JSL_GPI_IS 0x100 +#define JSL_GPI_IE 0x120 + +#define JSL_GPP(r, s, e, g) \ + { \ + .reg_num = (r), \ + .base = (s), \ + .size = ((e) - (s) + 1), \ + .gpio_base = (g), \ + } + +#define JSL_COMMUNITY(b, s, e, g) \ + { \ + .barno = (b), \ + .padown_offset = JSL_PAD_OWN, \ + .padcfglock_offset = JSL_PADCFGLOCK, \ + .hostown_offset = JSL_HOSTSW_OWN, \ + .is_offset = JSL_GPI_IS, \ + .ie_offset = JSL_GPI_IE, \ + .pin_base = (s), \ + .npins = ((e) - (s) + 1), \ + .gpps = (g), \ + .ngpps = ARRAY_SIZE(g), \ + } + +/* Jasper Lake */ +static const struct pinctrl_pin_desc jsl_pins[] = { + /* GPP_F */ + PINCTRL_PIN(0, "CNV_BRI_DT_UART0_RTSB"), + PINCTRL_PIN(1, "CNV_BRI_RSP_UART0_RXD"), + PINCTRL_PIN(2, "EMMC_HIP_MON"), + PINCTRL_PIN(3, "CNV_RGI_RSP_UART0_CTSB"), + PINCTRL_PIN(4, "CNV_RF_RESET_B"), + PINCTRL_PIN(5, "MODEM_CLKREQ"), + PINCTRL_PIN(6, "CNV_PA_BLANKING"), + PINCTRL_PIN(7, "EMMC_CMD"), + PINCTRL_PIN(8, "EMMC_DATA0"), + PINCTRL_PIN(9, "EMMC_DATA1"), + PINCTRL_PIN(10, "EMMC_DATA2"), + PINCTRL_PIN(11, "EMMC_DATA3"), + PINCTRL_PIN(12, "EMMC_DATA4"), + PINCTRL_PIN(13, "EMMC_DATA5"), + PINCTRL_PIN(14, "EMMC_DATA6"), + PINCTRL_PIN(15, "EMMC_DATA7"), + PINCTRL_PIN(16, "EMMC_RCLK"), + PINCTRL_PIN(17, "EMMC_CLK"), + PINCTRL_PIN(18, "EMMC_RESETB"), + PINCTRL_PIN(19, "A4WP_PRESENT"), + /* GPP_B */ + PINCTRL_PIN(20, "CORE_VID_0"), + PINCTRL_PIN(21, "CORE_VID_1"), + PINCTRL_PIN(22, "VRALERTB"), + PINCTRL_PIN(23, "CPU_GP_2"), + PINCTRL_PIN(24, "CPU_GP_3"), + PINCTRL_PIN(25, "SRCCLKREQB_0"), + PINCTRL_PIN(26, "SRCCLKREQB_1"), + PINCTRL_PIN(27, "SRCCLKREQB_2"), + PINCTRL_PIN(28, "SRCCLKREQB_3"), + PINCTRL_PIN(29, "SRCCLKREQB_4"), + PINCTRL_PIN(30, "SRCCLKREQB_5"), + PINCTRL_PIN(31, "PMCALERTB"), + PINCTRL_PIN(32, "SLP_S0B"), + PINCTRL_PIN(33, "PLTRSTB"), + PINCTRL_PIN(34, "SPKR"), + PINCTRL_PIN(35, "GSPI0_CS0B"), + PINCTRL_PIN(36, "GSPI0_CLK"), + PINCTRL_PIN(37, "GSPI0_MISO"), + PINCTRL_PIN(38, "GSPI0_MOSI"), + PINCTRL_PIN(39, "GSPI1_CS0B"), + PINCTRL_PIN(40, "GSPI1_CLK"), + PINCTRL_PIN(41, "GSPI1_MISO"), + PINCTRL_PIN(42, "GSPI1_MOSI"), + PINCTRL_PIN(43, "DDSP_HPD_A"), + PINCTRL_PIN(44, "GSPI0_CLK_LOOPBK"), + PINCTRL_PIN(45, "GSPI1_CLK_LOOPBK"), + /* GPP_A */ + PINCTRL_PIN(46, "ESPI_IO_0"), + PINCTRL_PIN(47, "ESPI_IO_1"), + PINCTRL_PIN(48, "ESPI_IO_2"), + PINCTRL_PIN(49, "ESPI_IO_3"), + PINCTRL_PIN(50, "ESPI_CSB"), + PINCTRL_PIN(51, "ESPI_CLK"), + PINCTRL_PIN(52, "ESPI_RESETB"), + PINCTRL_PIN(53, "SMBCLK"), + PINCTRL_PIN(54, "SMBDATA"), + PINCTRL_PIN(55, "SMBALERTB"), + PINCTRL_PIN(56, "CPU_GP_0"), + PINCTRL_PIN(57, "CPU_GP_1"), + PINCTRL_PIN(58, "USB2_OCB_1"), + PINCTRL_PIN(59, "USB2_OCB_2"), + PINCTRL_PIN(60, "USB2_OCB_3"), + PINCTRL_PIN(61, "DDSP_HPD_A_TIME_SYNC_0"), + PINCTRL_PIN(62, "DDSP_HPD_B"), + PINCTRL_PIN(63, "DDSP_HPD_C"), + PINCTRL_PIN(64, "USB2_OCB_0"), + PINCTRL_PIN(65, "PCHHOTB"), + PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"), + /* GPP_S */ + PINCTRL_PIN(67, "SNDW1_CLK"), + PINCTRL_PIN(68, "SNDW1_DATA"), + PINCTRL_PIN(69, "SNDW2_CLK"), + PINCTRL_PIN(70, "SNDW2_DATA"), + PINCTRL_PIN(71, "SNDW1_CLK"), + PINCTRL_PIN(72, "SNDW1_DATA"), + PINCTRL_PIN(73, "SNDW4_CLK_DMIC_CLK_0"), + PINCTRL_PIN(74, "SNDW4_DATA_DMIC_DATA_0"), + /* GPP_R */ + PINCTRL_PIN(75, "HDA_BCLK"), + PINCTRL_PIN(76, "HDA_SYNC"), + PINCTRL_PIN(77, "HDA_SDO"), + PINCTRL_PIN(78, "HDA_SDI_0"), + PINCTRL_PIN(79, "HDA_RSTB"), + PINCTRL_PIN(80, "HDA_SDI_1"), + PINCTRL_PIN(81, "I2S1_SFRM"), + PINCTRL_PIN(82, "I2S1_TXD"), + /* GPP_H */ + PINCTRL_PIN(83, "GPPC_H_0"), + PINCTRL_PIN(84, "SD_PWR_EN_B"), + PINCTRL_PIN(85, "MODEM_CLKREQ"), + PINCTRL_PIN(86, "SX_EXIT_HOLDOFFB"), + PINCTRL_PIN(87, "I2C2_SDA"), + PINCTRL_PIN(88, "I2C2_SCL"), + PINCTRL_PIN(89, "I2C3_SDA"), + PINCTRL_PIN(90, "I2C3_SCL"), + PINCTRL_PIN(91, "I2C4_SDA"), + PINCTRL_PIN(92, "I2C4_SCL"), + PINCTRL_PIN(93, "CPU_VCCIO_PWR_GATEB"), + PINCTRL_PIN(94, "I2S2_SCLK"), + PINCTRL_PIN(95, "I2S2_SFRM"), + PINCTRL_PIN(96, "I2S2_TXD"), + PINCTRL_PIN(97, "I2S2_RXD"), + PINCTRL_PIN(98, "I2S1_SCLK"), + PINCTRL_PIN(99, "GPPC_H_16"), + PINCTRL_PIN(100, "GPPC_H_17"), + PINCTRL_PIN(101, "GPPC_H_18"), + PINCTRL_PIN(102, "GPPC_H_19"), + PINCTRL_PIN(103, "GPPC_H_20"), + PINCTRL_PIN(104, "GPPC_H_21"), + PINCTRL_PIN(105, "GPPC_H_22"), + PINCTRL_PIN(106, "GPPC_H_23"), + /* GPP_D */ + PINCTRL_PIN(107, "SPI1_CSB"), + PINCTRL_PIN(108, "SPI1_CLK"), + PINCTRL_PIN(109, "SPI1_MISO_IO_1"), + PINCTRL_PIN(110, "SPI1_MOSI_IO_0"), + PINCTRL_PIN(111, "ISH_I2C0_SDA"), + PINCTRL_PIN(112, "ISH_I2C0_SCL"), + PINCTRL_PIN(113, "ISH_I2C1_SDA"), + PINCTRL_PIN(114, "ISH_I2C1_SCL"), + PINCTRL_PIN(115, "ISH_SPI_CSB"), + PINCTRL_PIN(116, "ISH_SPI_CLK"), + PINCTRL_PIN(117, "ISH_SPI_MISO"), + PINCTRL_PIN(118, "ISH_SPI_MOSI"), + PINCTRL_PIN(119, "ISH_UART0_RXD"), + PINCTRL_PIN(120, "ISH_UART0_TXD"), + PINCTRL_PIN(121, "ISH_UART0_RTSB"), + PINCTRL_PIN(122, "ISH_UART0_CTSB"), + PINCTRL_PIN(123, "SPI1_IO_2"), + PINCTRL_PIN(124, "SPI1_IO_3"), + PINCTRL_PIN(125, "I2S_MCLK"), + PINCTRL_PIN(126, "CNV_MFUART2_RXD"), + PINCTRL_PIN(127, "CNV_MFUART2_TXD"), + PINCTRL_PIN(128, "CNV_PA_BLANKING"), + PINCTRL_PIN(129, "I2C5_SDA"), + PINCTRL_PIN(130, "I2C5_SCL"), + PINCTRL_PIN(131, "GSPI2_CLK_LOOPBK"), + PINCTRL_PIN(132, "SPI1_CLK_LOOPBK"), + /* vGPIO */ + PINCTRL_PIN(133, "CNV_BTEN"), + PINCTRL_PIN(134, "CNV_WCEN"), + PINCTRL_PIN(135, "CNV_BT_HOST_WAKEB"), + PINCTRL_PIN(136, "CNV_BT_IF_SELECT"), + PINCTRL_PIN(137, "vCNV_BT_UART_TXD"), + PINCTRL_PIN(138, "vCNV_BT_UART_RXD"), + PINCTRL_PIN(139, "vCNV_BT_UART_CTS_B"), + PINCTRL_PIN(140, "vCNV_BT_UART_RTS_B"), + PINCTRL_PIN(141, "vCNV_MFUART1_TXD"), + PINCTRL_PIN(142, "vCNV_MFUART1_RXD"), + PINCTRL_PIN(143, "vCNV_MFUART1_CTS_B"), + PINCTRL_PIN(144, "vCNV_MFUART1_RTS_B"), + PINCTRL_PIN(145, "vUART0_TXD"), + PINCTRL_PIN(146, "vUART0_RXD"), + PINCTRL_PIN(147, "vUART0_CTS_B"), + PINCTRL_PIN(148, "vUART0_RTS_B"), + PINCTRL_PIN(149, "vISH_UART0_TXD"), + PINCTRL_PIN(150, "vISH_UART0_RXD"), + PINCTRL_PIN(151, "vISH_UART0_CTS_B"), + PINCTRL_PIN(152, "vISH_UART0_RTS_B"), + PINCTRL_PIN(153, "vCNV_BT_I2S_BCLK"), + PINCTRL_PIN(154, "vCNV_BT_I2S_WS_SYNC"), + PINCTRL_PIN(155, "vCNV_BT_I2S_SDO"), + PINCTRL_PIN(156, "vCNV_BT_I2S_SDI"), + PINCTRL_PIN(157, "vI2S2_SCLK"), + PINCTRL_PIN(158, "vI2S2_SFRM"), + PINCTRL_PIN(159, "vI2S2_TXD"), + PINCTRL_PIN(160, "vI2S2_RXD"), + PINCTRL_PIN(161, "vSD3_CD_B"), + /* GPP_C */ + PINCTRL_PIN(162, "GPPC_C_0"), + PINCTRL_PIN(163, "GPPC_C_1"), + PINCTRL_PIN(164, "GPPC_C_2"), + PINCTRL_PIN(165, "GPPC_C_3"), + PINCTRL_PIN(166, "GPPC_C_4"), + PINCTRL_PIN(167, "GPPC_C_5"), + PINCTRL_PIN(168, "SUSWARNB_SUSPWRDNACK"), + PINCTRL_PIN(169, "SUSACKB"), + PINCTRL_PIN(170, "UART0_RXD"), + PINCTRL_PIN(171, "UART0_TXD"), + PINCTRL_PIN(172, "UART0_RTSB"), + PINCTRL_PIN(173, "UART0_CTSB"), + PINCTRL_PIN(174, "UART1_RXD"), + PINCTRL_PIN(175, "UART1_TXD"), + PINCTRL_PIN(176, "UART1_RTSB"), + PINCTRL_PIN(177, "UART1_CTSB"), + PINCTRL_PIN(178, "I2C0_SDA"), + PINCTRL_PIN(179, "I2C0_SCL"), + PINCTRL_PIN(180, "I2C1_SDA"), + PINCTRL_PIN(181, "I2C1_SCL"), + PINCTRL_PIN(182, "UART2_RXD"), + PINCTRL_PIN(183, "UART2_TXD"), + PINCTRL_PIN(184, "UART2_RTSB"), + PINCTRL_PIN(185, "UART2_CTSB"), + /* HVCMOS */ + PINCTRL_PIN(186, "L_BKLTEN"), + PINCTRL_PIN(187, "L_BKLTCTL"), + PINCTRL_PIN(188, "L_VDDEN"), + PINCTRL_PIN(189, "SYS_PWROK"), + PINCTRL_PIN(190, "SYS_RESETB"), + PINCTRL_PIN(191, "MLK_RSTB"), + /* GPP_E */ + PINCTRL_PIN(192, "ISH_GP_0"), + PINCTRL_PIN(193, "ISH_GP_1"), + PINCTRL_PIN(194, "IMGCLKOUT_1"), + PINCTRL_PIN(195, "ISH_GP_2"), + PINCTRL_PIN(196, "IMGCLKOUT_2"), + PINCTRL_PIN(197, "SATA_LEDB"), + PINCTRL_PIN(198, "IMGCLKOUT_3"), + PINCTRL_PIN(199, "ISH_GP_3"), + PINCTRL_PIN(200, "ISH_GP_4"), + PINCTRL_PIN(201, "ISH_GP_5"), + PINCTRL_PIN(202, "ISH_GP_6"), + PINCTRL_PIN(203, "ISH_GP_7"), + PINCTRL_PIN(204, "IMGCLKOUT_4"), + PINCTRL_PIN(205, "DDPA_CTRLCLK"), + PINCTRL_PIN(206, "DDPA_CTRLDATA"), + PINCTRL_PIN(207, "DDPB_CTRLCLK"), + PINCTRL_PIN(208, "DDPB_CTRLDATA"), + PINCTRL_PIN(209, "DDPC_CTRLCLK"), + PINCTRL_PIN(210, "DDPC_CTRLDATA"), + PINCTRL_PIN(211, "IMGCLKOUT_5"), + PINCTRL_PIN(212, "CNV_BRI_DT"), + PINCTRL_PIN(213, "CNV_BRI_RSP"), + PINCTRL_PIN(214, "CNV_RGI_DT"), + PINCTRL_PIN(215, "CNV_RGI_RSP"), + /* GPP_G */ + PINCTRL_PIN(216, "SD3_CMD"), + PINCTRL_PIN(217, "SD3_D0"), + PINCTRL_PIN(218, "SD3_D1"), + PINCTRL_PIN(219, "SD3_D2"), + PINCTRL_PIN(220, "SD3_D3"), + PINCTRL_PIN(221, "SD3_CDB"), + PINCTRL_PIN(222, "SD3_CLK"), + PINCTRL_PIN(223, "SD3_WP"), +}; + +static const struct intel_padgroup jsl_community0_gpps[] = { + JSL_GPP(0, 0, 19, 320), /* GPP_F */ + JSL_GPP(1, 20, 45, 32), /* GPP_B */ + JSL_GPP(2, 46, 66, 64), /* GPP_A */ + JSL_GPP(3, 67, 74, 96), /* GPP_S */ + JSL_GPP(4, 75, 82, 128), /* GPP_R */ +}; + +static const struct intel_padgroup jsl_community1_gpps[] = { + JSL_GPP(0, 83, 106, 160), /* GPP_H */ + JSL_GPP(1, 107, 132, 192), /* GPP_D */ + JSL_GPP(2, 133, 161, 224), /* vGPIO */ + JSL_GPP(3, 162, 185, 256), /* GPP_C */ +}; + +static const struct intel_padgroup jsl_community4_gpps[] = { + JSL_GPP(0, 186, 191, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ + JSL_GPP(1, 192, 215, 288), /* GPP_E */ +}; + +static const struct intel_padgroup jsl_community5_gpps[] = { + JSL_GPP(0, 216, 223, INTEL_GPIO_BASE_ZERO), /* GPP_G */ +}; + +static const struct intel_community jsl_communities[] = { + JSL_COMMUNITY(0, 0, 82, jsl_community0_gpps), + JSL_COMMUNITY(1, 83, 185, jsl_community1_gpps), + JSL_COMMUNITY(2, 186, 215, jsl_community4_gpps), + JSL_COMMUNITY(3, 216, 223, jsl_community5_gpps), +}; + +static const struct intel_pinctrl_soc_data jsl_soc_data = { + .pins = jsl_pins, + .npins = ARRAY_SIZE(jsl_pins), + .communities = jsl_communities, + .ncommunities = ARRAY_SIZE(jsl_communities), +}; + +static const struct acpi_device_id jsl_pinctrl_acpi_match[] = { + { "INT34C8", (kernel_ulong_t)&jsl_soc_data }, + { } +}; +MODULE_DEVICE_TABLE(acpi, jsl_pinctrl_acpi_match); + +static INTEL_PINCTRL_PM_OPS(jsl_pinctrl_pm_ops); + +static struct platform_driver jsl_pinctrl_driver = { + .probe = intel_pinctrl_probe_by_hid, + .driver = { + .name = "jasperlake-pinctrl", + .acpi_match_table = jsl_pinctrl_acpi_match, + .pm = &jsl_pinctrl_pm_ops, + }, +}; + +module_platform_driver(jsl_pinctrl_driver); + +MODULE_AUTHOR("Andy Shevchenko "); +MODULE_DESCRIPTION("Intel Jasper Lake PCH pinctrl/GPIO driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index e928742c7181..a45b8f2182fd 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -794,11 +794,11 @@ static int lp_gpio_probe(struct platform_device *pdev) const struct intel_pinctrl_soc_data *soc; struct intel_pinctrl *lg; struct gpio_chip *gc; - struct resource *io_rc, *irq_rc; struct device *dev = &pdev->dev; + struct resource *io_rc; void __iomem *regs; unsigned int i; - int ret; + int irq, ret; soc = (const struct intel_pinctrl_soc_data *)device_get_match_data(dev); if (!soc) @@ -870,8 +870,8 @@ static int lp_gpio_probe(struct platform_device *pdev) gc->parent = dev; /* set up interrupts */ - irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (irq_rc && irq_rc->start) { + irq = platform_get_irq_optional(pdev, 0); + if (irq > 0) { struct gpio_irq_chip *girq; girq = &gc->irq; @@ -884,7 +884,7 @@ static int lp_gpio_probe(struct platform_device *pdev) GFP_KERNEL); if (!girq->parents) return -ENOMEM; - girq->parents[0] = (unsigned int)irq_rc->start; + girq->parents[0] = irq; girq->default_type = IRQ_TYPE_NONE; girq->handler = handle_bad_irq; } diff --git a/drivers/pinctrl/intel/pinctrl-tigerlake.c b/drivers/pinctrl/intel/pinctrl-tigerlake.c index 08a86f6fdea6..bcfd7548e282 100644 --- a/drivers/pinctrl/intel/pinctrl-tigerlake.c +++ b/drivers/pinctrl/intel/pinctrl-tigerlake.c @@ -21,8 +21,6 @@ #define TGL_GPI_IS 0x100 #define TGL_GPI_IE 0x120 -#define TGL_NO_GPIO -1 - #define TGL_GPP(r, s, e, g) \ { \ .reg_num = (r), \ @@ -342,30 +340,30 @@ static const struct pinctrl_pin_desc tgllp_pins[] = { }; static const struct intel_padgroup tgllp_community0_gpps[] = { - TGL_GPP(0, 0, 25, 0), /* GPP_B */ - TGL_GPP(1, 26, 41, 32), /* GPP_T */ - TGL_GPP(2, 42, 66, 64), /* GPP_A */ + TGL_GPP(0, 0, 25, 0), /* GPP_B */ + TGL_GPP(1, 26, 41, 32), /* GPP_T */ + TGL_GPP(2, 42, 66, 64), /* GPP_A */ }; static const struct intel_padgroup tgllp_community1_gpps[] = { - TGL_GPP(0, 67, 74, 96), /* GPP_S */ - TGL_GPP(1, 75, 98, 128), /* GPP_H */ - TGL_GPP(2, 99, 119, 160), /* GPP_D */ - TGL_GPP(3, 120, 143, 192), /* GPP_U */ - TGL_GPP(4, 144, 170, 224), /* vGPIO */ + TGL_GPP(0, 67, 74, 96), /* GPP_S */ + TGL_GPP(1, 75, 98, 128), /* GPP_H */ + TGL_GPP(2, 99, 119, 160), /* GPP_D */ + TGL_GPP(3, 120, 143, 192), /* GPP_U */ + TGL_GPP(4, 144, 170, 224), /* vGPIO */ }; static const struct intel_padgroup tgllp_community4_gpps[] = { - TGL_GPP(0, 171, 194, 256), /* GPP_C */ - TGL_GPP(1, 195, 219, 288), /* GPP_F */ - TGL_GPP(2, 220, 225, TGL_NO_GPIO), /* HVCMOS */ - TGL_GPP(3, 226, 250, 320), /* GPP_E */ - TGL_GPP(4, 251, 259, TGL_NO_GPIO), /* JTAG */ + TGL_GPP(0, 171, 194, 256), /* GPP_C */ + TGL_GPP(1, 195, 219, 288), /* GPP_F */ + TGL_GPP(2, 220, 225, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ + TGL_GPP(3, 226, 250, 320), /* GPP_E */ + TGL_GPP(4, 251, 259, INTEL_GPIO_BASE_NOMAP), /* JTAG */ }; static const struct intel_padgroup tgllp_community5_gpps[] = { - TGL_GPP(0, 260, 267, 352), /* GPP_R */ - TGL_GPP(1, 268, 276, TGL_NO_GPIO), /* SPI */ + TGL_GPP(0, 260, 267, 352), /* GPP_R */ + TGL_GPP(1, 268, 276, INTEL_GPIO_BASE_NOMAP), /* SPI */ }; static const struct intel_community tgllp_communities[] = { diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 701f9af63f5e..f32d3644c509 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -3,10 +3,12 @@ menu "MediaTek pinctrl drivers" depends on ARCH_MEDIATEK || COMPILE_TEST config EINT_MTK - bool "MediaTek External Interrupt Support" + tristate "MediaTek External Interrupt Support" depends on PINCTRL_MTK || PINCTRL_MTK_MOORE || PINCTRL_MTK_PARIS || COMPILE_TEST select GPIOLIB select IRQ_DOMAIN + default y if PINCTRL_MTK || PINCTRL_MTK_MOORE + default PINCTRL_MTK_PARIS config PINCTRL_MTK bool @@ -17,6 +19,9 @@ config PINCTRL_MTK select EINT_MTK select OF_GPIO +config PINCTRL_MTK_V2 + tristate + config PINCTRL_MTK_MOORE bool depends on OF @@ -25,15 +30,17 @@ config PINCTRL_MTK_MOORE select GENERIC_PINMUX_FUNCTIONS select GPIOLIB select OF_GPIO + select PINCTRL_MTK_V2 config PINCTRL_MTK_PARIS - bool + tristate depends on OF select PINMUX select GENERIC_PINCONF select GPIOLIB select EINT_MTK select OF_GPIO + select PINCTRL_MTK_V2 # For ARMv7 SoCs config PINCTRL_MT2701 @@ -80,7 +87,7 @@ config PINCTRL_MT2712 select PINCTRL_MTK config PINCTRL_MT6765 - bool "Mediatek MT6765 pin control" + tristate "Mediatek MT6765 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index a74325abd877..4b7132876e71 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -2,8 +2,9 @@ # Core obj-$(CONFIG_EINT_MTK) += mtk-eint.o obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o -obj-$(CONFIG_PINCTRL_MTK_MOORE) += pinctrl-moore.o pinctrl-mtk-common-v2.o -obj-$(CONFIG_PINCTRL_MTK_PARIS) += pinctrl-paris.o pinctrl-mtk-common-v2.o +obj-$(CONFIG_PINCTRL_MTK_V2) += pinctrl-mtk-common-v2.o +obj-$(CONFIG_PINCTRL_MTK_MOORE) += pinctrl-moore.o +obj-$(CONFIG_PINCTRL_MTK_PARIS) += pinctrl-paris.o # SoC Drivers obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o diff --git a/drivers/pinctrl/mediatek/mtk-eint.c b/drivers/pinctrl/mediatek/mtk-eint.c index 7e526bcf5e0b..22736f60c16c 100644 --- a/drivers/pinctrl/mediatek/mtk-eint.c +++ b/drivers/pinctrl/mediatek/mtk-eint.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -379,6 +380,7 @@ int mtk_eint_do_suspend(struct mtk_eint *eint) return 0; } +EXPORT_SYMBOL_GPL(mtk_eint_do_suspend); int mtk_eint_do_resume(struct mtk_eint *eint) { @@ -386,6 +388,7 @@ int mtk_eint_do_resume(struct mtk_eint *eint) return 0; } +EXPORT_SYMBOL_GPL(mtk_eint_do_resume); int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_num, unsigned int debounce) @@ -440,6 +443,7 @@ int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_num, return 0; } +EXPORT_SYMBOL_GPL(mtk_eint_set_debounce); int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n) { @@ -451,6 +455,7 @@ int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n) return irq; } +EXPORT_SYMBOL_GPL(mtk_eint_find_irq); int mtk_eint_do_init(struct mtk_eint *eint) { @@ -495,3 +500,7 @@ int mtk_eint_do_init(struct mtk_eint *eint) return 0; } +EXPORT_SYMBOL_GPL(mtk_eint_do_init); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MediaTek EINT Driver"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6765.c b/drivers/pinctrl/mediatek/pinctrl-mt6765.c index 905dae8c3fd8..2c59d3936256 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6765.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6765.c @@ -6,6 +6,7 @@ * */ +#include #include "pinctrl-mtk-mt6765.h" #include "pinctrl-paris.h" @@ -1103,3 +1104,6 @@ static int __init mt6765_pinctrl_init(void) return platform_driver_register(&mt6765_pinctrl_driver); } arch_initcall(mt6765_pinctrl_init); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MediaTek MT6765 Pinctrl Driver"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c index d3169a87e1b3..b77b18fe5adc 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include "mtk-eint.h" @@ -204,6 +205,7 @@ int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, return 0; } +EXPORT_SYMBOL_GPL(mtk_hw_set_value); int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, int field, int *value) @@ -223,6 +225,7 @@ int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, return 0; } +EXPORT_SYMBOL_GPL(mtk_hw_get_value); static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw, unsigned long eint_n) { @@ -361,6 +364,7 @@ int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev) return mtk_eint_do_init(hw->eint); } +EXPORT_SYMBOL_GPL(mtk_build_eint); /* Revision 0 */ int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw, @@ -380,6 +384,7 @@ int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_set); int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, int *res) @@ -402,6 +407,7 @@ int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_get); int mtk_pinconf_bias_set(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, bool pullup) @@ -421,6 +427,7 @@ int mtk_pinconf_bias_set(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set); int mtk_pinconf_bias_get(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, bool pullup, int *res) @@ -440,6 +447,7 @@ int mtk_pinconf_bias_get(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get); /* Revision 1 */ int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw, @@ -454,6 +462,7 @@ int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_set_rev1); int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, int *res) @@ -471,6 +480,7 @@ int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_get_rev1); int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, bool pullup) @@ -490,6 +500,7 @@ int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_rev1); int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, bool pullup, @@ -515,6 +526,7 @@ int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_rev1); /* Combo for the following pull register type: * 1. PU + PD @@ -715,6 +727,7 @@ int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw, out: return err; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_combo); int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, @@ -735,6 +748,7 @@ int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw, out: return err; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_combo); /* Revision 0 */ int mtk_pinconf_drive_set(struct mtk_pinctrl *hw, @@ -764,6 +778,7 @@ int mtk_pinconf_drive_set(struct mtk_pinctrl *hw, return err; } +EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set); int mtk_pinconf_drive_get(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, int *val) @@ -788,6 +803,7 @@ int mtk_pinconf_drive_get(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get); /* Revision 1 */ int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw, @@ -809,6 +825,7 @@ int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw, return err; } +EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set_rev1); int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, int *val) @@ -826,18 +843,21 @@ int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get_rev1); int mtk_pinconf_drive_set_raw(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, u32 arg) { return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV, arg); } +EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set_raw); int mtk_pinconf_drive_get_raw(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, int *val) { return mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, val); } +EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get_raw); int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, bool pullup, @@ -878,6 +898,7 @@ int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw, return err; } +EXPORT_SYMBOL_GPL(mtk_pinconf_adv_pull_set); int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, bool pullup, @@ -920,6 +941,7 @@ int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_adv_pull_get); int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, u32 arg) @@ -946,6 +968,7 @@ int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw, return err; } +EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_set); int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, u32 *val) @@ -969,3 +992,8 @@ int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_get); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Sean Wang "); +MODULE_DESCRIPTION("Pin configuration library module for mediatek SoCs"); diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c index ee305f140400..90a432bf9fed 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -10,6 +10,7 @@ */ #include +#include #include #include "pinctrl-paris.h" @@ -631,6 +632,7 @@ ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw, return len; } +EXPORT_SYMBOL_GPL(mtk_pctrl_show_one_pin); #define PIN_DBG_BUF_SZ 96 static void mtk_pctrl_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, @@ -1019,6 +1021,7 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev, return 0; } +EXPORT_SYMBOL_GPL(mtk_paris_pinctrl_probe); static int mtk_paris_pinctrl_suspend(struct device *device) { @@ -1038,3 +1041,6 @@ const struct dev_pm_ops mtk_paris_pinctrl_pm_ops = { .suspend_noirq = mtk_paris_pinctrl_suspend, .resume_noirq = mtk_paris_pinctrl_resume, }; + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MediaTek Pinctrl Common Driver V2 Paris"); diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index bbc919bef2bf..079f8ee8d353 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -549,6 +549,18 @@ static const struct pinconf_ops meson_pinconf_ops = { .is_generic = true, }; +static int meson_gpio_get_direction(struct gpio_chip *chip, unsigned gpio) +{ + struct meson_pinctrl *pc = gpiochip_get_data(chip); + int ret; + + ret = meson_pinconf_get_output(pc, gpio); + if (ret < 0) + return ret; + + return ret ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; +} + static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) { return meson_pinconf_set_output(gpiochip_get_data(chip), gpio, false); @@ -591,6 +603,8 @@ static int meson_gpiolib_register(struct meson_pinctrl *pc) pc->chip.parent = pc->dev; pc->chip.request = gpiochip_generic_request; pc->chip.free = gpiochip_generic_free; + pc->chip.set_config = gpiochip_generic_config; + pc->chip.get_direction = meson_gpio_get_direction; pc->chip.direction_input = meson_gpio_direction_input; pc->chip.direction_output = meson_gpio_direction_output; pc->chip.get = meson_gpio_get; diff --git a/drivers/pinctrl/nomadik/pinctrl-ab8505.c b/drivers/pinctrl/nomadik/pinctrl-ab8505.c index 5e6e7d28390a..b93af1fb37f0 100644 --- a/drivers/pinctrl/nomadik/pinctrl-ab8505.c +++ b/drivers/pinctrl/nomadik/pinctrl-ab8505.c @@ -178,6 +178,7 @@ static const struct abx500_pingroup ab8505_groups[] = { AB8505_PIN_GROUP(gpio40_a_1, ABX500_ALT_A), AB8505_PIN_GROUP(gpio41_a_1, ABX500_ALT_A), AB8505_PIN_GROUP(uartrxdata_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(gpio50_a_1, ABX500_ALT_A), AB8505_PIN_GROUP(gpio52_a_1, ABX500_ALT_A), AB8505_PIN_GROUP(gpio53_a_1, ABX500_ALT_A), AB8505_PIN_GROUP(pdmdata_b_1, ABX500_ALT_B), diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c index b9246e0b4fe2..acad3887cc74 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c @@ -691,18 +691,21 @@ static const struct nmk_pingroup nmk_db8500_groups[] = { DB8500_PIN_GROUP(lcd_d8_d11_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(lcd_d12_d23_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(kp_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(kpskaskb_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(mc2_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(ssp1_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(ssp0_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(ipgpio0_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(ipgpio1_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(modem_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(kp_a_2, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(msp2sck_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(msp2_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(mc1_a_2, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(mc1dir_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(hsit_a_2, NMK_GPIO_ALT_A), @@ -760,7 +763,7 @@ static const struct nmk_pingroup nmk_db8500_groups[] = { DB8500_PIN_GROUP(u0_c_1, NMK_GPIO_ALT_C), DB8500_PIN_GROUP(ipgpio4_c_1, NMK_GPIO_ALT_C), DB8500_PIN_GROUP(ipgpio5_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ipgpio6_c_2, NMK_GPIO_ALT_C), DB8500_PIN_GROUP(ipgpio7_c_1, NMK_GPIO_ALT_C), DB8500_PIN_GROUP(smcleale_c_1, NMK_GPIO_ALT_C), DB8500_PIN_GROUP(stmape_c_1, NMK_GPIO_ALT_C), @@ -955,6 +958,7 @@ static const struct nmk_function nmk_db8500_functions[] = { FUNCTION(spi0), FUNCTION(spi2), FUNCTION(remap), + FUNCTION(sbag), FUNCTION(ptm), FUNCTION(rf), FUNCTION(hx), diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c index ca7bbe4164c0..ba25c4654391 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c @@ -1343,8 +1343,6 @@ static const struct nmk_cfg_param nmk_cfg_params[] = { static int nmk_dt_pin_config(int index, int val, unsigned long *config) { - int ret = 0; - if (nmk_cfg_params[index].choice == NULL) *config = nmk_cfg_params[index].config; else { @@ -1354,7 +1352,7 @@ static int nmk_dt_pin_config(int index, int val, unsigned long *config) nmk_cfg_params[index].choice[val]; } } - return ret; + return 0; } static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name) diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index 694912409fd9..54222ccddfb1 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -1019,7 +1019,7 @@ static int atmel_pinctrl_probe(struct platform_device *pdev) atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(atmel_pioctrl->reg_base)) - return -EINVAL; + return PTR_ERR(atmel_pioctrl->reg_base); atmel_pioctrl->clk = devm_clk_get(dev, NULL); if (IS_ERR(atmel_pioctrl->clk)) { diff --git a/drivers/pinctrl/pinctrl-bm1880.c b/drivers/pinctrl/pinctrl-bm1880.c index f7dff4f14101..d1a7d9836787 100644 --- a/drivers/pinctrl/pinctrl-bm1880.c +++ b/drivers/pinctrl/pinctrl-bm1880.c @@ -408,6 +408,7 @@ static const struct bm1880_pctrl_group bm1880_pctrl_groups[] = { BM1880_PINCTRL_GRP(pwm34), BM1880_PINCTRL_GRP(pwm35), BM1880_PINCTRL_GRP(pwm36), + BM1880_PINCTRL_GRP(pwm37), BM1880_PINCTRL_GRP(i2c0), BM1880_PINCTRL_GRP(i2c1), BM1880_PINCTRL_GRP(i2c2), diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index e5dcf77fe43d..6a8d44504f94 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -1977,6 +1977,25 @@ static const struct pinctrl_ops ingenic_pctlops = { .dt_free_map = pinconf_generic_dt_free_map, }; +static int ingenic_gpio_irq_request(struct irq_data *data) +{ + struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); + int ret; + + ret = ingenic_gpio_direction_input(gpio_chip, data->hwirq); + if (ret) + return ret; + + return gpiochip_reqres_irq(gpio_chip, data->hwirq); +} + +static void ingenic_gpio_irq_release(struct irq_data *data) +{ + struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); + + return gpiochip_relres_irq(gpio_chip, data->hwirq); +} + static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc, int pin, int func) { @@ -2338,6 +2357,8 @@ static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc, jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack; jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type; jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake; + jzgc->irq_chip.irq_request_resources = ingenic_gpio_irq_request; + jzgc->irq_chip.irq_release_resources = ingenic_gpio_irq_release; jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND; girq = &jzgc->gc.irq; diff --git a/drivers/pinctrl/pinctrl-lantiq.c b/drivers/pinctrl/pinctrl-lantiq.c index aa92f141b865..626e02d7a1ba 100644 --- a/drivers/pinctrl/pinctrl-lantiq.c +++ b/drivers/pinctrl/pinctrl-lantiq.c @@ -221,7 +221,7 @@ static int match_mux(const struct ltq_mfp_pin *mfp, unsigned mux) return i; } -/* dont assume .mfp is linearly mapped. find the mfp with the correct .pin */ +/* don't assume .mfp is linearly mapped. find the mfp with the correct .pin */ static int match_mfp(const struct ltq_pinmux_info *info, int pin) { int i; diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c index 3a235487e38d..151931b593f6 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.c +++ b/drivers/pinctrl/pinctrl-mcp23s08.c @@ -1,34 +1,23 @@ // SPDX-License-Identifier: GPL-2.0-only /* MCP23S08 SPI/I2C GPIO driver */ +#include #include #include #include +#include #include +#include #include -#include -#include -#include #include #include #include -#include #include #include #include #include -/* - * MCP types supported by driver - */ -#define MCP_TYPE_S08 0 -#define MCP_TYPE_S17 1 -#define MCP_TYPE_008 2 -#define MCP_TYPE_017 3 -#define MCP_TYPE_S18 4 -#define MCP_TYPE_018 5 - -#define MCP_MAX_DEV_PER_CS 8 +#include "pinctrl-mcp23s08.h" /* Registers are all 8 bits wide. * @@ -53,31 +42,6 @@ #define MCP_GPIO 0x09 #define MCP_OLAT 0x0a -struct mcp23s08; - -struct mcp23s08 { - u8 addr; - bool irq_active_high; - bool reg_shift; - - u16 irq_rise; - u16 irq_fall; - int irq; - bool irq_controller; - int cached_gpio; - /* lock protects regmap access with bypass/cache flags */ - struct mutex lock; - - struct gpio_chip chip; - struct irq_chip irq_chip; - - struct regmap *regmap; - struct device *dev; - - struct pinctrl_dev *pctldev; - struct pinctrl_desc pinctrl_desc; -}; - static const struct reg_default mcp23x08_defaults[] = { {.reg = MCP_IODIR, .def = 0xff}, {.reg = MCP_IPOL, .def = 0x00}, @@ -109,7 +73,7 @@ static const struct regmap_access_table mcp23x08_precious_table = { .n_yes_ranges = 1, }; -static const struct regmap_config mcp23x08_regmap = { +const struct regmap_config mcp23x08_regmap = { .reg_bits = 8, .val_bits = 8, @@ -121,6 +85,7 @@ static const struct regmap_config mcp23x08_regmap = { .cache_type = REGCACHE_FLAT, .max_register = MCP_OLAT, }; +EXPORT_SYMBOL_GPL(mcp23x08_regmap); static const struct reg_default mcp23x16_defaults[] = { {.reg = MCP_IODIR << 1, .def = 0xffff}, @@ -153,7 +118,7 @@ static const struct regmap_access_table mcp23x16_precious_table = { .n_yes_ranges = 1, }; -static const struct regmap_config mcp23x17_regmap = { +const struct regmap_config mcp23x17_regmap = { .reg_bits = 8, .val_bits = 16, @@ -166,6 +131,7 @@ static const struct regmap_config mcp23x17_regmap = { .cache_type = REGCACHE_FLAT, .val_format_endian = REGMAP_ENDIAN_LITTLE, }; +EXPORT_SYMBOL_GPL(mcp23x17_regmap); static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val) { @@ -309,80 +275,6 @@ static const struct pinconf_ops mcp_pinconf_ops = { /*----------------------------------------------------------------------*/ -#ifdef CONFIG_SPI_MASTER - -static int mcp23sxx_spi_write(void *context, const void *data, size_t count) -{ - struct mcp23s08 *mcp = context; - struct spi_device *spi = to_spi_device(mcp->dev); - struct spi_message m; - struct spi_transfer t[2] = { { .tx_buf = &mcp->addr, .len = 1, }, - { .tx_buf = data, .len = count, }, }; - - spi_message_init(&m); - spi_message_add_tail(&t[0], &m); - spi_message_add_tail(&t[1], &m); - - return spi_sync(spi, &m); -} - -static int mcp23sxx_spi_gather_write(void *context, - const void *reg, size_t reg_size, - const void *val, size_t val_size) -{ - struct mcp23s08 *mcp = context; - struct spi_device *spi = to_spi_device(mcp->dev); - struct spi_message m; - struct spi_transfer t[3] = { { .tx_buf = &mcp->addr, .len = 1, }, - { .tx_buf = reg, .len = reg_size, }, - { .tx_buf = val, .len = val_size, }, }; - - spi_message_init(&m); - spi_message_add_tail(&t[0], &m); - spi_message_add_tail(&t[1], &m); - spi_message_add_tail(&t[2], &m); - - return spi_sync(spi, &m); -} - -static int mcp23sxx_spi_read(void *context, const void *reg, size_t reg_size, - void *val, size_t val_size) -{ - struct mcp23s08 *mcp = context; - struct spi_device *spi = to_spi_device(mcp->dev); - u8 tx[2]; - - if (reg_size != 1) - return -EINVAL; - - tx[0] = mcp->addr | 0x01; - tx[1] = *((u8 *) reg); - - return spi_write_then_read(spi, tx, sizeof(tx), val, val_size); -} - -static const struct regmap_bus mcp23sxx_spi_regmap = { - .write = mcp23sxx_spi_write, - .gather_write = mcp23sxx_spi_gather_write, - .read = mcp23sxx_spi_read, -}; - -#endif /* CONFIG_SPI_MASTER */ - -/*----------------------------------------------------------------------*/ - -/* A given spi_device can represent up to eight mcp23sxx chips - * sharing the same chipselect but using different addresses - * (e.g. chips #0 and #3 might be populated, but not #1 or $2). - * Driver data holds all the per-chip data. - */ -struct mcp23s08_driver_data { - unsigned ngpio; - struct mcp23s08 *mcp[8]; - struct mcp23s08 chip[]; -}; - - static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset) { struct mcp23s08 *mcp = gpiochip_get_data(chip); @@ -562,7 +454,6 @@ static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type) struct gpio_chip *gc = irq_data_get_irq_chip_data(data); struct mcp23s08 *mcp = gpiochip_get_data(gc); unsigned int pos = data->hwirq; - int status = 0; if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { mcp_set_bit(mcp, MCP_INTCON, pos, false); @@ -585,7 +476,7 @@ static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type) } else return -EINVAL; - return status; + return 0; } static void mcp23s08_irq_bus_lock(struct irq_data *data) @@ -656,21 +547,25 @@ static int mcp23s08_irqchip_setup(struct mcp23s08 *mcp) /*----------------------------------------------------------------------*/ -static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, - void *data, unsigned addr, unsigned type, - unsigned int base, int cs) +int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, + unsigned int addr, unsigned int type, unsigned int base) { int status, ret; bool mirror = false; bool open_drain = false; - struct regmap_config *one_regmap_config = NULL; - int raw_chip_address = (addr & ~0x40) >> 1; mutex_init(&mcp->lock); mcp->dev = dev; mcp->addr = addr; + mcp->irq_active_high = false; + mcp->irq_chip.name = dev_name(dev); + mcp->irq_chip.irq_mask = mcp23s08_irq_mask; + mcp->irq_chip.irq_unmask = mcp23s08_irq_unmask; + mcp->irq_chip.irq_set_type = mcp23s08_irq_set_type; + mcp->irq_chip.irq_bus_lock = mcp23s08_irq_bus_lock; + mcp->irq_chip.irq_bus_sync_unlock = mcp23s08_irq_bus_unlock; mcp->chip.direction_input = mcp23s08_direction_input; mcp->chip.get = mcp23s08_get; @@ -681,83 +576,6 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, mcp->chip.of_node = dev->of_node; #endif - switch (type) { -#ifdef CONFIG_SPI_MASTER - case MCP_TYPE_S08: - case MCP_TYPE_S17: - switch (type) { - case MCP_TYPE_S08: - one_regmap_config = - devm_kmemdup(dev, &mcp23x08_regmap, - sizeof(struct regmap_config), GFP_KERNEL); - mcp->reg_shift = 0; - mcp->chip.ngpio = 8; - mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, - "mcp23s08.%d", raw_chip_address); - break; - case MCP_TYPE_S17: - one_regmap_config = - devm_kmemdup(dev, &mcp23x17_regmap, - sizeof(struct regmap_config), GFP_KERNEL); - mcp->reg_shift = 1; - mcp->chip.ngpio = 16; - mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, - "mcp23s17.%d", raw_chip_address); - break; - } - if (!one_regmap_config) - return -ENOMEM; - - one_regmap_config->name = devm_kasprintf(dev, GFP_KERNEL, "%d", raw_chip_address); - mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, - one_regmap_config); - break; - - case MCP_TYPE_S18: - one_regmap_config = - devm_kmemdup(dev, &mcp23x17_regmap, - sizeof(struct regmap_config), GFP_KERNEL); - if (!one_regmap_config) - return -ENOMEM; - mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, - one_regmap_config); - mcp->reg_shift = 1; - mcp->chip.ngpio = 16; - mcp->chip.label = "mcp23s18"; - break; -#endif /* CONFIG_SPI_MASTER */ - -#if IS_ENABLED(CONFIG_I2C) - case MCP_TYPE_008: - mcp->regmap = devm_regmap_init_i2c(data, &mcp23x08_regmap); - mcp->reg_shift = 0; - mcp->chip.ngpio = 8; - mcp->chip.label = "mcp23008"; - break; - - case MCP_TYPE_017: - mcp->regmap = devm_regmap_init_i2c(data, &mcp23x17_regmap); - mcp->reg_shift = 1; - mcp->chip.ngpio = 16; - mcp->chip.label = "mcp23017"; - break; - - case MCP_TYPE_018: - mcp->regmap = devm_regmap_init_i2c(data, &mcp23x17_regmap); - mcp->reg_shift = 1; - mcp->chip.ngpio = 16; - mcp->chip.label = "mcp23018"; - break; -#endif /* CONFIG_I2C */ - - default: - dev_err(dev, "invalid device type (%d)\n", type); - return -EINVAL; - } - - if (IS_ERR(mcp->regmap)) - return PTR_ERR(mcp->regmap); - mcp->chip.base = base; mcp->chip.can_sleep = true; mcp->chip.parent = dev; @@ -816,14 +634,6 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, goto fail; } - if (one_regmap_config) { - mcp->pinctrl_desc.name = devm_kasprintf(dev, GFP_KERNEL, - "mcp23xxx-pinctrl.%d", raw_chip_address); - if (!mcp->pinctrl_desc.name) - return -ENOMEM; - } else { - mcp->pinctrl_desc.name = "mcp23xxx-pinctrl"; - } mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops; mcp->pinctrl_desc.confops = &mcp_pinconf_ops; mcp->pinctrl_desc.npins = mcp->chip.ngpio; @@ -847,291 +657,5 @@ fail: dev_dbg(dev, "can't setup chip %d, --> %d\n", addr, ret); return ret; } - -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_OF -#ifdef CONFIG_SPI_MASTER -static const struct of_device_id mcp23s08_spi_of_match[] = { - { - .compatible = "microchip,mcp23s08", - .data = (void *) MCP_TYPE_S08, - }, - { - .compatible = "microchip,mcp23s17", - .data = (void *) MCP_TYPE_S17, - }, - { - .compatible = "microchip,mcp23s18", - .data = (void *) MCP_TYPE_S18, - }, -/* NOTE: The use of the mcp prefix is deprecated and will be removed. */ - { - .compatible = "mcp,mcp23s08", - .data = (void *) MCP_TYPE_S08, - }, - { - .compatible = "mcp,mcp23s17", - .data = (void *) MCP_TYPE_S17, - }, - { }, -}; -MODULE_DEVICE_TABLE(of, mcp23s08_spi_of_match); -#endif - -#if IS_ENABLED(CONFIG_I2C) -static const struct of_device_id mcp23s08_i2c_of_match[] = { - { - .compatible = "microchip,mcp23008", - .data = (void *) MCP_TYPE_008, - }, - { - .compatible = "microchip,mcp23017", - .data = (void *) MCP_TYPE_017, - }, - { - .compatible = "microchip,mcp23018", - .data = (void *) MCP_TYPE_018, - }, -/* NOTE: The use of the mcp prefix is deprecated and will be removed. */ - { - .compatible = "mcp,mcp23008", - .data = (void *) MCP_TYPE_008, - }, - { - .compatible = "mcp,mcp23017", - .data = (void *) MCP_TYPE_017, - }, - { }, -}; -MODULE_DEVICE_TABLE(of, mcp23s08_i2c_of_match); -#endif -#endif /* CONFIG_OF */ - - -#if IS_ENABLED(CONFIG_I2C) - -static int mcp230xx_probe(struct i2c_client *client, - const struct i2c_device_id *id) -{ - struct mcp23s08_platform_data *pdata, local_pdata; - struct mcp23s08 *mcp; - int status; - - pdata = dev_get_platdata(&client->dev); - if (!pdata) { - pdata = &local_pdata; - pdata->base = -1; - } - - mcp = devm_kzalloc(&client->dev, sizeof(*mcp), GFP_KERNEL); - if (!mcp) - return -ENOMEM; - - mcp->irq = client->irq; - mcp->irq_chip.name = dev_name(&client->dev); - mcp->irq_chip.irq_mask = mcp23s08_irq_mask; - mcp->irq_chip.irq_unmask = mcp23s08_irq_unmask; - mcp->irq_chip.irq_set_type = mcp23s08_irq_set_type; - mcp->irq_chip.irq_bus_lock = mcp23s08_irq_bus_lock; - mcp->irq_chip.irq_bus_sync_unlock = mcp23s08_irq_bus_unlock; - - status = mcp23s08_probe_one(mcp, &client->dev, client, client->addr, - id->driver_data, pdata->base, 0); - if (status) - return status; - - i2c_set_clientdata(client, mcp); - - return 0; -} - -static const struct i2c_device_id mcp230xx_id[] = { - { "mcp23008", MCP_TYPE_008 }, - { "mcp23017", MCP_TYPE_017 }, - { "mcp23018", MCP_TYPE_018 }, - { }, -}; -MODULE_DEVICE_TABLE(i2c, mcp230xx_id); - -static struct i2c_driver mcp230xx_driver = { - .driver = { - .name = "mcp230xx", - .of_match_table = of_match_ptr(mcp23s08_i2c_of_match), - }, - .probe = mcp230xx_probe, - .id_table = mcp230xx_id, -}; - -static int __init mcp23s08_i2c_init(void) -{ - return i2c_add_driver(&mcp230xx_driver); -} - -static void mcp23s08_i2c_exit(void) -{ - i2c_del_driver(&mcp230xx_driver); -} - -#else - -static int __init mcp23s08_i2c_init(void) { return 0; } -static void mcp23s08_i2c_exit(void) { } - -#endif /* CONFIG_I2C */ - -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_SPI_MASTER - -static int mcp23s08_probe(struct spi_device *spi) -{ - struct mcp23s08_platform_data *pdata, local_pdata; - unsigned addr; - int chips = 0; - struct mcp23s08_driver_data *data; - int status, type; - unsigned ngpio = 0; - const struct of_device_id *match; - - match = of_match_device(of_match_ptr(mcp23s08_spi_of_match), &spi->dev); - if (match) - type = (int)(uintptr_t)match->data; - else - type = spi_get_device_id(spi)->driver_data; - - pdata = dev_get_platdata(&spi->dev); - if (!pdata) { - pdata = &local_pdata; - pdata->base = -1; - - status = device_property_read_u32(&spi->dev, - "microchip,spi-present-mask", &pdata->spi_present_mask); - if (status) { - status = device_property_read_u32(&spi->dev, - "mcp,spi-present-mask", - &pdata->spi_present_mask); - - if (status) { - dev_err(&spi->dev, "missing spi-present-mask"); - return -ENODEV; - } - } - } - - if (!pdata->spi_present_mask || pdata->spi_present_mask > 0xff) { - dev_err(&spi->dev, "invalid spi-present-mask"); - return -ENODEV; - } - - for (addr = 0; addr < MCP_MAX_DEV_PER_CS; addr++) { - if (pdata->spi_present_mask & BIT(addr)) - chips++; - } - - if (!chips) - return -ENODEV; - - data = devm_kzalloc(&spi->dev, - struct_size(data, chip, chips), GFP_KERNEL); - if (!data) - return -ENOMEM; - - spi_set_drvdata(spi, data); - - for (addr = 0; addr < MCP_MAX_DEV_PER_CS; addr++) { - if (!(pdata->spi_present_mask & BIT(addr))) - continue; - chips--; - data->mcp[addr] = &data->chip[chips]; - data->mcp[addr]->irq = spi->irq; - data->mcp[addr]->irq_chip.name = dev_name(&spi->dev); - data->mcp[addr]->irq_chip.irq_mask = mcp23s08_irq_mask; - data->mcp[addr]->irq_chip.irq_unmask = mcp23s08_irq_unmask; - data->mcp[addr]->irq_chip.irq_set_type = mcp23s08_irq_set_type; - data->mcp[addr]->irq_chip.irq_bus_lock = mcp23s08_irq_bus_lock; - data->mcp[addr]->irq_chip.irq_bus_sync_unlock = - mcp23s08_irq_bus_unlock; - status = mcp23s08_probe_one(data->mcp[addr], &spi->dev, spi, - 0x40 | (addr << 1), type, - pdata->base, addr); - if (status < 0) - return status; - - if (pdata->base != -1) - pdata->base += data->mcp[addr]->chip.ngpio; - ngpio += data->mcp[addr]->chip.ngpio; - } - data->ngpio = ngpio; - - return 0; -} - -static const struct spi_device_id mcp23s08_ids[] = { - { "mcp23s08", MCP_TYPE_S08 }, - { "mcp23s17", MCP_TYPE_S17 }, - { "mcp23s18", MCP_TYPE_S18 }, - { }, -}; -MODULE_DEVICE_TABLE(spi, mcp23s08_ids); - -static struct spi_driver mcp23s08_driver = { - .probe = mcp23s08_probe, - .id_table = mcp23s08_ids, - .driver = { - .name = "mcp23s08", - .of_match_table = of_match_ptr(mcp23s08_spi_of_match), - }, -}; - -static int __init mcp23s08_spi_init(void) -{ - return spi_register_driver(&mcp23s08_driver); -} - -static void mcp23s08_spi_exit(void) -{ - spi_unregister_driver(&mcp23s08_driver); -} - -#else - -static int __init mcp23s08_spi_init(void) { return 0; } -static void mcp23s08_spi_exit(void) { } - -#endif /* CONFIG_SPI_MASTER */ - -/*----------------------------------------------------------------------*/ - -static int __init mcp23s08_init(void) -{ - int ret; - - ret = mcp23s08_spi_init(); - if (ret) - goto spi_fail; - - ret = mcp23s08_i2c_init(); - if (ret) - goto i2c_fail; - - return 0; - - i2c_fail: - mcp23s08_spi_exit(); - spi_fail: - return ret; -} -/* register after spi/i2c postcore initcall and before - * subsys initcalls that may rely on these GPIOs - */ -subsys_initcall(mcp23s08_init); - -static void __exit mcp23s08_exit(void) -{ - mcp23s08_spi_exit(); - mcp23s08_i2c_exit(); -} -module_exit(mcp23s08_exit); - +EXPORT_SYMBOL_GPL(mcp23s08_probe_one); MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/pinctrl-mcp23s08.h b/drivers/pinctrl/pinctrl-mcp23s08.h new file mode 100644 index 000000000000..90dc27081a3c --- /dev/null +++ b/drivers/pinctrl/pinctrl-mcp23s08.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* MCP23S08 SPI/I2C GPIO driver */ + +#include +#include +#include +#include +#include + +/* + * MCP types supported by driver + */ +#define MCP_TYPE_S08 1 +#define MCP_TYPE_S17 2 +#define MCP_TYPE_008 3 +#define MCP_TYPE_017 4 +#define MCP_TYPE_S18 5 +#define MCP_TYPE_018 6 + +struct device; +struct regmap; + +struct pinctrl_dev; + +struct mcp23s08 { + u8 addr; + bool irq_active_high; + bool reg_shift; + + u16 irq_rise; + u16 irq_fall; + int irq; + bool irq_controller; + int cached_gpio; + /* lock protects regmap access with bypass/cache flags */ + struct mutex lock; + + struct gpio_chip chip; + struct irq_chip irq_chip; + + struct regmap *regmap; + struct device *dev; + + struct pinctrl_dev *pctldev; + struct pinctrl_desc pinctrl_desc; +}; + +extern const struct regmap_config mcp23x08_regmap; +extern const struct regmap_config mcp23x17_regmap; + +int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, + unsigned int addr, unsigned int type, unsigned int base); diff --git a/drivers/pinctrl/pinctrl-mcp23s08_i2c.c b/drivers/pinctrl/pinctrl-mcp23s08_i2c.c new file mode 100644 index 000000000000..e0b001c8c08c --- /dev/null +++ b/drivers/pinctrl/pinctrl-mcp23s08_i2c.c @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* MCP23S08 I2C GPIO driver */ + +#include +#include +#include +#include + +#include "pinctrl-mcp23s08.h" + +static int mcp230xx_probe(struct i2c_client *client, const struct i2c_device_id *id) +{ + struct device *dev = &client->dev; + unsigned int type = id->driver_data; + struct mcp23s08 *mcp; + int ret; + + mcp = devm_kzalloc(dev, sizeof(*mcp), GFP_KERNEL); + if (!mcp) + return -ENOMEM; + + switch (type) { + case MCP_TYPE_008: + mcp->regmap = devm_regmap_init_i2c(client, &mcp23x08_regmap); + mcp->reg_shift = 0; + mcp->chip.ngpio = 8; + mcp->chip.label = "mcp23008"; + break; + + case MCP_TYPE_017: + mcp->regmap = devm_regmap_init_i2c(client, &mcp23x17_regmap); + mcp->reg_shift = 1; + mcp->chip.ngpio = 16; + mcp->chip.label = "mcp23017"; + break; + + case MCP_TYPE_018: + mcp->regmap = devm_regmap_init_i2c(client, &mcp23x17_regmap); + mcp->reg_shift = 1; + mcp->chip.ngpio = 16; + mcp->chip.label = "mcp23018"; + break; + + default: + dev_err(dev, "invalid device type (%d)\n", type); + return -EINVAL; + } + + if (IS_ERR(mcp->regmap)) + return PTR_ERR(mcp->regmap); + + mcp->irq = client->irq; + mcp->pinctrl_desc.name = "mcp23xxx-pinctrl"; + + ret = mcp23s08_probe_one(mcp, dev, client->addr, type, -1); + if (ret) + return ret; + + i2c_set_clientdata(client, mcp); + + return 0; +} + +static const struct i2c_device_id mcp230xx_id[] = { + { "mcp23008", MCP_TYPE_008 }, + { "mcp23017", MCP_TYPE_017 }, + { "mcp23018", MCP_TYPE_018 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, mcp230xx_id); + +static const struct of_device_id mcp23s08_i2c_of_match[] = { + { + .compatible = "microchip,mcp23008", + .data = (void *) MCP_TYPE_008, + }, + { + .compatible = "microchip,mcp23017", + .data = (void *) MCP_TYPE_017, + }, + { + .compatible = "microchip,mcp23018", + .data = (void *) MCP_TYPE_018, + }, +/* NOTE: The use of the mcp prefix is deprecated and will be removed. */ + { + .compatible = "mcp,mcp23008", + .data = (void *) MCP_TYPE_008, + }, + { + .compatible = "mcp,mcp23017", + .data = (void *) MCP_TYPE_017, + }, + { } +}; +MODULE_DEVICE_TABLE(of, mcp23s08_i2c_of_match); + +static struct i2c_driver mcp230xx_driver = { + .driver = { + .name = "mcp230xx", + .of_match_table = mcp23s08_i2c_of_match, + }, + .probe = mcp230xx_probe, + .id_table = mcp230xx_id, +}; + +static int __init mcp23s08_i2c_init(void) +{ + return i2c_add_driver(&mcp230xx_driver); +} + +/* + * Register after I²C postcore initcall and before + * subsys initcalls that may rely on these GPIOs. + */ +subsys_initcall(mcp23s08_i2c_init); + +static void mcp23s08_i2c_exit(void) +{ + i2c_del_driver(&mcp230xx_driver); +} +module_exit(mcp23s08_i2c_exit); + +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/pinctrl-mcp23s08_spi.c b/drivers/pinctrl/pinctrl-mcp23s08_spi.c new file mode 100644 index 000000000000..e06fb885fd2b --- /dev/null +++ b/drivers/pinctrl/pinctrl-mcp23s08_spi.c @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* MCP23S08 SPI GPIO driver */ + +#include +#include +#include +#include +#include + +#include "pinctrl-mcp23s08.h" + +#define MCP_MAX_DEV_PER_CS 8 + +/* + * A given spi_device can represent up to eight mcp23sxx chips + * sharing the same chipselect but using different addresses + * (e.g. chips #0 and #3 might be populated, but not #1 or #2). + * Driver data holds all the per-chip data. + */ +struct mcp23s08_driver_data { + unsigned ngpio; + struct mcp23s08 *mcp[8]; + struct mcp23s08 chip[]; +}; + +static int mcp23sxx_spi_write(void *context, const void *data, size_t count) +{ + struct mcp23s08 *mcp = context; + struct spi_device *spi = to_spi_device(mcp->dev); + struct spi_message m; + struct spi_transfer t[2] = { { .tx_buf = &mcp->addr, .len = 1, }, + { .tx_buf = data, .len = count, }, }; + + spi_message_init(&m); + spi_message_add_tail(&t[0], &m); + spi_message_add_tail(&t[1], &m); + + return spi_sync(spi, &m); +} + +static int mcp23sxx_spi_gather_write(void *context, + const void *reg, size_t reg_size, + const void *val, size_t val_size) +{ + struct mcp23s08 *mcp = context; + struct spi_device *spi = to_spi_device(mcp->dev); + struct spi_message m; + struct spi_transfer t[3] = { { .tx_buf = &mcp->addr, .len = 1, }, + { .tx_buf = reg, .len = reg_size, }, + { .tx_buf = val, .len = val_size, }, }; + + spi_message_init(&m); + spi_message_add_tail(&t[0], &m); + spi_message_add_tail(&t[1], &m); + spi_message_add_tail(&t[2], &m); + + return spi_sync(spi, &m); +} + +static int mcp23sxx_spi_read(void *context, const void *reg, size_t reg_size, + void *val, size_t val_size) +{ + struct mcp23s08 *mcp = context; + struct spi_device *spi = to_spi_device(mcp->dev); + u8 tx[2]; + + if (reg_size != 1) + return -EINVAL; + + tx[0] = mcp->addr | 0x01; + tx[1] = *((u8 *) reg); + + return spi_write_then_read(spi, tx, sizeof(tx), val, val_size); +} + +static const struct regmap_bus mcp23sxx_spi_regmap = { + .write = mcp23sxx_spi_write, + .gather_write = mcp23sxx_spi_gather_write, + .read = mcp23sxx_spi_read, +}; + +static int mcp23s08_spi_regmap_init(struct mcp23s08 *mcp, struct device *dev, + unsigned int addr, unsigned int type) +{ + const struct regmap_config *config; + struct regmap_config *copy; + const char *name; + + switch (type) { + case MCP_TYPE_S08: + mcp->reg_shift = 0; + mcp->chip.ngpio = 8; + mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, "mcp23s08.%d", addr); + + config = &mcp23x08_regmap; + name = devm_kasprintf(dev, GFP_KERNEL, "%d", addr); + break; + + case MCP_TYPE_S17: + mcp->reg_shift = 1; + mcp->chip.ngpio = 16; + mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, "mcp23s17.%d", addr); + + config = &mcp23x17_regmap; + name = devm_kasprintf(dev, GFP_KERNEL, "%d", addr); + break; + + case MCP_TYPE_S18: + mcp->reg_shift = 1; + mcp->chip.ngpio = 16; + mcp->chip.label = "mcp23s18"; + + config = &mcp23x17_regmap; + name = config->name; + break; + + default: + dev_err(dev, "invalid device type (%d)\n", type); + return -EINVAL; + } + + copy = devm_kmemdup(dev, &config, sizeof(config), GFP_KERNEL); + if (!copy) + return -ENOMEM; + + copy->name = name; + + mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, copy); + if (IS_ERR(mcp->regmap)) + return PTR_ERR(mcp->regmap); + + return 0; +} + +static int mcp23s08_probe(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + struct mcp23s08_driver_data *data; + unsigned long spi_present_mask; + const void *match; + unsigned int addr; + unsigned int ngpio = 0; + int chips; + int type; + int ret; + u32 v; + + match = device_get_match_data(dev); + if (match) + type = (int)(uintptr_t)match; + else + type = spi_get_device_id(spi)->driver_data; + + ret = device_property_read_u32(dev, "microchip,spi-present-mask", &v); + if (ret) { + ret = device_property_read_u32(dev, "mcp,spi-present-mask", &v); + if (ret) { + dev_err(dev, "missing spi-present-mask"); + return ret; + } + } + spi_present_mask = v; + + if (!spi_present_mask || spi_present_mask >= BIT(MCP_MAX_DEV_PER_CS)) { + dev_err(dev, "invalid spi-present-mask"); + return -ENODEV; + } + + chips = hweight_long(spi_present_mask); + + data = devm_kzalloc(dev, struct_size(data, chip, chips), GFP_KERNEL); + if (!data) + return -ENOMEM; + + spi_set_drvdata(spi, data); + + for_each_set_bit(addr, &spi_present_mask, MCP_MAX_DEV_PER_CS) { + data->mcp[addr] = &data->chip[--chips]; + data->mcp[addr]->irq = spi->irq; + + ret = mcp23s08_spi_regmap_init(data->mcp[addr], dev, addr, type); + if (ret) + return ret; + + data->mcp[addr]->pinctrl_desc.name = devm_kasprintf(dev, GFP_KERNEL, + "mcp23xxx-pinctrl.%d", + addr); + if (!data->mcp[addr]->pinctrl_desc.name) + return -ENOMEM; + + ret = mcp23s08_probe_one(data->mcp[addr], dev, 0x40 | (addr << 1), type, -1); + if (ret < 0) + return ret; + + ngpio += data->mcp[addr]->chip.ngpio; + } + data->ngpio = ngpio; + + return 0; +} + +static const struct spi_device_id mcp23s08_ids[] = { + { "mcp23s08", MCP_TYPE_S08 }, + { "mcp23s17", MCP_TYPE_S17 }, + { "mcp23s18", MCP_TYPE_S18 }, + { } +}; +MODULE_DEVICE_TABLE(spi, mcp23s08_ids); + +static const struct of_device_id mcp23s08_spi_of_match[] = { + { + .compatible = "microchip,mcp23s08", + .data = (void *) MCP_TYPE_S08, + }, + { + .compatible = "microchip,mcp23s17", + .data = (void *) MCP_TYPE_S17, + }, + { + .compatible = "microchip,mcp23s18", + .data = (void *) MCP_TYPE_S18, + }, +/* NOTE: The use of the mcp prefix is deprecated and will be removed. */ + { + .compatible = "mcp,mcp23s08", + .data = (void *) MCP_TYPE_S08, + }, + { + .compatible = "mcp,mcp23s17", + .data = (void *) MCP_TYPE_S17, + }, + { } +}; +MODULE_DEVICE_TABLE(of, mcp23s08_spi_of_match); + +static struct spi_driver mcp23s08_driver = { + .probe = mcp23s08_probe, + .id_table = mcp23s08_ids, + .driver = { + .name = "mcp23s08", + .of_match_table = mcp23s08_spi_of_match, + }, +}; + +static int __init mcp23s08_spi_init(void) +{ + return spi_register_driver(&mcp23s08_driver); +} + +/* + * Register after SPI postcore initcall and before + * subsys initcalls that may rely on these GPIOs. + */ +subsys_initcall(mcp23s08_spi_init); + +static void mcp23s08_spi_exit(void) +{ + spi_unregister_driver(&mcp23s08_driver); +} +module_exit(mcp23s08_spi_exit); + +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index ed8eac6c1494..95c225bc7572 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -46,32 +46,15 @@ enum { FUNC_IRQ0_OUT, FUNC_IRQ1_IN, FUNC_IRQ1_OUT, - FUNC_MIIM1, - FUNC_MIIM2, + FUNC_MIIM, FUNC_PCI_WAKE, FUNC_PTP0, FUNC_PTP1, FUNC_PTP2, FUNC_PTP3, FUNC_PWM, - FUNC_RECO_CLK0, - FUNC_RECO_CLK1, - FUNC_SFP0, - FUNC_SFP1, - FUNC_SFP2, - FUNC_SFP3, - FUNC_SFP4, - FUNC_SFP5, - FUNC_SFP6, - FUNC_SFP7, - FUNC_SFP8, - FUNC_SFP9, - FUNC_SFP10, - FUNC_SFP11, - FUNC_SFP12, - FUNC_SFP13, - FUNC_SFP14, - FUNC_SFP15, + FUNC_RECO_CLK, + FUNC_SFP, FUNC_SG0, FUNC_SG1, FUNC_SG2, @@ -92,32 +75,15 @@ static const char *const ocelot_function_names[] = { [FUNC_IRQ0_OUT] = "irq0_out", [FUNC_IRQ1_IN] = "irq1_in", [FUNC_IRQ1_OUT] = "irq1_out", - [FUNC_MIIM1] = "miim1", - [FUNC_MIIM2] = "miim2", + [FUNC_MIIM] = "miim", [FUNC_PCI_WAKE] = "pci_wake", [FUNC_PTP0] = "ptp0", [FUNC_PTP1] = "ptp1", [FUNC_PTP2] = "ptp2", [FUNC_PTP3] = "ptp3", [FUNC_PWM] = "pwm", - [FUNC_RECO_CLK0] = "reco_clk0", - [FUNC_RECO_CLK1] = "reco_clk1", - [FUNC_SFP0] = "sfp0", - [FUNC_SFP1] = "sfp1", - [FUNC_SFP2] = "sfp2", - [FUNC_SFP3] = "sfp3", - [FUNC_SFP4] = "sfp4", - [FUNC_SFP5] = "sfp5", - [FUNC_SFP6] = "sfp6", - [FUNC_SFP7] = "sfp7", - [FUNC_SFP8] = "sfp8", - [FUNC_SFP9] = "sfp9", - [FUNC_SFP10] = "sfp10", - [FUNC_SFP11] = "sfp11", - [FUNC_SFP12] = "sfp12", - [FUNC_SFP13] = "sfp13", - [FUNC_SFP14] = "sfp14", - [FUNC_SFP15] = "sfp15", + [FUNC_RECO_CLK] = "reco_clk", + [FUNC_SFP] = "sfp", [FUNC_SG0] = "sg0", [FUNC_SG1] = "sg1", [FUNC_SG2] = "sg2", @@ -168,18 +134,18 @@ OCELOT_P(6, UART, TWI_SCL_M, NONE); OCELOT_P(7, UART, TWI_SCL_M, NONE); OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT); OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT); -OCELOT_P(10, PTP2, TWI_SCL_M, SFP0); -OCELOT_P(11, PTP3, TWI_SCL_M, SFP1); -OCELOT_P(12, UART2, TWI_SCL_M, SFP2); -OCELOT_P(13, UART2, TWI_SCL_M, SFP3); -OCELOT_P(14, MIIM1, TWI_SCL_M, SFP4); -OCELOT_P(15, MIIM1, TWI_SCL_M, SFP5); +OCELOT_P(10, PTP2, TWI_SCL_M, SFP); +OCELOT_P(11, PTP3, TWI_SCL_M, SFP); +OCELOT_P(12, UART2, TWI_SCL_M, SFP); +OCELOT_P(13, UART2, TWI_SCL_M, SFP); +OCELOT_P(14, MIIM, TWI_SCL_M, SFP); +OCELOT_P(15, MIIM, TWI_SCL_M, SFP); OCELOT_P(16, TWI, NONE, SI); OCELOT_P(17, TWI, TWI_SCL_M, SI); OCELOT_P(18, PTP0, TWI_SCL_M, NONE); OCELOT_P(19, PTP1, TWI_SCL_M, NONE); -OCELOT_P(20, RECO_CLK0, TACHO, NONE); -OCELOT_P(21, RECO_CLK1, PWM, NONE); +OCELOT_P(20, RECO_CLK, TACHO, TWI_SCL_M); +OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M); #define OCELOT_PIN(n) { \ .number = n, \ @@ -264,22 +230,22 @@ JAGUAR2_P(40, NONE, TWI_SCL_M); JAGUAR2_P(41, NONE, TWI_SCL_M); JAGUAR2_P(42, NONE, TWI_SCL_M); JAGUAR2_P(43, NONE, TWI_SCL_M); -JAGUAR2_P(44, NONE, SFP8); -JAGUAR2_P(45, NONE, SFP9); -JAGUAR2_P(46, NONE, SFP10); -JAGUAR2_P(47, NONE, SFP11); -JAGUAR2_P(48, SFP0, NONE); -JAGUAR2_P(49, SFP1, SI); -JAGUAR2_P(50, SFP2, SI); -JAGUAR2_P(51, SFP3, SI); -JAGUAR2_P(52, SFP4, NONE); -JAGUAR2_P(53, SFP5, NONE); -JAGUAR2_P(54, SFP6, NONE); -JAGUAR2_P(55, SFP7, NONE); -JAGUAR2_P(56, MIIM1, SFP12); -JAGUAR2_P(57, MIIM1, SFP13); -JAGUAR2_P(58, MIIM2, SFP14); -JAGUAR2_P(59, MIIM2, SFP15); +JAGUAR2_P(44, NONE, SFP); +JAGUAR2_P(45, NONE, SFP); +JAGUAR2_P(46, NONE, SFP); +JAGUAR2_P(47, NONE, SFP); +JAGUAR2_P(48, SFP, NONE); +JAGUAR2_P(49, SFP, SI); +JAGUAR2_P(50, SFP, SI); +JAGUAR2_P(51, SFP, SI); +JAGUAR2_P(52, SFP, NONE); +JAGUAR2_P(53, SFP, NONE); +JAGUAR2_P(54, SFP, NONE); +JAGUAR2_P(55, SFP, NONE); +JAGUAR2_P(56, MIIM, SFP); +JAGUAR2_P(57, MIIM, SFP); +JAGUAR2_P(58, MIIM, SFP); +JAGUAR2_P(59, MIIM, SFP); JAGUAR2_P(60, NONE, NONE); JAGUAR2_P(61, NONE, NONE); JAGUAR2_P(62, NONE, NONE); @@ -714,11 +680,12 @@ static void ocelot_irq_handler(struct irq_desc *desc) struct irq_chip *parent_chip = irq_desc_get_chip(desc); struct gpio_chip *chip = irq_desc_get_handler_data(desc); struct ocelot_pinctrl *info = gpiochip_get_data(chip); + unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride; unsigned int reg = 0, irq, i; unsigned long irqs; for (i = 0; i < info->stride; i++) { - regmap_read(info->map, OCELOT_GPIO_INTR_IDENT + 4 * i, ®); + regmap_read(info->map, id_reg + 4 * i, ®); if (!reg) continue; @@ -751,21 +718,21 @@ static int ocelot_gpiochip_register(struct platform_device *pdev, gc->of_node = info->dev->of_node; gc->label = "ocelot-gpio"; - irq = irq_of_parse_and_map(pdev->dev.of_node, 0); - if (irq <= 0) - return irq; - - girq = &gc->irq; - girq->chip = &ocelot_irqchip; - girq->parent_handler = ocelot_irq_handler; - girq->num_parents = 1; - girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), - GFP_KERNEL); - if (!girq->parents) - return -ENOMEM; - girq->parents[0] = irq; - girq->default_type = IRQ_TYPE_NONE; - girq->handler = handle_edge_irq; + irq = irq_of_parse_and_map(gc->of_node, 0); + if (irq) { + girq = &gc->irq; + girq->chip = &ocelot_irqchip; + girq->parent_handler = ocelot_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(&pdev->dev, 1, + sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + girq->parents[0] = irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_edge_irq; + } ret = devm_gpiochip_add_data(&pdev->dev, gc, info); if (ret) diff --git a/drivers/pinctrl/pinctrl-rk805.c b/drivers/pinctrl/pinctrl-rk805.c index cccbe072274e..c6f4229eb106 100644 --- a/drivers/pinctrl/pinctrl-rk805.c +++ b/drivers/pinctrl/pinctrl-rk805.c @@ -73,7 +73,7 @@ struct rk805_pctrl_info { int num_pin_groups; const struct pinctrl_pin_desc *pins; unsigned int num_pins; - struct rk805_pin_config *pin_cfg; + const struct rk805_pin_config *pin_cfg; }; enum rk805_pinmux_option { @@ -121,7 +121,7 @@ static const struct rk805_pin_group rk805_pin_groups[] = { #define RK805_GPIO0_VAL_MSK BIT(0) #define RK805_GPIO1_VAL_MSK BIT(1) -static struct rk805_pin_config rk805_gpio_cfgs[] = { +static const struct rk805_pin_config rk805_gpio_cfgs[] = { { .reg = RK805_OUT_REG, .val_msk = RK805_GPIO0_VAL_MSK, diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 098951346339..c07324d1f265 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -508,8 +508,8 @@ static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, } map_num += grp->npins; - new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map), - GFP_KERNEL); + + new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL); if (!new_map) return -ENOMEM; @@ -519,7 +519,7 @@ static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, /* create mux map */ parent = of_get_parent(np); if (!parent) { - devm_kfree(pctldev->dev, new_map); + kfree(new_map); return -EINVAL; } new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; @@ -546,6 +546,7 @@ static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, struct pinctrl_map *map, unsigned num_maps) { + kfree(map); } static const struct pinctrl_ops rockchip_pctrl_ops = { @@ -2940,14 +2941,14 @@ static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, sizeof(struct rockchip_pmx_func), GFP_KERNEL); if (!info->functions) - return -EINVAL; + return -ENOMEM; info->groups = devm_kcalloc(dev, info->ngroups, sizeof(struct rockchip_pin_group), GFP_KERNEL); if (!info->groups) - return -EINVAL; + return -ENOMEM; i = 0; diff --git a/drivers/pinctrl/pinctrl-rza1.c b/drivers/pinctrl/pinctrl-rza1.c index da2d8365c690..38a14bbced5f 100644 --- a/drivers/pinctrl/pinctrl-rza1.c +++ b/drivers/pinctrl/pinctrl-rza1.c @@ -93,7 +93,7 @@ struct rza1_bidir_entry { }; /** - * rza1_swio_pin - describe a single pin that needs bidir flag applied. + * rza1_swio_pin - describe a single pin that needs swio flag applied. */ struct rza1_swio_pin { u16 pin: 4; @@ -418,7 +418,7 @@ static const struct rza1_bidir_entry rza1l_bidir_entries[RZA1_NPORTS] = { }; static const struct rza1_swio_entry rza1l_swio_entries[] = { - [0] = { ARRAY_SIZE(rza1h_swio_pins), rza1h_swio_pins }, + [0] = { ARRAY_SIZE(rza1l_swio_pins), rza1l_swio_pins }, }; /* RZ/A1L (r7s72102x) pinmux flags table */ diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c index 60100b45f5e5..1aae803c12cd 100644 --- a/drivers/pinctrl/pinctrl-stmfx.c +++ b/drivers/pinctrl/pinctrl-stmfx.c @@ -288,7 +288,7 @@ static int stmfx_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, struct pinctrl_gpio_range *range; enum pin_config_param param; u32 arg; - int dir, i, ret; + int i, ret; range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); if (!range) { @@ -296,10 +296,6 @@ static int stmfx_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, return -EINVAL; } - dir = stmfx_gpio_get_direction(&pctl->gpio_chip, pin); - if (dir < 0) - return dir; - for (i = 0; i < num_configs; i++) { param = pinconf_to_config_param(configs[i]); arg = pinconf_to_config_argument(configs[i]); diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c index 6e74bd87d959..708bc91862fe 100644 --- a/drivers/pinctrl/pinctrl-sx150x.c +++ b/drivers/pinctrl/pinctrl-sx150x.c @@ -988,7 +988,7 @@ static unsigned int sx150x_maybe_swizzle(struct sx150x_pinctrl *pctl, /* * In order to mask the differences between 16 and 8 bit expander * devices we set up a sligthly ficticious regmap that pretends to be - * a set of 32-bit (to accomodate RegSenseLow/RegSenseHigh + * a set of 32-bit (to accommodate RegSenseLow/RegSenseHigh * pair/quartet) registers and transparently reconstructs those * registers via multiple I2C/SMBus reads * diff --git a/drivers/pinctrl/pxa/pinctrl-pxa2xx.c b/drivers/pinctrl/pxa/pinctrl-pxa2xx.c index bddf2c5dd3bf..eab029a21643 100644 --- a/drivers/pinctrl/pxa/pinctrl-pxa2xx.c +++ b/drivers/pinctrl/pxa/pinctrl-pxa2xx.c @@ -425,15 +425,6 @@ int pxa2xx_pinctrl_init(struct platform_device *pdev, } EXPORT_SYMBOL_GPL(pxa2xx_pinctrl_init); -int pxa2xx_pinctrl_exit(struct platform_device *pdev) -{ - struct pxa_pinctrl *pctl = platform_get_drvdata(pdev); - - pinctrl_unregister(pctl->pctl_dev); - return 0; -} -EXPORT_SYMBOL_GPL(pxa2xx_pinctrl_exit); - MODULE_AUTHOR("Robert Jarzmik "); MODULE_DESCRIPTION("Marvell PXA2xx pinctrl driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 332202c23497..765a6c98d71b 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -237,4 +237,13 @@ config PINCTRL_SM8150 Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM8150 platform. +config PINCTRL_SM8250 + tristate "Qualcomm Technologies Inc SM8250 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SM8250 platform. + endif diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index d9e09045a776..061ec9fb659b 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -26,3 +26,4 @@ obj-$(CONFIG_PINCTRL_SC7180) += pinctrl-sc7180.o obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o +obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index d31d25f0bf23..54a226f682e9 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -23,7 +23,6 @@ #include #include #include -#include #include diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250.c b/drivers/pinctrl/qcom/pinctrl-sm8250.c new file mode 100644 index 000000000000..a660f1274b66 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8250.c @@ -0,0 +1,1361 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +static const char * const sm8250_tiles[] = { + "west", + "south", + "north", +}; + +enum { + WEST, + SOUTH, + NORTH, +}; + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define REG_SIZE 0x1000 +#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = REG_SIZE * id + 0x4, \ + .intr_cfg_reg = REG_SIZE * id + 0x8, \ + .intr_status_reg = REG_SIZE * id + 0xc, \ + .intr_target_reg = REG_SIZE * id + 0x8, \ + .tile = _tile, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .tile = NORTH, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .tile = SOUTH, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc sm8250_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + PINCTRL_PIN(173, "GPIO_173"), + PINCTRL_PIN(174, "GPIO_174"), + PINCTRL_PIN(175, "GPIO_175"), + PINCTRL_PIN(176, "GPIO_176"), + PINCTRL_PIN(177, "GPIO_177"), + PINCTRL_PIN(178, "GPIO_178"), + PINCTRL_PIN(179, "GPIO_179"), + PINCTRL_PIN(180, "SDC2_CLK"), + PINCTRL_PIN(181, "SDC2_CMD"), + PINCTRL_PIN(182, "SDC2_DATA"), + PINCTRL_PIN(183, "UFS_RESET"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); +DECLARE_MSM_GPIO_PINS(166); +DECLARE_MSM_GPIO_PINS(167); +DECLARE_MSM_GPIO_PINS(168); +DECLARE_MSM_GPIO_PINS(169); +DECLARE_MSM_GPIO_PINS(170); +DECLARE_MSM_GPIO_PINS(171); +DECLARE_MSM_GPIO_PINS(172); +DECLARE_MSM_GPIO_PINS(173); +DECLARE_MSM_GPIO_PINS(174); +DECLARE_MSM_GPIO_PINS(175); +DECLARE_MSM_GPIO_PINS(176); +DECLARE_MSM_GPIO_PINS(177); +DECLARE_MSM_GPIO_PINS(178); +DECLARE_MSM_GPIO_PINS(179); + +static const unsigned int ufs_reset_pins[] = { 180 }; +static const unsigned int sdc2_clk_pins[] = { 181 }; +static const unsigned int sdc2_cmd_pins[] = { 182 }; +static const unsigned int sdc2_data_pins[] = { 183 }; + +enum sm8250_functions { + msm_mux_aoss_cti, + msm_mux_atest, + msm_mux_audio_ref, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_dp_hot, + msm_mux_dp_lcd, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gpio, + msm_mux_ibi_i3c, + msm_mux_jitter_bist, + msm_mux_lpass_slimbus, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0, + msm_mux_mdp_vsync1, + msm_mux_mdp_vsync2, + msm_mux_mdp_vsync3, + msm_mux_mi2s0_data0, + msm_mux_mi2s0_data1, + msm_mux_mi2s0_sck, + msm_mux_mi2s0_ws, + msm_mux_mi2s1_data0, + msm_mux_mi2s1_data1, + msm_mux_mi2s1_sck, + msm_mux_mi2s1_ws, + msm_mux_mi2s2_data0, + msm_mux_mi2s2_data1, + msm_mux_mi2s2_sck, + msm_mux_mi2s2_ws, + msm_mux_pci_e0, + msm_mux_pci_e1, + msm_mux_pci_e2, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_bypassnl, + msm_mux_pll_clk, + msm_mux_pll_reset, + msm_mux_pri_mi2s, + msm_mux_prng_rosc, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qspi0, + msm_mux_qspi1, + msm_mux_qspi2, + msm_mux_qspi3, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qup0, + msm_mux_qup1, + msm_mux_qup10, + msm_mux_qup11, + msm_mux_qup12, + msm_mux_qup13, + msm_mux_qup14, + msm_mux_qup15, + msm_mux_qup16, + msm_mux_qup17, + msm_mux_qup18, + msm_mux_qup19, + msm_mux_qup2, + msm_mux_qup3, + msm_mux_qup4, + msm_mux_qup5, + msm_mux_qup6, + msm_mux_qup7, + msm_mux_qup8, + msm_mux_qup9, + msm_mux_qup_l4, + msm_mux_qup_l5, + msm_mux_qup_l6, + msm_mux_sd_write, + msm_mux_sdc40, + msm_mux_sdc41, + msm_mux_sdc42, + msm_mux_sdc43, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sec_mi2s, + msm_mux_sp_cmu, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_tgu_ch2, + msm_mux_tgu_ch3, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_tsif0_clk, + msm_mux_tsif0_data, + msm_mux_tsif0_en, + msm_mux_tsif0_error, + msm_mux_tsif0_sync, + msm_mux_tsif1_clk, + msm_mux_tsif1_data, + msm_mux_tsif1_en, + msm_mux_tsif1_error, + msm_mux_tsif1_sync, + msm_mux_usb2phy_ac, + msm_mux_usb_phy, + msm_mux_vsense_trigger, + msm_mux__, +}; + +static const char * const tsif1_data_groups[] = { + "gpio75", +}; +static const char * const sdc41_groups[] = { + "gpio75", +}; +static const char * const tsif1_sync_groups[] = { + "gpio76", +}; +static const char * const sdc40_groups[] = { + "gpio76", +}; +static const char * const aoss_cti_groups[] = { + "gpio77", +}; +static const char * const phase_flag_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51", + "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio103", "gpio104", "gpio115", "gpio116", "gpio117", "gpio118", + "gpio119", "gpio120", "gpio122", "gpio124", "gpio125", +}; +static const char * const sd_write_groups[] = { + "gpio78", +}; +static const char * const pci_e0_groups[] = { + "gpio79", "gpio80", +}; +static const char * const pci_e1_groups[] = { + "gpio82", "gpio83", +}; +static const char * const pci_e2_groups[] = { + "gpio85", "gpio86", +}; +static const char * const tgu_ch0_groups[] = { + "gpio85", +}; +static const char * const atest_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", "gpio32", "gpio33", "gpio34", + "gpio35", "gpio36", "gpio37", "gpio85", "gpio86", "gpio87", "gpio88", + "gpio89", +}; +static const char * const tgu_ch3_groups[] = { + "gpio86", +}; +static const char * const tsif1_error_groups[] = { + "gpio90", +}; +static const char * const tgu_ch1_groups[] = { + "gpio90", +}; +static const char * const tsif0_error_groups[] = { + "gpio91", +}; +static const char * const tgu_ch2_groups[] = { + "gpio91", +}; +static const char * const cam_mclk_groups[] = { + "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", +}; +static const char * const ddr_bist_groups[] = { + "gpio94", "gpio95", "gpio143", "gpio144", +}; +static const char * const pll_bypassnl_groups[] = { + "gpio96", +}; +static const char * const pll_reset_groups[] = { + "gpio97", +}; +static const char * const cci_i2c_groups[] = { + "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", + "gpio107", "gpio108", +}; +static const char * const qdss_gpio_groups[] = { + "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", + "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", + "gpio107", "gpio108", "gpio109", "gpio110", "gpio111", "gpio160", + "gpio161", "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", + "gpio167", "gpio168", "gpio169", "gpio170", "gpio171", "gpio172", + "gpio173", "gpio174", "gpio175", "gpio176", "gpio177", +}; +static const char * const gcc_gp1_groups[] = { + "gpio106", "gpio136", +}; +static const char * const gcc_gp2_groups[] = { + "gpio107", "gpio137", +}; +static const char * const gcc_gp3_groups[] = { + "gpio108", "gpio138", +}; +static const char * const cci_timer0_groups[] = { + "gpio109", +}; +static const char * const cci_timer1_groups[] = { + "gpio110", +}; +static const char * const cci_timer2_groups[] = { + "gpio111", +}; +static const char * const cci_timer3_groups[] = { + "gpio112", +}; +static const char * const cci_async_groups[] = { + "gpio112", "gpio113", "gpio114", +}; +static const char * const cci_timer4_groups[] = { + "gpio113", +}; +static const char * const qup2_groups[] = { + "gpio115", "gpio116", "gpio117", "gpio118", +}; +static const char * const qup3_groups[] = { + "gpio119", "gpio120", "gpio121", "gpio122", +}; +static const char * const tsense_pwm1_groups[] = { + "gpio123", +}; +static const char * const tsense_pwm2_groups[] = { + "gpio123", +}; +static const char * const qup9_groups[] = { + "gpio125", "gpio126", "gpio127", "gpio128", +}; +static const char * const qup10_groups[] = { + "gpio129", "gpio130", "gpio131", "gpio132", +}; +static const char * const mi2s2_sck_groups[] = { + "gpio133", +}; +static const char * const mi2s2_data0_groups[] = { + "gpio134", +}; +static const char * const mi2s2_ws_groups[] = { + "gpio135", +}; +static const char * const pri_mi2s_groups[] = { + "gpio136", +}; +static const char * const sec_mi2s_groups[] = { + "gpio137", +}; +static const char * const audio_ref_groups[] = { + "gpio137", +}; +static const char * const mi2s2_data1_groups[] = { + "gpio137", +}; +static const char * const mi2s0_sck_groups[] = { + "gpio138", +}; +static const char * const mi2s0_data0_groups[] = { + "gpio139", +}; +static const char * const mi2s0_data1_groups[] = { + "gpio140", +}; +static const char * const mi2s0_ws_groups[] = { + "gpio141", +}; +static const char * const lpass_slimbus_groups[] = { + "gpio142", "gpio143", "gpio144", "gpio145", +}; +static const char * const mi2s1_sck_groups[] = { + "gpio142", +}; +static const char * const mi2s1_data0_groups[] = { + "gpio143", +}; +static const char * const mi2s1_data1_groups[] = { + "gpio144", +}; +static const char * const mi2s1_ws_groups[] = { + "gpio145", +}; +static const char * const cri_trng0_groups[] = { + "gpio159", +}; +static const char * const cri_trng1_groups[] = { + "gpio160", +}; +static const char * const cri_trng_groups[] = { + "gpio161", +}; +static const char * const sp_cmu_groups[] = { + "gpio162", +}; +static const char * const prng_rosc_groups[] = { + "gpio163", +}; +static const char * const qup19_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", + "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158", + "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", + "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", + "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", + "gpio177", "gpio178", "gpio179", +}; +static const char * const qdss_cti_groups[] = { + "gpio0", "gpio2", "gpio2", "gpio44", "gpio45", "gpio46", "gpio92", + "gpio93", +}; +static const char * const qup1_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const ibi_i3c_groups[] = { + "gpio4", "gpio5", "gpio24", "gpio25", "gpio28", "gpio29", "gpio40", + "gpio41", +}; +static const char * const qup_l4_groups[] = { + "gpio6", "gpio14", "gpio46", "gpio123", +}; +static const char * const qup_l5_groups[] = { + "gpio7", "gpio15", "gpio47", "gpio124", +}; +static const char * const qup4_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const qup5_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; +static const char * const qup6_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; +static const char * const qup7_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; +static const char * const qup8_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", +}; +static const char * const qup0_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", +}; +static const char * const qup12_groups[] = { + "gpio32", "gpio33", "gpio34", "gpio35", +}; +static const char * const qup13_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; +static const char * const qup14_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", +}; +static const char * const ddr_pxi3_groups[] = { + "gpio40", "gpio43", +}; +static const char * const ddr_pxi1_groups[] = { + "gpio41", "gpio42", +}; +static const char * const vsense_trigger_groups[] = { + "gpio42", +}; +static const char * const qup15_groups[] = { + "gpio44", "gpio45", "gpio46", "gpio47", +}; +static const char * const dbg_out_groups[] = { + "gpio44", +}; +static const char * const qup16_groups[] = { + "gpio48", "gpio49", "gpio50", "gpio51", +}; +static const char * const qup17_groups[] = { + "gpio52", "gpio53", "gpio54", "gpio55", +}; +static const char * const ddr_pxi0_groups[] = { + "gpio52", "gpio53", +}; +static const char * const jitter_bist_groups[] = { + "gpio54", +}; +static const char * const pll_bist_groups[] = { + "gpio55", +}; +static const char * const ddr_pxi2_groups[] = { + "gpio55", "gpio56", +}; +static const char * const qup18_groups[] = { + "gpio56", "gpio57", "gpio58", "gpio59", +}; +static const char * const qup11_groups[] = { + "gpio60", "gpio61", "gpio62", "gpio63", +}; +static const char * const usb2phy_ac_groups[] = { + "gpio64", "gpio90", +}; +static const char * const qup_l6_groups[] = { + "gpio64", "gpio77", "gpio92", "gpio93", +}; +static const char * const usb_phy_groups[] = { + "gpio65", +}; +static const char * const pll_clk_groups[] = { + "gpio65", +}; +static const char * const mdp_vsync_groups[] = { + "gpio66", "gpio67", "gpio68", "gpio122", "gpio124", +}; +static const char * const dp_lcd_groups[] = { + "gpio67", +}; +static const char * const dp_hot_groups[] = { + "gpio68", +}; +static const char * const qspi_cs_groups[] = { + "gpio69", "gpio75", +}; +static const char * const tsif0_clk_groups[] = { + "gpio69", +}; +static const char * const qspi0_groups[] = { + "gpio70", +}; +static const char * const tsif0_en_groups[] = { + "gpio70", +}; +static const char * const mdp_vsync0_groups[] = { + "gpio70", +}; +static const char * const mdp_vsync1_groups[] = { + "gpio70", +}; +static const char * const mdp_vsync2_groups[] = { + "gpio70", +}; +static const char * const mdp_vsync3_groups[] = { + "gpio70", +}; +static const char * const qspi1_groups[] = { + "gpio71", +}; +static const char * const tsif0_data_groups[] = { + "gpio71", +}; +static const char * const sdc4_cmd_groups[] = { + "gpio71", +}; +static const char * const qspi2_groups[] = { + "gpio72", +}; +static const char * const tsif0_sync_groups[] = { + "gpio72", +}; +static const char * const sdc43_groups[] = { + "gpio72", +}; +static const char * const qspi_clk_groups[] = { + "gpio73", +}; +static const char * const tsif1_clk_groups[] = { + "gpio73", +}; +static const char * const sdc4_clk_groups[] = { + "gpio73", +}; +static const char * const qspi3_groups[] = { + "gpio74", +}; +static const char * const tsif1_en_groups[] = { + "gpio74", +}; +static const char * const sdc42_groups[] = { + "gpio74", +}; + +static const struct msm_function sm8250_functions[] = { + FUNCTION(aoss_cti), + FUNCTION(atest), + FUNCTION(audio_ref), + FUNCTION(cam_mclk), + FUNCTION(cci_async), + FUNCTION(cci_i2c), + FUNCTION(cci_timer0), + FUNCTION(cci_timer1), + FUNCTION(cci_timer2), + FUNCTION(cci_timer3), + FUNCTION(cci_timer4), + FUNCTION(cri_trng), + FUNCTION(cri_trng0), + FUNCTION(cri_trng1), + FUNCTION(dbg_out), + FUNCTION(ddr_bist), + FUNCTION(ddr_pxi0), + FUNCTION(ddr_pxi1), + FUNCTION(ddr_pxi2), + FUNCTION(ddr_pxi3), + FUNCTION(dp_hot), + FUNCTION(dp_lcd), + FUNCTION(gcc_gp1), + FUNCTION(gcc_gp2), + FUNCTION(gcc_gp3), + FUNCTION(gpio), + FUNCTION(ibi_i3c), + FUNCTION(jitter_bist), + FUNCTION(lpass_slimbus), + FUNCTION(mdp_vsync), + FUNCTION(mdp_vsync0), + FUNCTION(mdp_vsync1), + FUNCTION(mdp_vsync2), + FUNCTION(mdp_vsync3), + FUNCTION(mi2s0_data0), + FUNCTION(mi2s0_data1), + FUNCTION(mi2s0_sck), + FUNCTION(mi2s0_ws), + FUNCTION(mi2s1_data0), + FUNCTION(mi2s1_data1), + FUNCTION(mi2s1_sck), + FUNCTION(mi2s1_ws), + FUNCTION(mi2s2_data0), + FUNCTION(mi2s2_data1), + FUNCTION(mi2s2_sck), + FUNCTION(mi2s2_ws), + FUNCTION(pci_e0), + FUNCTION(pci_e1), + FUNCTION(pci_e2), + FUNCTION(phase_flag), + FUNCTION(pll_bist), + FUNCTION(pll_bypassnl), + FUNCTION(pll_clk), + FUNCTION(pll_reset), + FUNCTION(pri_mi2s), + FUNCTION(prng_rosc), + FUNCTION(qdss_cti), + FUNCTION(qdss_gpio), + FUNCTION(qspi0), + FUNCTION(qspi1), + FUNCTION(qspi2), + FUNCTION(qspi3), + FUNCTION(qspi_clk), + FUNCTION(qspi_cs), + FUNCTION(qup0), + FUNCTION(qup1), + FUNCTION(qup10), + FUNCTION(qup11), + FUNCTION(qup12), + FUNCTION(qup13), + FUNCTION(qup14), + FUNCTION(qup15), + FUNCTION(qup16), + FUNCTION(qup17), + FUNCTION(qup18), + FUNCTION(qup19), + FUNCTION(qup2), + FUNCTION(qup3), + FUNCTION(qup4), + FUNCTION(qup5), + FUNCTION(qup6), + FUNCTION(qup7), + FUNCTION(qup8), + FUNCTION(qup9), + FUNCTION(qup_l4), + FUNCTION(qup_l5), + FUNCTION(qup_l6), + FUNCTION(sd_write), + FUNCTION(sdc40), + FUNCTION(sdc41), + FUNCTION(sdc42), + FUNCTION(sdc43), + FUNCTION(sdc4_clk), + FUNCTION(sdc4_cmd), + FUNCTION(sec_mi2s), + FUNCTION(sp_cmu), + FUNCTION(tgu_ch0), + FUNCTION(tgu_ch1), + FUNCTION(tgu_ch2), + FUNCTION(tgu_ch3), + FUNCTION(tsense_pwm1), + FUNCTION(tsense_pwm2), + FUNCTION(tsif0_clk), + FUNCTION(tsif0_data), + FUNCTION(tsif0_en), + FUNCTION(tsif0_error), + FUNCTION(tsif0_sync), + FUNCTION(tsif1_clk), + FUNCTION(tsif1_data), + FUNCTION(tsif1_en), + FUNCTION(tsif1_error), + FUNCTION(tsif1_sync), + FUNCTION(usb2phy_ac), + FUNCTION(usb_phy), + FUNCTION(vsense_trigger), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sm8250_groups[] = { + [0] = PINGROUP(0, SOUTH, qup19, qdss_cti, _, _, _, _, _, _, _), + [1] = PINGROUP(1, SOUTH, qup19, _, _, _, _, _, _, _, _), + [2] = PINGROUP(2, SOUTH, qup19, qdss_cti, qdss_cti, _, _, _, _, _, _), + [3] = PINGROUP(3, SOUTH, qup19, _, _, _, _, _, _, _, _), + [4] = PINGROUP(4, NORTH, qup1, ibi_i3c, _, _, _, _, _, _, _), + [5] = PINGROUP(5, NORTH, qup1, ibi_i3c, _, _, _, _, _, _, _), + [6] = PINGROUP(6, NORTH, qup1, qup_l4, _, _, _, _, _, _, _), + [7] = PINGROUP(7, NORTH, qup1, qup_l5, _, _, _, _, _, _, _), + [8] = PINGROUP(8, NORTH, qup4, _, _, _, _, _, _, _, _), + [9] = PINGROUP(9, NORTH, qup4, _, _, _, _, _, _, _, _), + [10] = PINGROUP(10, NORTH, qup4, _, _, _, _, _, _, _, _), + [11] = PINGROUP(11, NORTH, qup4, _, _, _, _, _, _, _, _), + [12] = PINGROUP(12, NORTH, qup5, _, _, _, _, _, _, _, _), + [13] = PINGROUP(13, NORTH, qup5, _, _, _, _, _, _, _, _), + [14] = PINGROUP(14, NORTH, qup5, qup_l4, _, _, _, _, _, _, _), + [15] = PINGROUP(15, NORTH, qup5, qup_l5, _, _, _, _, _, _, _), + [16] = PINGROUP(16, NORTH, qup6, _, _, _, _, _, _, _, _), + [17] = PINGROUP(17, NORTH, qup6, _, _, _, _, _, _, _, _), + [18] = PINGROUP(18, NORTH, qup6, _, _, _, _, _, _, _, _), + [19] = PINGROUP(19, NORTH, qup6, _, _, _, _, _, _, _, _), + [20] = PINGROUP(20, NORTH, qup7, _, _, _, _, _, _, _, _), + [21] = PINGROUP(21, NORTH, qup7, _, _, _, _, _, _, _, _), + [22] = PINGROUP(22, NORTH, qup7, _, _, _, _, _, _, _, _), + [23] = PINGROUP(23, NORTH, qup7, _, _, _, _, _, _, _, _), + [24] = PINGROUP(24, SOUTH, qup8, ibi_i3c, atest, _, _, _, _, _, _), + [25] = PINGROUP(25, SOUTH, qup8, ibi_i3c, atest, _, _, _, _, _, _), + [26] = PINGROUP(26, SOUTH, qup8, atest, _, _, _, _, _, _, _), + [27] = PINGROUP(27, SOUTH, qup8, atest, _, _, _, _, _, _, _), + [28] = PINGROUP(28, NORTH, qup0, ibi_i3c, _, _, _, _, _, _, _), + [29] = PINGROUP(29, NORTH, qup0, ibi_i3c, _, _, _, _, _, _, _), + [30] = PINGROUP(30, NORTH, qup0, _, _, _, _, _, _, _, _), + [31] = PINGROUP(31, NORTH, qup0, _, _, _, _, _, _, _, _), + [32] = PINGROUP(32, SOUTH, qup12, _, atest, _, _, _, _, _, _), + [33] = PINGROUP(33, SOUTH, qup12, atest, _, _, _, _, _, _, _), + [34] = PINGROUP(34, SOUTH, qup12, atest, _, _, _, _, _, _, _), + [35] = PINGROUP(35, SOUTH, qup12, atest, _, _, _, _, _, _, _), + [36] = PINGROUP(36, SOUTH, qup13, atest, _, _, _, _, _, _, _), + [37] = PINGROUP(37, SOUTH, qup13, atest, _, _, _, _, _, _, _), + [38] = PINGROUP(38, SOUTH, qup13, _, _, _, _, _, _, _, _), + [39] = PINGROUP(39, SOUTH, qup13, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, SOUTH, qup14, ibi_i3c, _, ddr_pxi3, _, _, _, _, _), + [41] = PINGROUP(41, SOUTH, qup14, ibi_i3c, _, ddr_pxi1, _, _, _, _, _), + [42] = PINGROUP(42, SOUTH, qup14, vsense_trigger, ddr_pxi1, _, _, _, _, _, _), + [43] = PINGROUP(43, SOUTH, qup14, ddr_pxi3, _, _, _, _, _, _, _), + [44] = PINGROUP(44, SOUTH, qup15, qdss_cti, dbg_out, _, _, _, _, _, _), + [45] = PINGROUP(45, SOUTH, qup15, qdss_cti, phase_flag, _, _, _, _, _, _), + [46] = PINGROUP(46, SOUTH, qup15, qup_l4, qdss_cti, phase_flag, _, _, _, _, _), + [47] = PINGROUP(47, SOUTH, qup15, qup_l5, phase_flag, _, _, _, _, _, _), + [48] = PINGROUP(48, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _), + [49] = PINGROUP(49, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _), + [50] = PINGROUP(50, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _), + [51] = PINGROUP(51, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _), + [52] = PINGROUP(52, SOUTH, qup17, ddr_pxi0, _, _, _, _, _, _, _), + [53] = PINGROUP(53, SOUTH, qup17, ddr_pxi0, _, _, _, _, _, _, _), + [54] = PINGROUP(54, SOUTH, qup17, jitter_bist, _, _, _, _, _, _, _), + [55] = PINGROUP(55, SOUTH, qup17, pll_bist, ddr_pxi2, _, _, _, _, _, _), + [56] = PINGROUP(56, SOUTH, qup18, ddr_pxi2, _, _, _, _, _, _, _), + [57] = PINGROUP(57, SOUTH, qup18, _, _, _, _, _, _, _, _), + [58] = PINGROUP(58, SOUTH, qup18, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, SOUTH, qup18, _, _, _, _, _, _, _, _), + [60] = PINGROUP(60, SOUTH, qup11, _, _, _, _, _, _, _, _), + [61] = PINGROUP(61, SOUTH, qup11, _, _, _, _, _, _, _, _), + [62] = PINGROUP(62, SOUTH, qup11, _, _, _, _, _, _, _, _), + [63] = PINGROUP(63, SOUTH, qup11, _, _, _, _, _, _, _, _), + [64] = PINGROUP(64, SOUTH, usb2phy_ac, qup_l6, _, _, _, _, _, _, _), + [65] = PINGROUP(65, SOUTH, usb_phy, pll_clk, _, _, _, _, _, _, _), + [66] = PINGROUP(66, NORTH, mdp_vsync, _, _, _, _, _, _, _, _), + [67] = PINGROUP(67, NORTH, mdp_vsync, dp_lcd, _, _, _, _, _, _, _), + [68] = PINGROUP(68, NORTH, mdp_vsync, dp_hot, _, _, _, _, _, _, _), + [69] = PINGROUP(69, SOUTH, qspi_cs, tsif0_clk, phase_flag, _, _, _, _, _, _), + [70] = PINGROUP(70, SOUTH, qspi0, tsif0_en, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, phase_flag, _, _), + [71] = PINGROUP(71, SOUTH, qspi1, tsif0_data, sdc4_cmd, phase_flag, _, _, _, _, _), + [72] = PINGROUP(72, SOUTH, qspi2, tsif0_sync, sdc43, phase_flag, _, _, _, _, _), + [73] = PINGROUP(73, SOUTH, qspi_clk, tsif1_clk, sdc4_clk, phase_flag, _, _, _, _, _), + [74] = PINGROUP(74, SOUTH, qspi3, tsif1_en, sdc42, phase_flag, _, _, _, _, _), + [75] = PINGROUP(75, SOUTH, qspi_cs, tsif1_data, sdc41, _, _, _, _, _, _), + [76] = PINGROUP(76, SOUTH, tsif1_sync, sdc40, _, _, _, _, _, _, _), + [77] = PINGROUP(77, NORTH, qup_l6, aoss_cti, phase_flag, _, _, _, _, _, _), + [78] = PINGROUP(78, NORTH, sd_write, phase_flag, _, _, _, _, _, _, _), + [79] = PINGROUP(79, NORTH, pci_e0, phase_flag, _, _, _, _, _, _, _), + [80] = PINGROUP(80, NORTH, pci_e0, phase_flag, _, _, _, _, _, _, _), + [81] = PINGROUP(81, NORTH, phase_flag, _, _, _, _, _, _, _, _), + [82] = PINGROUP(82, NORTH, pci_e1, phase_flag, _, _, _, _, _, _, _), + [83] = PINGROUP(83, NORTH, pci_e1, phase_flag, _, _, _, _, _, _, _), + [84] = PINGROUP(84, NORTH, phase_flag, _, _, _, _, _, _, _, _), + [85] = PINGROUP(85, SOUTH, pci_e2, tgu_ch0, atest, _, _, _, _, _, _), + [86] = PINGROUP(86, SOUTH, pci_e2, tgu_ch3, atest, _, _, _, _, _, _), + [87] = PINGROUP(87, SOUTH, atest, _, _, _, _, _, _, _, _), + [88] = PINGROUP(88, SOUTH, _, atest, _, _, _, _, _, _, _), + [89] = PINGROUP(89, SOUTH, _, atest, _, _, _, _, _, _, _), + [90] = PINGROUP(90, SOUTH, tsif1_error, usb2phy_ac, tgu_ch1, _, _, _, _, _, _), + [91] = PINGROUP(91, SOUTH, tsif0_error, tgu_ch2, _, _, _, _, _, _, _), + [92] = PINGROUP(92, NORTH, qup_l6, qdss_cti, _, _, _, _, _, _, _), + [93] = PINGROUP(93, NORTH, qup_l6, qdss_cti, _, _, _, _, _, _, _), + [94] = PINGROUP(94, NORTH, cam_mclk, ddr_bist, qdss_gpio, _, _, _, _, _, _), + [95] = PINGROUP(95, NORTH, cam_mclk, ddr_bist, qdss_gpio, _, _, _, _, _, _), + [96] = PINGROUP(96, NORTH, cam_mclk, pll_bypassnl, qdss_gpio, _, _, _, _, _, _), + [97] = PINGROUP(97, NORTH, cam_mclk, pll_reset, qdss_gpio, _, _, _, _, _, _), + [98] = PINGROUP(98, NORTH, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [99] = PINGROUP(99, NORTH, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [100] = PINGROUP(100, NORTH, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [101] = PINGROUP(101, NORTH, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [102] = PINGROUP(102, NORTH, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [103] = PINGROUP(103, NORTH, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _), + [104] = PINGROUP(104, NORTH, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _), + [105] = PINGROUP(105, NORTH, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [106] = PINGROUP(106, NORTH, cci_i2c, gcc_gp1, qdss_gpio, _, _, _, _, _, _), + [107] = PINGROUP(107, NORTH, cci_i2c, gcc_gp2, qdss_gpio, _, _, _, _, _, _), + [108] = PINGROUP(108, NORTH, cci_i2c, gcc_gp3, qdss_gpio, _, _, _, _, _, _), + [109] = PINGROUP(109, NORTH, cci_timer0, qdss_gpio, _, _, _, _, _, _, _), + [110] = PINGROUP(110, NORTH, cci_timer1, qdss_gpio, _, _, _, _, _, _, _), + [111] = PINGROUP(111, NORTH, cci_timer2, qdss_gpio, _, _, _, _, _, _, _), + [112] = PINGROUP(112, NORTH, cci_timer3, cci_async, _, _, _, _, _, _, _), + [113] = PINGROUP(113, NORTH, cci_timer4, cci_async, _, _, _, _, _, _, _), + [114] = PINGROUP(114, NORTH, cci_async, _, _, _, _, _, _, _, _), + [115] = PINGROUP(115, NORTH, qup2, phase_flag, _, _, _, _, _, _, _), + [116] = PINGROUP(116, NORTH, qup2, phase_flag, _, _, _, _, _, _, _), + [117] = PINGROUP(117, NORTH, qup2, phase_flag, _, _, _, _, _, _, _), + [118] = PINGROUP(118, NORTH, qup2, phase_flag, _, _, _, _, _, _, _), + [119] = PINGROUP(119, NORTH, qup3, phase_flag, _, _, _, _, _, _, _), + [120] = PINGROUP(120, NORTH, qup3, phase_flag, _, _, _, _, _, _, _), + [121] = PINGROUP(121, NORTH, qup3, _, _, _, _, _, _, _, _), + [122] = PINGROUP(122, NORTH, qup3, mdp_vsync, phase_flag, _, _, _, _, _, _), + [123] = PINGROUP(123, NORTH, qup_l4, tsense_pwm1, tsense_pwm2, _, _, _, _, _, _), + [124] = PINGROUP(124, NORTH, qup_l5, mdp_vsync, phase_flag, _, _, _, _, _, _), + [125] = PINGROUP(125, SOUTH, qup9, phase_flag, _, _, _, _, _, _, _), + [126] = PINGROUP(126, SOUTH, qup9, _, _, _, _, _, _, _, _), + [127] = PINGROUP(127, SOUTH, qup9, _, _, _, _, _, _, _, _), + [128] = PINGROUP(128, SOUTH, qup9, _, _, _, _, _, _, _, _), + [129] = PINGROUP(129, SOUTH, qup10, _, _, _, _, _, _, _, _), + [130] = PINGROUP(130, SOUTH, qup10, _, _, _, _, _, _, _, _), + [131] = PINGROUP(131, SOUTH, qup10, _, _, _, _, _, _, _, _), + [132] = PINGROUP(132, SOUTH, qup10, _, _, _, _, _, _, _, _), + [133] = PINGROUP(133, WEST, mi2s2_sck, _, _, _, _, _, _, _, _), + [134] = PINGROUP(134, WEST, mi2s2_data0, _, _, _, _, _, _, _, _), + [135] = PINGROUP(135, WEST, mi2s2_ws, _, _, _, _, _, _, _, _), + [136] = PINGROUP(136, WEST, pri_mi2s, gcc_gp1, _, _, _, _, _, _, _), + [137] = PINGROUP(137, WEST, sec_mi2s, audio_ref, mi2s2_data1, gcc_gp2, _, _, _, _, _), + [138] = PINGROUP(138, WEST, mi2s0_sck, gcc_gp3, _, _, _, _, _, _, _), + [139] = PINGROUP(139, WEST, mi2s0_data0, _, _, _, _, _, _, _, _), + [140] = PINGROUP(140, WEST, mi2s0_data1, _, _, _, _, _, _, _, _), + [141] = PINGROUP(141, WEST, mi2s0_ws, _, _, _, _, _, _, _, _), + [142] = PINGROUP(142, WEST, lpass_slimbus, mi2s1_sck, _, _, _, _, _, _, _), + [143] = PINGROUP(143, WEST, lpass_slimbus, mi2s1_data0, ddr_bist, _, _, _, _, _, _), + [144] = PINGROUP(144, WEST, lpass_slimbus, mi2s1_data1, ddr_bist, _, _, _, _, _, _), + [145] = PINGROUP(145, WEST, lpass_slimbus, mi2s1_ws, _, _, _, _, _, _, _), + [146] = PINGROUP(146, WEST, _, _, _, _, _, _, _, _, _), + [147] = PINGROUP(147, WEST, _, _, _, _, _, _, _, _, _), + [148] = PINGROUP(148, WEST, _, _, _, _, _, _, _, _, _), + [149] = PINGROUP(149, WEST, _, _, _, _, _, _, _, _, _), + [150] = PINGROUP(150, WEST, _, _, _, _, _, _, _, _, _), + [151] = PINGROUP(151, WEST, _, _, _, _, _, _, _, _, _), + [152] = PINGROUP(152, WEST, _, _, _, _, _, _, _, _, _), + [153] = PINGROUP(153, WEST, _, _, _, _, _, _, _, _, _), + [154] = PINGROUP(154, WEST, _, _, _, _, _, _, _, _, _), + [155] = PINGROUP(155, WEST, _, _, _, _, _, _, _, _, _), + [156] = PINGROUP(156, WEST, _, _, _, _, _, _, _, _, _), + [157] = PINGROUP(157, WEST, _, _, _, _, _, _, _, _, _), + [158] = PINGROUP(158, WEST, _, _, _, _, _, _, _, _, _), + [159] = PINGROUP(159, WEST, cri_trng0, _, _, _, _, _, _, _, _), + [160] = PINGROUP(160, WEST, cri_trng1, qdss_gpio, _, _, _, _, _, _, _), + [161] = PINGROUP(161, WEST, cri_trng, qdss_gpio, _, _, _, _, _, _, _), + [162] = PINGROUP(162, WEST, sp_cmu, qdss_gpio, _, _, _, _, _, _, _), + [163] = PINGROUP(163, WEST, prng_rosc, qdss_gpio, _, _, _, _, _, _, _), + [164] = PINGROUP(164, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [165] = PINGROUP(165, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [166] = PINGROUP(166, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [167] = PINGROUP(167, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [168] = PINGROUP(168, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [169] = PINGROUP(169, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [170] = PINGROUP(170, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [171] = PINGROUP(171, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [172] = PINGROUP(172, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [173] = PINGROUP(173, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [174] = PINGROUP(174, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [175] = PINGROUP(175, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [176] = PINGROUP(176, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [177] = PINGROUP(177, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [178] = PINGROUP(178, WEST, _, _, _, _, _, _, _, _, _), + [179] = PINGROUP(179, WEST, _, _, _, _, _, _, _, _, _), + [180] = UFS_RESET(ufs_reset, 0xb8000), + [181] = SDC_PINGROUP(sdc2_clk, 0x7000, 14, 6), + [182] = SDC_PINGROUP(sdc2_cmd, 0xb7000, 11, 3), + [183] = SDC_PINGROUP(sdc2_data, 0xb7000, 9, 0), +}; + +static const struct msm_pinctrl_soc_data sm8250_pinctrl = { + .pins = sm8250_pins, + .npins = ARRAY_SIZE(sm8250_pins), + .functions = sm8250_functions, + .nfunctions = ARRAY_SIZE(sm8250_functions), + .groups = sm8250_groups, + .ngroups = ARRAY_SIZE(sm8250_groups), + .ngpios = 181, + .tiles = sm8250_tiles, + .ntiles = ARRAY_SIZE(sm8250_tiles), +}; + +static int sm8250_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sm8250_pinctrl); +} + +static const struct of_device_id sm8250_pinctrl_of_match[] = { + { .compatible = "qcom,sm8250-pinctrl", }, + { }, +}; + +static struct platform_driver sm8250_pinctrl_driver = { + .driver = { + .name = "sm8250-pinctrl", + .of_match_table = sm8250_pinctrl_of_match, + }, + .probe = sm8250_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sm8250_pinctrl_init(void) +{ + return platform_driver_register(&sm8250_pinctrl_driver); +} +arch_initcall(sm8250_pinctrl_init); + +static void __exit sm8250_pinctrl_exit(void) +{ + platform_driver_unregister(&sm8250_pinctrl_driver); +} +module_exit(sm8250_pinctrl_exit); + +MODULE_DESCRIPTION("QTI sm8250 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, sm8250_pinctrl_of_match); diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index 0599f5127b01..84501c785473 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -40,6 +40,8 @@ struct exynos_irq_chip { u32 eint_pend; u32 eint_wake_mask_value; u32 eint_wake_mask_reg; + void (*set_eint_wakeup_mask)(struct samsung_pinctrl_drv_data *drvdata, + struct exynos_irq_chip *irq_chip); }; static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip) @@ -265,6 +267,7 @@ struct exynos_eint_gpio_save { u32 eint_con; u32 eint_fltcon0; u32 eint_fltcon1; + u32 eint_mask; }; /* @@ -342,6 +345,47 @@ static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on) return 0; } +static void +exynos_pinctrl_set_eint_wakeup_mask(struct samsung_pinctrl_drv_data *drvdata, + struct exynos_irq_chip *irq_chip) +{ + struct regmap *pmu_regs; + + if (!drvdata->retention_ctrl || !drvdata->retention_ctrl->priv) { + dev_warn(drvdata->dev, + "No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n"); + return; + } + + pmu_regs = drvdata->retention_ctrl->priv; + dev_info(drvdata->dev, + "Setting external wakeup interrupt mask: 0x%x\n", + irq_chip->eint_wake_mask_value); + + regmap_write(pmu_regs, irq_chip->eint_wake_mask_reg, + irq_chip->eint_wake_mask_value); +} + +static void +s5pv210_pinctrl_set_eint_wakeup_mask(struct samsung_pinctrl_drv_data *drvdata, + struct exynos_irq_chip *irq_chip) + +{ + void __iomem *clk_base; + + if (!drvdata->retention_ctrl || !drvdata->retention_ctrl->priv) { + dev_warn(drvdata->dev, + "No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n"); + return; + } + + + clk_base = (void __iomem *) drvdata->retention_ctrl->priv; + + __raw_writel(irq_chip->eint_wake_mask_value, + clk_base + irq_chip->eint_wake_mask_reg); +} + /* * irq_chip for wakeup interrupts */ @@ -360,8 +404,9 @@ static const struct exynos_irq_chip s5pv210_wkup_irq_chip __initconst = { .eint_mask = EXYNOS_WKUP_EMASK_OFFSET, .eint_pend = EXYNOS_WKUP_EPEND_OFFSET, .eint_wake_mask_value = EXYNOS_EINT_WAKEUP_MASK_DISABLED, - /* Only difference with exynos4210_wkup_irq_chip: */ + /* Only differences with exynos4210_wkup_irq_chip: */ .eint_wake_mask_reg = S5PV210_EINT_WAKEUP_MASK, + .set_eint_wakeup_mask = s5pv210_pinctrl_set_eint_wakeup_mask, }; static const struct exynos_irq_chip exynos4210_wkup_irq_chip __initconst = { @@ -380,6 +425,7 @@ static const struct exynos_irq_chip exynos4210_wkup_irq_chip __initconst = { .eint_pend = EXYNOS_WKUP_EPEND_OFFSET, .eint_wake_mask_value = EXYNOS_EINT_WAKEUP_MASK_DISABLED, .eint_wake_mask_reg = EXYNOS_EINT_WAKEUP_MASK, + .set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask, }; static const struct exynos_irq_chip exynos7_wkup_irq_chip __initconst = { @@ -398,6 +444,7 @@ static const struct exynos_irq_chip exynos7_wkup_irq_chip __initconst = { .eint_pend = EXYNOS7_WKUP_EPEND_OFFSET, .eint_wake_mask_value = EXYNOS_EINT_WAKEUP_MASK_DISABLED, .eint_wake_mask_reg = EXYNOS5433_EINT_WAKEUP_MASK, + .set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask, }; /* list of external wakeup controllers supported */ @@ -574,27 +621,6 @@ int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) return 0; } -static void -exynos_pinctrl_set_eint_wakeup_mask(struct samsung_pinctrl_drv_data *drvdata, - struct exynos_irq_chip *irq_chip) -{ - struct regmap *pmu_regs; - - if (!drvdata->retention_ctrl || !drvdata->retention_ctrl->priv) { - dev_warn(drvdata->dev, - "No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n"); - return; - } - - pmu_regs = drvdata->retention_ctrl->priv; - dev_info(drvdata->dev, - "Setting external wakeup interrupt mask: 0x%x\n", - irq_chip->eint_wake_mask_value); - - regmap_write(pmu_regs, irq_chip->eint_wake_mask_reg, - irq_chip->eint_wake_mask_value); -} - static void exynos_pinctrl_suspend_bank( struct samsung_pinctrl_drv_data *drvdata, struct samsung_pin_bank *bank) @@ -608,10 +634,13 @@ static void exynos_pinctrl_suspend_bank( + 2 * bank->eint_offset); save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + 2 * bank->eint_offset + 4); + save->eint_mask = readl(regs + bank->irq_chip->eint_mask + + bank->eint_offset); pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0); pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1); + pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask); } void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) @@ -626,8 +655,8 @@ void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) else if (bank->eint_type == EINT_TYPE_WKUP) { if (!irq_chip) { irq_chip = bank->irq_chip; - exynos_pinctrl_set_eint_wakeup_mask(drvdata, - irq_chip); + irq_chip->set_eint_wakeup_mask(drvdata, + irq_chip); } else if (bank->irq_chip != irq_chip) { dev_warn(drvdata->dev, "More than one external wakeup interrupt chip configured (bank: %s). This is not supported by hardware nor by driver.\n", @@ -653,6 +682,9 @@ static void exynos_pinctrl_resume_bank( pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + 2 * bank->eint_offset + 4), save->eint_fltcon1); + pr_debug("%s: mask %#010x => %#010x\n", bank->name, + readl(regs + bank->irq_chip->eint_mask + + bank->eint_offset), save->eint_mask); writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET + bank->eint_offset); @@ -660,6 +692,8 @@ static void exynos_pinctrl_resume_bank( + 2 * bank->eint_offset); writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET + 2 * bank->eint_offset + 4); + writel(save->eint_mask, regs + bank->irq_chip->eint_mask + + bank->eint_offset); } void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index 9552851b96f1..c461a2f1927a 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -12,6 +12,7 @@ config PINCTRL_SH_PFC select PINCTRL_PFC_EMEV2 if ARCH_EMEV2 select PINCTRL_PFC_R8A73A4 if ARCH_R8A73A4 select PINCTRL_PFC_R8A7740 if ARCH_R8A7740 + select PINCTRL_PFC_R8A7742 if ARCH_R8A7742 select PINCTRL_PFC_R8A7743 if ARCH_R8A7743 select PINCTRL_PFC_R8A7744 if ARCH_R8A7744 select PINCTRL_PFC_R8A7745 if ARCH_R8A7745 @@ -74,6 +75,9 @@ config PINCTRL_PFC_R8A7740 bool "R-Mobile A1 pin control support" if COMPILE_TEST select PINCTRL_SH_PFC_GPIO +config PINCTRL_PFC_R8A7742 + bool "RZ/G1H pin control support" if COMPILE_TEST + config PINCTRL_PFC_R8A7743 bool "RZ/G1M pin control support" if COMPILE_TEST diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile index 9ebe321d24c4..3855d82069c9 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/sh-pfc/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_SH_PFC_GPIO) += gpio.o obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o +obj-$(CONFIG_PINCTRL_PFC_R8A7742) += pfc-r8a7790.o obj-$(CONFIG_PINCTRL_PFC_R8A7743) += pfc-r8a7791.o obj-$(CONFIG_PINCTRL_PFC_R8A7744) += pfc-r8a7791.o obj-$(CONFIG_PINCTRL_PFC_R8A7745) += pfc-r8a7794.o diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index a2e19efa26e3..f368383cba61 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -485,6 +485,12 @@ static const struct of_device_id sh_pfc_of_table[] = { .data = &r8a7740_pinmux_info, }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A7742 + { + .compatible = "renesas,pfc-r8a7742", + .data = &r8a7742_pinmux_info, + }, +#endif #ifdef CONFIG_PINCTRL_PFC_R8A7743 { .compatible = "renesas,pfc-r8a7743", diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index 3366ed561cce..f524401fec5f 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -3938,297 +3938,304 @@ static const unsigned int vin3_clk_mux[] = { VI3_CLK_MARK, }; -static const struct sh_pfc_pin_group pinmux_groups[] = { - SH_PFC_PIN_GROUP(audio_clk_a), - SH_PFC_PIN_GROUP(audio_clk_b), - SH_PFC_PIN_GROUP(audio_clk_c), - SH_PFC_PIN_GROUP(audio_clkout), - SH_PFC_PIN_GROUP(audio_clkout_b), - SH_PFC_PIN_GROUP(audio_clkout_c), - SH_PFC_PIN_GROUP(audio_clkout_d), - SH_PFC_PIN_GROUP(avb_link), - SH_PFC_PIN_GROUP(avb_magic), - SH_PFC_PIN_GROUP(avb_phy_int), - SH_PFC_PIN_GROUP(avb_mdio), - SH_PFC_PIN_GROUP(avb_mii), - SH_PFC_PIN_GROUP(avb_gmii), - SH_PFC_PIN_GROUP(du_rgb666), - SH_PFC_PIN_GROUP(du_rgb888), - SH_PFC_PIN_GROUP(du_clk_out_0), - SH_PFC_PIN_GROUP(du_clk_out_1), - SH_PFC_PIN_GROUP(du_sync_0), - SH_PFC_PIN_GROUP(du_sync_1), - SH_PFC_PIN_GROUP(du_cde), - SH_PFC_PIN_GROUP(du0_clk_in), - SH_PFC_PIN_GROUP(du1_clk_in), - SH_PFC_PIN_GROUP(du2_clk_in), - SH_PFC_PIN_GROUP(eth_link), - SH_PFC_PIN_GROUP(eth_magic), - SH_PFC_PIN_GROUP(eth_mdio), - SH_PFC_PIN_GROUP(eth_rmii), - SH_PFC_PIN_GROUP(hscif0_data), - SH_PFC_PIN_GROUP(hscif0_clk), - SH_PFC_PIN_GROUP(hscif0_ctrl), - SH_PFC_PIN_GROUP(hscif0_data_b), - SH_PFC_PIN_GROUP(hscif0_ctrl_b), - SH_PFC_PIN_GROUP(hscif0_data_c), - SH_PFC_PIN_GROUP(hscif0_ctrl_c), - SH_PFC_PIN_GROUP(hscif0_data_d), - SH_PFC_PIN_GROUP(hscif0_ctrl_d), - SH_PFC_PIN_GROUP(hscif0_data_e), - SH_PFC_PIN_GROUP(hscif0_ctrl_e), - SH_PFC_PIN_GROUP(hscif0_data_f), - SH_PFC_PIN_GROUP(hscif0_ctrl_f), - SH_PFC_PIN_GROUP(hscif1_data), - SH_PFC_PIN_GROUP(hscif1_clk), - SH_PFC_PIN_GROUP(hscif1_ctrl), - SH_PFC_PIN_GROUP(hscif1_data_b), - SH_PFC_PIN_GROUP(hscif1_clk_b), - SH_PFC_PIN_GROUP(hscif1_ctrl_b), - SH_PFC_PIN_GROUP(i2c0), - SH_PFC_PIN_GROUP(i2c1), - SH_PFC_PIN_GROUP(i2c1_b), - SH_PFC_PIN_GROUP(i2c1_c), - SH_PFC_PIN_GROUP(i2c2), - SH_PFC_PIN_GROUP(i2c2_b), - SH_PFC_PIN_GROUP(i2c2_c), - SH_PFC_PIN_GROUP(i2c2_d), - SH_PFC_PIN_GROUP(i2c2_e), - SH_PFC_PIN_GROUP(i2c3), - SH_PFC_PIN_GROUP(iic0), - SH_PFC_PIN_GROUP(iic1), - SH_PFC_PIN_GROUP(iic1_b), - SH_PFC_PIN_GROUP(iic1_c), - SH_PFC_PIN_GROUP(iic2), - SH_PFC_PIN_GROUP(iic2_b), - SH_PFC_PIN_GROUP(iic2_c), - SH_PFC_PIN_GROUP(iic2_d), - SH_PFC_PIN_GROUP(iic2_e), - SH_PFC_PIN_GROUP(iic3), - SH_PFC_PIN_GROUP(intc_irq0), - SH_PFC_PIN_GROUP(intc_irq1), - SH_PFC_PIN_GROUP(intc_irq2), - SH_PFC_PIN_GROUP(intc_irq3), - SH_PFC_PIN_GROUP(mlb_3pin), - SH_PFC_PIN_GROUP(mmc0_data1), - SH_PFC_PIN_GROUP(mmc0_data4), - SH_PFC_PIN_GROUP(mmc0_data8), - SH_PFC_PIN_GROUP(mmc0_ctrl), - SH_PFC_PIN_GROUP(mmc1_data1), - SH_PFC_PIN_GROUP(mmc1_data4), - SH_PFC_PIN_GROUP(mmc1_data8), - SH_PFC_PIN_GROUP(mmc1_ctrl), - SH_PFC_PIN_GROUP(msiof0_clk), - SH_PFC_PIN_GROUP(msiof0_sync), - SH_PFC_PIN_GROUP(msiof0_ss1), - SH_PFC_PIN_GROUP(msiof0_ss2), - SH_PFC_PIN_GROUP(msiof0_rx), - SH_PFC_PIN_GROUP(msiof0_tx), - SH_PFC_PIN_GROUP(msiof0_clk_b), - SH_PFC_PIN_GROUP(msiof0_ss1_b), - SH_PFC_PIN_GROUP(msiof0_ss2_b), - SH_PFC_PIN_GROUP(msiof0_rx_b), - SH_PFC_PIN_GROUP(msiof0_tx_b), - SH_PFC_PIN_GROUP(msiof1_clk), - SH_PFC_PIN_GROUP(msiof1_sync), - SH_PFC_PIN_GROUP(msiof1_ss1), - SH_PFC_PIN_GROUP(msiof1_ss2), - SH_PFC_PIN_GROUP(msiof1_rx), - SH_PFC_PIN_GROUP(msiof1_tx), - SH_PFC_PIN_GROUP(msiof1_clk_b), - SH_PFC_PIN_GROUP(msiof1_ss1_b), - SH_PFC_PIN_GROUP(msiof1_ss2_b), - SH_PFC_PIN_GROUP(msiof1_rx_b), - SH_PFC_PIN_GROUP(msiof1_tx_b), - SH_PFC_PIN_GROUP(msiof2_clk), - SH_PFC_PIN_GROUP(msiof2_sync), - SH_PFC_PIN_GROUP(msiof2_ss1), - SH_PFC_PIN_GROUP(msiof2_ss2), - SH_PFC_PIN_GROUP(msiof2_rx), - SH_PFC_PIN_GROUP(msiof2_tx), - SH_PFC_PIN_GROUP(msiof3_clk), - SH_PFC_PIN_GROUP(msiof3_sync), - SH_PFC_PIN_GROUP(msiof3_ss1), - SH_PFC_PIN_GROUP(msiof3_ss2), - SH_PFC_PIN_GROUP(msiof3_rx), - SH_PFC_PIN_GROUP(msiof3_tx), - SH_PFC_PIN_GROUP(msiof3_clk_b), - SH_PFC_PIN_GROUP(msiof3_sync_b), - SH_PFC_PIN_GROUP(msiof3_rx_b), - SH_PFC_PIN_GROUP(msiof3_tx_b), - SH_PFC_PIN_GROUP(pwm0), - SH_PFC_PIN_GROUP(pwm0_b), - SH_PFC_PIN_GROUP(pwm1), - SH_PFC_PIN_GROUP(pwm1_b), - SH_PFC_PIN_GROUP(pwm2), - SH_PFC_PIN_GROUP(pwm3), - SH_PFC_PIN_GROUP(pwm4), - SH_PFC_PIN_GROUP(pwm5), - SH_PFC_PIN_GROUP(pwm6), - SH_PFC_PIN_GROUP(qspi_ctrl), - SH_PFC_PIN_GROUP(qspi_data2), - SH_PFC_PIN_GROUP(qspi_data4), - SH_PFC_PIN_GROUP(scif0_data), - SH_PFC_PIN_GROUP(scif0_clk), - SH_PFC_PIN_GROUP(scif0_ctrl), - SH_PFC_PIN_GROUP(scif0_data_b), - SH_PFC_PIN_GROUP(scif1_data), - SH_PFC_PIN_GROUP(scif1_clk), - SH_PFC_PIN_GROUP(scif1_ctrl), - SH_PFC_PIN_GROUP(scif1_data_b), - SH_PFC_PIN_GROUP(scif1_data_c), - SH_PFC_PIN_GROUP(scif1_data_d), - SH_PFC_PIN_GROUP(scif1_clk_d), - SH_PFC_PIN_GROUP(scif1_data_e), - SH_PFC_PIN_GROUP(scif1_clk_e), - SH_PFC_PIN_GROUP(scif2_data), - SH_PFC_PIN_GROUP(scif2_clk), - SH_PFC_PIN_GROUP(scif2_data_b), - SH_PFC_PIN_GROUP(scifa0_data), - SH_PFC_PIN_GROUP(scifa0_clk), - SH_PFC_PIN_GROUP(scifa0_ctrl), - SH_PFC_PIN_GROUP(scifa0_data_b), - SH_PFC_PIN_GROUP(scifa0_clk_b), - SH_PFC_PIN_GROUP(scifa0_ctrl_b), - SH_PFC_PIN_GROUP(scifa1_data), - SH_PFC_PIN_GROUP(scifa1_clk), - SH_PFC_PIN_GROUP(scifa1_ctrl), - SH_PFC_PIN_GROUP(scifa1_data_b), - SH_PFC_PIN_GROUP(scifa1_clk_b), - SH_PFC_PIN_GROUP(scifa1_ctrl_b), - SH_PFC_PIN_GROUP(scifa1_data_c), - SH_PFC_PIN_GROUP(scifa1_clk_c), - SH_PFC_PIN_GROUP(scifa1_ctrl_c), - SH_PFC_PIN_GROUP(scifa1_data_d), - SH_PFC_PIN_GROUP(scifa1_clk_d), - SH_PFC_PIN_GROUP(scifa1_ctrl_d), - SH_PFC_PIN_GROUP(scifa2_data), - SH_PFC_PIN_GROUP(scifa2_clk), - SH_PFC_PIN_GROUP(scifa2_ctrl), - SH_PFC_PIN_GROUP(scifa2_data_b), - SH_PFC_PIN_GROUP(scifa2_data_c), - SH_PFC_PIN_GROUP(scifa2_clk_c), - SH_PFC_PIN_GROUP(scifb0_data), - SH_PFC_PIN_GROUP(scifb0_clk), - SH_PFC_PIN_GROUP(scifb0_ctrl), - SH_PFC_PIN_GROUP(scifb0_data_b), - SH_PFC_PIN_GROUP(scifb0_clk_b), - SH_PFC_PIN_GROUP(scifb0_ctrl_b), - SH_PFC_PIN_GROUP(scifb0_data_c), - SH_PFC_PIN_GROUP(scifb1_data), - SH_PFC_PIN_GROUP(scifb1_clk), - SH_PFC_PIN_GROUP(scifb1_ctrl), - SH_PFC_PIN_GROUP(scifb1_data_b), - SH_PFC_PIN_GROUP(scifb1_clk_b), - SH_PFC_PIN_GROUP(scifb1_ctrl_b), - SH_PFC_PIN_GROUP(scifb1_data_c), - SH_PFC_PIN_GROUP(scifb1_data_d), - SH_PFC_PIN_GROUP(scifb1_data_e), - SH_PFC_PIN_GROUP(scifb1_clk_e), - SH_PFC_PIN_GROUP(scifb1_data_f), - SH_PFC_PIN_GROUP(scifb1_data_g), - SH_PFC_PIN_GROUP(scifb1_clk_g), - SH_PFC_PIN_GROUP(scifb2_data), - SH_PFC_PIN_GROUP(scifb2_clk), - SH_PFC_PIN_GROUP(scifb2_ctrl), - SH_PFC_PIN_GROUP(scifb2_data_b), - SH_PFC_PIN_GROUP(scifb2_clk_b), - SH_PFC_PIN_GROUP(scifb2_ctrl_b), - SH_PFC_PIN_GROUP(scifb2_data_c), - SH_PFC_PIN_GROUP(scif_clk), - SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), - SH_PFC_PIN_GROUP(sdhi0_ctrl), - SH_PFC_PIN_GROUP(sdhi0_cd), - SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), - SH_PFC_PIN_GROUP(sdhi1_ctrl), - SH_PFC_PIN_GROUP(sdhi1_cd), - SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), - SH_PFC_PIN_GROUP(sdhi2_ctrl), - SH_PFC_PIN_GROUP(sdhi2_cd), - SH_PFC_PIN_GROUP(sdhi2_wp), - SH_PFC_PIN_GROUP(sdhi3_data1), - SH_PFC_PIN_GROUP(sdhi3_data4), - SH_PFC_PIN_GROUP(sdhi3_ctrl), - SH_PFC_PIN_GROUP(sdhi3_cd), - SH_PFC_PIN_GROUP(sdhi3_wp), - SH_PFC_PIN_GROUP(ssi0_data), - SH_PFC_PIN_GROUP(ssi0129_ctrl), - SH_PFC_PIN_GROUP(ssi1_data), - SH_PFC_PIN_GROUP(ssi1_ctrl), - SH_PFC_PIN_GROUP(ssi2_data), - SH_PFC_PIN_GROUP(ssi2_ctrl), - SH_PFC_PIN_GROUP(ssi3_data), - SH_PFC_PIN_GROUP(ssi34_ctrl), - SH_PFC_PIN_GROUP(ssi4_data), - SH_PFC_PIN_GROUP(ssi4_ctrl), - SH_PFC_PIN_GROUP(ssi5), - SH_PFC_PIN_GROUP(ssi5_b), - SH_PFC_PIN_GROUP(ssi5_c), - SH_PFC_PIN_GROUP(ssi6), - SH_PFC_PIN_GROUP(ssi6_b), - SH_PFC_PIN_GROUP(ssi7_data), - SH_PFC_PIN_GROUP(ssi7_b_data), - SH_PFC_PIN_GROUP(ssi7_c_data), - SH_PFC_PIN_GROUP(ssi78_ctrl), - SH_PFC_PIN_GROUP(ssi78_b_ctrl), - SH_PFC_PIN_GROUP(ssi78_c_ctrl), - SH_PFC_PIN_GROUP(ssi8_data), - SH_PFC_PIN_GROUP(ssi8_b_data), - SH_PFC_PIN_GROUP(ssi8_c_data), - SH_PFC_PIN_GROUP(ssi9_data), - SH_PFC_PIN_GROUP(ssi9_ctrl), - SH_PFC_PIN_GROUP(tpu0_to0), - SH_PFC_PIN_GROUP(tpu0_to1), - SH_PFC_PIN_GROUP(tpu0_to2), - SH_PFC_PIN_GROUP(tpu0_to3), - SH_PFC_PIN_GROUP(usb0), - SH_PFC_PIN_GROUP(usb0_ovc_vbus), - SH_PFC_PIN_GROUP(usb1), - SH_PFC_PIN_GROUP(usb2), - VIN_DATA_PIN_GROUP(vin0_data, 24), - VIN_DATA_PIN_GROUP(vin0_data, 20), - SH_PFC_PIN_GROUP(vin0_data18), - VIN_DATA_PIN_GROUP(vin0_data, 16), - VIN_DATA_PIN_GROUP(vin0_data, 12), - VIN_DATA_PIN_GROUP(vin0_data, 10), - VIN_DATA_PIN_GROUP(vin0_data, 8), - VIN_DATA_PIN_GROUP(vin0_data, 4), - SH_PFC_PIN_GROUP(vin0_sync), - SH_PFC_PIN_GROUP(vin0_field), - SH_PFC_PIN_GROUP(vin0_clkenb), - SH_PFC_PIN_GROUP(vin0_clk), - VIN_DATA_PIN_GROUP(vin1_data, 24), - VIN_DATA_PIN_GROUP(vin1_data, 20), - SH_PFC_PIN_GROUP(vin1_data18), - VIN_DATA_PIN_GROUP(vin1_data, 16), - VIN_DATA_PIN_GROUP(vin1_data, 12), - VIN_DATA_PIN_GROUP(vin1_data, 10), - VIN_DATA_PIN_GROUP(vin1_data, 8), - VIN_DATA_PIN_GROUP(vin1_data, 4), - SH_PFC_PIN_GROUP(vin1_sync), - SH_PFC_PIN_GROUP(vin1_field), - SH_PFC_PIN_GROUP(vin1_clkenb), - SH_PFC_PIN_GROUP(vin1_clk), - VIN_DATA_PIN_GROUP(vin2_data, 24), - SH_PFC_PIN_GROUP(vin2_data18), - VIN_DATA_PIN_GROUP(vin2_data, 16), - VIN_DATA_PIN_GROUP(vin2_data, 8), - VIN_DATA_PIN_GROUP(vin2_data, 4), - SH_PFC_PIN_GROUP(vin2_sync), - SH_PFC_PIN_GROUP(vin2_field), - SH_PFC_PIN_GROUP(vin2_clkenb), - SH_PFC_PIN_GROUP(vin2_clk), - SH_PFC_PIN_GROUP(vin3_data8), - SH_PFC_PIN_GROUP(vin3_sync), - SH_PFC_PIN_GROUP(vin3_field), - SH_PFC_PIN_GROUP(vin3_clkenb), - SH_PFC_PIN_GROUP(vin3_clk), +static const struct { + struct sh_pfc_pin_group common[289]; + struct sh_pfc_pin_group automotive[1]; +} pinmux_groups = { + .common = { + SH_PFC_PIN_GROUP(audio_clk_a), + SH_PFC_PIN_GROUP(audio_clk_b), + SH_PFC_PIN_GROUP(audio_clk_c), + SH_PFC_PIN_GROUP(audio_clkout), + SH_PFC_PIN_GROUP(audio_clkout_b), + SH_PFC_PIN_GROUP(audio_clkout_c), + SH_PFC_PIN_GROUP(audio_clkout_d), + SH_PFC_PIN_GROUP(avb_link), + SH_PFC_PIN_GROUP(avb_magic), + SH_PFC_PIN_GROUP(avb_phy_int), + SH_PFC_PIN_GROUP(avb_mdio), + SH_PFC_PIN_GROUP(avb_mii), + SH_PFC_PIN_GROUP(avb_gmii), + SH_PFC_PIN_GROUP(du_rgb666), + SH_PFC_PIN_GROUP(du_rgb888), + SH_PFC_PIN_GROUP(du_clk_out_0), + SH_PFC_PIN_GROUP(du_clk_out_1), + SH_PFC_PIN_GROUP(du_sync_0), + SH_PFC_PIN_GROUP(du_sync_1), + SH_PFC_PIN_GROUP(du_cde), + SH_PFC_PIN_GROUP(du0_clk_in), + SH_PFC_PIN_GROUP(du1_clk_in), + SH_PFC_PIN_GROUP(du2_clk_in), + SH_PFC_PIN_GROUP(eth_link), + SH_PFC_PIN_GROUP(eth_magic), + SH_PFC_PIN_GROUP(eth_mdio), + SH_PFC_PIN_GROUP(eth_rmii), + SH_PFC_PIN_GROUP(hscif0_data), + SH_PFC_PIN_GROUP(hscif0_clk), + SH_PFC_PIN_GROUP(hscif0_ctrl), + SH_PFC_PIN_GROUP(hscif0_data_b), + SH_PFC_PIN_GROUP(hscif0_ctrl_b), + SH_PFC_PIN_GROUP(hscif0_data_c), + SH_PFC_PIN_GROUP(hscif0_ctrl_c), + SH_PFC_PIN_GROUP(hscif0_data_d), + SH_PFC_PIN_GROUP(hscif0_ctrl_d), + SH_PFC_PIN_GROUP(hscif0_data_e), + SH_PFC_PIN_GROUP(hscif0_ctrl_e), + SH_PFC_PIN_GROUP(hscif0_data_f), + SH_PFC_PIN_GROUP(hscif0_ctrl_f), + SH_PFC_PIN_GROUP(hscif1_data), + SH_PFC_PIN_GROUP(hscif1_clk), + SH_PFC_PIN_GROUP(hscif1_ctrl), + SH_PFC_PIN_GROUP(hscif1_data_b), + SH_PFC_PIN_GROUP(hscif1_clk_b), + SH_PFC_PIN_GROUP(hscif1_ctrl_b), + SH_PFC_PIN_GROUP(i2c0), + SH_PFC_PIN_GROUP(i2c1), + SH_PFC_PIN_GROUP(i2c1_b), + SH_PFC_PIN_GROUP(i2c1_c), + SH_PFC_PIN_GROUP(i2c2), + SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c2_c), + SH_PFC_PIN_GROUP(i2c2_d), + SH_PFC_PIN_GROUP(i2c2_e), + SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(iic0), + SH_PFC_PIN_GROUP(iic1), + SH_PFC_PIN_GROUP(iic1_b), + SH_PFC_PIN_GROUP(iic1_c), + SH_PFC_PIN_GROUP(iic2), + SH_PFC_PIN_GROUP(iic2_b), + SH_PFC_PIN_GROUP(iic2_c), + SH_PFC_PIN_GROUP(iic2_d), + SH_PFC_PIN_GROUP(iic2_e), + SH_PFC_PIN_GROUP(iic3), + SH_PFC_PIN_GROUP(intc_irq0), + SH_PFC_PIN_GROUP(intc_irq1), + SH_PFC_PIN_GROUP(intc_irq2), + SH_PFC_PIN_GROUP(intc_irq3), + SH_PFC_PIN_GROUP(mmc0_data1), + SH_PFC_PIN_GROUP(mmc0_data4), + SH_PFC_PIN_GROUP(mmc0_data8), + SH_PFC_PIN_GROUP(mmc0_ctrl), + SH_PFC_PIN_GROUP(mmc1_data1), + SH_PFC_PIN_GROUP(mmc1_data4), + SH_PFC_PIN_GROUP(mmc1_data8), + SH_PFC_PIN_GROUP(mmc1_ctrl), + SH_PFC_PIN_GROUP(msiof0_clk), + SH_PFC_PIN_GROUP(msiof0_sync), + SH_PFC_PIN_GROUP(msiof0_ss1), + SH_PFC_PIN_GROUP(msiof0_ss2), + SH_PFC_PIN_GROUP(msiof0_rx), + SH_PFC_PIN_GROUP(msiof0_tx), + SH_PFC_PIN_GROUP(msiof0_clk_b), + SH_PFC_PIN_GROUP(msiof0_ss1_b), + SH_PFC_PIN_GROUP(msiof0_ss2_b), + SH_PFC_PIN_GROUP(msiof0_rx_b), + SH_PFC_PIN_GROUP(msiof0_tx_b), + SH_PFC_PIN_GROUP(msiof1_clk), + SH_PFC_PIN_GROUP(msiof1_sync), + SH_PFC_PIN_GROUP(msiof1_ss1), + SH_PFC_PIN_GROUP(msiof1_ss2), + SH_PFC_PIN_GROUP(msiof1_rx), + SH_PFC_PIN_GROUP(msiof1_tx), + SH_PFC_PIN_GROUP(msiof1_clk_b), + SH_PFC_PIN_GROUP(msiof1_ss1_b), + SH_PFC_PIN_GROUP(msiof1_ss2_b), + SH_PFC_PIN_GROUP(msiof1_rx_b), + SH_PFC_PIN_GROUP(msiof1_tx_b), + SH_PFC_PIN_GROUP(msiof2_clk), + SH_PFC_PIN_GROUP(msiof2_sync), + SH_PFC_PIN_GROUP(msiof2_ss1), + SH_PFC_PIN_GROUP(msiof2_ss2), + SH_PFC_PIN_GROUP(msiof2_rx), + SH_PFC_PIN_GROUP(msiof2_tx), + SH_PFC_PIN_GROUP(msiof3_clk), + SH_PFC_PIN_GROUP(msiof3_sync), + SH_PFC_PIN_GROUP(msiof3_ss1), + SH_PFC_PIN_GROUP(msiof3_ss2), + SH_PFC_PIN_GROUP(msiof3_rx), + SH_PFC_PIN_GROUP(msiof3_tx), + SH_PFC_PIN_GROUP(msiof3_clk_b), + SH_PFC_PIN_GROUP(msiof3_sync_b), + SH_PFC_PIN_GROUP(msiof3_rx_b), + SH_PFC_PIN_GROUP(msiof3_tx_b), + SH_PFC_PIN_GROUP(pwm0), + SH_PFC_PIN_GROUP(pwm0_b), + SH_PFC_PIN_GROUP(pwm1), + SH_PFC_PIN_GROUP(pwm1_b), + SH_PFC_PIN_GROUP(pwm2), + SH_PFC_PIN_GROUP(pwm3), + SH_PFC_PIN_GROUP(pwm4), + SH_PFC_PIN_GROUP(pwm5), + SH_PFC_PIN_GROUP(pwm6), + SH_PFC_PIN_GROUP(qspi_ctrl), + SH_PFC_PIN_GROUP(qspi_data2), + SH_PFC_PIN_GROUP(qspi_data4), + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_clk), + SH_PFC_PIN_GROUP(scif0_ctrl), + SH_PFC_PIN_GROUP(scif0_data_b), + SH_PFC_PIN_GROUP(scif1_data), + SH_PFC_PIN_GROUP(scif1_clk), + SH_PFC_PIN_GROUP(scif1_ctrl), + SH_PFC_PIN_GROUP(scif1_data_b), + SH_PFC_PIN_GROUP(scif1_data_c), + SH_PFC_PIN_GROUP(scif1_data_d), + SH_PFC_PIN_GROUP(scif1_clk_d), + SH_PFC_PIN_GROUP(scif1_data_e), + SH_PFC_PIN_GROUP(scif1_clk_e), + SH_PFC_PIN_GROUP(scif2_data), + SH_PFC_PIN_GROUP(scif2_clk), + SH_PFC_PIN_GROUP(scif2_data_b), + SH_PFC_PIN_GROUP(scifa0_data), + SH_PFC_PIN_GROUP(scifa0_clk), + SH_PFC_PIN_GROUP(scifa0_ctrl), + SH_PFC_PIN_GROUP(scifa0_data_b), + SH_PFC_PIN_GROUP(scifa0_clk_b), + SH_PFC_PIN_GROUP(scifa0_ctrl_b), + SH_PFC_PIN_GROUP(scifa1_data), + SH_PFC_PIN_GROUP(scifa1_clk), + SH_PFC_PIN_GROUP(scifa1_ctrl), + SH_PFC_PIN_GROUP(scifa1_data_b), + SH_PFC_PIN_GROUP(scifa1_clk_b), + SH_PFC_PIN_GROUP(scifa1_ctrl_b), + SH_PFC_PIN_GROUP(scifa1_data_c), + SH_PFC_PIN_GROUP(scifa1_clk_c), + SH_PFC_PIN_GROUP(scifa1_ctrl_c), + SH_PFC_PIN_GROUP(scifa1_data_d), + SH_PFC_PIN_GROUP(scifa1_clk_d), + SH_PFC_PIN_GROUP(scifa1_ctrl_d), + SH_PFC_PIN_GROUP(scifa2_data), + SH_PFC_PIN_GROUP(scifa2_clk), + SH_PFC_PIN_GROUP(scifa2_ctrl), + SH_PFC_PIN_GROUP(scifa2_data_b), + SH_PFC_PIN_GROUP(scifa2_data_c), + SH_PFC_PIN_GROUP(scifa2_clk_c), + SH_PFC_PIN_GROUP(scifb0_data), + SH_PFC_PIN_GROUP(scifb0_clk), + SH_PFC_PIN_GROUP(scifb0_ctrl), + SH_PFC_PIN_GROUP(scifb0_data_b), + SH_PFC_PIN_GROUP(scifb0_clk_b), + SH_PFC_PIN_GROUP(scifb0_ctrl_b), + SH_PFC_PIN_GROUP(scifb0_data_c), + SH_PFC_PIN_GROUP(scifb1_data), + SH_PFC_PIN_GROUP(scifb1_clk), + SH_PFC_PIN_GROUP(scifb1_ctrl), + SH_PFC_PIN_GROUP(scifb1_data_b), + SH_PFC_PIN_GROUP(scifb1_clk_b), + SH_PFC_PIN_GROUP(scifb1_ctrl_b), + SH_PFC_PIN_GROUP(scifb1_data_c), + SH_PFC_PIN_GROUP(scifb1_data_d), + SH_PFC_PIN_GROUP(scifb1_data_e), + SH_PFC_PIN_GROUP(scifb1_clk_e), + SH_PFC_PIN_GROUP(scifb1_data_f), + SH_PFC_PIN_GROUP(scifb1_data_g), + SH_PFC_PIN_GROUP(scifb1_clk_g), + SH_PFC_PIN_GROUP(scifb2_data), + SH_PFC_PIN_GROUP(scifb2_clk), + SH_PFC_PIN_GROUP(scifb2_ctrl), + SH_PFC_PIN_GROUP(scifb2_data_b), + SH_PFC_PIN_GROUP(scifb2_clk_b), + SH_PFC_PIN_GROUP(scifb2_ctrl_b), + SH_PFC_PIN_GROUP(scifb2_data_c), + SH_PFC_PIN_GROUP(scif_clk), + SH_PFC_PIN_GROUP(scif_clk_b), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi1_cd), + SH_PFC_PIN_GROUP(sdhi1_wp), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(sdhi2_cd), + SH_PFC_PIN_GROUP(sdhi2_wp), + SH_PFC_PIN_GROUP(sdhi3_data1), + SH_PFC_PIN_GROUP(sdhi3_data4), + SH_PFC_PIN_GROUP(sdhi3_ctrl), + SH_PFC_PIN_GROUP(sdhi3_cd), + SH_PFC_PIN_GROUP(sdhi3_wp), + SH_PFC_PIN_GROUP(ssi0_data), + SH_PFC_PIN_GROUP(ssi0129_ctrl), + SH_PFC_PIN_GROUP(ssi1_data), + SH_PFC_PIN_GROUP(ssi1_ctrl), + SH_PFC_PIN_GROUP(ssi2_data), + SH_PFC_PIN_GROUP(ssi2_ctrl), + SH_PFC_PIN_GROUP(ssi3_data), + SH_PFC_PIN_GROUP(ssi34_ctrl), + SH_PFC_PIN_GROUP(ssi4_data), + SH_PFC_PIN_GROUP(ssi4_ctrl), + SH_PFC_PIN_GROUP(ssi5), + SH_PFC_PIN_GROUP(ssi5_b), + SH_PFC_PIN_GROUP(ssi5_c), + SH_PFC_PIN_GROUP(ssi6), + SH_PFC_PIN_GROUP(ssi6_b), + SH_PFC_PIN_GROUP(ssi7_data), + SH_PFC_PIN_GROUP(ssi7_b_data), + SH_PFC_PIN_GROUP(ssi7_c_data), + SH_PFC_PIN_GROUP(ssi78_ctrl), + SH_PFC_PIN_GROUP(ssi78_b_ctrl), + SH_PFC_PIN_GROUP(ssi78_c_ctrl), + SH_PFC_PIN_GROUP(ssi8_data), + SH_PFC_PIN_GROUP(ssi8_b_data), + SH_PFC_PIN_GROUP(ssi8_c_data), + SH_PFC_PIN_GROUP(ssi9_data), + SH_PFC_PIN_GROUP(ssi9_ctrl), + SH_PFC_PIN_GROUP(tpu0_to0), + SH_PFC_PIN_GROUP(tpu0_to1), + SH_PFC_PIN_GROUP(tpu0_to2), + SH_PFC_PIN_GROUP(tpu0_to3), + SH_PFC_PIN_GROUP(usb0), + SH_PFC_PIN_GROUP(usb0_ovc_vbus), + SH_PFC_PIN_GROUP(usb1), + SH_PFC_PIN_GROUP(usb2), + VIN_DATA_PIN_GROUP(vin0_data, 24), + VIN_DATA_PIN_GROUP(vin0_data, 20), + SH_PFC_PIN_GROUP(vin0_data18), + VIN_DATA_PIN_GROUP(vin0_data, 16), + VIN_DATA_PIN_GROUP(vin0_data, 12), + VIN_DATA_PIN_GROUP(vin0_data, 10), + VIN_DATA_PIN_GROUP(vin0_data, 8), + VIN_DATA_PIN_GROUP(vin0_data, 4), + SH_PFC_PIN_GROUP(vin0_sync), + SH_PFC_PIN_GROUP(vin0_field), + SH_PFC_PIN_GROUP(vin0_clkenb), + SH_PFC_PIN_GROUP(vin0_clk), + VIN_DATA_PIN_GROUP(vin1_data, 24), + VIN_DATA_PIN_GROUP(vin1_data, 20), + SH_PFC_PIN_GROUP(vin1_data18), + VIN_DATA_PIN_GROUP(vin1_data, 16), + VIN_DATA_PIN_GROUP(vin1_data, 12), + VIN_DATA_PIN_GROUP(vin1_data, 10), + VIN_DATA_PIN_GROUP(vin1_data, 8), + VIN_DATA_PIN_GROUP(vin1_data, 4), + SH_PFC_PIN_GROUP(vin1_sync), + SH_PFC_PIN_GROUP(vin1_field), + SH_PFC_PIN_GROUP(vin1_clkenb), + SH_PFC_PIN_GROUP(vin1_clk), + VIN_DATA_PIN_GROUP(vin2_data, 24), + SH_PFC_PIN_GROUP(vin2_data18), + VIN_DATA_PIN_GROUP(vin2_data, 16), + VIN_DATA_PIN_GROUP(vin2_data, 8), + VIN_DATA_PIN_GROUP(vin2_data, 4), + SH_PFC_PIN_GROUP(vin2_sync), + SH_PFC_PIN_GROUP(vin2_field), + SH_PFC_PIN_GROUP(vin2_clkenb), + SH_PFC_PIN_GROUP(vin2_clk), + SH_PFC_PIN_GROUP(vin3_data8), + SH_PFC_PIN_GROUP(vin3_sync), + SH_PFC_PIN_GROUP(vin3_field), + SH_PFC_PIN_GROUP(vin3_clkenb), + SH_PFC_PIN_GROUP(vin3_clk), + }, + .automotive = { + SH_PFC_PIN_GROUP(mlb_3pin), + } }; static const char * const audio_clk_groups[] = { @@ -4689,63 +4696,70 @@ static const char * const vin3_groups[] = { "vin3_clk", }; -static const struct sh_pfc_function pinmux_functions[] = { - SH_PFC_FUNCTION(audio_clk), - SH_PFC_FUNCTION(avb), - SH_PFC_FUNCTION(du), - SH_PFC_FUNCTION(du0), - SH_PFC_FUNCTION(du1), - SH_PFC_FUNCTION(du2), - SH_PFC_FUNCTION(eth), - SH_PFC_FUNCTION(hscif0), - SH_PFC_FUNCTION(hscif1), - SH_PFC_FUNCTION(i2c0), - SH_PFC_FUNCTION(i2c1), - SH_PFC_FUNCTION(i2c2), - SH_PFC_FUNCTION(i2c3), - SH_PFC_FUNCTION(iic0), - SH_PFC_FUNCTION(iic1), - SH_PFC_FUNCTION(iic2), - SH_PFC_FUNCTION(iic3), - SH_PFC_FUNCTION(intc), - SH_PFC_FUNCTION(mlb), - SH_PFC_FUNCTION(mmc0), - SH_PFC_FUNCTION(mmc1), - SH_PFC_FUNCTION(msiof0), - SH_PFC_FUNCTION(msiof1), - SH_PFC_FUNCTION(msiof2), - SH_PFC_FUNCTION(msiof3), - SH_PFC_FUNCTION(pwm0), - SH_PFC_FUNCTION(pwm1), - SH_PFC_FUNCTION(pwm2), - SH_PFC_FUNCTION(pwm3), - SH_PFC_FUNCTION(pwm4), - SH_PFC_FUNCTION(pwm5), - SH_PFC_FUNCTION(pwm6), - SH_PFC_FUNCTION(qspi), - SH_PFC_FUNCTION(scif0), - SH_PFC_FUNCTION(scif1), - SH_PFC_FUNCTION(scif2), - SH_PFC_FUNCTION(scifa0), - SH_PFC_FUNCTION(scifa1), - SH_PFC_FUNCTION(scifa2), - SH_PFC_FUNCTION(scifb0), - SH_PFC_FUNCTION(scifb1), - SH_PFC_FUNCTION(scifb2), - SH_PFC_FUNCTION(scif_clk), - SH_PFC_FUNCTION(sdhi0), - SH_PFC_FUNCTION(sdhi1), - SH_PFC_FUNCTION(sdhi2), - SH_PFC_FUNCTION(sdhi3), - SH_PFC_FUNCTION(ssi), - SH_PFC_FUNCTION(tpu0), - SH_PFC_FUNCTION(usb0), - SH_PFC_FUNCTION(usb1), - SH_PFC_FUNCTION(usb2), - SH_PFC_FUNCTION(vin0), - SH_PFC_FUNCTION(vin1), - SH_PFC_FUNCTION(vin2), - SH_PFC_FUNCTION(vin3), +static const struct { + struct sh_pfc_function common[55]; + struct sh_pfc_function automotive[1]; +} pinmux_functions = { + .common = { + SH_PFC_FUNCTION(audio_clk), + SH_PFC_FUNCTION(avb), + SH_PFC_FUNCTION(du), + SH_PFC_FUNCTION(du0), + SH_PFC_FUNCTION(du1), + SH_PFC_FUNCTION(du2), + SH_PFC_FUNCTION(eth), + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(i2c0), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(iic0), + SH_PFC_FUNCTION(iic1), + SH_PFC_FUNCTION(iic2), + SH_PFC_FUNCTION(iic3), + SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(mmc0), + SH_PFC_FUNCTION(mmc1), + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(msiof3), + SH_PFC_FUNCTION(pwm0), + SH_PFC_FUNCTION(pwm1), + SH_PFC_FUNCTION(pwm2), + SH_PFC_FUNCTION(pwm3), + SH_PFC_FUNCTION(pwm4), + SH_PFC_FUNCTION(pwm5), + SH_PFC_FUNCTION(pwm6), + SH_PFC_FUNCTION(qspi), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif2), + SH_PFC_FUNCTION(scifa0), + SH_PFC_FUNCTION(scifa1), + SH_PFC_FUNCTION(scifa2), + SH_PFC_FUNCTION(scifb0), + SH_PFC_FUNCTION(scifb1), + SH_PFC_FUNCTION(scifb2), + SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(sdhi3), + SH_PFC_FUNCTION(ssi), + SH_PFC_FUNCTION(tpu0), + SH_PFC_FUNCTION(usb0), + SH_PFC_FUNCTION(usb1), + SH_PFC_FUNCTION(usb2), + SH_PFC_FUNCTION(vin0), + SH_PFC_FUNCTION(vin1), + SH_PFC_FUNCTION(vin2), + SH_PFC_FUNCTION(vin3), + }, + .automotive = { + SH_PFC_FUNCTION(mlb), + } }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { @@ -5736,6 +5750,29 @@ static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = { .pin_to_pocctrl = r8a7790_pin_to_pocctrl, }; +#ifdef CONFIG_PINCTRL_PFC_R8A7742 +const struct sh_pfc_soc_info r8a7742_pinmux_info = { + .name = "r8a77420_pfc", + .ops = &r8a7790_pinmux_ops, + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups.common, + .nr_groups = ARRAY_SIZE(pinmux_groups.common), + .functions = pinmux_functions.common, + .nr_functions = ARRAY_SIZE(pinmux_functions.common), + + .cfg_regs = pinmux_config_regs, + + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), +}; +#endif + +#ifdef CONFIG_PINCTRL_PFC_R8A7790 const struct sh_pfc_soc_info r8a7790_pinmux_info = { .name = "r8a77900_pfc", .ops = &r8a7790_pinmux_ops, @@ -5745,13 +5782,16 @@ const struct sh_pfc_soc_info r8a7790_pinmux_info = { .pins = pinmux_pins, .nr_pins = ARRAY_SIZE(pinmux_pins), - .groups = pinmux_groups, - .nr_groups = ARRAY_SIZE(pinmux_groups), - .functions = pinmux_functions, - .nr_functions = ARRAY_SIZE(pinmux_functions), + .groups = pinmux_groups.common, + .nr_groups = ARRAY_SIZE(pinmux_groups.common) + + ARRAY_SIZE(pinmux_groups.automotive), + .functions = pinmux_functions.common, + .nr_functions = ARRAY_SIZE(pinmux_functions.common) + + ARRAY_SIZE(pinmux_functions.automotive), .cfg_regs = pinmux_config_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; +#endif diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c index d20974a55d93..e2916aaa8304 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c @@ -1963,8 +1963,9 @@ static const struct pinmux_func pinmux_func_gpios[] = { static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* "name" addr register_size Field_Width */ - /* where Field_Width is 1 for single mode registers or 4 for upto 16 - mode registers and modes are described in assending order [0..16] */ + /* where Field_Width is 1 for single mode registers or 4 for up to 16 + * mode registers and modes are described in assending order [0..15] + */ { PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1, GROUP( 0, 0, 0, 0, 0, 0, 0, 0, diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index d57e633e99c0..0f013827baf9 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -304,6 +304,7 @@ struct sh_pfc_soc_info { extern const struct sh_pfc_soc_info emev2_pinmux_info; extern const struct sh_pfc_soc_info r8a73a4_pinmux_info; extern const struct sh_pfc_soc_info r8a7740_pinmux_info; +extern const struct sh_pfc_soc_info r8a7742_pinmux_info; extern const struct sh_pfc_soc_info r8a7743_pinmux_info; extern const struct sh_pfc_soc_info r8a7744_pinmux_info; extern const struct sh_pfc_soc_info r8a7745_pinmux_info; diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c index 1ebcb957c654..63a287d5795f 100644 --- a/drivers/pinctrl/sirf/pinctrl-sirf.c +++ b/drivers/pinctrl/sirf/pinctrl-sirf.c @@ -794,13 +794,17 @@ static int sirfsoc_gpio_probe(struct device_node *np) return -ENODEV; sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL); - if (!sgpio) - return -ENOMEM; + if (!sgpio) { + err = -ENOMEM; + goto out_put_device; + } spin_lock_init(&sgpio->lock); regs = of_iomap(np, 0); - if (!regs) - return -ENOMEM; + if (!regs) { + err = -ENOMEM; + goto out_put_device; + } sgpio->chip.gc.request = sirfsoc_gpio_request; sgpio->chip.gc.free = sirfsoc_gpio_free; @@ -824,8 +828,10 @@ static int sirfsoc_gpio_probe(struct device_node *np) girq->parents = devm_kcalloc(&pdev->dev, SIRFSOC_GPIO_NO_OF_BANKS, sizeof(*girq->parents), GFP_KERNEL); - if (!girq->parents) - return -ENOMEM; + if (!girq->parents) { + err = -ENOMEM; + goto out_put_device; + } for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { bank = &sgpio->sgpio_bank[i]; spin_lock_init(&bank->lock); @@ -868,6 +874,8 @@ out_no_range: gpiochip_remove(&sgpio->chip.gc); out: iounmap(regs); +out_put_device: + put_device(&pdev->dev); return err; } diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.c b/drivers/pinctrl/sprd/pinctrl-sprd.c index 48cbf2a2837f..08dc1931b358 100644 --- a/drivers/pinctrl/sprd/pinctrl-sprd.c +++ b/drivers/pinctrl/sprd/pinctrl-sprd.c @@ -68,8 +68,8 @@ #define SLEEP_PULL_UP_MASK 0x1 #define SLEEP_PULL_UP_SHIFT 3 -#define PULL_UP_20K (BIT(12) | BIT(7)) -#define PULL_UP_4_7K BIT(12) +#define PULL_UP_4_7K (BIT(12) | BIT(7)) +#define PULL_UP_20K BIT(7) #define PULL_UP_MASK 0x21 #define PULL_UP_SHIFT 7 diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c index 8a08c4afc6a8..9e5b61449999 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c @@ -103,8 +103,11 @@ static int sun8i_a23_r_pinctrl_probe(struct platform_device *pdev) rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); if (IS_ERR(rstc)) { - dev_err(&pdev->dev, "Reset controller missing\n"); - return PTR_ERR(rstc); + ret = PTR_ERR(rstc); + if (ret == -EPROBE_DEFER) + return ret; + dev_err(&pdev->dev, "Reset controller missing err=%d\n", ret); + return ret; } ret = reset_control_deassert(rstc); diff --git a/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c b/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c index 6f7b3767f453..43922ab81666 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c @@ -123,7 +123,7 @@ static int tegra_xusb_padctl_get_group_pins(struct pinctrl_dev *pinctrl, unsigned *num_pins) { /* - * For the tegra-xusb pad controller groups are synonomous + * For the tegra-xusb pad controller groups are synonymous * with lanes/pins and there is always one lane/pin per group. */ *pins = &pinctrl->desc->pins[group].number; diff --git a/drivers/pinctrl/zte/pinctrl-zx.c b/drivers/pinctrl/zte/pinctrl-zx.c index 786bf89487d6..80d00ab8c110 100644 --- a/drivers/pinctrl/zte/pinctrl-zx.c +++ b/drivers/pinctrl/zte/pinctrl-zx.c @@ -94,7 +94,7 @@ static int zx_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, if (data->aon_pin) { /* * It's an AON pin, whose mux register offset and bit position - * can be caluculated from pin number. Each register covers 16 + * can be calculated from pin number. Each register covers 16 * pins, and each pin occupies 2 bits. */ u16 aoffset = pindesc->number / 16 * 4; diff --git a/drivers/reset/reset-zynqmp.c b/drivers/reset/reset-zynqmp.c index 0144075b11a6..373ea8d4f7a1 100644 --- a/drivers/reset/reset-zynqmp.c +++ b/drivers/reset/reset-zynqmp.c @@ -15,7 +15,6 @@ struct zynqmp_reset_data { struct reset_controller_dev rcdev; - const struct zynqmp_eemi_ops *eemi_ops; }; static inline struct zynqmp_reset_data * @@ -27,28 +26,23 @@ to_zynqmp_reset_data(struct reset_controller_dev *rcdev) static int zynqmp_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) { - struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev); - - return priv->eemi_ops->reset_assert(ZYNQMP_RESET_ID + id, - PM_RESET_ACTION_ASSERT); + return zynqmp_pm_reset_assert(ZYNQMP_RESET_ID + id, + PM_RESET_ACTION_ASSERT); } static int zynqmp_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) { - struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev); - - return priv->eemi_ops->reset_assert(ZYNQMP_RESET_ID + id, - PM_RESET_ACTION_RELEASE); + return zynqmp_pm_reset_assert(ZYNQMP_RESET_ID + id, + PM_RESET_ACTION_RELEASE); } static int zynqmp_reset_status(struct reset_controller_dev *rcdev, unsigned long id) { - struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev); int val, err; - err = priv->eemi_ops->reset_get_status(ZYNQMP_RESET_ID + id, &val); + err = zynqmp_pm_reset_get_status(ZYNQMP_RESET_ID + id, &val); if (err) return err; @@ -58,10 +52,8 @@ static int zynqmp_reset_status(struct reset_controller_dev *rcdev, static int zynqmp_reset_reset(struct reset_controller_dev *rcdev, unsigned long id) { - struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev); - - return priv->eemi_ops->reset_assert(ZYNQMP_RESET_ID + id, - PM_RESET_ACTION_PULSE); + return zynqmp_pm_reset_assert(ZYNQMP_RESET_ID + id, + PM_RESET_ACTION_PULSE); } static const struct reset_control_ops zynqmp_reset_ops = { @@ -79,10 +71,6 @@ static int zynqmp_reset_probe(struct platform_device *pdev) if (!priv) return -ENOMEM; - priv->eemi_ops = zynqmp_pm_get_eemi_ops(); - if (IS_ERR(priv->eemi_ops)) - return PTR_ERR(priv->eemi_ops); - platform_set_drvdata(pdev, priv); priv->rcdev.ops = &zynqmp_reset_ops; diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 527957d9c6ce..b54d87d45c89 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -1680,6 +1680,7 @@ config RTC_DRV_MPC5121 config RTC_DRV_JZ4740 tristate "Ingenic JZ4740 SoC" depends on MIPS || COMPILE_TEST + depends on OF help If you say yes here you get support for the Ingenic JZ47xx SoCs RTC controllers. diff --git a/drivers/rtc/rtc-88pm860x.c b/drivers/rtc/rtc-88pm860x.c index cc9b14ef90f1..c90457d001e9 100644 --- a/drivers/rtc/rtc-88pm860x.c +++ b/drivers/rtc/rtc-88pm860x.c @@ -106,12 +106,6 @@ static int pm860x_rtc_set_time(struct device *dev, struct rtc_time *tm) unsigned char buf[4]; unsigned long ticks, base, data; - if (tm->tm_year > 206) { - dev_dbg(info->dev, "Set time %d out of range. " - "Please set time between 1970 to 2106.\n", - 1900 + tm->tm_year); - return -EINVAL; - } ticks = rtc_tm_to_time64(tm); /* load 32-bit read-only counter */ diff --git a/drivers/rtc/rtc-abx80x.c b/drivers/rtc/rtc-abx80x.c index 3521d8e8dc38..803725b3a02c 100644 --- a/drivers/rtc/rtc-abx80x.c +++ b/drivers/rtc/rtc-abx80x.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -554,8 +555,9 @@ static const struct rtc_class_ops abx80x_rtc_ops = { .ioctl = abx80x_ioctl, }; -static int abx80x_dt_trickle_cfg(struct device_node *np) +static int abx80x_dt_trickle_cfg(struct i2c_client *client) { + struct device_node *np = client->dev.of_node; const char *diode; int trickle_cfg = 0; int i, ret; @@ -565,12 +567,14 @@ static int abx80x_dt_trickle_cfg(struct device_node *np) if (ret) return ret; - if (!strcmp(diode, "standard")) + if (!strcmp(diode, "standard")) { trickle_cfg |= ABX8XX_TRICKLE_STANDARD_DIODE; - else if (!strcmp(diode, "schottky")) + } else if (!strcmp(diode, "schottky")) { trickle_cfg |= ABX8XX_TRICKLE_SCHOTTKY_DIODE; - else + } else { + dev_dbg(&client->dev, "Invalid tc-diode value: %s\n", diode); return -EINVAL; + } ret = of_property_read_u32(np, "abracon,tc-resistor", &tmp); if (ret) @@ -580,8 +584,10 @@ static int abx80x_dt_trickle_cfg(struct device_node *np) if (trickle_resistors[i] == tmp) break; - if (i == sizeof(trickle_resistors)) + if (i == sizeof(trickle_resistors)) { + dev_dbg(&client->dev, "Invalid tc-resistor value: %u\n", tmp); return -EINVAL; + } return (trickle_cfg | i); } @@ -793,7 +799,7 @@ static int abx80x_probe(struct i2c_client *client, } if (np && abx80x_caps[part].has_tc) - trickle_cfg = abx80x_dt_trickle_cfg(np); + trickle_cfg = abx80x_dt_trickle_cfg(client); if (trickle_cfg > 0) { dev_info(&client->dev, "Enabling trickle charger: %02x\n", @@ -863,9 +869,57 @@ static const struct i2c_device_id abx80x_id[] = { }; MODULE_DEVICE_TABLE(i2c, abx80x_id); +#ifdef CONFIG_OF +static const struct of_device_id abx80x_of_match[] = { + { + .compatible = "abracon,abx80x", + .data = (void *)ABX80X + }, + { + .compatible = "abracon,ab0801", + .data = (void *)AB0801 + }, + { + .compatible = "abracon,ab0803", + .data = (void *)AB0803 + }, + { + .compatible = "abracon,ab0804", + .data = (void *)AB0804 + }, + { + .compatible = "abracon,ab0805", + .data = (void *)AB0805 + }, + { + .compatible = "abracon,ab1801", + .data = (void *)AB1801 + }, + { + .compatible = "abracon,ab1803", + .data = (void *)AB1803 + }, + { + .compatible = "abracon,ab1804", + .data = (void *)AB1804 + }, + { + .compatible = "abracon,ab1805", + .data = (void *)AB1805 + }, + { + .compatible = "microcrystal,rv1805", + .data = (void *)RV1805 + }, + { } +}; +MODULE_DEVICE_TABLE(of, abx80x_of_match); +#endif + static struct i2c_driver abx80x_driver = { .driver = { .name = "rtc-abx80x", + .of_match_table = of_match_ptr(abx80x_of_match), }, .probe = abx80x_probe, .id_table = abx80x_id, diff --git a/drivers/rtc/rtc-fsl-ftm-alarm.c b/drivers/rtc/rtc-fsl-ftm-alarm.c index 756af62b0486..68f0a1801a2e 100644 --- a/drivers/rtc/rtc-fsl-ftm-alarm.c +++ b/drivers/rtc/rtc-fsl-ftm-alarm.c @@ -21,6 +21,7 @@ #include #include #include +#include #define FTM_SC_CLK(c) ((c) << FTM_SC_CLK_MASK_SHIFT) @@ -268,13 +269,11 @@ static int ftm_rtc_probe(struct platform_device *pdev) } irq = platform_get_irq(pdev, 0); - if (irq < 0) { - dev_err(&pdev->dev, "can't get irq number\n"); + if (irq < 0) return irq; - } ret = devm_request_irq(&pdev->dev, irq, ftm_rtc_alarm_interrupt, - IRQF_NO_SUSPEND, dev_name(&pdev->dev), rtc); + 0, dev_name(&pdev->dev), rtc); if (ret < 0) { dev_err(&pdev->dev, "failed to request irq\n"); return ret; @@ -287,6 +286,9 @@ static int ftm_rtc_probe(struct platform_device *pdev) rtc->rtc_dev->ops = &ftm_rtc_ops; device_init_wakeup(&pdev->dev, true); + ret = dev_pm_set_wake_irq(&pdev->dev, irq); + if (ret) + dev_err(&pdev->dev, "failed to enable irq wake\n"); ret = rtc_register_device(rtc->rtc_dev); if (ret) { diff --git a/drivers/rtc/rtc-goldfish.c b/drivers/rtc/rtc-goldfish.c index cb6b0ad7ec3f..27797157fcb3 100644 --- a/drivers/rtc/rtc-goldfish.c +++ b/drivers/rtc/rtc-goldfish.c @@ -174,7 +174,7 @@ static int goldfish_rtc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, rtcdrv); rtcdrv->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(rtcdrv->base)) - return -ENODEV; + return PTR_ERR(rtcdrv->base); rtcdrv->irq = platform_get_irq(pdev, 0); if (rtcdrv->irq < 0) diff --git a/drivers/rtc/rtc-jz4740.c b/drivers/rtc/rtc-jz4740.c index e4c719085c31..9607e6b6e0b3 100644 --- a/drivers/rtc/rtc-jz4740.c +++ b/drivers/rtc/rtc-jz4740.c @@ -55,14 +55,8 @@ struct jz4740_rtc { enum jz4740_rtc_type type; struct rtc_device *rtc; - struct clk *clk; - - int irq; spinlock_t lock; - - unsigned int min_wakeup_pin_assert_time; - unsigned int reset_pin_assert_time; }; static struct device *dev_for_power_off; @@ -259,44 +253,15 @@ static void jz4740_rtc_poweroff(struct device *dev) static void jz4740_rtc_power_off(void) { - struct jz4740_rtc *rtc = dev_get_drvdata(dev_for_power_off); - unsigned long rtc_rate; - unsigned long wakeup_filter_ticks; - unsigned long reset_counter_ticks; - - clk_prepare_enable(rtc->clk); - - rtc_rate = clk_get_rate(rtc->clk); - - /* - * Set minimum wakeup pin assertion time: 100 ms. - * Range is 0 to 2 sec if RTC is clocked at 32 kHz. - */ - wakeup_filter_ticks = - (rtc->min_wakeup_pin_assert_time * rtc_rate) / 1000; - if (wakeup_filter_ticks < JZ_RTC_WAKEUP_FILTER_MASK) - wakeup_filter_ticks &= JZ_RTC_WAKEUP_FILTER_MASK; - else - wakeup_filter_ticks = JZ_RTC_WAKEUP_FILTER_MASK; - jz4740_rtc_reg_write(rtc, - JZ_REG_RTC_WAKEUP_FILTER, wakeup_filter_ticks); - - /* - * Set reset pin low-level assertion time after wakeup: 60 ms. - * Range is 0 to 125 ms if RTC is clocked at 32 kHz. - */ - reset_counter_ticks = (rtc->reset_pin_assert_time * rtc_rate) / 1000; - if (reset_counter_ticks < JZ_RTC_RESET_COUNTER_MASK) - reset_counter_ticks &= JZ_RTC_RESET_COUNTER_MASK; - else - reset_counter_ticks = JZ_RTC_RESET_COUNTER_MASK; - jz4740_rtc_reg_write(rtc, - JZ_REG_RTC_RESET_COUNTER, reset_counter_ticks); - jz4740_rtc_poweroff(dev_for_power_off); kernel_halt(); } +static void jz4740_rtc_clk_disable(void *data) +{ + clk_disable_unprepare(data); +} + static const struct of_device_id jz4740_rtc_of_match[] = { { .compatible = "ingenic,jz4740-rtc", .data = (void *)ID_JZ4740 }, { .compatible = "ingenic,jz4760-rtc", .data = (void *)ID_JZ4760 }, @@ -305,110 +270,140 @@ static const struct of_device_id jz4740_rtc_of_match[] = { }; MODULE_DEVICE_TABLE(of, jz4740_rtc_of_match); +static void jz4740_rtc_set_wakeup_params(struct jz4740_rtc *rtc, + struct device_node *np, + unsigned long rate) +{ + unsigned long wakeup_ticks, reset_ticks; + unsigned int min_wakeup_pin_assert_time = 60; /* Default: 60ms */ + unsigned int reset_pin_assert_time = 100; /* Default: 100ms */ + + of_property_read_u32(np, "ingenic,reset-pin-assert-time-ms", + &reset_pin_assert_time); + of_property_read_u32(np, "ingenic,min-wakeup-pin-assert-time-ms", + &min_wakeup_pin_assert_time); + + /* + * Set minimum wakeup pin assertion time: 100 ms. + * Range is 0 to 2 sec if RTC is clocked at 32 kHz. + */ + wakeup_ticks = (min_wakeup_pin_assert_time * rate) / 1000; + if (wakeup_ticks < JZ_RTC_WAKEUP_FILTER_MASK) + wakeup_ticks &= JZ_RTC_WAKEUP_FILTER_MASK; + else + wakeup_ticks = JZ_RTC_WAKEUP_FILTER_MASK; + jz4740_rtc_reg_write(rtc, JZ_REG_RTC_WAKEUP_FILTER, wakeup_ticks); + + /* + * Set reset pin low-level assertion time after wakeup: 60 ms. + * Range is 0 to 125 ms if RTC is clocked at 32 kHz. + */ + reset_ticks = (reset_pin_assert_time * rate) / 1000; + if (reset_ticks < JZ_RTC_RESET_COUNTER_MASK) + reset_ticks &= JZ_RTC_RESET_COUNTER_MASK; + else + reset_ticks = JZ_RTC_RESET_COUNTER_MASK; + jz4740_rtc_reg_write(rtc, JZ_REG_RTC_RESET_COUNTER, reset_ticks); +} + static int jz4740_rtc_probe(struct platform_device *pdev) { - int ret; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; struct jz4740_rtc *rtc; - const struct platform_device_id *id = platform_get_device_id(pdev); - const struct of_device_id *of_id = of_match_device( - jz4740_rtc_of_match, &pdev->dev); - struct device_node *np = pdev->dev.of_node; + unsigned long rate; + struct clk *clk; + int ret, irq; - rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); + rtc = devm_kzalloc(dev, sizeof(*rtc), GFP_KERNEL); if (!rtc) return -ENOMEM; - if (of_id) - rtc->type = (enum jz4740_rtc_type)of_id->data; - else - rtc->type = id->driver_data; + rtc->type = (enum jz4740_rtc_type)device_get_match_data(dev); - rtc->irq = platform_get_irq(pdev, 0); - if (rtc->irq < 0) - return -ENOENT; + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; rtc->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(rtc->base)) return PTR_ERR(rtc->base); - rtc->clk = devm_clk_get(&pdev->dev, "rtc"); - if (IS_ERR(rtc->clk)) { - dev_err(&pdev->dev, "Failed to get RTC clock\n"); - return PTR_ERR(rtc->clk); + clk = devm_clk_get(dev, "rtc"); + if (IS_ERR(clk)) { + dev_err(dev, "Failed to get RTC clock\n"); + return PTR_ERR(clk); + } + + ret = clk_prepare_enable(clk); + if (ret) { + dev_err(dev, "Failed to enable clock\n"); + return ret; + } + + ret = devm_add_action_or_reset(dev, jz4740_rtc_clk_disable, clk); + if (ret) { + dev_err(dev, "Failed to register devm action\n"); + return ret; } spin_lock_init(&rtc->lock); platform_set_drvdata(pdev, rtc); - device_init_wakeup(&pdev->dev, 1); + device_init_wakeup(dev, 1); - ret = dev_pm_set_wake_irq(&pdev->dev, rtc->irq); + ret = dev_pm_set_wake_irq(dev, irq); if (ret) { - dev_err(&pdev->dev, "Failed to set wake irq: %d\n", ret); + dev_err(dev, "Failed to set wake irq: %d\n", ret); return ret; } - rtc->rtc = devm_rtc_allocate_device(&pdev->dev); + rtc->rtc = devm_rtc_allocate_device(dev); if (IS_ERR(rtc->rtc)) { ret = PTR_ERR(rtc->rtc); - dev_err(&pdev->dev, "Failed to allocate rtc device: %d\n", ret); + dev_err(dev, "Failed to allocate rtc device: %d\n", ret); return ret; } rtc->rtc->ops = &jz4740_rtc_ops; rtc->rtc->range_max = U32_MAX; + rate = clk_get_rate(clk); + jz4740_rtc_set_wakeup_params(rtc, np, rate); + + /* Each 1 Hz pulse should happen after (rate) ticks */ + jz4740_rtc_reg_write(rtc, JZ_REG_RTC_REGULATOR, rate - 1); + ret = rtc_register_device(rtc->rtc); if (ret) return ret; - ret = devm_request_irq(&pdev->dev, rtc->irq, jz4740_rtc_irq, 0, - pdev->name, rtc); + ret = devm_request_irq(dev, irq, jz4740_rtc_irq, 0, + pdev->name, rtc); if (ret) { - dev_err(&pdev->dev, "Failed to request rtc irq: %d\n", ret); + dev_err(dev, "Failed to request rtc irq: %d\n", ret); return ret; } - if (np && of_device_is_system_power_controller(np)) { - if (!pm_power_off) { - /* Default: 60ms */ - rtc->reset_pin_assert_time = 60; - of_property_read_u32(np, - "ingenic,reset-pin-assert-time-ms", - &rtc->reset_pin_assert_time); + if (of_device_is_system_power_controller(np)) { + dev_for_power_off = dev; - /* Default: 100ms */ - rtc->min_wakeup_pin_assert_time = 100; - of_property_read_u32(np, - "ingenic,min-wakeup-pin-assert-time-ms", - &rtc->min_wakeup_pin_assert_time); - - dev_for_power_off = &pdev->dev; + if (!pm_power_off) pm_power_off = jz4740_rtc_power_off; - } else { - dev_warn(&pdev->dev, - "Poweroff handler already present!\n"); - } + else + dev_warn(dev, "Poweroff handler already present!\n"); } return 0; } -static const struct platform_device_id jz4740_rtc_ids[] = { - { "jz4740-rtc", ID_JZ4740 }, - { "jz4780-rtc", ID_JZ4780 }, - {} -}; -MODULE_DEVICE_TABLE(platform, jz4740_rtc_ids); - static struct platform_driver jz4740_rtc_driver = { .probe = jz4740_rtc_probe, .driver = { .name = "jz4740-rtc", - .of_match_table = of_match_ptr(jz4740_rtc_of_match), + .of_match_table = jz4740_rtc_of_match, }, - .id_table = jz4740_rtc_ids, }; module_platform_driver(jz4740_rtc_driver); diff --git a/drivers/rtc/rtc-lpc24xx.c b/drivers/rtc/rtc-lpc24xx.c index 00ef16ba9480..eec881a81067 100644 --- a/drivers/rtc/rtc-lpc24xx.c +++ b/drivers/rtc/rtc-lpc24xx.c @@ -205,10 +205,8 @@ static int lpc24xx_rtc_probe(struct platform_device *pdev) return PTR_ERR(rtc->rtc_base); irq = platform_get_irq(pdev, 0); - if (irq < 0) { - dev_warn(&pdev->dev, "can't get interrupt resource\n"); + if (irq < 0) return irq; - } rtc->clk_rtc = devm_clk_get(&pdev->dev, "rtc"); if (IS_ERR(rtc->clk_rtc)) { diff --git a/drivers/rtc/rtc-max77686.c b/drivers/rtc/rtc-max77686.c index d5a0e27dd0a0..03ebcf1c0f3d 100644 --- a/drivers/rtc/rtc-max77686.c +++ b/drivers/rtc/rtc-max77686.c @@ -78,6 +78,8 @@ struct max77686_rtc_driver_data { int alarm_pending_status_reg; /* RTC IRQ CHIP for regmap */ const struct regmap_irq_chip *rtc_irq_chip; + /* regmap configuration for the chip */ + const struct regmap_config *regmap_config; }; struct max77686_rtc_info { @@ -182,6 +184,11 @@ static const struct regmap_irq_chip max77686_rtc_irq_chip = { .num_irqs = ARRAY_SIZE(max77686_rtc_irqs), }; +static const struct regmap_config max77686_rtc_regmap_config = { + .reg_bits = 8, + .val_bits = 8, +}; + static const struct max77686_rtc_driver_data max77686_drv_data = { .delay = 16000, .mask = 0x7f, @@ -191,6 +198,13 @@ static const struct max77686_rtc_driver_data max77686_drv_data = { .alarm_pending_status_reg = MAX77686_REG_STATUS2, .rtc_i2c_addr = MAX77686_I2C_ADDR_RTC, .rtc_irq_chip = &max77686_rtc_irq_chip, + .regmap_config = &max77686_rtc_regmap_config, +}; + +static const struct regmap_config max77620_rtc_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .use_single_write = true, }; static const struct max77686_rtc_driver_data max77620_drv_data = { @@ -202,6 +216,7 @@ static const struct max77686_rtc_driver_data max77620_drv_data = { .alarm_pending_status_reg = MAX77686_INVALID_REG, .rtc_i2c_addr = MAX77620_I2C_ADDR_RTC, .rtc_irq_chip = &max77686_rtc_irq_chip, + .regmap_config = &max77620_rtc_regmap_config, }; static const unsigned int max77802_map[REG_RTC_END] = { @@ -658,11 +673,6 @@ static int max77686_rtc_init_reg(struct max77686_rtc_info *info) return ret; } -static const struct regmap_config max77686_rtc_regmap_config = { - .reg_bits = 8, - .val_bits = 8, -}; - static int max77686_init_rtc_regmap(struct max77686_rtc_info *info) { struct device *parent = info->dev->parent; @@ -698,7 +708,7 @@ static int max77686_init_rtc_regmap(struct max77686_rtc_info *info) } info->rtc_regmap = devm_regmap_init_i2c(info->rtc, - &max77686_rtc_regmap_config); + info->drv_data->regmap_config); if (IS_ERR(info->rtc_regmap)) { ret = PTR_ERR(info->rtc_regmap); dev_err(info->dev, "Failed to allocate RTC regmap: %d\n", ret); diff --git a/drivers/rtc/rtc-mc13xxx.c b/drivers/rtc/rtc-mc13xxx.c index afce2c0b4bd6..d6802e6191cb 100644 --- a/drivers/rtc/rtc-mc13xxx.c +++ b/drivers/rtc/rtc-mc13xxx.c @@ -308,8 +308,10 @@ static int __init mc13xxx_rtc_probe(struct platform_device *pdev) mc13xxx_unlock(mc13xxx); ret = rtc_register_device(priv->rtc); - if (ret) + if (ret) { + mc13xxx_lock(mc13xxx); goto err_irq_request; + } return 0; diff --git a/drivers/rtc/rtc-mpc5121.c b/drivers/rtc/rtc-mpc5121.c index 3040844129ce..5c2ce71aa044 100644 --- a/drivers/rtc/rtc-mpc5121.c +++ b/drivers/rtc/rtc-mpc5121.c @@ -316,7 +316,7 @@ static int mpc5121_rtc_probe(struct platform_device *op) rtc->regs = devm_platform_ioremap_resource(op, 0); if (IS_ERR(rtc->regs)) { dev_err(&op->dev, "%s: couldn't map io space\n", __func__); - return -ENOSYS; + return PTR_ERR(rtc->regs); } device_init_wakeup(&op->dev, 1); diff --git a/drivers/rtc/rtc-mt2712.c b/drivers/rtc/rtc-mt2712.c index 581b8731fb8a..d5f691c8a035 100644 --- a/drivers/rtc/rtc-mt2712.c +++ b/drivers/rtc/rtc-mt2712.c @@ -310,7 +310,6 @@ static const struct rtc_class_ops mt2712_rtc_ops = { static int mt2712_rtc_probe(struct platform_device *pdev) { - struct resource *res; struct mt2712_rtc *mt2712_rtc; int ret; @@ -319,8 +318,7 @@ static int mt2712_rtc_probe(struct platform_device *pdev) if (!mt2712_rtc) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - mt2712_rtc->base = devm_ioremap_resource(&pdev->dev, res); + mt2712_rtc->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(mt2712_rtc->base)) return PTR_ERR(mt2712_rtc->base); @@ -328,10 +326,8 @@ static int mt2712_rtc_probe(struct platform_device *pdev) mt2712_rtc_hw_init(mt2712_rtc); mt2712_rtc->irq = platform_get_irq(pdev, 0); - if (mt2712_rtc->irq < 0) { - dev_err(&pdev->dev, "No IRQ resource\n"); + if (mt2712_rtc->irq < 0) return mt2712_rtc->irq; - } platform_set_drvdata(pdev, mt2712_rtc); @@ -356,13 +352,7 @@ static int mt2712_rtc_probe(struct platform_device *pdev) mt2712_rtc->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; mt2712_rtc->rtc->range_max = MT2712_RTC_TIMESTAMP_END_2127; - ret = rtc_register_device(mt2712_rtc->rtc); - if (ret) { - dev_err(&pdev->dev, "register rtc device failed\n"); - return ret; - } - - return 0; + return rtc_register_device(mt2712_rtc->rtc); } #ifdef CONFIG_PM_SLEEP diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c index 4e50d6768f13..9c5670776c68 100644 --- a/drivers/rtc/rtc-pcf2127.c +++ b/drivers/rtc/rtc-pcf2127.c @@ -137,8 +137,7 @@ static int pcf2127_rtc_read_time(struct device *dev, struct rtc_time *tm) tm->tm_wday = buf[PCF2127_REG_DW] & 0x07; tm->tm_mon = bcd2bin(buf[PCF2127_REG_MO] & 0x1F) - 1; /* rtc mn 1-12 */ tm->tm_year = bcd2bin(buf[PCF2127_REG_YR]); - if (tm->tm_year < 70) - tm->tm_year += 100; /* assume we are in 1970...2069 */ + tm->tm_year += 100; dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " "mday=%d, mon=%d, year=%d, wday=%d\n", @@ -172,7 +171,7 @@ static int pcf2127_rtc_set_time(struct device *dev, struct rtc_time *tm) buf[i++] = bin2bcd(tm->tm_mon + 1); /* year */ - buf[i++] = bin2bcd(tm->tm_year % 100); + buf[i++] = bin2bcd(tm->tm_year - 100); /* write register's data */ err = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_SC, buf, i); @@ -185,30 +184,35 @@ static int pcf2127_rtc_set_time(struct device *dev, struct rtc_time *tm) return 0; } -#ifdef CONFIG_RTC_INTF_DEV static int pcf2127_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) { struct pcf2127 *pcf2127 = dev_get_drvdata(dev); - int touser; + int val, touser = 0; int ret; switch (cmd) { case RTC_VL_READ: - ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL3, &touser); + ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL3, &val); if (ret) return ret; - touser = touser & PCF2127_BIT_CTRL3_BLF ? RTC_VL_BACKUP_LOW : 0; + if (val & PCF2127_BIT_CTRL3_BLF) + touser |= RTC_VL_BACKUP_LOW; + + if (val & PCF2127_BIT_CTRL3_BF) + touser |= RTC_VL_BACKUP_SWITCH; return put_user(touser, (unsigned int __user *)arg); + + case RTC_VL_CLR: + return regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, + PCF2127_BIT_CTRL3_BF, 0); + default: return -ENOIOCTLCMD; } } -#else -#define pcf2127_rtc_ioctl NULL -#endif static const struct rtc_class_ops pcf2127_rtc_ops = { .ioctl = pcf2127_rtc_ioctl, @@ -433,6 +437,9 @@ static int pcf2127_probe(struct device *dev, struct regmap *regmap, return PTR_ERR(pcf2127->rtc); pcf2127->rtc->ops = &pcf2127_rtc_ops; + pcf2127->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; + pcf2127->rtc->range_max = RTC_TIMESTAMP_END_2099; + pcf2127->rtc->set_start_time = true; /* Sets actual start to 1970 */ pcf2127->wdd.parent = dev; pcf2127->wdd.info = &pcf2127_wdt_info; @@ -441,6 +448,7 @@ static int pcf2127_probe(struct device *dev, struct regmap *regmap, pcf2127->wdd.max_timeout = PCF2127_WD_VAL_MAX; pcf2127->wdd.timeout = PCF2127_WD_VAL_DEFAULT; pcf2127->wdd.min_hw_heartbeat_ms = 500; + pcf2127->wdd.status = WATCHDOG_NOWAYOUT_INIT_STATUS; watchdog_set_drvdata(&pcf2127->wdd, pcf2127); @@ -495,7 +503,6 @@ static int pcf2127_probe(struct device *dev, struct regmap *regmap, */ ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, PCF2127_BIT_CTRL3_BTSE | - PCF2127_BIT_CTRL3_BF | PCF2127_BIT_CTRL3_BIE | PCF2127_BIT_CTRL3_BLIE, 0); if (ret) { @@ -636,6 +643,7 @@ static int pcf2127_i2c_probe(struct i2c_client *client, static const struct regmap_config config = { .reg_bits = 8, .val_bits = 8, + .max_register = 0x1d, }; if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) @@ -703,6 +711,7 @@ static int pcf2127_spi_probe(struct spi_device *spi) .val_bits = 8, .read_flag_mask = 0xa0, .write_flag_mask = 0x20, + .max_register = 0x1d, }; struct regmap *regmap; diff --git a/drivers/rtc/rtc-rc5t619.c b/drivers/rtc/rtc-rc5t619.c index 24e386ecbc7e..dd1a20977478 100644 --- a/drivers/rtc/rtc-rc5t619.c +++ b/drivers/rtc/rtc-rc5t619.c @@ -356,10 +356,8 @@ static int rc5t619_rtc_probe(struct platform_device *pdev) int err; rtc = devm_kzalloc(dev, sizeof(*rtc), GFP_KERNEL); - if (IS_ERR(rtc)) { - err = PTR_ERR(rtc); + if (!rtc) return -ENOMEM; - } rtc->rn5t618 = rn5t618; diff --git a/drivers/rtc/rtc-rv3028.c b/drivers/rtc/rtc-rv3028.c index a0ddc86c975a..ec84db0b3d7a 100644 --- a/drivers/rtc/rtc-rv3028.c +++ b/drivers/rtc/rtc-rv3028.c @@ -755,6 +755,8 @@ static int rv3028_probe(struct i2c_client *client) return -ENOMEM; rv3028->regmap = devm_regmap_init_i2c(client, ®map_config); + if (IS_ERR(rv3028->regmap)) + return PTR_ERR(rv3028->regmap); i2c_set_clientdata(client, rv3028); diff --git a/drivers/rtc/rtc-snvs.c b/drivers/rtc/rtc-snvs.c index 35ee08aa7584..0263d996b8a8 100644 --- a/drivers/rtc/rtc-snvs.c +++ b/drivers/rtc/rtc-snvs.c @@ -148,10 +148,21 @@ static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable) static int snvs_rtc_read_time(struct device *dev, struct rtc_time *tm) { struct snvs_rtc_data *data = dev_get_drvdata(dev); - unsigned long time = rtc_read_lp_counter(data); + unsigned long time; + int ret; + if (data->clk) { + ret = clk_enable(data->clk); + if (ret) + return ret; + } + + time = rtc_read_lp_counter(data); rtc_time64_to_tm(time, tm); + if (data->clk) + clk_disable(data->clk); + return 0; } @@ -161,6 +172,12 @@ static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm) unsigned long time = rtc_tm_to_time64(tm); int ret; + if (data->clk) { + ret = clk_enable(data->clk); + if (ret) + return ret; + } + /* Disable RTC first */ ret = snvs_rtc_enable(data, false); if (ret) @@ -173,6 +190,9 @@ static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm) /* Enable RTC again */ ret = snvs_rtc_enable(data, true); + if (data->clk) + clk_disable(data->clk); + return ret; } @@ -180,6 +200,13 @@ static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) { struct snvs_rtc_data *data = dev_get_drvdata(dev); u32 lptar, lpsr; + int ret; + + if (data->clk) { + ret = clk_enable(data->clk); + if (ret) + return ret; + } regmap_read(data->regmap, data->offset + SNVS_LPTAR, &lptar); rtc_time64_to_tm(lptar, &alrm->time); @@ -187,18 +214,33 @@ static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr); alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0; + if (data->clk) + clk_disable(data->clk); + return 0; } static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable) { struct snvs_rtc_data *data = dev_get_drvdata(dev); + int ret; + + if (data->clk) { + ret = clk_enable(data->clk); + if (ret) + return ret; + } regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN), enable ? (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN) : 0); - return rtc_write_sync_lp(data); + ret = rtc_write_sync_lp(data); + + if (data->clk) + clk_disable(data->clk); + + return ret; } static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) @@ -207,6 +249,12 @@ static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) unsigned long time = rtc_tm_to_time64(&alrm->time); int ret; + if (data->clk) { + ret = clk_enable(data->clk); + if (ret) + return ret; + } + regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_LPTA_EN, 0); ret = rtc_write_sync_lp(data); if (ret) @@ -216,6 +264,9 @@ static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) /* Clear alarm interrupt status bit */ regmap_write(data->regmap, data->offset + SNVS_LPSR, SNVS_LPSR_LPTA); + if (data->clk) + clk_disable(data->clk); + return snvs_rtc_alarm_irq_enable(dev, alrm->enabled); } @@ -362,7 +413,7 @@ static int __maybe_unused snvs_rtc_suspend_noirq(struct device *dev) struct snvs_rtc_data *data = dev_get_drvdata(dev); if (data->clk) - clk_disable_unprepare(data->clk); + clk_disable(data->clk); return 0; } @@ -372,7 +423,7 @@ static int __maybe_unused snvs_rtc_resume_noirq(struct device *dev) struct snvs_rtc_data *data = dev_get_drvdata(dev); if (data->clk) - return clk_prepare_enable(data->clk); + return clk_enable(data->clk); return 0; } diff --git a/drivers/rtc/rtc-stmp3xxx.c b/drivers/rtc/rtc-stmp3xxx.c index ff6488be385f..c9bc3d4a1e66 100644 --- a/drivers/rtc/rtc-stmp3xxx.c +++ b/drivers/rtc/rtc-stmp3xxx.c @@ -416,5 +416,5 @@ module_platform_driver(stmp3xxx_rtcdrv); MODULE_DESCRIPTION("STMP3xxx RTC Driver"); MODULE_AUTHOR("dmitry pervushin and " - "Wolfram Sang "); + "Wolfram Sang "); MODULE_LICENSE("GPL"); diff --git a/drivers/slimbus/core.c b/drivers/slimbus/core.c index 526e3215d8fe..ae1e248a8fb8 100644 --- a/drivers/slimbus/core.c +++ b/drivers/slimbus/core.c @@ -162,9 +162,8 @@ static int slim_add_device(struct slim_controller *ctrl, sbdev->ctrl = ctrl; INIT_LIST_HEAD(&sbdev->stream_list); spin_lock_init(&sbdev->stream_list_lock); - - if (node) - sbdev->dev.of_node = of_node_get(node); + sbdev->dev.of_node = of_node_get(node); + sbdev->dev.fwnode = of_fwnode_handle(node); dev_set_name(&sbdev->dev, "%x:%x:%x:%x", sbdev->e_addr.manf_id, @@ -283,6 +282,7 @@ EXPORT_SYMBOL_GPL(slim_register_controller); /* slim_remove_device: Remove the effect of slim_add_device() */ static void slim_remove_device(struct slim_device *sbdev) { + of_node_put(sbdev->dev.of_node); device_unregister(&sbdev->dev); } diff --git a/drivers/slimbus/qcom-ngd-ctrl.c b/drivers/slimbus/qcom-ngd-ctrl.c index fc2575fef51b..743ee7b4e63f 100644 --- a/drivers/slimbus/qcom-ngd-ctrl.c +++ b/drivers/slimbus/qcom-ngd-ctrl.c @@ -1361,12 +1361,10 @@ static int of_qcom_slim_ngd_register(struct device *parent, ngd->pdev->driver_override = QCOM_SLIM_NGD_DRV_NAME; ngd->pdev->dev.of_node = node; ctrl->ngd = ngd; - platform_set_drvdata(ngd->pdev, ctrl); platform_device_add(ngd->pdev); ngd->base = ctrl->base + ngd->id * data->offset + (ngd->id - 1) * data->size; - ctrl->ngd = ngd; return 0; } @@ -1376,12 +1374,13 @@ static int of_qcom_slim_ngd_register(struct device *parent, static int qcom_slim_ngd_probe(struct platform_device *pdev) { - struct qcom_slim_ngd_ctrl *ctrl = platform_get_drvdata(pdev); struct device *dev = &pdev->dev; + struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev->parent); int ret; ctrl->ctrl.dev = dev; + platform_set_drvdata(pdev, ctrl); pm_runtime_use_autosuspend(dev); pm_runtime_set_autosuspend_delay(dev, QCOM_SLIM_NGD_AUTOSUSPEND); pm_runtime_set_suspended(dev); diff --git a/drivers/soc/xilinx/zynqmp_pm_domains.c b/drivers/soc/xilinx/zynqmp_pm_domains.c index 23d90cb12ba9..226d343f0a6a 100644 --- a/drivers/soc/xilinx/zynqmp_pm_domains.c +++ b/drivers/soc/xilinx/zynqmp_pm_domains.c @@ -23,8 +23,6 @@ /* Flag stating if PM nodes mapped to the PM domain has been requested */ #define ZYNQMP_PM_DOMAIN_REQUESTED BIT(0) -static const struct zynqmp_eemi_ops *eemi_ops; - static int min_capability; /** @@ -76,11 +74,8 @@ static int zynqmp_gpd_power_on(struct generic_pm_domain *domain) int ret; struct zynqmp_pm_domain *pd; - if (!eemi_ops->set_requirement) - return -ENXIO; - pd = container_of(domain, struct zynqmp_pm_domain, gpd); - ret = eemi_ops->set_requirement(pd->node_id, + ret = zynqmp_pm_set_requirement(pd->node_id, ZYNQMP_PM_CAPABILITY_ACCESS, ZYNQMP_PM_MAX_QOS, ZYNQMP_PM_REQUEST_ACK_BLOCKING); @@ -111,9 +106,6 @@ static int zynqmp_gpd_power_off(struct generic_pm_domain *domain) u32 capabilities = min_capability; bool may_wakeup; - if (!eemi_ops->set_requirement) - return -ENXIO; - pd = container_of(domain, struct zynqmp_pm_domain, gpd); /* If domain is already released there is nothing to be done */ @@ -134,7 +126,7 @@ static int zynqmp_gpd_power_off(struct generic_pm_domain *domain) } } - ret = eemi_ops->set_requirement(pd->node_id, capabilities, 0, + ret = zynqmp_pm_set_requirement(pd->node_id, capabilities, 0, ZYNQMP_PM_REQUEST_ACK_NO); /** * If powering down of any node inside this domain fails, @@ -163,16 +155,13 @@ static int zynqmp_gpd_attach_dev(struct generic_pm_domain *domain, int ret; struct zynqmp_pm_domain *pd; - if (!eemi_ops->request_node) - return -ENXIO; - pd = container_of(domain, struct zynqmp_pm_domain, gpd); /* If this is not the first device to attach there is nothing to do */ if (domain->device_count) return 0; - ret = eemi_ops->request_node(pd->node_id, 0, 0, + ret = zynqmp_pm_request_node(pd->node_id, 0, 0, ZYNQMP_PM_REQUEST_ACK_BLOCKING); /* If requesting a node fails print and return the error */ if (ret) { @@ -199,16 +188,13 @@ static void zynqmp_gpd_detach_dev(struct generic_pm_domain *domain, int ret; struct zynqmp_pm_domain *pd; - if (!eemi_ops->release_node) - return; - pd = container_of(domain, struct zynqmp_pm_domain, gpd); /* If this is not the last device to detach there is nothing to do */ if (domain->device_count) return; - ret = eemi_ops->release_node(pd->node_id); + ret = zynqmp_pm_release_node(pd->node_id); /* If releasing a node fails print the error and return */ if (ret) { pr_err("%s() %s release failed for node %d: %d\n", @@ -266,10 +252,6 @@ static int zynqmp_gpd_probe(struct platform_device *pdev) struct zynqmp_pm_domain *pd; struct device *dev = &pdev->dev; - eemi_ops = zynqmp_pm_get_eemi_ops(); - if (IS_ERR(eemi_ops)) - return PTR_ERR(eemi_ops); - pd = devm_kcalloc(dev, ZYNQMP_NUM_DOMAINS, sizeof(*pd), GFP_KERNEL); if (!pd) return -ENOMEM; diff --git a/drivers/soc/xilinx/zynqmp_power.c b/drivers/soc/xilinx/zynqmp_power.c index 09227895d216..31ff49fcd078 100644 --- a/drivers/soc/xilinx/zynqmp_power.c +++ b/drivers/soc/xilinx/zynqmp_power.c @@ -30,7 +30,6 @@ struct zynqmp_pm_work_struct { static struct zynqmp_pm_work_struct *zynqmp_pm_init_suspend_work; static struct mbox_chan *rx_chan; -static const struct zynqmp_eemi_ops *eemi_ops; enum pm_suspend_mode { PM_SUSPEND_MODE_FIRST = 0, @@ -155,9 +154,6 @@ static ssize_t suspend_mode_store(struct device *dev, { int md, ret = -EINVAL; - if (!eemi_ops->set_suspend_mode) - return ret; - for (md = PM_SUSPEND_MODE_FIRST; md < ARRAY_SIZE(suspend_modes); md++) if (suspend_modes[md] && sysfs_streq(suspend_modes[md], buf)) { @@ -166,7 +162,7 @@ static ssize_t suspend_mode_store(struct device *dev, } if (!ret && md != suspend_mode) { - ret = eemi_ops->set_suspend_mode(md); + ret = zynqmp_pm_set_suspend_mode(md); if (likely(!ret)) suspend_mode = md; } @@ -182,15 +178,8 @@ static int zynqmp_pm_probe(struct platform_device *pdev) u32 pm_api_version; struct mbox_client *client; - eemi_ops = zynqmp_pm_get_eemi_ops(); - if (IS_ERR(eemi_ops)) - return PTR_ERR(eemi_ops); - - if (!eemi_ops->get_api_version || !eemi_ops->init_finalize) - return -ENXIO; - - eemi_ops->init_finalize(); - eemi_ops->get_api_version(&pm_api_version); + zynqmp_pm_init_finalize(); + zynqmp_pm_get_api_version(&pm_api_version); /* Check PM API version number */ if (pm_api_version < ZYNQMP_PM_VERSION) diff --git a/drivers/soundwire/Makefile b/drivers/soundwire/Makefile index e2cdff990e9f..b5871612613b 100644 --- a/drivers/soundwire/Makefile +++ b/drivers/soundwire/Makefile @@ -4,7 +4,8 @@ # #Bus Objs -soundwire-bus-objs := bus_type.o bus.o slave.o mipi_disco.o stream.o +soundwire-bus-objs := bus_type.o bus.o master.o slave.o mipi_disco.o stream.o \ + sysfs_slave.o sysfs_slave_dpn.o obj-$(CONFIG_SOUNDWIRE) += soundwire-bus.o ifdef CONFIG_DEBUG_FS @@ -16,12 +17,9 @@ soundwire-cadence-objs := cadence_master.o obj-$(CONFIG_SOUNDWIRE_CADENCE) += soundwire-cadence.o #Intel driver -soundwire-intel-objs := intel.o +soundwire-intel-objs := intel.o intel_init.o obj-$(CONFIG_SOUNDWIRE_INTEL) += soundwire-intel.o -soundwire-intel-init-objs := intel_init.o -obj-$(CONFIG_SOUNDWIRE_INTEL) += soundwire-intel-init.o - #Qualcomm driver soundwire-qcom-objs := qcom.o obj-$(CONFIG_SOUNDWIRE_QCOM) += soundwire-qcom.o diff --git a/drivers/soundwire/bus.c b/drivers/soundwire/bus.c index 488c3c9e4947..24ba77226376 100644 --- a/drivers/soundwire/bus.c +++ b/drivers/soundwire/bus.c @@ -8,24 +8,54 @@ #include #include #include "bus.h" +#include "sysfs_local.h" + +static DEFINE_IDA(sdw_ida); + +static int sdw_get_id(struct sdw_bus *bus) +{ + int rc = ida_alloc(&sdw_ida, GFP_KERNEL); + + if (rc < 0) + return rc; + + bus->id = rc; + return 0; +} /** - * sdw_add_bus_master() - add a bus Master instance + * sdw_bus_master_add() - add a bus Master instance * @bus: bus instance + * @parent: parent device + * @fwnode: firmware node handle * * Initializes the bus instance, read properties and create child * devices. */ -int sdw_add_bus_master(struct sdw_bus *bus) +int sdw_bus_master_add(struct sdw_bus *bus, struct device *parent, + struct fwnode_handle *fwnode) { struct sdw_master_prop *prop = NULL; int ret; - if (!bus->dev) { - pr_err("SoundWire bus has no device\n"); + if (!parent) { + pr_err("SoundWire parent device is not set\n"); return -ENODEV; } + ret = sdw_get_id(bus); + if (ret) { + dev_err(parent, "Failed to get bus id\n"); + return ret; + } + + ret = sdw_master_device_add(bus, parent, fwnode); + if (ret) { + dev_err(parent, "Failed to add master device at link %d\n", + bus->link_id); + return ret; + } + if (!bus->ops) { dev_err(bus->dev, "SoundWire Bus ops are not set\n"); return -EINVAL; @@ -107,7 +137,7 @@ int sdw_add_bus_master(struct sdw_bus *bus) return 0; } -EXPORT_SYMBOL(sdw_add_bus_master); +EXPORT_SYMBOL(sdw_bus_master_add); static int sdw_delete_slave(struct device *dev, void *data) { @@ -131,18 +161,20 @@ static int sdw_delete_slave(struct device *dev, void *data) } /** - * sdw_delete_bus_master() - delete the bus master instance + * sdw_bus_master_delete() - delete the bus master instance * @bus: bus to be deleted * * Remove the instance, delete the child devices. */ -void sdw_delete_bus_master(struct sdw_bus *bus) +void sdw_bus_master_delete(struct sdw_bus *bus) { device_for_each_child(bus->dev, NULL, sdw_delete_slave); + sdw_master_device_del(bus); sdw_bus_debugfs_exit(bus); + ida_free(&sdw_ida, bus->id); } -EXPORT_SYMBOL(sdw_delete_bus_master); +EXPORT_SYMBOL(sdw_bus_master_delete); /* * SDW IO Calls @@ -284,9 +316,10 @@ int sdw_fill_msg(struct sdw_msg *msg, struct sdw_slave *slave, msg->flags = flags; msg->buf = buf; - if (addr < SDW_REG_NO_PAGE) { /* no paging area */ + if (addr < SDW_REG_NO_PAGE) /* no paging area */ return 0; - } else if (addr >= SDW_REG_MAX) { /* illegal addr */ + + if (addr >= SDW_REG_MAX) { /* illegal addr */ pr_err("SDW: Invalid address %x passed\n", addr); return -EINVAL; } @@ -306,7 +339,9 @@ int sdw_fill_msg(struct sdw_msg *msg, struct sdw_slave *slave, if (!slave) { pr_err("SDW: No slave for paging addr\n"); return -EINVAL; - } else if (!slave->prop.paging_support) { + } + + if (!slave->prop.paging_support) { dev_err(&slave->dev, "address %x needs paging but no support\n", addr); return -EINVAL; @@ -375,8 +410,8 @@ sdw_bread_no_pm(struct sdw_bus *bus, u16 dev_num, u32 addr) ret = sdw_transfer(bus, &msg); if (ret < 0) return ret; - else - return buf; + + return buf; } static int @@ -471,8 +506,8 @@ int sdw_read(struct sdw_slave *slave, u32 addr) ret = sdw_nread(slave, addr, 1, &buf); if (ret < 0) return ret; - else - return buf; + + return buf; } EXPORT_SYMBOL(sdw_read); @@ -563,9 +598,9 @@ static int sdw_assign_device_num(struct sdw_slave *slave) } if (!new_device) - dev_info(slave->bus->dev, - "Slave already registered, reusing dev_num:%d\n", - slave->dev_num); + dev_dbg(slave->bus->dev, + "Slave already registered, reusing dev_num:%d\n", + slave->dev_num); /* Clear the slave->dev_num to transfer message on device 0 */ dev_num = slave->dev_num; diff --git a/drivers/soundwire/bus.h b/drivers/soundwire/bus.h index 204204a26db8..82484f741168 100644 --- a/drivers/soundwire/bus.h +++ b/drivers/soundwire/bus.h @@ -19,6 +19,9 @@ static inline int sdw_acpi_find_slaves(struct sdw_bus *bus) int sdw_of_find_slaves(struct sdw_bus *bus); void sdw_extract_slave_id(struct sdw_bus *bus, u64 addr, struct sdw_slave_id *id); +int sdw_master_device_add(struct sdw_bus *bus, struct device *parent, + struct fwnode_handle *fwnode); +int sdw_master_device_del(struct sdw_bus *bus); #ifdef CONFIG_DEBUG_FS void sdw_bus_debugfs_init(struct sdw_bus *bus); @@ -172,5 +175,6 @@ sdw_update(struct sdw_slave *slave, u32 addr, u8 mask, u8 val) #define SDW_UNATTACH_REQUEST_MASTER_RESET BIT(0) void sdw_clear_slave_status(struct sdw_bus *bus, u32 request); +int sdw_slave_modalias(const struct sdw_slave *slave, char *buf, size_t size); #endif /* __SDW_BUS_H */ diff --git a/drivers/soundwire/bus_type.c b/drivers/soundwire/bus_type.c index 17f096dd6806..de9a671802b8 100644 --- a/drivers/soundwire/bus_type.c +++ b/drivers/soundwire/bus_type.c @@ -7,6 +7,7 @@ #include #include #include "bus.h" +#include "sysfs_local.h" /** * sdw_get_device_id - find the matching SoundWire device id @@ -33,10 +34,17 @@ sdw_get_device_id(struct sdw_slave *slave, struct sdw_driver *drv) static int sdw_bus_match(struct device *dev, struct device_driver *ddrv) { - struct sdw_slave *slave = dev_to_sdw_dev(dev); - struct sdw_driver *drv = drv_to_sdw_driver(ddrv); + struct sdw_slave *slave; + struct sdw_driver *drv; + int ret = 0; - return !!sdw_get_device_id(slave, drv); + if (is_sdw_slave(dev)) { + slave = dev_to_sdw_dev(dev); + drv = drv_to_sdw_driver(ddrv); + + ret = !!sdw_get_device_id(slave, drv); + } + return ret; } int sdw_slave_modalias(const struct sdw_slave *slave, char *buf, size_t size) @@ -47,7 +55,7 @@ int sdw_slave_modalias(const struct sdw_slave *slave, char *buf, size_t size) slave->id.mfg_id, slave->id.part_id); } -static int sdw_uevent(struct device *dev, struct kobj_uevent_env *env) +int sdw_slave_uevent(struct device *dev, struct kobj_uevent_env *env) { struct sdw_slave *slave = dev_to_sdw_dev(dev); char modalias[32]; @@ -63,7 +71,6 @@ static int sdw_uevent(struct device *dev, struct kobj_uevent_env *env) struct bus_type sdw_bus_type = { .name = "soundwire", .match = sdw_bus_match, - .uevent = sdw_uevent, }; EXPORT_SYMBOL_GPL(sdw_bus_type); @@ -98,6 +105,11 @@ static int sdw_drv_probe(struct device *dev) if (slave->ops && slave->ops->read_prop) slave->ops->read_prop(slave); + /* init the sysfs as we have properties now */ + ret = sdw_slave_sysfs_init(slave); + if (ret < 0) + dev_warn(dev, "Slave sysfs init failed:%d\n", ret); + /* * Check for valid clk_stop_timeout, use DisCo worst case value of * 300ms diff --git a/drivers/soundwire/cadence_master.c b/drivers/soundwire/cadence_master.c index ecd357d1c63d..9ea87538b9ef 100644 --- a/drivers/soundwire/cadence_master.c +++ b/drivers/soundwire/cadence_master.c @@ -407,7 +407,9 @@ cdns_fill_msg_resp(struct sdw_cdns *cdns, if (nack) { dev_err_ratelimited(cdns->dev, "Msg NACKed for Slave %d\n", msg->dev_num); return SDW_CMD_FAIL; - } else if (no_ack) { + } + + if (no_ack) { dev_dbg_ratelimited(cdns->dev, "Msg ignored for Slave %d\n", msg->dev_num); return SDW_CMD_IGNORED; } @@ -520,7 +522,9 @@ cdns_program_scp_addr(struct sdw_cdns *cdns, struct sdw_msg *msg) dev_err_ratelimited(cdns->dev, "SCP_addrpage NACKed for Slave %d\n", msg->dev_num); return SDW_CMD_FAIL; - } else if (no_ack) { + } + + if (no_ack) { dev_dbg_ratelimited(cdns->dev, "SCP_addrpage ignored for Slave %d\n", msg->dev_num); return SDW_CMD_IGNORED; diff --git a/drivers/soundwire/debugfs.c b/drivers/soundwire/debugfs.c index fb1140e82b86..b6cad0d59b7b 100644 --- a/drivers/soundwire/debugfs.c +++ b/drivers/soundwire/debugfs.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only // Copyright(c) 2017-2019 Intel Corporation. #include diff --git a/drivers/soundwire/intel.c b/drivers/soundwire/intel.c index ed8d576bf5dc..4cfdd074e310 100644 --- a/drivers/soundwire/intel.c +++ b/drivers/soundwire/intel.c @@ -1099,7 +1099,6 @@ static int intel_probe(struct platform_device *pdev) sdw->cdns.registers = sdw->link_res->registers; sdw->cdns.instance = sdw->instance; sdw->cdns.msg_count = 0; - sdw->cdns.bus.dev = &pdev->dev; sdw->cdns.bus.link_id = pdev->id; sdw_cdns_probe(&sdw->cdns); @@ -1110,9 +1109,9 @@ static int intel_probe(struct platform_device *pdev) platform_set_drvdata(pdev, sdw); - ret = sdw_add_bus_master(&sdw->cdns.bus); + ret = sdw_bus_master_add(&sdw->cdns.bus, &pdev->dev, pdev->dev.fwnode); if (ret) { - dev_err(&pdev->dev, "sdw_add_bus_master fail: %d\n", ret); + dev_err(&pdev->dev, "sdw_bus_master_add fail: %d\n", ret); return ret; } @@ -1173,7 +1172,7 @@ err_interrupt: sdw_cdns_enable_interrupt(&sdw->cdns, false); free_irq(sdw->link_res->irq, sdw); err_init: - sdw_delete_bus_master(&sdw->cdns.bus); + sdw_bus_master_delete(&sdw->cdns.bus); return ret; } @@ -1189,7 +1188,7 @@ static int intel_remove(struct platform_device *pdev) free_irq(sdw->link_res->irq, sdw); snd_soc_unregister_component(sdw->cdns.dev); } - sdw_delete_bus_master(&sdw->cdns.bus); + sdw_bus_master_delete(&sdw->cdns.bus); return 0; } diff --git a/drivers/soundwire/intel_init.c b/drivers/soundwire/intel_init.c index 4b769409f6f8..d5d42795a48f 100644 --- a/drivers/soundwire/intel_init.c +++ b/drivers/soundwire/intel_init.c @@ -86,7 +86,9 @@ static struct sdw_intel_ctx dev_err(&adev->dev, "Link count %d exceeds max %d\n", count, SDW_MAX_LINKS); return NULL; - } else if (!count) { + } + + if (!count) { dev_warn(&adev->dev, "No SoundWire links detected\n"); return NULL; } diff --git a/drivers/soundwire/master.c b/drivers/soundwire/master.c new file mode 100644 index 000000000000..5f0b2189defe --- /dev/null +++ b/drivers/soundwire/master.c @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright(c) 2019-2020 Intel Corporation. + +#include +#include +#include +#include +#include +#include "bus.h" + +/* + * The sysfs for properties reflects the MIPI description as given + * in the MIPI DisCo spec + * + * Base file is: + * sdw-master-N + * |---- revision + * |---- clk_stop_modes + * |---- max_clk_freq + * |---- clk_freq + * |---- clk_gears + * |---- default_row + * |---- default_col + * |---- dynamic_shape + * |---- err_threshold + */ + +#define sdw_master_attr(field, format_string) \ +static ssize_t field##_show(struct device *dev, \ + struct device_attribute *attr, \ + char *buf) \ +{ \ + struct sdw_master_device *md = dev_to_sdw_master_device(dev); \ + return sprintf(buf, format_string, md->bus->prop.field); \ +} \ +static DEVICE_ATTR_RO(field) + +sdw_master_attr(revision, "0x%x\n"); +sdw_master_attr(clk_stop_modes, "0x%x\n"); +sdw_master_attr(max_clk_freq, "%d\n"); +sdw_master_attr(default_row, "%d\n"); +sdw_master_attr(default_col, "%d\n"); +sdw_master_attr(default_frame_rate, "%d\n"); +sdw_master_attr(dynamic_frame, "%d\n"); +sdw_master_attr(err_threshold, "%d\n"); + +static ssize_t clock_frequencies_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sdw_master_device *md = dev_to_sdw_master_device(dev); + ssize_t size = 0; + int i; + + for (i = 0; i < md->bus->prop.num_clk_freq; i++) + size += sprintf(buf + size, "%8d ", + md->bus->prop.clk_freq[i]); + size += sprintf(buf + size, "\n"); + + return size; +} +static DEVICE_ATTR_RO(clock_frequencies); + +static ssize_t clock_gears_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sdw_master_device *md = dev_to_sdw_master_device(dev); + ssize_t size = 0; + int i; + + for (i = 0; i < md->bus->prop.num_clk_gears; i++) + size += sprintf(buf + size, "%8d ", + md->bus->prop.clk_gears[i]); + size += sprintf(buf + size, "\n"); + + return size; +} +static DEVICE_ATTR_RO(clock_gears); + +static struct attribute *master_node_attrs[] = { + &dev_attr_revision.attr, + &dev_attr_clk_stop_modes.attr, + &dev_attr_max_clk_freq.attr, + &dev_attr_default_row.attr, + &dev_attr_default_col.attr, + &dev_attr_default_frame_rate.attr, + &dev_attr_dynamic_frame.attr, + &dev_attr_err_threshold.attr, + &dev_attr_clock_frequencies.attr, + &dev_attr_clock_gears.attr, + NULL, +}; +ATTRIBUTE_GROUPS(master_node); + +static void sdw_master_device_release(struct device *dev) +{ + struct sdw_master_device *md = dev_to_sdw_master_device(dev); + + kfree(md); +} + +static const struct dev_pm_ops master_dev_pm = { + SET_RUNTIME_PM_OPS(pm_generic_runtime_suspend, + pm_generic_runtime_resume, NULL) +}; + +struct device_type sdw_master_type = { + .name = "soundwire_master", + .release = sdw_master_device_release, + .pm = &master_dev_pm, +}; + +/** + * sdw_master_device_add() - create a Linux Master Device representation. + * @bus: SDW bus instance + * @parent: parent device + * @fwnode: firmware node handle + */ +int sdw_master_device_add(struct sdw_bus *bus, struct device *parent, + struct fwnode_handle *fwnode) +{ + struct sdw_master_device *md; + int ret; + + if (!parent) + return -EINVAL; + + md = kzalloc(sizeof(*md), GFP_KERNEL); + if (!md) + return -ENOMEM; + + md->dev.bus = &sdw_bus_type; + md->dev.type = &sdw_master_type; + md->dev.parent = parent; + md->dev.groups = master_node_groups; + md->dev.of_node = parent->of_node; + md->dev.fwnode = fwnode; + md->dev.dma_mask = parent->dma_mask; + + dev_set_name(&md->dev, "sdw-master-%d", bus->id); + + ret = device_register(&md->dev); + if (ret) { + dev_err(parent, "Failed to add master: ret %d\n", ret); + /* + * On err, don't free but drop ref as this will be freed + * when release method is invoked. + */ + put_device(&md->dev); + goto device_register_err; + } + + /* add shortcuts to improve code readability/compactness */ + md->bus = bus; + bus->dev = &md->dev; + bus->md = md; + +device_register_err: + return ret; +} + +/** + * sdw_master_device_del() - delete a Linux Master Device representation. + * @bus: bus handle + * + * This function is the dual of sdw_master_device_add() + */ +int sdw_master_device_del(struct sdw_bus *bus) +{ + device_unregister(bus->dev); + + return 0; +} diff --git a/drivers/soundwire/mipi_disco.c b/drivers/soundwire/mipi_disco.c index 844e6b22974f..4ae62b452b8c 100644 --- a/drivers/soundwire/mipi_disco.c +++ b/drivers/soundwire/mipi_disco.c @@ -231,16 +231,17 @@ static int sdw_slave_read_dpn(struct sdw_slave *slave, nval = fwnode_property_count_u32(node, "mipi-sdw-channel-number-list"); if (nval > 0) { - dpn[i].num_ch = nval; - dpn[i].ch = devm_kcalloc(&slave->dev, dpn[i].num_ch, - sizeof(*dpn[i].ch), + dpn[i].num_channels = nval; + dpn[i].channels = devm_kcalloc(&slave->dev, + dpn[i].num_channels, + sizeof(*dpn[i].channels), GFP_KERNEL); - if (!dpn[i].ch) + if (!dpn[i].channels) return -ENOMEM; fwnode_property_read_u32_array(node, "mipi-sdw-channel-number-list", - dpn[i].ch, dpn[i].num_ch); + dpn[i].channels, dpn[i].num_channels); } nval = fwnode_property_count_u32(node, "mipi-sdw-channel-combination-list"); diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index d6c9ad231873..a1c2a44a3b4d 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -765,12 +765,16 @@ static int qcom_swrm_probe(struct platform_device *pdev) } ctrl->irq = of_irq_get(dev->of_node, 0); - if (ctrl->irq < 0) - return ctrl->irq; + if (ctrl->irq < 0) { + ret = ctrl->irq; + goto err_init; + } ctrl->hclk = devm_clk_get(dev, "iface"); - if (IS_ERR(ctrl->hclk)) - return PTR_ERR(ctrl->hclk); + if (IS_ERR(ctrl->hclk)) { + ret = PTR_ERR(ctrl->hclk); + goto err_init; + } clk_prepare_enable(ctrl->hclk); @@ -780,14 +784,13 @@ static int qcom_swrm_probe(struct platform_device *pdev) mutex_init(&ctrl->port_lock); INIT_WORK(&ctrl->slave_work, qcom_swrm_slave_wq); - ctrl->bus.dev = dev; ctrl->bus.ops = &qcom_swrm_ops; ctrl->bus.port_ops = &qcom_swrm_port_ops; ctrl->bus.compute_params = &qcom_swrm_compute_params; ret = qcom_swrm_get_port_config(ctrl); if (ret) - return ret; + goto err_clk; params = &ctrl->bus.params; params->max_dr_freq = DEFAULT_CLK_FREQ; @@ -810,32 +813,37 @@ static int qcom_swrm_probe(struct platform_device *pdev) ret = devm_request_threaded_irq(dev, ctrl->irq, NULL, qcom_swrm_irq_handler, - IRQF_TRIGGER_RISING, + IRQF_TRIGGER_RISING | + IRQF_ONESHOT, "soundwire", ctrl); if (ret) { dev_err(dev, "Failed to request soundwire irq\n"); - goto err; + goto err_clk; } - ret = sdw_add_bus_master(&ctrl->bus); + ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode); if (ret) { dev_err(dev, "Failed to register Soundwire controller (%d)\n", ret); - goto err; + goto err_clk; } qcom_swrm_init(ctrl); ret = qcom_swrm_register_dais(ctrl); if (ret) - goto err; + goto err_master_add; dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n", (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff, ctrl->version & 0xffff); return 0; -err: + +err_master_add: + sdw_bus_master_delete(&ctrl->bus); +err_clk: clk_disable_unprepare(ctrl->hclk); +err_init: return ret; } @@ -843,7 +851,7 @@ static int qcom_swrm_remove(struct platform_device *pdev) { struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev); - sdw_delete_bus_master(&ctrl->bus); + sdw_bus_master_delete(&ctrl->bus); clk_disable_unprepare(ctrl->hclk); return 0; diff --git a/drivers/soundwire/slave.c b/drivers/soundwire/slave.c index aace57fae7f8..0839445ee07b 100644 --- a/drivers/soundwire/slave.c +++ b/drivers/soundwire/slave.c @@ -14,6 +14,12 @@ static void sdw_slave_release(struct device *dev) kfree(slave); } +struct device_type sdw_slave_type = { + .name = "sdw_slave", + .release = sdw_slave_release, + .uevent = sdw_slave_uevent, +}; + static int sdw_slave_add(struct sdw_bus *bus, struct sdw_slave_id *id, struct fwnode_handle *fwnode) { @@ -41,9 +47,9 @@ static int sdw_slave_add(struct sdw_bus *bus, id->class_id, id->unique_id); } - slave->dev.release = sdw_slave_release; slave->dev.bus = &sdw_bus_type; slave->dev.of_node = of_node_get(to_of_node(fwnode)); + slave->dev.type = &sdw_slave_type; slave->bus = bus; slave->status = SDW_SLAVE_UNATTACHED; init_completion(&slave->enumeration_complete); @@ -68,6 +74,8 @@ static int sdw_slave_add(struct sdw_bus *bus, list_del(&slave->node); mutex_unlock(&bus->bus_lock); put_device(&slave->dev); + + return ret; } sdw_slave_debugfs_init(slave); diff --git a/drivers/soundwire/sysfs_local.h b/drivers/soundwire/sysfs_local.h new file mode 100644 index 000000000000..ff60adee3c41 --- /dev/null +++ b/drivers/soundwire/sysfs_local.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright(c) 2015-2020 Intel Corporation. */ + +#ifndef __SDW_SYSFS_LOCAL_H +#define __SDW_SYSFS_LOCAL_H + +/* + * SDW sysfs APIs - + */ + +int sdw_slave_sysfs_init(struct sdw_slave *slave); +int sdw_slave_sysfs_dpn_init(struct sdw_slave *slave); + +#endif /* __SDW_SYSFS_LOCAL_H */ diff --git a/drivers/soundwire/sysfs_slave.c b/drivers/soundwire/sysfs_slave.c new file mode 100644 index 000000000000..f510071b0add --- /dev/null +++ b/drivers/soundwire/sysfs_slave.c @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright(c) 2015-2020 Intel Corporation. + +#include +#include +#include +#include +#include +#include +#include "bus.h" +#include "sysfs_local.h" + +/* + * Slave sysfs + */ + +/* + * The sysfs for Slave reflects the MIPI description as given + * in the MIPI DisCo spec + * + * Base file is device + * |---- modalias + * |---- dev-properties + * |---- mipi_revision + * |---- wake_capable + * |---- test_mode_capable + * |---- clk_stop_mode1 + * |---- simple_clk_stop_capable + * |---- clk_stop_timeout + * |---- ch_prep_timeout + * |---- reset_behave + * |---- high_PHY_capable + * |---- paging_support + * |---- bank_delay_support + * |---- p15_behave + * |---- master_count + * |---- source_ports + * |---- sink_ports + * |---- dp0 + * |---- max_word + * |---- min_word + * |---- words + * |---- BRA_flow_controlled + * |---- simple_ch_prep_sm + * |---- imp_def_interrupts + * |---- dpN_ + * |---- max_word + * |---- min_word + * |---- words + * |---- type + * |---- max_grouping + * |---- simple_ch_prep_sm + * |---- ch_prep_timeout + * |---- imp_def_interrupts + * |---- min_ch + * |---- max_ch + * |---- channels + * |---- ch_combinations + * |---- max_async_buffer + * |---- block_pack_mode + * |---- port_encoding + * + */ + +#define sdw_slave_attr(field, format_string) \ +static ssize_t field##_show(struct device *dev, \ + struct device_attribute *attr, \ + char *buf) \ +{ \ + struct sdw_slave *slave = dev_to_sdw_dev(dev); \ + return sprintf(buf, format_string, slave->prop.field); \ +} \ +static DEVICE_ATTR_RO(field) + +sdw_slave_attr(mipi_revision, "0x%x\n"); +sdw_slave_attr(wake_capable, "%d\n"); +sdw_slave_attr(test_mode_capable, "%d\n"); +sdw_slave_attr(clk_stop_mode1, "%d\n"); +sdw_slave_attr(simple_clk_stop_capable, "%d\n"); +sdw_slave_attr(clk_stop_timeout, "%d\n"); +sdw_slave_attr(ch_prep_timeout, "%d\n"); +sdw_slave_attr(reset_behave, "%d\n"); +sdw_slave_attr(high_PHY_capable, "%d\n"); +sdw_slave_attr(paging_support, "%d\n"); +sdw_slave_attr(bank_delay_support, "%d\n"); +sdw_slave_attr(p15_behave, "%d\n"); +sdw_slave_attr(master_count, "%d\n"); +sdw_slave_attr(source_ports, "0x%x\n"); +sdw_slave_attr(sink_ports, "0x%x\n"); + +static ssize_t modalias_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sdw_slave *slave = dev_to_sdw_dev(dev); + + return sdw_slave_modalias(slave, buf, 256); +} +static DEVICE_ATTR_RO(modalias); + +static struct attribute *slave_attrs[] = { + &dev_attr_modalias.attr, + NULL, +}; +ATTRIBUTE_GROUPS(slave); + +static struct attribute *slave_dev_attrs[] = { + &dev_attr_mipi_revision.attr, + &dev_attr_wake_capable.attr, + &dev_attr_test_mode_capable.attr, + &dev_attr_clk_stop_mode1.attr, + &dev_attr_simple_clk_stop_capable.attr, + &dev_attr_clk_stop_timeout.attr, + &dev_attr_ch_prep_timeout.attr, + &dev_attr_reset_behave.attr, + &dev_attr_high_PHY_capable.attr, + &dev_attr_paging_support.attr, + &dev_attr_bank_delay_support.attr, + &dev_attr_p15_behave.attr, + &dev_attr_master_count.attr, + &dev_attr_source_ports.attr, + &dev_attr_sink_ports.attr, + NULL, +}; + +/* + * we don't use ATTRIBUTES_GROUP here since we want to add a subdirectory + * for device-level properties + */ +static struct attribute_group sdw_slave_dev_attr_group = { + .attrs = slave_dev_attrs, + .name = "dev-properties", +}; + +/* + * DP0 sysfs + */ + +#define sdw_dp0_attr(field, format_string) \ +static ssize_t field##_show(struct device *dev, \ + struct device_attribute *attr, \ + char *buf) \ +{ \ + struct sdw_slave *slave = dev_to_sdw_dev(dev); \ + return sprintf(buf, format_string, slave->prop.dp0_prop->field);\ +} \ +static DEVICE_ATTR_RO(field) + +sdw_dp0_attr(max_word, "%d\n"); +sdw_dp0_attr(min_word, "%d\n"); +sdw_dp0_attr(BRA_flow_controlled, "%d\n"); +sdw_dp0_attr(simple_ch_prep_sm, "%d\n"); +sdw_dp0_attr(imp_def_interrupts, "0x%x\n"); + +static ssize_t words_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sdw_slave *slave = dev_to_sdw_dev(dev); + ssize_t size = 0; + int i; + + for (i = 0; i < slave->prop.dp0_prop->num_words; i++) + size += sprintf(buf + size, "%d ", + slave->prop.dp0_prop->words[i]); + size += sprintf(buf + size, "\n"); + + return size; +} +static DEVICE_ATTR_RO(words); + +static struct attribute *dp0_attrs[] = { + &dev_attr_max_word.attr, + &dev_attr_min_word.attr, + &dev_attr_words.attr, + &dev_attr_BRA_flow_controlled.attr, + &dev_attr_simple_ch_prep_sm.attr, + &dev_attr_imp_def_interrupts.attr, + NULL, +}; + +/* + * we don't use ATTRIBUTES_GROUP here since we want to add a subdirectory + * for dp0-level properties + */ +static const struct attribute_group dp0_group = { + .attrs = dp0_attrs, + .name = "dp0", +}; + +int sdw_slave_sysfs_init(struct sdw_slave *slave) +{ + int ret; + + ret = devm_device_add_groups(&slave->dev, slave_groups); + if (ret < 0) + return ret; + + ret = devm_device_add_group(&slave->dev, &sdw_slave_dev_attr_group); + if (ret < 0) + return ret; + + if (slave->prop.dp0_prop) { + ret = devm_device_add_group(&slave->dev, &dp0_group); + if (ret < 0) + return ret; + } + + if (slave->prop.source_ports || slave->prop.sink_ports) { + ret = sdw_slave_sysfs_dpn_init(slave); + if (ret < 0) + return ret; + } + + return 0; +} diff --git a/drivers/soundwire/sysfs_slave_dpn.c b/drivers/soundwire/sysfs_slave_dpn.c new file mode 100644 index 000000000000..05a721ea9830 --- /dev/null +++ b/drivers/soundwire/sysfs_slave_dpn.c @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright(c) 2015-2020 Intel Corporation. + +#include +#include +#include +#include +#include +#include +#include "bus.h" +#include "sysfs_local.h" + +struct dpn_attribute { + struct device_attribute dev_attr; + int N; + int dir; + const char *format_string; +}; + +/* + * Since we can't use ARRAY_SIZE, hard-code number of dpN attributes. + * This needs to be updated when adding new attributes - an error will be + * flagged on a mismatch. + */ +#define SDW_DPN_ATTRIBUTES 15 + +#define sdw_dpn_attribute_alloc(field) \ +static int field##_attribute_alloc(struct device *dev, \ + struct attribute **res, \ + int N, int dir, \ + const char *format_string) \ +{ \ + struct dpn_attribute *dpn_attr; \ + \ + dpn_attr = devm_kzalloc(dev, sizeof(*dpn_attr), GFP_KERNEL); \ + if (!dpn_attr) \ + return -ENOMEM; \ + dpn_attr->N = N; \ + dpn_attr->dir = dir; \ + dpn_attr->format_string = format_string; \ + dpn_attr->dev_attr.attr.name = __stringify(field); \ + dpn_attr->dev_attr.attr.mode = 0444; \ + dpn_attr->dev_attr.show = field##_show; \ + \ + *res = &dpn_attr->dev_attr.attr; \ + \ + return 0; \ +} + +#define sdw_dpn_attr(field) \ + \ +static ssize_t field##_dpn_show(struct sdw_slave *slave, \ + int N, \ + int dir, \ + const char *format_string, \ + char *buf) \ +{ \ + struct sdw_dpn_prop *dpn; \ + unsigned long mask; \ + int bit; \ + int i; \ + \ + if (dir) { \ + dpn = slave->prop.src_dpn_prop; \ + mask = slave->prop.source_ports; \ + } else { \ + dpn = slave->prop.sink_dpn_prop; \ + mask = slave->prop.sink_ports; \ + } \ + \ + i = 0; \ + for_each_set_bit(bit, &mask, 32) { \ + if (bit == N) { \ + return sprintf(buf, format_string, \ + dpn[i].field); \ + } \ + i++; \ + } \ + return -EINVAL; \ +} \ + \ +static ssize_t field##_show(struct device *dev, \ + struct device_attribute *attr, \ + char *buf) \ +{ \ + struct sdw_slave *slave = dev_to_sdw_dev(dev); \ + struct dpn_attribute *dpn_attr = \ + container_of(attr, struct dpn_attribute, dev_attr); \ + \ + return field##_dpn_show(slave, \ + dpn_attr->N, dpn_attr->dir, \ + dpn_attr->format_string, \ + buf); \ +} \ +sdw_dpn_attribute_alloc(field) + +sdw_dpn_attr(imp_def_interrupts); +sdw_dpn_attr(max_word); +sdw_dpn_attr(min_word); +sdw_dpn_attr(type); +sdw_dpn_attr(max_grouping); +sdw_dpn_attr(simple_ch_prep_sm); +sdw_dpn_attr(ch_prep_timeout); +sdw_dpn_attr(max_ch); +sdw_dpn_attr(min_ch); +sdw_dpn_attr(max_async_buffer); +sdw_dpn_attr(block_pack_mode); +sdw_dpn_attr(port_encoding); + +#define sdw_dpn_array_attr(field) \ + \ +static ssize_t field##_dpn_show(struct sdw_slave *slave, \ + int N, \ + int dir, \ + const char *format_string, \ + char *buf) \ +{ \ + struct sdw_dpn_prop *dpn; \ + unsigned long mask; \ + ssize_t size = 0; \ + int bit; \ + int i; \ + int j; \ + \ + if (dir) { \ + dpn = slave->prop.src_dpn_prop; \ + mask = slave->prop.source_ports; \ + } else { \ + dpn = slave->prop.sink_dpn_prop; \ + mask = slave->prop.sink_ports; \ + } \ + \ + i = 0; \ + for_each_set_bit(bit, &mask, 32) { \ + if (bit == N) { \ + for (j = 0; j < dpn[i].num_##field; j++) \ + size += sprintf(buf + size, \ + format_string, \ + dpn[i].field[j]); \ + size += sprintf(buf + size, "\n"); \ + return size; \ + } \ + i++; \ + } \ + return -EINVAL; \ +} \ +static ssize_t field##_show(struct device *dev, \ + struct device_attribute *attr, \ + char *buf) \ +{ \ + struct sdw_slave *slave = dev_to_sdw_dev(dev); \ + struct dpn_attribute *dpn_attr = \ + container_of(attr, struct dpn_attribute, dev_attr); \ + \ + return field##_dpn_show(slave, \ + dpn_attr->N, dpn_attr->dir, \ + dpn_attr->format_string, \ + buf); \ +} \ +sdw_dpn_attribute_alloc(field) + +sdw_dpn_array_attr(words); +sdw_dpn_array_attr(ch_combinations); +sdw_dpn_array_attr(channels); + +static int add_all_attributes(struct device *dev, int N, int dir) +{ + struct attribute **dpn_attrs; + struct attribute_group *dpn_group; + int i = 0; + int ret; + + /* allocate attributes, last one is NULL */ + dpn_attrs = devm_kcalloc(dev, SDW_DPN_ATTRIBUTES + 1, + sizeof(struct attribute *), + GFP_KERNEL); + if (!dpn_attrs) + return -ENOMEM; + + ret = max_word_attribute_alloc(dev, &dpn_attrs[i++], + N, dir, "%d\n"); + if (ret < 0) + return ret; + + ret = min_word_attribute_alloc(dev, &dpn_attrs[i++], + N, dir, "%d\n"); + if (ret < 0) + return ret; + + ret = words_attribute_alloc(dev, &dpn_attrs[i++], + N, dir, "%d\n"); + if (ret < 0) + return ret; + + ret = type_attribute_alloc(dev, &dpn_attrs[i++], + N, dir, "%d\n"); + if (ret < 0) + return ret; + + ret = max_grouping_attribute_alloc(dev, &dpn_attrs[i++], + N, dir, "%d\n"); + if (ret < 0) + return ret; + + ret = simple_ch_prep_sm_attribute_alloc(dev, &dpn_attrs[i++], + N, dir, "%d\n"); + if (ret < 0) + return ret; + + ret = ch_prep_timeout_attribute_alloc(dev, &dpn_attrs[i++], + N, dir, "%d\n"); + if (ret < 0) + return ret; + + ret = imp_def_interrupts_attribute_alloc(dev, &dpn_attrs[i++], + N, dir, "0x%x\n"); + if (ret < 0) + return ret; + + ret = min_ch_attribute_alloc(dev, &dpn_attrs[i++], + N, dir, "%d\n"); + if (ret < 0) + return ret; + + ret = max_ch_attribute_alloc(dev, &dpn_attrs[i++], + N, dir, "%d\n"); + if (ret < 0) + return ret; + + ret = channels_attribute_alloc(dev, &dpn_attrs[i++], + N, dir, "%d\n"); + if (ret < 0) + return ret; + + ret = ch_combinations_attribute_alloc(dev, &dpn_attrs[i++], + N, dir, "%d\n"); + if (ret < 0) + return ret; + + ret = max_async_buffer_attribute_alloc(dev, &dpn_attrs[i++], + N, dir, "%d\n"); + if (ret < 0) + return ret; + + ret = block_pack_mode_attribute_alloc(dev, &dpn_attrs[i++], + N, dir, "%d\n"); + if (ret < 0) + return ret; + + ret = port_encoding_attribute_alloc(dev, &dpn_attrs[i++], + N, dir, "%d\n"); + if (ret < 0) + return ret; + + /* paranoia check for editing mistakes */ + if (i != SDW_DPN_ATTRIBUTES) { + dev_err(dev, "mismatch in attributes, allocated %d got %d\n", + SDW_DPN_ATTRIBUTES, i); + return -EINVAL; + } + + dpn_group = devm_kzalloc(dev, sizeof(*dpn_group), GFP_KERNEL); + if (!dpn_group) + return -ENOMEM; + + dpn_group->attrs = dpn_attrs; + dpn_group->name = devm_kasprintf(dev, GFP_KERNEL, "dp%d_%s", + N, dir ? "src" : "sink"); + if (!dpn_group->name) + return -ENOMEM; + + ret = devm_device_add_group(dev, dpn_group); + if (ret < 0) + return ret; + + return 0; +} + +int sdw_slave_sysfs_dpn_init(struct sdw_slave *slave) +{ + unsigned long mask; + int ret; + int i; + + mask = slave->prop.source_ports; + for_each_set_bit(i, &mask, 32) { + ret = add_all_attributes(&slave->dev, i, 1); + if (ret < 0) + return ret; + } + + mask = slave->prop.sink_ports; + for_each_set_bit(i, &mask, 32) { + ret = add_all_attributes(&slave->dev, i, 0); + if (ret < 0) + return ret; + } + + return 0; +} diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index 7412a3042a8d..811c97a7c858 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -135,7 +135,6 @@ #define SPI_AUTOSUSPEND_TIMEOUT 3000 enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA}; -static const struct zynqmp_eemi_ops *eemi_ops; /** * struct zynqmp_qspi - Defines qspi driver instance @@ -1015,10 +1014,6 @@ static int zynqmp_qspi_probe(struct platform_device *pdev) struct zynqmp_qspi *xqspi; struct device *dev = &pdev->dev; - eemi_ops = zynqmp_pm_get_eemi_ops(); - if (IS_ERR(eemi_ops)) - return PTR_ERR(eemi_ops); - master = spi_alloc_master(&pdev->dev, sizeof(*xqspi)); if (!master) return -ENOMEM; diff --git a/drivers/staging/android/ion/heaps/ion_page_pool.c b/drivers/staging/android/ion/heaps/ion_page_pool.c index 98baa27a57d7..d34c192b1c27 100644 --- a/drivers/staging/android/ion/heaps/ion_page_pool.c +++ b/drivers/staging/android/ion/heaps/ion_page_pool.c @@ -37,7 +37,7 @@ static void ion_page_pool_add(struct ion_page_pool *pool, struct page *page) } mod_node_page_state(page_pgdat(page), NR_KERNEL_MISC_RECLAIMABLE, - 1 << pool->order); + 1 << pool->order); mutex_unlock(&pool->mutex); } @@ -57,7 +57,7 @@ static struct page *ion_page_pool_remove(struct ion_page_pool *pool, bool high) list_del(&page->lru); mod_node_page_state(page_pgdat(page), NR_KERNEL_MISC_RECLAIMABLE, - -(1 << pool->order)); + -(1 << pool->order)); return page; } diff --git a/drivers/staging/axis-fifo/axis-fifo.c b/drivers/staging/axis-fifo/axis-fifo.c index 5801067e7c1b..2bb1c2e9cb57 100644 --- a/drivers/staging/axis-fifo/axis-fifo.c +++ b/drivers/staging/axis-fifo/axis-fifo.c @@ -383,8 +383,9 @@ static ssize_t axis_fifo_read(struct file *f, char __user *buf, mutex_lock(&fifo->read_lock); ret = wait_event_interruptible_timeout(fifo->read_queue, ioread32(fifo->base_addr + XLLF_RDFO_OFFSET), - (read_timeout >= 0) ? msecs_to_jiffies(read_timeout) : - MAX_SCHEDULE_TIMEOUT); + (read_timeout >= 0) ? + msecs_to_jiffies(read_timeout) : + MAX_SCHEDULE_TIMEOUT); if (ret <= 0) { if (ret == 0) { @@ -525,9 +526,10 @@ static ssize_t axis_fifo_write(struct file *f, const char __user *buf, mutex_lock(&fifo->write_lock); ret = wait_event_interruptible_timeout(fifo->write_queue, ioread32(fifo->base_addr + XLLF_TDFV_OFFSET) - >= words_to_write, - (write_timeout >= 0) ? msecs_to_jiffies(write_timeout) : - MAX_SCHEDULE_TIMEOUT); + >= words_to_write, + (write_timeout >= 0) ? + msecs_to_jiffies(write_timeout) : + MAX_SCHEDULE_TIMEOUT); if (ret <= 0) { if (ret == 0) { diff --git a/drivers/staging/comedi/comedi_internal.h b/drivers/staging/comedi/comedi_internal.h index 7c8f18f55122..9b3631a654c8 100644 --- a/drivers/staging/comedi/comedi_internal.h +++ b/drivers/staging/comedi/comedi_internal.h @@ -32,8 +32,8 @@ void comedi_buf_map_get(struct comedi_buf_map *bm); int comedi_buf_map_put(struct comedi_buf_map *bm); int comedi_buf_map_access(struct comedi_buf_map *bm, unsigned long offset, void *buf, int len, int write); -struct comedi_buf_map *comedi_buf_map_from_subdev_get( - struct comedi_subdevice *s); +struct comedi_buf_map * +comedi_buf_map_from_subdev_get(struct comedi_subdevice *s); unsigned int comedi_buf_write_n_available(struct comedi_subdevice *s); unsigned int comedi_buf_write_n_allocated(struct comedi_subdevice *s); void comedi_device_cancel_all(struct comedi_device *dev); diff --git a/drivers/staging/comedi/drivers/ni_pcimio.c b/drivers/staging/comedi/drivers/ni_pcimio.c index 7c82d5f9778f..c1d70eec24ab 100644 --- a/drivers/staging/comedi/drivers/ni_pcimio.c +++ b/drivers/staging/comedi/drivers/ni_pcimio.c @@ -1214,7 +1214,7 @@ static void m_series_init_eeprom_buffer(struct comedi_device *dev) struct ni_private *devpriv = dev->private; struct mite *mite = devpriv->mite; resource_size_t daq_phys_addr; - static const int Start_Cal_EEPROM = 0x400; + static const int start_cal_eeprom = 0x400; static const unsigned int window_size = 10; unsigned int old_iodwbsr_bits; unsigned int old_iodwbsr1_bits; @@ -1234,7 +1234,7 @@ static void m_series_init_eeprom_buffer(struct comedi_device *dev) writel(0xf, mite->mmio + 0x30); for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i) - devpriv->eeprom_buffer[i] = ni_readb(dev, Start_Cal_EEPROM + i); + devpriv->eeprom_buffer[i] = ni_readb(dev, start_cal_eeprom + i); writel(old_iodwbsr1_bits, mite->mmio + MITE_IODWBSR_1); writel(old_iodwbsr_bits, mite->mmio + MITE_IODWBSR); diff --git a/drivers/staging/fbtft/fb_st7789v.c b/drivers/staging/fbtft/fb_st7789v.c index 3c3f387936e8..3a280cc1892c 100644 --- a/drivers/staging/fbtft/fb_st7789v.c +++ b/drivers/staging/fbtft/fb_st7789v.c @@ -20,6 +20,12 @@ "70 2C 2E 15 10 09 48 33 53 0B 19 18 20 25\n" \ "70 2C 2E 15 10 09 48 33 53 0B 19 18 20 25" +#define HSD20_IPS_GAMMA \ + "D0 05 0A 09 08 05 2E 44 45 0F 17 16 2B 33\n" \ + "D0 05 0A 09 08 05 2E 43 45 0F 16 16 2B 33" + +#define HSD20_IPS 1 + /** * enum st7789v_command - ST7789V display controller commands * @@ -82,14 +88,20 @@ static int init_display(struct fbtft_par *par) /* set pixel format to RGB-565 */ write_reg(par, MIPI_DCS_SET_PIXEL_FORMAT, MIPI_DCS_PIXEL_FMT_16BIT); + if (HSD20_IPS) + write_reg(par, PORCTRL, 0x05, 0x05, 0x00, 0x33, 0x33); - write_reg(par, PORCTRL, 0x08, 0x08, 0x00, 0x22, 0x22); + else + write_reg(par, PORCTRL, 0x08, 0x08, 0x00, 0x22, 0x22); /* * VGH = 13.26V * VGL = -10.43V */ - write_reg(par, GCTRL, 0x35); + if (HSD20_IPS) + write_reg(par, GCTRL, 0x75); + else + write_reg(par, GCTRL, 0x35); /* * VDV and VRH register values come from command write @@ -101,13 +113,19 @@ static int init_display(struct fbtft_par *par) * VAP = 4.1V + (VCOM + VCOM offset + 0.5 * VDV) * VAN = -4.1V + (VCOM + VCOM offset + 0.5 * VDV) */ - write_reg(par, VRHS, 0x0B); + if (HSD20_IPS) + write_reg(par, VRHS, 0x13); + else + write_reg(par, VRHS, 0x0B); /* VDV = 0V */ write_reg(par, VDVS, 0x20); /* VCOM = 0.9V */ - write_reg(par, VCOMS, 0x20); + if (HSD20_IPS) + write_reg(par, VCOMS, 0x22); + else + write_reg(par, VCOMS, 0x20); /* VCOM offset = 0V */ write_reg(par, VCMOFSET, 0x20); @@ -120,6 +138,10 @@ static int init_display(struct fbtft_par *par) write_reg(par, PWCTRL1, 0xA4, 0xA1); write_reg(par, MIPI_DCS_SET_DISPLAY_ON); + + if (HSD20_IPS) + write_reg(par, MIPI_DCS_ENTER_INVERT_MODE); + return 0; } @@ -234,7 +256,7 @@ static struct fbtft_display display = { .height = 320, .gamma_num = 2, .gamma_len = 14, - .gamma = DEFAULT_GAMMA, + .gamma = HSD20_IPS_GAMMA, .fbtftops = { .init_display = init_display, .set_var = set_var, diff --git a/drivers/staging/fsl-dpaa2/ethsw/ethsw.c b/drivers/staging/fsl-dpaa2/ethsw/ethsw.c index 676d1ad1b50d..546ad376df99 100644 --- a/drivers/staging/fsl-dpaa2/ethsw/ethsw.c +++ b/drivers/staging/fsl-dpaa2/ethsw/ethsw.c @@ -1094,7 +1094,8 @@ static int swdev_port_obj_del(struct net_device *netdev, static int ethsw_switchdev_port_attr_set_event(struct net_device *netdev, - struct switchdev_notifier_port_attr_info *port_attr_info) + struct switchdev_notifier_port_attr_info + *port_attr_info) { int err; @@ -1277,7 +1278,8 @@ err_addr_alloc: static int ethsw_switchdev_port_obj_event(unsigned long event, struct net_device *netdev, - struct switchdev_notifier_port_obj_info *port_obj_info) + struct switchdev_notifier_port_obj_info + *port_obj_info) { int err = -EOPNOTSUPP; diff --git a/drivers/staging/gasket/gasket_page_table.c b/drivers/staging/gasket/gasket_page_table.c index f6d715787da8..f3dbe0fe2a67 100644 --- a/drivers/staging/gasket/gasket_page_table.c +++ b/drivers/staging/gasket/gasket_page_table.c @@ -898,7 +898,7 @@ static int gasket_alloc_extended_subtable(struct gasket_page_table *pg_tbl, * * Note that memory for second level page tables is allocated as needed, but * that memory is only freed on the final close of the device file, when the - * page tables are repartitioned, or the the device is removed. If there is an + * page tables are repartitioned, or the device is removed. If there is an * error or if the full range of slots is not available, any memory * allocated for second level page tables remains allocated until final close, * repartition, or device removal. diff --git a/drivers/staging/gasket/gasket_sysfs.c b/drivers/staging/gasket/gasket_sysfs.c index 5f0e089573a2..af26bc9f184a 100644 --- a/drivers/staging/gasket/gasket_sysfs.c +++ b/drivers/staging/gasket/gasket_sysfs.c @@ -339,6 +339,7 @@ void gasket_sysfs_put_attr(struct device *device, dev_err(device, "Unable to put unknown attribute: %s\n", attr->attr.attr.name); + put_mapping(mapping); } EXPORT_SYMBOL(gasket_sysfs_put_attr); @@ -372,6 +373,7 @@ ssize_t gasket_sysfs_register_store(struct device *device, gasket_dev = mapping->gasket_dev; if (!gasket_dev) { dev_err(device, "Device driver may have been removed\n"); + put_mapping(mapping); return 0; } diff --git a/drivers/staging/gdm724x/gdm_lte.c b/drivers/staging/gdm724x/gdm_lte.c index 354727f0a1fc..eb309190f5be 100644 --- a/drivers/staging/gdm724x/gdm_lte.c +++ b/drivers/staging/gdm724x/gdm_lte.c @@ -172,7 +172,7 @@ static int gdm_lte_emulate_arp(struct sk_buff *skb_in, u32 nic_type) static __sum16 icmp6_checksum(struct ipv6hdr *ipv6, u16 *ptr, int len) { - unsigned short *w = ptr; + unsigned short *w; __wsum sum = 0; int i; u16 pa; diff --git a/drivers/staging/greybus/hid.c b/drivers/staging/greybus/hid.c index 04bfd9110502..ed706f39e87a 100644 --- a/drivers/staging/greybus/hid.c +++ b/drivers/staging/greybus/hid.c @@ -290,9 +290,8 @@ static int gb_hid_parse(struct hid_device *hid) } rdesc = kzalloc(rsize, GFP_KERNEL); - if (!rdesc) { + if (!rdesc) return -ENOMEM; - } ret = gb_hid_get_report_desc(ghid, rdesc); if (ret) { diff --git a/drivers/staging/greybus/light.c b/drivers/staging/greybus/light.c index d6ba25f21d80..d2672b65c3f4 100644 --- a/drivers/staging/greybus/light.c +++ b/drivers/staging/greybus/light.c @@ -1026,7 +1026,8 @@ static int gb_lights_light_config(struct gb_lights *glights, u8 id) light->channels_count = conf.channel_count; light->name = kstrndup(conf.name, NAMES_MAX, GFP_KERNEL); - + if (!light->name) + return -ENOMEM; light->channels = kcalloc(light->channels_count, sizeof(struct gb_channel), GFP_KERNEL); if (!light->channels) diff --git a/drivers/staging/greybus/loopback.c b/drivers/staging/greybus/loopback.c index 583d9708a191..2471448ba42a 100644 --- a/drivers/staging/greybus/loopback.c +++ b/drivers/staging/greybus/loopback.c @@ -135,7 +135,7 @@ static ssize_t name##_##field##_show(struct device *dev, \ char *buf) \ { \ struct gb_loopback *gb = dev_get_drvdata(dev); \ - /* Report 0 for min and max if no transfer successed */ \ + /* Report 0 for min and max if no transfer succeeded */ \ if (!gb->requests_completed) \ return sprintf(buf, "0\n"); \ return sprintf(buf, "%" #type "\n", gb->name.field); \ diff --git a/drivers/staging/greybus/uart.c b/drivers/staging/greybus/uart.c index 4ffb334cd5cd..607378bfebb7 100644 --- a/drivers/staging/greybus/uart.c +++ b/drivers/staging/greybus/uart.c @@ -40,14 +40,6 @@ #define GB_UART_FIRMWARE_CREDITS 4096 #define GB_UART_CREDIT_WAIT_TIMEOUT_MSEC 10000 -struct gb_tty_line_coding { - __le32 rate; - __u8 format; - __u8 parity; - __u8 data_bits; - __u8 flow_control; -}; - struct gb_tty { struct gbphy_device *gbphy_dev; struct tty_port port; @@ -66,7 +58,7 @@ struct gb_tty { struct mutex mutex; u8 ctrlin; /* input control lines */ u8 ctrlout; /* output control lines */ - struct gb_tty_line_coding line_coding; + struct gb_uart_set_line_coding_request line_coding; struct work_struct tx_work; struct kfifo write_fifo; bool close_pending; @@ -288,12 +280,9 @@ static void gb_uart_tx_write_work(struct work_struct *work) static int send_line_coding(struct gb_tty *tty) { - struct gb_uart_set_line_coding_request request; - - memcpy(&request, &tty->line_coding, - sizeof(tty->line_coding)); return gb_operation_sync(tty->connection, GB_UART_TYPE_SET_LINE_CODING, - &request, sizeof(request), NULL, 0); + &tty->line_coding, sizeof(tty->line_coding), + NULL, 0); } static int send_control(struct gb_tty *gb_tty, u8 control) @@ -493,9 +482,9 @@ static int gb_tty_break_ctl(struct tty_struct *tty, int state) static void gb_tty_set_termios(struct tty_struct *tty, struct ktermios *termios_old) { + struct gb_uart_set_line_coding_request newline; struct gb_tty *gb_tty = tty->driver_data; struct ktermios *termios = &tty->termios; - struct gb_tty_line_coding newline; u8 newctrl = gb_tty->ctrlout; newline.rate = cpu_to_le32(tty_get_baud_rate(tty)); diff --git a/drivers/staging/iio/Documentation/overview.txt b/drivers/staging/iio/Documentation/overview.txt index 43f92b06bc3e..ebdc64f451d7 100644 --- a/drivers/staging/iio/Documentation/overview.txt +++ b/drivers/staging/iio/Documentation/overview.txt @@ -34,7 +34,7 @@ turned on or off (if possible) via sysfs interfaces. fifo / ring buffers on the sensor chip. These greatly reduce the load on the host CPU by buffering relatively large numbers of data samples based on an internal sampling clock. Examples include VTI SCA3000 -series and Analog Device ADXL345 accelerometers. Each buffer supports +series and Analog Devices ADXL345 accelerometers. Each buffer supports polling to establish when data is available. * Trigger and software buffer support. In many data analysis diff --git a/drivers/staging/iio/impedance-analyzer/ad5933.c b/drivers/staging/iio/impedance-analyzer/ad5933.c index af0bcf95ee8a..c468355b0848 100644 --- a/drivers/staging/iio/impedance-analyzer/ad5933.c +++ b/drivers/staging/iio/impedance-analyzer/ad5933.c @@ -602,11 +602,12 @@ static const struct iio_buffer_setup_ops ad5933_ring_setup_ops = { .postdisable = ad5933_ring_postdisable, }; -static int ad5933_register_ring_funcs_and_init(struct iio_dev *indio_dev) +static int ad5933_register_ring_funcs_and_init(struct device *dev, + struct iio_dev *indio_dev) { struct iio_buffer *buffer; - buffer = iio_kfifo_allocate(); + buffer = devm_iio_kfifo_allocate(dev); if (!buffer) return -ENOMEM; @@ -676,6 +677,20 @@ static void ad5933_work(struct work_struct *work) } } +static void ad5933_reg_disable(void *data) +{ + struct ad5933_state *st = data; + + regulator_disable(st->reg); +} + +static void ad5933_clk_disable(void *data) +{ + struct ad5933_state *st = data; + + clk_disable_unprepare(st->mclk); +} + static int ad5933_probe(struct i2c_client *client, const struct i2c_device_id *id) { @@ -703,23 +718,32 @@ static int ad5933_probe(struct i2c_client *client, dev_err(&client->dev, "Failed to enable specified VDD supply\n"); return ret; } - ret = regulator_get_voltage(st->reg); + ret = devm_add_action_or_reset(&client->dev, ad5933_reg_disable, st); + if (ret) + return ret; + + ret = regulator_get_voltage(st->reg); if (ret < 0) - goto error_disable_reg; + return ret; st->vref_mv = ret / 1000; st->mclk = devm_clk_get(&client->dev, "mclk"); - if (IS_ERR(st->mclk) && PTR_ERR(st->mclk) != -ENOENT) { - ret = PTR_ERR(st->mclk); - goto error_disable_reg; - } + if (IS_ERR(st->mclk) && PTR_ERR(st->mclk) != -ENOENT) + return PTR_ERR(st->mclk); if (!IS_ERR(st->mclk)) { ret = clk_prepare_enable(st->mclk); if (ret < 0) - goto error_disable_reg; + return ret; + + ret = devm_add_action_or_reset(&client->dev, + ad5933_clk_disable, + st); + if (ret) + return ret; + ext_clk_hz = clk_get_rate(st->mclk); } @@ -742,41 +766,15 @@ static int ad5933_probe(struct i2c_client *client, indio_dev->channels = ad5933_channels; indio_dev->num_channels = ARRAY_SIZE(ad5933_channels); - ret = ad5933_register_ring_funcs_and_init(indio_dev); + ret = ad5933_register_ring_funcs_and_init(&client->dev, indio_dev); if (ret) - goto error_disable_mclk; + return ret; ret = ad5933_setup(st); if (ret) - goto error_unreg_ring; + return ret; - ret = iio_device_register(indio_dev); - if (ret) - goto error_unreg_ring; - - return 0; - -error_unreg_ring: - iio_kfifo_free(indio_dev->buffer); -error_disable_mclk: - clk_disable_unprepare(st->mclk); -error_disable_reg: - regulator_disable(st->reg); - - return ret; -} - -static int ad5933_remove(struct i2c_client *client) -{ - struct iio_dev *indio_dev = i2c_get_clientdata(client); - struct ad5933_state *st = iio_priv(indio_dev); - - iio_device_unregister(indio_dev); - iio_kfifo_free(indio_dev->buffer); - regulator_disable(st->reg); - clk_disable_unprepare(st->mclk); - - return 0; + return devm_iio_device_register(&client->dev, indio_dev); } static const struct i2c_device_id ad5933_id[] = { @@ -801,7 +799,6 @@ static struct i2c_driver ad5933_driver = { .of_match_table = ad5933_of_match, }, .probe = ad5933_probe, - .remove = ad5933_remove, .id_table = ad5933_id, }; module_i2c_driver(ad5933_driver); diff --git a/drivers/staging/most/usb/Kconfig b/drivers/staging/most/usb/Kconfig index a86f1f63def4..75dc25c0e0e5 100644 --- a/drivers/staging/most/usb/Kconfig +++ b/drivers/staging/most/usb/Kconfig @@ -7,7 +7,7 @@ config MOST_USB tristate "USB" depends on USB && NET help - Say Y here if you want to connect via USB to network tranceiver. + Say Y here if you want to connect via USB to network transceiver. This device driver depends on the networking AIM. To compile this driver as a module, choose M here: the diff --git a/drivers/staging/most/usb/usb.c b/drivers/staging/most/usb/usb.c index e8c5a8c98375..2640c5b326a4 100644 --- a/drivers/staging/most/usb/usb.c +++ b/drivers/staging/most/usb/usb.c @@ -5,7 +5,6 @@ * Copyright (C) 2013-2015 Microchip Technology Germany II GmbH & Co. KG */ -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include #include #include @@ -140,9 +139,10 @@ static void wq_netinfo(struct work_struct *wq_obj); static inline int drci_rd_reg(struct usb_device *dev, u16 reg, u16 *buf) { int retval; - __le16 *dma_buf = kzalloc(sizeof(*dma_buf), GFP_KERNEL); + __le16 *dma_buf; u8 req_type = USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE; + dma_buf = kzalloc(sizeof(*dma_buf), GFP_KERNEL); if (!dma_buf) return -ENOMEM; @@ -153,7 +153,9 @@ static inline int drci_rd_reg(struct usb_device *dev, u16 reg, u16 *buf) *buf = le16_to_cpu(*dma_buf); kfree(dma_buf); - return retval; + if (retval < 0) + return retval; + return 0; } /** @@ -184,16 +186,18 @@ static inline int start_sync_ep(struct usb_device *usb_dev, u16 ep) /** * get_stream_frame_size - calculate frame size of current configuration + * @dev: device structure * @cfg: channel configuration */ -static unsigned int get_stream_frame_size(struct most_channel_config *cfg) +static unsigned int get_stream_frame_size(struct device *dev, + struct most_channel_config *cfg) { - unsigned int frame_size = 0; + unsigned int frame_size; unsigned int sub_size = cfg->subbuffer_size; if (!sub_size) { - pr_warn("Misconfig: Subbuffer size zero.\n"); - return frame_size; + dev_warn(dev, "Misconfig: Subbuffer size zero.\n"); + return 0; } switch (cfg->data_type) { case MOST_CH_ISOC: @@ -201,7 +205,7 @@ static unsigned int get_stream_frame_size(struct most_channel_config *cfg) break; case MOST_CH_SYNC: if (cfg->packets_per_xact == 0) { - pr_warn("Misconfig: Packets per XACT zero\n"); + dev_warn(dev, "Misconfig: Packets per XACT zero\n"); frame_size = 0; } else if (cfg->packets_per_xact == 0xFF) { frame_size = (USB_MTU / sub_size) * sub_size; @@ -210,7 +214,8 @@ static unsigned int get_stream_frame_size(struct most_channel_config *cfg) } break; default: - pr_warn("Query frame size of non-streaming channel\n"); + dev_warn(dev, "Query frame size of non-streaming channel\n"); + frame_size = 0; break; } return frame_size; @@ -233,11 +238,7 @@ static int hdm_poison_channel(struct most_interface *iface, int channel) unsigned long flags; spinlock_t *lock; /* temp. lock */ - if (unlikely(!iface)) { - dev_warn(&mdev->usb_device->dev, "Poison: Bad interface.\n"); - return -EIO; - } - if (unlikely(channel < 0 || channel >= iface->num_channels)) { + if (channel < 0 || channel >= iface->num_channels) { dev_warn(&mdev->usb_device->dev, "Channel ID out of range.\n"); return -ECHRNG; } @@ -274,17 +275,17 @@ static int hdm_poison_channel(struct most_interface *iface, int channel) static int hdm_add_padding(struct most_dev *mdev, int channel, struct mbo *mbo) { struct most_channel_config *conf = &mdev->conf[channel]; - unsigned int frame_size = get_stream_frame_size(conf); + unsigned int frame_size = get_stream_frame_size(&mdev->dev, conf); unsigned int j, num_frames; if (!frame_size) - return -EIO; + return -EINVAL; num_frames = mbo->buffer_length / frame_size; if (num_frames < 1) { dev_err(&mdev->usb_device->dev, "Missed minimal transfer unit.\n"); - return -EIO; + return -EINVAL; } for (j = num_frames - 1; j > 0; j--) @@ -308,11 +309,11 @@ static int hdm_remove_padding(struct most_dev *mdev, int channel, struct mbo *mbo) { struct most_channel_config *const conf = &mdev->conf[channel]; - unsigned int frame_size = get_stream_frame_size(conf); + unsigned int frame_size = get_stream_frame_size(&mdev->dev, conf); unsigned int j, num_frames; if (!frame_size) - return -EIO; + return -EINVAL; num_frames = mbo->processed_length / USB_MTU; for (j = 1; j < num_frames; j++) @@ -386,103 +387,6 @@ static void hdm_write_completion(struct urb *urb) * padding bytes -if necessary- and calls the completion function. * * Context: interrupt! - * - * ************************************************************************** - * Error codes returned by in urb->status - * or in iso_frame_desc[n].status (for ISO) - * ************************************************************************* - * - * USB device drivers may only test urb status values in completion handlers. - * This is because otherwise there would be a race between HCDs updating - * these values on one CPU, and device drivers testing them on another CPU. - * - * A transfer's actual_length may be positive even when an error has been - * reported. That's because transfers often involve several packets, so that - * one or more packets could finish before an error stops further endpoint I/O. - * - * For isochronous URBs, the urb status value is non-zero only if the URB is - * unlinked, the device is removed, the host controller is disabled or the total - * transferred length is less than the requested length and the URB_SHORT_NOT_OK - * flag is set. Completion handlers for isochronous URBs should only see - * urb->status set to zero, -ENOENT, -ECONNRESET, -ESHUTDOWN, or -EREMOTEIO. - * Individual frame descriptor status fields may report more status codes. - * - * - * 0 Transfer completed successfully - * - * -ENOENT URB was synchronously unlinked by usb_unlink_urb - * - * -EINPROGRESS URB still pending, no results yet - * (That is, if drivers see this it's a bug.) - * - * -EPROTO (*, **) a) bitstuff error - * b) no response packet received within the - * prescribed bus turn-around time - * c) unknown USB error - * - * -EILSEQ (*, **) a) CRC mismatch - * b) no response packet received within the - * prescribed bus turn-around time - * c) unknown USB error - * - * Note that often the controller hardware does not - * distinguish among cases a), b), and c), so a - * driver cannot tell whether there was a protocol - * error, a failure to respond (often caused by - * device disconnect), or some other fault. - * - * -ETIME (**) No response packet received within the prescribed - * bus turn-around time. This error may instead be - * reported as -EPROTO or -EILSEQ. - * - * -ETIMEDOUT Synchronous USB message functions use this code - * to indicate timeout expired before the transfer - * completed, and no other error was reported by HC. - * - * -EPIPE (**) Endpoint stalled. For non-control endpoints, - * reset this status with usb_clear_halt(). - * - * -ECOMM During an IN transfer, the host controller - * received data from an endpoint faster than it - * could be written to system memory - * - * -ENOSR During an OUT transfer, the host controller - * could not retrieve data from system memory fast - * enough to keep up with the USB data rate - * - * -EOVERFLOW (*) The amount of data returned by the endpoint was - * greater than either the max packet size of the - * endpoint or the remaining buffer size. "Babble". - * - * -EREMOTEIO The data read from the endpoint did not fill the - * specified buffer, and URB_SHORT_NOT_OK was set in - * urb->transfer_flags. - * - * -ENODEV Device was removed. Often preceded by a burst of - * other errors, since the hub driver doesn't detect - * device removal events immediately. - * - * -EXDEV ISO transfer only partially completed - * (only set in iso_frame_desc[n].status, not urb->status) - * - * -EINVAL ISO madness, if this happens: Log off and go home - * - * -ECONNRESET URB was asynchronously unlinked by usb_unlink_urb - * - * -ESHUTDOWN The device or host controller has been disabled due - * to some problem that could not be worked around, - * such as a physical disconnect. - * - * - * (*) Error codes like -EPROTO, -EILSEQ and -EOVERFLOW normally indicate - * hardware problems such as bad devices (including firmware) or cables. - * - * (**) This is also one of several codes that different kinds of host - * controller use to indicate a transfer has failed because of device - * disconnect. In the interval before the hub driver starts disconnect - * processing, devices may receive such fault reports for every request. - * - * See */ static void hdm_read_completion(struct urb *urb) { @@ -552,36 +456,33 @@ static void hdm_read_completion(struct urb *urb) static int hdm_enqueue(struct most_interface *iface, int channel, struct mbo *mbo) { - struct most_dev *mdev; + struct most_dev *mdev = to_mdev(iface); struct most_channel_config *conf; int retval = 0; struct urb *urb; unsigned long length; void *virt_address; - if (unlikely(!iface || !mbo)) - return -EIO; - if (unlikely(iface->num_channels <= channel || channel < 0)) + if (!mbo) + return -EINVAL; + if (iface->num_channels <= channel || channel < 0) return -ECHRNG; - mdev = to_mdev(iface); + urb = usb_alloc_urb(NO_ISOCHRONOUS_URB, GFP_KERNEL); + if (!urb) + return -ENOMEM; + conf = &mdev->conf[channel]; mutex_lock(&mdev->io_mutex); if (!mdev->usb_device) { retval = -ENODEV; - goto unlock_io_mutex; - } - - urb = usb_alloc_urb(NO_ISOCHRONOUS_URB, GFP_ATOMIC); - if (!urb) { - retval = -ENOMEM; - goto unlock_io_mutex; + goto err_free_urb; } if ((conf->direction & MOST_CH_TX) && mdev->padding_active[channel] && hdm_add_padding(mdev, channel, mbo)) { - retval = -EIO; + retval = -EINVAL; goto err_free_urb; } @@ -619,13 +520,13 @@ static int hdm_enqueue(struct most_interface *iface, int channel, "URB submit failed with error %d.\n", retval); goto err_unanchor_urb; } - goto unlock_io_mutex; + mutex_unlock(&mdev->io_mutex); + return 0; err_unanchor_urb: usb_unanchor_urb(urb); err_free_urb: usb_free_urb(urb); -unlock_io_mutex: mutex_unlock(&mdev->io_mutex); return retval; } @@ -669,19 +570,20 @@ static int hdm_configure_channel(struct most_interface *iface, int channel, struct most_dev *mdev = to_mdev(iface); struct device *dev = &mdev->usb_device->dev; + if (!conf) { + dev_err(dev, "Bad config pointer.\n"); + return -EINVAL; + } + if (channel < 0 || channel >= iface->num_channels) { + dev_err(dev, "Channel ID out of range.\n"); + return -EINVAL; + } + mdev->is_channel_healthy[channel] = true; mdev->clear_work[channel].channel = channel; mdev->clear_work[channel].mdev = mdev; INIT_WORK(&mdev->clear_work[channel].ws, wq_clear_halt); - if (unlikely(!iface || !conf)) { - dev_err(dev, "Bad interface or config pointer.\n"); - return -EINVAL; - } - if (unlikely(channel < 0 || channel >= iface->num_channels)) { - dev_err(dev, "Channel ID out of range.\n"); - return -EINVAL; - } if (!conf->num_buffers || !conf->buffer_size) { dev_err(dev, "Misconfig: buffer size or #buffers zero.\n"); return -EINVAL; @@ -701,7 +603,7 @@ static int hdm_configure_channel(struct most_interface *iface, int channel, mdev->padding_active[channel] = true; - frame_size = get_stream_frame_size(conf); + frame_size = get_stream_frame_size(&mdev->dev, conf); if (frame_size == 0 || frame_size > USB_MTU) { dev_warn(dev, "Misconfig: frame size wrong\n"); return -EINVAL; @@ -745,10 +647,8 @@ static void hdm_request_netinfo(struct most_interface *iface, int channel, unsigned char, unsigned char *)) { - struct most_dev *mdev; + struct most_dev *mdev = to_mdev(iface); - BUG_ON(!iface); - mdev = to_mdev(iface); mdev->on_netinfo = on_netinfo; if (!on_netinfo) return; @@ -787,22 +687,22 @@ static void wq_netinfo(struct work_struct *wq_obj) u16 hi, mi, lo, link; u8 hw_addr[6]; - if (drci_rd_reg(usb_device, DRCI_REG_HW_ADDR_HI, &hi) < 0) { + if (drci_rd_reg(usb_device, DRCI_REG_HW_ADDR_HI, &hi)) { dev_err(dev, "Vendor request 'hw_addr_hi' failed\n"); return; } - if (drci_rd_reg(usb_device, DRCI_REG_HW_ADDR_MI, &mi) < 0) { + if (drci_rd_reg(usb_device, DRCI_REG_HW_ADDR_MI, &mi)) { dev_err(dev, "Vendor request 'hw_addr_mid' failed\n"); return; } - if (drci_rd_reg(usb_device, DRCI_REG_HW_ADDR_LO, &lo) < 0) { + if (drci_rd_reg(usb_device, DRCI_REG_HW_ADDR_LO, &lo)) { dev_err(dev, "Vendor request 'hw_addr_low' failed\n"); return; } - if (drci_rd_reg(usb_device, DRCI_REG_NI_STATE, &link) < 0) { + if (drci_rd_reg(usb_device, DRCI_REG_NI_STATE, &link)) { dev_err(dev, "Vendor request 'link status' failed\n"); return; } @@ -830,6 +730,8 @@ static void wq_clear_halt(struct work_struct *wq_obj) struct most_dev *mdev = clear_work->mdev; unsigned int channel = clear_work->channel; int pipe = clear_work->pipe; + int snd_pipe; + int peer; mutex_lock(&mdev->io_mutex); most_stop_enqueue(&mdev->iface, channel); @@ -847,9 +749,12 @@ static void wq_clear_halt(struct work_struct *wq_obj) */ if (mdev->conf[channel].data_type == MOST_CH_ASYNC && mdev->conf[channel].direction == MOST_CH_RX) { - int peer = 1 - channel; - int snd_pipe = usb_sndbulkpipe(mdev->usb_device, - mdev->ep_address[peer]); + if (channel == 0) + peer = 1; + else + peer = 0; + snd_pipe = usb_sndbulkpipe(mdev->usb_device, + mdev->ep_address[peer]); usb_clear_halt(mdev->usb_device, snd_pipe); } mdev->is_channel_healthy[channel] = true; @@ -904,12 +809,12 @@ static int get_stat_reg_addr(const struct regs *regs, int size, int i; for (i = 0; i < size; i++) { - if (!strcmp(name, regs[i].name)) { + if (sysfs_streq(name, regs[i].name)) { *reg_addr = regs[i].reg; return 0; } } - return -EFAULT; + return -EINVAL; } #define get_static_reg_addr(regs, name, reg_addr) \ @@ -924,14 +829,14 @@ static ssize_t value_show(struct device *dev, struct device_attribute *attr, u16 reg_addr; int err; - if (!strcmp(name, "arb_address")) + if (sysfs_streq(name, "arb_address")) return snprintf(buf, PAGE_SIZE, "%04x\n", dci_obj->reg_addr); - if (!strcmp(name, "arb_value")) + if (sysfs_streq(name, "arb_value")) reg_addr = dci_obj->reg_addr; else if (get_static_reg_addr(ro_regs, name, ®_addr) && get_static_reg_addr(rw_regs, name, ®_addr)) - return -EFAULT; + return -EINVAL; err = drci_rd_reg(dci_obj->usb_device, reg_addr, &val); if (err < 0) @@ -948,24 +853,25 @@ static ssize_t value_store(struct device *dev, struct device_attribute *attr, const char *name = attr->attr.name; struct most_dci_obj *dci_obj = to_dci_obj(dev); struct usb_device *usb_dev = dci_obj->usb_device; - int err = kstrtou16(buf, 16, &val); + int err; + err = kstrtou16(buf, 16, &val); if (err) return err; - if (!strcmp(name, "arb_address")) { + if (sysfs_streq(name, "arb_address")) { dci_obj->reg_addr = val; return count; } - if (!strcmp(name, "arb_value")) + if (sysfs_streq(name, "arb_value")) err = drci_wr_reg(usb_dev, dci_obj->reg_addr, val); - else if (!strcmp(name, "sync_ep")) + else if (sysfs_streq(name, "sync_ep")) err = start_sync_ep(usb_dev, val); else if (!get_static_reg_addr(rw_regs, name, ®_addr)) err = drci_wr_reg(usb_dev, reg_addr, val); else - return -EFAULT; + return -EINVAL; if (err < 0) return err; @@ -1008,19 +914,13 @@ static struct attribute *dci_attrs[] = { NULL, }; -static struct attribute_group dci_attr_group = { - .attrs = dci_attrs, -}; - -static const struct attribute_group *dci_attr_groups[] = { - &dci_attr_group, - NULL, -}; +ATTRIBUTE_GROUPS(dci); static void release_dci(struct device *dev) { struct most_dci_obj *dci = to_dci_obj(dev); + put_device(dev->parent); kfree(dci); } @@ -1048,18 +948,23 @@ hdm_probe(struct usb_interface *interface, const struct usb_device_id *id) struct usb_host_interface *usb_iface_desc = interface->cur_altsetting; struct usb_device *usb_dev = interface_to_usbdev(interface); struct device *dev = &usb_dev->dev; - struct most_dev *mdev = kzalloc(sizeof(*mdev), GFP_KERNEL); + struct most_dev *mdev; unsigned int i; unsigned int num_endpoints; struct most_channel_capability *tmp_cap; struct usb_endpoint_descriptor *ep_desc; - int ret = 0; + int ret = -ENOMEM; + mdev = kzalloc(sizeof(*mdev), GFP_KERNEL); if (!mdev) - goto err_out_of_memory; + return -ENOMEM; usb_set_intfdata(interface, mdev); num_endpoints = usb_iface_desc->desc.bNumEndpoints; + if (num_endpoints > MAX_NUM_ENDPOINTS) { + kfree(mdev); + return -EINVAL; + } mutex_init(&mdev->io_mutex); INIT_WORK(&mdev->poll_work_obj, wq_netinfo); timer_setup(&mdev->link_stat_timer, link_stat_timer_handler, 0); @@ -1134,17 +1039,17 @@ hdm_probe(struct usb_interface *interface, const struct usb_device_id *id) init_usb_anchor(&mdev->busy_urbs[i]); spin_lock_init(&mdev->channel_lock[i]); } - dev_notice(dev, "claimed gadget: Vendor=%4.4x ProdID=%4.4x Bus=%02x Device=%02x\n", - le16_to_cpu(usb_dev->descriptor.idVendor), - le16_to_cpu(usb_dev->descriptor.idProduct), - usb_dev->bus->busnum, - usb_dev->devnum); + dev_dbg(dev, "claimed gadget: Vendor=%4.4x ProdID=%4.4x Bus=%02x Device=%02x\n", + le16_to_cpu(usb_dev->descriptor.idVendor), + le16_to_cpu(usb_dev->descriptor.idProduct), + usb_dev->bus->busnum, + usb_dev->devnum); - dev_notice(dev, "device path: /sys/bus/usb/devices/%d-%s:%d.%d\n", - usb_dev->bus->busnum, - usb_dev->devpath, - usb_dev->config->desc.bConfigurationValue, - usb_iface_desc->desc.bInterfaceNumber); + dev_dbg(dev, "device path: /sys/bus/usb/devices/%d-%s:%d.%d\n", + usb_dev->bus->busnum, + usb_dev->devpath, + usb_dev->config->desc.bConfigurationValue, + usb_iface_desc->desc.bInterfaceNumber); ret = most_register_interface(&mdev->iface); if (ret) @@ -1164,7 +1069,7 @@ hdm_probe(struct usb_interface *interface, const struct usb_device_id *id) mdev->dci->dev.init_name = "dci"; mdev->dci->dev.parent = get_device(mdev->iface.dev); - mdev->dci->dev.groups = dci_attr_groups; + mdev->dci->dev.groups = dci_groups; mdev->dci->dev.release = release_dci; if (device_register(&mdev->dci->dev)) { mutex_unlock(&mdev->io_mutex); @@ -1188,11 +1093,6 @@ err_free_conf: kfree(mdev->conf); err_free_mdev: put_device(&mdev->dev); -err_out_of_memory: - if (ret == 0 || ret == -ENOMEM) { - ret = -ENOMEM; - dev_err(dev, "out of memory\n"); - } return ret; } @@ -1225,14 +1125,43 @@ static void hdm_disconnect(struct usb_interface *interface) kfree(mdev->cap); kfree(mdev->conf); kfree(mdev->ep_address); + put_device(&mdev->dci->dev); put_device(&mdev->dev); } +static int hdm_suspend(struct usb_interface *interface, pm_message_t message) +{ + struct most_dev *mdev = usb_get_intfdata(interface); + int i; + + mutex_lock(&mdev->io_mutex); + for (i = 0; i < mdev->iface.num_channels; i++) { + most_stop_enqueue(&mdev->iface, i); + usb_kill_anchored_urbs(&mdev->busy_urbs[i]); + } + mutex_unlock(&mdev->io_mutex); + return 0; +} + +static int hdm_resume(struct usb_interface *interface) +{ + struct most_dev *mdev = usb_get_intfdata(interface); + int i; + + mutex_lock(&mdev->io_mutex); + for (i = 0; i < mdev->iface.num_channels; i++) + most_resume_enqueue(&mdev->iface, i); + mutex_unlock(&mdev->io_mutex); + return 0; +} + static struct usb_driver hdm_usb = { .name = "hdm_usb", .id_table = usbid, .probe = hdm_probe, .disconnect = hdm_disconnect, + .resume = hdm_resume, + .suspend = hdm_suspend, }; module_usb_driver(hdm_usb); diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi index 9e5cf68731bb..82aa93634eda 100644 --- a/drivers/staging/mt7621-dts/mt7621.dtsi +++ b/drivers/staging/mt7621-dts/mt7621.dtsi @@ -523,11 +523,10 @@ 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */ >; - #interrupt-cells = <1>; - interrupt-map-mask = <0xF0000 0 0 1>; - interrupt-map = <0x10000 0 0 1 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>, - <0x20000 0 0 1 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>, - <0x30000 0 0 1 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + interrupts = ; status = "disabled"; diff --git a/drivers/staging/mt7621-pci-phy/mediatek,mt7621-pci-phy.txt b/drivers/staging/mt7621-pci-phy/mediatek,mt7621-pci-phy.txt deleted file mode 100644 index a369d715378b..000000000000 --- a/drivers/staging/mt7621-pci-phy/mediatek,mt7621-pci-phy.txt +++ /dev/null @@ -1,28 +0,0 @@ -Mediatek Mt7621 PCIe PHY - -Required properties: -- compatible: must be "mediatek,mt7621-pci-phy" -- reg: base address and length of the PCIe PHY block -- #phy-cells: must be <1> for pcie0_phy and for pcie1_phy. - -Example: - pcie0_phy: pcie-phy@1e149000 { - compatible = "mediatek,mt7621-pci-phy"; - reg = <0x1e149000 0x0700>; - #phy-cells = <1>; - }; - - pcie1_phy: pcie-phy@1e14a000 { - compatible = "mediatek,mt7621-pci-phy"; - reg = <0x1e14a000 0x0700>; - #phy-cells = <1>; - }; - - /* users of the PCIe phy */ - - pcie: pcie@1e140000 { - ... - ... - phys = <&pcie0_phy 0>, <&pcie0_phy 1>, <&pcie1_phy 0>; - phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; - }; diff --git a/drivers/staging/mt7621-pci-phy/mediatek,mt7621-pci-phy.yaml b/drivers/staging/mt7621-pci-phy/mediatek,mt7621-pci-phy.yaml new file mode 100644 index 000000000000..cf32bbc45b5d --- /dev/null +++ b/drivers/staging/mt7621-pci-phy/mediatek,mt7621-pci-phy.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/mediatek,mt7621-pci-phy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Mediatek Mt7621 PCIe PHY Device Tree Bindings + +maintainers: + - Sergio Paracuellos + +properties: + compatible: + const: mediatek,mt7621-pci-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 1 + description: selects if the phy is dual-ported + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + pcie0_phy: pcie-phy@1e149000 { + compatible = "mediatek,mt7621-pci-phy"; + reg = <0x1e149000 0x0700>; + #phy-cells = <1>; + }; diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index f58e3a51fc71..f961b353c22e 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -55,7 +55,7 @@ #define RALINK_PCI_IOBASE 0x002C /* PCICFG virtual bridges */ -#define PCIE_P2P_MAX 3 +#define PCIE_P2P_CNT 3 #define PCIE_P2P_BR_DEVNUM_SHIFT(p) (16 + (p) * 4) #define PCIE_P2P_BR_DEVNUM0_SHIFT PCIE_P2P_BR_DEVNUM_SHIFT(0) #define PCIE_P2P_BR_DEVNUM1_SHIFT PCIE_P2P_BR_DEVNUM_SHIFT(1) @@ -97,6 +97,7 @@ * @pcie_rst: pointer to port reset control * @gpio_rst: gpio reset * @slot: port slot + * @irq: GIC irq * @enabled: indicates if port is enabled */ struct mt7621_pcie_port { @@ -107,6 +108,7 @@ struct mt7621_pcie_port { struct reset_control *pcie_rst; struct gpio_desc *gpio_rst; u32 slot; + int irq; bool enabled; }; @@ -120,6 +122,7 @@ struct mt7621_pcie_port { * @dev: Pointer to PCIe device * @io_map_base: virtual memory base address for io * @ports: pointer to PCIe port information + * @irq_map: irq mapping info according pcie link status * @resets_inverted: depends on chip revision * reset lines are inverted. */ @@ -135,6 +138,7 @@ struct mt7621_pcie { } offset; unsigned long io_map_base; struct list_head ports; + int irq_map[PCIE_P2P_CNT]; bool resets_inverted; }; @@ -279,6 +283,16 @@ static void setup_cm_memory_region(struct mt7621_pcie *pcie) } } +static int mt7621_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin) +{ + struct mt7621_pcie *pcie = pdev->bus->sysdata; + struct device *dev = pcie->dev; + int irq = pcie->irq_map[slot]; + + dev_info(dev, "bus=%d slot=%d irq=%d\n", pdev->bus->number, slot, irq); + return irq; +} + static int mt7621_pci_parse_request_of_pci_ranges(struct mt7621_pcie *pcie) { struct device *dev = pcie->dev; @@ -330,6 +344,7 @@ static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie, { struct mt7621_pcie_port *port; struct device *dev = pcie->dev; + struct platform_device *pdev = to_platform_device(dev); struct device_node *pnode = dev->of_node; struct resource regs; char name[10]; @@ -371,6 +386,12 @@ static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie, port->slot = slot; port->pcie = pcie; + port->irq = platform_get_irq(pdev, slot); + if (port->irq < 0) { + dev_err(dev, "Failed to get IRQ for PCIe%d\n", slot); + return -ENXIO; + } + INIT_LIST_HEAD(&port->list); list_add_tail(&port->list, &pcie->ports); @@ -502,17 +523,25 @@ static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie) mt7621_pcie_reset_ep_deassert(pcie); + tmp = NULL; list_for_each_entry(port, &pcie->ports, list) { u32 slot = port->slot; if (!mt7621_pcie_port_is_linkup(port)) { dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n", slot); - if (slot != 1) - phy_power_off(port->phy); mt7621_control_assert(port); mt7621_pcie_port_clk_disable(port); port->enabled = false; + + if (slot == 0) { + tmp = port; + continue; + } + + if (slot == 1 && tmp && !tmp->enabled) + phy_power_off(tmp->phy); + } } } @@ -576,14 +605,16 @@ static void mt7621_pcie_enable_ports(struct mt7621_pcie *pcie) static int mt7621_pcie_init_virtual_bridges(struct mt7621_pcie *pcie) { u32 pcie_link_status = 0; - u32 n; - int i; - u32 p2p_br_devnum[PCIE_P2P_MAX]; + u32 n = 0; + int i = 0; + u32 p2p_br_devnum[PCIE_P2P_CNT]; + int irqs[PCIE_P2P_CNT]; struct mt7621_pcie_port *port; list_for_each_entry(port, &pcie->ports, list) { u32 slot = port->slot; + irqs[i++] = port->irq; if (port->enabled) pcie_link_status |= BIT(slot); } @@ -591,12 +622,16 @@ static int mt7621_pcie_init_virtual_bridges(struct mt7621_pcie *pcie) if (pcie_link_status == 0) return -1; - n = 0; - for (i = 0; i < PCIE_P2P_MAX; i++) + /* + * Assign device numbers from zero to the enabled ports, + * then assigning remaining device numbers to any disabled + * ports. + */ + for (i = 0; i < PCIE_P2P_CNT; i++) if (pcie_link_status & BIT(i)) p2p_br_devnum[i] = n++; - for (i = 0; i < PCIE_P2P_MAX; i++) + for (i = 0; i < PCIE_P2P_CNT; i++) if ((pcie_link_status & BIT(i)) == 0) p2p_br_devnum[i] = n++; @@ -606,6 +641,15 @@ static int mt7621_pcie_init_virtual_bridges(struct mt7621_pcie *pcie) (p2p_br_devnum[1] << PCIE_P2P_BR_DEVNUM1_SHIFT) | (p2p_br_devnum[2] << PCIE_P2P_BR_DEVNUM2_SHIFT)); + /* Assign IRQs */ + n = 0; + for (i = 0; i < PCIE_P2P_CNT; i++) + if (pcie_link_status & BIT(i)) + pcie->irq_map[n++] = irqs[i]; + + for (i = n; i < PCIE_P2P_CNT; i++) + pcie->irq_map[i] = -1; + return 0; } @@ -630,7 +674,7 @@ static int mt7621_pcie_register_host(struct pci_host_bridge *host, host->busnr = pcie->busn.start; host->dev.parent = pcie->dev; host->ops = &mt7621_pci_ops; - host->map_irq = of_irq_parse_and_map_pci; + host->map_irq = mt7621_map_irq; host->swizzle_irq = pci_common_swizzle; host->sysdata = pcie; diff --git a/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c b/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c index d0f06790d38f..caaf9e34f1ee 100644 --- a/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c +++ b/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c @@ -220,7 +220,7 @@ static int rt2880_pinmux_index(struct rt2880_priv *p) /* allocate our function and group mapping index buffers */ f = p->func = devm_kcalloc(p->dev, p->func_count, - sizeof(struct rt2880_pmx_func), + sizeof(*p->func), GFP_KERNEL); gpio_func.groups = devm_kcalloc(p->dev, p->group_count, sizeof(int), GFP_KERNEL); diff --git a/drivers/staging/pi433/pi433_if.c b/drivers/staging/pi433/pi433_if.c index 313d22f6210f..c8d0c63fdd1d 100644 --- a/drivers/staging/pi433/pi433_if.c +++ b/drivers/staging/pi433/pi433_if.c @@ -1230,6 +1230,7 @@ static int pi433_probe(struct spi_device *spi) device->cdev = cdev_alloc(); if (!device->cdev) { dev_dbg(device->dev, "allocation of cdev failed"); + retval = -ENOMEM; goto cdev_failed; } device->cdev->owner = THIS_MODULE; diff --git a/drivers/staging/qlge/qlge_dbg.c b/drivers/staging/qlge/qlge_dbg.c index 1795533cbd3a..058889687907 100644 --- a/drivers/staging/qlge/qlge_dbg.c +++ b/drivers/staging/qlge/qlge_dbg.c @@ -1559,18 +1559,17 @@ void ql_dump_stat(struct ql_adapter *qdev) #ifdef QL_DEV_DUMP #define DUMP_QDEV_FIELD(qdev, type, field) \ - pr_err("qdev->%-24s = " type "\n", #field, (qdev)->(field)) + pr_err("qdev->%-24s = " type "\n", #field, (qdev)->field) #define DUMP_QDEV_DMA_FIELD(qdev, field) \ pr_err("qdev->%-24s = %llx\n", #field, (unsigned long long)qdev->field) #define DUMP_QDEV_ARRAY(qdev, type, array, index, field) \ pr_err("%s[%d].%s = " type "\n", \ - #array, index, #field, (qdev)->array[index].field); + #array, index, #field, (qdev)->array[index].field) void ql_dump_qdev(struct ql_adapter *qdev) { int i; DUMP_QDEV_FIELD(qdev, "%lx", flags); - DUMP_QDEV_FIELD(qdev, "%p", vlgrp); DUMP_QDEV_FIELD(qdev, "%p", pdev); DUMP_QDEV_FIELD(qdev, "%p", ndev); DUMP_QDEV_FIELD(qdev, "%d", chip_rev_id); @@ -1758,8 +1757,6 @@ void ql_dump_rx_ring(struct rx_ring *rx_ring) rx_ring->lbq.prod_idx_db_reg); pr_err("rx_ring->lbq.next_to_use = %d\n", rx_ring->lbq.next_to_use); pr_err("rx_ring->lbq.next_to_clean = %d\n", rx_ring->lbq.next_to_clean); - pr_err("rx_ring->lbq_clean_idx = %d\n", rx_ring->lbq_clean_idx); - pr_err("rx_ring->lbq_free_cnt = %d\n", rx_ring->lbq_free_cnt); pr_err("rx_ring->sbq.base = %p\n", rx_ring->sbq.base); pr_err("rx_ring->sbq.base_dma = %llx\n", diff --git a/drivers/staging/qlge/qlge_main.c b/drivers/staging/qlge/qlge_main.c index c92820f07968..402edaeffe12 100644 --- a/drivers/staging/qlge/qlge_main.c +++ b/drivers/staging/qlge/qlge_main.c @@ -214,19 +214,20 @@ int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit, u32 mask; u32 value; - direction = - (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE : - PCI_DMA_FROMDEVICE; + if (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) + direction = DMA_TO_DEVICE; + else + direction = DMA_FROM_DEVICE; - map = pci_map_single(qdev->pdev, ptr, size, direction); - if (pci_dma_mapping_error(qdev->pdev, map)) { + map = dma_map_single(&qdev->pdev->dev, ptr, size, direction); + if (dma_mapping_error(&qdev->pdev->dev, map)) { netif_err(qdev, ifup, qdev->ndev, "Couldn't map DMA area.\n"); return -ENOMEM; } status = ql_sem_spinlock(qdev, SEM_ICB_MASK); if (status) - return status; + goto lock_failed; status = ql_wait_cfg(qdev, bit); if (status) { @@ -235,8 +236,8 @@ int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit, goto exit; } - ql_write32(qdev, ICB_L, (u32) map); - ql_write32(qdev, ICB_H, (u32) (map >> 32)); + ql_write32(qdev, ICB_L, (u32)map); + ql_write32(qdev, ICB_H, (u32)(map >> 32)); mask = CFG_Q_MASK | (bit << 16); value = bit | (q_id << CFG_Q_SHIFT); @@ -248,7 +249,8 @@ int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit, status = ql_wait_cfg(qdev, bit); exit: ql_sem_unlock(qdev, SEM_ICB_MASK); /* does flush too */ - pci_unmap_single(qdev->pdev, map, size, direction); +lock_failed: + dma_unmap_single(&qdev->pdev->dev, map, size, direction); return status; } @@ -261,52 +263,50 @@ int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index, switch (type) { case MAC_ADDR_TYPE_MULTI_MAC: - case MAC_ADDR_TYPE_CAM_MAC: - { - status = - ql_wait_reg_rdy(qdev, - MAC_ADDR_IDX, MAC_ADDR_MW, 0); - if (status) - goto exit; - ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */ - (index << MAC_ADDR_IDX_SHIFT) | /* index */ - MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */ - status = - ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MR, 0); - if (status) - goto exit; - *value++ = ql_read32(qdev, MAC_ADDR_DATA); - status = - ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); - if (status) - goto exit; - ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */ - (index << MAC_ADDR_IDX_SHIFT) | /* index */ - MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */ - status = - ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MR, 0); - if (status) - goto exit; - *value++ = ql_read32(qdev, MAC_ADDR_DATA); - if (type == MAC_ADDR_TYPE_CAM_MAC) { - status = - ql_wait_reg_rdy(qdev, - MAC_ADDR_IDX, MAC_ADDR_MW, - 0); - if (status) - goto exit; - ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */ - (index << MAC_ADDR_IDX_SHIFT) | /* index */ - MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */ - status = - ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, - MAC_ADDR_MR, 0); - if (status) - goto exit; - *value++ = ql_read32(qdev, MAC_ADDR_DATA); - } + case MAC_ADDR_TYPE_CAM_MAC: { + status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); + if (status) break; + ql_write32(qdev, MAC_ADDR_IDX, + (offset++) | /* offset */ + (index << MAC_ADDR_IDX_SHIFT) | /* index */ + MAC_ADDR_ADR | MAC_ADDR_RS | + type); /* type */ + status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MR, 0); + if (status) + break; + *value++ = ql_read32(qdev, MAC_ADDR_DATA); + status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); + if (status) + break; + ql_write32(qdev, MAC_ADDR_IDX, + (offset++) | /* offset */ + (index << MAC_ADDR_IDX_SHIFT) | /* index */ + MAC_ADDR_ADR | MAC_ADDR_RS | + type); /* type */ + status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MR, 0); + if (status) + break; + *value++ = ql_read32(qdev, MAC_ADDR_DATA); + if (type == MAC_ADDR_TYPE_CAM_MAC) { + status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, + MAC_ADDR_MW, 0); + if (status) + break; + ql_write32(qdev, MAC_ADDR_IDX, + (offset++) | /* offset */ + (index + << MAC_ADDR_IDX_SHIFT) | /* index */ + MAC_ADDR_ADR | + MAC_ADDR_RS | type); /* type */ + status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, + MAC_ADDR_MR, 0); + if (status) + break; + *value++ = ql_read32(qdev, MAC_ADDR_DATA); } + break; + } case MAC_ADDR_TYPE_VLAN: case MAC_ADDR_TYPE_MULTI_FLTR: default: @@ -314,7 +314,6 @@ int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index, "Address type %d not yet supported.\n", type); status = -EPERM; } -exit: return status; } @@ -328,107 +327,93 @@ static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type, int status = 0; switch (type) { - case MAC_ADDR_TYPE_MULTI_MAC: - { - u32 upper = (addr[0] << 8) | addr[1]; - u32 lower = (addr[2] << 24) | (addr[3] << 16) | - (addr[4] << 8) | (addr[5]); - - status = - ql_wait_reg_rdy(qdev, - MAC_ADDR_IDX, MAC_ADDR_MW, 0); - if (status) - goto exit; - ql_write32(qdev, MAC_ADDR_IDX, (offset++) | - (index << MAC_ADDR_IDX_SHIFT) | - type | MAC_ADDR_E); - ql_write32(qdev, MAC_ADDR_DATA, lower); - status = - ql_wait_reg_rdy(qdev, - MAC_ADDR_IDX, MAC_ADDR_MW, 0); - if (status) - goto exit; - ql_write32(qdev, MAC_ADDR_IDX, (offset++) | - (index << MAC_ADDR_IDX_SHIFT) | - type | MAC_ADDR_E); - - ql_write32(qdev, MAC_ADDR_DATA, upper); - status = - ql_wait_reg_rdy(qdev, - MAC_ADDR_IDX, MAC_ADDR_MW, 0); - if (status) - goto exit; - break; - } - case MAC_ADDR_TYPE_CAM_MAC: - { - u32 cam_output; - u32 upper = (addr[0] << 8) | addr[1]; - u32 lower = - (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | + case MAC_ADDR_TYPE_MULTI_MAC: { + u32 upper = (addr[0] << 8) | addr[1]; + u32 lower = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | (addr[5]); - status = - ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); - if (status) - goto exit; - ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */ - (index << MAC_ADDR_IDX_SHIFT) | /* index */ - type); /* type */ - ql_write32(qdev, MAC_ADDR_DATA, lower); - status = - ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); - if (status) - goto exit; - ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */ - (index << MAC_ADDR_IDX_SHIFT) | /* index */ - type); /* type */ - ql_write32(qdev, MAC_ADDR_DATA, upper); - status = - ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); - if (status) - goto exit; - ql_write32(qdev, MAC_ADDR_IDX, (offset) | /* offset */ - (index << MAC_ADDR_IDX_SHIFT) | /* index */ - type); /* type */ - /* This field should also include the queue id - * and possibly the function id. Right now we hardcode - * the route field to NIC core. - */ - cam_output = (CAM_OUT_ROUTE_NIC | - (qdev-> - func << CAM_OUT_FUNC_SHIFT) | - (0 << CAM_OUT_CQ_ID_SHIFT)); - if (qdev->ndev->features & NETIF_F_HW_VLAN_CTAG_RX) - cam_output |= CAM_OUT_RV; - /* route to NIC core */ - ql_write32(qdev, MAC_ADDR_DATA, cam_output); + + status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); + if (status) break; - } - case MAC_ADDR_TYPE_VLAN: - { - u32 enable_bit = *((u32 *) &addr[0]); - /* For VLAN, the addr actually holds a bit that - * either enables or disables the vlan id we are - * addressing. It's either MAC_ADDR_E on or off. - * That's bit-27 we're talking about. - */ - status = - ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); - if (status) - goto exit; - ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */ - (index << MAC_ADDR_IDX_SHIFT) | /* index */ - type | /* type */ - enable_bit); /* enable/disable */ + ql_write32(qdev, MAC_ADDR_IDX, + (offset++) | (index << MAC_ADDR_IDX_SHIFT) | type | + MAC_ADDR_E); + ql_write32(qdev, MAC_ADDR_DATA, lower); + status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); + if (status) break; - } + ql_write32(qdev, MAC_ADDR_IDX, + (offset++) | (index << MAC_ADDR_IDX_SHIFT) | type | + MAC_ADDR_E); + + ql_write32(qdev, MAC_ADDR_DATA, upper); + status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); + break; + } + case MAC_ADDR_TYPE_CAM_MAC: { + u32 cam_output; + u32 upper = (addr[0] << 8) | addr[1]; + u32 lower = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | + (addr[5]); + status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); + if (status) + break; + ql_write32(qdev, MAC_ADDR_IDX, + (offset++) | /* offset */ + (index << MAC_ADDR_IDX_SHIFT) | /* index */ + type); /* type */ + ql_write32(qdev, MAC_ADDR_DATA, lower); + status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); + if (status) + break; + ql_write32(qdev, MAC_ADDR_IDX, + (offset++) | /* offset */ + (index << MAC_ADDR_IDX_SHIFT) | /* index */ + type); /* type */ + ql_write32(qdev, MAC_ADDR_DATA, upper); + status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); + if (status) + break; + ql_write32(qdev, MAC_ADDR_IDX, + (offset) | /* offset */ + (index << MAC_ADDR_IDX_SHIFT) | /* index */ + type); /* type */ + /* This field should also include the queue id + * and possibly the function id. Right now we hardcode + * the route field to NIC core. + */ + cam_output = (CAM_OUT_ROUTE_NIC | + (qdev->func << CAM_OUT_FUNC_SHIFT) | + (0 << CAM_OUT_CQ_ID_SHIFT)); + if (qdev->ndev->features & NETIF_F_HW_VLAN_CTAG_RX) + cam_output |= CAM_OUT_RV; + /* route to NIC core */ + ql_write32(qdev, MAC_ADDR_DATA, cam_output); + break; + } + case MAC_ADDR_TYPE_VLAN: { + u32 enable_bit = *((u32 *)&addr[0]); + /* For VLAN, the addr actually holds a bit that + * either enables or disables the vlan id we are + * addressing. It's either MAC_ADDR_E on or off. + * That's bit-27 we're talking about. + */ + status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); + if (status) + break; + ql_write32(qdev, MAC_ADDR_IDX, + offset | /* offset */ + (index << MAC_ADDR_IDX_SHIFT) | /* index */ + type | /* type */ + enable_bit); /* enable/disable */ + break; + } case MAC_ADDR_TYPE_MULTI_FLTR: default: netif_crit(qdev, ifup, qdev->ndev, "Address type %d not yet supported.\n", type); status = -EPERM; } -exit: return status; } @@ -455,7 +440,7 @@ static int ql_set_mac_addr(struct ql_adapter *qdev, int set) status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK); if (status) return status; - status = ql_set_mac_addr_reg(qdev, (u8 *) addr, + status = ql_set_mac_addr_reg(qdev, (u8 *)addr, MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ); ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK); @@ -857,7 +842,7 @@ int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data) if (status) goto exit; - *data = (u64) lo | ((u64) hi << 32); + *data = (u64)lo | ((u64)hi << 32); exit: return status; @@ -983,14 +968,14 @@ static struct qlge_bq_desc *ql_get_curr_lchunk(struct ql_adapter *qdev, { struct qlge_bq_desc *lbq_desc = qlge_get_curr_buf(&rx_ring->lbq); - pci_dma_sync_single_for_cpu(qdev->pdev, lbq_desc->dma_addr, - qdev->lbq_buf_size, PCI_DMA_FROMDEVICE); + dma_sync_single_for_cpu(&qdev->pdev->dev, lbq_desc->dma_addr, + qdev->lbq_buf_size, DMA_FROM_DEVICE); if ((lbq_desc->p.pg_chunk.offset + qdev->lbq_buf_size) == ql_lbq_block_size(qdev)) { /* last chunk of the master page */ - pci_unmap_page(qdev->pdev, lbq_desc->dma_addr, - ql_lbq_block_size(qdev), PCI_DMA_FROMDEVICE); + dma_unmap_page(&qdev->pdev->dev, lbq_desc->dma_addr, + ql_lbq_block_size(qdev), DMA_FROM_DEVICE); } return lbq_desc; @@ -1036,10 +1021,10 @@ static int qlge_refill_sb(struct rx_ring *rx_ring, return -ENOMEM; skb_reserve(skb, QLGE_SB_PAD); - sbq_desc->dma_addr = pci_map_single(qdev->pdev, skb->data, + sbq_desc->dma_addr = dma_map_single(&qdev->pdev->dev, skb->data, SMALL_BUF_MAP_SIZE, - PCI_DMA_FROMDEVICE); - if (pci_dma_mapping_error(qdev->pdev, sbq_desc->dma_addr)) { + DMA_FROM_DEVICE); + if (dma_mapping_error(&qdev->pdev->dev, sbq_desc->dma_addr)) { netif_err(qdev, ifup, qdev->ndev, "PCI mapping failed.\n"); dev_kfree_skb_any(skb); return -EIO; @@ -1064,10 +1049,10 @@ static int qlge_refill_lb(struct rx_ring *rx_ring, page = alloc_pages(gfp | __GFP_COMP, qdev->lbq_buf_order); if (unlikely(!page)) return -ENOMEM; - dma_addr = pci_map_page(qdev->pdev, page, 0, + dma_addr = dma_map_page(&qdev->pdev->dev, page, 0, ql_lbq_block_size(qdev), - PCI_DMA_FROMDEVICE); - if (pci_dma_mapping_error(qdev->pdev, dma_addr)) { + DMA_FROM_DEVICE); + if (dma_mapping_error(&qdev->pdev->dev, dma_addr)) { __free_pages(page, qdev->lbq_buf_order); netif_err(qdev, drv, qdev->ndev, "PCI mapping failed.\n"); @@ -1224,20 +1209,20 @@ static void ql_unmap_send(struct ql_adapter *qdev, qdev->ndev, "unmapping OAL area.\n"); } - pci_unmap_single(qdev->pdev, + dma_unmap_single(&qdev->pdev->dev, dma_unmap_addr(&tx_ring_desc->map[i], mapaddr), dma_unmap_len(&tx_ring_desc->map[i], maplen), - PCI_DMA_TODEVICE); + DMA_TO_DEVICE); } else { netif_printk(qdev, tx_done, KERN_DEBUG, qdev->ndev, "unmapping frag %d.\n", i); - pci_unmap_page(qdev->pdev, + dma_unmap_page(&qdev->pdev->dev, dma_unmap_addr(&tx_ring_desc->map[i], mapaddr), dma_unmap_len(&tx_ring_desc->map[i], - maplen), PCI_DMA_TODEVICE); + maplen), DMA_TO_DEVICE); } } @@ -1263,9 +1248,9 @@ static int ql_map_send(struct ql_adapter *qdev, /* * Map the skb buffer first. */ - map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE); + map = dma_map_single(&qdev->pdev->dev, skb->data, len, DMA_TO_DEVICE); - err = pci_dma_mapping_error(qdev->pdev, map); + err = dma_mapping_error(&qdev->pdev->dev, map); if (err) { netif_err(qdev, tx_queued, qdev->ndev, "PCI mapping failed with error: %d\n", err); @@ -1310,10 +1295,10 @@ static int ql_map_send(struct ql_adapter *qdev, * etc... */ /* Tack on the OAL in the eighth segment of IOCB. */ - map = pci_map_single(qdev->pdev, &tx_ring_desc->oal, + map = dma_map_single(&qdev->pdev->dev, &tx_ring_desc->oal, sizeof(struct oal), - PCI_DMA_TODEVICE); - err = pci_dma_mapping_error(qdev->pdev, map); + DMA_TO_DEVICE); + err = dma_mapping_error(&qdev->pdev->dev, map); if (err) { netif_err(qdev, tx_queued, qdev->ndev, "PCI mapping outbound address list with error: %d\n", @@ -1584,8 +1569,8 @@ static void ql_process_mac_rx_skb(struct ql_adapter *qdev, } skb_reserve(new_skb, NET_IP_ALIGN); - pci_dma_sync_single_for_cpu(qdev->pdev, sbq_desc->dma_addr, - SMALL_BUF_MAP_SIZE, PCI_DMA_FROMDEVICE); + dma_sync_single_for_cpu(&qdev->pdev->dev, sbq_desc->dma_addr, + SMALL_BUF_MAP_SIZE, DMA_FROM_DEVICE); skb_put_data(new_skb, skb->data, length); @@ -1647,7 +1632,7 @@ static void ql_process_mac_rx_skb(struct ql_adapter *qdev, } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) && (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) { /* Unfragmented ipv4 UDP frame. */ - struct iphdr *iph = (struct iphdr *) skb->data; + struct iphdr *iph = (struct iphdr *)skb->data; if (!(iph->frag_off & htons(IP_MF|IP_OFFSET))) { @@ -1707,8 +1692,8 @@ static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev, * Headers fit nicely into a small buffer. */ sbq_desc = qlge_get_curr_buf(&rx_ring->sbq); - pci_unmap_single(qdev->pdev, sbq_desc->dma_addr, - SMALL_BUF_MAP_SIZE, PCI_DMA_FROMDEVICE); + dma_unmap_single(&qdev->pdev->dev, sbq_desc->dma_addr, + SMALL_BUF_MAP_SIZE, DMA_FROM_DEVICE); skb = sbq_desc->p.skb; ql_realign_skb(skb, hdr_len); skb_put(skb, hdr_len); @@ -1737,10 +1722,10 @@ static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev, * buffer. */ sbq_desc = qlge_get_curr_buf(&rx_ring->sbq); - pci_dma_sync_single_for_cpu(qdev->pdev, - sbq_desc->dma_addr, - SMALL_BUF_MAP_SIZE, - PCI_DMA_FROMDEVICE); + dma_sync_single_for_cpu(&qdev->pdev->dev, + sbq_desc->dma_addr, + SMALL_BUF_MAP_SIZE, + DMA_FROM_DEVICE); skb_put_data(skb, sbq_desc->p.skb->data, length); } else { netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, @@ -1750,9 +1735,9 @@ static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev, skb = sbq_desc->p.skb; ql_realign_skb(skb, length); skb_put(skb, length); - pci_unmap_single(qdev->pdev, sbq_desc->dma_addr, + dma_unmap_single(&qdev->pdev->dev, sbq_desc->dma_addr, SMALL_BUF_MAP_SIZE, - PCI_DMA_FROMDEVICE); + DMA_FROM_DEVICE); sbq_desc->p.skb = NULL; } } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) { @@ -1787,9 +1772,9 @@ static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev, "No skb available, drop the packet.\n"); return NULL; } - pci_unmap_page(qdev->pdev, lbq_desc->dma_addr, + dma_unmap_page(&qdev->pdev->dev, lbq_desc->dma_addr, qdev->lbq_buf_size, - PCI_DMA_FROMDEVICE); + DMA_FROM_DEVICE); skb_reserve(skb, NET_IP_ALIGN); netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", @@ -1820,8 +1805,8 @@ static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev, int size, i = 0; sbq_desc = qlge_get_curr_buf(&rx_ring->sbq); - pci_unmap_single(qdev->pdev, sbq_desc->dma_addr, - SMALL_BUF_MAP_SIZE, PCI_DMA_FROMDEVICE); + dma_unmap_single(&qdev->pdev->dev, sbq_desc->dma_addr, + SMALL_BUF_MAP_SIZE, DMA_FROM_DEVICE); if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) { /* * This is an non TCP/UDP IP frame, so @@ -1936,7 +1921,7 @@ static void ql_process_mac_split_rx_intr(struct ql_adapter *qdev, } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) && (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) { /* Unfragmented ipv4 UDP frame. */ - struct iphdr *iph = (struct iphdr *) skb->data; + struct iphdr *iph = (struct iphdr *)skb->data; if (!(iph->frag_off & htons(IP_MF|IP_OFFSET))) { @@ -2317,7 +2302,7 @@ static int __qlge_vlan_rx_add_vid(struct ql_adapter *qdev, u16 vid) u32 enable_bit = MAC_ADDR_E; int err; - err = ql_set_mac_addr_reg(qdev, (u8 *) &enable_bit, + err = ql_set_mac_addr_reg(qdev, (u8 *)&enable_bit, MAC_ADDR_TYPE_VLAN, vid); if (err) netif_err(qdev, ifup, qdev->ndev, @@ -2348,7 +2333,7 @@ static int __qlge_vlan_rx_kill_vid(struct ql_adapter *qdev, u16 vid) u32 enable_bit = 0; int err; - err = ql_set_mac_addr_reg(qdev, (u8 *) &enable_bit, + err = ql_set_mac_addr_reg(qdev, (u8 *)&enable_bit, MAC_ADDR_TYPE_VLAN, vid); if (err) netif_err(qdev, ifup, qdev->ndev, @@ -2489,7 +2474,7 @@ static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr) mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB; mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC; - mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len); + mac_iocb_ptr->frame_len = cpu_to_le32((u32)skb->len); mac_iocb_ptr->total_hdrs_len = cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb)); mac_iocb_ptr->net_trans_offset = @@ -2527,7 +2512,7 @@ static void ql_hw_csum_setup(struct sk_buff *skb, __sum16 *check; mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB; - mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len); + mac_iocb_ptr->frame_len = cpu_to_le32((u32)skb->len); mac_iocb_ptr->net_trans_offset = cpu_to_le16(skb_network_offset(skb) | skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT); @@ -2558,7 +2543,7 @@ static netdev_tx_t qlge_send(struct sk_buff *skb, struct net_device *ndev) struct ql_adapter *qdev = netdev_priv(ndev); int tso; struct tx_ring *tx_ring; - u32 tx_ring_idx = (u32) skb->queue_mapping; + u32 tx_ring_idx = (u32)skb->queue_mapping; tx_ring = &qdev->tx_ring[tx_ring_idx]; @@ -2585,7 +2570,7 @@ static netdev_tx_t qlge_send(struct sk_buff *skb, struct net_device *ndev) mac_iocb_ptr->txq_idx = tx_ring_idx; tx_ring_desc->skb = skb; - mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len); + mac_iocb_ptr->frame_len = cpu_to_le16((u16)skb->len); if (skb_vlan_tag_present(skb)) { netif_printk(qdev, tx_queued, KERN_DEBUG, qdev->ndev, @@ -2636,17 +2621,17 @@ static netdev_tx_t qlge_send(struct sk_buff *skb, struct net_device *ndev) static void ql_free_shadow_space(struct ql_adapter *qdev) { if (qdev->rx_ring_shadow_reg_area) { - pci_free_consistent(qdev->pdev, - PAGE_SIZE, - qdev->rx_ring_shadow_reg_area, - qdev->rx_ring_shadow_reg_dma); + dma_free_coherent(&qdev->pdev->dev, + PAGE_SIZE, + qdev->rx_ring_shadow_reg_area, + qdev->rx_ring_shadow_reg_dma); qdev->rx_ring_shadow_reg_area = NULL; } if (qdev->tx_ring_shadow_reg_area) { - pci_free_consistent(qdev->pdev, - PAGE_SIZE, - qdev->tx_ring_shadow_reg_area, - qdev->tx_ring_shadow_reg_dma); + dma_free_coherent(&qdev->pdev->dev, + PAGE_SIZE, + qdev->tx_ring_shadow_reg_area, + qdev->tx_ring_shadow_reg_dma); qdev->tx_ring_shadow_reg_area = NULL; } } @@ -2654,8 +2639,8 @@ static void ql_free_shadow_space(struct ql_adapter *qdev) static int ql_alloc_shadow_space(struct ql_adapter *qdev) { qdev->rx_ring_shadow_reg_area = - pci_zalloc_consistent(qdev->pdev, PAGE_SIZE, - &qdev->rx_ring_shadow_reg_dma); + dma_alloc_coherent(&qdev->pdev->dev, PAGE_SIZE, + &qdev->rx_ring_shadow_reg_dma, GFP_ATOMIC); if (!qdev->rx_ring_shadow_reg_area) { netif_err(qdev, ifup, qdev->ndev, "Allocation of RX shadow space failed.\n"); @@ -2663,8 +2648,8 @@ static int ql_alloc_shadow_space(struct ql_adapter *qdev) } qdev->tx_ring_shadow_reg_area = - pci_zalloc_consistent(qdev->pdev, PAGE_SIZE, - &qdev->tx_ring_shadow_reg_dma); + dma_alloc_coherent(&qdev->pdev->dev, PAGE_SIZE, + &qdev->tx_ring_shadow_reg_dma, GFP_ATOMIC); if (!qdev->tx_ring_shadow_reg_area) { netif_err(qdev, ifup, qdev->ndev, "Allocation of TX shadow space failed.\n"); @@ -2673,10 +2658,10 @@ static int ql_alloc_shadow_space(struct ql_adapter *qdev) return 0; err_wqp_sh_area: - pci_free_consistent(qdev->pdev, - PAGE_SIZE, - qdev->rx_ring_shadow_reg_area, - qdev->rx_ring_shadow_reg_dma); + dma_free_coherent(&qdev->pdev->dev, + PAGE_SIZE, + qdev->rx_ring_shadow_reg_area, + qdev->rx_ring_shadow_reg_dma); return -ENOMEM; } @@ -2702,8 +2687,8 @@ static void ql_free_tx_resources(struct ql_adapter *qdev, struct tx_ring *tx_ring) { if (tx_ring->wq_base) { - pci_free_consistent(qdev->pdev, tx_ring->wq_size, - tx_ring->wq_base, tx_ring->wq_base_dma); + dma_free_coherent(&qdev->pdev->dev, tx_ring->wq_size, + tx_ring->wq_base, tx_ring->wq_base_dma); tx_ring->wq_base = NULL; } kfree(tx_ring->q); @@ -2714,8 +2699,8 @@ static int ql_alloc_tx_resources(struct ql_adapter *qdev, struct tx_ring *tx_ring) { tx_ring->wq_base = - pci_alloc_consistent(qdev->pdev, tx_ring->wq_size, - &tx_ring->wq_base_dma); + dma_alloc_coherent(&qdev->pdev->dev, tx_ring->wq_size, + &tx_ring->wq_base_dma, GFP_ATOMIC); if (!tx_ring->wq_base || tx_ring->wq_base_dma & WQ_ADDR_ALIGN) @@ -2729,8 +2714,8 @@ static int ql_alloc_tx_resources(struct ql_adapter *qdev, return 0; err: - pci_free_consistent(qdev->pdev, tx_ring->wq_size, - tx_ring->wq_base, tx_ring->wq_base_dma); + dma_free_coherent(&qdev->pdev->dev, tx_ring->wq_size, + tx_ring->wq_base, tx_ring->wq_base_dma); tx_ring->wq_base = NULL; pci_alloc_err: netif_err(qdev, ifup, qdev->ndev, "tx_ring alloc failed.\n"); @@ -2748,17 +2733,17 @@ static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring &lbq->queue[lbq->next_to_clean]; if (lbq_desc->p.pg_chunk.offset == last_offset) - pci_unmap_page(qdev->pdev, lbq_desc->dma_addr, + dma_unmap_page(&qdev->pdev->dev, lbq_desc->dma_addr, ql_lbq_block_size(qdev), - PCI_DMA_FROMDEVICE); + DMA_FROM_DEVICE); put_page(lbq_desc->p.pg_chunk.page); lbq->next_to_clean = QLGE_BQ_WRAP(lbq->next_to_clean + 1); } if (rx_ring->master_chunk.page) { - pci_unmap_page(qdev->pdev, rx_ring->chunk_dma_addr, - ql_lbq_block_size(qdev), PCI_DMA_FROMDEVICE); + dma_unmap_page(&qdev->pdev->dev, rx_ring->chunk_dma_addr, + ql_lbq_block_size(qdev), DMA_FROM_DEVICE); put_page(rx_ring->master_chunk.page); rx_ring->master_chunk.page = NULL; } @@ -2777,9 +2762,9 @@ static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring return; } if (sbq_desc->p.skb) { - pci_unmap_single(qdev->pdev, sbq_desc->dma_addr, + dma_unmap_single(&qdev->pdev->dev, sbq_desc->dma_addr, SMALL_BUF_MAP_SIZE, - PCI_DMA_FROMDEVICE); + DMA_FROM_DEVICE); dev_kfree_skb(sbq_desc->p.skb); sbq_desc->p.skb = NULL; } @@ -2820,8 +2805,8 @@ static int qlge_init_bq(struct qlge_bq *bq) __le64 *buf_ptr; int i; - bq->base = pci_alloc_consistent(qdev->pdev, QLGE_BQ_SIZE, - &bq->base_dma); + bq->base = dma_alloc_coherent(&qdev->pdev->dev, QLGE_BQ_SIZE, + &bq->base_dma, GFP_ATOMIC); if (!bq->base) { netif_err(qdev, ifup, qdev->ndev, "ring %u %s allocation failed.\n", rx_ring->cq_id, @@ -2850,8 +2835,8 @@ static void ql_free_rx_resources(struct ql_adapter *qdev, { /* Free the small buffer queue. */ if (rx_ring->sbq.base) { - pci_free_consistent(qdev->pdev, QLGE_BQ_SIZE, - rx_ring->sbq.base, rx_ring->sbq.base_dma); + dma_free_coherent(&qdev->pdev->dev, QLGE_BQ_SIZE, + rx_ring->sbq.base, rx_ring->sbq.base_dma); rx_ring->sbq.base = NULL; } @@ -2861,8 +2846,8 @@ static void ql_free_rx_resources(struct ql_adapter *qdev, /* Free the large buffer queue. */ if (rx_ring->lbq.base) { - pci_free_consistent(qdev->pdev, QLGE_BQ_SIZE, - rx_ring->lbq.base, rx_ring->lbq.base_dma); + dma_free_coherent(&qdev->pdev->dev, QLGE_BQ_SIZE, + rx_ring->lbq.base, rx_ring->lbq.base_dma); rx_ring->lbq.base = NULL; } @@ -2872,9 +2857,9 @@ static void ql_free_rx_resources(struct ql_adapter *qdev, /* Free the rx queue. */ if (rx_ring->cq_base) { - pci_free_consistent(qdev->pdev, - rx_ring->cq_size, - rx_ring->cq_base, rx_ring->cq_base_dma); + dma_free_coherent(&qdev->pdev->dev, + rx_ring->cq_size, + rx_ring->cq_base, rx_ring->cq_base_dma); rx_ring->cq_base = NULL; } } @@ -2890,8 +2875,8 @@ static int ql_alloc_rx_resources(struct ql_adapter *qdev, * Allocate the completion queue for this rx_ring. */ rx_ring->cq_base = - pci_alloc_consistent(qdev->pdev, rx_ring->cq_size, - &rx_ring->cq_base_dma); + dma_alloc_coherent(&qdev->pdev->dev, rx_ring->cq_size, + &rx_ring->cq_base_dma, GFP_ATOMIC); if (!rx_ring->cq_base) { netif_err(qdev, ifup, qdev->ndev, "rx_ring alloc failed.\n"); @@ -3008,7 +2993,7 @@ static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring) rx_ring->sbq.base_indirect_dma = shadow_reg_dma; /* PCI doorbell mem area + 0x00 for consumer index register */ - rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area; + rx_ring->cnsmr_idx_db_reg = (u32 __iomem *)doorbell_area; rx_ring->cnsmr_idx = 0; rx_ring->curr_entry = rx_ring->cq_base; @@ -3108,7 +3093,7 @@ static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring) * Assign doorbell registers for this tx_ring. */ /* TX PCI doorbell mem area for tx producer index */ - tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area; + tx_ring->prod_idx_db_reg = (u32 __iomem *)doorbell_area; tx_ring->prod_idx = 0; /* TX PCI doorbell mem area + 0x04 */ tx_ring->valid_db_reg = doorbell_area + 0x04; @@ -3131,7 +3116,7 @@ static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring) ql_init_tx_ring(qdev, tx_ring); err = ql_write_cfg(qdev, wqicb, sizeof(*wqicb), CFG_LRQ, - (u16) tx_ring->wq_id); + (u16)tx_ring->wq_id); if (err) { netif_err(qdev, ifup, qdev->ndev, "Failed to load tx_ring.\n"); return err; @@ -3431,9 +3416,9 @@ static int ql_request_irq(struct ql_adapter *qdev) &qdev->rx_ring[0]); status = request_irq(pdev->irq, qlge_isr, - test_bit(QL_MSI_ENABLED, - &qdev-> - flags) ? 0 : IRQF_SHARED, + test_bit(QL_MSI_ENABLED, &qdev->flags) + ? 0 + : IRQF_SHARED, intr_context->name, &qdev->rx_ring[0]); if (status) goto err_irq; @@ -3463,7 +3448,7 @@ static int ql_start_rss(struct ql_adapter *qdev) struct ricb *ricb = &qdev->ricb; int status = 0; int i; - u8 *hash_id = (u8 *) ricb->hash_cq_id; + u8 *hash_id = (u8 *)ricb->hash_cq_id; memset((void *)ricb, 0, sizeof(*ricb)); @@ -4125,11 +4110,11 @@ static struct net_device_stats *qlge_get_stats(struct net_device /* Get RX stats. */ pkts = mcast = dropped = errors = bytes = 0; for (i = 0; i < qdev->rss_ring_count; i++, rx_ring++) { - pkts += rx_ring->rx_packets; - bytes += rx_ring->rx_bytes; - dropped += rx_ring->rx_dropped; - errors += rx_ring->rx_errors; - mcast += rx_ring->rx_multicast; + pkts += rx_ring->rx_packets; + bytes += rx_ring->rx_bytes; + dropped += rx_ring->rx_dropped; + errors += rx_ring->rx_errors; + mcast += rx_ring->rx_multicast; } ndev->stats.rx_packets = pkts; ndev->stats.rx_bytes = bytes; @@ -4140,9 +4125,9 @@ static struct net_device_stats *qlge_get_stats(struct net_device /* Get TX stats. */ pkts = errors = bytes = 0; for (i = 0; i < qdev->tx_ring_count; i++, tx_ring++) { - pkts += tx_ring->tx_packets; - bytes += tx_ring->tx_bytes; - errors += tx_ring->tx_errors; + pkts += tx_ring->tx_packets; + bytes += tx_ring->tx_bytes; + errors += tx_ring->tx_errors; } ndev->stats.tx_packets = pkts; ndev->stats.tx_bytes = bytes; @@ -4218,7 +4203,7 @@ static void qlge_set_multicast_list(struct net_device *ndev) goto exit; i = 0; netdev_for_each_mc_addr(ha, ndev) { - if (ql_set_mac_addr_reg(qdev, (u8 *) ha->addr, + if (ql_set_mac_addr_reg(qdev, (u8 *)ha->addr, MAC_ADDR_TYPE_MULTI_MAC, i)) { netif_err(qdev, hw, qdev->ndev, "Failed to loadmulticast address.\n"); @@ -4255,7 +4240,7 @@ static int qlge_set_mac_address(struct net_device *ndev, void *p) status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK); if (status) return status; - status = ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr, + status = ql_set_mac_addr_reg(qdev, (u8 *)ndev->dev_addr, MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ); if (status) @@ -4430,13 +4415,14 @@ static int ql_init_device(struct pci_dev *pdev, struct net_device *ndev, } pci_set_master(pdev); - if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { + if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) { set_bit(QL_DMA64, &qdev->flags); - err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); + err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); } else { - err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); + err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); if (!err) - err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); + err = dma_set_coherent_mask(&pdev->dev, + DMA_BIT_MASK(32)); } if (err) { @@ -4448,8 +4434,7 @@ static int ql_init_device(struct pci_dev *pdev, struct net_device *ndev, pdev->needs_freset = 1; pci_save_state(pdev); qdev->reg_base = - ioremap(pci_resource_start(pdev, 1), - pci_resource_len(pdev, 1)); + ioremap(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1)); if (!qdev->reg_base) { dev_err(&pdev->dev, "Register mapping failed.\n"); err = -ENOMEM; @@ -4458,8 +4443,7 @@ static int ql_init_device(struct pci_dev *pdev, struct net_device *ndev, qdev->doorbell_area_size = pci_resource_len(pdev, 3); qdev->doorbell_area = - ioremap(pci_resource_start(pdev, 3), - pci_resource_len(pdev, 3)); + ioremap(pci_resource_start(pdev, 3), pci_resource_len(pdev, 3)); if (!qdev->doorbell_area) { dev_err(&pdev->dev, "Doorbell register mapping failed.\n"); err = -ENOMEM; diff --git a/drivers/staging/rtl8188eu/core/rtw_ap.c b/drivers/staging/rtl8188eu/core/rtw_ap.c index 93283c7deec4..817793b9aff2 100644 --- a/drivers/staging/rtl8188eu/core/rtw_ap.c +++ b/drivers/staging/rtl8188eu/core/rtw_ap.c @@ -264,8 +264,10 @@ void expire_timeout_chk(struct adapter *padapter) list_del_init(&psta->asoc_list); pstapriv->asoc_list_cnt--; - DBG_88E("asoc expire %pM, state = 0x%x\n", (psta->hwaddr), psta->state); - updated = ap_free_sta(padapter, psta, true, WLAN_REASON_DEAUTH_LEAVING); + DBG_88E("asoc expire %pM, state = 0x%x\n", + (psta->hwaddr), psta->state); + updated = ap_free_sta(padapter, psta, true, + WLAN_REASON_DEAUTH_LEAVING); } else { /* TODO: Aging mechanism to digest frames in sleep_q to avoid running out of xmitframe */ if (psta->sleepq_len > (NR_XMITFRAME / pstapriv->asoc_list_cnt) && @@ -294,16 +296,21 @@ void expire_timeout_chk(struct adapter *padapter) for (i = 0; i < chk_alive_num; i++) { int ret = _FAIL; - psta = rtw_get_stainfo_by_offset(pstapriv, chk_alive_list[i]); + psta = rtw_get_stainfo_by_offset(pstapriv, + chk_alive_list[i]); - if (psta->state & WIFI_SLEEP_STATE) - ret = issue_nulldata(padapter, psta->hwaddr, 0, 1, 50); - else - ret = issue_nulldata(padapter, psta->hwaddr, 0, 3, 50); + if (psta->state & WIFI_SLEEP_STATE) { + ret = issue_nulldata(padapter, psta->hwaddr, + 0, 1, 50); + } else { + ret = issue_nulldata(padapter, psta->hwaddr, + 0, 3, 50); + } psta->keep_alive_trycnt++; if (ret == _SUCCESS) { - DBG_88E("asoc check, sta(%pM) is alive\n", (psta->hwaddr)); + DBG_88E("asoc check, sta(%pM) is alive\n", + (psta->hwaddr)); psta->expire_to = pstapriv->expire_to; psta->keep_alive_trycnt = 0; continue; @@ -315,11 +322,13 @@ void expire_timeout_chk(struct adapter *padapter) psta->keep_alive_trycnt = 0; - DBG_88E("asoc expire %pM, state = 0x%x\n", (psta->hwaddr), psta->state); + DBG_88E("asoc expire %pM, state = 0x%x\n", + psta->hwaddr, psta->state); spin_lock_bh(&pstapriv->asoc_list_lock); list_del_init(&psta->asoc_list); pstapriv->asoc_list_cnt--; - updated = ap_free_sta(padapter, psta, true, WLAN_REASON_DEAUTH_LEAVING); + updated = ap_free_sta(padapter, psta, true, + WLAN_REASON_DEAUTH_LEAVING); spin_unlock_bh(&pstapriv->asoc_list_lock); } @@ -431,7 +440,8 @@ static void update_bmc_sta(struct adapter *padapter) supportRateNum = rtw_get_rateset_len((u8 *)&pcur_network->SupportedRates); network_type = rtw_check_network_type((u8 *)&pcur_network->SupportedRates); - memcpy(psta->bssrateset, &pcur_network->SupportedRates, supportRateNum); + memcpy(psta->bssrateset, &pcur_network->SupportedRates, + supportRateNum); psta->bssratelen = supportRateNum; /* b/g mode ra_bitmap */ @@ -445,7 +455,8 @@ static void update_bmc_sta(struct adapter *padapter) tx_ra_bitmap = 0xf; raid = networktype_to_raid(network_type); - init_rate = get_highest_rate_idx(tx_ra_bitmap & 0x0fffffff) & 0x3f; + init_rate = get_highest_rate_idx(tx_ra_bitmap & 0x0fffffff) & + 0x3f; /* ap mode */ rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, true); @@ -456,7 +467,8 @@ static void update_bmc_sta(struct adapter *padapter) arg = psta->mac_id & 0x1f; arg |= BIT(7); tx_ra_bitmap |= ((raid << 28) & 0xf0000000); - DBG_88E("%s, mask = 0x%x, arg = 0x%x\n", __func__, tx_ra_bitmap, arg); + DBG_88E("%s, mask = 0x%x, arg = 0x%x\n", __func__, + tx_ra_bitmap, arg); /* bitmap[0:27] = tx_rate_bitmap */ /* bitmap[28:31]= Rate Adaptive id */ @@ -647,7 +659,8 @@ static void start_bss_network(struct adapter *padapter, u8 *pbuf) rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8)); /* Beacon Control related register */ - rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&bcn_interval)); + rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, + (u8 *)(&bcn_interval)); UpdateBrateTbl(padapter, pnetwork->SupportedRates); rtw_hal_set_hwreg(padapter, HW_VAR_BASIC_RATE, pnetwork->SupportedRates); @@ -657,7 +670,10 @@ static void start_bss_network(struct adapter *padapter, u8 *pbuf) Switch_DM_Func(padapter, DYNAMIC_ALL_FUNC_ENABLE, true); } /* set channel, bwmode */ - p = rtw_get_ie((pnetwork->ies + sizeof(struct ndis_802_11_fixed_ie)), _HT_ADD_INFO_IE_, &ie_len, (pnetwork->ie_length - sizeof(struct ndis_802_11_fixed_ie))); + p = rtw_get_ie(pnetwork->ies + sizeof(struct ndis_802_11_fixed_ie), + _HT_ADD_INFO_IE_, &ie_len, + pnetwork->ie_length - + sizeof(struct ndis_802_11_fixed_ie)); if (p && ie_len) { pht_info = (struct HT_info_element *)(p + 2); @@ -682,7 +698,8 @@ static void start_bss_network(struct adapter *padapter, u8 *pbuf) */ set_channel_bwmode(padapter, cur_channel, cur_ch_offset, cur_bwmode); - DBG_88E("CH =%d, BW =%d, offset =%d\n", cur_channel, cur_bwmode, cur_ch_offset); + DBG_88E("CH =%d, BW =%d, offset =%d\n", cur_channel, cur_bwmode, + cur_ch_offset); /* */ pmlmeext->cur_channel = cur_channel; @@ -771,17 +788,19 @@ int rtw_check_beacon_data(struct adapter *padapter, u8 *pbuf, int len) cap = get_unaligned_le16(ie); /* SSID */ - p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _SSID_IE_, &ie_len, (pbss_network->ie_length - _BEACON_IE_OFFSET_)); + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _SSID_IE_, &ie_len, + pbss_network->ie_length - _BEACON_IE_OFFSET_); if (p && ie_len > 0) { memset(&pbss_network->ssid, 0, sizeof(struct ndis_802_11_ssid)); - memcpy(pbss_network->ssid.ssid, (p + 2), ie_len); + memcpy(pbss_network->ssid.ssid, p + 2, ie_len); pbss_network->ssid.ssid_length = ie_len; } /* channel */ channel = 0; pbss_network->Configuration.Length = 0; - p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _DSSET_IE_, &ie_len, (pbss_network->ie_length - _BEACON_IE_OFFSET_)); + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _DSSET_IE_, &ie_len, + (pbss_network->ie_length - _BEACON_IE_OFFSET_)); if (p && ie_len > 0) channel = *(p + 2); @@ -789,14 +808,16 @@ int rtw_check_beacon_data(struct adapter *padapter, u8 *pbuf, int len) memset(supportRate, 0, NDIS_802_11_LENGTH_RATES_EX); /* get supported rates */ - p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _SUPPORTEDRATES_IE_, &ie_len, (pbss_network->ie_length - _BEACON_IE_OFFSET_)); + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _SUPPORTEDRATES_IE_, &ie_len, + pbss_network->ie_length - _BEACON_IE_OFFSET_); if (p) { memcpy(supportRate, p + 2, ie_len); supportRateNum = ie_len; } /* get ext_supported rates */ - p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _EXT_SUPPORTEDRATES_IE_, &ie_len, pbss_network->ie_length - _BEACON_IE_OFFSET_); + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _EXT_SUPPORTEDRATES_IE_, + &ie_len, pbss_network->ie_length - _BEACON_IE_OFFSET_); if (p) { memcpy(supportRate + supportRateNum, p + 2, ie_len); supportRateNum += ie_len; @@ -807,7 +828,8 @@ int rtw_check_beacon_data(struct adapter *padapter, u8 *pbuf, int len) rtw_set_supported_rate(pbss_network->SupportedRates, network_type); /* parsing ERP_IE */ - p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _ERPINFO_IE_, &ie_len, (pbss_network->ie_length - _BEACON_IE_OFFSET_)); + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _ERPINFO_IE_, &ie_len, + pbss_network->ie_length - _BEACON_IE_OFFSET_); if (p && ie_len > 0) ERP_IE_handler(padapter, (struct ndis_802_11_var_ie *)p); @@ -824,7 +846,8 @@ int rtw_check_beacon_data(struct adapter *padapter, u8 *pbuf, int len) pairwise_cipher = 0; psecuritypriv->wpa2_group_cipher = _NO_PRIVACY_; psecuritypriv->wpa2_pairwise_cipher = _NO_PRIVACY_; - p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _RSN_IE_2_, &ie_len, (pbss_network->ie_length - _BEACON_IE_OFFSET_)); + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _RSN_IE_2_, &ie_len, + pbss_network->ie_length - _BEACON_IE_OFFSET_); if (p && ie_len > 0) { if (rtw_parse_wpa2_ie(p, ie_len + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) { psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; @@ -844,7 +867,7 @@ int rtw_check_beacon_data(struct adapter *padapter, u8 *pbuf, int len) psecuritypriv->wpa_pairwise_cipher = _NO_PRIVACY_; for (p = ie + _BEACON_IE_OFFSET_;; p += (ie_len + 2)) { p = rtw_get_ie(p, _SSN_IE_1_, &ie_len, - (pbss_network->ie_length - _BEACON_IE_OFFSET_ - (ie_len + 2))); + pbss_network->ie_length - _BEACON_IE_OFFSET_ - (ie_len + 2)); if ((p) && (!memcmp(p + 2, OUI1, 4))) { if (rtw_parse_wpa_ie(p, ie_len + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) { @@ -869,7 +892,7 @@ int rtw_check_beacon_data(struct adapter *padapter, u8 *pbuf, int len) if (pregistrypriv->wmm_enable) { for (p = ie + _BEACON_IE_OFFSET_;; p += (ie_len + 2)) { p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &ie_len, - (pbss_network->ie_length - _BEACON_IE_OFFSET_ - (ie_len + 2))); + pbss_network->ie_length - _BEACON_IE_OFFSET_ - (ie_len + 2)); if ((p) && !memcmp(p + 2, WMM_PARA_IE, 6)) { pmlmepriv->qospriv.qos_option = 1; @@ -892,7 +915,7 @@ int rtw_check_beacon_data(struct adapter *padapter, u8 *pbuf, int len) } /* parsing HT_CAP_IE */ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_CAPABILITY_IE_, &ie_len, - (pbss_network->ie_length - _BEACON_IE_OFFSET_)); + pbss_network->ie_length - _BEACON_IE_OFFSET_); if (p && ie_len > 0) { struct ieee80211_ht_cap *pht_cap = (struct ieee80211_ht_cap *)(p + 2); @@ -916,7 +939,7 @@ int rtw_check_beacon_data(struct adapter *padapter, u8 *pbuf, int len) /* parsing HT_INFO_IE */ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &ie_len, - (pbss_network->ie_length - _BEACON_IE_OFFSET_)); + pbss_network->ie_length - _BEACON_IE_OFFSET_); if (p && ie_len > 0) pHT_info_ie = p; switch (network_type) { @@ -1226,17 +1249,17 @@ void update_beacon(struct adapter *padapter, u8 ie_id, u8 *oui, u8 tx) } /* -op_mode -Set to 0 (HT pure) under the following conditions - - all STAs in the BSS are 20/40 MHz HT in 20/40 MHz BSS or - - all STAs in the BSS are 20 MHz HT in 20 MHz BSS -Set to 1 (HT non-member protection) if there may be non-HT STAs - in both the primary and the secondary channel -Set to 2 if only HT STAs are associated in BSS, - however and at least one 20 MHz HT STA is associated -Set to 3 (HT mixed mode) when one or more non-HT STAs are associated - (currently non-GF HT station is considered as non-HT STA also) -*/ + * op_mode + * Set to 0 (HT pure) under the following conditions + * - all STAs in the BSS are 20/40 MHz HT in 20/40 MHz BSS or + * - all STAs in the BSS are 20 MHz HT in 20 MHz BSS + * Set to 1 (HT non-member protection) if there may be non-HT STAs + * in both the primary and the secondary channel + * Set to 2 if only HT STAs are associated in BSS, + * however and at least one 20 MHz HT STA is associated + * Set to 3 (HT mixed mode) when one or more non-HT STAs are associated + * (currently non-GF HT station is considered as non-HT STA also) + */ static int rtw_ht_operation_update(struct adapter *padapter) { u16 cur_op_mode, new_op_mode; diff --git a/drivers/staging/rtl8188eu/core/rtw_efuse.c b/drivers/staging/rtl8188eu/core/rtw_efuse.c index c525682d0edf..9bb3ec0cd62f 100644 --- a/drivers/staging/rtl8188eu/core/rtw_efuse.c +++ b/drivers/staging/rtl8188eu/core/rtw_efuse.c @@ -370,28 +370,27 @@ static u16 Efuse_GetCurrentSize(struct adapter *pAdapter) while (efuse_OneByteRead(pAdapter, efuse_addr, &efuse_data) && AVAILABLE_EFUSE_ADDR(efuse_addr)) { - if (efuse_data != 0xFF) { - if ((efuse_data & 0x1F) == 0x0F) { /* extended header */ - hoffset = efuse_data; - efuse_addr++; - efuse_OneByteRead(pAdapter, efuse_addr, &efuse_data); - if ((efuse_data & 0x0F) == 0x0F) { - efuse_addr++; - continue; - } else { - hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1); - hworden = efuse_data & 0x0F; - } - } else { - hoffset = (efuse_data >> 4) & 0x0F; - hworden = efuse_data & 0x0F; - } - word_cnts = Efuse_CalculateWordCnts(hworden); - /* read next header */ - efuse_addr = efuse_addr + (word_cnts * 2) + 1; - } else { + if (efuse_data == 0xFF) break; + if ((efuse_data & 0x1F) == 0x0F) { /* extended header */ + hoffset = efuse_data; + efuse_addr++; + efuse_OneByteRead(pAdapter, efuse_addr, &efuse_data); + if ((efuse_data & 0x0F) == 0x0F) { + efuse_addr++; + continue; + } else { + hoffset = ((hoffset & 0xE0) >> 5) | + ((efuse_data & 0xF0) >> 1); + hworden = efuse_data & 0x0F; + } + } else { + hoffset = (efuse_data >> 4) & 0x0F; + hworden = efuse_data & 0x0F; } + word_cnts = Efuse_CalculateWordCnts(hworden); + /* read next header */ + efuse_addr = efuse_addr + (word_cnts * 2) + 1; } rtw_hal_set_hwreg(pAdapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr); diff --git a/drivers/staging/rtl8188eu/core/rtw_ieee80211.c b/drivers/staging/rtl8188eu/core/rtw_ieee80211.c index e186982d5908..caf600eba03b 100644 --- a/drivers/staging/rtl8188eu/core/rtw_ieee80211.c +++ b/drivers/staging/rtl8188eu/core/rtw_ieee80211.c @@ -253,11 +253,11 @@ int rtw_generate_ie(struct registry_priv *pregistrypriv) } /* DS parameter set */ - ie = rtw_set_ie(ie, _DSSET_IE_, 1, (u8 *)&(pdev_network->Configuration.DSConfig), &sz); + ie = rtw_set_ie(ie, _DSSET_IE_, 1, (u8 *)&pdev_network->Configuration.DSConfig, &sz); /* IBSS Parameter Set */ - ie = rtw_set_ie(ie, _IBSS_PARA_IE_, 2, (u8 *)&(pdev_network->Configuration.ATIMWindow), &sz); + ie = rtw_set_ie(ie, _IBSS_PARA_IE_, 2, (u8 *)&pdev_network->Configuration.ATIMWindow, &sz); if (rateLen > 8) ie = rtw_set_ie(ie, _EXT_SUPPORTEDRATES_IE_, (rateLen - 8), (pdev_network->SupportedRates + 8), &sz); diff --git a/drivers/staging/rtl8188eu/core/rtw_led.c b/drivers/staging/rtl8188eu/core/rtw_led.c index d1406cc99768..32dccae186ca 100644 --- a/drivers/staging/rtl8188eu/core/rtw_led.c +++ b/drivers/staging/rtl8188eu/core/rtw_led.c @@ -90,7 +90,6 @@ static void SwLedBlink1(struct LED_871x *pLed) { struct adapter *padapter = pLed->padapter; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - u8 bStopBlinking = false; /* Change LED according to BlinkingLedState specified. */ if (pLed->BlinkingLedState == RTW_LED_ON) { @@ -128,9 +127,7 @@ static void SwLedBlink1(struct LED_871x *pLed) break; case LED_BLINK_SCAN: pLed->BlinkTimes--; - if (pLed->BlinkTimes == 0) - bStopBlinking = true; - if (bStopBlinking) { + if (pLed->BlinkTimes == 0) { if (check_fwstate(pmlmepriv, _FW_LINKED)) { pLed->bLedLinkBlinkInProgress = true; pLed->CurrLedState = LED_BLINK_NORMAL; @@ -164,9 +161,7 @@ static void SwLedBlink1(struct LED_871x *pLed) break; case LED_BLINK_TXRX: pLed->BlinkTimes--; - if (pLed->BlinkTimes == 0) - bStopBlinking = true; - if (bStopBlinking) { + if (pLed->BlinkTimes == 0) { if (check_fwstate(pmlmepriv, _FW_LINKED)) { pLed->bLedLinkBlinkInProgress = true; pLed->CurrLedState = LED_BLINK_NORMAL; @@ -188,7 +183,6 @@ static void SwLedBlink1(struct LED_871x *pLed) msecs_to_jiffies(LED_BLINK_NO_LINK_INTERVAL_ALPHA)); RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState)); } - pLed->BlinkTimes = 0; pLed->bLedBlinkInProgress = false; } else { if (pLed->bLedOn) @@ -208,12 +202,7 @@ static void SwLedBlink1(struct LED_871x *pLed) msecs_to_jiffies(LED_BLINK_SCAN_INTERVAL_ALPHA)); break; case LED_BLINK_WPS_STOP: /* WPS success */ - if (pLed->BlinkingLedState == RTW_LED_ON) - bStopBlinking = false; - else - bStopBlinking = true; - - if (bStopBlinking) { + if (pLed->BlinkingLedState != RTW_LED_ON) { pLed->bLedLinkBlinkInProgress = true; pLed->CurrLedState = LED_BLINK_NORMAL; if (pLed->bLedOn) diff --git a/drivers/staging/rtl8188eu/core/rtw_mlme_ext.c b/drivers/staging/rtl8188eu/core/rtw_mlme_ext.c index 04897cd48370..8d035f67ef61 100644 --- a/drivers/staging/rtl8188eu/core/rtw_mlme_ext.c +++ b/drivers/staging/rtl8188eu/core/rtw_mlme_ext.c @@ -1781,7 +1781,7 @@ static void issue_action_BSSCoexistPacket(struct adapter *padapter) p = rtw_get_ie(pbss_network->ies + _FIXED_IE_LENGTH_, _HT_CAPABILITY_IE_, &len, pbss_network->ie_length - _FIXED_IE_LENGTH_); if (!p || len == 0) { /* non-HT */ - if ((pbss_network->Configuration.DSConfig <= 0) || (pbss_network->Configuration.DSConfig > 14)) + if (pbss_network->Configuration.DSConfig <= 0) continue; ICS[0][pbss_network->Configuration.DSConfig] = 1; @@ -1932,11 +1932,11 @@ static void site_survey(struct adapter *padapter) if (pmlmeext->sitesurvey_res.ssid[i].ssid_length) { /* todo: to issue two probe req??? */ issue_probereq(padapter, - &(pmlmeext->sitesurvey_res.ssid[i]), + &pmlmeext->sitesurvey_res.ssid[i], NULL, false); /* msleep(SURVEY_TO>>1); */ issue_probereq(padapter, - &(pmlmeext->sitesurvey_res.ssid[i]), + &pmlmeext->sitesurvey_res.ssid[i], NULL, false); } } diff --git a/drivers/staging/rtl8188eu/core/rtw_pwrctrl.c b/drivers/staging/rtl8188eu/core/rtw_pwrctrl.c index c4f58507dbfd..c000382c96d9 100644 --- a/drivers/staging/rtl8188eu/core/rtw_pwrctrl.c +++ b/drivers/staging/rtl8188eu/core/rtw_pwrctrl.c @@ -173,7 +173,7 @@ int ips_leave(struct adapter *padapter) DBG_88E_LEVEL(_drv_info_, "nolinked power save leave\n"); - if ((_WEP40_ == psecuritypriv->dot11PrivacyAlgrthm) || (_WEP104_ == psecuritypriv->dot11PrivacyAlgrthm)) { + if ((psecuritypriv->dot11PrivacyAlgrthm == _WEP40_) || (psecuritypriv->dot11PrivacyAlgrthm == _WEP104_)) { DBG_88E("==>%s, channel(%d), processing(%x)\n", __func__, padapter->mlmeextpriv.cur_channel, pwrpriv->bips_processing); set_channel_bwmode(padapter, padapter->mlmeextpriv.cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); for (keyid = 0; keyid < 4; keyid++) { diff --git a/drivers/staging/rtl8188eu/core/rtw_recv.c b/drivers/staging/rtl8188eu/core/rtw_recv.c index d4278361e002..a036ef104198 100644 --- a/drivers/staging/rtl8188eu/core/rtw_recv.c +++ b/drivers/staging/rtl8188eu/core/rtw_recv.c @@ -1525,21 +1525,14 @@ static int amsdu_to_msdu(struct adapter *padapter, struct recv_frame *prframe) /* Allocate new skb for releasing to upper layer */ sub_skb = dev_alloc_skb(nSubframe_Length + 12); - if (sub_skb) { - skb_reserve(sub_skb, 12); - skb_put_data(sub_skb, pdata, nSubframe_Length); - } else { - sub_skb = skb_clone(prframe->pkt, GFP_ATOMIC); - if (sub_skb) { - sub_skb->data = pdata; - sub_skb->len = nSubframe_Length; - skb_set_tail_pointer(sub_skb, nSubframe_Length); - } else { - DBG_88E("skb_clone() Fail!!! , nr_subframes=%d\n", nr_subframes); - break; - } + if (!sub_skb) { + DBG_88E("dev_alloc_skb() Fail!!! , nr_subframes=%d\n", nr_subframes); + break; } + skb_reserve(sub_skb, 12); + skb_put_data(sub_skb, pdata, nSubframe_Length); + subframes[nr_subframes++] = sub_skb; if (nr_subframes >= MAX_SUBFRAME_COUNT) { diff --git a/drivers/staging/rtl8188eu/hal/fw.c b/drivers/staging/rtl8188eu/hal/fw.c index 486ee4bd4744..3d1d29e9f8e0 100644 --- a/drivers/staging/rtl8188eu/hal/fw.c +++ b/drivers/staging/rtl8188eu/hal/fw.c @@ -111,7 +111,7 @@ static int _rtl88e_fw_free_to_go(struct adapter *adapt) do { value32 = usb_read32(adapt, REG_MCUFWDL); - if (value32 & FWDL_ChkSum_rpt) + if (value32 & FWDL_CHKSUM_RPT) break; } while (counter++ < POLLING_READY_TIMEOUT_COUNT); @@ -146,7 +146,7 @@ int rtl88eu_download_fw(struct adapter *adapt) struct dvobj_priv *dvobj = adapter_to_dvobj(adapt); struct device *device = dvobj_to_dev(dvobj); const struct firmware *fw; - const char fw_name[] = "rtlwifi/rtl8188eufw.bin"; + static const char fw_name[] = "rtlwifi/rtl8188eufw.bin"; struct rtl92c_firmware_header *pfwheader = NULL; u8 *download_data, *fw_data; size_t download_size; @@ -192,7 +192,8 @@ int rtl88eu_download_fw(struct adapter *adapt) rtl88e_firmware_selfreset(adapt); } _rtl88e_enable_fw_download(adapt, true); - usb_write8(adapt, REG_MCUFWDL, usb_read8(adapt, REG_MCUFWDL) | FWDL_ChkSum_rpt); + usb_write8(adapt, REG_MCUFWDL, + usb_read8(adapt, REG_MCUFWDL) | FWDL_CHKSUM_RPT); _rtl88e_write_fw(adapt, download_data, download_size); _rtl88e_enable_fw_download(adapt, false); diff --git a/drivers/staging/rtl8188eu/hal/odm.c b/drivers/staging/rtl8188eu/hal/odm.c index 698377ea60ee..28974808839d 100644 --- a/drivers/staging/rtl8188eu/hal/odm.c +++ b/drivers/staging/rtl8188eu/hal/odm.c @@ -5,8 +5,6 @@ * ******************************************************************************/ -/* include files */ - #include "odm_precomp.h" #include "phy.h" @@ -193,7 +191,7 @@ void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm) odm_DIG(pDM_Odm); odm_CCKPacketDetectionThresh(pDM_Odm); - if (*(pDM_Odm->pbPowerSaving)) + if (*pDM_Odm->pbPowerSaving) return; odm_RefreshRateAdaptiveMask(pDM_Odm); @@ -229,13 +227,13 @@ void odm_CommonInfoSelfUpdate(struct odm_dm_struct *pDM_Odm) u8 i; struct sta_info *pEntry; - if (*(pDM_Odm->pBandWidth) == ODM_BW40M) { - if (*(pDM_Odm->pSecChOffset) == 1) - pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 2; - else if (*(pDM_Odm->pSecChOffset) == 2) - pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 2; + if (*pDM_Odm->pBandWidth == ODM_BW40M) { + if (*pDM_Odm->pSecChOffset == 1) + pDM_Odm->ControlChannel = *pDM_Odm->pChannel - 2; + else if (*pDM_Odm->pSecChOffset == 2) + pDM_Odm->ControlChannel = *pDM_Odm->pChannel + 2; } else { - pDM_Odm->ControlChannel = *(pDM_Odm->pChannel); + pDM_Odm->ControlChannel = *pDM_Odm->pChannel; } for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { @@ -270,16 +268,16 @@ void odm_CmnInfoInit_Debug(struct odm_dm_struct *pDM_Odm) void odm_CmnInfoHook_Debug(struct odm_dm_struct *pDM_Odm) { ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoHook_Debug==>\n")); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumTxBytesUnicast=%llu\n", *(pDM_Odm->pNumTxBytesUnicast))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumRxBytesUnicast=%llu\n", *(pDM_Odm->pNumRxBytesUnicast))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pWirelessMode=0x%x\n", *(pDM_Odm->pWirelessMode))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecChOffset=%d\n", *(pDM_Odm->pSecChOffset))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecurity=%d\n", *(pDM_Odm->pSecurity))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBandWidth=%d\n", *(pDM_Odm->pBandWidth))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pChannel=%d\n", *(pDM_Odm->pChannel))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumTxBytesUnicast=%llu\n", *pDM_Odm->pNumTxBytesUnicast)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumRxBytesUnicast=%llu\n", *pDM_Odm->pNumRxBytesUnicast)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pWirelessMode=0x%x\n", *pDM_Odm->pWirelessMode)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecChOffset=%d\n", *pDM_Odm->pSecChOffset)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecurity=%d\n", *pDM_Odm->pSecurity)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBandWidth=%d\n", *pDM_Odm->pBandWidth)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pChannel=%d\n", *pDM_Odm->pChannel)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbScanInProcess=%d\n", *(pDM_Odm->pbScanInProcess))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbPowerSaving=%d\n", *(pDM_Odm->pbPowerSaving))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbScanInProcess=%d\n", *pDM_Odm->pbScanInProcess)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbPowerSaving=%d\n", *pDM_Odm->pbPowerSaving)); } void odm_CmnInfoUpdate_Debug(struct odm_dm_struct *pDM_Odm) @@ -348,7 +346,7 @@ void odm_DIG(struct odm_dm_struct *pDM_Odm) return; } - if (*(pDM_Odm->pbScanInProcess)) { + if (*pDM_Odm->pbScanInProcess) { ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: In Scan Progress\n")); return; } @@ -508,7 +506,7 @@ void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm) { struct adapter *adapter = pDM_Odm->Adapter; u32 ret_value; - struct false_alarm_stats *FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); + struct false_alarm_stats *FalseAlmCnt = &pDM_Odm->FalseAlmCnt; if (!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT)) return; @@ -581,7 +579,7 @@ void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm) void odm_CCKPacketDetectionThresh(struct odm_dm_struct *pDM_Odm) { u8 CurCCK_CCAThres; - struct false_alarm_stats *FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); + struct false_alarm_stats *FalseAlmCnt = &pDM_Odm->FalseAlmCnt; if (!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD | ODM_BB_FA_CNT))) return; @@ -739,7 +737,7 @@ u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid, u32 ra_mask, u } else if (rssi_level == DM_RATR_STA_MIDDLE) { rate_bitmap = 0x000ff000; } else { - if (*(pDM_Odm->pBandWidth) == ODM_BW40M) + if (*pDM_Odm->pBandWidth == ODM_BW40M) rate_bitmap = 0x000ff015; else rate_bitmap = 0x000ff005; @@ -945,7 +943,7 @@ void odm_TXPowerTrackingInit(struct odm_dm_struct *pDM_Odm) { pDM_Odm->RFCalibrateInfo.bTXPowerTracking = true; pDM_Odm->RFCalibrateInfo.TXPowercount = 0; - if (*(pDM_Odm->mp_mode) != 1) + if (*pDM_Odm->mp_mode != 1) pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true; MSG_88E("pDM_Odm TxPowerTrackControl = %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl); @@ -1035,11 +1033,11 @@ void odm_EdcaTurboCheckCE(struct odm_dm_struct *pDM_Odm) u64 cur_tx_bytes = 0; u64 cur_rx_bytes = 0; u8 bbtchange = false; - struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); - struct recv_priv *precvpriv = &(Adapter->recvpriv); + struct xmit_priv *pxmitpriv = &Adapter->xmitpriv; + struct recv_priv *precvpriv = &Adapter->recvpriv; struct registry_priv *pregpriv = &Adapter->registrypriv; - struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; if (pregpriv->wifi_spec == 1) /* (pmlmeinfo->HT_enable == 0)) */ goto dm_CheckEdcaTurbo_EXIT; diff --git a/drivers/staging/rtl8188eu/hal/odm_hwconfig.c b/drivers/staging/rtl8188eu/hal/odm_hwconfig.c index a6f2731b076d..65a346ae3cb0 100644 --- a/drivers/staging/rtl8188eu/hal/odm_hwconfig.c +++ b/drivers/staging/rtl8188eu/hal/odm_hwconfig.c @@ -5,8 +5,6 @@ * ******************************************************************************/ -/* include files */ - #include "odm_precomp.h" #define READ_AND_CONFIG READ_AND_CONFIG_MP diff --git a/drivers/staging/rtl8188eu/hal/phy.c b/drivers/staging/rtl8188eu/hal/phy.c index b9025815b682..920688fc9e9f 100644 --- a/drivers/staging/rtl8188eu/hal/phy.c +++ b/drivers/staging/rtl8188eu/hal/phy.c @@ -345,8 +345,8 @@ static void dm_txpwr_track_setpwr(struct odm_dm_struct *dm_odm) { if (dm_odm->BbSwingFlagOfdm || dm_odm->BbSwingFlagCck) { ODM_RT_TRACE(dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("dm_txpwr_track_setpwr CH=%d\n", *(dm_odm->pChannel))); - phy_set_tx_power_level(dm_odm->Adapter, *(dm_odm->pChannel)); + ("dm_txpwr_track_setpwr CH=%d\n", *dm_odm->pChannel)); + phy_set_tx_power_level(dm_odm->Adapter, *dm_odm->pChannel); dm_odm->BbSwingFlagOfdm = false; dm_odm->BbSwingFlagCck = false; } @@ -786,7 +786,7 @@ static void pathb_fill_iqk(struct adapter *adapt, bool iqkok, s32 result[][8], } } -static void save_adda_registers(struct adapter *adapt, u32 *addareg, +static void save_adda_registers(struct adapter *adapt, const u32 *addareg, u32 *backup, u32 register_num) { u32 i; @@ -795,7 +795,7 @@ static void save_adda_registers(struct adapter *adapt, u32 *addareg, backup[i] = phy_query_bb_reg(adapt, addareg[i], bMaskDWord); } -static void save_mac_registers(struct adapter *adapt, u32 *mac_reg, +static void save_mac_registers(struct adapter *adapt, const u32 *mac_reg, u32 *backup) { u32 i; @@ -806,7 +806,7 @@ static void save_mac_registers(struct adapter *adapt, u32 *mac_reg, backup[i] = usb_read32(adapt, mac_reg[i]); } -static void reload_adda_reg(struct adapter *adapt, u32 *adda_reg, +static void reload_adda_reg(struct adapter *adapt, const u32 *adda_reg, u32 *backup, u32 regiester_num) { u32 i; @@ -815,8 +815,8 @@ static void reload_adda_reg(struct adapter *adapt, u32 *adda_reg, phy_set_bb_reg(adapt, adda_reg[i], bMaskDWord, backup[i]); } -static void reload_mac_registers(struct adapter *adapt, - u32 *mac_reg, u32 *backup) +static void reload_mac_registers(struct adapter *adapt, const u32 *mac_reg, + u32 *backup) { u32 i; @@ -826,7 +826,7 @@ static void reload_mac_registers(struct adapter *adapt, usb_write32(adapt, mac_reg[i], backup[i]); } -static void path_adda_on(struct adapter *adapt, u32 *adda_reg, +static void path_adda_on(struct adapter *adapt, const u32 *adda_reg, bool is_path_a_on, bool is2t) { u32 path_on; @@ -844,7 +844,8 @@ static void path_adda_on(struct adapter *adapt, u32 *adda_reg, phy_set_bb_reg(adapt, adda_reg[i], bMaskDWord, path_on); } -static void mac_setting_calibration(struct adapter *adapt, u32 *mac_reg, u32 *backup) +static void mac_setting_calibration(struct adapter *adapt, const u32 *mac_reg, + u32 *backup) { u32 i = 0; @@ -952,30 +953,31 @@ static void phy_iq_calibrate(struct adapter *adapt, s32 result[][8], struct odm_dm_struct *dm_odm = &adapt->HalData->odmpriv; u32 i; u8 path_a_ok, path_b_ok; - u32 adda_reg[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN}; - - u32 iqk_mac_reg[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; - + static const u32 adda_reg[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN + }; + static const u32 iqk_mac_reg[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG + }; /* since 92C & 92D have the different define in IQK_BB_REG */ - u32 iqk_bb_reg_92c[IQK_BB_REG_NUM] = { - rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, - rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, - rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD}; + static const u32 iqk_bb_reg_92c[IQK_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD + }; u32 retry_count = 9; - if (*(dm_odm->mp_mode) == 1) + if (*dm_odm->mp_mode == 1) retry_count = 9; else retry_count = 2; @@ -1320,7 +1322,7 @@ void rtl88eu_phy_lc_calibrate(struct adapter *adapt) if (singletone || carrier_sup) return; - while (*(dm_odm->pbScanInProcess) && timecount < timeout) { + while (*dm_odm->pbScanInProcess && timecount < timeout) { mdelay(50); timecount += 50; } diff --git a/drivers/staging/rtl8188eu/hal/rf.c b/drivers/staging/rtl8188eu/hal/rf.c index 00a9f692bb06..6702f263c770 100644 --- a/drivers/staging/rtl8188eu/hal/rf.c +++ b/drivers/staging/rtl8188eu/hal/rf.c @@ -79,7 +79,7 @@ void rtl88eu_phy_rf6052_set_cck_txpower(struct adapter *adapt, u8 *powerlevel) } } for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) { - ptr = (u8 *)(&(tx_agc[idx1])); + ptr = (u8 *)(&tx_agc[idx1]); for (idx2 = 0; idx2 < 4; idx2++) { if (*ptr > RF6052_MAX_TX_PWR) *ptr = RF6052_MAX_TX_PWR; diff --git a/drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c b/drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c index 371e746915dd..176716d3e903 100644 --- a/drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c +++ b/drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c @@ -256,7 +256,7 @@ static void ConstructBeacon(struct adapter *adapt, u8 *pframe, u32 *pLength) pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, min_t(u32, rate_len, 8), cur_network->SupportedRates, &pktlen); /* DS parameter set */ - pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pktlen); + pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&cur_network->Configuration.DSConfig, &pktlen); if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) { u32 ATIMWindow; diff --git a/drivers/staging/rtl8188eu/hal/rtl8188e_dm.c b/drivers/staging/rtl8188eu/hal/rtl8188e_dm.c index 241f55b92808..1af919ff6d93 100644 --- a/drivers/staging/rtl8188eu/hal/rtl8188e_dm.c +++ b/drivers/staging/rtl8188eu/hal/rtl8188e_dm.c @@ -29,9 +29,6 @@ static void dm_InitGPIOSetting(struct adapter *Adapter) usb_write8(Adapter, REG_GPIO_MUXCFG, tmp1byte); } -/* */ -/* functions */ -/* */ static void Init_ODM_ComInfo_88E(struct adapter *Adapter) { struct hal_data_8188e *hal_data = Adapter->HalData; diff --git a/drivers/staging/rtl8188eu/include/osdep_service.h b/drivers/staging/rtl8188eu/include/osdep_service.h index c0114ad79788..0d3e4a6e7e85 100644 --- a/drivers/staging/rtl8188eu/include/osdep_service.h +++ b/drivers/staging/rtl8188eu/include/osdep_service.h @@ -50,7 +50,7 @@ struct __queue { static inline struct list_head *get_list_head(struct __queue *queue) { - return &(queue->queue); + return &queue->queue; } static inline int rtw_netif_queue_stopped(struct net_device *pnetdev) diff --git a/drivers/staging/rtl8188eu/include/rtl8188e_spec.h b/drivers/staging/rtl8188eu/include/rtl8188e_spec.h index dd943c831d91..be30c9434a29 100644 --- a/drivers/staging/rtl8188eu/include/rtl8188e_spec.h +++ b/drivers/staging/rtl8188eu/include/rtl8188e_spec.h @@ -817,7 +817,7 @@ So the following defines for 92C is not entire!!!!!! /* 2 MCUFWDL */ #define MCUFWDL_EN BIT(0) #define MCUFWDL_RDY BIT(1) -#define FWDL_ChkSum_rpt BIT(2) +#define FWDL_CHKSUM_RPT BIT(2) #define MACINI_RDY BIT(3) #define BBINI_RDY BIT(4) #define RFINI_RDY BIT(5) diff --git a/drivers/staging/rtl8188eu/os_dep/ioctl_linux.c b/drivers/staging/rtl8188eu/os_dep/ioctl_linux.c index 9a89791720e0..d5968ef9f43d 100644 --- a/drivers/staging/rtl8188eu/os_dep/ioctl_linux.c +++ b/drivers/staging/rtl8188eu/os_dep/ioctl_linux.c @@ -93,7 +93,7 @@ static char *translate_scan(struct adapter *padapter, struct wlan_network *pnetwork, char *start, char *stop) { - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct iw_event iwe; u16 cap; __le16 le_tmp; @@ -417,7 +417,7 @@ static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, ret = -EOPNOTSUPP; goto exit; } - memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength); + memcpy(&psecuritypriv->dot11DefKey[wep_key_idx].skey[0], pwep->KeyMaterial, pwep->KeyLength); psecuritypriv->dot11DefKeylen[wep_key_idx] = pwep->KeyLength; rtw_set_key(padapter, psecuritypriv, wep_key_idx, 0); } @@ -444,8 +444,8 @@ static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, min_t(u16, param->u.crypt.key_len, 16)); if (strcmp(param->u.crypt.alg, "TKIP") == 0) { /* set mic key */ - memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8); - memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8); + memcpy(psta->dot11tkiptxmickey.skey, ¶m->u.crypt.key[16], 8); + memcpy(psta->dot11tkiprxmickey.skey, ¶m->u.crypt.key[24], 8); padapter->securitypriv.busetkipkey = false; } @@ -454,8 +454,8 @@ static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, rtw_setstakey_cmd(padapter, (unsigned char *)psta, true); } else { /* group key */ memcpy(padapter->securitypriv.dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, min_t(u16, param->u.crypt.key_len, 16 )); - memcpy(padapter->securitypriv.dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); - memcpy(padapter->securitypriv.dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); + memcpy(padapter->securitypriv.dot118021XGrptxmickey[param->u.crypt.idx].skey, ¶m->u.crypt.key[16], 8); + memcpy(padapter->securitypriv.dot118021XGrprxmickey[param->u.crypt.idx].skey, ¶m->u.crypt.key[24], 8); padapter->securitypriv.binstallGrpkey = true; DBG_88E(" ~~~~set sta key:groupkey\n"); @@ -620,7 +620,7 @@ static int rtw_wx_get_name(struct net_device *dev, u32 ht_ielen = 0; char *p; u8 ht_cap = false; - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wlan_bssid_ex *pcur_bss = &pmlmepriv->cur_network.network; NDIS_802_11_RATES_EX *prates = NULL; @@ -669,7 +669,7 @@ static int rtw_wx_get_freq(struct net_device *dev, union iwreq_data *wrqu, char *extra) { struct adapter *padapter = (struct adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wlan_bssid_ex *pcur_bss = &pmlmepriv->cur_network.network; if (check_fwstate(pmlmepriv, _FW_LINKED)) { @@ -738,7 +738,7 @@ static int rtw_wx_get_mode(struct net_device *dev, struct iw_request_info *a, union iwreq_data *wrqu, char *b) { struct adapter *padapter = (struct adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, (" rtw_wx_get_mode\n")); @@ -938,10 +938,10 @@ static int rtw_wx_set_wap(struct net_device *dev, uint ret = 0; struct adapter *padapter = (struct adapter *)rtw_netdev_priv(dev); struct sockaddr *temp = (struct sockaddr *)awrq; - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct list_head *phead; u8 *dst_bssid, *src_bssid; - struct __queue *queue = &(pmlmepriv->scanned_queue); + struct __queue *queue = &pmlmepriv->scanned_queue; struct wlan_network *pnetwork = NULL; enum ndis_802_11_auth_mode authmode; @@ -1002,7 +1002,7 @@ static int rtw_wx_get_wap(struct net_device *dev, union iwreq_data *wrqu, char *extra) { struct adapter *padapter = (struct adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wlan_bssid_ex *pcur_bss = &pmlmepriv->cur_network.network; wrqu->ap_addr.sa_family = ARPHRD_ETHER; @@ -1188,8 +1188,8 @@ static int rtw_wx_get_scan(struct net_device *dev, struct iw_request_info *a, { struct list_head *plist, *phead; struct adapter *padapter = (struct adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct __queue *queue = &(pmlmepriv->scanned_queue); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct __queue *queue = &pmlmepriv->scanned_queue; struct wlan_network *pnetwork = NULL; char *ev = extra; char *stop = ev + wrqu->data.length; @@ -1217,7 +1217,7 @@ static int rtw_wx_get_scan(struct net_device *dev, struct iw_request_info *a, break; } - spin_lock_bh(&(pmlmepriv->scanned_queue.lock)); + spin_lock_bh(&pmlmepriv->scanned_queue.lock); phead = get_list_head(queue); plist = phead->next; @@ -1358,7 +1358,7 @@ static int rtw_wx_get_essid(struct net_device *dev, { u32 len; struct adapter *padapter = (struct adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wlan_bssid_ex *pcur_bss = &pmlmepriv->cur_network.network; RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_wx_get_essid\n")); @@ -1564,7 +1564,7 @@ static int rtw_wx_set_enc(struct net_device *dev, struct ndis_802_11_wep wep; enum ndis_802_11_auth_mode authmode; - struct iw_point *erq = &(wrqu->encoding); + struct iw_point *erq = &wrqu->encoding; struct adapter *padapter = (struct adapter *)rtw_netdev_priv(dev); struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; @@ -1675,8 +1675,8 @@ static int rtw_wx_get_enc(struct net_device *dev, { uint key; struct adapter *padapter = (struct adapter *)rtw_netdev_priv(dev); - struct iw_point *erq = &(wrqu->encoding); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct iw_point *erq = &wrqu->encoding; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; if (!check_fwstate(pmlmepriv, _FW_LINKED)) { if (!check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) { @@ -1759,7 +1759,7 @@ static int rtw_wx_set_auth(struct net_device *dev, union iwreq_data *wrqu, char *extra) { struct adapter *padapter = (struct adapter *)rtw_netdev_priv(dev); - struct iw_param *param = (struct iw_param *)&(wrqu->param); + struct iw_param *param = (struct iw_param *)&wrqu->param; int ret = 0; switch (param->flags & IW_AUTH_INDEX) { @@ -2012,14 +2012,9 @@ static int wpa_supplicant_ioctl(struct net_device *dev, struct iw_point *p) if (!p->pointer || p->length != sizeof(struct ieee_param)) return -EINVAL; - param = (struct ieee_param *)rtw_malloc(p->length); - if (!param) - return -ENOMEM; - - if (copy_from_user(param, p->pointer, p->length)) { - kfree(param); - return -EFAULT; - } + param = memdup_user(p->pointer, p->length); + if (IS_ERR(param)) + return PTR_ERR(param); switch (param->cmd) { case IEEE_CMD_SET_WPA_PARAM: @@ -2093,7 +2088,7 @@ static int set_group_key(struct adapter *padapter, u8 *key, u8 alg, int keyid) u8 keylen; struct cmd_obj *pcmd; struct setkey_parm *psetkeyparm; - struct cmd_priv *pcmdpriv = &(padapter->cmdpriv); + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; int res = _SUCCESS; DBG_88E("%s\n", __func__); @@ -2130,7 +2125,7 @@ static int set_group_key(struct adapter *padapter, u8 *key, u8 alg, int keyid) keylen = 16; } - memcpy(&(psetkeyparm->key[0]), key, keylen); + memcpy(&psetkeyparm->key[0], key, keylen); pcmd->cmdcode = _SetKey_CMD_; pcmd->parmbuf = (u8 *)psetkeyparm; @@ -2173,7 +2168,7 @@ static int rtw_set_encryption(struct net_device *dev, struct ieee_param *param, struct sta_info *psta = NULL, *pbcmc_sta = NULL; struct adapter *padapter = (struct adapter *)rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct security_priv *psecuritypriv = &(padapter->securitypriv); + struct security_priv *psecuritypriv = &padapter->securitypriv; struct sta_priv *pstapriv = &padapter->stapriv; DBG_88E("%s\n", __func__); @@ -2245,7 +2240,7 @@ static int rtw_set_encryption(struct net_device *dev, struct ieee_param *param, psecuritypriv->dot11PrivacyKeyIndex = wep_key_idx; - memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength); + memcpy(&psecuritypriv->dot11DefKey[wep_key_idx].skey[0], pwep->KeyMaterial, pwep->KeyLength); psecuritypriv->dot11DefKeylen[wep_key_idx] = pwep->KeyLength; @@ -2256,7 +2251,7 @@ static int rtw_set_encryption(struct net_device *dev, struct ieee_param *param, /* don't update "psecuritypriv->dot11PrivacyAlgrthm" and */ /* psecuritypriv->dot11PrivacyKeyIndex = keyid", but can rtw_set_key to cam */ - memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength); + memcpy(&psecuritypriv->dot11DefKey[wep_key_idx].skey[0], pwep->KeyMaterial, pwep->KeyLength); psecuritypriv->dot11DefKeylen[wep_key_idx] = pwep->KeyLength; @@ -2283,8 +2278,8 @@ static int rtw_set_encryption(struct net_device *dev, struct ieee_param *param, memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, min_t(u16, param->u.crypt.key_len, 16)); /* set mic key */ - memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); - memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); + memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, ¶m->u.crypt.key[16], 8); + memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, ¶m->u.crypt.key[24], 8); psecuritypriv->busetkipkey = true; } else if (strcmp(param->u.crypt.alg, "CCMP") == 0) { @@ -2326,8 +2321,8 @@ static int rtw_set_encryption(struct net_device *dev, struct ieee_param *param, psta->dot118021XPrivacy = _TKIP_; /* set mic key */ - memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8); - memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8); + memcpy(psta->dot11tkiptxmickey.skey, ¶m->u.crypt.key[16], 8); + memcpy(psta->dot11tkiprxmickey.skey, ¶m->u.crypt.key[24], 8); psecuritypriv->busetkipkey = true; } else if (strcmp(param->u.crypt.alg, "CCMP") == 0) { @@ -2357,8 +2352,8 @@ static int rtw_set_encryption(struct net_device *dev, struct ieee_param *param, param->u.crypt.key, min_t(u16, param->u.crypt.key_len, 16)); /* set mic key */ - memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); - memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); + memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, ¶m->u.crypt.key[16], 8); + memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, ¶m->u.crypt.key[24], 8); psecuritypriv->busetkipkey = true; } else if (strcmp(param->u.crypt.alg, "CCMP") == 0) { @@ -2398,7 +2393,7 @@ static int rtw_set_beacon(struct net_device *dev, struct ieee_param *param, int { int ret = 0; struct adapter *padapter = (struct adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct sta_priv *pstapriv = &padapter->stapriv; unsigned char *pbuf = param->u.bcn_ie.buf; @@ -2436,7 +2431,7 @@ static int rtw_add_sta(struct net_device *dev, struct ieee_param *param) int ret = 0; struct sta_info *psta = NULL; struct adapter *padapter = (struct adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct sta_priv *pstapriv = &padapter->stapriv; DBG_88E("rtw_add_sta(aid =%d) =%pM\n", param->u.add_sta.aid, (param->sta_addr)); @@ -2489,7 +2484,7 @@ static int rtw_del_sta(struct net_device *dev, struct ieee_param *param) { struct sta_info *psta = NULL; struct adapter *padapter = (struct adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct sta_priv *pstapriv = &padapter->stapriv; int updated = 0; @@ -2524,7 +2519,7 @@ static int rtw_ioctl_get_sta_data(struct net_device *dev, struct ieee_param *par int ret = 0; struct sta_info *psta = NULL; struct adapter *padapter = (struct adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct sta_priv *pstapriv = &padapter->stapriv; struct ieee_param_ex *param_ex = (struct ieee_param_ex *)param; struct sta_data *psta_data = (struct sta_data *)param_ex->data; @@ -2580,7 +2575,7 @@ static int rtw_get_sta_wpaie(struct net_device *dev, struct ieee_param *param) int ret = 0; struct sta_info *psta = NULL; struct adapter *padapter = (struct adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct sta_priv *pstapriv = &padapter->stapriv; DBG_88E("rtw_get_sta_wpaie, sta_addr: %pM\n", (param->sta_addr)); @@ -2616,8 +2611,8 @@ static int rtw_set_wps_beacon(struct net_device *dev, struct ieee_param *param, { unsigned char wps_oui[4] = {0x0, 0x50, 0xf2, 0x04}; struct adapter *padapter = (struct adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; int ie_len; DBG_88E("%s, len =%d\n", __func__, len); @@ -2651,7 +2646,7 @@ static int rtw_set_wps_beacon(struct net_device *dev, struct ieee_param *param, static int rtw_set_wps_probe_resp(struct net_device *dev, struct ieee_param *param, int len) { struct adapter *padapter = (struct adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; int ie_len; DBG_88E("%s, len =%d\n", __func__, len); @@ -2680,7 +2675,7 @@ static int rtw_set_wps_probe_resp(struct net_device *dev, struct ieee_param *par static int rtw_set_wps_assoc_resp(struct net_device *dev, struct ieee_param *param, int len) { struct adapter *padapter = (struct adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; int ie_len; DBG_88E("%s, len =%d\n", __func__, len); @@ -2710,9 +2705,9 @@ static int rtw_set_wps_assoc_resp(struct net_device *dev, struct ieee_param *par static int rtw_set_hidden_ssid(struct net_device *dev, struct ieee_param *param, int len) { struct adapter *padapter = (struct adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; u8 value; @@ -2734,7 +2729,7 @@ static int rtw_set_hidden_ssid(struct net_device *dev, struct ieee_param *param, static int rtw_ioctl_acl_remove_sta(struct net_device *dev, struct ieee_param *param, int len) { struct adapter *padapter = (struct adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; if (!check_fwstate(pmlmepriv, WIFI_AP_STATE)) return -EINVAL; @@ -2748,7 +2743,7 @@ static int rtw_ioctl_acl_remove_sta(struct net_device *dev, struct ieee_param *p static int rtw_ioctl_acl_add_sta(struct net_device *dev, struct ieee_param *param, int len) { struct adapter *padapter = (struct adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; if (!check_fwstate(pmlmepriv, WIFI_AP_STATE)) return -EINVAL; @@ -2762,7 +2757,7 @@ static int rtw_ioctl_acl_add_sta(struct net_device *dev, struct ieee_param *para static int rtw_ioctl_set_macaddr_acl(struct net_device *dev, struct ieee_param *param, int len) { struct adapter *padapter = (struct adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; if (!check_fwstate(pmlmepriv, WIFI_AP_STATE)) return -EINVAL; @@ -2789,14 +2784,9 @@ static int rtw_hostapd_ioctl(struct net_device *dev, struct iw_point *p) if (!p->pointer || p->length != sizeof(struct ieee_param)) return -EINVAL; - param = (struct ieee_param *)rtw_malloc(p->length); - if (!param) - return -ENOMEM; - - if (copy_from_user(param, p->pointer, p->length)) { - kfree(param); - return -EFAULT; - } + param = memdup_user(p->pointer, p->length); + if (IS_ERR(param)) + return PTR_ERR(param); switch (param->cmd) { case RTL871X_HOSTAPD_FLUSH: @@ -2882,7 +2872,7 @@ static int rtw_wx_set_priv(struct net_device *dev, /* added for wps2.0 @20110524 */ if (dwrq->flags == 0x8766 && len > 8) { u32 cp_sz; - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; u8 *probereq_wpsie = ext; int probereq_wpsie_len = len; u8 wps_oui[4] = {0x0, 0x50, 0xf2, 0x04}; diff --git a/drivers/staging/rtl8188eu/os_dep/rtw_android.c b/drivers/staging/rtl8188eu/os_dep/rtw_android.c index daf6db354982..bf86d03820ca 100644 --- a/drivers/staging/rtl8188eu/os_dep/rtw_android.c +++ b/drivers/staging/rtl8188eu/os_dep/rtw_android.c @@ -77,7 +77,7 @@ static int rtw_android_get_rssi(struct net_device *net, char *command, int total_len) { struct adapter *padapter = (struct adapter *)rtw_netdev_priv(net); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wlan_network *pcur_network = &pmlmepriv->cur_network; int bytes_written = 0; diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_core.c b/drivers/staging/rtl8192e/rtl8192e/rtl_core.c index d3664e508cbe..a7cd4de65b28 100644 --- a/drivers/staging/rtl8192e/rtl8192e/rtl_core.c +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_core.c @@ -81,8 +81,8 @@ static int _rtl92e_hard_start_xmit(struct sk_buff *skb, struct net_device *dev); static void _rtl92e_tx_cmd(struct net_device *dev, struct sk_buff *skb); static short _rtl92e_tx(struct net_device *dev, struct sk_buff *skb); static short _rtl92e_pci_initdescring(struct net_device *dev); -static void _rtl92e_irq_tx_tasklet(struct r8192_priv *priv); -static void _rtl92e_irq_rx_tasklet(struct r8192_priv *priv); +static void _rtl92e_irq_tx_tasklet(unsigned long data); +static void _rtl92e_irq_rx_tasklet(unsigned long data); static void _rtl92e_cancel_deferred_work(struct r8192_priv *priv); static int _rtl92e_up(struct net_device *dev, bool is_silent_reset); static int _rtl92e_try_up(struct net_device *dev); @@ -516,8 +516,9 @@ static int _rtl92e_handle_assoc_response(struct net_device *dev, return 0; } -static void _rtl92e_prepare_beacon(struct r8192_priv *priv) +static void _rtl92e_prepare_beacon(unsigned long data) { + struct r8192_priv *priv = (struct r8192_priv *)data; struct net_device *dev = priv->rtllib->dev; struct sk_buff *pskb = NULL, *pnewskb = NULL; struct cb_desc *tcb_desc = NULL; @@ -1007,14 +1008,11 @@ static void _rtl92e_init_priv_task(struct net_device *dev) (void *)rtl92e_hw_wakeup_wq, dev); INIT_DELAYED_WORK_RSL(&priv->rtllib->hw_sleep_wq, (void *)rtl92e_hw_sleep_wq, dev); - tasklet_init(&priv->irq_rx_tasklet, - (void(*)(unsigned long))_rtl92e_irq_rx_tasklet, + tasklet_init(&priv->irq_rx_tasklet, _rtl92e_irq_rx_tasklet, (unsigned long)priv); - tasklet_init(&priv->irq_tx_tasklet, - (void(*)(unsigned long))_rtl92e_irq_tx_tasklet, + tasklet_init(&priv->irq_tx_tasklet, _rtl92e_irq_tx_tasklet, (unsigned long)priv); - tasklet_init(&priv->irq_prepare_beacon_tasklet, - (void(*)(unsigned long))_rtl92e_prepare_beacon, + tasklet_init(&priv->irq_prepare_beacon_tasklet, _rtl92e_prepare_beacon, (unsigned long)priv); } @@ -2113,13 +2111,17 @@ static void _rtl92e_tx_resume(struct net_device *dev) } } -static void _rtl92e_irq_tx_tasklet(struct r8192_priv *priv) +static void _rtl92e_irq_tx_tasklet(unsigned long data) { + struct r8192_priv *priv = (struct r8192_priv *)data; + _rtl92e_tx_resume(priv->rtllib->dev); } -static void _rtl92e_irq_rx_tasklet(struct r8192_priv *priv) +static void _rtl92e_irq_rx_tasklet(unsigned long data) { + struct r8192_priv *priv = (struct r8192_priv *)data; + _rtl92e_rx_normal(priv->rtllib->dev); rtl92e_writel(priv->rtllib->dev, INTA_MASK, diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_dm.c b/drivers/staging/rtl8192e/rtl8192e/rtl_dm.c index 20e494186c9e..462835684e8b 100644 --- a/drivers/staging/rtl8192e/rtl8192e/rtl_dm.c +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_dm.c @@ -456,7 +456,7 @@ static void _rtl92e_dm_bandwidth_autoswitch(struct net_device *dev) if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 || !priv->rtllib->bandwidth_auto_switch.bautoswitch_enable) return; - if (priv->rtllib->bandwidth_auto_switch.bforced_tx20Mhz == false) { + if (!priv->rtllib->bandwidth_auto_switch.bforced_tx20Mhz) { if (priv->undecorated_smoothed_pwdb <= priv->rtllib->bandwidth_auto_switch.threshold_40Mhzto20Mhz) priv->rtllib->bandwidth_auto_switch.bforced_tx20Mhz = true; @@ -1297,7 +1297,7 @@ static void _rtl92e_dm_dig_init(struct net_device *dev) static void _rtl92e_dm_ctrl_initgain_byrssi(struct net_device *dev) { - if (dm_digtable.dig_enable_flag == false) + if (!dm_digtable.dig_enable_flag) return; if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) @@ -1332,7 +1332,7 @@ static void _rtl92e_dm_ctrl_initgain_byrssi_driver(struct net_device *dev) u8 i; static u8 fw_dig; - if (dm_digtable.dig_enable_flag == false) + if (!dm_digtable.dig_enable_flag) return; if (dm_digtable.dig_algorithm_switch) @@ -1366,7 +1366,7 @@ static void _rtl92e_dm_ctrl_initgain_byrssi_false_alarm(struct net_device *dev) static u32 reset_cnt; u8 i; - if (dm_digtable.dig_enable_flag == false) + if (!dm_digtable.dig_enable_flag) return; if (dm_digtable.dig_algorithm_switch) { @@ -1501,7 +1501,7 @@ static void _rtl92e_dm_initial_gain(struct net_device *dev) reset_cnt = 0; } - if (rtllib_act_scanning(priv->rtllib, true) == true) { + if (rtllib_act_scanning(priv->rtllib, true)) { force_write = 1; return; } @@ -2444,7 +2444,7 @@ static void _rtl92e_dm_init_dynamic_tx_power(struct net_device *dev) static void _rtl92e_dm_dynamic_tx_power(struct net_device *dev) { struct r8192_priv *priv = rtllib_priv(dev); - unsigned int txhipower_threshhold = 0; + unsigned int txhipower_threshold = 0; unsigned int txlowpower_threshold = 0; if (priv->rtllib->bdynamic_txpower_enable != true) { @@ -2454,10 +2454,10 @@ static void _rtl92e_dm_dynamic_tx_power(struct net_device *dev) } if ((priv->rtllib->pHTInfo->IOTPeer == HT_IOT_PEER_ATHEROS) && (priv->rtllib->mode == IEEE_G)) { - txhipower_threshhold = TX_POWER_ATHEROAP_THRESH_HIGH; + txhipower_threshold = TX_POWER_ATHEROAP_THRESH_HIGH; txlowpower_threshold = TX_POWER_ATHEROAP_THRESH_LOW; } else { - txhipower_threshhold = TX_POWER_NEAR_FIELD_THRESH_HIGH; + txhipower_threshold = TX_POWER_NEAR_FIELD_THRESH_HIGH; txlowpower_threshold = TX_POWER_NEAR_FIELD_THRESH_LOW; } @@ -2465,7 +2465,7 @@ static void _rtl92e_dm_dynamic_tx_power(struct net_device *dev) priv->undecorated_smoothed_pwdb); if (priv->rtllib->state == RTLLIB_LINKED) { - if (priv->undecorated_smoothed_pwdb >= txhipower_threshhold) { + if (priv->undecorated_smoothed_pwdb >= txhipower_threshold) { priv->bDynamicTxHighPower = true; priv->bDynamicTxLowPower = false; } else { diff --git a/drivers/staging/rtl8192e/rtl819x_HTProc.c b/drivers/staging/rtl8192e/rtl819x_HTProc.c index d83d72594312..8abc921ecb3e 100644 --- a/drivers/staging/rtl8192e/rtl819x_HTProc.c +++ b/drivers/staging/rtl8192e/rtl819x_HTProc.c @@ -371,7 +371,7 @@ void HTConstructInfoElement(struct rtllib_device *ieee, u8 *posHTInfo, if ((ieee->iw_mode == IW_MODE_ADHOC) || (ieee->iw_mode == IW_MODE_MASTER)) { pHTInfoEle->ControlChl = ieee->current_network.channel; - pHTInfoEle->ExtChlOffset = ((pHT->bRegBW40MHz == false) ? + pHTInfoEle->ExtChlOffset = ((!pHT->bRegBW40MHz) ? HT_EXTCHNL_OFFSET_NO_EXT : (ieee->current_network.channel <= 6) ? HT_EXTCHNL_OFFSET_UPPER : @@ -526,7 +526,7 @@ void HTOnAssocRsp(struct rtllib_device *ieee) static u8 EWC11NHTCap[] = {0x00, 0x90, 0x4c, 0x33}; static u8 EWC11NHTInfo[] = {0x00, 0x90, 0x4c, 0x34}; - if (pHTInfo->bCurrentHTSupport == false) { + if (!pHTInfo->bCurrentHTSupport) { netdev_warn(ieee->dev, "%s(): HT_DISABLE\n", __func__); return; } @@ -873,7 +873,7 @@ void HTSetConnectBwMode(struct rtllib_device *ieee, { struct rt_hi_throughput *pHTInfo = ieee->pHTInfo; - if (pHTInfo->bRegBW40MHz == false) + if (!pHTInfo->bRegBW40MHz) return; if (ieee->GetHalfNmodeSupportByAPsHandler(ieee->dev)) diff --git a/drivers/staging/rtl8192u/ieee80211/ieee80211_rx.c b/drivers/staging/rtl8192u/ieee80211/ieee80211_rx.c index e101f7b13c7e..195d963c4fbb 100644 --- a/drivers/staging/rtl8192u/ieee80211/ieee80211_rx.c +++ b/drivers/staging/rtl8192u/ieee80211/ieee80211_rx.c @@ -520,55 +520,68 @@ static bool AddReorderEntry(struct rx_ts_record *pTS, struct rx_reorder_entry *p return true; } -void ieee80211_indicate_packets(struct ieee80211_device *ieee, struct ieee80211_rxb **prxbIndicateArray, u8 index) +static void indicate_packets(struct ieee80211_device *ieee, + struct ieee80211_rxb *rxb) { - u8 i = 0, j = 0; + struct net_device_stats *stats = &ieee->stats; + struct net_device *dev = ieee->dev; u16 ethertype; -// if(index > 1) -// IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): hahahahhhh, We indicate packet from reorder list, index is %u\n",__func__,index); - for (j = 0; j < index; j++) { -//added by amy for reorder - struct ieee80211_rxb *prxb = prxbIndicateArray[j]; - for (i = 0; i < prxb->nr_subframes; i++) { - struct sk_buff *sub_skb = prxb->subframes[i]; + u8 i; + + for (i = 0; i < rxb->nr_subframes; i++) { + struct sk_buff *sub_skb = rxb->subframes[i]; + + if (!sub_skb) + continue; /* convert hdr + possible LLC headers into Ethernet header */ - ethertype = (sub_skb->data[6] << 8) | sub_skb->data[7]; - if (sub_skb->len >= 8 && - ((memcmp(sub_skb->data, rfc1042_header, SNAP_SIZE) == 0 && - ethertype != ETH_P_AARP && ethertype != ETH_P_IPX) || - memcmp(sub_skb->data, bridge_tunnel_header, SNAP_SIZE) == 0)) { + ethertype = (sub_skb->data[6] << 8) | sub_skb->data[7]; + if (sub_skb->len >= 8 && + ((!memcmp(sub_skb->data, rfc1042_header, SNAP_SIZE) && + ethertype != ETH_P_AARP && + ethertype != ETH_P_IPX) || + !memcmp(sub_skb->data, bridge_tunnel_header, SNAP_SIZE))) { /* remove RFC1042 or Bridge-Tunnel encapsulation and * replace EtherType */ - skb_pull(sub_skb, SNAP_SIZE); - memcpy(skb_push(sub_skb, ETH_ALEN), prxb->src, ETH_ALEN); - memcpy(skb_push(sub_skb, ETH_ALEN), prxb->dst, ETH_ALEN); - } else { + skb_pull(sub_skb, SNAP_SIZE); + } else { /* Leave Ethernet header part of hdr and full payload */ - put_unaligned_be16(sub_skb->len, skb_push(sub_skb, 2)); - memcpy(skb_push(sub_skb, ETH_ALEN), prxb->src, ETH_ALEN); - memcpy(skb_push(sub_skb, ETH_ALEN), prxb->dst, ETH_ALEN); - } - //stats->rx_packets++; - //stats->rx_bytes += sub_skb->len; + put_unaligned_be16(sub_skb->len, skb_push(sub_skb, 2)); + } + memcpy(skb_push(sub_skb, ETH_ALEN), rxb->src, ETH_ALEN); + memcpy(skb_push(sub_skb, ETH_ALEN), rxb->dst, ETH_ALEN); + + stats->rx_packets++; + stats->rx_bytes += sub_skb->len; + if (is_multicast_ether_addr(rxb->dst)) + stats->multicast++; /* Indicate the packets to upper layer */ - if (sub_skb) { - sub_skb->protocol = eth_type_trans(sub_skb, ieee->dev); - memset(sub_skb->cb, 0, sizeof(sub_skb->cb)); - sub_skb->dev = ieee->dev; - sub_skb->ip_summed = CHECKSUM_NONE; /* 802.11 crc not sufficient */ - //skb->ip_summed = CHECKSUM_UNNECESSARY; /* 802.11 crc not sufficient */ - ieee->last_rx_ps_time = jiffies; - netif_rx(sub_skb); - } - } + sub_skb->protocol = eth_type_trans(sub_skb, dev); + memset(sub_skb->cb, 0, sizeof(sub_skb->cb)); + sub_skb->dev = dev; + /* 802.11 crc not sufficient */ + sub_skb->ip_summed = CHECKSUM_NONE; + ieee->last_rx_ps_time = jiffies; + netif_rx(sub_skb); + } +} + +void ieee80211_indicate_packets(struct ieee80211_device *ieee, + struct ieee80211_rxb **prxbIndicateArray, + u8 index) +{ + u8 i; + + for (i = 0; i < index; i++) { + struct ieee80211_rxb *prxb = prxbIndicateArray[i]; + + indicate_packets(ieee, prxb); kfree(prxb); prxb = NULL; } } - static void RxReorderIndicatePacket(struct ieee80211_device *ieee, struct ieee80211_rxb *prxb, struct rx_ts_record *pTS, u16 SeqNum) @@ -877,7 +890,6 @@ int ieee80211_rx(struct ieee80211_device *ieee, struct sk_buff *skb, u16 fc, type, stype, sc; struct net_device_stats *stats; unsigned int frag; - u16 ethertype; //added by amy for reorder u8 TID = 0; u16 SeqNum = 0; @@ -1260,47 +1272,7 @@ int ieee80211_rx(struct ieee80211_device *ieee, struct sk_buff *skb, //added by amy for reorder if (!ieee->pHTInfo->bCurRxReorderEnable || !pTS) { -//added by amy for reorder - for (i = 0; i < rxb->nr_subframes; i++) { - struct sk_buff *sub_skb = rxb->subframes[i]; - - if (sub_skb) { - /* convert hdr + possible LLC headers into Ethernet header */ - ethertype = (sub_skb->data[6] << 8) | sub_skb->data[7]; - if (sub_skb->len >= 8 && - ((memcmp(sub_skb->data, rfc1042_header, SNAP_SIZE) == 0 && - ethertype != ETH_P_AARP && ethertype != ETH_P_IPX) || - memcmp(sub_skb->data, bridge_tunnel_header, SNAP_SIZE) == 0)) { - /* remove RFC1042 or Bridge-Tunnel encapsulation and - * replace EtherType */ - skb_pull(sub_skb, SNAP_SIZE); - memcpy(skb_push(sub_skb, ETH_ALEN), src, ETH_ALEN); - memcpy(skb_push(sub_skb, ETH_ALEN), dst, ETH_ALEN); - } else { - u16 len; - /* Leave Ethernet header part of hdr and full payload */ - len = be16_to_cpu(htons(sub_skb->len)); - memcpy(skb_push(sub_skb, 2), &len, 2); - memcpy(skb_push(sub_skb, ETH_ALEN), src, ETH_ALEN); - memcpy(skb_push(sub_skb, ETH_ALEN), dst, ETH_ALEN); - } - - stats->rx_packets++; - stats->rx_bytes += sub_skb->len; - if (is_multicast_ether_addr(dst)) { - stats->multicast++; - } - - /* Indicate the packets to upper layer */ - sub_skb->protocol = eth_type_trans(sub_skb, dev); - memset(sub_skb->cb, 0, sizeof(sub_skb->cb)); - sub_skb->dev = dev; - sub_skb->ip_summed = CHECKSUM_NONE; /* 802.11 crc not sufficient */ - //skb->ip_summed = CHECKSUM_UNNECESSARY; /* 802.11 crc not sufficient */ - ieee->last_rx_ps_time = jiffies; - netif_rx(sub_skb); - } - } + indicate_packets(ieee, rxb); kfree(rxb); rxb = NULL; diff --git a/drivers/staging/rtl8192u/ieee80211/ieee80211_tx.c b/drivers/staging/rtl8192u/ieee80211/ieee80211_tx.c index 0ee054d82832..63a561ab4a76 100644 --- a/drivers/staging/rtl8192u/ieee80211/ieee80211_tx.c +++ b/drivers/staging/rtl8192u/ieee80211/ieee80211_tx.c @@ -372,9 +372,9 @@ ieee80211_query_HTCapShortGI(struct ieee80211_device *ieee, struct cb_desc *tcb_ return; } - if ((pHTInfo->bCurBW40MHz == true) && pHTInfo->bCurShortGI40MHz) + if (pHTInfo->bCurBW40MHz && pHTInfo->bCurShortGI40MHz) tcb_desc->bUseShortGI = true; - else if ((pHTInfo->bCurBW40MHz == false) && pHTInfo->bCurShortGI20MHz) + else if (!pHTInfo->bCurBW40MHz && pHTInfo->bCurShortGI20MHz) tcb_desc->bUseShortGI = true; } diff --git a/drivers/staging/rtl8712/rtl871x_xmit.c b/drivers/staging/rtl8712/rtl871x_xmit.c index f0b85338b567..2f0d0ffa6fae 100644 --- a/drivers/staging/rtl8712/rtl871x_xmit.c +++ b/drivers/staging/rtl8712/rtl871x_xmit.c @@ -71,12 +71,13 @@ int _r8712_init_xmit_priv(struct xmit_priv *pxmitpriv, _init_queue(&pxmitpriv->apsd_queue); _init_queue(&pxmitpriv->free_xmit_queue); /* - * Please allocate memory with the sz = (struct xmit_frame) * NR_XMITFRAME, + * Please allocate memory with sz = (struct xmit_frame) * NR_XMITFRAME, * and initialize free_xmit_frame below. * Please also apply free_txobj to link_up all the xmit_frames... */ pxmitpriv->pallocated_frame_buf = - kmalloc(NR_XMITFRAME * sizeof(struct xmit_frame) + 4, GFP_ATOMIC); + kmalloc(NR_XMITFRAME * sizeof(struct xmit_frame) + 4, + GFP_ATOMIC); if (!pxmitpriv->pallocated_frame_buf) { pxmitpriv->pxmit_frame_buf = NULL; return -ENOMEM; @@ -126,8 +127,8 @@ int _r8712_init_xmit_priv(struct xmit_priv *pxmitpriv, pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf; for (i = 0; i < NR_XMITBUFF; i++) { INIT_LIST_HEAD(&pxmitbuf->list); - pxmitbuf->pallocated_buf = kmalloc(MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ, - GFP_ATOMIC); + pxmitbuf->pallocated_buf = + kmalloc(MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ, GFP_ATOMIC); if (!pxmitbuf->pallocated_buf) return -ENOMEM; pxmitbuf->pbuf = pxmitbuf->pallocated_buf + XMITBUF_ALIGN_SZ - @@ -350,7 +351,7 @@ static int xmitframe_addmic(struct _adapter *padapter, struct sta_info *stainfo; struct qos_priv *pqospriv = &(padapter->mlmepriv.qospriv); struct pkt_attrib *pattrib = &pxmitframe->attrib; - struct security_priv *psecuritypriv = &padapter->securitypriv; + struct security_priv *psecpriv = &padapter->securitypriv; struct xmit_priv *pxmitpriv = &padapter->xmitpriv; u8 priority[4] = {0x0, 0x0, 0x0, 0x0}; bool bmcst = is_multicast_ether_addr(pattrib->ra); @@ -368,15 +369,14 @@ static int xmitframe_addmic(struct _adapter *padapter, 0x0, 0x0}; pframe = pxmitframe->buf_addr + TXDESC_OFFSET; if (bmcst) { - if (!memcmp(psecuritypriv->XGrptxmickey - [psecuritypriv->XGrpKeyid].skey, + if (!memcmp(psecpriv->XGrptxmickey + [psecpriv->XGrpKeyid].skey, null_key, 16)) return -ENOMEM; /*start to calculate the mic code*/ r8712_secmicsetkey(&micdata, - psecuritypriv-> - XGrptxmickey[psecuritypriv-> - XGrpKeyid].skey); + psecpriv->XGrptxmickey + [psecpriv->XGrpKeyid].skey); } else { if (!memcmp(&stainfo->tkiptxmickey.skey[0], null_key, 16)) @@ -416,7 +416,7 @@ static int xmitframe_addmic(struct _adapter *padapter, length = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - - ((psecuritypriv->sw_encrypt) + ((psecpriv->sw_encrypt) ? pattrib->icv_len : 0); r8712_secmicappend(&micdata, payload, length); @@ -424,7 +424,7 @@ static int xmitframe_addmic(struct _adapter *padapter, } else { length = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - - ((psecuritypriv->sw_encrypt) ? + ((psecpriv->sw_encrypt) ? pattrib->icv_len : 0); r8712_secmicappend(&micdata, payload, length); @@ -477,75 +477,72 @@ static int make_wlanhdr(struct _adapter *padapter, u8 *hdr, struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct qos_priv *pqospriv = &pmlmepriv->qospriv; __le16 *fctrl = &pwlanhdr->frame_ctl; + u8 *bssid; memset(hdr, 0, WLANHDR_OFFSET); SetFrameSubType(fctrl, pattrib->subtype); - if (pattrib->subtype & WIFI_DATA_TYPE) { - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { - /* to_ds = 1, fr_ds = 0; */ - SetToDs(fctrl); - memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), - ETH_ALEN); - memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); - memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN); - } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { - /* to_ds = 0, fr_ds = 1; */ - SetFrDs(fctrl); - memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); - memcpy(pwlanhdr->addr2, get_bssid(pmlmepriv), - ETH_ALEN); - memcpy(pwlanhdr->addr3, pattrib->src, ETH_ALEN); - } else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || - check_fwstate(pmlmepriv, - WIFI_ADHOC_MASTER_STATE)) { - memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); - memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); - memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), - ETH_ALEN); - } else if (check_fwstate(pmlmepriv, WIFI_MP_STATE)) { - memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); - memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); - memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), - ETH_ALEN); - } else { - return -EINVAL; - } + if (!(pattrib->subtype & WIFI_DATA_TYPE)) + return 0; - if (pattrib->encrypt) - SetPrivacy(fctrl); - if (pqospriv->qos_option) { - qc = (unsigned short *)(hdr + pattrib->hdrlen - 2); - if (pattrib->priority) - SetPriority(qc, pattrib->priority); - SetAckpolicy(qc, pattrib->ack_policy); - } - /* TODO: fill HT Control Field */ - /* Update Seq Num will be handled by f/w */ - { - struct sta_info *psta; - bool bmcst = is_multicast_ether_addr(pattrib->ra); + bssid = get_bssid(pmlmepriv); - if (pattrib->psta) { - psta = pattrib->psta; - } else { - if (bmcst) - psta = r8712_get_bcmc_stainfo(padapter); - else - psta = - r8712_get_stainfo(&padapter->stapriv, - pattrib->ra); - } - if (psta) { - psta->sta_xmitpriv.txseq_tid - [pattrib->priority]++; - psta->sta_xmitpriv.txseq_tid[pattrib->priority] - &= 0xFFF; - pattrib->seqnum = psta->sta_xmitpriv. - txseq_tid[pattrib->priority]; - SetSeqNum(hdr, pattrib->seqnum); - } + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { + /* to_ds = 1, fr_ds = 0; */ + SetToDs(fctrl); + ether_addr_copy(pwlanhdr->addr1, bssid); + ether_addr_copy(pwlanhdr->addr2, pattrib->src); + ether_addr_copy(pwlanhdr->addr3, pattrib->dst); + } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { + /* to_ds = 0, fr_ds = 1; */ + SetFrDs(fctrl); + ether_addr_copy(pwlanhdr->addr1, pattrib->dst); + ether_addr_copy(pwlanhdr->addr2, bssid); + ether_addr_copy(pwlanhdr->addr3, pattrib->src); + } else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || + check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) { + ether_addr_copy(pwlanhdr->addr1, pattrib->dst); + ether_addr_copy(pwlanhdr->addr2, pattrib->src); + ether_addr_copy(pwlanhdr->addr3, bssid); + } else if (check_fwstate(pmlmepriv, WIFI_MP_STATE)) { + ether_addr_copy(pwlanhdr->addr1, pattrib->dst); + ether_addr_copy(pwlanhdr->addr2, pattrib->src); + ether_addr_copy(pwlanhdr->addr3, bssid); + } else { + return -EINVAL; + } + + if (pattrib->encrypt) + SetPrivacy(fctrl); + if (pqospriv->qos_option) { + qc = (unsigned short *)(hdr + pattrib->hdrlen - 2); + if (pattrib->priority) + SetPriority(qc, pattrib->priority); + SetAckpolicy(qc, pattrib->ack_policy); + } + /* TODO: fill HT Control Field */ + /* Update Seq Num will be handled by f/w */ + { + struct sta_info *psta; + bool bmcst = is_multicast_ether_addr(pattrib->ra); + + if (pattrib->psta) + psta = pattrib->psta; + else if (bmcst) + psta = r8712_get_bcmc_stainfo(padapter); + else + psta = r8712_get_stainfo(&padapter->stapriv, + pattrib->ra); + + if (psta) { + u16 *txtid = psta->sta_xmitpriv.txseq_tid; + + txtid[pattrib->priority]++; + txtid[pattrib->priority] &= 0xFFF; + pattrib->seqnum = txtid[pattrib->priority]; + SetSeqNum(hdr, pattrib->seqnum); } } + return 0; } @@ -589,7 +586,7 @@ sint r8712_xmitframe_coalesce(struct _adapter *padapter, _pkt *pkt, addr_t addr; u8 *pframe, *mem_start, *ptxdesc; struct sta_info *psta; - struct security_priv *psecuritypriv = &padapter->securitypriv; + struct security_priv *psecpriv = &padapter->securitypriv; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct xmit_priv *pxmitpriv = &padapter->xmitpriv; struct pkt_attrib *pattrib = &pxmitframe->attrib; @@ -632,15 +629,13 @@ sint r8712_xmitframe_coalesce(struct _adapter *padapter, _pkt *pkt, case _WEP40_: case _WEP104_: WEP_IV(pattrib->iv, psta->txpn, - (u8)psecuritypriv-> - PrivacyKeyIndex); + (u8)psecpriv->PrivacyKeyIndex); break; case _TKIP_: if (bmcst) TKIP_IV(pattrib->iv, psta->txpn, - (u8)psecuritypriv-> - XGrpKeyid); + (u8)psecpriv->XGrpKeyid); else TKIP_IV(pattrib->iv, psta->txpn, 0); @@ -648,8 +643,7 @@ sint r8712_xmitframe_coalesce(struct _adapter *padapter, _pkt *pkt, case _AES_: if (bmcst) AES_IV(pattrib->iv, psta->txpn, - (u8)psecuritypriv-> - XGrpKeyid); + (u8)psecpriv->XGrpKeyid); else AES_IV(pattrib->iv, psta->txpn, 0); diff --git a/drivers/staging/rtl8712/rtl871x_xmit.h b/drivers/staging/rtl8712/rtl871x_xmit.h index f227828094bf..c0c0c781fe17 100644 --- a/drivers/staging/rtl8712/rtl871x_xmit.h +++ b/drivers/staging/rtl8712/rtl871x_xmit.h @@ -115,7 +115,7 @@ struct pkt_attrib { u8 icv_len; unsigned char iv[8]; unsigned char icv[8]; - u8 dst[ETH_ALEN]; + u8 dst[ETH_ALEN] __aligned(2); /* for ether_addr_copy */ u8 src[ETH_ALEN]; u8 ta[ETH_ALEN]; u8 ra[ETH_ALEN]; diff --git a/drivers/staging/rtl8712/usb_halinit.c b/drivers/staging/rtl8712/usb_halinit.c index 6cc4a704c3a0..313c569748e9 100644 --- a/drivers/staging/rtl8712/usb_halinit.c +++ b/drivers/staging/rtl8712/usb_halinit.c @@ -58,7 +58,7 @@ u8 r8712_usb_hal_bus_init(struct _adapter *adapter) r8712_write8(adapter, SYS_ISO_CTRL + 1, val8); val8 = r8712_read8(adapter, SYS_ISO_CTRL + 1); val8 = val8 & 0xEF; - /* attatch AFE PLL to MACTOP/BB/PCIe Digital */ + /* attach AFE PLL to MACTOP/BB/PCIe Digital */ r8712_write8(adapter, SYS_ISO_CTRL + 1, val8); val8 = r8712_read8(adapter, AFE_XTAL_CTRL + 1); val8 = val8 & 0xFB; diff --git a/drivers/staging/rtl8712/wifi.h b/drivers/staging/rtl8712/wifi.h index be731f1a2209..91b65731fcaa 100644 --- a/drivers/staging/rtl8712/wifi.h +++ b/drivers/staging/rtl8712/wifi.h @@ -440,7 +440,7 @@ static inline unsigned char *get_hdr_bssid(unsigned char *pframe) /* block-ack parameters */ #define IEEE80211_ADDBA_PARAM_POLICY_MASK 0x0002 #define IEEE80211_ADDBA_PARAM_TID_MASK 0x003C -#define IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK 0xFFA0 +#define IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK 0xFFC0 #define IEEE80211_DELBA_PARAM_TID_MASK 0xF000 #define IEEE80211_DELBA_PARAM_INITIATOR_MASK 0x0800 @@ -532,13 +532,6 @@ struct ieee80211_ht_addt_info { #define IEEE80211_HT_IE_NON_GF_STA_PRSNT 0x0004 #define IEEE80211_HT_IE_NON_HT_STA_PRSNT 0x0010 -/* block-ack parameters */ -#define IEEE80211_ADDBA_PARAM_POLICY_MASK 0x0002 -#define IEEE80211_ADDBA_PARAM_TID_MASK 0x003C -#define IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK 0xFFA0 -#define IEEE80211_DELBA_PARAM_TID_MASK 0xF000 -#define IEEE80211_DELBA_PARAM_INITIATOR_MASK 0x0800 - /* * A-PMDU buffer sizes * According to IEEE802.11n spec size varies from 8K to 64K (in powers of 2) diff --git a/drivers/staging/rtl8723bs/core/rtw_cmd.c b/drivers/staging/rtl8723bs/core/rtw_cmd.c index efb5135ad743..bd18d1803e27 100644 --- a/drivers/staging/rtl8723bs/core/rtw_cmd.c +++ b/drivers/staging/rtl8723bs/core/rtw_cmd.c @@ -822,7 +822,7 @@ u8 rtw_joinbss_cmd(struct adapter *padapter, struct wlan_network *pnetwork) psecnetwork->IELength = 0; /* Added by Albert 2009/02/18 */ - /* If the the driver wants to use the bssid to create the connection. */ + /* If the driver wants to use the bssid to create the connection. */ /* If not, we have to copy the connecting AP's MAC address to it so that */ /* the driver just has the bssid information for PMKIDList searching. */ diff --git a/drivers/staging/rtl8723bs/core/rtw_mlme.c b/drivers/staging/rtl8723bs/core/rtw_mlme.c index d7a58af76ea0..e65c5a870b46 100644 --- a/drivers/staging/rtl8723bs/core/rtw_mlme.c +++ b/drivers/staging/rtl8723bs/core/rtw_mlme.c @@ -1097,9 +1097,6 @@ inline void rtw_indicate_scan_done(struct adapter *padapter, bool aborted) (!adapter_to_pwrctl(padapter)->bInSuspend) && (!check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE|WIFI_UNDER_LINKING))) { - struct pwrctrl_priv *pwrpriv; - - pwrpriv = adapter_to_pwrctl(padapter); rtw_set_ips_deny(padapter, 0); _set_timer(&padapter->mlmepriv.dynamic_chk_timer, 1); } @@ -2917,12 +2914,11 @@ void rtw_append_exented_cap(struct adapter *padapter, u8 *out_ie, uint *pout_len struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct ht_priv *phtpriv = &pmlmepriv->htpriv; u8 cap_content[8] = {0}; - u8 *pframe; if (phtpriv->bss_coexist) SET_EXT_CAPABILITY_ELE_BSS_COEXIST(cap_content, 1); - pframe = rtw_set_ie(out_ie + *pout_len, EID_EXTCapability, 8, cap_content, pout_len); + rtw_set_ie(out_ie + *pout_len, EID_EXTCapability, 8, cap_content, pout_len); } inline void rtw_set_to_roam(struct adapter *adapter, u8 to_roam) diff --git a/drivers/staging/rtl8723bs/core/rtw_mlme_ext.c b/drivers/staging/rtl8723bs/core/rtw_mlme_ext.c index 8f9da1d49343..d6d7198dfe45 100644 --- a/drivers/staging/rtl8723bs/core/rtw_mlme_ext.c +++ b/drivers/staging/rtl8723bs/core/rtw_mlme_ext.c @@ -1084,7 +1084,7 @@ auth_fail: unsigned int OnAuthClient(struct adapter *padapter, union recv_frame *precv_frame) { - unsigned int seq, len, status, algthm, offset; + unsigned int seq, len, status, offset; unsigned char *p; unsigned int go2asoc = 0; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; @@ -1103,7 +1103,6 @@ unsigned int OnAuthClient(struct adapter *padapter, union recv_frame *precv_fram offset = (GetPrivacy(pframe)) ? 4 : 0; - algthm = le16_to_cpu(*(__le16 *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset)); seq = le16_to_cpu(*(__le16 *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset + 2)); status = le16_to_cpu(*(__le16 *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset + 4)); @@ -1170,7 +1169,7 @@ authclnt_fail: unsigned int OnAssocReq(struct adapter *padapter, union recv_frame *precv_frame) { - u16 capab_info, listen_interval; + u16 capab_info; struct rtw_ieee802_11_elems elems; struct sta_info *pstat; unsigned char reassoc, *p, *pos, *wpa_ie; @@ -1216,8 +1215,6 @@ unsigned int OnAssocReq(struct adapter *padapter, union recv_frame *precv_frame) capab_info = RTW_GET_LE16(pframe + WLAN_HDR_A3_LEN); /* capab_info = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN)); */ - /* listen_interval = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN+2)); */ - listen_interval = RTW_GET_LE16(pframe + WLAN_HDR_A3_LEN+2); left = pkt_len - (sizeof(struct ieee80211_hdr_3addr) + ie_offset); pos = pframe + (sizeof(struct ieee80211_hdr_3addr) + ie_offset); diff --git a/drivers/staging/rtl8723bs/core/rtw_recv.c b/drivers/staging/rtl8723bs/core/rtw_recv.c index 5245098b9ecf..7e1da0e35812 100644 --- a/drivers/staging/rtl8723bs/core/rtw_recv.c +++ b/drivers/staging/rtl8723bs/core/rtw_recv.c @@ -10,14 +10,11 @@ #include #include #include +#include static u8 SNAP_ETH_TYPE_IPX[2] = {0x81, 0x37}; static u8 SNAP_ETH_TYPE_APPLETALK_AARP[2] = {0x80, 0xf3}; -u8 rtw_rfc1042_header[] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00 }; -/* Bridge-Tunnel header (for EtherTypes ETH_P_AARP and ETH_P_IPX) */ -u8 rtw_bridge_tunnel_header[] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0xf8 }; - static void rtw_signal_stat_timer_hdl(struct timer_list *t); void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv) @@ -1625,11 +1622,11 @@ sint wlanhdr_to_ethhdr(union recv_frame *precvframe) psnap_type = ptr+pattrib->hdrlen + pattrib->iv_len+SNAP_SIZE; /* convert hdr + possible LLC headers into Ethernet header */ /* eth_type = (psnap_type[0] << 8) | psnap_type[1]; */ - if ((!memcmp(psnap, rtw_rfc1042_header, SNAP_SIZE) && + if ((!memcmp(psnap, rfc1042_header, SNAP_SIZE) && (memcmp(psnap_type, SNAP_ETH_TYPE_IPX, 2)) && (memcmp(psnap_type, SNAP_ETH_TYPE_APPLETALK_AARP, 2))) || /* eth_type != ETH_P_AARP && eth_type != ETH_P_IPX) || */ - !memcmp(psnap, rtw_bridge_tunnel_header, SNAP_SIZE)) { + !memcmp(psnap, bridge_tunnel_header, SNAP_SIZE)) { /* remove RFC1042 or Bridge-Tunnel encapsulation and replace EtherType */ bsnaphdr = true; } else diff --git a/drivers/staging/rtl8723bs/core/rtw_security.c b/drivers/staging/rtl8723bs/core/rtw_security.c index 5ebf691bd743..0f95009a30b6 100644 --- a/drivers/staging/rtl8723bs/core/rtw_security.c +++ b/drivers/staging/rtl8723bs/core/rtw_security.c @@ -756,7 +756,7 @@ u32 rtw_tkip_decrypt(struct adapter *padapter, u8 *precvframe) static u32 no_gkey_bc_cnt; static u32 no_gkey_mc_cnt; - if (psecuritypriv->binstallGrpkey == false) { + if (!psecuritypriv->binstallGrpkey) { res = _FAIL; if (start == 0) @@ -1837,7 +1837,7 @@ u32 rtw_aes_decrypt(struct adapter *padapter, u8 *precvframe) static u32 no_gkey_bc_cnt; static u32 no_gkey_mc_cnt; - if (psecuritypriv->binstallGrpkey == false) { + if (!psecuritypriv->binstallGrpkey) { res = _FAIL; if (start == 0) @@ -2369,7 +2369,7 @@ u8 rtw_handle_tkip_countermeasure(struct adapter *adapter, const char *caller) struct security_priv *securitypriv = &(adapter->securitypriv); u8 status = _SUCCESS; - if (securitypriv->btkip_countermeasure == true) { + if (securitypriv->btkip_countermeasure) { unsigned long passing_ms = jiffies_to_msecs(jiffies - securitypriv->btkip_countermeasure_time); if (passing_ms > 60*1000) { DBG_871X_LEVEL(_drv_always_, "%s("ADPT_FMT") countermeasure time:%lus > 60s\n", diff --git a/drivers/staging/rtl8723bs/core/rtw_sta_mgt.c b/drivers/staging/rtl8723bs/core/rtw_sta_mgt.c index 09d2ca30d653..e3f56c6cc882 100644 --- a/drivers/staging/rtl8723bs/core/rtw_sta_mgt.c +++ b/drivers/staging/rtl8723bs/core/rtw_sta_mgt.c @@ -553,7 +553,6 @@ u32 rtw_init_bcmc_stainfo(struct adapter *padapter) { struct sta_info *psta; - struct tx_servq *ptxservq; u32 res = _SUCCESS; NDIS_802_11_MAC_ADDRESS bcast_addr = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; @@ -571,7 +570,6 @@ u32 rtw_init_bcmc_stainfo(struct adapter *padapter) /* default broadcast & multicast use macid 1 */ psta->mac_id = 1; - ptxservq = &(psta->sta_xmitpriv.be_q); exit: return _SUCCESS; } diff --git a/drivers/staging/rtl8723bs/core/rtw_wlan_util.c b/drivers/staging/rtl8723bs/core/rtw_wlan_util.c index 110338dbe372..69bcd172b298 100644 --- a/drivers/staging/rtl8723bs/core/rtw_wlan_util.c +++ b/drivers/staging/rtl8723bs/core/rtw_wlan_util.c @@ -1271,13 +1271,13 @@ int rtw_check_bcn_info(struct adapter *Adapter, u8 *pframe, u32 packet_len) unsigned char *pbuf; u32 wpa_ielen = 0; u8 *pbssid = GetAddr3Ptr(pframe); - u32 hidden_ssid = 0; struct HT_info_element *pht_info = NULL; struct rtw_ieee80211_ht_cap *pht_cap = NULL; u32 bcn_channel; unsigned short ht_cap_info; unsigned char ht_info_infos_0; struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; + int ssid_len; if (is_client_associated_to_ap(Adapter) == false) return true; @@ -1370,21 +1370,15 @@ int rtw_check_bcn_info(struct adapter *Adapter, u8 *pframe, u32 packet_len) } /* checking SSID */ + ssid_len = 0; p = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _SSID_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_); - if (!p) { - DBG_871X("%s marc: cannot find SSID for survey event\n", __func__); - hidden_ssid = true; - } else { - hidden_ssid = false; - } - - if ((NULL != p) && (false == hidden_ssid && (*(p + 1)))) { - memcpy(bssid->Ssid.Ssid, (p + 2), *(p + 1)); - bssid->Ssid.SsidLength = *(p + 1); - } else { - bssid->Ssid.SsidLength = 0; - bssid->Ssid.Ssid[0] = '\0'; + if (p) { + ssid_len = *(p + 1); + if (ssid_len > NDIS_802_11_LENGTH_SSID) + ssid_len = 0; } + memcpy(bssid->Ssid.Ssid, (p + 2), ssid_len); + bssid->Ssid.SsidLength = ssid_len; RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("%s bssid.Ssid.Ssid:%s bssid.Ssid.SsidLength:%d " "cur_network->network.Ssid.Ssid:%s len:%d\n", __func__, bssid->Ssid.Ssid, diff --git a/drivers/staging/rtl8723bs/hal/hal_btcoex.c b/drivers/staging/rtl8723bs/hal/hal_btcoex.c index d5793e4614bf..3705a60a0546 100644 --- a/drivers/staging/rtl8723bs/hal/hal_btcoex.c +++ b/drivers/staging/rtl8723bs/hal/hal_btcoex.c @@ -12,49 +12,6 @@ #include /* Global variables */ -static const char *const BtProfileString[] = { - "NONE", - "A2DP", - "PAN", - "HID", - "SCO", -}; - -static const char *const BtSpecString[] = { - "1.0b", - "1.1", - "1.2", - "2.0+EDR", - "2.1+EDR", - "3.0+HS", - "4.0", -}; - -static const char *const BtLinkRoleString[] = { - "Master", - "Slave", -}; - -static const char *const h2cStaString[] = { - "successful", - "h2c busy", - "rf off", - "fw not read", -}; - -static const char *const ioStaString[] = { - "success", - "can not IO", - "rf off", - "fw not read", - "wait io timeout", - "invalid len", - "idle Q empty", - "insert waitQ fail", - "unknown fail", - "wrong level", - "h2c stopped", -}; BTC_COEXIST GLBtCoexist; static u8 GLBtcWiFiInScanState; @@ -450,7 +407,7 @@ static u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf) break; case BTC_GET_BL_WIFI_ENABLE_ENCRYPTION: - *pu8 = padapter->securitypriv.dot11PrivacyAlgrthm == 0 ? false : true; + *pu8 = padapter->securitypriv.dot11PrivacyAlgrthm != 0; break; case BTC_GET_BL_WIFI_UNDER_B_MODE: diff --git a/drivers/staging/rtl8723bs/hal/hal_com_phycfg.c b/drivers/staging/rtl8723bs/hal/hal_com_phycfg.c index 767e2a784f78..10250642d30a 100644 --- a/drivers/staging/rtl8723bs/hal/hal_com_phycfg.c +++ b/drivers/staging/rtl8723bs/hal/hal_com_phycfg.c @@ -1816,7 +1816,7 @@ static void phy_CrossReferenceHTAndVHTTxPowerLimit(struct adapter *padapter) s8 tempPwrLmt = 0; for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) { - for (bw = 0; bw < MAX_5G_BANDWITH_NUM; ++bw) { + for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) { for (channel = 0; channel < CHANNEL_MAX_NUMBER_5G; ++channel) { for (rateSection = 0; rateSection < MAX_RATE_SECTION_NUM; ++rateSection) { tempPwrLmt = pHalData->TxPwrLimit_5G[regulation][bw][rateSection][channel][ODM_RF_PATH_A]; @@ -1877,7 +1877,7 @@ void PHY_ConvertTxPowerLimitToPowerIndex(struct adapter *Adapter) phy_CrossReferenceHTAndVHTTxPowerLimit(Adapter); for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) { - for (bw = 0; bw < MAX_2_4G_BANDWITH_NUM; ++bw) { + for (bw = 0; bw < MAX_2_4G_BANDWIDTH_NUM; ++bw) { for (channel = 0; channel < CHANNEL_MAX_NUMBER_2G; ++channel) { for (rateSection = 0; rateSection < MAX_RATE_SECTION_NUM; ++rateSection) { tempPwrLmt = pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][ODM_RF_PATH_A]; @@ -1920,7 +1920,7 @@ void PHY_InitTxPowerLimit(struct adapter *Adapter) /* DBG_871X("=====> PHY_InitTxPowerLimit()!\n"); */ for (i = 0; i < MAX_REGULATION_NUM; ++i) { - for (j = 0; j < MAX_2_4G_BANDWITH_NUM; ++j) + for (j = 0; j < MAX_2_4G_BANDWIDTH_NUM; ++j) for (k = 0; k < MAX_RATE_SECTION_NUM; ++k) for (m = 0; m < CHANNEL_MAX_NUMBER_2G; ++m) for (l = 0; l < MAX_RF_PATH_NUM; ++l) @@ -1928,7 +1928,7 @@ void PHY_InitTxPowerLimit(struct adapter *Adapter) } for (i = 0; i < MAX_REGULATION_NUM; ++i) { - for (j = 0; j < MAX_5G_BANDWITH_NUM; ++j) + for (j = 0; j < MAX_5G_BANDWIDTH_NUM; ++j) for (k = 0; k < MAX_RATE_SECTION_NUM; ++k) for (m = 0; m < CHANNEL_MAX_NUMBER_5G; ++m) for (l = 0; l < MAX_RF_PATH_NUM; ++l) diff --git a/drivers/staging/rtl8723bs/hal/odm.c b/drivers/staging/rtl8723bs/hal/odm.c index aa6631ee4ea7..f2a9e95a1563 100644 --- a/drivers/staging/rtl8723bs/hal/odm.c +++ b/drivers/staging/rtl8723bs/hal/odm.c @@ -7,19 +7,6 @@ #include "odm_precomp.h" -static const u16 dB_Invert_Table[8][12] = { - {1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4}, - {4, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16}, - {18, 20, 22, 25, 28, 32, 35, 40, 45, 50, 56, 63}, - {71, 79, 89, 100, 112, 126, 141, 158, 178, 200, 224, 251}, - {282, 316, 355, 398, 447, 501, 562, 631, 708, 794, 891, 1000}, - {1122, 1259, 1413, 1585, 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981}, - {4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000, 11220, 12589, 14125, - 15849}, - {17783, 19953, 22387, 25119, 28184, 31623, 35481, 39811, 44668, 50119, - 56234, 65535} - }; - /* Global var */ u32 OFDMSwingTable[OFDM_TABLE_SIZE] = { diff --git a/drivers/staging/rtl8723bs/hal/odm.h b/drivers/staging/rtl8723bs/hal/odm.h index b77d1fe33a28..16e8f66a3171 100644 --- a/drivers/staging/rtl8723bs/hal/odm.h +++ b/drivers/staging/rtl8723bs/hal/odm.h @@ -541,7 +541,7 @@ typedef enum tag_Operation_Mode_Definition { /* ODM_CMNINFO_WM_MODE */ typedef enum tag_Wireless_Mode_Definition { - ODM_WM_UNKNOW = 0x0, + ODM_WM_UNKNOWN = 0x0, ODM_WM_B = BIT0, ODM_WM_G = BIT1, ODM_WM_A = BIT2, diff --git a/drivers/staging/rtl8723bs/hal/odm_RegDefine11N.h b/drivers/staging/rtl8723bs/hal/odm_RegDefine11N.h index f2c0707aad4c..1c6c08000e27 100644 --- a/drivers/staging/rtl8723bs/hal/odm_RegDefine11N.h +++ b/drivers/staging/rtl8723bs/hal/odm_RegDefine11N.h @@ -31,8 +31,8 @@ #define ODM_REG_TX_ANT_CTRL_11N 0x80C #define ODM_REG_BB_PWR_SAV5_11N 0x818 #define ODM_REG_CCK_RPT_FORMAT_11N 0x824 -#define ODM_REG_RX_DEFUALT_A_11N 0x858 -#define ODM_REG_RX_DEFUALT_B_11N 0x85A +#define ODM_REG_RX_DEFAULT_A_11N 0x858 +#define ODM_REG_RX_DEFAULT_B_11N 0x85A #define ODM_REG_BB_PWR_SAV3_11N 0x85C #define ODM_REG_ANTSEL_CTRL_11N 0x860 #define ODM_REG_RX_ANT_CTRL_11N 0x864 diff --git a/drivers/staging/rtl8723bs/hal/rtl8723bs_recv.c b/drivers/staging/rtl8723bs/hal/rtl8723bs_recv.c index c3051ebaeb78..29c29e2e125b 100644 --- a/drivers/staging/rtl8723bs/hal/rtl8723bs_recv.c +++ b/drivers/staging/rtl8723bs/hal/rtl8723bs_recv.c @@ -311,39 +311,21 @@ static void rtl8723bs_recv_tasklet(unsigned long priv) } pkt_copy = rtw_skb_alloc(alloc_sz); - - if (pkt_copy) { - pkt_copy->dev = padapter->pnetdev; - precvframe->u.hdr.pkt = pkt_copy; - skb_reserve(pkt_copy, 8 - ((SIZE_PTR)(pkt_copy->data) & 7));/* force pkt_copy->data at 8-byte alignment address */ - skb_reserve(pkt_copy, shift_sz);/* force ip_hdr at 8-byte alignment address according to shift_sz. */ - memcpy(pkt_copy->data, (ptr + rx_report_sz + pattrib->shift_sz), skb_len); - precvframe->u.hdr.rx_head = pkt_copy->head; - precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pkt_copy->data; - precvframe->u.hdr.rx_end = skb_end_pointer(pkt_copy); - } else { - if ((pattrib->mfrag == 1) && (pattrib->frag_num == 0)) { - DBG_8192C("%s: alloc_skb fail, drop frag frame\n", __func__); - rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue); - break; - } - - precvframe->u.hdr.pkt = rtw_skb_clone(precvbuf->pskb); - if (precvframe->u.hdr.pkt) { - _pkt *pkt_clone = precvframe->u.hdr.pkt; - - pkt_clone->data = ptr + rx_report_sz + pattrib->shift_sz; - skb_reset_tail_pointer(pkt_clone); - precvframe->u.hdr.rx_head = precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail - = pkt_clone->data; - precvframe->u.hdr.rx_end = pkt_clone->data + skb_len; - } else { - DBG_8192C("%s: rtw_skb_clone fail\n", __func__); - rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue); - break; - } + if (!pkt_copy) { + DBG_8192C("%s: alloc_skb fail, drop frame\n", __func__); + rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue); + break; } + pkt_copy->dev = padapter->pnetdev; + precvframe->u.hdr.pkt = pkt_copy; + skb_reserve(pkt_copy, 8 - ((SIZE_PTR)(pkt_copy->data) & 7));/* force pkt_copy->data at 8-byte alignment address */ + skb_reserve(pkt_copy, shift_sz);/* force ip_hdr at 8-byte alignment address according to shift_sz. */ + memcpy(pkt_copy->data, (ptr + rx_report_sz + pattrib->shift_sz), skb_len); + precvframe->u.hdr.rx_head = pkt_copy->head; + precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pkt_copy->data; + precvframe->u.hdr.rx_end = skb_end_pointer(pkt_copy); + recvframe_put(precvframe, skb_len); /* recvframe_pull(precvframe, drvinfo_sz + RXDESC_SIZE); */ diff --git a/drivers/staging/rtl8723bs/hal/sdio_halinit.c b/drivers/staging/rtl8723bs/hal/sdio_halinit.c index 7853af53051d..e42d8c18e1ae 100644 --- a/drivers/staging/rtl8723bs/hal/sdio_halinit.c +++ b/drivers/staging/rtl8723bs/hal/sdio_halinit.c @@ -544,13 +544,9 @@ static void _InitRetryFunction(struct adapter *padapter) static void HalRxAggr8723BSdio(struct adapter *padapter) { - struct registry_priv *pregistrypriv; u8 valueDMATimeout; u8 valueDMAPageCount; - - pregistrypriv = &padapter->registrypriv; - valueDMATimeout = 0x06; valueDMAPageCount = 0x06; diff --git a/drivers/staging/rtl8723bs/include/hal_data.h b/drivers/staging/rtl8723bs/include/hal_data.h index e5e667df6154..fa5d70016f05 100644 --- a/drivers/staging/rtl8723bs/include/hal_data.h +++ b/drivers/staging/rtl8723bs/include/hal_data.h @@ -56,9 +56,9 @@ enum RT_AMPDU_BURST { /* Tx Power Limit Table Size */ #define MAX_REGULATION_NUM 4 #define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE 4 -#define MAX_2_4G_BANDWITH_NUM 4 +#define MAX_2_4G_BANDWIDTH_NUM 4 #define MAX_RATE_SECTION_NUM 10 -#define MAX_5G_BANDWITH_NUM 4 +#define MAX_5G_BANDWIDTH_NUM 4 #define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G 10 /* CCK:1, OFDM:1, HT:4, VHT:4 */ #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 9 /* OFDM:1, HT:4, VHT:4 */ @@ -280,14 +280,14 @@ struct hal_com_data { /* Power Limit Table for 2.4G */ s8 TxPwrLimit_2_4G[MAX_REGULATION_NUM] - [MAX_2_4G_BANDWITH_NUM] + [MAX_2_4G_BANDWIDTH_NUM] [MAX_RATE_SECTION_NUM] [CHANNEL_MAX_NUMBER_2G] [MAX_RF_PATH_NUM]; /* Power Limit Table for 5G */ s8 TxPwrLimit_5G[MAX_REGULATION_NUM] - [MAX_5G_BANDWITH_NUM] + [MAX_5G_BANDWIDTH_NUM] [MAX_RATE_SECTION_NUM] [CHANNEL_MAX_NUMBER_5G] [MAX_RF_PATH_NUM]; diff --git a/drivers/staging/rtl8723bs/include/rtw_recv.h b/drivers/staging/rtl8723bs/include/rtw_recv.h index 98c3e92245b7..a851b818ef0e 100644 --- a/drivers/staging/rtl8723bs/include/rtw_recv.h +++ b/drivers/staging/rtl8723bs/include/rtw_recv.h @@ -38,8 +38,6 @@ #define RX_MAX_QUEUE 2 #define MAX_SUBFRAME_COUNT 64 -extern u8 rtw_rfc1042_header[]; -extern u8 rtw_bridge_tunnel_header[]; /* for Rx reordering buffer control */ struct recv_reorder_ctrl diff --git a/drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c b/drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c index cd31ad2b8a7b..2fb80b6eb51d 100644 --- a/drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c +++ b/drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c @@ -98,7 +98,7 @@ static struct ieee80211_channel rtw_2ghz_channels[] = { static void rtw_2g_channels_init(struct ieee80211_channel *channels) { - memcpy((void*)channels, (void*)rtw_2ghz_channels, + memcpy((void *)channels, (void *)rtw_2ghz_channels, sizeof(struct ieee80211_channel)*RTW_2G_CHANNELS_NUM ); } @@ -133,8 +133,8 @@ static struct ieee80211_supported_band *rtw_spt_band_alloc( if (!spt_band) goto exit; - spt_band->channels = (struct ieee80211_channel*)(((u8 *)spt_band)+sizeof(struct ieee80211_supported_band)); - spt_band->bitrates = (struct ieee80211_rate*)(((u8 *)spt_band->channels)+sizeof(struct ieee80211_channel)*n_channels); + spt_band->channels = (struct ieee80211_channel *)(((u8 *)spt_band)+sizeof(struct ieee80211_supported_band)); + spt_band->bitrates = (struct ieee80211_rate *)(((u8 *)spt_band->channels)+sizeof(struct ieee80211_channel)*n_channels); spt_band->band = band; spt_band->n_channels = n_channels; spt_band->n_bitrates = n_bitrates; @@ -152,22 +152,6 @@ exit: return spt_band; } -static void rtw_spt_band_free(struct ieee80211_supported_band *spt_band) -{ - u32 size = 0; - - if (!spt_band) - return; - - if (spt_band->band == NL80211_BAND_2GHZ) - { - size = sizeof(struct ieee80211_supported_band) - + sizeof(struct ieee80211_channel)*RTW_2G_CHANNELS_NUM - + sizeof(struct ieee80211_rate)*RTW_G_RATES_NUM; - } - kfree(spt_band); -} - static const struct ieee80211_txrx_stypes rtw_cfg80211_default_mgmt_stypes[NUM_NL80211_IFTYPES] = { [NL80211_IFTYPE_ADHOC] = { @@ -358,7 +342,7 @@ struct cfg80211_bss *rtw_cfg80211_inform_bss(struct adapter *padapter, struct wl memcpy(pbuf, pnetwork->network.IEs, pnetwork->network.IELength); len += pnetwork->network.IELength; - *((__le64*)pbuf) = cpu_to_le64(notify_timestamp); + *((__le64 *)pbuf) = cpu_to_le64(notify_timestamp); bss = cfg80211_inform_bss_frame(wiphy, notify_channel, (struct ieee80211_mgmt *)buf, len, notify_signal, GFP_ATOMIC); @@ -1129,7 +1113,7 @@ static int cfg80211_rtw_add_key(struct wiphy *wiphy, struct net_device *ndev, else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == true) { if (mac_addr) - memcpy(param->sta_addr, (void*)mac_addr, ETH_ALEN); + memcpy(param->sta_addr, (void *)mac_addr, ETH_ALEN); ret = rtw_cfg80211_ap_set_encryption(ndev, param, param_len); } @@ -2485,7 +2469,7 @@ static netdev_tx_t rtw_cfg80211_monitor_if_xmit_entry(struct sk_buff *skb, struc * for two MAC addresses */ skb_pull(skb, dot11_hdr_len + qos_len + snap_len - sizeof(src_mac_addr) * 2); - pdata = (unsigned char*)skb->data; + pdata = (unsigned char *)skb->data; memcpy(pdata, dst_mac_addr, sizeof(dst_mac_addr)); memcpy(pdata + sizeof(dst_mac_addr), src_mac_addr, sizeof(src_mac_addr)); @@ -2540,7 +2524,7 @@ static netdev_tx_t rtw_cfg80211_monitor_if_xmit_entry(struct sk_buff *skb, struc pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - memcpy(pframe, (void*)buf, len); + memcpy(pframe, (void *)buf, len); pattrib->pktlen = len; pwlanhdr = (struct ieee80211_hdr *)pframe; @@ -3030,7 +3014,7 @@ static int _cfg80211_rtw_mgmt_tx(struct adapter *padapter, u8 tx_ch, const u8 *b pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - memcpy(pframe, (void*)buf, len); + memcpy(pframe, (void *)buf, len); pattrib->pktlen = len; pwlanhdr = (struct ieee80211_hdr *)pframe; @@ -3463,7 +3447,7 @@ void rtw_wdev_free(struct wireless_dev *wdev) if (!wdev) return; - rtw_spt_band_free(wdev->wiphy->bands[NL80211_BAND_2GHZ]); + kfree(wdev->wiphy->bands[NL80211_BAND_2GHZ]); wiphy_free(wdev->wiphy); diff --git a/drivers/staging/rtl8723bs/os_dep/ioctl_linux.c b/drivers/staging/rtl8723bs/os_dep/ioctl_linux.c index 5059b874080e..902ac8169948 100644 --- a/drivers/staging/rtl8723bs/os_dep/ioctl_linux.c +++ b/drivers/staging/rtl8723bs/os_dep/ioctl_linux.c @@ -2561,14 +2561,16 @@ static int rtw_wps_start(struct net_device *dev, struct adapter *padapter = (struct adapter *)rtw_netdev_priv(dev); struct iw_point *pdata = &wrqu->data; u32 u32wps_start = 0; - unsigned int uintRet = 0; if ((true == padapter->bDriverStopped) || (true == padapter->bSurpriseRemoved) || (NULL == pdata)) { ret = -EINVAL; goto exit; } - uintRet = copy_from_user((void *)&u32wps_start, pdata->pointer, 4); + if (copy_from_user((void *)&u32wps_start, pdata->pointer, 4)) { + ret = -EFAULT; + goto exit; + } if (u32wps_start == 0) u32wps_start = *extra; diff --git a/drivers/staging/rtl8723bs/os_dep/os_intfs.c b/drivers/staging/rtl8723bs/os_dep/os_intfs.c index d29f59bbb613..50a3c2c3a8d2 100644 --- a/drivers/staging/rtl8723bs/os_dep/os_intfs.c +++ b/drivers/staging/rtl8723bs/os_dep/os_intfs.c @@ -1057,9 +1057,9 @@ static int pm_netdev_open(struct net_device *pnetdev, u8 bnormal) status = _netdev_open(pnetdev); mutex_unlock(&(adapter_to_dvobj(padapter)->hw_init_mutex)); } - } - else + } else { status = (_SUCCESS == ips_netdrv_open(padapter)) ? (0) : (-1); + } return status; } @@ -1192,8 +1192,7 @@ void rtw_dev_unload(struct adapter *padapter) padapter->bup = false; DBG_871X("<=== %s\n", __func__); - } - else { + } else { RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("%s: bup ==false\n", __func__)); DBG_871X("%s: bup ==false\n", __func__); } @@ -1223,8 +1222,7 @@ static int rtw_suspend_free_assoc_resource(struct adapter *padapter) rtw_disassoc_cmd(padapter, 0, false); /* s2-2. indicate disconnect to os */ rtw_indicate_disconnect(padapter); - } - else if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { + } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { rtw_sta_flush(padapter); } @@ -1270,9 +1268,8 @@ void rtw_suspend_wow(struct adapter *padapter) padapter->bDriverStopped = false; /* for 32k command */ /* 2. disable interrupt */ - if (padapter->intf_stop) { + if (padapter->intf_stop) padapter->intf_stop(padapter); - } /* 2.1 clean interrupt */ if (padapter->HalFunc.clear_interrupt) @@ -1448,14 +1445,13 @@ int rtw_suspend_common(struct adapter *padapter) if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == true) { #ifdef CONFIG_WOWLAN - if (check_fwstate(pmlmepriv, _FW_LINKED)) { + if (check_fwstate(pmlmepriv, _FW_LINKED)) pwrpriv->wowlan_mode = true; - } else if (pwrpriv->wowlan_pno_enable == true) { + else if (pwrpriv->wowlan_pno_enable == true) pwrpriv->wowlan_mode |= pwrpriv->wowlan_pno_enable; - } if (pwrpriv->wowlan_mode == true) - rtw_suspend_wow(padapter); + rtw_suspend_wow(padapter); else rtw_suspend_normal(padapter); @@ -1522,9 +1518,8 @@ int rtw_resume_process_wow(struct adapter *padapter) pwrpriv->bFwCurrentInPSMode = false; - if (padapter->intf_stop) { + if (padapter->intf_stop) padapter->intf_stop(padapter); - } if (padapter->HalFunc.clear_interrupt) padapter->HalFunc.clear_interrupt(padapter); @@ -1541,18 +1536,15 @@ int rtw_resume_process_wow(struct adapter *padapter) padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_WOWLAN, (u8 *)&poidparam); psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv)); - if (psta) { + if (psta) set_sta_rate(padapter, psta); - } - padapter->bDriverStopped = false; DBG_871X("%s: wowmode resuming, DriverStopped:%d\n", __func__, padapter->bDriverStopped); rtw_start_drv_threads(padapter); - if (padapter->intf_start) { + if (padapter->intf_start) padapter->intf_start(padapter); - } /* start netif queue */ if (pnetdev) { @@ -1656,9 +1648,8 @@ int rtw_resume_process_ap_wow(struct adapter *padapter) DBG_871X("%s: wowmode resuming, DriverStopped:%d\n", __func__, padapter->bDriverStopped); rtw_start_drv_threads(padapter); - if (padapter->intf_start) { + if (padapter->intf_start) padapter->intf_start(padapter); - } /* start netif queue */ if (pnetdev) { diff --git a/drivers/staging/rtl8723bs/os_dep/recv_linux.c b/drivers/staging/rtl8723bs/os_dep/recv_linux.c index 60c35d92ba29..eb4d1c3008fe 100644 --- a/drivers/staging/rtl8723bs/os_dep/recv_linux.c +++ b/drivers/staging/rtl8723bs/os_dep/recv_linux.c @@ -9,6 +9,7 @@ #include #include #include +#include void rtw_os_free_recvframe(union recv_frame *precvframe) { @@ -60,27 +61,20 @@ _pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, u16 nSubframe_Length, u8 pattrib = &prframe->u.hdr.attrib; sub_skb = rtw_skb_alloc(nSubframe_Length + 12); - if (sub_skb) { - skb_reserve(sub_skb, 12); - skb_put_data(sub_skb, (pdata + ETH_HLEN), nSubframe_Length); - } else { - sub_skb = rtw_skb_clone(prframe->u.hdr.pkt); - if (sub_skb) { - sub_skb->data = pdata + ETH_HLEN; - sub_skb->len = nSubframe_Length; - skb_set_tail_pointer(sub_skb, nSubframe_Length); - } else { - DBG_871X("%s(): rtw_skb_clone() Fail!!!\n", __func__); - return NULL; - } + if (!sub_skb) { + DBG_871X("%s(): rtw_skb_alloc() Fail!!!\n", __func__); + return NULL; } + skb_reserve(sub_skb, 12); + skb_put_data(sub_skb, (pdata + ETH_HLEN), nSubframe_Length); + eth_type = RTW_GET_BE16(&sub_skb->data[6]); if (sub_skb->len >= 8 && - ((!memcmp(sub_skb->data, rtw_rfc1042_header, SNAP_SIZE) && + ((!memcmp(sub_skb->data, rfc1042_header, SNAP_SIZE) && eth_type != ETH_P_AARP && eth_type != ETH_P_IPX) || - !memcmp(sub_skb->data, rtw_bridge_tunnel_header, SNAP_SIZE))) { + !memcmp(sub_skb->data, bridge_tunnel_header, SNAP_SIZE))) { /* * remove RFC1042 or Bridge-Tunnel encapsulation and replace * EtherType @@ -230,7 +224,7 @@ static void rtw_os_ksocket_send(struct adapter *padapter, union recv_frame *prec if (rx_pid == psta->pid) { int i; - u16 len = *(u16*)(skb->data+ETH_HLEN+2); + u16 len = *(u16 *)(skb->data+ETH_HLEN+2); DBG_871X("eth, RC: len = 0x%x\n", len); for (i = 0; i < len; i++) diff --git a/drivers/staging/rtl8723bs/os_dep/sdio_intf.c b/drivers/staging/rtl8723bs/os_dep/sdio_intf.c index b093b5629171..5b1392deb0a7 100644 --- a/drivers/staging/rtl8723bs/os_dep/sdio_intf.c +++ b/drivers/staging/rtl8723bs/os_dep/sdio_intf.c @@ -514,7 +514,7 @@ static void rtw_dev_remove(struct sdio_func *func) rtw_unregister_netdevs(dvobj); - if (padapter->bSurpriseRemoved == false) { + if (!padapter->bSurpriseRemoved) { int err; /* test surprise remove */ @@ -554,12 +554,12 @@ static int rtw_sdio_suspend(struct device *dev) struct adapter *padapter = psdpriv->if1; struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; - if (padapter->bDriverStopped == true) { + if (padapter->bDriverStopped) { DBG_871X("%s bDriverStopped = %d\n", __func__, padapter->bDriverStopped); return 0; } - if (pwrpriv->bInSuspend == true) { + if (pwrpriv->bInSuspend) { DBG_871X("%s bInSuspend = %d\n", __func__, pwrpriv->bInSuspend); pdbgpriv->dbg_suspend_error_cnt++; return 0; @@ -574,7 +574,7 @@ static int rtw_resume_process(struct adapter *padapter) struct dvobj_priv *psdpriv = padapter->dvobj; struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; - if (pwrpriv->bInSuspend == false) { + if (!pwrpriv->bInSuspend) { pdbgpriv->dbg_resume_error_cnt++; DBG_871X("%s bInSuspend = %d\n", __func__, pwrpriv->bInSuspend); return -1; diff --git a/drivers/staging/sm750fb/sm750.c b/drivers/staging/sm750fb/sm750.c index 59568d18ce23..a1a82e59dfee 100644 --- a/drivers/staging/sm750fb/sm750.c +++ b/drivers/staging/sm750fb/sm750.c @@ -297,6 +297,62 @@ static int lynxfb_ops_pan_display(struct fb_var_screeninfo *var, return hw_sm750_pan_display(crtc, var, info); } +static inline void lynxfb_set_visual_mode(struct fb_info *info) +{ + switch (info->var.bits_per_pixel) { + case 8: + info->fix.visual = FB_VISUAL_PSEUDOCOLOR; + break; + case 16: + case 24: + case 32: + info->fix.visual = FB_VISUAL_TRUECOLOR; + break; + default: + break; + } +} + +static inline int lynxfb_set_color_offsets(struct fb_info *info) +{ + lynxfb_set_visual_mode(info); + + switch (info->var.bits_per_pixel) { + case 8: + info->var.red.offset = 0; + info->var.red.length = 8; + info->var.green.offset = 0; + info->var.green.length = 8; + info->var.blue.offset = 0; + info->var.blue.length = 8; + info->var.transp.length = 0; + info->var.transp.offset = 0; + break; + case 16: + info->var.red.offset = 11; + info->var.red.length = 5; + info->var.green.offset = 5; + info->var.green.length = 6; + info->var.blue.offset = 0; + info->var.blue.length = 5; + info->var.transp.length = 0; + info->var.transp.offset = 0; + break; + case 24: + case 32: + info->var.red.offset = 16; + info->var.red.length = 8; + info->var.green.offset = 8; + info->var.green.length = 8; + info->var.blue.offset = 0; + info->var.blue.length = 8; + break; + default: + return -EINVAL; + } + return 0; +} + static int lynxfb_ops_set_par(struct fb_info *info) { struct lynxfb_par *par; @@ -328,48 +384,13 @@ static int lynxfb_ops_set_par(struct fb_info *info) * and these data should be set before setcolreg routine */ - switch (var->bits_per_pixel) { - case 8: - fix->visual = FB_VISUAL_PSEUDOCOLOR; - var->red.offset = 0; - var->red.length = 8; - var->green.offset = 0; - var->green.length = 8; - var->blue.offset = 0; - var->blue.length = 8; - var->transp.length = 0; - var->transp.offset = 0; - break; - case 16: - var->red.offset = 11; - var->red.length = 5; - var->green.offset = 5; - var->green.length = 6; - var->blue.offset = 0; - var->blue.length = 5; - var->transp.length = 0; - var->transp.offset = 0; - fix->visual = FB_VISUAL_TRUECOLOR; - break; - case 24: - case 32: - var->red.offset = 16; - var->red.length = 8; - var->green.offset = 8; - var->green.length = 8; - var->blue.offset = 0; - var->blue.length = 8; - fix->visual = FB_VISUAL_TRUECOLOR; - break; - default: - ret = -EINVAL; - break; - } + ret = lynxfb_set_color_offsets(info); + var->height = var->width = -1; var->accel_flags = 0;/*FB_ACCELF_TEXT;*/ if (ret) { - pr_err("pixel bpp format not satisfied\n."); + pr_err("bpp %d not supported\n", var->bits_per_pixel); return ret; } ret = hw_sm750_crtc_setMode(crtc, var, fix); @@ -511,10 +532,12 @@ lynxfb_resume_err: static int lynxfb_ops_check_var(struct fb_var_screeninfo *var, struct fb_info *info) { + int ret; struct lynxfb_par *par; struct lynxfb_crtc *crtc; resource_size_t request; + ret = 0; par = info->par; crtc = &par->crtc; @@ -523,43 +546,13 @@ static int lynxfb_ops_check_var(struct fb_var_screeninfo *var, var->yres, var->bits_per_pixel); - switch (var->bits_per_pixel) { - case 8: - info->fix.visual = FB_VISUAL_PSEUDOCOLOR; - var->red.offset = 0; - var->red.length = 8; - var->green.offset = 0; - var->green.length = 8; - var->blue.offset = 0; - var->blue.length = 8; - var->transp.length = 0; - var->transp.offset = 0; - break; - case 16: - var->red.offset = 11; - var->red.length = 5; - var->green.offset = 5; - var->green.length = 6; - var->blue.offset = 0; - var->blue.length = 5; - var->transp.length = 0; - var->transp.offset = 0; - info->fix.visual = FB_VISUAL_TRUECOLOR; - break; - case 24: - case 32: - var->red.offset = 16; - var->red.length = 8; - var->green.offset = 8; - var->green.length = 8; - var->blue.offset = 0; - var->blue.length = 8; - info->fix.visual = FB_VISUAL_TRUECOLOR; - break; - default: + ret = lynxfb_set_color_offsets(info); + + if (ret) { pr_err("bpp %d not supported\n", var->bits_per_pixel); - return -EINVAL; + return ret; } + var->height = var->width = -1; var->accel_flags = 0;/* FB_ACCELF_TEXT; */ @@ -709,7 +702,9 @@ static int sm750fb_set_drv(struct lynxfb_par *par) } else { output->paths = sm750_crt; crtc->channel = sm750_primary; - /* not consider of padding stuffs for oScreen,need fix */ + /* not consider of padding stuffs for oScreen, + * need fix + */ crtc->oScreen = sm750_dev->vidmem_size >> 1; crtc->vScreen = sm750_dev->pvMem + crtc->oScreen; } @@ -893,15 +888,8 @@ static int lynxfb_set_fbinfo(struct fb_info *info, int index) pr_info("fix->mmio_start = %lx\n", fix->mmio_start); fix->mmio_len = sm750_dev->vidreg_size; pr_info("fix->mmio_len = %x\n", fix->mmio_len); - switch (var->bits_per_pixel) { - case 8: - fix->visual = FB_VISUAL_PSEUDOCOLOR; - break; - case 16: - case 32: - fix->visual = FB_VISUAL_TRUECOLOR; - break; - } + + lynxfb_set_visual_mode(info); /* set var */ var->activate = FB_ACTIVATE_NOW; diff --git a/drivers/staging/sm750fb/sm750.h b/drivers/staging/sm750fb/sm750.h index ce90adcb449d..19823c7277a4 100644 --- a/drivers/staging/sm750fb/sm750.h +++ b/drivers/staging/sm750fb/sm750.h @@ -59,16 +59,19 @@ struct lynx_accel { int (*de_wait)(void);/* see if hardware ready to work */ - int (*de_fillrect)(struct lynx_accel *, u32, u32, u32, u32, - u32, u32, u32, u32, u32); + int (*de_fillrect)(struct lynx_accel *, + u32, u32, u32, u32, + u32, u32, u32, u32, u32); - int (*de_copyarea)(struct lynx_accel *, u32, u32, u32, u32, - u32, u32, u32, u32, - u32, u32, u32, u32); + int (*de_copyarea)(struct lynx_accel *, + u32, u32, u32, u32, + u32, u32, u32, u32, + u32, u32, u32, u32); - int (*de_imageblit)(struct lynx_accel *, const char *, u32, u32, u32, u32, - u32, u32, u32, u32, - u32, u32, u32, u32); + int (*de_imageblit)(struct lynx_accel *, const char *, + u32, u32, u32, u32, + u32, u32, u32, u32, + u32, u32, u32, u32); }; @@ -163,7 +166,7 @@ struct lynxfb_output { */ void *priv; - int (*proc_setBLANK)(struct lynxfb_output*, int); + int (*proc_setBLANK)(struct lynxfb_output *output, int blank); }; struct lynxfb_par { diff --git a/drivers/staging/sm750fb/sm750_hw.c b/drivers/staging/sm750fb/sm750_hw.c index b8d60701f898..7136d751cff5 100644 --- a/drivers/staging/sm750fb/sm750_hw.c +++ b/drivers/staging/sm750fb/sm750_hw.c @@ -51,7 +51,7 @@ int hw_sm750_map(struct sm750_dev *sm750_dev, struct pci_dev *pdev) /* now map mmio and vidmem */ sm750_dev->pvReg = ioremap(sm750_dev->vidreg_start, - sm750_dev->vidreg_size); + sm750_dev->vidreg_size); if (!sm750_dev->pvReg) { pr_err("mmio failed\n"); ret = -EFAULT; diff --git a/drivers/staging/speakup/speakup_decext.c b/drivers/staging/speakup/speakup_decext.c index ddbb7e97d118..7408eb29cf38 100644 --- a/drivers/staging/speakup/speakup_decext.c +++ b/drivers/staging/speakup/speakup_decext.c @@ -43,6 +43,7 @@ static struct var_t vars[] = { { CAPS_STOP, .u.s = {"[:dv ap 100]" } }, { RATE, .u.n = {"[:ra %d]", 7, 0, 9, 150, 25, NULL } }, { PITCH, .u.n = {"[:dv ap %d]", 100, 0, 100, 0, 0, NULL } }, + { INFLECTION, .u.n = {"[:dv pr %d] ", 100, 0, 10000, 0, 0, NULL } }, { VOL, .u.n = {"[:dv gv %d]", 13, 0, 16, 0, 5, NULL } }, { PUNCT, .u.n = {"[:pu %c]", 0, 0, 2, 0, 0, "nsa" } }, { VOICE, .u.n = {"[:n%c]", 0, 0, 9, 0, 0, "phfdburwkv" } }, @@ -59,6 +60,8 @@ static struct kobj_attribute caps_stop_attribute = __ATTR(caps_stop, 0644, spk_var_show, spk_var_store); static struct kobj_attribute pitch_attribute = __ATTR(pitch, 0644, spk_var_show, spk_var_store); +static struct kobj_attribute inflection_attribute = + __ATTR(inflection, 0644, spk_var_show, spk_var_store); static struct kobj_attribute punct_attribute = __ATTR(punct, 0644, spk_var_show, spk_var_store); static struct kobj_attribute rate_attribute = @@ -87,6 +90,7 @@ static struct attribute *synth_attrs[] = { &caps_start_attribute.attr, &caps_stop_attribute.attr, &pitch_attribute.attr, + &inflection_attribute.attr, &punct_attribute.attr, &rate_attribute.attr, &voice_attribute.attr, diff --git a/drivers/staging/speakup/speakup_decpc.c b/drivers/staging/speakup/speakup_decpc.c index 798c42dfa16c..96f24c848cc5 100644 --- a/drivers/staging/speakup/speakup_decpc.c +++ b/drivers/staging/speakup/speakup_decpc.c @@ -139,6 +139,7 @@ static struct var_t vars[] = { { CAPS_STOP, .u.s = {"[:dv ap 100]" } }, { RATE, .u.n = {"[:ra %d]", 9, 0, 18, 150, 25, NULL } }, { PITCH, .u.n = {"[:dv ap %d]", 80, 0, 100, 20, 0, NULL } }, + { INFLECTION, .u.n = {"[:dv pr %d] ", 100, 0, 10000, 0, 0, NULL } }, { VOL, .u.n = {"[:vo se %d]", 5, 0, 9, 5, 10, NULL } }, { PUNCT, .u.n = {"[:pu %c]", 0, 0, 2, 0, 0, "nsa" } }, { VOICE, .u.n = {"[:n%c]", 0, 0, 9, 0, 0, "phfdburwkv" } }, @@ -155,6 +156,8 @@ static struct kobj_attribute caps_stop_attribute = __ATTR(caps_stop, 0644, spk_var_show, spk_var_store); static struct kobj_attribute pitch_attribute = __ATTR(pitch, 0644, spk_var_show, spk_var_store); +static struct kobj_attribute inflection_attribute = + __ATTR(inflection, 0644, spk_var_show, spk_var_store); static struct kobj_attribute punct_attribute = __ATTR(punct, 0644, spk_var_show, spk_var_store); static struct kobj_attribute rate_attribute = @@ -183,6 +186,7 @@ static struct attribute *synth_attrs[] = { &caps_start_attribute.attr, &caps_stop_attribute.attr, &pitch_attribute.attr, + &inflection_attribute.attr, &punct_attribute.attr, &rate_attribute.attr, &voice_attribute.attr, diff --git a/drivers/staging/speakup/speakup_dectlk.c b/drivers/staging/speakup/speakup_dectlk.c index dccb4ea29d37..780214b5ca16 100644 --- a/drivers/staging/speakup/speakup_dectlk.c +++ b/drivers/staging/speakup/speakup_dectlk.c @@ -44,7 +44,7 @@ static struct var_t vars[] = { { CAPS_START, .u.s = {"[:dv ap 160] " } }, { CAPS_STOP, .u.s = {"[:dv ap 100 ] " } }, { RATE, .u.n = {"[:ra %d] ", 180, 75, 650, 0, 0, NULL } }, - { PITCH, .u.n = {"[:dv ap %d] ", 122, 50, 350, 0, 0, NULL } }, + { INFLECTION, .u.n = {"[:dv pr %d] ", 100, 0, 10000, 0, 0, NULL } }, { VOL, .u.n = {"[:dv g5 %d] ", 86, 60, 86, 0, 0, NULL } }, { PUNCT, .u.n = {"[:pu %c] ", 0, 0, 2, 0, 0, "nsa" } }, { VOICE, .u.n = {"[:n%c] ", 0, 0, 9, 0, 0, "phfdburwkv" } }, @@ -61,6 +61,8 @@ static struct kobj_attribute caps_stop_attribute = __ATTR(caps_stop, 0644, spk_var_show, spk_var_store); static struct kobj_attribute pitch_attribute = __ATTR(pitch, 0644, spk_var_show, spk_var_store); +static struct kobj_attribute inflection_attribute = + __ATTR(inflection, 0644, spk_var_show, spk_var_store); static struct kobj_attribute punct_attribute = __ATTR(punct, 0644, spk_var_show, spk_var_store); static struct kobj_attribute rate_attribute = @@ -89,6 +91,7 @@ static struct attribute *synth_attrs[] = { &caps_start_attribute.attr, &caps_stop_attribute.attr, &pitch_attribute.attr, + &inflection_attribute.attr, &punct_attribute.attr, &rate_attribute.attr, &voice_attribute.attr, diff --git a/drivers/staging/speakup/speakup_dummy.c b/drivers/staging/speakup/speakup_dummy.c index 7df1a84297f6..e393438af81b 100644 --- a/drivers/staging/speakup/speakup_dummy.c +++ b/drivers/staging/speakup/speakup_dummy.c @@ -24,6 +24,7 @@ static struct var_t vars[] = { { PAUSE, .u.s = {"PAUSE\n"} }, { RATE, .u.n = {"RATE %d\n", 8, 1, 16, 0, 0, NULL } }, { PITCH, .u.n = {"PITCH %d\n", 8, 0, 16, 0, 0, NULL } }, + { INFLECTION, .u.n = {"INFLECTION %d\n", 8, 0, 16, 0, 0, NULL } }, { VOL, .u.n = {"VOL %d\n", 8, 0, 16, 0, 0, NULL } }, { TONE, .u.n = {"TONE %d\n", 8, 0, 16, 0, 0, NULL } }, { DIRECT, .u.n = {NULL, 0, 0, 1, 0, 0, NULL } }, @@ -39,6 +40,8 @@ static struct kobj_attribute caps_stop_attribute = __ATTR(caps_stop, 0644, spk_var_show, spk_var_store); static struct kobj_attribute pitch_attribute = __ATTR(pitch, 0644, spk_var_show, spk_var_store); +static struct kobj_attribute inflection_attribute = + __ATTR(inflection, 0644, spk_var_show, spk_var_store); static struct kobj_attribute rate_attribute = __ATTR(rate, 0644, spk_var_show, spk_var_store); static struct kobj_attribute tone_attribute = @@ -65,6 +68,7 @@ static struct attribute *synth_attrs[] = { &caps_start_attribute.attr, &caps_stop_attribute.attr, &pitch_attribute.attr, + &inflection_attribute.attr, &rate_attribute.attr, &tone_attribute.attr, &vol_attribute.attr, diff --git a/drivers/staging/speakup/speakup_soft.c b/drivers/staging/speakup/speakup_soft.c index f591ec095582..9a7029539f35 100644 --- a/drivers/staging/speakup/speakup_soft.c +++ b/drivers/staging/speakup/speakup_soft.c @@ -38,6 +38,7 @@ static struct var_t vars[] = { { PAUSE, .u.n = {"\x01P" } }, { RATE, .u.n = {"\x01%ds", 2, 0, 9, 0, 0, NULL } }, { PITCH, .u.n = {"\x01%dp", 5, 0, 9, 0, 0, NULL } }, + { INFLECTION, .u.n = {"\x01%dr", 5, 0, 9, 0, 0, NULL } }, { VOL, .u.n = {"\x01%dv", 5, 0, 9, 0, 0, NULL } }, { TONE, .u.n = {"\x01%dx", 1, 0, 2, 0, 0, NULL } }, { PUNCT, .u.n = {"\x01%db", 0, 0, 2, 0, 0, NULL } }, @@ -57,6 +58,8 @@ static struct kobj_attribute freq_attribute = __ATTR(freq, 0644, spk_var_show, spk_var_store); static struct kobj_attribute pitch_attribute = __ATTR(pitch, 0644, spk_var_show, spk_var_store); +static struct kobj_attribute inflection_attribute = + __ATTR(inflection, 0644, spk_var_show, spk_var_store); static struct kobj_attribute punct_attribute = __ATTR(punct, 0644, spk_var_show, spk_var_store); static struct kobj_attribute rate_attribute = @@ -96,6 +99,7 @@ static struct attribute *synth_attrs[] = { &freq_attribute.attr, /* &lang_attribute.attr, */ &pitch_attribute.attr, + &inflection_attribute.attr, &punct_attribute.attr, &rate_attribute.attr, &tone_attribute.attr, diff --git a/drivers/staging/speakup/spk_types.h b/drivers/staging/speakup/spk_types.h index fc6a9416829c..d3272c6d199a 100644 --- a/drivers/staging/speakup/spk_types.h +++ b/drivers/staging/speakup/spk_types.h @@ -42,7 +42,8 @@ enum var_id_t { SAY_CONTROL, SAY_WORD_CTL, NO_INTERRUPT, KEY_ECHO, SPELL_DELAY, PUNC_LEVEL, READING_PUNC, ATTRIB_BLEEP, BLEEPS, - RATE, PITCH, VOL, TONE, PUNCT, VOICE, FREQUENCY, LANG, DIRECT, PAUSE, + RATE, PITCH, INFLECTION, VOL, TONE, PUNCT, VOICE, FREQUENCY, LANG, + DIRECT, PAUSE, CAPS_START, CAPS_STOP, CHARTAB, MAXVARS }; diff --git a/drivers/staging/speakup/spkguide.txt b/drivers/staging/speakup/spkguide.txt index c23549c54c3c..1e622cd34363 100644 --- a/drivers/staging/speakup/spkguide.txt +++ b/drivers/staging/speakup/spkguide.txt @@ -406,6 +406,7 @@ freq full_time jiffy_delta pitch +inflection punct rate tone @@ -518,9 +519,9 @@ All the entries in the Speakup sys system are readable, some are writable by root only, and some are writable by everyone. Unless you know what you are doing, you should probably leave the ones that are writable by root only alone. Most of the names are self explanatory. -Vol for controlling volume, pitch for pitch, rate for controlling speaking -rate, etc. If you find one you aren't sure about, you can post a query -on the Speakup list. +Vol for controlling volume, pitch for pitch, inflection for pitch range, rate +for controlling speaking rate, etc. If you find one you aren't sure about, you +can post a query on the Speakup list. 6. Changing Synthesizers diff --git a/drivers/staging/speakup/sysfs-driver-speakup b/drivers/staging/speakup/sysfs-driver-speakup index be3f5d6962e9..c6a32c434ce9 100644 --- a/drivers/staging/speakup/sysfs-driver-speakup +++ b/drivers/staging/speakup/sysfs-driver-speakup @@ -325,6 +325,12 @@ KernelVersion: 2.6 Contact: speakup@linux-speakup.org Description: Gets or sets the pitch of the synthesizer. The range is 0-9. +What: /sys/accessibility/speakup/soft/inflection +KernelVersion: 5.8 +Contact: speakup@linux-speakup.org +Description: Gets or sets the inflection of the synthesizer, i.e. the pitch + range. The range is 0-9. + What: /sys/accessibility/speakup/soft/punct KernelVersion: 2.6 Contact: speakup@linux-speakup.org diff --git a/drivers/staging/speakup/varhandlers.c b/drivers/staging/speakup/varhandlers.c index 5741d1cb6227..d7f6bec7ff06 100644 --- a/drivers/staging/speakup/varhandlers.c +++ b/drivers/staging/speakup/varhandlers.c @@ -37,6 +37,7 @@ static struct st_var_header var_headers[] = { { "bell_pos", BELL_POS, VAR_NUM, &spk_bell_pos, NULL }, { "rate", RATE, VAR_NUM, NULL, NULL }, { "pitch", PITCH, VAR_NUM, NULL, NULL }, + { "inflection", INFLECTION, VAR_NUM, NULL, NULL }, { "vol", VOL, VAR_NUM, NULL, NULL }, { "tone", TONE, VAR_NUM, NULL, NULL }, { "punct", PUNCT, VAR_NUM, NULL, NULL }, diff --git a/drivers/staging/unisys/visorhba/visorhba_main.c b/drivers/staging/unisys/visorhba/visorhba_main.c index dd979ee4dcf1..99c57ceeb357 100644 --- a/drivers/staging/unisys/visorhba/visorhba_main.c +++ b/drivers/staging/unisys/visorhba/visorhba_main.c @@ -292,7 +292,7 @@ static void cleanup_scsitaskmgmt_handles(struct idr *idrtable, * @tasktype: Type of taskmgmt command * @scsidev: Scsidev that issued command * - * Create a cmdrsp packet and send it to the Serivce Partition + * Create a cmdrsp packet and send it to the Service Partition * that will service this request. * * Return: Int representing whether command was queued successfully or not diff --git a/drivers/staging/vc04_services/bcm2835-audio/bcm2835-pcm.c b/drivers/staging/vc04_services/bcm2835-audio/bcm2835-pcm.c index 33485184a98a..f783b632141b 100644 --- a/drivers/staging/vc04_services/bcm2835-audio/bcm2835-pcm.c +++ b/drivers/staging/vc04_services/bcm2835-audio/bcm2835-pcm.c @@ -233,7 +233,7 @@ static int snd_bcm2835_pcm_prepare(struct snd_pcm_substream *substream) } static void snd_bcm2835_pcm_transfer(struct snd_pcm_substream *substream, - struct snd_pcm_indirect *rec, size_t bytes) + struct snd_pcm_indirect *rec, size_t bytes) { struct snd_pcm_runtime *runtime = substream->runtime; struct bcm2835_alsa_stream *alsa_stream = runtime->private_data; @@ -346,7 +346,7 @@ int snd_bcm2835_new_pcm(struct bcm2835_chip *chip, const char *name, &snd_bcm2835_playback_ops); snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, - chip->card->dev, 128 * 1024, 128 * 1024); + chip->card->dev, 128 * 1024, 128 * 1024); if (spdif) chip->pcm_spdif = pcm; diff --git a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c index 597acef35d0b..4f1adddb804f 100644 --- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c +++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c @@ -369,8 +369,8 @@ static void buffer_cb(struct vchiq_mmal_instance *instance, if (dev->capture.vc_start_timestamp != -1 && pts) { ktime_t timestamp; - s64 runtime_us = pts - - dev->capture.vc_start_timestamp; + s64 runtime_us = pts - dev->capture.vc_start_timestamp; + timestamp = ktime_add_us(dev->capture.kernel_start_ts, runtime_us); v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, @@ -420,9 +420,8 @@ static int enable_camera(struct bm2835_mmal_dev *dev) return -EINVAL; } - ret = vchiq_mmal_component_enable( - dev->instance, - dev->component[COMP_CAMERA]); + ret = vchiq_mmal_component_enable(dev->instance, + dev->component[COMP_CAMERA]); if (ret < 0) { v4l2_err(&dev->v4l2_dev, "Failed enabling camera, ret %d\n", ret); @@ -451,10 +450,8 @@ static int disable_camera(struct bm2835_mmal_dev *dev) v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "Disabling camera\n"); - ret = - vchiq_mmal_component_disable( - dev->instance, - dev->component[COMP_CAMERA]); + ret = vchiq_mmal_component_disable(dev->instance, + dev->component[COMP_CAMERA]); if (ret < 0) { v4l2_err(&dev->v4l2_dev, "Failed disabling camera, ret %d\n", ret); @@ -555,8 +552,8 @@ static int start_streaming(struct vb2_queue *vq, unsigned int count) /* enable the camera port */ dev->capture.port->cb_ctx = dev; - ret = - vchiq_mmal_port_enable(dev->instance, dev->capture.port, buffer_cb); + ret = vchiq_mmal_port_enable(dev->instance, dev->capture.port, + buffer_cb); if (ret) { v4l2_err(&dev->v4l2_dev, "Failed to enable capture port - error %d. Disabling camera port again\n", @@ -668,7 +665,7 @@ static int set_overlay_params(struct bm2835_mmal_dev *dev, MMAL_DISPLAY_SET_ALPHA | MMAL_DISPLAY_SET_DEST_RECT | MMAL_DISPLAY_SET_FULLSCREEN, - .layer = PREVIEW_LAYER, + .layer = 2, .alpha = dev->overlay.global_alpha, .fullscreen = 0, .dest_rect = { @@ -767,16 +764,14 @@ static int vidioc_overlay(struct file *file, void *f, unsigned int on) (!on && !dev->component[COMP_PREVIEW]->enabled)) return 0; /* already in requested state */ - src = - &dev->component[COMP_CAMERA]->output[CAM_PORT_PREVIEW]; + src = &dev->component[COMP_CAMERA]->output[CAM_PORT_PREVIEW]; if (!on) { /* disconnect preview ports and disable component */ ret = vchiq_mmal_port_disable(dev->instance, src); if (!ret) - ret = - vchiq_mmal_port_connect_tunnel(dev->instance, src, - NULL); + ret = vchiq_mmal_port_connect_tunnel(dev->instance, src, + NULL); if (ret >= 0) ret = vchiq_mmal_component_disable( dev->instance, @@ -800,9 +795,8 @@ static int vidioc_overlay(struct file *file, void *f, unsigned int on) if (enable_camera(dev) < 0) return -EINVAL; - ret = vchiq_mmal_component_enable( - dev->instance, - dev->component[COMP_PREVIEW]); + ret = vchiq_mmal_component_enable(dev->instance, + dev->component[COMP_PREVIEW]); if (ret < 0) return ret; @@ -1001,6 +995,141 @@ static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, return 0; } + +static int mmal_setup_video_component(struct bm2835_mmal_dev *dev, + struct v4l2_format *f) +{ + bool overlay_enabled = !!dev->component[COMP_PREVIEW]->enabled; + struct vchiq_mmal_port *preview_port; + int ret; + + preview_port = &dev->component[COMP_CAMERA]->output[CAM_PORT_PREVIEW]; + + /* Preview and encode ports need to match on resolution */ + if (overlay_enabled) { + /* Need to disable the overlay before we can update + * the resolution + */ + ret = vchiq_mmal_port_disable(dev->instance, preview_port); + if (!ret) { + ret = vchiq_mmal_port_connect_tunnel(dev->instance, + preview_port, + NULL); + } + } + preview_port->es.video.width = f->fmt.pix.width; + preview_port->es.video.height = f->fmt.pix.height; + preview_port->es.video.crop.x = 0; + preview_port->es.video.crop.y = 0; + preview_port->es.video.crop.width = f->fmt.pix.width; + preview_port->es.video.crop.height = f->fmt.pix.height; + preview_port->es.video.frame_rate.num = + dev->capture.timeperframe.denominator; + preview_port->es.video.frame_rate.den = + dev->capture.timeperframe.numerator; + ret = vchiq_mmal_port_set_format(dev->instance, preview_port); + + if (overlay_enabled) { + ret = vchiq_mmal_port_connect_tunnel(dev->instance, + preview_port, + &dev->component[COMP_PREVIEW]->input[0]); + if (ret) + return ret; + + ret = vchiq_mmal_port_enable(dev->instance, preview_port, NULL); + } + + return ret; +} + +static int mmal_setup_encode_component(struct bm2835_mmal_dev *dev, + struct v4l2_format *f, + struct vchiq_mmal_port *port, + struct vchiq_mmal_port *camera_port, + struct vchiq_mmal_component *component) +{ + struct mmal_fmt *mfmt = get_format(f); + int ret; + + v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, + "vid_cap - set up encode comp\n"); + + /* configure buffering */ + camera_port->current_buffer.size = camera_port->recommended_buffer.size; + camera_port->current_buffer.num = camera_port->recommended_buffer.num; + + ret = vchiq_mmal_port_connect_tunnel(dev->instance, camera_port, + &component->input[0]); + if (ret) { + v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, + "%s failed to create connection\n", __func__); + /* ensure capture is not going to be tried */ + dev->capture.port = NULL; + return ret; + } + + port->es.video.width = f->fmt.pix.width; + port->es.video.height = f->fmt.pix.height; + port->es.video.crop.x = 0; + port->es.video.crop.y = 0; + port->es.video.crop.width = f->fmt.pix.width; + port->es.video.crop.height = f->fmt.pix.height; + port->es.video.frame_rate.num = + dev->capture.timeperframe.denominator; + port->es.video.frame_rate.den = + dev->capture.timeperframe.numerator; + + port->format.encoding = mfmt->mmal; + port->format.encoding_variant = 0; + /* Set any encoding specific parameters */ + switch (mfmt->mmal_component) { + case COMP_VIDEO_ENCODE: + port->format.bitrate = dev->capture.encode_bitrate; + break; + case COMP_IMAGE_ENCODE: + /* Could set EXIF parameters here */ + break; + default: + break; + } + + ret = vchiq_mmal_port_set_format(dev->instance, port); + if (ret) { + v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, + "%s failed to set format %dx%d fmt %08X\n", + __func__, + f->fmt.pix.width, + f->fmt.pix.height, + f->fmt.pix.pixelformat); + return ret; + } + + ret = vchiq_mmal_component_enable(dev->instance, component); + if (ret) { + v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, + "%s Failed to enable encode components\n", __func__); + return ret; + } + + /* configure buffering */ + port->current_buffer.num = 1; + port->current_buffer.size = f->fmt.pix.sizeimage; + if (port->format.encoding == MMAL_ENCODING_JPEG) { + v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, + "JPG - buf size now %d was %d\n", + f->fmt.pix.sizeimage, + port->current_buffer.size); + port->current_buffer.size = + (f->fmt.pix.sizeimage < (100 << 10)) ? + (100 << 10) : f->fmt.pix.sizeimage; + } + v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, + "vid_cap - cur_buf.size set to %d\n", f->fmt.pix.sizeimage); + port->current_buffer.alignment = 0; + + return 0; +} + static int mmal_setup_components(struct bm2835_mmal_dev *dev, struct v4l2_format *f) { @@ -1075,8 +1204,7 @@ static int mmal_setup_components(struct bm2835_mmal_dev *dev, } remove_padding = mfmt->remove_padding; - vchiq_mmal_port_parameter_set(dev->instance, - camera_port, + vchiq_mmal_port_parameter_set(dev->instance, camera_port, MMAL_PARAMETER_NO_IMAGE_PADDING, &remove_padding, sizeof(remove_padding)); @@ -1096,46 +1224,7 @@ static int mmal_setup_components(struct bm2835_mmal_dev *dev, if (!ret && camera_port == &dev->component[COMP_CAMERA]->output[CAM_PORT_VIDEO]) { - bool overlay_enabled = - !!dev->component[COMP_PREVIEW]->enabled; - struct vchiq_mmal_port *preview_port = - &dev->component[COMP_CAMERA]->output[CAM_PORT_PREVIEW]; - /* Preview and encode ports need to match on resolution */ - if (overlay_enabled) { - /* Need to disable the overlay before we can update - * the resolution - */ - ret = - vchiq_mmal_port_disable(dev->instance, - preview_port); - if (!ret) - ret = - vchiq_mmal_port_connect_tunnel( - dev->instance, - preview_port, - NULL); - } - preview_port->es.video.width = f->fmt.pix.width; - preview_port->es.video.height = f->fmt.pix.height; - preview_port->es.video.crop.x = 0; - preview_port->es.video.crop.y = 0; - preview_port->es.video.crop.width = f->fmt.pix.width; - preview_port->es.video.crop.height = f->fmt.pix.height; - preview_port->es.video.frame_rate.num = - dev->capture.timeperframe.denominator; - preview_port->es.video.frame_rate.den = - dev->capture.timeperframe.numerator; - ret = vchiq_mmal_port_set_format(dev->instance, preview_port); - if (overlay_enabled) { - ret = vchiq_mmal_port_connect_tunnel( - dev->instance, - preview_port, - &dev->component[COMP_PREVIEW]->input[0]); - if (!ret) - ret = vchiq_mmal_port_enable(dev->instance, - preview_port, - NULL); - } + ret = mmal_setup_video_component(dev, f); } if (ret) { @@ -1145,129 +1234,40 @@ static int mmal_setup_components(struct bm2835_mmal_dev *dev, f->fmt.pix.pixelformat); /* ensure capture is not going to be tried */ dev->capture.port = NULL; - } else { - if (encode_component) { - v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, - "vid_cap - set up encode comp\n"); - - /* configure buffering */ - camera_port->current_buffer.size = - camera_port->recommended_buffer.size; - camera_port->current_buffer.num = - camera_port->recommended_buffer.num; - - ret = - vchiq_mmal_port_connect_tunnel( - dev->instance, - camera_port, - &encode_component->input[0]); - if (ret) { - v4l2_dbg(1, bcm2835_v4l2_debug, - &dev->v4l2_dev, - "%s failed to create connection\n", - __func__); - /* ensure capture is not going to be tried */ - dev->capture.port = NULL; - } else { - port->es.video.width = f->fmt.pix.width; - port->es.video.height = f->fmt.pix.height; - port->es.video.crop.x = 0; - port->es.video.crop.y = 0; - port->es.video.crop.width = f->fmt.pix.width; - port->es.video.crop.height = f->fmt.pix.height; - port->es.video.frame_rate.num = - dev->capture.timeperframe.denominator; - port->es.video.frame_rate.den = - dev->capture.timeperframe.numerator; - - port->format.encoding = mfmt->mmal; - port->format.encoding_variant = 0; - /* Set any encoding specific parameters */ - switch (mfmt->mmal_component) { - case COMP_VIDEO_ENCODE: - port->format.bitrate = - dev->capture.encode_bitrate; - break; - case COMP_IMAGE_ENCODE: - /* Could set EXIF parameters here */ - break; - default: - break; - } - ret = vchiq_mmal_port_set_format(dev->instance, - port); - if (ret) - v4l2_dbg(1, bcm2835_v4l2_debug, - &dev->v4l2_dev, - "%s failed to set format %dx%d fmt %08X\n", - __func__, - f->fmt.pix.width, - f->fmt.pix.height, - f->fmt.pix.pixelformat - ); - } - - if (!ret) { - ret = vchiq_mmal_component_enable( - dev->instance, - encode_component); - if (ret) { - v4l2_dbg(1, bcm2835_v4l2_debug, - &dev->v4l2_dev, - "%s Failed to enable encode components\n", - __func__); - } - } - if (!ret) { - /* configure buffering */ - port->current_buffer.num = 1; - port->current_buffer.size = - f->fmt.pix.sizeimage; - if (port->format.encoding == - MMAL_ENCODING_JPEG) { - v4l2_dbg(1, bcm2835_v4l2_debug, - &dev->v4l2_dev, - "JPG - buf size now %d was %d\n", - f->fmt.pix.sizeimage, - port->current_buffer.size); - port->current_buffer.size = - (f->fmt.pix.sizeimage < - (100 << 10)) ? - (100 << 10) : f->fmt.pix.sizeimage; - } - v4l2_dbg(1, bcm2835_v4l2_debug, - &dev->v4l2_dev, - "vid_cap - cur_buf.size set to %d\n", - f->fmt.pix.sizeimage); - port->current_buffer.alignment = 0; - } - } else { - /* configure buffering */ - camera_port->current_buffer.num = 1; - camera_port->current_buffer.size = f->fmt.pix.sizeimage; - camera_port->current_buffer.alignment = 0; - } - - if (!ret) { - dev->capture.fmt = mfmt; - dev->capture.stride = f->fmt.pix.bytesperline; - dev->capture.width = camera_port->es.video.crop.width; - dev->capture.height = camera_port->es.video.crop.height; - dev->capture.buffersize = port->current_buffer.size; - - /* select port for capture */ - dev->capture.port = port; - dev->capture.camera_port = camera_port; - dev->capture.encode_component = encode_component; - v4l2_dbg(1, bcm2835_v4l2_debug, - &dev->v4l2_dev, - "Set dev->capture.fmt %08X, %dx%d, stride %d, size %d", - port->format.encoding, - dev->capture.width, dev->capture.height, - dev->capture.stride, dev->capture.buffersize); - } + return ret; } + if (encode_component) { + ret = mmal_setup_encode_component(dev, f, port, + camera_port, + encode_component); + + if (ret) + return ret; + } else { + /* configure buffering */ + camera_port->current_buffer.num = 1; + camera_port->current_buffer.size = f->fmt.pix.sizeimage; + camera_port->current_buffer.alignment = 0; + } + + dev->capture.fmt = mfmt; + dev->capture.stride = f->fmt.pix.bytesperline; + dev->capture.width = camera_port->es.video.crop.width; + dev->capture.height = camera_port->es.video.crop.height; + dev->capture.buffersize = port->current_buffer.size; + + /* select port for capture */ + dev->capture.port = port; + dev->capture.camera_port = camera_port; + dev->capture.encode_component = encode_component; + v4l2_dbg(1, bcm2835_v4l2_debug, + &dev->v4l2_dev, + "Set dev->capture.fmt %08X, %dx%d, stride %d, size %d", + port->format.encoding, + dev->capture.width, dev->capture.height, + dev->capture.stride, dev->capture.buffersize); + /* todo: Need to convert the vchiq/mmal error into a v4l2 error. */ return ret; } @@ -1658,9 +1658,8 @@ static int mmal_init(struct bm2835_mmal_dev *dev) dev->capture.enc_level = V4L2_MPEG_VIDEO_H264_LEVEL_4_0; /* get the preview component ready */ - ret = vchiq_mmal_component_init( - dev->instance, "ril.video_render", - &dev->component[COMP_PREVIEW]); + ret = vchiq_mmal_component_init(dev->instance, "ril.video_render", + &dev->component[COMP_PREVIEW]); if (ret < 0) goto unreg_camera; @@ -1672,9 +1671,8 @@ static int mmal_init(struct bm2835_mmal_dev *dev) } /* get the image encoder component ready */ - ret = vchiq_mmal_component_init( - dev->instance, "ril.image_encode", - &dev->component[COMP_IMAGE_ENCODE]); + ret = vchiq_mmal_component_init(dev->instance, "ril.image_encode", + &dev->component[COMP_IMAGE_ENCODE]); if (ret < 0) goto unreg_preview; @@ -1734,15 +1732,13 @@ static int mmal_init(struct bm2835_mmal_dev *dev) unreg_vid_encoder: pr_err("Cleanup: Destroy video encoder\n"); - vchiq_mmal_component_finalise( - dev->instance, - dev->component[COMP_VIDEO_ENCODE]); + vchiq_mmal_component_finalise(dev->instance, + dev->component[COMP_VIDEO_ENCODE]); unreg_image_encoder: pr_err("Cleanup: Destroy image encoder\n"); - vchiq_mmal_component_finalise( - dev->instance, - dev->component[COMP_IMAGE_ENCODE]); + vchiq_mmal_component_finalise(dev->instance, + dev->component[COMP_IMAGE_ENCODE]); unreg_preview: pr_err("Cleanup: Destroy video render\n"); @@ -1775,8 +1771,7 @@ static int bm2835_mmal_init_device(struct bm2835_mmal_dev *dev, /* video device needs to be able to access instance data */ video_set_drvdata(vfd, dev); - ret = video_register_device(vfd, - VFL_TYPE_VIDEO, + ret = video_register_device(vfd, VFL_TYPE_VIDEO, video_nr[dev->camera_num]); if (ret < 0) return ret; diff --git a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.h b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.h index b5fce38de038..75524adff0f5 100644 --- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.h +++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.h @@ -30,79 +30,77 @@ enum { CAM_PORT_COUNT }; -#define PREVIEW_LAYER 2 - extern int bcm2835_v4l2_debug; struct bm2835_mmal_dev { /* v4l2 devices */ - struct v4l2_device v4l2_dev; - struct video_device vdev; - struct mutex mutex; + struct v4l2_device v4l2_dev; + struct video_device vdev; + struct mutex mutex; /* controls */ - struct v4l2_ctrl_handler ctrl_handler; - struct v4l2_ctrl *ctrls[V4L2_CTRL_COUNT]; - enum v4l2_scene_mode scene_mode; - struct mmal_colourfx colourfx; - int hflip; - int vflip; - int red_gain; - int blue_gain; + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_ctrl *ctrls[V4L2_CTRL_COUNT]; + enum v4l2_scene_mode scene_mode; + struct mmal_colourfx colourfx; + int hflip; + int vflip; + int red_gain; + int blue_gain; enum mmal_parameter_exposuremode exposure_mode_user; enum v4l2_exposure_auto_type exposure_mode_v4l2_user; /* active exposure mode may differ if selected via a scene mode */ enum mmal_parameter_exposuremode exposure_mode_active; enum mmal_parameter_exposuremeteringmode metering_mode; - unsigned int manual_shutter_speed; - bool exp_auto_priority; + unsigned int manual_shutter_speed; + bool exp_auto_priority; bool manual_iso_enabled; u32 iso; /* allocated mmal instance and components */ - struct vchiq_mmal_instance *instance; - struct vchiq_mmal_component *component[COMP_COUNT]; + struct vchiq_mmal_instance *instance; + struct vchiq_mmal_component *component[COMP_COUNT]; int camera_use_count; struct v4l2_window overlay; struct { - unsigned int width; /* width */ - unsigned int height; /* height */ - unsigned int stride; /* stride */ - unsigned int buffersize; /* buffer size with padding */ - struct mmal_fmt *fmt; + unsigned int width; /* width */ + unsigned int height; /* height */ + unsigned int stride; /* stride */ + unsigned int buffersize; /* buffer size with padding */ + struct mmal_fmt *fmt; struct v4l2_fract timeperframe; /* H264 encode bitrate */ - int encode_bitrate; + int encode_bitrate; /* H264 bitrate mode. CBR/VBR */ - int encode_bitrate_mode; + int encode_bitrate_mode; /* H264 profile */ enum v4l2_mpeg_video_h264_profile enc_profile; /* H264 level */ enum v4l2_mpeg_video_h264_level enc_level; /* JPEG Q-factor */ - int q_factor; + int q_factor; - struct vb2_queue vb_vidq; + struct vb2_queue vb_vidq; /* VC start timestamp for streaming */ - s64 vc_start_timestamp; + s64 vc_start_timestamp; /* Kernel start timestamp for streaming */ ktime_t kernel_start_ts; /* Sequence number of last buffer */ - u32 sequence; + u32 sequence; - struct vchiq_mmal_port *port; /* port being used for capture */ + struct vchiq_mmal_port *port; /* port being used for capture */ /* camera port being used for capture */ - struct vchiq_mmal_port *camera_port; + struct vchiq_mmal_port *camera_port; /* component being used for encode */ struct vchiq_mmal_component *encode_component; /* number of frames remaining which driver should capture */ - unsigned int frame_count; + unsigned int frame_count; /* last frame completion */ - struct completion frame_cmplt; + struct completion frame_cmplt; } capture; diff --git a/drivers/staging/vc04_services/bcm2835-camera/controls.c b/drivers/staging/vc04_services/bcm2835-camera/controls.c index 5137fcf203d6..b096a12387f7 100644 --- a/drivers/staging/vc04_services/bcm2835-camera/controls.c +++ b/drivers/staging/vc04_services/bcm2835-camera/controls.c @@ -135,8 +135,8 @@ static const struct v4l2_to_mmal_effects_setting }; struct v4l2_mmal_scene_config { - enum v4l2_scene_mode v4l2_scene; - enum mmal_parameter_exposuremode exposure_mode; + enum v4l2_scene_mode v4l2_scene; + enum mmal_parameter_exposuremode exposure_mode; enum mmal_parameter_exposuremeteringmode metering_mode; }; @@ -377,11 +377,9 @@ static int ctrl_set_metering_mode(struct bm2835_mmal_dev *dev, dev->metering_mode = MMAL_PARAM_EXPOSUREMETERINGMODE_SPOT; break; - /* todo matrix weighting not added to Linux API till 3.9 - * case V4L2_EXPOSURE_METERING_MATRIX: - * dev->metering_mode = MMAL_PARAM_EXPOSUREMETERINGMODE_MATRIX; - * break; - */ + case V4L2_EXPOSURE_METERING_MATRIX: + dev->metering_mode = MMAL_PARAM_EXPOSUREMETERINGMODE_MATRIX; + break; } if (dev->scene_mode == V4L2_SCENE_MODE_NONE) { @@ -516,42 +514,41 @@ static int ctrl_set_image_effect(struct bm2835_mmal_dev *dev, struct mmal_parameter_imagefx_parameters imagefx; for (i = 0; i < ARRAY_SIZE(v4l2_to_mmal_effects_values); i++) { - if (ctrl->val == v4l2_to_mmal_effects_values[i].v4l2_effect) { - imagefx.effect = - v4l2_to_mmal_effects_values[i].mmal_effect; - imagefx.num_effect_params = - v4l2_to_mmal_effects_values[i].num_effect_params; + if (ctrl->val != v4l2_to_mmal_effects_values[i].v4l2_effect) + continue; - if (imagefx.num_effect_params > MMAL_MAX_IMAGEFX_PARAMETERS) - imagefx.num_effect_params = MMAL_MAX_IMAGEFX_PARAMETERS; + imagefx.effect = + v4l2_to_mmal_effects_values[i].mmal_effect; + imagefx.num_effect_params = + v4l2_to_mmal_effects_values[i].num_effect_params; - for (j = 0; j < imagefx.num_effect_params; j++) - imagefx.effect_parameter[j] = - v4l2_to_mmal_effects_values[i].effect_params[j]; + if (imagefx.num_effect_params > MMAL_MAX_IMAGEFX_PARAMETERS) + imagefx.num_effect_params = MMAL_MAX_IMAGEFX_PARAMETERS; - dev->colourfx.enable = - v4l2_to_mmal_effects_values[i].col_fx_enable; - if (!v4l2_to_mmal_effects_values[i].col_fx_fixed_cbcr) { - dev->colourfx.u = - v4l2_to_mmal_effects_values[i].u; - dev->colourfx.v = - v4l2_to_mmal_effects_values[i].v; - } + for (j = 0; j < imagefx.num_effect_params; j++) + imagefx.effect_parameter[j] = + v4l2_to_mmal_effects_values[i].effect_params[j]; - control = &dev->component[COMP_CAMERA]->control; - - ret = vchiq_mmal_port_parameter_set( - dev->instance, control, - MMAL_PARAMETER_IMAGE_EFFECT_PARAMETERS, - &imagefx, sizeof(imagefx)); - if (ret) - goto exit; - - ret = vchiq_mmal_port_parameter_set( - dev->instance, control, - MMAL_PARAMETER_COLOUR_EFFECT, - &dev->colourfx, sizeof(dev->colourfx)); + dev->colourfx.enable = + v4l2_to_mmal_effects_values[i].col_fx_enable; + if (!v4l2_to_mmal_effects_values[i].col_fx_fixed_cbcr) { + dev->colourfx.u = v4l2_to_mmal_effects_values[i].u; + dev->colourfx.v = v4l2_to_mmal_effects_values[i].v; } + + control = &dev->component[COMP_CAMERA]->control; + + ret = vchiq_mmal_port_parameter_set( + dev->instance, control, + MMAL_PARAMETER_IMAGE_EFFECT_PARAMETERS, + &imagefx, sizeof(imagefx)); + if (ret) + goto exit; + + ret = vchiq_mmal_port_parameter_set( + dev->instance, control, + MMAL_PARAMETER_COLOUR_EFFECT, + &dev->colourfx, sizeof(dev->colourfx)); } exit: @@ -841,8 +838,7 @@ static int ctrl_set_scene_mode(struct bm2835_mmal_dev *dev, enum mmal_parameter_exposuremeteringmode metering_mode; for (i = 0; i < ARRAY_SIZE(scene_configs); i++) { - if (scene_configs[i].v4l2_scene == - ctrl->val) { + if (scene_configs[i].v4l2_scene == ctrl->val) { scene = &scene_configs[i]; break; } @@ -1045,8 +1041,8 @@ static const struct bm2835_mmal_v4l2_ctrl v4l2_ctrls[V4L2_CTRL_COUNT] = { { .id = V4L2_CID_EXPOSURE_METERING, .type = MMAL_CONTROL_TYPE_STD_MENU, - .min = ~0x7, - .max = V4L2_EXPOSURE_METERING_SPOT, + .min = ~0xf, + .max = V4L2_EXPOSURE_METERING_MATRIX, .def = V4L2_EXPOSURE_METERING_AVERAGE, .step = 0, .imenu = NULL, @@ -1282,21 +1278,18 @@ int set_framerate_params(struct bm2835_mmal_dev *dev) struct mmal_parameter_fps_range fps_range; int ret; + fps_range.fps_high.num = dev->capture.timeperframe.denominator; + fps_range.fps_high.den = dev->capture.timeperframe.numerator; + if ((dev->exposure_mode_active != MMAL_PARAM_EXPOSUREMODE_OFF) && (dev->exp_auto_priority)) { - /* Variable FPS. Define min FPS as 1fps. - * Max as max defined FPS. - */ + /* Variable FPS. Define min FPS as 1fps. */ fps_range.fps_low.num = 1; fps_range.fps_low.den = 1; - fps_range.fps_high.num = dev->capture.timeperframe.denominator; - fps_range.fps_high.den = dev->capture.timeperframe.numerator; } else { /* Fixed FPS - set min and max to be the same */ - fps_range.fps_low.num = fps_range.fps_high.num = - dev->capture.timeperframe.denominator; - fps_range.fps_low.den = fps_range.fps_high.den = - dev->capture.timeperframe.numerator; + fps_range.fps_low.num = fps_range.fps_high.num; + fps_range.fps_low.den = fps_range.fps_high.den; } v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, diff --git a/drivers/staging/vc04_services/bcm2835-camera/mmal-common.h b/drivers/staging/vc04_services/bcm2835-camera/mmal-common.h index ff5398737b4a..ce88fac7c24b 100644 --- a/drivers/staging/vc04_services/bcm2835-camera/mmal-common.h +++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-common.h @@ -26,13 +26,13 @@ struct mmal_msg_context; /* mapping between v4l and mmal video modes */ struct mmal_fmt { - u32 fourcc; /* v4l2 format id */ - int flags; /* v4l2 flags field */ - u32 mmal; - int depth; - u32 mmal_component; /* MMAL component index to be used to encode */ - u32 ybbp; /* depth of first Y plane for planar formats */ - bool remove_padding; /* Does the GPU have to remove padding, + u32 fourcc; /* v4l2 format id */ + int flags; /* v4l2 flags field */ + u32 mmal; + int depth; + u32 mmal_component; /* MMAL component index to be used to encode */ + u32 ybbp; /* depth of first Y plane for planar formats */ + bool remove_padding; /* Does the GPU have to remove padding, * or can we do hide padding via bytesperline. */ }; @@ -40,10 +40,10 @@ struct mmal_fmt { /* buffer for one video frame */ struct mmal_buffer { /* v4l buffer data -- must be first */ - struct vb2_v4l2_buffer vb; + struct vb2_v4l2_buffer vb; /* list of buffers available */ - struct list_head list; + struct list_head list; void *buffer; /* buffer pointer */ unsigned long buffer_size; /* size of allocated buffer */ diff --git a/drivers/staging/vc04_services/bcm2835-camera/mmal-parameters.h b/drivers/staging/vc04_services/bcm2835-camera/mmal-parameters.h index 80a99128f5f3..f4ac5a6149ea 100644 --- a/drivers/staging/vc04_services/bcm2835-camera/mmal-parameters.h +++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-parameters.h @@ -724,11 +724,11 @@ struct mmal_parameter_imagefx_parameters { #define MMAL_PARAMETER_CAMERA_INFO_MAX_STR_LEN 16 struct mmal_parameter_camera_info_camera_t { - u32 port_id; - u32 max_width; - u32 max_height; - u32 lens_present; - u8 camera_name[MMAL_PARAMETER_CAMERA_INFO_MAX_STR_LEN]; + u32 port_id; + u32 max_width; + u32 max_height; + u32 lens_present; + u8 camera_name[MMAL_PARAMETER_CAMERA_INFO_MAX_STR_LEN]; }; enum mmal_parameter_camera_info_flash_type_t { @@ -744,8 +744,8 @@ struct mmal_parameter_camera_info_flash_t { }; struct mmal_parameter_camera_info_t { - u32 num_cameras; - u32 num_flashes; + u32 num_cameras; + u32 num_flashes; struct mmal_parameter_camera_info_camera_t cameras[MMAL_PARAMETER_CAMERA_INFO_MAX_CAMERAS]; struct mmal_parameter_camera_info_flash_t diff --git a/drivers/staging/vc04_services/interface/vchi/vchi.h b/drivers/staging/vc04_services/interface/vchi/vchi.h index ff2b960d8cac..1a981e98e82b 100644 --- a/drivers/staging/vc04_services/interface/vchi/vchi.h +++ b/drivers/staging/vc04_services/interface/vchi/vchi.h @@ -60,32 +60,18 @@ struct vchi_service_handle; * (local / remote) *****************************************************************************/ -#ifdef __cplusplus -extern "C" { -#endif - // Routine used to initialise the vchi on both local + remote connections extern int32_t vchi_initialise(struct vchi_instance_handle **instance_handle); -extern int32_t vchi_exit(void); - extern int32_t vchi_connect(struct vchi_instance_handle *instance_handle); //When this is called, ensure that all services have no data pending. //Bulk transfers can remain 'queued' extern int32_t vchi_disconnect(struct vchi_instance_handle *instance_handle); -// helper functions -extern void *vchi_allocate_buffer(struct vchi_service_handle *handle, uint32_t *length); -extern void vchi_free_buffer(struct vchi_service_handle *handle, void *address); -extern uint32_t vchi_current_time(struct vchi_instance_handle *instance_handle); - /****************************************************************************** * Global service API *****************************************************************************/ -// Routine to destroy a service -extern int32_t vchi_service_destroy(const struct vchi_service_handle *handle); - // Routine to open a named service extern int32_t vchi_service_open(struct vchi_instance_handle *instance_handle, struct service_creation *setup, @@ -103,23 +89,12 @@ extern int32_t vchi_service_use(const struct vchi_service_handle *handle); // Routine to decrement ref count on a named service extern int32_t vchi_service_release(const struct vchi_service_handle *handle); -// Routine to set a control option for a named service -extern int32_t vchi_service_set_option(const struct vchi_service_handle *handle, - enum vchi_service_option option, - int value); - /* Routine to send a message from kernel memory across a service */ extern int vchi_queue_kernel_message(struct vchi_service_handle *handle, void *data, unsigned int size); -/* Routine to send a message from user memory across a service */ -extern int -vchi_queue_user_message(struct vchi_service_handle *handle, - void __user *data, - unsigned int size); - // Routine to receive a msg from a service // Dequeue is equivalent to hold, copy into client buffer, release extern int32_t vchi_msg_dequeue(struct vchi_service_handle *handle, @@ -149,54 +124,14 @@ extern int32_t vchi_msg_hold(struct vchi_service_handle *handle, enum vchi_flags flags, struct vchi_held_msg *message_descriptor); -// Initialise an iterator to look through messages in place -extern int32_t vchi_msg_look_ahead(struct vchi_service_handle *handle, - struct vchi_msg_iter *iter, - enum vchi_flags flags); - /******************************************************************************* * Global service support API - operations on held messages * and message iterators ******************************************************************************/ -// Routine to get the address of a held message -extern void *vchi_held_msg_ptr(const struct vchi_held_msg *message); - -// Routine to get the size of a held message -extern int32_t vchi_held_msg_size(const struct vchi_held_msg *message); - -// Routine to get the transmit timestamp as written into the header by the peer -extern uint32_t vchi_held_msg_tx_timestamp(const struct vchi_held_msg *message); - -// Routine to get the reception timestamp, written as we parsed the header -extern uint32_t vchi_held_msg_rx_timestamp(const struct vchi_held_msg *message); - // Routine to release a held message after it has been processed extern int32_t vchi_held_msg_release(struct vchi_held_msg *message); -// Indicates whether the iterator has a next message. -extern int32_t vchi_msg_iter_has_next(const struct vchi_msg_iter *iter); - -// Return the pointer and length for the next message and advance the iterator. -extern int32_t vchi_msg_iter_next(struct vchi_msg_iter *iter, - void **data, - uint32_t *msg_size); - -// Remove the last message returned by vchi_msg_iter_next. -// Can only be called once after each call to vchi_msg_iter_next. -extern int32_t vchi_msg_iter_remove(struct vchi_msg_iter *iter); - -// Hold the last message returned by vchi_msg_iter_next. -// Can only be called once after each call to vchi_msg_iter_next. -extern int32_t vchi_msg_iter_hold(struct vchi_msg_iter *iter, - struct vchi_held_msg *message); - -// Return information for the next message, and hold it, advancing the iterator. -extern int32_t vchi_msg_iter_hold_next(struct vchi_msg_iter *iter, - void **data, // } may be NULL - uint32_t *msg_size, // } - struct vchi_held_msg *message); - /****************************************************************************** * Global bulk API *****************************************************************************/ @@ -208,13 +143,6 @@ extern int32_t vchi_bulk_queue_receive(struct vchi_service_handle *handle, enum vchi_flags flags, void *transfer_handle); -// Prepare interface for a transfer from the other side into relocatable memory. -int32_t vchi_bulk_queue_receive_reloc(const struct vchi_service_handle *handle, - uint32_t offset, - uint32_t data_size, - const enum vchi_flags flags, - void * const bulk_handle); - // Routine to queue up data ready for transfer to the other (once they have signalled they are ready) extern int32_t vchi_bulk_queue_transmit(struct vchi_service_handle *handle, const void *data_src, @@ -226,15 +154,6 @@ extern int32_t vchi_bulk_queue_transmit(struct vchi_service_handle *handle, * Configuration plumbing *****************************************************************************/ -#ifdef __cplusplus -} -#endif - -extern int32_t vchi_bulk_queue_transmit_reloc(struct vchi_service_handle *handle, - uint32_t offset, - uint32_t data_size, - enum vchi_flags flags, - void *transfer_handle); #endif /* VCHI_H_ */ /****************************** End of file **********************************/ diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c index c18c6ca0b6c0..38a13e4618a8 100644 --- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c +++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c @@ -371,14 +371,15 @@ create_pagelist(char __user *buf, size_t count, unsigned short type) pagelistinfo->scatterlist = scatterlist; pagelistinfo->scatterlist_mapped = 0; - if (is_vmalloc_addr(buf)) { + if (is_vmalloc_addr((void __force *)buf)) { unsigned long length = count; unsigned int off = offset; for (actual_pages = 0; actual_pages < num_pages; actual_pages++) { - struct page *pg = vmalloc_to_page(buf + (actual_pages * - PAGE_SIZE)); + struct page *pg = + vmalloc_to_page((void __force *)(buf + + (actual_pages * PAGE_SIZE))); size_t bytes = PAGE_SIZE - off; if (!pg) { diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c index a1ea9777a444..28ea8c3a4cba 100644 --- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c +++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c @@ -1209,7 +1209,9 @@ vchiq_ioctl(struct file *file, unsigned int cmd, unsigned long arg) /* The completion must point to the ** msgbuf. */ - completion->header = msgbuf; + completion->header = + (struct vchiq_header __force *) + msgbuf; } if ((completion->reason == @@ -2353,7 +2355,7 @@ vchiq_use_internal(struct vchiq_state *state, struct vchiq_service *service, enum vchiq_status ret = VCHIQ_SUCCESS; char entity[16]; int *entity_uc; - int local_uc, local_entity_uc; + int local_uc; if (!arm_state) goto out; @@ -2377,7 +2379,7 @@ vchiq_use_internal(struct vchiq_state *state, struct vchiq_service *service, write_lock_bh(&arm_state->susp_res_lock); local_uc = ++arm_state->videocore_use_count; - local_entity_uc = ++(*entity_uc); + ++(*entity_uc); vchiq_log_trace(vchiq_susp_log_level, "%s %s count %d, state count %d", diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_connected.c b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_connected.c index 1640906e3929..79b75efa6868 100644 --- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_connected.c +++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_connected.c @@ -14,12 +14,7 @@ static VCHIQ_CONNECTED_CALLBACK_T g_deferred_callback[MAX_CALLBACKS]; static int g_once_init; static struct mutex g_connected_mutex; -/**************************************************************************** -* -* Function to initialize our lock. -* -***************************************************************************/ - +/* Function to initialize our lock */ static void connected_init(void) { if (!g_once_init) { @@ -28,15 +23,12 @@ static void connected_init(void) } } -/**************************************************************************** -* -* This function is used to defer initialization until the vchiq stack is -* initialized. If the stack is already initialized, then the callback will -* be made immediately, otherwise it will be deferred until -* vchiq_call_connected_callbacks is called. -* -***************************************************************************/ - +/* + * This function is used to defer initialization until the vchiq stack is + * initialized. If the stack is already initialized, then the callback will + * be made immediately, otherwise it will be deferred until + * vchiq_call_connected_callbacks is called. + */ void vchiq_add_connected_callback(VCHIQ_CONNECTED_CALLBACK_T callback) { connected_init(); @@ -63,13 +55,10 @@ void vchiq_add_connected_callback(VCHIQ_CONNECTED_CALLBACK_T callback) mutex_unlock(&g_connected_mutex); } -/**************************************************************************** -* -* This function is called by the vchiq stack once it has been connected to -* the videocore and clients can start to use the stack. -* -***************************************************************************/ - +/* + * This function is called by the vchiq stack once it has been connected to + * the videocore and clients can start to use the stack. + */ void vchiq_call_connected_callbacks(void) { int i; diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c index edcd97373809..ae9183db44ee 100644 --- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c +++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c @@ -372,6 +372,10 @@ make_service_callback(struct vchiq_service *service, enum vchiq_reason reason, service->state->id, service->handle); status = VCHIQ_SUCCESS; } + + if (reason != VCHIQ_MESSAGE_AVAILABLE) + vchiq_release_message(service->handle, header); + return status; } @@ -1480,15 +1484,6 @@ parse_open(struct vchiq_state *state, struct vchiq_header *header) : VCHIQ_SRVSTATE_OPEN); } - service->remoteport = remoteport; - service->client_id = ((int *)header->data)[1]; - if (make_service_callback(service, VCHIQ_SERVICE_OPENED, - NULL, NULL) == VCHIQ_RETRY) { - /* Bail out if not ready */ - service->remoteport = VCHIQ_PORT_FREE; - goto bail_not_ready; - } - /* Success - the message has been dealt with */ unlock_service(service); return 1; @@ -3147,6 +3142,12 @@ error_exit: return status; } +enum vchiq_status vchiq_queue_kernel_message(unsigned int handle, void *context, + size_t size) +{ + return vchiq_queue_message(handle, memcpy_copy_callback, context, size); +} + void vchiq_release_message(unsigned int handle, struct vchiq_header *header) diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.h b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.h index cedd8e721aae..1fe6cd8b86c0 100644 --- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.h +++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.h @@ -587,6 +587,13 @@ lock_service(struct vchiq_service *service); extern void unlock_service(struct vchiq_service *service); +extern enum vchiq_status +vchiq_queue_message(unsigned int handle, + ssize_t (*copy_callback)(void *context, void *dest, + size_t offset, size_t maxsize), + void *context, + size_t size); + /* The following functions are called from vchiq_core, and external ** implementations must be provided. */ diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_if.h b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_if.h index 39b77ea19210..b62fd6d6f1ac 100644 --- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_if.h +++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_if.h @@ -105,12 +105,8 @@ extern enum vchiq_status vchiq_close_service(unsigned int service); extern enum vchiq_status vchiq_remove_service(unsigned int service); extern enum vchiq_status vchiq_use_service(unsigned int service); extern enum vchiq_status vchiq_release_service(unsigned int service); -extern enum vchiq_status -vchiq_queue_message(unsigned int handle, - ssize_t (*copy_callback)(void *context, void *dest, - size_t offset, size_t maxsize), - void *context, - size_t size); +extern enum vchiq_status vchiq_queue_kernel_message(unsigned int handle, + void *context, size_t size); extern void vchiq_release_message(unsigned int service, struct vchiq_header *header); extern enum vchiq_status vchiq_bulk_transmit(unsigned int service, diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_shim.c b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_shim.c index efdd3b1c7d85..75d87b6992c4 100644 --- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_shim.c +++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_shim.c @@ -9,8 +9,6 @@ #include "vchiq_util.h" -#define vchiq_status_to_vchi(status) ((int32_t)status) - struct shim_service { unsigned int handle; @@ -84,35 +82,15 @@ int32_t vchi_msg_remove(struct vchi_service_handle *handle) } EXPORT_SYMBOL(vchi_msg_remove); -/*********************************************************** - * Name: vchi_msg_queue - * - * Arguments: struct vchi_service_handle *handle, - * ssize_t (*copy_callback)(void *context, void *dest, - * size_t offset, size_t maxsize), - * void *context, - * uint32_t data_size - * - * Description: Thin wrapper to queue a message onto a connection - * - * Returns: int32_t - success == 0 - * - ***********************************************************/ -static -int32_t vchi_msg_queue(struct vchi_service_handle *handle, - ssize_t (*copy_callback)(void *context, void *dest, - size_t offset, size_t maxsize), - void *context, - uint32_t data_size) +int vchi_queue_kernel_message(struct vchi_service_handle *handle, void *data, + unsigned int size) { struct shim_service *service = (struct shim_service *)handle; enum vchiq_status status; while (1) { - status = vchiq_queue_message(service->handle, - copy_callback, - context, - data_size); + status = vchiq_queue_kernel_message(service->handle, data, + size); /* * vchiq_queue_message() may return VCHIQ_RETRY, so we need to @@ -125,65 +103,10 @@ int32_t vchi_msg_queue(struct vchi_service_handle *handle, msleep(1); } - return vchiq_status_to_vchi(status); -} - -static ssize_t -vchi_queue_kernel_message_callback(void *context, - void *dest, - size_t offset, - size_t maxsize) -{ - memcpy(dest, context + offset, maxsize); - return maxsize; -} - -int -vchi_queue_kernel_message(struct vchi_service_handle *handle, - void *data, - unsigned int size) -{ - return vchi_msg_queue(handle, - vchi_queue_kernel_message_callback, - data, - size); + return status; } EXPORT_SYMBOL(vchi_queue_kernel_message); -struct vchi_queue_user_message_context { - void __user *data; -}; - -static ssize_t -vchi_queue_user_message_callback(void *context, - void *dest, - size_t offset, - size_t maxsize) -{ - struct vchi_queue_user_message_context *copycontext = context; - - if (copy_from_user(dest, copycontext->data + offset, maxsize)) - return -EFAULT; - - return maxsize; -} - -int -vchi_queue_user_message(struct vchi_service_handle *handle, - void __user *data, - unsigned int size) -{ - struct vchi_queue_user_message_context copycontext = { - .data = data - }; - - return vchi_msg_queue(handle, - vchi_queue_user_message_callback, - ©context, - size); -} -EXPORT_SYMBOL(vchi_queue_user_message); - /*********************************************************** * Name: vchi_bulk_queue_receive * @@ -221,7 +144,7 @@ int32_t vchi_bulk_queue_receive(struct vchi_service_handle *handle, void *data_d break; default: WARN(1, "unsupported message\n"); - return vchiq_status_to_vchi(VCHIQ_ERROR); + return VCHIQ_ERROR; } while (1) { @@ -238,7 +161,7 @@ int32_t vchi_bulk_queue_receive(struct vchi_service_handle *handle, void *data_d msleep(1); } - return vchiq_status_to_vchi(status); + return status; } EXPORT_SYMBOL(vchi_bulk_queue_receive); @@ -282,7 +205,7 @@ int32_t vchi_bulk_queue_transmit(struct vchi_service_handle *handle, break; default: WARN(1, "unsupported message\n"); - return vchiq_status_to_vchi(VCHIQ_ERROR); + return VCHIQ_ERROR; } while (1) { @@ -300,7 +223,7 @@ int32_t vchi_bulk_queue_transmit(struct vchi_service_handle *handle, msleep(1); } - return vchiq_status_to_vchi(status); + return status; } EXPORT_SYMBOL(vchi_bulk_queue_transmit); @@ -447,7 +370,7 @@ int32_t vchi_initialise(struct vchi_instance_handle **instance_handle) *instance_handle = (struct vchi_instance_handle *)instance; - return vchiq_status_to_vchi(status); + return status; } EXPORT_SYMBOL(vchi_initialise); @@ -485,7 +408,7 @@ int32_t vchi_disconnect(struct vchi_instance_handle *instance_handle) { struct vchiq_instance *instance = (struct vchiq_instance *)instance_handle; - return vchiq_status_to_vchi(vchiq_shutdown(instance)); + return vchiq_shutdown(instance); } EXPORT_SYMBOL(vchi_disconnect); @@ -521,7 +444,7 @@ static enum vchiq_status shim_callback(enum vchiq_reason reason, service->callback(service->callback_param, VCHI_CALLBACK_MSG_AVAILABLE, NULL); - goto done; + break; case VCHIQ_BULK_TRANSMIT_DONE: service->callback(service->callback_param, @@ -538,10 +461,6 @@ static enum vchiq_status shim_callback(enum vchiq_reason reason, VCHI_CALLBACK_SERVICE_CLOSED, NULL); break; - case VCHIQ_SERVICE_OPENED: - /* No equivalent VCHI reason */ - break; - case VCHIQ_BULK_TRANSMIT_ABORTED: service->callback(service->callback_param, VCHI_CALLBACK_BULK_TRANSMIT_ABORTED, @@ -560,8 +479,6 @@ static enum vchiq_status shim_callback(enum vchiq_reason reason, } release: - vchiq_release_message(service->handle, header); -done: return VCHIQ_SUCCESS; } @@ -636,62 +553,12 @@ int32_t vchi_service_close(const struct vchi_service_handle *handle) if (status == VCHIQ_SUCCESS) service_free(service); - ret = vchiq_status_to_vchi(status); + ret = status; } return ret; } EXPORT_SYMBOL(vchi_service_close); -int32_t vchi_service_destroy(const struct vchi_service_handle *handle) -{ - int32_t ret = -1; - struct shim_service *service = (struct shim_service *)handle; - - if (service) { - enum vchiq_status status = vchiq_remove_service(service->handle); - - if (status == VCHIQ_SUCCESS) { - service_free(service); - service = NULL; - } - - ret = vchiq_status_to_vchi(status); - } - return ret; -} -EXPORT_SYMBOL(vchi_service_destroy); - -int32_t vchi_service_set_option(const struct vchi_service_handle *handle, - enum vchi_service_option option, - int value) -{ - int32_t ret = -1; - struct shim_service *service = (struct shim_service *)handle; - enum vchiq_service_option vchiq_option; - - switch (option) { - case VCHI_SERVICE_OPTION_TRACE: - vchiq_option = VCHIQ_SERVICE_OPTION_TRACE; - break; - case VCHI_SERVICE_OPTION_SYNCHRONOUS: - vchiq_option = VCHIQ_SERVICE_OPTION_SYNCHRONOUS; - break; - default: - service = NULL; - break; - } - if (service) { - enum vchiq_status status = - vchiq_set_service_option(service->handle, - vchiq_option, - value); - - ret = vchiq_status_to_vchi(status); - } - return ret; -} -EXPORT_SYMBOL(vchi_service_set_option); - int32_t vchi_get_peer_version(const struct vchi_service_handle *handle, short *peer_version) { int32_t ret = -1; @@ -701,7 +568,7 @@ int32_t vchi_get_peer_version(const struct vchi_service_handle *handle, short *p enum vchiq_status status; status = vchiq_get_peer_version(service->handle, peer_version); - ret = vchiq_status_to_vchi(status); + ret = status; } return ret; } @@ -723,7 +590,7 @@ int32_t vchi_service_use(const struct vchi_service_handle *handle) struct shim_service *service = (struct shim_service *)handle; if (service) - ret = vchiq_status_to_vchi(vchiq_use_service(service->handle)); + ret = vchiq_use_service(service->handle); return ret; } EXPORT_SYMBOL(vchi_service_use); @@ -744,8 +611,7 @@ int32_t vchi_service_release(const struct vchi_service_handle *handle) struct shim_service *service = (struct shim_service *)handle; if (service) - ret = vchiq_status_to_vchi( - vchiq_release_service(service->handle)); + ret = vchiq_release_service(service->handle); return ret; } EXPORT_SYMBOL(vchi_service_release); diff --git a/drivers/staging/vt6655/Makefile b/drivers/staging/vt6655/Makefile index a151f30fc46f..e70357ec0af8 100644 --- a/drivers/staging/vt6655/Makefile +++ b/drivers/staging/vt6655/Makefile @@ -1,7 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 -# TODO: all of these should be removed -ccflags-y := -DLINUX -D__KERNEL__ -D__NO_VERSION__ -ccflags-y += -DHOSTAP vt6655_stage-y += device_main.o \ card.o \ diff --git a/drivers/staging/vt6655/baseband.c b/drivers/staging/vt6655/baseband.c index b4cdc0b7fee7..6b25d75d2501 100644 --- a/drivers/staging/vt6655/baseband.c +++ b/drivers/staging/vt6655/baseband.c @@ -12,12 +12,10 @@ * Date: Aug.22, 2002 * * Functions: - * BBuGetFrameTime - Calculate data frame transmitting time - * BBvCalculateParameter - Calculate PhyLength, PhyService and Phy Signal - * parameter for baseband Tx - * BBbReadEmbedded - Embedded read baseband register via MAC - * BBbWriteEmbedded - Embedded write baseband register via MAC - * BBbVT3253Init - VIA VT3253 baseband chip init code + * bb_get_frame_time - Calculate data frame transmitting time + * bb_read_embedded - Embedded read baseband register via MAC + * bb_write_embedded - Embedded write baseband register via MAC + * bb_vt3253_init - VIA VT3253 baseband chip init code * * Revision History: * 06-10-2003 Bryan YC Fan: Re-write codes to support VT3253 spec. @@ -1695,53 +1693,53 @@ static const unsigned short awcFrameTime[MAX_RATE] = { * * Parameters: * In: - * byPreambleType - Preamble Type - * byPktType - PK_TYPE_11A, PK_TYPE_11B, PK_TYPE_11GB, PK_TYPE_11GA - * cbFrameLength - Baseband Type - * wRate - Tx Rate + * by_preamble_type - Preamble Type + * by_pkt_type - PK_TYPE_11A, PK_TYPE_11B, PK_TYPE_11GB, PK_TYPE_11GA + * cb_frame_length - Baseband Type + * tx_rate - Tx Rate * Out: * * Return Value: FrameTime * */ -unsigned int BBuGetFrameTime(unsigned char byPreambleType, - unsigned char byPktType, - unsigned int cbFrameLength, unsigned short wRate) +unsigned int bb_get_frame_time(unsigned char by_preamble_type, + unsigned char by_pkt_type, + unsigned int cb_frame_length, + unsigned short tx_rate) { - unsigned int uFrameTime; - unsigned int uPreamble; - unsigned int uTmp; - unsigned int uRateIdx = (unsigned int)wRate; - unsigned int uRate = 0; + unsigned int frame_time; + unsigned int preamble; + unsigned int tmp; + unsigned int rate_idx = (unsigned int)tx_rate; + unsigned int rate = 0; - if (uRateIdx > RATE_54M) + if (rate_idx > RATE_54M) return 0; - uRate = (unsigned int)awcFrameTime[uRateIdx]; + rate = (unsigned int)awcFrameTime[rate_idx]; - if (uRateIdx <= 3) { /* CCK mode */ - if (byPreambleType == 1) /* Short */ - uPreamble = 96; + if (rate_idx <= 3) { /* CCK mode */ + if (by_preamble_type == 1) /* Short */ + preamble = 96; else - uPreamble = 192; + preamble = 192; + frame_time = (cb_frame_length * 80) / rate; /* ????? */ + tmp = (frame_time * rate) / 80; + if (cb_frame_length != tmp) + frame_time++; - uFrameTime = (cbFrameLength * 80) / uRate; /* ????? */ - uTmp = (uFrameTime * uRate) / 80; - if (cbFrameLength != uTmp) - uFrameTime++; - - return uPreamble + uFrameTime; + return preamble + frame_time; } - uFrameTime = (cbFrameLength * 8 + 22) / uRate; /* ???????? */ - uTmp = ((uFrameTime * uRate) - 22) / 8; - if (cbFrameLength != uTmp) - uFrameTime++; + frame_time = (cb_frame_length * 8 + 22) / rate; /* ???????? */ + tmp = ((frame_time * rate) - 22) / 8; + if (cb_frame_length != tmp) + frame_time++; - uFrameTime = uFrameTime * 4; /* ??????? */ - if (byPktType != PK_TYPE_11A) - uFrameTime += 6; /* ?????? */ + frame_time = frame_time * 4; /* ??????? */ + if (by_pkt_type != PK_TYPE_11A) + frame_time += 6; /* ?????? */ - return 20 + uFrameTime; /* ?????? */ + return 20 + frame_time; /* ?????? */ } /* @@ -1899,34 +1897,34 @@ void vnt_get_phy_field(struct vnt_private *priv, u32 frame_length, * Parameters: * In: * iobase - I/O base address - * byBBAddr - address of register in Baseband + * by_bb_addr - address of register in Baseband * Out: - * pbyData - data read + * pby_data - data read * * Return Value: true if succeeded; false if failed. * */ -bool BBbReadEmbedded(struct vnt_private *priv, - unsigned char byBBAddr, unsigned char *pbyData) +bool bb_read_embedded(struct vnt_private *priv, unsigned char by_bb_addr, + unsigned char *pby_data) { void __iomem *iobase = priv->PortOffset; unsigned short ww; - unsigned char byValue; + unsigned char by_value; /* BB reg offset */ - VNSvOutPortB(iobase + MAC_REG_BBREGADR, byBBAddr); + VNSvOutPortB(iobase + MAC_REG_BBREGADR, by_bb_addr); /* turn on REGR */ MACvRegBitsOn(iobase, MAC_REG_BBREGCTL, BBREGCTL_REGR); /* W_MAX_TIMEOUT is the timeout period */ for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { - VNSvInPortB(iobase + MAC_REG_BBREGCTL, &byValue); - if (byValue & BBREGCTL_DONE) + VNSvInPortB(iobase + MAC_REG_BBREGCTL, &by_value); + if (by_value & BBREGCTL_DONE) break; } /* get BB data */ - VNSvInPortB(iobase + MAC_REG_BBREGDATA, pbyData); + VNSvInPortB(iobase + MAC_REG_BBREGDATA, pby_data); if (ww == W_MAX_TIMEOUT) { pr_debug(" DBG_PORT80(0x30)\n"); @@ -1941,32 +1939,32 @@ bool BBbReadEmbedded(struct vnt_private *priv, * Parameters: * In: * iobase - I/O base address - * byBBAddr - address of register in Baseband - * byData - data to write + * by_bb_addr - address of register in Baseband + * by_data - data to write * Out: * none * * Return Value: true if succeeded; false if failed. * */ -bool BBbWriteEmbedded(struct vnt_private *priv, - unsigned char byBBAddr, unsigned char byData) +bool bb_write_embedded(struct vnt_private *priv, unsigned char by_bb_addr, + unsigned char by_data) { void __iomem *iobase = priv->PortOffset; unsigned short ww; - unsigned char byValue; + unsigned char by_value; /* BB reg offset */ - VNSvOutPortB(iobase + MAC_REG_BBREGADR, byBBAddr); + VNSvOutPortB(iobase + MAC_REG_BBREGADR, by_bb_addr); /* set BB data */ - VNSvOutPortB(iobase + MAC_REG_BBREGDATA, byData); + VNSvOutPortB(iobase + MAC_REG_BBREGDATA, by_data); /* turn on BBREGCTL_REGW */ MACvRegBitsOn(iobase, MAC_REG_BBREGCTL, BBREGCTL_REGW); /* W_MAX_TIMEOUT is the timeout period */ for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { - VNSvInPortB(iobase + MAC_REG_BBREGCTL, &byValue); - if (byValue & BBREGCTL_DONE) + VNSvInPortB(iobase + MAC_REG_BBREGCTL, &by_value); + if (by_value & BBREGCTL_DONE) break; } @@ -1992,29 +1990,29 @@ bool BBbWriteEmbedded(struct vnt_private *priv, * */ -bool BBbVT3253Init(struct vnt_private *priv) +bool bb_vt3253_init(struct vnt_private *priv) { - bool bResult = true; + bool result = true; int ii; void __iomem *iobase = priv->PortOffset; - unsigned char byRFType = priv->byRFType; - unsigned char byLocalID = priv->byLocalID; + unsigned char by_rf_type = priv->byRFType; + unsigned char by_local_id = priv->byLocalID; - if (byRFType == RF_RFMD2959) { - if (byLocalID <= REV_ID_VT3253_A1) { + if (by_rf_type == RF_RFMD2959) { + if (by_local_id <= REV_ID_VT3253_A1) { for (ii = 0; ii < CB_VT3253_INIT_FOR_RFMD; ii++) - bResult &= BBbWriteEmbedded(priv, + result &= bb_write_embedded(priv, byVT3253InitTab_RFMD[ii][0], byVT3253InitTab_RFMD[ii][1]); } else { for (ii = 0; ii < CB_VT3253B0_INIT_FOR_RFMD; ii++) - bResult &= BBbWriteEmbedded(priv, + result &= bb_write_embedded(priv, byVT3253B0_RFMD[ii][0], byVT3253B0_RFMD[ii][1]); for (ii = 0; ii < CB_VT3253B0_AGC_FOR_RFMD2959; ii++) - bResult &= BBbWriteEmbedded(priv, + result &= bb_write_embedded(priv, byVT3253B0_AGC4_RFMD2959[ii][0], byVT3253B0_AGC4_RFMD2959[ii][1]); @@ -2029,14 +2027,14 @@ bool BBbVT3253Init(struct vnt_private *priv) priv->ldBmThreshold[1] = -50; priv->ldBmThreshold[2] = 0; priv->ldBmThreshold[3] = 0; - } else if ((byRFType == RF_AIROHA) || (byRFType == RF_AL2230S)) { + } else if ((by_rf_type == RF_AIROHA) || (by_rf_type == RF_AL2230S)) { for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++) - bResult &= BBbWriteEmbedded(priv, + result &= bb_write_embedded(priv, byVT3253B0_AIROHA2230[ii][0], byVT3253B0_AIROHA2230[ii][1]); for (ii = 0; ii < CB_VT3253B0_AGC; ii++) - bResult &= BBbWriteEmbedded(priv, + result &= bb_write_embedded(priv, byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]); priv->abyBBVGA[0] = 0x1C; @@ -2047,14 +2045,14 @@ bool BBbVT3253Init(struct vnt_private *priv) priv->ldBmThreshold[1] = -48; priv->ldBmThreshold[2] = 0; priv->ldBmThreshold[3] = 0; - } else if (byRFType == RF_UW2451) { + } else if (by_rf_type == RF_UW2451) { for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++) - bResult &= BBbWriteEmbedded(priv, + result &= bb_write_embedded(priv, byVT3253B0_UW2451[ii][0], byVT3253B0_UW2451[ii][1]); for (ii = 0; ii < CB_VT3253B0_AGC; ii++) - bResult &= BBbWriteEmbedded(priv, + result &= bb_write_embedded(priv, byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]); @@ -2069,9 +2067,9 @@ bool BBbVT3253Init(struct vnt_private *priv) priv->ldBmThreshold[1] = -50; priv->ldBmThreshold[2] = 0; priv->ldBmThreshold[3] = 0; - } else if (byRFType == RF_UW2452) { + } else if (by_rf_type == RF_UW2452) { for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++) - bResult &= BBbWriteEmbedded(priv, + result &= bb_write_embedded(priv, byVT3253B0_UW2451[ii][0], byVT3253B0_UW2451[ii][1]); @@ -2080,7 +2078,7 @@ bool BBbVT3253Init(struct vnt_private *priv) * 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted) */ - /*bResult &= BBbWriteEmbedded(iobase,0x09,0x41);*/ + /*bResult &= bb_write_embedded(iobase,0x09,0x41);*/ /* Init ANT B select, * RX Config CR10 = 0x28->0x2A, @@ -2088,23 +2086,23 @@ bool BBbVT3253Init(struct vnt_private *priv) * make the ANT_A, ANT_B inverted) */ - /*bResult &= BBbWriteEmbedded(iobase,0x0a,0x28);*/ + /*bResult &= bb_write_embedded(iobase,0x0a,0x28);*/ /* Select VC1/VC2, CR215 = 0x02->0x06 */ - bResult &= BBbWriteEmbedded(priv, 0xd7, 0x06); + result &= bb_write_embedded(priv, 0xd7, 0x06); /* {{RobertYu:20050125, request by Jack */ - bResult &= BBbWriteEmbedded(priv, 0x90, 0x20); - bResult &= BBbWriteEmbedded(priv, 0x97, 0xeb); + result &= bb_write_embedded(priv, 0x90, 0x20); + result &= bb_write_embedded(priv, 0x97, 0xeb); /* }} */ /* {{RobertYu:20050221, request by Jack */ - bResult &= BBbWriteEmbedded(priv, 0xa6, 0x00); - bResult &= BBbWriteEmbedded(priv, 0xa8, 0x30); + result &= bb_write_embedded(priv, 0xa6, 0x00); + result &= bb_write_embedded(priv, 0xa8, 0x30); /* }} */ - bResult &= BBbWriteEmbedded(priv, 0xb0, 0x58); + result &= bb_write_embedded(priv, 0xb0, 0x58); for (ii = 0; ii < CB_VT3253B0_AGC; ii++) - bResult &= BBbWriteEmbedded(priv, + result &= bb_write_embedded(priv, byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]); priv->abyBBVGA[0] = 0x14; @@ -2117,14 +2115,14 @@ bool BBbVT3253Init(struct vnt_private *priv) priv->ldBmThreshold[3] = 0; /* }} RobertYu */ - } else if (byRFType == RF_VT3226) { + } else if (by_rf_type == RF_VT3226) { for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++) - bResult &= BBbWriteEmbedded(priv, + result &= bb_write_embedded(priv, byVT3253B0_AIROHA2230[ii][0], byVT3253B0_AIROHA2230[ii][1]); for (ii = 0; ii < CB_VT3253B0_AGC; ii++) - bResult &= BBbWriteEmbedded(priv, + result &= bb_write_embedded(priv, byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]); priv->abyBBVGA[0] = 0x1C; @@ -2138,9 +2136,9 @@ bool BBbVT3253Init(struct vnt_private *priv) /* Fix VT3226 DFC system timing issue */ MACvSetRFLE_LatchBase(iobase); /* {{ RobertYu: 20050104 */ - } else if (byRFType == RF_AIROHA7230) { + } else if (by_rf_type == RF_AIROHA7230) { for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++) - bResult &= BBbWriteEmbedded(priv, + result &= bb_write_embedded(priv, byVT3253B0_AIROHA2230[ii][0], byVT3253B0_AIROHA2230[ii][1]); @@ -2148,17 +2146,17 @@ bool BBbVT3253Init(struct vnt_private *priv) /* Init ANT B select,TX Config CR09 = 0x61->0x45, * 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted) */ - /*bResult &= BBbWriteEmbedded(iobase,0x09,0x41);*/ + /* bResult &= bb_write_embedded(iobase,0x09,0x41);*/ /* Init ANT B select,RX Config CR10 = 0x28->0x2A, * 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted) */ - /*bResult &= BBbWriteEmbedded(iobase,0x0a,0x28);*/ + /* bResult &= BBbWriteEmbedded(iobase,0x0a,0x28);*/ /* Select VC1/VC2, CR215 = 0x02->0x06 */ - bResult &= BBbWriteEmbedded(priv, 0xd7, 0x06); + result &= bb_write_embedded(priv, 0xd7, 0x06); /* }} */ for (ii = 0; ii < CB_VT3253B0_AGC; ii++) - bResult &= BBbWriteEmbedded(priv, + result &= bb_write_embedded(priv, byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]); priv->abyBBVGA[0] = 0x1C; @@ -2176,12 +2174,12 @@ bool BBbVT3253Init(struct vnt_private *priv) priv->abyBBVGA[0] = 0x1C; } - if (byLocalID > REV_ID_VT3253_A1) { - BBbWriteEmbedded(priv, 0x04, 0x7F); - BBbWriteEmbedded(priv, 0x0D, 0x01); + if (by_local_id > REV_ID_VT3253_A1) { + bb_write_embedded(priv, 0x04, 0x7F); + bb_write_embedded(priv, 0x0D, 0x01); } - return bResult; + return result; } /* @@ -2197,42 +2195,42 @@ bool BBbVT3253Init(struct vnt_private *priv) * */ void -BBvSetShortSlotTime(struct vnt_private *priv) +bb_set_short_slot_time(struct vnt_private *priv) { - unsigned char byBBRxConf = 0; - unsigned char byBBVGA = 0; + unsigned char by_bb_rx_conf = 0; + unsigned char by_bb_vga = 0; - BBbReadEmbedded(priv, 0x0A, &byBBRxConf); /* CR10 */ + bb_read_embedded(priv, 0x0A, &by_bb_rx_conf); /* CR10 */ if (priv->bShortSlotTime) - byBBRxConf &= 0xDF; /* 1101 1111 */ + by_bb_rx_conf &= 0xDF; /* 1101 1111 */ else - byBBRxConf |= 0x20; /* 0010 0000 */ + by_bb_rx_conf |= 0x20; /* 0010 0000 */ /* patch for 3253B0 Baseband with Cardbus module */ - BBbReadEmbedded(priv, 0xE7, &byBBVGA); - if (byBBVGA == priv->abyBBVGA[0]) - byBBRxConf |= 0x20; /* 0010 0000 */ + bb_read_embedded(priv, 0xE7, &by_bb_vga); + if (by_bb_vga == priv->abyBBVGA[0]) + by_bb_rx_conf |= 0x20; /* 0010 0000 */ - BBbWriteEmbedded(priv, 0x0A, byBBRxConf); /* CR10 */ + bb_write_embedded(priv, 0x0A, by_bb_rx_conf); /* CR10 */ } -void BBvSetVGAGainOffset(struct vnt_private *priv, unsigned char byData) +void bb_set_vga_gain_offset(struct vnt_private *priv, unsigned char by_data) { - unsigned char byBBRxConf = 0; + unsigned char by_bb_rx_conf = 0; - BBbWriteEmbedded(priv, 0xE7, byData); + bb_write_embedded(priv, 0xE7, by_data); - BBbReadEmbedded(priv, 0x0A, &byBBRxConf); /* CR10 */ + bb_read_embedded(priv, 0x0A, &by_bb_rx_conf); /* CR10 */ /* patch for 3253B0 Baseband with Cardbus module */ - if (byData == priv->abyBBVGA[0]) - byBBRxConf |= 0x20; /* 0010 0000 */ + if (by_data == priv->abyBBVGA[0]) + by_bb_rx_conf |= 0x20; /* 0010 0000 */ else if (priv->bShortSlotTime) - byBBRxConf &= 0xDF; /* 1101 1111 */ + by_bb_rx_conf &= 0xDF; /* 1101 1111 */ else - byBBRxConf |= 0x20; /* 0010 0000 */ - priv->byBBVGACurrent = byData; - BBbWriteEmbedded(priv, 0x0A, byBBRxConf); /* CR10 */ + by_bb_rx_conf |= 0x20; /* 0010 0000 */ + priv->byBBVGACurrent = by_data; + bb_write_embedded(priv, 0x0A, by_bb_rx_conf); /* CR10 */ } /* @@ -2248,12 +2246,12 @@ void BBvSetVGAGainOffset(struct vnt_private *priv, unsigned char byData) * */ void -BBvSoftwareReset(struct vnt_private *priv) +bb_software_reset(struct vnt_private *priv) { - BBbWriteEmbedded(priv, 0x50, 0x40); - BBbWriteEmbedded(priv, 0x50, 0); - BBbWriteEmbedded(priv, 0x9C, 0x01); - BBbWriteEmbedded(priv, 0x9C, 0); + bb_write_embedded(priv, 0x50, 0x40); + bb_write_embedded(priv, 0x50, 0); + bb_write_embedded(priv, 0x9C, 0x01); + bb_write_embedded(priv, 0x9C, 0); } /* @@ -2269,13 +2267,13 @@ BBvSoftwareReset(struct vnt_private *priv) * */ void -BBvPowerSaveModeON(struct vnt_private *priv) +bb_power_save_mode_on(struct vnt_private *priv) { - unsigned char byOrgData; + unsigned char by_org_data; - BBbReadEmbedded(priv, 0x0D, &byOrgData); - byOrgData |= BIT(0); - BBbWriteEmbedded(priv, 0x0D, byOrgData); + bb_read_embedded(priv, 0x0D, &by_org_data); + by_org_data |= BIT(0); + bb_write_embedded(priv, 0x0D, by_org_data); } /* @@ -2291,13 +2289,13 @@ BBvPowerSaveModeON(struct vnt_private *priv) * */ void -BBvPowerSaveModeOFF(struct vnt_private *priv) +bb_power_save_mode_off(struct vnt_private *priv) { - unsigned char byOrgData; + unsigned char by_org_data; - BBbReadEmbedded(priv, 0x0D, &byOrgData); - byOrgData &= ~(BIT(0)); - BBbWriteEmbedded(priv, 0x0D, byOrgData); + bb_read_embedded(priv, 0x0D, &by_org_data); + by_org_data &= ~(BIT(0)); + bb_write_embedded(priv, 0x0D, by_org_data); } /* @@ -2306,7 +2304,7 @@ BBvPowerSaveModeOFF(struct vnt_private *priv) * Parameters: * In: * priv - Device Structure - * byAntennaMode - Antenna Mode + * by_antenna_mode - Antenna Mode * Out: * none * @@ -2315,22 +2313,22 @@ BBvPowerSaveModeOFF(struct vnt_private *priv) */ void -BBvSetTxAntennaMode(struct vnt_private *priv, unsigned char byAntennaMode) +bb_set_tx_antenna_mode(struct vnt_private *priv, unsigned char by_antenna_mode) { - unsigned char byBBTxConf; + unsigned char by_bb_tx_conf; - BBbReadEmbedded(priv, 0x09, &byBBTxConf); /* CR09 */ - if (byAntennaMode == ANT_DIVERSITY) { + bb_read_embedded(priv, 0x09, &by_bb_tx_conf); /* CR09 */ + if (by_antenna_mode == ANT_DIVERSITY) { /* bit 1 is diversity */ - byBBTxConf |= 0x02; - } else if (byAntennaMode == ANT_A) { + by_bb_tx_conf |= 0x02; + } else if (by_antenna_mode == ANT_A) { /* bit 2 is ANTSEL */ - byBBTxConf &= 0xF9; /* 1111 1001 */ - } else if (byAntennaMode == ANT_B) { - byBBTxConf &= 0xFD; /* 1111 1101 */ - byBBTxConf |= 0x04; + by_bb_tx_conf &= 0xF9; /* 1111 1001 */ + } else if (by_antenna_mode == ANT_B) { + by_bb_tx_conf &= 0xFD; /* 1111 1101 */ + by_bb_tx_conf |= 0x04; } - BBbWriteEmbedded(priv, 0x09, byBBTxConf); /* CR09 */ + bb_write_embedded(priv, 0x09, by_bb_tx_conf); /* CR09 */ } /* @@ -2339,7 +2337,7 @@ BBvSetTxAntennaMode(struct vnt_private *priv, unsigned char byAntennaMode) * Parameters: * In: * priv - Device Structure - * byAntennaMode - Antenna Mode + * by_antenna_mode - Antenna Mode * Out: * none * @@ -2348,25 +2346,25 @@ BBvSetTxAntennaMode(struct vnt_private *priv, unsigned char byAntennaMode) */ void -BBvSetRxAntennaMode(struct vnt_private *priv, unsigned char byAntennaMode) +bb_set_rx_antenna_mode(struct vnt_private *priv, unsigned char by_antenna_mode) { - unsigned char byBBRxConf; + unsigned char by_bb_rx_conf; - BBbReadEmbedded(priv, 0x0A, &byBBRxConf); /* CR10 */ - if (byAntennaMode == ANT_DIVERSITY) { - byBBRxConf |= 0x01; + bb_read_embedded(priv, 0x0A, &by_bb_rx_conf); /* CR10 */ + if (by_antenna_mode == ANT_DIVERSITY) { + by_bb_rx_conf |= 0x01; - } else if (byAntennaMode == ANT_A) { - byBBRxConf &= 0xFC; /* 1111 1100 */ - } else if (byAntennaMode == ANT_B) { - byBBRxConf &= 0xFE; /* 1111 1110 */ - byBBRxConf |= 0x02; + } else if (by_antenna_mode == ANT_A) { + by_bb_rx_conf &= 0xFC; /* 1111 1100 */ + } else if (by_antenna_mode == ANT_B) { + by_bb_rx_conf &= 0xFE; /* 1111 1110 */ + by_bb_rx_conf |= 0x02; } - BBbWriteEmbedded(priv, 0x0A, byBBRxConf); /* CR10 */ + bb_write_embedded(priv, 0x0A, by_bb_rx_conf); /* CR10 */ } /* - * Description: BBvSetDeepSleep + * Description: bb_set_deep_sleep * * Parameters: * In: @@ -2378,15 +2376,9 @@ BBvSetRxAntennaMode(struct vnt_private *priv, unsigned char byAntennaMode) * */ void -BBvSetDeepSleep(struct vnt_private *priv, unsigned char byLocalID) +bb_set_deep_sleep(struct vnt_private *priv, unsigned char by_local_id) { - BBbWriteEmbedded(priv, 0x0C, 0x17); /* CR12 */ - BBbWriteEmbedded(priv, 0x0D, 0xB9); /* CR13 */ + bb_write_embedded(priv, 0x0C, 0x17); /* CR12 */ + bb_write_embedded(priv, 0x0D, 0xB9); /* CR13 */ } -void -BBvExitDeepSleep(struct vnt_private *priv, unsigned char byLocalID) -{ - BBbWriteEmbedded(priv, 0x0C, 0x00); /* CR12 */ - BBbWriteEmbedded(priv, 0x0D, 0x01); /* CR13 */ -} diff --git a/drivers/staging/vt6655/baseband.h b/drivers/staging/vt6655/baseband.h index 0cc2e07829c5..9354ce724446 100644 --- a/drivers/staging/vt6655/baseband.h +++ b/drivers/staging/vt6655/baseband.h @@ -46,30 +46,31 @@ #define TOP_RATE_2M 0x00200000 #define TOP_RATE_1M 0x00100000 -unsigned int BBuGetFrameTime(unsigned char byPreambleType, - unsigned char byPktType, - unsigned int cbFrameLength, - unsigned short wRate); +unsigned int bb_get_frame_time(unsigned char by_preamble_type, + unsigned char by_pkt_type, + unsigned int cb_frame_length, + unsigned short w_rate); void vnt_get_phy_field(struct vnt_private *priv, u32 frame_length, u16 tx_rate, u8 pkt_type, struct vnt_phy_field *phy); -bool BBbReadEmbedded(struct vnt_private *priv, unsigned char byBBAddr, - unsigned char *pbyData); -bool BBbWriteEmbedded(struct vnt_private *priv, unsigned char byBBAddr, - unsigned char byData); +bool bb_read_embedded(struct vnt_private *priv, unsigned char by_bb_addr, + unsigned char *pby_data); +bool bb_write_embedded(struct vnt_private *priv, unsigned char by_bb_addr, + unsigned char by_data); -void BBvSetShortSlotTime(struct vnt_private *priv); -void BBvSetVGAGainOffset(struct vnt_private *priv, unsigned char byData); +void bb_set_short_slot_time(struct vnt_private *priv); +void bb_set_vga_gain_offset(struct vnt_private *priv, unsigned char by_data); /* VT3253 Baseband */ -bool BBbVT3253Init(struct vnt_private *priv); -void BBvSoftwareReset(struct vnt_private *priv); -void BBvPowerSaveModeON(struct vnt_private *priv); -void BBvPowerSaveModeOFF(struct vnt_private *priv); -void BBvSetTxAntennaMode(struct vnt_private *priv, unsigned char byAntennaMode); -void BBvSetRxAntennaMode(struct vnt_private *priv, unsigned char byAntennaMode); -void BBvSetDeepSleep(struct vnt_private *priv, unsigned char byLocalID); -void BBvExitDeepSleep(struct vnt_private *priv, unsigned char byLocalID); +bool bb_vt3253_init(struct vnt_private *priv); +void bb_software_reset(struct vnt_private *priv); +void bb_power_save_mode_on(struct vnt_private *priv); +void bb_power_save_mode_off(struct vnt_private *priv); +void bb_set_tx_antenna_mode(struct vnt_private *priv, + unsigned char by_antenna_mode); +void bb_set_rx_antenna_mode(struct vnt_private *priv, + unsigned char by_antenna_mode); +void bb_set_deep_sleep(struct vnt_private *priv, unsigned char by_local_id); #endif /* __BASEBAND_H__ */ diff --git a/drivers/staging/vt6655/card.c b/drivers/staging/vt6655/card.c index e65c9825ea5a..6148310c06d6 100644 --- a/drivers/staging/vt6655/card.c +++ b/drivers/staging/vt6655/card.c @@ -11,15 +11,12 @@ * CARDvUpdateBasicTopRate - Update BasicTopRate * CARDbAddBasicRate - Add to BasicRateSet * CARDbIsOFDMinBasicRate - Check if any OFDM rate is in BasicRateSet - * CARDvSetLoopbackMode - Set Loopback mode - * CARDbSoftwareReset - Sortware reset NIC * CARDqGetTSFOffset - Calculate TSFOffset * CARDbGetCurrentTSF - Read Current NIC TSF counter * CARDqGetNextTBTT - Calculate Next Beacon TSF counter * CARDvSetFirstNextTBTT - Set NIC Beacon time * CARDvUpdateNextTBTT - Sync. NIC Beacon time * CARDbRadioPowerOff - Turn Off NIC Radio Power - * CARDbRadioPowerOn - Turn On NIC Radio Power * * Revision History: * 06-10-2003 Bryan YC Fan: Re-write codes to support VT3253 spec. @@ -198,22 +195,22 @@ bool CARDbSetPhyParameter(struct vnt_private *priv, u8 bb_type) priv->abyBBVGA[0] = 0x20; priv->abyBBVGA[2] = 0x10; priv->abyBBVGA[3] = 0x10; - BBbReadEmbedded(priv, 0xE7, &byData); + bb_read_embedded(priv, 0xE7, &byData); if (byData == 0x1C) - BBbWriteEmbedded(priv, 0xE7, priv->abyBBVGA[0]); + bb_write_embedded(priv, 0xE7, priv->abyBBVGA[0]); } else if (priv->byRFType == RF_UW2452) { MACvSetBBType(priv->PortOffset, BB_TYPE_11A); priv->abyBBVGA[0] = 0x18; - BBbReadEmbedded(priv, 0xE7, &byData); + bb_read_embedded(priv, 0xE7, &byData); if (byData == 0x14) { - BBbWriteEmbedded(priv, 0xE7, priv->abyBBVGA[0]); - BBbWriteEmbedded(priv, 0xE1, 0x57); + bb_write_embedded(priv, 0xE7, priv->abyBBVGA[0]); + bb_write_embedded(priv, 0xE1, 0x57); } } else { MACvSetBBType(priv->PortOffset, BB_TYPE_11A); } - BBbWriteEmbedded(priv, 0x88, 0x03); + bb_write_embedded(priv, 0x88, 0x03); bySlot = C_SLOT_SHORT; bySIFS = C_SIFS_A; byDIFS = C_SIFS_A + 2 * C_SLOT_SHORT; @@ -224,19 +221,19 @@ bool CARDbSetPhyParameter(struct vnt_private *priv, u8 bb_type) priv->abyBBVGA[0] = 0x1C; priv->abyBBVGA[2] = 0x00; priv->abyBBVGA[3] = 0x00; - BBbReadEmbedded(priv, 0xE7, &byData); + bb_read_embedded(priv, 0xE7, &byData); if (byData == 0x20) - BBbWriteEmbedded(priv, 0xE7, priv->abyBBVGA[0]); + bb_write_embedded(priv, 0xE7, priv->abyBBVGA[0]); } else if (priv->byRFType == RF_UW2452) { priv->abyBBVGA[0] = 0x14; - BBbReadEmbedded(priv, 0xE7, &byData); + bb_read_embedded(priv, 0xE7, &byData); if (byData == 0x18) { - BBbWriteEmbedded(priv, 0xE7, priv->abyBBVGA[0]); - BBbWriteEmbedded(priv, 0xE1, 0xD3); + bb_write_embedded(priv, 0xE7, priv->abyBBVGA[0]); + bb_write_embedded(priv, 0xE1, 0xD3); } } - BBbWriteEmbedded(priv, 0x88, 0x02); + bb_write_embedded(priv, 0x88, 0x02); bySlot = C_SLOT_LONG; bySIFS = C_SIFS_BG; byDIFS = C_SIFS_BG + 2 * C_SLOT_LONG; @@ -247,19 +244,19 @@ bool CARDbSetPhyParameter(struct vnt_private *priv, u8 bb_type) priv->abyBBVGA[0] = 0x1C; priv->abyBBVGA[2] = 0x00; priv->abyBBVGA[3] = 0x00; - BBbReadEmbedded(priv, 0xE7, &byData); + bb_read_embedded(priv, 0xE7, &byData); if (byData == 0x20) - BBbWriteEmbedded(priv, 0xE7, priv->abyBBVGA[0]); + bb_write_embedded(priv, 0xE7, priv->abyBBVGA[0]); } else if (priv->byRFType == RF_UW2452) { priv->abyBBVGA[0] = 0x14; - BBbReadEmbedded(priv, 0xE7, &byData); + bb_read_embedded(priv, 0xE7, &byData); if (byData == 0x18) { - BBbWriteEmbedded(priv, 0xE7, priv->abyBBVGA[0]); - BBbWriteEmbedded(priv, 0xE1, 0xD3); + bb_write_embedded(priv, 0xE7, priv->abyBBVGA[0]); + bb_write_embedded(priv, 0xE1, 0xD3); } } - BBbWriteEmbedded(priv, 0x88, 0x08); + bb_write_embedded(priv, 0x88, 0x08); bySIFS = C_SIFS_BG; if (priv->bShortSlotTime) { @@ -310,7 +307,7 @@ bool CARDbSetPhyParameter(struct vnt_private *priv, u8 bb_type) priv->bySlot = bySlot; VNSvOutPortB(priv->PortOffset + MAC_REG_SLOT, priv->bySlot); - BBvSetShortSlotTime(priv); + bb_set_short_slot_time(priv); } if (priv->byCWMaxMin != byCWMaxMin) { priv->byCWMaxMin = byCWMaxMin; @@ -431,7 +428,7 @@ void CARDbRadioPowerOff(struct vnt_private *priv) MACvRegBitsOff(priv->PortOffset, MAC_REG_HOSTCR, HOSTCR_RXON); - BBvSetDeepSleep(priv, priv->byLocalID); + bb_set_deep_sleep(priv, priv->byLocalID); priv->bRadioOff = true; pr_debug("chester power off\n"); @@ -439,60 +436,6 @@ void CARDbRadioPowerOff(struct vnt_private *priv) LED_ACTSET); /* LED issue */ } -/* - * Description: Turn on Radio power - * - * Parameters: - * In: - * priv - The adapter to be turned on - * Out: - * none - * - * Return Value: true if success; otherwise false - */ -bool CARDbRadioPowerOn(struct vnt_private *priv) -{ - bool bResult = true; - - pr_debug("chester power on\n"); - if (priv->bRadioControlOff) { - if (priv->bHWRadioOff) - pr_debug("chester bHWRadioOff\n"); - if (priv->bRadioControlOff) - pr_debug("chester bRadioControlOff\n"); - return false; } - - if (!priv->bRadioOff) { - pr_debug("chester pbRadioOff\n"); - return true; } - - BBvExitDeepSleep(priv, priv->byLocalID); - - MACvRegBitsOn(priv->PortOffset, MAC_REG_HOSTCR, HOSTCR_RXON); - - switch (priv->byRFType) { - case RF_RFMD2959: - MACvWordRegBitsOn(priv->PortOffset, MAC_REG_SOFTPWRCTL, - SOFTPWRCTL_TXPEINV); - MACvWordRegBitsOff(priv->PortOffset, MAC_REG_SOFTPWRCTL, - SOFTPWRCTL_SWPE1); - break; - - case RF_AIROHA: - case RF_AL2230S: - case RF_AIROHA7230: - MACvWordRegBitsOn(priv->PortOffset, MAC_REG_SOFTPWRCTL, - (SOFTPWRCTL_SWPE2 | SOFTPWRCTL_SWPE3)); - break; - } - - priv->bRadioOff = false; - pr_debug("chester power on\n"); - MACvRegBitsOff(priv->PortOffset, MAC_REG_GPIOCTL0, - LED_ACTSET); /* LED issue */ - return bResult; -} - void CARDvSafeResetTx(struct vnt_private *priv) { unsigned int uu; @@ -815,54 +758,6 @@ unsigned char CARDbyGetPktType(struct vnt_private *priv) return PK_TYPE_11GB; } -/* - * Description: Set NIC Loopback mode - * - * Parameters: - * In: - * priv - The adapter to be set - * wLoopbackMode - Loopback mode to be set - * Out: - * none - * - * Return Value: none - */ -void CARDvSetLoopbackMode(struct vnt_private *priv, - unsigned short wLoopbackMode) -{ - switch (wLoopbackMode) { - case CARD_LB_NONE: - case CARD_LB_MAC: - case CARD_LB_PHY: - break; - default: - break; - } - /* set MAC loopback */ - MACvSetLoopbackMode(priv, LOBYTE(wLoopbackMode)); - /* set Baseband loopback */ -} - -/* - * Description: Software Reset NIC - * - * Parameters: - * In: - * priv - The adapter to be reset - * Out: - * none - * - * Return Value: none - */ -bool CARDbSoftwareReset(struct vnt_private *priv) -{ - /* reset MAC */ - if (!MACbSafeSoftwareReset(priv)) - return false; - - return true; -} - /* * Description: Calculate TSF offset of two TSF input * Get TSF Offset from RxBCN's TSF and local TSF diff --git a/drivers/staging/vt6655/card.h b/drivers/staging/vt6655/card.h index 337266add6b2..568a2ddd6588 100644 --- a/drivers/staging/vt6655/card.h +++ b/drivers/staging/vt6655/card.h @@ -44,9 +44,6 @@ struct vnt_private; void CARDvSetRSPINF(struct vnt_private *priv, u8 bb_type); void CARDvUpdateBasicTopRate(struct vnt_private *priv); bool CARDbIsOFDMinBasicRate(struct vnt_private *priv); -void CARDvSetLoopbackMode(struct vnt_private *priv, - unsigned short wLoopbackMode); -bool CARDbSoftwareReset(struct vnt_private *priv); void CARDvSetFirstNextTBTT(struct vnt_private *priv, unsigned short wBeaconInterval); void CARDvUpdateNextTBTT(struct vnt_private *priv, u64 qwTSF, @@ -58,7 +55,6 @@ unsigned char CARDbyGetPktType(struct vnt_private *priv); void CARDvSafeResetTx(struct vnt_private *priv); void CARDvSafeResetRx(struct vnt_private *priv); void CARDbRadioPowerOff(struct vnt_private *priv); -bool CARDbRadioPowerOn(struct vnt_private *priv); bool CARDbSetPhyParameter(struct vnt_private *priv, u8 bb_type); bool CARDbUpdateTSF(struct vnt_private *priv, unsigned char byRxRate, u64 qwBSSTimestamp); diff --git a/drivers/staging/vt6655/channel.c b/drivers/staging/vt6655/channel.c index dec6f0f23b88..62a85c1ca6c4 100644 --- a/drivers/staging/vt6655/channel.c +++ b/drivers/staging/vt6655/channel.c @@ -173,7 +173,7 @@ bool set_channel(struct vnt_private *priv, struct ieee80211_channel *ch) priv->byBBVGACurrent != priv->abyBBVGA[0]) { priv->byBBVGACurrent = priv->abyBBVGA[0]; - BBvSetVGAGainOffset(priv, priv->byBBVGACurrent); + bb_set_vga_gain_offset(priv, priv->byBBVGACurrent); } /* clear NAV */ @@ -195,7 +195,7 @@ bool set_channel(struct vnt_private *priv, struct ieee80211_channel *ch) if (priv->bEnablePSMode) RFvWriteWakeProgSyn(priv, priv->byRFType, ch->hw_value); - BBvSoftwareReset(priv); + bb_software_reset(priv); if (priv->byLocalID > REV_ID_VT3253_B1) { unsigned long flags; diff --git a/drivers/staging/vt6655/device_main.c b/drivers/staging/vt6655/device_main.c index 5c86cc60eb5c..41cbec4134b0 100644 --- a/drivers/staging/vt6655/device_main.c +++ b/drivers/staging/vt6655/device_main.c @@ -21,18 +21,17 @@ * device_alloc_rx_buf - rx buffer pre-allocated function * device_free_rx_buf - free rx buffer function * device_free_tx_buf - free tx buffer function - * device_init_rd0_ring- initial rd dma0 ring - * device_init_rd1_ring- initial rd dma1 ring - * device_init_td0_ring- initial tx dma0 ring buffer - * device_init_td1_ring- initial tx dma1 ring buffer - * device_init_registers- initial MAC & BBP & RF internal registers. - * device_init_rings- initial tx/rx ring buffer - * device_free_rings- free all allocated ring buffer - * device_tx_srv- tx interrupt service function + * device_init_rd0_ring - initial rd dma0 ring + * device_init_rd1_ring - initial rd dma1 ring + * device_init_td0_ring - initial tx dma0 ring buffer + * device_init_td1_ring - initial tx dma1 ring buffer + * device_init_registers - initial MAC & BBP & RF internal registers. + * device_init_rings - initial tx/rx ring buffer + * device_free_rings - free all allocated ring buffer + * device_tx_srv - tx interrupt service function * * Revision History: */ -#undef __NO_VERSION__ #include #include "device.h" @@ -202,7 +201,7 @@ static void device_init_registers(struct vnt_private *priv) unsigned char byOFDMPwrdBm = 0; MACbShutdown(priv); - BBvSoftwareReset(priv); + bb_software_reset(priv); /* Do MACbSoftwareReset in MACvInitialize */ MACbSoftwareReset(priv); @@ -279,8 +278,8 @@ static void device_init_registers(struct vnt_private *priv) } /* Set initial antenna mode */ - BBvSetTxAntennaMode(priv, priv->byTxAntennaMode); - BBvSetRxAntennaMode(priv, priv->byRxAntennaMode); + bb_set_tx_antenna_mode(priv, priv->byTxAntennaMode); + bb_set_rx_antenna_mode(priv, priv->byRxAntennaMode); /* zonetype initial */ priv->byOriginalZonetype = priv->abyEEPROM[EEP_OFS_ZONETYPE]; @@ -357,16 +356,16 @@ static void device_init_registers(struct vnt_private *priv) VNSvOutPortB(priv->PortOffset + MAC_REG_TFTCTL, TFTCTL_TSFCNTREN); /* initialize BBP registers */ - BBbVT3253Init(priv); + bb_vt3253_init(priv); if (priv->bUpdateBBVGA) { priv->byBBVGACurrent = priv->abyBBVGA[0]; priv->byBBVGANew = priv->byBBVGACurrent; - BBvSetVGAGainOffset(priv, priv->abyBBVGA[0]); + bb_set_vga_gain_offset(priv, priv->abyBBVGA[0]); } - BBvSetRxAntennaMode(priv, priv->byRxAntennaMode); - BBvSetTxAntennaMode(priv, priv->byTxAntennaMode); + bb_set_rx_antenna_mode(priv, priv->byRxAntennaMode); + bb_set_tx_antenna_mode(priv, priv->byTxAntennaMode); /* Set BB and packet type at the same time. */ /* Set Short Slot Time, xIFS, and RSPINF. */ @@ -1001,7 +1000,7 @@ static void vnt_check_bb_vga(struct vnt_private *priv) if (priv->uBBVGADiffCount == 1) { /* first VGA diff gain */ - BBvSetVGAGainOffset(priv, priv->byBBVGANew); + bb_set_vga_gain_offset(priv, priv->byBBVGANew); dev_dbg(&priv->pcid->dev, "First RSSI[%d] NewGain[%d] OldGain[%d] Count[%d]\n", @@ -1017,7 +1016,7 @@ static void vnt_check_bb_vga(struct vnt_private *priv) priv->byBBVGACurrent, (int)priv->uBBVGADiffCount); - BBvSetVGAGainOffset(priv, priv->byBBVGANew); + bb_set_vga_gain_offset(priv, priv->byBBVGANew); } } @@ -1445,7 +1444,7 @@ static void vnt_bss_info_changed(struct ieee80211_hw *hw, priv->bShortSlotTime = false; CARDbSetPhyParameter(priv, priv->byBBType); - BBvSetVGAGainOffset(priv, priv->abyBBVGA[0]); + bb_set_vga_gain_offset(priv, priv->abyBBVGA[0]); } if (changed & BSS_CHANGED_TXPOWER) diff --git a/drivers/staging/vt6655/rf.c b/drivers/staging/vt6655/rf.c index d6ca6e5551a7..747d79265a7c 100644 --- a/drivers/staging/vt6655/rf.c +++ b/drivers/staging/vt6655/rf.c @@ -419,7 +419,7 @@ static bool s_bAL7230Init(struct vnt_private *priv) MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI | SOFTPWRCTL_TXPEINV)); - BBvPowerSaveModeOFF(priv); /* RobertYu:20050106, have DC value for Calibration */ + bb_power_save_mode_off(priv); /* RobertYu:20050106, have DC value for Calibration */ for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++) ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[ii]); @@ -443,7 +443,7 @@ static bool s_bAL7230Init(struct vnt_private *priv) SOFTPWRCTL_SWPECTI | SOFTPWRCTL_TXPEINV)); - BBvPowerSaveModeON(priv); /* RobertYu:20050106 */ + bb_power_save_mode_on(priv); /* RobertYu:20050106 */ /* PE1: TX_ON, PE2: RX_ON, PE3: PLLON */ /* 3-wire control for power saving mode */ diff --git a/drivers/staging/vt6655/rxtx.c b/drivers/staging/vt6655/rxtx.c index 37fcc42ed000..cfab64d2b312 100644 --- a/drivers/staging/vt6655/rxtx.c +++ b/drivers/staging/vt6655/rxtx.c @@ -165,16 +165,21 @@ s_uGetTxRsvTime( { unsigned int uDataTime, uAckTime; - uDataTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, cbFrameLength, wRate); - if (byPktType == PK_TYPE_11B) /* llb,CCK mode */ - uAckTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, (unsigned short)pDevice->byTopCCKBasicRate); - else /* 11g 2.4G OFDM mode & 11a 5G OFDM mode */ - uAckTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, (unsigned short)pDevice->byTopOFDMBasicRate); + uDataTime = bb_get_frame_time(pDevice->byPreambleType, byPktType, cbFrameLength, wRate); - if (bNeedAck) - return uDataTime + pDevice->uSIFS + uAckTime; - else + if (!bNeedAck) return uDataTime; + + /* + * CCK mode - 11b + * OFDM mode - 11g 2.4G & 11a 5G + */ + uAckTime = bb_get_frame_time(pDevice->byPreambleType, byPktType, 14, + byPktType == PK_TYPE_11B ? + pDevice->byTopCCKBasicRate : + pDevice->byTopOFDMBasicRate); + + return uDataTime + pDevice->uSIFS + uAckTime; } static __le16 vnt_rxtx_rsvtime_le16(struct vnt_private *priv, u8 pkt_type, @@ -195,24 +200,28 @@ s_uGetRTSCTSRsvTime( unsigned short wCurrentRate ) { - unsigned int uRrvTime, uRTSTime, uCTSTime, uAckTime, uDataTime; + unsigned int uRrvTime = 0; + unsigned int uRTSTime = 0; + unsigned int uCTSTime = 0; + unsigned int uAckTime = 0; + unsigned int uDataTime = 0; - uRrvTime = uRTSTime = uCTSTime = uAckTime = uDataTime = 0; - - uDataTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, cbFrameLength, wCurrentRate); + uDataTime = bb_get_frame_time(pDevice->byPreambleType, byPktType, cbFrameLength, wCurrentRate); if (byRTSRsvType == 0) { /* RTSTxRrvTime_bb */ - uRTSTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 20, pDevice->byTopCCKBasicRate); - uCTSTime = uAckTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopCCKBasicRate); + uRTSTime = bb_get_frame_time(pDevice->byPreambleType, byPktType, 20, pDevice->byTopCCKBasicRate); + uAckTime = bb_get_frame_time(pDevice->byPreambleType, byPktType, 14, pDevice->byTopCCKBasicRate); + uCTSTime = uAckTime; } else if (byRTSRsvType == 1) { /* RTSTxRrvTime_ba, only in 2.4GHZ */ - uRTSTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 20, pDevice->byTopCCKBasicRate); - uCTSTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopCCKBasicRate); - uAckTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopOFDMBasicRate); + uRTSTime = bb_get_frame_time(pDevice->byPreambleType, byPktType, 20, pDevice->byTopCCKBasicRate); + uCTSTime = bb_get_frame_time(pDevice->byPreambleType, byPktType, 14, pDevice->byTopCCKBasicRate); + uAckTime = bb_get_frame_time(pDevice->byPreambleType, byPktType, 14, pDevice->byTopOFDMBasicRate); } else if (byRTSRsvType == 2) { /* RTSTxRrvTime_aa */ - uRTSTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 20, pDevice->byTopOFDMBasicRate); - uCTSTime = uAckTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopOFDMBasicRate); + uRTSTime = bb_get_frame_time(pDevice->byPreambleType, byPktType, 20, pDevice->byTopOFDMBasicRate); + uAckTime = bb_get_frame_time(pDevice->byPreambleType, byPktType, 14, pDevice->byTopOFDMBasicRate); + uCTSTime = uAckTime; } else if (byRTSRsvType == 3) { /* CTSTxRrvTime_ba, only in 2.4GHZ */ - uCTSTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopCCKBasicRate); - uAckTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopOFDMBasicRate); + uCTSTime = bb_get_frame_time(pDevice->byPreambleType, byPktType, 14, pDevice->byTopCCKBasicRate); + uAckTime = bb_get_frame_time(pDevice->byPreambleType, byPktType, 14, pDevice->byTopOFDMBasicRate); uRrvTime = uCTSTime + uAckTime + uDataTime + 2 * pDevice->uSIFS; return cpu_to_le16((u16)uRrvTime); } @@ -239,138 +248,83 @@ s_uGetDataDuration( ) { bool bLastFrag = false; - unsigned int uAckTime = 0, uNextPktTime = 0; + unsigned int uAckTime = 0, uNextPktTime = 0, len; if (uFragIdx == (uMACfragNum - 1)) bLastFrag = true; + if (uFragIdx == (uMACfragNum - 2)) + len = cbLastFragmentSize; + else + len = cbFrameLength; + switch (byDurType) { case DATADUR_B: /* DATADUR_B */ - if (((uMACfragNum == 1)) || bLastFrag) {/* Non Frag or Last Frag */ - if (bNeedAck) { - uAckTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopCCKBasicRate); - return pDevice->uSIFS + uAckTime; - } else { - return 0; - } - } else {/* First Frag or Mid Frag */ - if (uFragIdx == (uMACfragNum - 2)) - uNextPktTime = s_uGetTxRsvTime(pDevice, byPktType, cbLastFragmentSize, wRate, bNeedAck); - else - uNextPktTime = s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wRate, bNeedAck); - - if (bNeedAck) { - uAckTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopCCKBasicRate); - return pDevice->uSIFS + uAckTime + uNextPktTime; - } else { - return pDevice->uSIFS + uNextPktTime; - } + if (bNeedAck) { + uAckTime = bb_get_frame_time(pDevice->byPreambleType, + byPktType, 14, + pDevice->byTopCCKBasicRate); } - break; + /* Non Frag or Last Frag */ + if ((uMACfragNum == 1) || bLastFrag) { + if (!bNeedAck) + return 0; + } else { + /* First Frag or Mid Frag */ + uNextPktTime = s_uGetTxRsvTime(pDevice, byPktType, + len, wRate, bNeedAck); + } + + return pDevice->uSIFS + uAckTime + uNextPktTime; case DATADUR_A: /* DATADUR_A */ - if (((uMACfragNum == 1)) || bLastFrag) {/* Non Frag or Last Frag */ - if (bNeedAck) { - uAckTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopOFDMBasicRate); - return pDevice->uSIFS + uAckTime; - } else { - return 0; - } - } else {/* First Frag or Mid Frag */ - if (uFragIdx == (uMACfragNum - 2)) - uNextPktTime = s_uGetTxRsvTime(pDevice, byPktType, cbLastFragmentSize, wRate, bNeedAck); - else - uNextPktTime = s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wRate, bNeedAck); - - if (bNeedAck) { - uAckTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopOFDMBasicRate); - return pDevice->uSIFS + uAckTime + uNextPktTime; - } else { - return pDevice->uSIFS + uNextPktTime; - } + if (bNeedAck) { + uAckTime = bb_get_frame_time(pDevice->byPreambleType, + byPktType, 14, + pDevice->byTopOFDMBasicRate); } - break; + /* Non Frag or Last Frag */ + if ((uMACfragNum == 1) || bLastFrag) { + if (!bNeedAck) + return 0; + } else { + /* First Frag or Mid Frag */ + uNextPktTime = s_uGetTxRsvTime(pDevice, byPktType, + len, wRate, bNeedAck); + } + + return pDevice->uSIFS + uAckTime + uNextPktTime; case DATADUR_A_F0: /* DATADUR_A_F0 */ - if (((uMACfragNum == 1)) || bLastFrag) {/* Non Frag or Last Frag */ - if (bNeedAck) { - uAckTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopOFDMBasicRate); - return pDevice->uSIFS + uAckTime; - } else { - return 0; - } - } else { /* First Frag or Mid Frag */ - if (byFBOption == AUTO_FB_0) { - if (wRate < RATE_18M) - wRate = RATE_18M; - else if (wRate > RATE_54M) - wRate = RATE_54M; - - if (uFragIdx == (uMACfragNum - 2)) - uNextPktTime = s_uGetTxRsvTime(pDevice, byPktType, cbLastFragmentSize, wFB_Opt0[FB_RATE0][wRate-RATE_18M], bNeedAck); - else - uNextPktTime = s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wFB_Opt0[FB_RATE0][wRate-RATE_18M], bNeedAck); - - } else { /* (byFBOption == AUTO_FB_1) */ - if (wRate < RATE_18M) - wRate = RATE_18M; - else if (wRate > RATE_54M) - wRate = RATE_54M; - - if (uFragIdx == (uMACfragNum - 2)) - uNextPktTime = s_uGetTxRsvTime(pDevice, byPktType, cbLastFragmentSize, wFB_Opt1[FB_RATE0][wRate-RATE_18M], bNeedAck); - else - uNextPktTime = s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wFB_Opt1[FB_RATE0][wRate-RATE_18M], bNeedAck); - } - - if (bNeedAck) { - uAckTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopOFDMBasicRate); - return pDevice->uSIFS + uAckTime + uNextPktTime; - } else { - return pDevice->uSIFS + uNextPktTime; - } - } - break; - case DATADUR_A_F1: /* DATADUR_A_F1 */ - if (((uMACfragNum == 1)) || bLastFrag) { /* Non Frag or Last Frag */ - if (bNeedAck) { - uAckTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopOFDMBasicRate); - return pDevice->uSIFS + uAckTime; - } else { - return 0; - } - } else { /* First Frag or Mid Frag */ - if (byFBOption == AUTO_FB_0) { - if (wRate < RATE_18M) - wRate = RATE_18M; - else if (wRate > RATE_54M) - wRate = RATE_54M; - - if (uFragIdx == (uMACfragNum - 2)) - uNextPktTime = s_uGetTxRsvTime(pDevice, byPktType, cbLastFragmentSize, wFB_Opt0[FB_RATE1][wRate-RATE_18M], bNeedAck); - else - uNextPktTime = s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wFB_Opt0[FB_RATE1][wRate-RATE_18M], bNeedAck); - - } else { /* (byFBOption == AUTO_FB_1) */ - if (wRate < RATE_18M) - wRate = RATE_18M; - else if (wRate > RATE_54M) - wRate = RATE_54M; - - if (uFragIdx == (uMACfragNum - 2)) - uNextPktTime = s_uGetTxRsvTime(pDevice, byPktType, cbLastFragmentSize, wFB_Opt1[FB_RATE1][wRate-RATE_18M], bNeedAck); - else - uNextPktTime = s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wFB_Opt1[FB_RATE1][wRate-RATE_18M], bNeedAck); - } - if (bNeedAck) { - uAckTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopOFDMBasicRate); - return pDevice->uSIFS + uAckTime + uNextPktTime; - } else { - return pDevice->uSIFS + uNextPktTime; - } + if (bNeedAck) { + uAckTime = bb_get_frame_time(pDevice->byPreambleType, + byPktType, 14, + pDevice->byTopOFDMBasicRate); } - break; + /* Non Frag or Last Frag */ + if ((uMACfragNum == 1) || bLastFrag) { + if (!bNeedAck) + return 0; + } else { + /* First Frag or Mid Frag */ + if (wRate < RATE_18M) + wRate = RATE_18M; + else if (wRate > RATE_54M) + wRate = RATE_54M; + + wRate -= RATE_18M; + + if (byFBOption == AUTO_FB_0) + wRate = wFB_Opt0[FB_RATE0][wRate]; + else + wRate = wFB_Opt1[FB_RATE0][wRate]; + + uNextPktTime = s_uGetTxRsvTime(pDevice, byPktType, + len, wRate, bNeedAck); + } + + return pDevice->uSIFS + uAckTime + uNextPktTime; default: break; @@ -396,17 +350,17 @@ s_uGetRTSCTSDuration( switch (byDurType) { case RTSDUR_BB: /* RTSDuration_bb */ - uCTSTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopCCKBasicRate); + uCTSTime = bb_get_frame_time(pDevice->byPreambleType, byPktType, 14, pDevice->byTopCCKBasicRate); uDurTime = uCTSTime + 2 * pDevice->uSIFS + s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wRate, bNeedAck); break; case RTSDUR_BA: /* RTSDuration_ba */ - uCTSTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopCCKBasicRate); + uCTSTime = bb_get_frame_time(pDevice->byPreambleType, byPktType, 14, pDevice->byTopCCKBasicRate); uDurTime = uCTSTime + 2 * pDevice->uSIFS + s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wRate, bNeedAck); break; case RTSDUR_AA: /* RTSDuration_aa */ - uCTSTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopOFDMBasicRate); + uCTSTime = bb_get_frame_time(pDevice->byPreambleType, byPktType, 14, pDevice->byTopOFDMBasicRate); uDurTime = uCTSTime + 2 * pDevice->uSIFS + s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wRate, bNeedAck); break; @@ -415,7 +369,7 @@ s_uGetRTSCTSDuration( break; case RTSDUR_BA_F0: /* RTSDuration_ba_f0 */ - uCTSTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopCCKBasicRate); + uCTSTime = bb_get_frame_time(pDevice->byPreambleType, byPktType, 14, pDevice->byTopCCKBasicRate); if ((byFBOption == AUTO_FB_0) && (wRate >= RATE_18M) && (wRate <= RATE_54M)) uDurTime = uCTSTime + 2 * pDevice->uSIFS + s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wFB_Opt0[FB_RATE0][wRate-RATE_18M], bNeedAck); else if ((byFBOption == AUTO_FB_1) && (wRate >= RATE_18M) && (wRate <= RATE_54M)) @@ -424,7 +378,7 @@ s_uGetRTSCTSDuration( break; case RTSDUR_AA_F0: /* RTSDuration_aa_f0 */ - uCTSTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopOFDMBasicRate); + uCTSTime = bb_get_frame_time(pDevice->byPreambleType, byPktType, 14, pDevice->byTopOFDMBasicRate); if ((byFBOption == AUTO_FB_0) && (wRate >= RATE_18M) && (wRate <= RATE_54M)) uDurTime = uCTSTime + 2 * pDevice->uSIFS + s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wFB_Opt0[FB_RATE0][wRate-RATE_18M], bNeedAck); else if ((byFBOption == AUTO_FB_1) && (wRate >= RATE_18M) && (wRate <= RATE_54M)) @@ -433,7 +387,7 @@ s_uGetRTSCTSDuration( break; case RTSDUR_BA_F1: /* RTSDuration_ba_f1 */ - uCTSTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopCCKBasicRate); + uCTSTime = bb_get_frame_time(pDevice->byPreambleType, byPktType, 14, pDevice->byTopCCKBasicRate); if ((byFBOption == AUTO_FB_0) && (wRate >= RATE_18M) && (wRate <= RATE_54M)) uDurTime = uCTSTime + 2*pDevice->uSIFS + s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wFB_Opt0[FB_RATE1][wRate-RATE_18M], bNeedAck); else if ((byFBOption == AUTO_FB_1) && (wRate >= RATE_18M) && (wRate <= RATE_54M)) @@ -442,7 +396,7 @@ s_uGetRTSCTSDuration( break; case RTSDUR_AA_F1: /* RTSDuration_aa_f1 */ - uCTSTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopOFDMBasicRate); + uCTSTime = bb_get_frame_time(pDevice->byPreambleType, byPktType, 14, pDevice->byTopOFDMBasicRate); if ((byFBOption == AUTO_FB_0) && (wRate >= RATE_18M) && (wRate <= RATE_54M)) uDurTime = uCTSTime + 2 * pDevice->uSIFS + s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wFB_Opt0[FB_RATE1][wRate-RATE_18M], bNeedAck); else if ((byFBOption == AUTO_FB_1) && (wRate >= RATE_18M) && (wRate <= RATE_54M)) @@ -1040,16 +994,14 @@ s_cbFillTxBufHead(struct vnt_private *pDevice, unsigned char byPktType, bool bRTS = (bool)(fifo_ctl & FIFOCTL_RTS); struct vnt_tx_desc *ptdCurr; unsigned int cbHeaderLength = 0; - void *pvRrvTime; - struct vnt_mic_hdr *pMICHDR; - void *pvRTS; - void *pvCTS; - void *pvTxDataHd; + void *pvRrvTime = NULL; + struct vnt_mic_hdr *pMICHDR = NULL; + void *pvRTS = NULL; + void *pvCTS = NULL; + void *pvTxDataHd = NULL; unsigned short wTxBufSize; /* FFinfo size */ unsigned char byFBOption = AUTO_FB_NONE; - pvRrvTime = pMICHDR = pvRTS = pvCTS = pvTxDataHd = NULL; - cbFrameSize = skb->len + 4; if (info->control.hw_key) { diff --git a/drivers/staging/vt6656/Makefile b/drivers/staging/vt6656/Makefile index 375f54e9f58b..f696a9d7a143 100644 --- a/drivers/staging/vt6656/Makefile +++ b/drivers/staging/vt6656/Makefile @@ -1,7 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 -# TODO: all of these should be removed -ccflags-y := -DLINUX -D__KERNEL__ -DEXPORT_SYMTAB -D__NO_VERSION__ -ccflags-y += -DHOSTAP vt6656_stage-y += main_usb.o \ card.o \ @@ -13,7 +10,6 @@ vt6656_stage-y += main_usb.o \ key.o \ rf.o \ usbpipe.o \ - channel.o \ - firmware.o + channel.o obj-$(CONFIG_VT6656) += vt6656_stage.o diff --git a/drivers/staging/vt6656/baseband.c b/drivers/staging/vt6656/baseband.c index a19a563d8bcc..41ae779ec61f 100644 --- a/drivers/staging/vt6656/baseband.c +++ b/drivers/staging/vt6656/baseband.c @@ -23,13 +23,15 @@ */ #include +#include #include +#include "device.h" #include "mac.h" #include "baseband.h" #include "rf.h" #include "usbpipe.h" -static u8 vnt_vt3184_agc[] = { +static const u8 vnt_vt3184_agc[] = { 0x00, 0x00, 0x02, 0x02, 0x04, 0x04, 0x06, 0x06, 0x08, 0x08, 0x0a, 0x0a, 0x0c, 0x0c, 0x0e, 0x0e, /* 0x0f */ 0x10, 0x10, 0x12, 0x12, 0x14, 0x14, 0x16, 0x16, @@ -76,7 +78,7 @@ static u8 vnt_vt3184_al2230[] = { }; /* {{RobertYu:20060515, new BB setting for VT3226D0 */ -static u8 vnt_vt3184_vt3226d0[] = { +static const u8 vnt_vt3184_vt3226d0[] = { 0x31, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x70, 0x45, 0x2a, 0x76, 0x00, 0x00, 0x80, 0x00, /* 0x0f */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -111,198 +113,85 @@ static u8 vnt_vt3184_vt3226d0[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* 0xff */ }; -static const u16 vnt_frame_time[MAX_RATE] = { - 10, 20, 55, 110, 24, 36, 48, 72, 96, 144, 192, 216 +struct vnt_threshold { + u8 bb_pre_ed_rssi; + u8 cr_201; + u8 cr_206; }; -/* - * Description: Calculate data frame transmitting time - * - * Parameters: - * In: - * preamble_type - Preamble Type - * pkt_type - PK_TYPE_11A, PK_TYPE_11B, PK_TYPE_11GB, PK_TYPE_11GA - * frame_length - Baseband Type - * tx_rate - Tx Rate - * Out: - * - * Return Value: FrameTime - * - */ -unsigned int vnt_get_frame_time(u8 preamble_type, u8 pkt_type, - unsigned int frame_length, u16 tx_rate) -{ - unsigned int frame_time; - unsigned int preamble; - unsigned int rate = 0; +static const struct vnt_threshold al2230_vnt_threshold[] = { + {0, 0x00, 0x30}, /* Max sensitivity */ + {68, 0x00, 0x36}, + {67, 0x00, 0x43}, + {66, 0x00, 0x51}, + {65, 0x00, 0x62}, + {64, 0x00, 0x79}, + {63, 0x00, 0x93}, + {62, 0x00, 0xb9}, + {61, 0x00, 0xe3}, + {60, 0x01, 0x18}, + {59, 0x01, 0x54}, + {58, 0x01, 0xa0}, + {57, 0x02, 0x20}, + {56, 0x02, 0xa0}, + {55, 0x03, 0x00}, + {53, 0x06, 0x00}, + {51, 0x09, 0x00}, + {49, 0x0e, 0x00}, + {47, 0x15, 0x00}, + {46, 0x1a, 0x00}, + {45, 0xff, 0x00} +}; - if (tx_rate > RATE_54M) - return 0; +static const struct vnt_threshold vt3226_vnt_threshold[] = { + {0, 0x00, 0x24}, /* Max sensitivity */ + {68, 0x00, 0x2d}, + {67, 0x00, 0x36}, + {66, 0x00, 0x43}, + {65, 0x00, 0x52}, + {64, 0x00, 0x68}, + {63, 0x00, 0x80}, + {62, 0x00, 0x9c}, + {61, 0x00, 0xc0}, + {60, 0x00, 0xea}, + {59, 0x01, 0x30}, + {58, 0x01, 0x70}, + {57, 0x01, 0xb0}, + {56, 0x02, 0x30}, + {55, 0x02, 0xc0}, + {53, 0x04, 0x00}, + {51, 0x07, 0x00}, + {49, 0x0a, 0x00}, + {47, 0x11, 0x00}, + {45, 0x18, 0x00}, + {43, 0x26, 0x00}, + {42, 0x36, 0x00}, + {41, 0xff, 0x00} +}; - rate = (unsigned int)vnt_frame_time[tx_rate]; - - if (tx_rate <= 3) { - if (preamble_type == 1) - preamble = 96; - else - preamble = 192; - - frame_time = DIV_ROUND_UP(frame_length * 80, rate); - return preamble + frame_time; - } - - frame_time = DIV_ROUND_UP(frame_length * 8 + 22, rate); - frame_time = frame_time * 4; - - if (pkt_type != PK_TYPE_11A) - frame_time += 6; - return 20 + frame_time; -} - -/* - * Description: Calculate Length, Service, and Signal fields of Phy for Tx - * - * Parameters: - * In: - * priv - Device Structure - * frame_length - Tx Frame Length - * tx_rate - Tx Rate - * Out: - * struct vnt_phy_field *phy - * - pointer to Phy Length field - * - pointer to Phy Service field - * - pointer to Phy Signal field - * - * Return Value: none - * - */ -void vnt_get_phy_field(struct vnt_private *priv, u32 frame_length, - u16 tx_rate, u8 pkt_type, struct vnt_phy_field *phy) -{ - u32 bit_count; - u32 count = 0; - u32 tmp; - int ext_bit; - u8 preamble_type = priv->preamble_type; - - bit_count = frame_length * 8; - ext_bit = false; - - switch (tx_rate) { - case RATE_1M: - count = bit_count; - - phy->signal = 0x00; - - break; - case RATE_2M: - count = bit_count / 2; - - if (preamble_type == 1) - phy->signal = 0x09; - else - phy->signal = 0x01; - - break; - case RATE_5M: - count = DIV_ROUND_UP(bit_count * 10, 55); - - if (preamble_type == 1) - phy->signal = 0x0a; - else - phy->signal = 0x02; - - break; - case RATE_11M: - count = bit_count / 11; - tmp = count * 11; - - if (tmp != bit_count) { - count++; - - if ((bit_count - tmp) <= 3) - ext_bit = true; - } - - if (preamble_type == 1) - phy->signal = 0x0b; - else - phy->signal = 0x03; - - break; - case RATE_6M: - if (pkt_type == PK_TYPE_11A) - phy->signal = 0x9b; - else - phy->signal = 0x8b; - - break; - case RATE_9M: - if (pkt_type == PK_TYPE_11A) - phy->signal = 0x9f; - else - phy->signal = 0x8f; - - break; - case RATE_12M: - if (pkt_type == PK_TYPE_11A) - phy->signal = 0x9a; - else - phy->signal = 0x8a; - - break; - case RATE_18M: - if (pkt_type == PK_TYPE_11A) - phy->signal = 0x9e; - else - phy->signal = 0x8e; - - break; - case RATE_24M: - if (pkt_type == PK_TYPE_11A) - phy->signal = 0x99; - else - phy->signal = 0x89; - - break; - case RATE_36M: - if (pkt_type == PK_TYPE_11A) - phy->signal = 0x9d; - else - phy->signal = 0x8d; - - break; - case RATE_48M: - if (pkt_type == PK_TYPE_11A) - phy->signal = 0x98; - else - phy->signal = 0x88; - - break; - case RATE_54M: - if (pkt_type == PK_TYPE_11A) - phy->signal = 0x9c; - else - phy->signal = 0x8c; - break; - default: - if (pkt_type == PK_TYPE_11A) - phy->signal = 0x9c; - else - phy->signal = 0x8c; - break; - } - - if (pkt_type == PK_TYPE_11B) { - phy->service = 0x00; - if (ext_bit) - phy->service |= 0x80; - phy->len = cpu_to_le16((u16)count); - } else { - phy->service = 0x00; - phy->len = cpu_to_le16((u16)frame_length); - } -} +static const struct vnt_threshold vt3342_vnt_threshold[] = { + {0, 0x00, 0x38}, /* Max sensitivity */ + {66, 0x00, 0x43}, + {65, 0x00, 0x52}, + {64, 0x00, 0x68}, + {63, 0x00, 0x80}, + {62, 0x00, 0x9c}, + {61, 0x00, 0xc0}, + {60, 0x00, 0xea}, + {59, 0x01, 0x30}, + {58, 0x01, 0x70}, + {57, 0x01, 0xb0}, + {56, 0x02, 0x30}, + {55, 0x02, 0xc0}, + {53, 0x04, 0x00}, + {51, 0x07, 0x00}, + {49, 0x0a, 0x00}, + {47, 0x11, 0x00}, + {45, 0x18, 0x00}, + {43, 0x26, 0x00}, + {42, 0x36, 0x00}, + {41, 0xff, 0x00} +}; /* * Description: Set Antenna mode @@ -352,9 +241,10 @@ int vnt_set_antenna_mode(struct vnt_private *priv, u8 antenna_mode) int vnt_vt3184_init(struct vnt_private *priv) { - int ret = 0; + int ret; u16 length; - u8 *addr; + u8 *addr = NULL; + const u8 *c_addr; u8 data; ret = vnt_control_in(priv, MESSAGE_TYPE_READ, 0, MESSAGE_REQUEST_EEPROM, @@ -366,23 +256,15 @@ int vnt_vt3184_init(struct vnt_private *priv) dev_dbg(&priv->usb->dev, "RF Type %d\n", priv->rf_type); - if (priv->rf_type == RF_AL2230 || - priv->rf_type == RF_AL2230S) { + if ((priv->rf_type == RF_AL2230) || + (priv->rf_type == RF_AL2230S) || + (priv->rf_type == RF_AIROHA7230)) { priv->bb_rx_conf = vnt_vt3184_al2230[10]; length = sizeof(vnt_vt3184_al2230); addr = vnt_vt3184_al2230; - priv->bb_vga[0] = 0x1C; - priv->bb_vga[1] = 0x10; - priv->bb_vga[2] = 0x0; - priv->bb_vga[3] = 0x0; - - } else if (priv->rf_type == RF_AIROHA7230) { - priv->bb_rx_conf = vnt_vt3184_al2230[10]; - length = sizeof(vnt_vt3184_al2230); - addr = vnt_vt3184_al2230; - - addr[0xd7] = 0x06; + if (priv->rf_type == RF_AIROHA7230) + addr[0xd7] = 0x06; priv->bb_vga[0] = 0x1c; priv->bb_vga[1] = 0x10; @@ -390,25 +272,11 @@ int vnt_vt3184_init(struct vnt_private *priv) priv->bb_vga[3] = 0x0; } else if ((priv->rf_type == RF_VT3226) || - (priv->rf_type == RF_VT3226D0)) { + (priv->rf_type == RF_VT3226D0) || + (priv->rf_type == RF_VT3342A0)) { priv->bb_rx_conf = vnt_vt3184_vt3226d0[10]; length = sizeof(vnt_vt3184_vt3226d0); - addr = vnt_vt3184_vt3226d0; - - priv->bb_vga[0] = 0x20; - priv->bb_vga[1] = 0x10; - priv->bb_vga[2] = 0x0; - priv->bb_vga[3] = 0x0; - - /* Fix VT3226 DFC system timing issue */ - ret = vnt_mac_reg_bits_on(priv, MAC_REG_SOFTPWRCTL2, - SOFTPWRCTL_RFLEOPT); - if (ret) - goto end; - } else if (priv->rf_type == RF_VT3342A0) { - priv->bb_rx_conf = vnt_vt3184_vt3226d0[10]; - length = sizeof(vnt_vt3184_vt3226d0); - addr = vnt_vt3184_vt3226d0; + c_addr = vnt_vt3184_vt3226d0; priv->bb_vga[0] = 0x20; priv->bb_vga[1] = 0x10; @@ -424,8 +292,11 @@ int vnt_vt3184_init(struct vnt_private *priv) goto end; } + if (addr) + c_addr = addr; + ret = vnt_control_out_blocks(priv, VNT_REG_BLOCK_SIZE, - MESSAGE_REQUEST_BBREG, length, addr); + MESSAGE_REQUEST_BBREG, length, c_addr); if (ret) goto end; @@ -435,19 +306,13 @@ int vnt_vt3184_init(struct vnt_private *priv) if (ret) goto end; - if (priv->rf_type == RF_VT3226 || - priv->rf_type == RF_VT3342A0) { - ret = vnt_control_out_u8(priv, MESSAGE_REQUEST_MACREG, - MAC_REG_ITRTMSET, 0x23); - if (ret) - goto end; + if ((priv->rf_type == RF_VT3226) || + (priv->rf_type == RF_VT3342A0) || + (priv->rf_type == RF_VT3226D0)) { + data = (priv->rf_type == RF_VT3226D0) ? 0x11 : 0x23; - ret = vnt_mac_reg_bits_on(priv, MAC_REG_PAPEDELAY, BIT(0)); - if (ret) - goto end; - } else if (priv->rf_type == RF_VT3226D0) { ret = vnt_control_out_u8(priv, MESSAGE_REQUEST_MACREG, - MAC_REG_ITRTMSET, 0x11); + MAC_REG_ITRTMSET, data); if (ret) goto end; @@ -507,21 +372,22 @@ int vnt_set_short_slot_time(struct vnt_private *priv) ret = vnt_control_in_u8(priv, MESSAGE_REQUEST_BBREG, 0xe7, &bb_vga); if (ret) - goto end; + return ret; if (bb_vga == priv->bb_vga[0]) priv->bb_rx_conf |= 0x20; - ret = vnt_control_out_u8(priv, MESSAGE_REQUEST_BBREG, 0x0a, - priv->bb_rx_conf); - -end: - return ret; + return vnt_control_out_u8(priv, MESSAGE_REQUEST_BBREG, 0x0a, + priv->bb_rx_conf); } -void vnt_set_vga_gain_offset(struct vnt_private *priv, u8 data) +int vnt_set_vga_gain_offset(struct vnt_private *priv, u8 data) { - vnt_control_out_u8(priv, MESSAGE_REQUEST_BBREG, 0xE7, data); + int ret; + + ret = vnt_control_out_u8(priv, MESSAGE_REQUEST_BBREG, 0xE7, data); + if (ret) + return ret; /* patch for 3253B0 Baseband with Cardbus module */ if (priv->short_slot_time) @@ -529,7 +395,8 @@ void vnt_set_vga_gain_offset(struct vnt_private *priv, u8 data) else priv->bb_rx_conf |= 0x20; /* 0010 0000 */ - vnt_control_out_u8(priv, MESSAGE_REQUEST_BBREG, 0x0a, priv->bb_rx_conf); + return vnt_control_out_u8(priv, MESSAGE_REQUEST_BBREG, 0x0a, + priv->bb_rx_conf); } /* @@ -570,268 +437,57 @@ int vnt_exit_deep_sleep(struct vnt_private *priv) return vnt_control_out_u8(priv, MESSAGE_REQUEST_BBREG, 0x0d, 0x01); } -void vnt_update_pre_ed_threshold(struct vnt_private *priv, int scanning) +int vnt_update_pre_ed_threshold(struct vnt_private *priv, int scanning) { - u8 cr_201 = 0x0, cr_206 = 0x0; - u8 ed_inx = priv->bb_pre_ed_index; + const struct vnt_threshold *threshold = NULL; + u8 length; + u8 cr_201, cr_206; + u8 ed_inx; + int ret; switch (priv->rf_type) { case RF_AL2230: case RF_AL2230S: case RF_AIROHA7230: - if (scanning) { /* Max sensitivity */ - ed_inx = 0; - cr_206 = 0x30; - break; - } - - if (priv->bb_pre_ed_rssi <= 45) { - ed_inx = 20; - cr_201 = 0xff; - } else if (priv->bb_pre_ed_rssi <= 46) { - ed_inx = 19; - cr_201 = 0x1a; - } else if (priv->bb_pre_ed_rssi <= 47) { - ed_inx = 18; - cr_201 = 0x15; - } else if (priv->bb_pre_ed_rssi <= 49) { - ed_inx = 17; - cr_201 = 0xe; - } else if (priv->bb_pre_ed_rssi <= 51) { - ed_inx = 16; - cr_201 = 0x9; - } else if (priv->bb_pre_ed_rssi <= 53) { - ed_inx = 15; - cr_201 = 0x6; - } else if (priv->bb_pre_ed_rssi <= 55) { - ed_inx = 14; - cr_201 = 0x3; - } else if (priv->bb_pre_ed_rssi <= 56) { - ed_inx = 13; - cr_201 = 0x2; - cr_206 = 0xa0; - } else if (priv->bb_pre_ed_rssi <= 57) { - ed_inx = 12; - cr_201 = 0x2; - cr_206 = 0x20; - } else if (priv->bb_pre_ed_rssi <= 58) { - ed_inx = 11; - cr_201 = 0x1; - cr_206 = 0xa0; - } else if (priv->bb_pre_ed_rssi <= 59) { - ed_inx = 10; - cr_201 = 0x1; - cr_206 = 0x54; - } else if (priv->bb_pre_ed_rssi <= 60) { - ed_inx = 9; - cr_201 = 0x1; - cr_206 = 0x18; - } else if (priv->bb_pre_ed_rssi <= 61) { - ed_inx = 8; - cr_206 = 0xe3; - } else if (priv->bb_pre_ed_rssi <= 62) { - ed_inx = 7; - cr_206 = 0xb9; - } else if (priv->bb_pre_ed_rssi <= 63) { - ed_inx = 6; - cr_206 = 0x93; - } else if (priv->bb_pre_ed_rssi <= 64) { - ed_inx = 5; - cr_206 = 0x79; - } else if (priv->bb_pre_ed_rssi <= 65) { - ed_inx = 4; - cr_206 = 0x62; - } else if (priv->bb_pre_ed_rssi <= 66) { - ed_inx = 3; - cr_206 = 0x51; - } else if (priv->bb_pre_ed_rssi <= 67) { - ed_inx = 2; - cr_206 = 0x43; - } else if (priv->bb_pre_ed_rssi <= 68) { - ed_inx = 1; - cr_206 = 0x36; - } else { - ed_inx = 0; - cr_206 = 0x30; - } + threshold = al2230_vnt_threshold; + length = ARRAY_SIZE(al2230_vnt_threshold); break; case RF_VT3226: case RF_VT3226D0: - if (scanning) { /* Max sensitivity */ - ed_inx = 0; - cr_206 = 0x24; - break; - } - - if (priv->bb_pre_ed_rssi <= 41) { - ed_inx = 22; - cr_201 = 0xff; - } else if (priv->bb_pre_ed_rssi <= 42) { - ed_inx = 21; - cr_201 = 0x36; - } else if (priv->bb_pre_ed_rssi <= 43) { - ed_inx = 20; - cr_201 = 0x26; - } else if (priv->bb_pre_ed_rssi <= 45) { - ed_inx = 19; - cr_201 = 0x18; - } else if (priv->bb_pre_ed_rssi <= 47) { - ed_inx = 18; - cr_201 = 0x11; - } else if (priv->bb_pre_ed_rssi <= 49) { - ed_inx = 17; - cr_201 = 0xa; - } else if (priv->bb_pre_ed_rssi <= 51) { - ed_inx = 16; - cr_201 = 0x7; - } else if (priv->bb_pre_ed_rssi <= 53) { - ed_inx = 15; - cr_201 = 0x4; - } else if (priv->bb_pre_ed_rssi <= 55) { - ed_inx = 14; - cr_201 = 0x2; - cr_206 = 0xc0; - } else if (priv->bb_pre_ed_rssi <= 56) { - ed_inx = 13; - cr_201 = 0x2; - cr_206 = 0x30; - } else if (priv->bb_pre_ed_rssi <= 57) { - ed_inx = 12; - cr_201 = 0x1; - cr_206 = 0xb0; - } else if (priv->bb_pre_ed_rssi <= 58) { - ed_inx = 11; - cr_201 = 0x1; - cr_206 = 0x70; - } else if (priv->bb_pre_ed_rssi <= 59) { - ed_inx = 10; - cr_201 = 0x1; - cr_206 = 0x30; - } else if (priv->bb_pre_ed_rssi <= 60) { - ed_inx = 9; - cr_206 = 0xea; - } else if (priv->bb_pre_ed_rssi <= 61) { - ed_inx = 8; - cr_206 = 0xc0; - } else if (priv->bb_pre_ed_rssi <= 62) { - ed_inx = 7; - cr_206 = 0x9c; - } else if (priv->bb_pre_ed_rssi <= 63) { - ed_inx = 6; - cr_206 = 0x80; - } else if (priv->bb_pre_ed_rssi <= 64) { - ed_inx = 5; - cr_206 = 0x68; - } else if (priv->bb_pre_ed_rssi <= 65) { - ed_inx = 4; - cr_206 = 0x52; - } else if (priv->bb_pre_ed_rssi <= 66) { - ed_inx = 3; - cr_206 = 0x43; - } else if (priv->bb_pre_ed_rssi <= 67) { - ed_inx = 2; - cr_206 = 0x36; - } else if (priv->bb_pre_ed_rssi <= 68) { - ed_inx = 1; - cr_206 = 0x2d; - } else { - ed_inx = 0; - cr_206 = 0x24; - } + threshold = vt3226_vnt_threshold; + length = ARRAY_SIZE(vt3226_vnt_threshold); break; case RF_VT3342A0: - if (scanning) { /* need Max sensitivity */ - ed_inx = 0; - cr_206 = 0x38; - break; - } - - if (priv->bb_pre_ed_rssi <= 41) { - ed_inx = 20; - cr_201 = 0xff; - } else if (priv->bb_pre_ed_rssi <= 42) { - ed_inx = 19; - cr_201 = 0x36; - } else if (priv->bb_pre_ed_rssi <= 43) { - ed_inx = 18; - cr_201 = 0x26; - } else if (priv->bb_pre_ed_rssi <= 45) { - ed_inx = 17; - cr_201 = 0x18; - } else if (priv->bb_pre_ed_rssi <= 47) { - ed_inx = 16; - cr_201 = 0x11; - } else if (priv->bb_pre_ed_rssi <= 49) { - ed_inx = 15; - cr_201 = 0xa; - } else if (priv->bb_pre_ed_rssi <= 51) { - ed_inx = 14; - cr_201 = 0x7; - } else if (priv->bb_pre_ed_rssi <= 53) { - ed_inx = 13; - cr_201 = 0x4; - } else if (priv->bb_pre_ed_rssi <= 55) { - ed_inx = 12; - cr_201 = 0x2; - cr_206 = 0xc0; - } else if (priv->bb_pre_ed_rssi <= 56) { - ed_inx = 11; - cr_201 = 0x2; - cr_206 = 0x30; - } else if (priv->bb_pre_ed_rssi <= 57) { - ed_inx = 10; - cr_201 = 0x1; - cr_206 = 0xb0; - } else if (priv->bb_pre_ed_rssi <= 58) { - ed_inx = 9; - cr_201 = 0x1; - cr_206 = 0x70; - } else if (priv->bb_pre_ed_rssi <= 59) { - ed_inx = 8; - cr_201 = 0x1; - cr_206 = 0x30; - } else if (priv->bb_pre_ed_rssi <= 60) { - ed_inx = 7; - cr_206 = 0xea; - } else if (priv->bb_pre_ed_rssi <= 61) { - ed_inx = 6; - cr_206 = 0xc0; - } else if (priv->bb_pre_ed_rssi <= 62) { - ed_inx = 5; - cr_206 = 0x9c; - } else if (priv->bb_pre_ed_rssi <= 63) { - ed_inx = 4; - cr_206 = 0x80; - } else if (priv->bb_pre_ed_rssi <= 64) { - ed_inx = 3; - cr_206 = 0x68; - } else if (priv->bb_pre_ed_rssi <= 65) { - ed_inx = 2; - cr_206 = 0x52; - } else if (priv->bb_pre_ed_rssi <= 66) { - ed_inx = 1; - cr_206 = 0x43; - } else { - ed_inx = 0; - cr_206 = 0x38; - } + threshold = vt3342_vnt_threshold; + length = ARRAY_SIZE(vt3342_vnt_threshold); break; } + if (!threshold) + return -EINVAL; + + for (ed_inx = scanning ? 0 : length - 1; ed_inx > 0; ed_inx--) { + if (priv->bb_pre_ed_rssi <= threshold[ed_inx].bb_pre_ed_rssi) + break; + } + + cr_201 = threshold[ed_inx].cr_201; + cr_206 = threshold[ed_inx].cr_206; + if (ed_inx == priv->bb_pre_ed_index && !scanning) - return; + return 0; priv->bb_pre_ed_index = ed_inx; dev_dbg(&priv->usb->dev, "%s bb_pre_ed_rssi %d\n", __func__, priv->bb_pre_ed_rssi); - if (!cr_201 && !cr_206) - return; + ret = vnt_control_out_u8(priv, MESSAGE_REQUEST_BBREG, 0xc9, cr_201); + if (ret) + return ret; - vnt_control_out_u8(priv, MESSAGE_REQUEST_BBREG, 0xc9, cr_201); - vnt_control_out_u8(priv, MESSAGE_REQUEST_BBREG, 0xce, cr_206); + return vnt_control_out_u8(priv, MESSAGE_REQUEST_BBREG, 0xce, cr_206); } diff --git a/drivers/staging/vt6656/baseband.h b/drivers/staging/vt6656/baseband.h index dc42aa6ae1d9..12456ebc23ec 100644 --- a/drivers/staging/vt6656/baseband.h +++ b/drivers/staging/vt6656/baseband.h @@ -66,25 +66,12 @@ #define TOP_RATE_2M 0x00200000 #define TOP_RATE_1M 0x00100000 -/* Length, Service, and Signal fields of Phy for Tx */ -struct vnt_phy_field { - u8 signal; - u8 service; - __le16 len; -} __packed; - -unsigned int vnt_get_frame_time(u8 preamble_type, u8 pkt_type, - unsigned int frame_length, u16 tx_rate); - -void vnt_get_phy_field(struct vnt_private *priv, u32 frame_length, - u16 tx_rate, u8 pkt_type, struct vnt_phy_field *phy); - int vnt_set_short_slot_time(struct vnt_private *priv); -void vnt_set_vga_gain_offset(struct vnt_private *priv, u8 data); +int vnt_set_vga_gain_offset(struct vnt_private *priv, u8 data); int vnt_set_antenna_mode(struct vnt_private *priv, u8 antenna_mode); int vnt_vt3184_init(struct vnt_private *priv); int vnt_set_deep_sleep(struct vnt_private *priv); int vnt_exit_deep_sleep(struct vnt_private *priv); -void vnt_update_pre_ed_threshold(struct vnt_private *priv, int scanning); +int vnt_update_pre_ed_threshold(struct vnt_private *priv, int scanning); #endif /* __BASEBAND_H__ */ diff --git a/drivers/staging/vt6656/card.c b/drivers/staging/vt6656/card.c index dc3ab10eb630..10f3dfda83b5 100644 --- a/drivers/staging/vt6656/card.c +++ b/drivers/staging/vt6656/card.c @@ -26,7 +26,8 @@ * */ -#include +#include +#include #include "device.h" #include "card.h" #include "baseband.h" @@ -45,20 +46,12 @@ static const u16 cw_rxbcntsf_off[MAX_RATE] = { 192, 96, 34, 17, 34, 23, 17, 11, 8, 5, 4, 3 }; -/* - * Description: Set NIC media channel - * - * Parameters: - * In: - * pDevice - The adapter to be set - * connection_channel - Channel to be set - * Out: - * none - */ -void vnt_set_channel(struct vnt_private *priv, u32 connection_channel) +int vnt_set_channel(struct vnt_private *priv, u32 connection_channel) { + int ret; + if (connection_channel > CB_MAX_CHANNEL || !connection_channel) - return; + return -EINVAL; /* clear NAV */ vnt_mac_reg_bits_on(priv, MAC_REG_MACCR, MACCR_CLRNAV); @@ -67,284 +60,73 @@ void vnt_set_channel(struct vnt_private *priv, u32 connection_channel) vnt_mac_reg_bits_off(priv, MAC_REG_CHANNEL, (BIT(7) | BIT(5) | BIT(4))); - vnt_control_out(priv, MESSAGE_TYPE_SELECT_CHANNEL, - connection_channel, 0, 0, NULL); + ret = vnt_control_out(priv, MESSAGE_TYPE_SELECT_CHANNEL, + connection_channel, 0, 0, NULL); + if (ret) + return ret; - vnt_control_out_u8(priv, MESSAGE_REQUEST_MACREG, MAC_REG_CHANNEL, - (u8)(connection_channel | 0x80)); + return vnt_control_out_u8(priv, MESSAGE_REQUEST_MACREG, MAC_REG_CHANNEL, + (u8)(connection_channel | 0x80)); } -/* - * Description: Get CCK mode basic rate - * - * Parameters: - * In: - * priv - The adapter to be set - * rate_idx - Receiving data rate - * Out: - * none - * - * Return Value: response Control frame rate - * - */ -static u16 vnt_get_cck_rate(struct vnt_private *priv, u16 rate_idx) +static const u8 vnt_rspinf_b_short_table[] = { + 0x70, 0x00, 0x00, 0x00, 0x38, 0x00, 0x09, 0x00, + 0x15, 0x00, 0x0a, 0x00, 0x0b, 0x00, 0x0b, 0x80 +}; + +static const u8 vnt_rspinf_b_long_table[] = { + 0x70, 0x00, 0x00, 0x00, 0x38, 0x00, 0x01, 0x00, + 0x15, 0x00, 0x02, 0x00, 0x0b, 0x00, 0x03, 0x80 +}; + +static const u8 vnt_rspinf_a_table[] = { + 0x9b, 0x18, 0x9f, 0x10, 0x9a, 0x0a, 0x9e, 0x08, 0x99, + 0x08, 0x9d, 0x04, 0x98, 0x04, 0x9c, 0x04, 0x9c, 0x04 +}; + +static const u8 vnt_rspinf_gb_table[] = { + 0x8b, 0x1e, 0x8f, 0x16, 0x8a, 0x12, 0x8e, 0x0e, 0x89, + 0x0e, 0x8d, 0x0a, 0x88, 0x0a, 0x8c, 0x0a, 0x8c, 0x0a +}; + +int vnt_set_rspinf(struct vnt_private *priv, u8 bb_type) { - u16 ui = rate_idx; + const u8 *data; + u16 len; + int ret; - while (ui > RATE_1M) { - if (priv->basic_rates & (1 << ui)) - return ui; - ui--; + if (priv->preamble_type) { + data = vnt_rspinf_b_short_table; + len = ARRAY_SIZE(vnt_rspinf_b_short_table); + } else { + data = vnt_rspinf_b_long_table; + len = ARRAY_SIZE(vnt_rspinf_b_long_table); } - return RATE_1M; + /* RSPINF_b_1 to RSPINF_b_11 */ + ret = vnt_control_out(priv, MESSAGE_TYPE_WRITE, MAC_REG_RSPINF_B_1, + MESSAGE_REQUEST_MACREG, len, data); + if (ret) + return ret; + + if (bb_type == BB_TYPE_11A) { + data = vnt_rspinf_a_table; + len = ARRAY_SIZE(vnt_rspinf_a_table); + } else { + data = vnt_rspinf_gb_table; + len = ARRAY_SIZE(vnt_rspinf_gb_table); + } + + /* RSPINF_a_6 to RSPINF_a_72 */ + return vnt_control_out(priv, MESSAGE_TYPE_WRITE, MAC_REG_RSPINF_A_6, + MESSAGE_REQUEST_MACREG, len, data); } -/* - * Description: Get OFDM mode basic rate - * - * Parameters: - * In: - * priv - The adapter to be set - * rate_idx - Receiving data rate - * Out: - * none - * - * Return Value: response Control frame rate - * - */ -static u16 vnt_get_ofdm_rate(struct vnt_private *priv, u16 rate_idx) -{ - u16 ui = rate_idx; - - dev_dbg(&priv->usb->dev, "%s basic rate: %d\n", - __func__, priv->basic_rates); - - if (!vnt_ofdm_min_rate(priv)) { - dev_dbg(&priv->usb->dev, "%s (NO OFDM) %d\n", - __func__, rate_idx); - if (rate_idx > RATE_24M) - rate_idx = RATE_24M; - return rate_idx; - } - - while (ui > RATE_11M) { - if (priv->basic_rates & (1 << ui)) { - dev_dbg(&priv->usb->dev, "%s rate: %d\n", - __func__, ui); - return ui; - } - ui--; - } - - dev_dbg(&priv->usb->dev, "%s basic rate: 24M\n", __func__); - - return RATE_24M; -} - -/* - * Description: Calculate TxRate and RsvTime fields for RSPINF in OFDM mode. - * - * Parameters: - * In: - * rate - Tx Rate - * bb_type - Tx Packet type - * Out: - * tx_rate - pointer to RSPINF TxRate field - * rsv_time- pointer to RSPINF RsvTime field - * - * Return Value: none - * - */ -static void vnt_calculate_ofdm_rate(u16 rate, u8 bb_type, - u8 *tx_rate, u8 *rsv_time) -{ - switch (rate) { - case RATE_6M: - if (bb_type == BB_TYPE_11A) { - *tx_rate = 0x9b; - *rsv_time = 24; - } else { - *tx_rate = 0x8b; - *rsv_time = 30; - } - break; - case RATE_9M: - if (bb_type == BB_TYPE_11A) { - *tx_rate = 0x9f; - *rsv_time = 16; - } else { - *tx_rate = 0x8f; - *rsv_time = 22; - } - break; - case RATE_12M: - if (bb_type == BB_TYPE_11A) { - *tx_rate = 0x9a; - *rsv_time = 12; - } else { - *tx_rate = 0x8a; - *rsv_time = 18; - } - break; - case RATE_18M: - if (bb_type == BB_TYPE_11A) { - *tx_rate = 0x9e; - *rsv_time = 8; - } else { - *tx_rate = 0x8e; - *rsv_time = 14; - } - break; - case RATE_36M: - if (bb_type == BB_TYPE_11A) { - *tx_rate = 0x9d; - *rsv_time = 4; - } else { - *tx_rate = 0x8d; - *rsv_time = 10; - } - break; - case RATE_48M: - if (bb_type == BB_TYPE_11A) { - *tx_rate = 0x98; - *rsv_time = 4; - } else { - *tx_rate = 0x88; - *rsv_time = 10; - } - break; - case RATE_54M: - if (bb_type == BB_TYPE_11A) { - *tx_rate = 0x9c; - *rsv_time = 4; - } else { - *tx_rate = 0x8c; - *rsv_time = 10; - } - break; - case RATE_24M: - default: - if (bb_type == BB_TYPE_11A) { - *tx_rate = 0x99; - *rsv_time = 8; - } else { - *tx_rate = 0x89; - *rsv_time = 14; - } - break; - } -} - -/* - * Description: Set RSPINF - * - * Parameters: - * In: - * pDevice - The adapter to be set - * Out: - * none - * - * Return Value: None. - * - */ - -void vnt_set_rspinf(struct vnt_private *priv, u8 bb_type) -{ - struct vnt_phy_field phy[4]; - u8 tx_rate[9] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; /* For OFDM */ - u8 rsv_time[9] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; - u8 data[34]; - int i; - - /*RSPINF_b_1*/ - vnt_get_phy_field(priv, 14, vnt_get_cck_rate(priv, RATE_1M), - PK_TYPE_11B, &phy[0]); - - /*RSPINF_b_2*/ - vnt_get_phy_field(priv, 14, vnt_get_cck_rate(priv, RATE_2M), - PK_TYPE_11B, &phy[1]); - - /*RSPINF_b_5*/ - vnt_get_phy_field(priv, 14, vnt_get_cck_rate(priv, RATE_5M), - PK_TYPE_11B, &phy[2]); - - /*RSPINF_b_11*/ - vnt_get_phy_field(priv, 14, vnt_get_cck_rate(priv, RATE_11M), - PK_TYPE_11B, &phy[3]); - - /*RSPINF_a_6*/ - vnt_calculate_ofdm_rate(RATE_6M, bb_type, &tx_rate[0], &rsv_time[0]); - - /*RSPINF_a_9*/ - vnt_calculate_ofdm_rate(RATE_9M, bb_type, &tx_rate[1], &rsv_time[1]); - - /*RSPINF_a_12*/ - vnt_calculate_ofdm_rate(RATE_12M, bb_type, &tx_rate[2], &rsv_time[2]); - - /*RSPINF_a_18*/ - vnt_calculate_ofdm_rate(RATE_18M, bb_type, &tx_rate[3], &rsv_time[3]); - - /*RSPINF_a_24*/ - vnt_calculate_ofdm_rate(RATE_24M, bb_type, &tx_rate[4], &rsv_time[4]); - - /*RSPINF_a_36*/ - vnt_calculate_ofdm_rate(vnt_get_ofdm_rate(priv, RATE_36M), - bb_type, &tx_rate[5], &rsv_time[5]); - - /*RSPINF_a_48*/ - vnt_calculate_ofdm_rate(vnt_get_ofdm_rate(priv, RATE_48M), - bb_type, &tx_rate[6], &rsv_time[6]); - - /*RSPINF_a_54*/ - vnt_calculate_ofdm_rate(vnt_get_ofdm_rate(priv, RATE_54M), - bb_type, &tx_rate[7], &rsv_time[7]); - - /*RSPINF_a_72*/ - vnt_calculate_ofdm_rate(vnt_get_ofdm_rate(priv, RATE_54M), - bb_type, &tx_rate[8], &rsv_time[8]); - - put_unaligned(phy[0].len, (u16 *)&data[0]); - data[2] = phy[0].signal; - data[3] = phy[0].service; - - put_unaligned(phy[1].len, (u16 *)&data[4]); - data[6] = phy[1].signal; - data[7] = phy[1].service; - - put_unaligned(phy[2].len, (u16 *)&data[8]); - data[10] = phy[2].signal; - data[11] = phy[2].service; - - put_unaligned(phy[3].len, (u16 *)&data[12]); - data[14] = phy[3].signal; - data[15] = phy[3].service; - - for (i = 0; i < 9; i++) { - data[16 + i * 2] = tx_rate[i]; - data[16 + i * 2 + 1] = rsv_time[i]; - } - - vnt_control_out(priv, MESSAGE_TYPE_WRITE, MAC_REG_RSPINF_B_1, - MESSAGE_REQUEST_MACREG, 34, &data[0]); -} - -/* - * Description: Update IFS - * - * Parameters: - * In: - * priv - The adapter to be set - * Out: - * none - * - * Return Value: None. - * - */ -void vnt_update_ifs(struct vnt_private *priv) +int vnt_update_ifs(struct vnt_private *priv) { u8 max_min = 0; u8 data[4]; + int ret; if (priv->packet_type == PK_TYPE_11A) { priv->slot = C_SLOT_SHORT; @@ -367,89 +149,36 @@ void vnt_update_ifs(struct vnt_private *priv) priv->eifs = C_EIFS; - switch (priv->rf_type) { - case RF_VT3226D0: - if (priv->bb_type != BB_TYPE_11B) { - priv->sifs -= 1; - priv->difs -= 1; - break; - } - /* fall through */ - case RF_AIROHA7230: - case RF_AL2230: - case RF_AL2230S: - if (priv->bb_type != BB_TYPE_11B) - break; - /* fall through */ - case RF_RFMD2959: - case RF_VT3226: - case RF_VT3342A0: - priv->sifs -= 3; - priv->difs -= 3; - break; - case RF_MAXIM2829: - if (priv->bb_type == BB_TYPE_11A) { - priv->sifs -= 5; - priv->difs -= 5; - } else { - priv->sifs -= 2; - priv->difs -= 2; - } - - break; - } - data[0] = (u8)priv->sifs; data[1] = (u8)priv->difs; data[2] = (u8)priv->eifs; data[3] = (u8)priv->slot; - vnt_control_out(priv, MESSAGE_TYPE_WRITE, MAC_REG_SIFS, - MESSAGE_REQUEST_MACREG, 4, &data[0]); + ret = vnt_control_out(priv, MESSAGE_TYPE_WRITE, MAC_REG_SIFS, + MESSAGE_REQUEST_MACREG, 4, &data[0]); + if (ret) + return ret; max_min |= 0xa0; - vnt_control_out(priv, MESSAGE_TYPE_WRITE, MAC_REG_CWMAXMIN0, - MESSAGE_REQUEST_MACREG, 1, &max_min); + return vnt_control_out(priv, MESSAGE_TYPE_WRITE, MAC_REG_CWMAXMIN0, + MESSAGE_REQUEST_MACREG, 1, &max_min); } void vnt_update_top_rates(struct vnt_private *priv) { - u8 top_ofdm = RATE_24M, top_cck = RATE_1M; - u8 i; + int pos; - /*Determines the highest basic rate.*/ - for (i = RATE_54M; i >= RATE_6M; i--) { - if (priv->basic_rates & (u16)(1 << i)) { - top_ofdm = i; - break; - } - } + pos = fls(priv->basic_rates & GENMASK(RATE_54M, RATE_6M)); + priv->top_ofdm_basic_rate = pos ? (pos - 1) : RATE_24M; - priv->top_ofdm_basic_rate = top_ofdm; - - for (i = RATE_11M;; i--) { - if (priv->basic_rates & (u16)(1 << i)) { - top_cck = i; - break; - } - if (i == RATE_1M) - break; - } - - priv->top_cck_basic_rate = top_cck; + pos = fls(priv->basic_rates & GENMASK(RATE_11M, RATE_1M)); + priv->top_cck_basic_rate = pos ? (pos - 1) : RATE_1M; } -int vnt_ofdm_min_rate(struct vnt_private *priv) +bool vnt_ofdm_min_rate(struct vnt_private *priv) { - int ii; - - for (ii = RATE_54M; ii >= RATE_6M; ii--) { - if ((priv->basic_rates) & ((u16)BIT(ii))) - return true; - } - - return false; + return priv->basic_rates & GENMASK(RATE_54M, RATE_6M) ? true : false; } u8 vnt_get_pkt_type(struct vnt_private *priv) @@ -481,23 +210,8 @@ u64 vnt_get_tsf_offset(u8 rx_rate, u64 tsf1, u64 tsf2) return tsf1 - tsf2 - (u64)cw_rxbcntsf_off[rx_rate % MAX_RATE]; } -/* - * Description: Sync. TSF counter to BSS - * Get TSF offset and write to HW - * - * Parameters: - * In: - * priv - The adapter to be sync. - * time_stamp - Rx BCN's TSF - * local_tsf - Local TSF - * Out: - * none - * - * Return Value: none - * - */ -void vnt_adjust_tsf(struct vnt_private *priv, u8 rx_rate, - u64 time_stamp, u64 local_tsf) +int vnt_adjust_tsf(struct vnt_private *priv, u8 rx_rate, + u64 time_stamp, u64 local_tsf) { u64 tsf_offset = 0; u8 data[8]; @@ -513,8 +227,8 @@ void vnt_adjust_tsf(struct vnt_private *priv, u8 rx_rate, data[6] = (u8)(tsf_offset >> 48); data[7] = (u8)(tsf_offset >> 56); - vnt_control_out(priv, MESSAGE_TYPE_SET_TSFTBTT, - MESSAGE_REQUEST_TSF, 0, 8, data); + return vnt_control_out(priv, MESSAGE_TYPE_SET_TSFTBTT, + MESSAGE_REQUEST_TSF, 0, 8, data); } /* @@ -589,21 +303,7 @@ u64 vnt_get_next_tbtt(u64 tsf, u16 beacon_interval) return tsf; } -/* - * Description: Set NIC TSF counter for first Beacon time - * Get NEXTTBTT from adjusted TSF and Beacon Interval - * - * Parameters: - * In: - * dwIoBase - IO Base - * beacon_interval - Beacon Interval - * Out: - * none - * - * Return Value: none - * - */ -void vnt_reset_next_tbtt(struct vnt_private *priv, u16 beacon_interval) +int vnt_reset_next_tbtt(struct vnt_private *priv, u16 beacon_interval) { u64 next_tbtt = 0; u8 data[8]; @@ -621,29 +321,15 @@ void vnt_reset_next_tbtt(struct vnt_private *priv, u16 beacon_interval) data[6] = (u8)(next_tbtt >> 48); data[7] = (u8)(next_tbtt >> 56); - vnt_control_out(priv, MESSAGE_TYPE_SET_TSFTBTT, - MESSAGE_REQUEST_TBTT, 0, 8, data); + return vnt_control_out(priv, MESSAGE_TYPE_SET_TSFTBTT, + MESSAGE_REQUEST_TBTT, 0, 8, data); } -/* - * Description: Sync NIC TSF counter for Beacon time - * Get NEXTTBTT and write to HW - * - * Parameters: - * In: - * priv - The adapter to be set - * tsf - Current TSF counter - * beacon_interval - Beacon Interval - * Out: - * none - * - * Return Value: none - * - */ -void vnt_update_next_tbtt(struct vnt_private *priv, u64 tsf, - u16 beacon_interval) +int vnt_update_next_tbtt(struct vnt_private *priv, u64 tsf, + u16 beacon_interval) { u8 data[8]; + int ret; tsf = vnt_get_next_tbtt(tsf, beacon_interval); @@ -656,10 +342,13 @@ void vnt_update_next_tbtt(struct vnt_private *priv, u64 tsf, data[6] = (u8)(tsf >> 48); data[7] = (u8)(tsf >> 56); - vnt_control_out(priv, MESSAGE_TYPE_SET_TSFTBTT, - MESSAGE_REQUEST_TBTT, 0, 8, data); + ret = vnt_control_out(priv, MESSAGE_TYPE_SET_TSFTBTT, + MESSAGE_REQUEST_TBTT, 0, 8, data); + if (ret) + return ret; dev_dbg(&priv->usb->dev, "%s TBTT: %8llx\n", __func__, tsf); + return 0; } /* @@ -723,9 +412,13 @@ int vnt_radio_power_on(struct vnt_private *priv) { int ret = 0; - vnt_exit_deep_sleep(priv); + ret = vnt_exit_deep_sleep(priv); + if (ret) + return ret; - vnt_mac_reg_bits_on(priv, MAC_REG_HOSTCR, HOSTCR_RXON); + ret = vnt_mac_reg_bits_on(priv, MAC_REG_HOSTCR, HOSTCR_RXON); + if (ret) + return ret; switch (priv->rf_type) { case RF_AL2230: @@ -734,56 +427,69 @@ int vnt_radio_power_on(struct vnt_private *priv) case RF_VT3226: case RF_VT3226D0: case RF_VT3342A0: - vnt_mac_reg_bits_on(priv, MAC_REG_SOFTPWRCTL, - (SOFTPWRCTL_SWPE2 | SOFTPWRCTL_SWPE3)); - break; + ret = vnt_mac_reg_bits_on(priv, MAC_REG_SOFTPWRCTL, + (SOFTPWRCTL_SWPE2 | + SOFTPWRCTL_SWPE3)); + if (ret) + return ret; } - vnt_mac_reg_bits_off(priv, MAC_REG_GPIOCTL1, GPIO3_INTMD); - - return ret; + return vnt_mac_reg_bits_off(priv, MAC_REG_GPIOCTL1, GPIO3_INTMD); } -void vnt_set_bss_mode(struct vnt_private *priv) +int vnt_set_bss_mode(struct vnt_private *priv) { + int ret; + unsigned char type = priv->bb_type; + unsigned char data = 0; + unsigned char bb_vga_0 = 0x1c; + unsigned char bb_vga_2_3 = 0x00; + if (priv->rf_type == RF_AIROHA7230 && priv->bb_type == BB_TYPE_11A) - vnt_mac_set_bb_type(priv, BB_TYPE_11G); - else - vnt_mac_set_bb_type(priv, priv->bb_type); + type = BB_TYPE_11G; + + ret = vnt_mac_set_bb_type(priv, type); + if (ret) + return ret; priv->packet_type = vnt_get_pkt_type(priv); - if (priv->bb_type == BB_TYPE_11A) - vnt_control_out_u8(priv, MESSAGE_REQUEST_BBREG, 0x88, 0x03); - else if (priv->bb_type == BB_TYPE_11B) - vnt_control_out_u8(priv, MESSAGE_REQUEST_BBREG, 0x88, 0x02); - else if (priv->bb_type == BB_TYPE_11G) - vnt_control_out_u8(priv, MESSAGE_REQUEST_BBREG, 0x88, 0x08); - - vnt_update_ifs(priv); - vnt_set_rspinf(priv, (u8)priv->bb_type); - if (priv->bb_type == BB_TYPE_11A) { - if (priv->rf_type == RF_AIROHA7230) { - priv->bb_vga[0] = 0x20; - - vnt_control_out_u8(priv, MESSAGE_REQUEST_BBREG, - 0xe7, priv->bb_vga[0]); - } - - priv->bb_vga[2] = 0x10; - priv->bb_vga[3] = 0x10; - } else { - if (priv->rf_type == RF_AIROHA7230) { - priv->bb_vga[0] = 0x1c; - - vnt_control_out_u8(priv, MESSAGE_REQUEST_BBREG, - 0xe7, priv->bb_vga[0]); - } - - priv->bb_vga[2] = 0x0; - priv->bb_vga[3] = 0x0; + data = 0x03; + bb_vga_0 = 0x20; + bb_vga_2_3 = 0x10; + } else if (priv->bb_type == BB_TYPE_11B) { + data = 0x02; + } else if (priv->bb_type == BB_TYPE_11G) { + data = 0x08; } - vnt_set_vga_gain_offset(priv, priv->bb_vga[0]); + if (data) { + ret = vnt_control_out_u8(priv, MESSAGE_REQUEST_BBREG, + 0x88, data); + if (ret) + return ret; + } + + ret = vnt_update_ifs(priv); + if (ret) + return ret; + + ret = vnt_set_rspinf(priv, priv->bb_type); + if (ret) + return ret; + + if (priv->rf_type == RF_AIROHA7230) { + priv->bb_vga[0] = bb_vga_0; + + ret = vnt_control_out_u8(priv, MESSAGE_REQUEST_BBREG, + 0xe7, priv->bb_vga[0]); + if (ret) + return ret; + } + + priv->bb_vga[2] = bb_vga_2_3; + priv->bb_vga[3] = bb_vga_2_3; + + return vnt_set_vga_gain_offset(priv, priv->bb_vga[0]); } diff --git a/drivers/staging/vt6656/card.h b/drivers/staging/vt6656/card.h index 75cd340c0cce..a524fdc60ae3 100644 --- a/drivers/staging/vt6656/card.h +++ b/drivers/staging/vt6656/card.h @@ -25,23 +25,23 @@ struct vnt_private; -void vnt_set_channel(struct vnt_private *priv, u32 connection_channel); -void vnt_set_rspinf(struct vnt_private *priv, u8 bb_type); -void vnt_update_ifs(struct vnt_private *priv); +int vnt_set_channel(struct vnt_private *priv, u32 connection_channel); +int vnt_set_rspinf(struct vnt_private *priv, u8 bb_type); +int vnt_update_ifs(struct vnt_private *priv); void vnt_update_top_rates(struct vnt_private *priv); -int vnt_ofdm_min_rate(struct vnt_private *priv); -void vnt_adjust_tsf(struct vnt_private *priv, u8 rx_rate, - u64 time_stamp, u64 local_tsf); +bool vnt_ofdm_min_rate(struct vnt_private *priv); +int vnt_adjust_tsf(struct vnt_private *priv, u8 rx_rate, + u64 time_stamp, u64 local_tsf); bool vnt_get_current_tsf(struct vnt_private *priv, u64 *current_tsf); bool vnt_clear_current_tsf(struct vnt_private *priv); -void vnt_reset_next_tbtt(struct vnt_private *priv, u16 beacon_interval); -void vnt_update_next_tbtt(struct vnt_private *priv, u64 tsf, - u16 beacon_interval); +int vnt_reset_next_tbtt(struct vnt_private *priv, u16 beacon_interval); +int vnt_update_next_tbtt(struct vnt_private *priv, u64 tsf, + u16 beacon_interval); u64 vnt_get_next_tbtt(u64 tsf, u16 beacon_interval); u64 vnt_get_tsf_offset(u8 rx_rate, u64 tsf1, u64 tsf2); int vnt_radio_power_off(struct vnt_private *priv); int vnt_radio_power_on(struct vnt_private *priv); u8 vnt_get_pkt_type(struct vnt_private *priv); -void vnt_set_bss_mode(struct vnt_private *priv); +int vnt_set_bss_mode(struct vnt_private *priv); #endif /* __CARD_H__ */ diff --git a/drivers/staging/vt6656/device.h b/drivers/staging/vt6656/device.h index e6ee9411f080..947530fefe94 100644 --- a/drivers/staging/vt6656/device.h +++ b/drivers/staging/vt6656/device.h @@ -73,6 +73,10 @@ #define DEVICE_VERSION "mac80211" +#define FIRMWARE_VERSION 0x133 /* version 1.51 */ +#define FIRMWARE_NAME "vntwusb.fw" +#define FIRMWARE_CHUNK_SIZE 0x400 + #define CONFIG_PATH "/etc/vntconfiguration.dat" #define MAX_UINTS 8 @@ -202,8 +206,7 @@ struct vnt_rsp_card_init { * Enum of context types for SendPacket */ enum { - CONTEXT_DATA_PACKET = 1, - CONTEXT_MGMT_PACKET, + CONTEXT_DATA_PACKET = 0, CONTEXT_BEACON_PACKET }; @@ -234,18 +237,14 @@ struct vnt_rcb { struct vnt_usb_send_context { void *priv; struct sk_buff *skb; - struct urb *urb; - struct ieee80211_hdr *hdr; - unsigned int buf_len; + void *tx_buffer; u32 frame_len; u16 tx_hdr_size; u16 tx_rate; u8 type; u8 pkt_no; u8 pkt_type; - u8 need_ack; bool in_use; - unsigned char data[MAX_TOTAL_SIZE_WITH_ALL_HEADERS]; }; /* @@ -288,6 +287,7 @@ struct vnt_private { /* Variables to track resources for the BULK Out Pipe */ struct vnt_usb_send_context *tx_context[CB_MAX_TX_DESC]; + struct usb_anchor tx_submitted; u32 num_tx_context; /* Variables to track resources for the Interrupt In Pipe */ @@ -344,13 +344,9 @@ struct vnt_private { u8 ofdm_pwr_tbl[14]; u8 ofdm_a_pwr_tbl[42]; - u16 current_rate; u16 tx_rate_fb0; u16 tx_rate_fb1; - u8 short_retry_limit; - u8 long_retry_limit; - enum nl80211_iftype op_mode; int short_slot_time; @@ -383,8 +379,6 @@ struct vnt_private { u8 bb_pre_ed_rssi; u8 bb_pre_ed_index; - u16 wake_up_count; - /* command timer */ struct delayed_work run_command_work; diff --git a/drivers/staging/vt6656/firmware.c b/drivers/staging/vt6656/firmware.c deleted file mode 100644 index 70358d427211..000000000000 --- a/drivers/staging/vt6656/firmware.c +++ /dev/null @@ -1,106 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. - * All rights reserved. - * - * File: baseband.c - * - * Purpose: Implement functions to access baseband - * - * Author: Yiching Chen - * - * Date: May 20, 2004 - * - * Functions: - * - * Revision History: - * - */ - -#include -#include "firmware.h" -#include "usbpipe.h" - -#define FIRMWARE_VERSION 0x133 /* version 1.51 */ -#define FIRMWARE_NAME "vntwusb.fw" - -#define FIRMWARE_CHUNK_SIZE 0x400 - -int vnt_download_firmware(struct vnt_private *priv) -{ - struct device *dev = &priv->usb->dev; - const struct firmware *fw; - u16 length; - int ii; - int ret = 0; - - dev_dbg(dev, "---->Download firmware\n"); - - ret = request_firmware(&fw, FIRMWARE_NAME, dev); - if (ret) { - dev_err(dev, "firmware file %s request failed (%d)\n", - FIRMWARE_NAME, ret); - goto end; - } - - for (ii = 0; ii < fw->size; ii += FIRMWARE_CHUNK_SIZE) { - length = min_t(int, fw->size - ii, FIRMWARE_CHUNK_SIZE); - - ret = vnt_control_out(priv, 0, 0x1200 + ii, 0x0000, length, - fw->data + ii); - if (ret) - goto free_fw; - - dev_dbg(dev, "Download firmware...%d %zu\n", ii, fw->size); - } - -free_fw: - release_firmware(fw); -end: - return ret; -} -MODULE_FIRMWARE(FIRMWARE_NAME); - -int vnt_firmware_branch_to_sram(struct vnt_private *priv) -{ - dev_dbg(&priv->usb->dev, "---->Branch to Sram\n"); - - return vnt_control_out(priv, 1, 0x1200, 0x0000, 0, NULL); -} - -int vnt_check_firmware_version(struct vnt_private *priv) -{ - int ret = 0; - - ret = vnt_control_in(priv, MESSAGE_TYPE_READ, 0, - MESSAGE_REQUEST_VERSION, 2, - (u8 *)&priv->firmware_version); - if (ret) { - dev_dbg(&priv->usb->dev, - "Could not get firmware version: %d.\n", ret); - goto end; - } - - dev_dbg(&priv->usb->dev, "Firmware Version [%04x]\n", - priv->firmware_version); - - if (priv->firmware_version == 0xFFFF) { - dev_dbg(&priv->usb->dev, "In Loader.\n"); - ret = -EINVAL; - goto end; - } - - if (priv->firmware_version < FIRMWARE_VERSION) { - /* branch to loader for download new firmware */ - ret = vnt_firmware_branch_to_sram(priv); - if (ret) { - dev_dbg(&priv->usb->dev, - "Could not branch to SRAM: %d.\n", ret); - } else { - ret = -EINVAL; - } - } - -end: - return ret; -} diff --git a/drivers/staging/vt6656/firmware.h b/drivers/staging/vt6656/firmware.h deleted file mode 100644 index 161126faf396..000000000000 --- a/drivers/staging/vt6656/firmware.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. - * All rights reserved. - * - * File: firmware.h - * - * Purpose: Version and Release Information - * - * Author: Yiching Chen - * - * Date: May 20, 2004 - * - */ - -#ifndef __FIRMWARE_H__ -#define __FIRMWARE_H__ - -#include "device.h" - -int vnt_download_firmware(struct vnt_private *priv); -int vnt_firmware_branch_to_sram(struct vnt_private *priv); -int vnt_check_firmware_version(struct vnt_private *priv); - -#endif /* __FIRMWARE_H__ */ diff --git a/drivers/staging/vt6656/key.c b/drivers/staging/vt6656/key.c index ac3b188984d0..c66cb53cfc09 100644 --- a/drivers/staging/vt6656/key.c +++ b/drivers/staging/vt6656/key.c @@ -35,7 +35,7 @@ int vnt_key_init_table(struct vnt_private *priv) static int vnt_set_keymode(struct ieee80211_hw *hw, u8 *mac_addr, struct ieee80211_key_conf *key, u32 key_type, - u32 mode, bool onfly_latch) + u32 mode) { struct vnt_private *priv = hw->priv; u8 broadcast[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; @@ -68,17 +68,11 @@ static int vnt_set_keymode(struct ieee80211_hw *hw, u8 *mac_addr, entry = MAX_KEY_TABLE - 1; key->hw_key_idx = entry; /* fall through */ - case VNT_KEY_ALLGROUP: - key_mode |= VNT_KEY_ALLGROUP; - if (onfly_latch) - key_mode |= VNT_KEY_ONFLY_ALL; - /* fall through */ case VNT_KEY_GROUP_ADDRESS: - key_mode |= mode; - /* fall through */ + key_mode = mode | (mode << 4); + break; case VNT_KEY_GROUP: - key_mode |= (mode << 4); - key_mode |= VNT_KEY_GROUP; + key_mode = mode << 4; break; case VNT_KEY_PAIRWISE: key_mode |= mode; @@ -88,8 +82,7 @@ static int vnt_set_keymode(struct ieee80211_hw *hw, u8 *mac_addr, return -EINVAL; } - if (onfly_latch) - key_mode |= VNT_KEY_ONFLY; + key_mode |= key_type; if (mode == KEY_CTL_WEP) { if (key->keylen == WLAN_KEY_LEN_WEP40) @@ -98,9 +91,8 @@ static int vnt_set_keymode(struct ieee80211_hw *hw, u8 *mac_addr, key->key[15] |= 0x80; } - vnt_mac_set_keyentry(priv, key_mode, entry, key_inx, bssid, key->key); - - return 0; + return vnt_mac_set_keyentry(priv, key_mode, entry, + key_inx, bssid, key->key); } int vnt_set_keys(struct ieee80211_hw *hw, struct ieee80211_sta *sta, @@ -109,28 +101,21 @@ int vnt_set_keys(struct ieee80211_hw *hw, struct ieee80211_sta *sta, struct vnt_private *priv = hw->priv; u8 *mac_addr = NULL; u8 key_dec_mode = 0; - int ret = 0, u; if (sta) mac_addr = &sta->addr[0]; switch (key->cipher) { - case 0: - for (u = 0 ; u < MAX_KEY_TABLE; u++) - vnt_mac_disable_keyentry(priv, u); - return ret; - case WLAN_CIPHER_SUITE_WEP40: case WLAN_CIPHER_SUITE_WEP104: - for (u = 0; u < MAX_KEY_TABLE; u++) - vnt_mac_disable_keyentry(priv, u); - vnt_set_keymode(hw, mac_addr, key, VNT_KEY_DEFAULTKEY, - KEY_CTL_WEP, true); + KEY_CTL_WEP); key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; - return ret; + return vnt_set_keymode(hw, mac_addr, key, VNT_KEY_DEFAULTKEY, + KEY_CTL_WEP); + case WLAN_CIPHER_SUITE_TKIP: key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; @@ -151,11 +136,9 @@ int vnt_set_keys(struct ieee80211_hw *hw, struct ieee80211_sta *sta, } if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) - vnt_set_keymode(hw, mac_addr, key, VNT_KEY_PAIRWISE, - key_dec_mode, true); - else - vnt_set_keymode(hw, mac_addr, key, VNT_KEY_GROUP_ADDRESS, - key_dec_mode, true); + return vnt_set_keymode(hw, mac_addr, key, VNT_KEY_PAIRWISE, + key_dec_mode); - return 0; + return vnt_set_keymode(hw, mac_addr, key, + VNT_KEY_GROUP_ADDRESS, key_dec_mode); } diff --git a/drivers/staging/vt6656/key.h b/drivers/staging/vt6656/key.h index 918c07cf86cd..1f3449e66143 100644 --- a/drivers/staging/vt6656/key.h +++ b/drivers/staging/vt6656/key.h @@ -25,13 +25,14 @@ #define KEY_CTL_TKIP 0x02 #define KEY_CTL_CCMP 0x03 -#define VNT_KEY_DEFAULTKEY 0x1 -#define VNT_KEY_GROUP_ADDRESS 0x2 -#define VNT_KEY_ALLGROUP 0x4 -#define VNT_KEY_GROUP 0x40 -#define VNT_KEY_PAIRWISE 0x00 -#define VNT_KEY_ONFLY 0x8000 #define VNT_KEY_ONFLY_ALL 0x4000 +#define VNT_KEY_ONFLY 0x8000 +#define VNT_KEY_ALLGROUP 0x04 +#define VNT_KEY_GROUP 0x40 +#define VNT_KEY_PAIRWISE VNT_KEY_ONFLY +#define VNT_KEY_GROUP_ADDRESS (VNT_KEY_ALLGROUP | VNT_KEY_GROUP) +#define VNT_KEY_DEFAULTKEY (VNT_KEY_GROUP_ADDRESS | VNT_KEY_ONFLY |\ + VNT_KEY_ONFLY_ALL) int vnt_key_init_table(struct vnt_private *priv); diff --git a/drivers/staging/vt6656/mac.c b/drivers/staging/vt6656/mac.c index 5cacf6e60e90..da7067c34643 100644 --- a/drivers/staging/vt6656/mac.c +++ b/drivers/staging/vt6656/mac.c @@ -22,90 +22,40 @@ #include "mac.h" #include "usbpipe.h" -/* - * Description: - * Write MAC Multicast Address Mask - * - * Parameters: - * In: - * mc_filter (mac filter) - * Out: - * none - * - * Return Value: none - * - */ -void vnt_mac_set_filter(struct vnt_private *priv, u64 mc_filter) +int vnt_mac_set_filter(struct vnt_private *priv, u64 mc_filter) { __le64 le_mc = cpu_to_le64(mc_filter); - vnt_control_out(priv, MESSAGE_TYPE_WRITE, MAC_REG_MAR0, - MESSAGE_REQUEST_MACREG, sizeof(le_mc), (u8 *)&le_mc); + return vnt_control_out(priv, MESSAGE_TYPE_WRITE, MAC_REG_MAR0, + MESSAGE_REQUEST_MACREG, sizeof(le_mc), + (u8 *)&le_mc); } -/* - * Description: - * Shut Down MAC - * - * Parameters: - * In: - * Out: - * none - * - * - */ -void vnt_mac_shutdown(struct vnt_private *priv) +int vnt_mac_shutdown(struct vnt_private *priv) { - vnt_control_out(priv, MESSAGE_TYPE_MACSHUTDOWN, 0, 0, 0, NULL); + return vnt_control_out(priv, MESSAGE_TYPE_MACSHUTDOWN, 0, 0, 0, NULL); } -void vnt_mac_set_bb_type(struct vnt_private *priv, u8 type) +int vnt_mac_set_bb_type(struct vnt_private *priv, u8 type) { u8 data[2]; data[0] = type; data[1] = EnCFG_BBType_MASK; - vnt_control_out(priv, MESSAGE_TYPE_WRITE_MASK, MAC_REG_ENCFG0, - MESSAGE_REQUEST_MACREG, ARRAY_SIZE(data), data); + return vnt_control_out(priv, MESSAGE_TYPE_WRITE_MASK, MAC_REG_ENCFG0, + MESSAGE_REQUEST_MACREG, ARRAY_SIZE(data), + data); } -/* - * Description: - * Disable the Key Entry by MISCFIFO - * - * Parameters: - * In: - * dwIoBase - Base Address for MAC - * - * Out: - * none - * - * Return Value: none - * - */ -void vnt_mac_disable_keyentry(struct vnt_private *priv, u8 entry_idx) +int vnt_mac_disable_keyentry(struct vnt_private *priv, u8 entry_idx) { - vnt_control_out(priv, MESSAGE_TYPE_CLRKEYENTRY, 0, 0, - sizeof(entry_idx), &entry_idx); + return vnt_control_out(priv, MESSAGE_TYPE_CLRKEYENTRY, 0, 0, + sizeof(entry_idx), &entry_idx); } -/* - * Description: - * Set the Key by MISCFIFO - * - * Parameters: - * In: - * dwIoBase - Base Address for MAC - * - * Out: - * none - * - * Return Value: none - * - */ -void vnt_mac_set_keyentry(struct vnt_private *priv, u16 key_ctl, u32 entry_idx, - u32 key_idx, u8 *addr, u8 *key) +int vnt_mac_set_keyentry(struct vnt_private *priv, u16 key_ctl, u32 entry_idx, + u32 key_idx, u8 *addr, u8 *key) { struct vnt_mac_set_key set_key; u16 offset; @@ -124,9 +74,9 @@ void vnt_mac_set_keyentry(struct vnt_private *priv, u16 key_ctl, u32 entry_idx, dev_dbg(&priv->usb->dev, "offset %d key ctl %d set key %24ph\n", offset, key_ctl, (u8 *)&set_key); - vnt_control_out(priv, MESSAGE_TYPE_SETKEY, offset, - (u16)key_idx, sizeof(struct vnt_mac_set_key), - (u8 *)&set_key); + return vnt_control_out(priv, MESSAGE_TYPE_SETKEY, offset, + (u16)key_idx, sizeof(struct vnt_mac_set_key), + (u8 *)&set_key); } int vnt_mac_reg_bits_off(struct vnt_private *priv, u8 reg_ofs, u8 bits) @@ -151,76 +101,76 @@ int vnt_mac_reg_bits_on(struct vnt_private *priv, u8 reg_ofs, u8 bits) MESSAGE_REQUEST_MACREG, ARRAY_SIZE(data), data); } -void vnt_mac_write_word(struct vnt_private *priv, u8 reg_ofs, u16 word) +int vnt_mac_write_word(struct vnt_private *priv, u8 reg_ofs, u16 word) { u8 data[2]; data[0] = (u8)(word & 0xff); data[1] = (u8)(word >> 8); - vnt_control_out(priv, MESSAGE_TYPE_WRITE, reg_ofs, - MESSAGE_REQUEST_MACREG, ARRAY_SIZE(data), data); + return vnt_control_out(priv, MESSAGE_TYPE_WRITE, reg_ofs, + MESSAGE_REQUEST_MACREG, ARRAY_SIZE(data), data); } -void vnt_mac_set_bssid_addr(struct vnt_private *priv, u8 *addr) +int vnt_mac_set_bssid_addr(struct vnt_private *priv, u8 *addr) { - vnt_control_out(priv, MESSAGE_TYPE_WRITE, MAC_REG_BSSID0, - MESSAGE_REQUEST_MACREG, ETH_ALEN, addr); + return vnt_control_out(priv, MESSAGE_TYPE_WRITE, MAC_REG_BSSID0, + MESSAGE_REQUEST_MACREG, ETH_ALEN, addr); } -void vnt_mac_enable_protect_mode(struct vnt_private *priv) +int vnt_mac_enable_protect_mode(struct vnt_private *priv) { u8 data[2]; data[0] = EnCFG_ProtectMd; data[1] = EnCFG_ProtectMd; - vnt_control_out(priv, MESSAGE_TYPE_WRITE_MASK, MAC_REG_ENCFG0, - MESSAGE_REQUEST_MACREG, ARRAY_SIZE(data), data); + return vnt_control_out(priv, MESSAGE_TYPE_WRITE_MASK, MAC_REG_ENCFG0, + MESSAGE_REQUEST_MACREG, ARRAY_SIZE(data), data); } -void vnt_mac_disable_protect_mode(struct vnt_private *priv) +int vnt_mac_disable_protect_mode(struct vnt_private *priv) { u8 data[2]; data[0] = 0; data[1] = EnCFG_ProtectMd; - vnt_control_out(priv, MESSAGE_TYPE_WRITE_MASK, MAC_REG_ENCFG0, - MESSAGE_REQUEST_MACREG, ARRAY_SIZE(data), data); + return vnt_control_out(priv, MESSAGE_TYPE_WRITE_MASK, MAC_REG_ENCFG0, + MESSAGE_REQUEST_MACREG, ARRAY_SIZE(data), data); } -void vnt_mac_enable_barker_preamble_mode(struct vnt_private *priv) +int vnt_mac_enable_barker_preamble_mode(struct vnt_private *priv) { u8 data[2]; data[0] = EnCFG_BarkerPream; data[1] = EnCFG_BarkerPream; - vnt_control_out(priv, MESSAGE_TYPE_WRITE_MASK, MAC_REG_ENCFG2, - MESSAGE_REQUEST_MACREG, ARRAY_SIZE(data), data); + return vnt_control_out(priv, MESSAGE_TYPE_WRITE_MASK, MAC_REG_ENCFG2, + MESSAGE_REQUEST_MACREG, ARRAY_SIZE(data), data); } -void vnt_mac_disable_barker_preamble_mode(struct vnt_private *priv) +int vnt_mac_disable_barker_preamble_mode(struct vnt_private *priv) { u8 data[2]; data[0] = 0; data[1] = EnCFG_BarkerPream; - vnt_control_out(priv, MESSAGE_TYPE_WRITE_MASK, MAC_REG_ENCFG2, - MESSAGE_REQUEST_MACREG, ARRAY_SIZE(data), data); + return vnt_control_out(priv, MESSAGE_TYPE_WRITE_MASK, MAC_REG_ENCFG2, + MESSAGE_REQUEST_MACREG, ARRAY_SIZE(data), data); } -void vnt_mac_set_beacon_interval(struct vnt_private *priv, u16 interval) +int vnt_mac_set_beacon_interval(struct vnt_private *priv, u16 interval) { u8 data[2]; data[0] = (u8)(interval & 0xff); data[1] = (u8)(interval >> 8); - vnt_control_out(priv, MESSAGE_TYPE_WRITE, MAC_REG_BI, - MESSAGE_REQUEST_MACREG, ARRAY_SIZE(data), data); + return vnt_control_out(priv, MESSAGE_TYPE_WRITE, MAC_REG_BI, + MESSAGE_REQUEST_MACREG, ARRAY_SIZE(data), data); } int vnt_mac_set_led(struct vnt_private *priv, u8 state, u8 led) diff --git a/drivers/staging/vt6656/mac.h b/drivers/staging/vt6656/mac.h index c532b27de37f..dae70b5c7634 100644 --- a/drivers/staging/vt6656/mac.h +++ b/drivers/staging/vt6656/mac.h @@ -177,7 +177,7 @@ #define EnCFG_BBType_a 0x00 #define EnCFG_BBType_b BIT(0) #define EnCFG_BBType_g BIT(1) -#define EnCFG_BBType_MASK (BIT(0) | BIT(1)) +#define EnCFG_BBType_MASK (EnCFG_BBType_b | EnCFG_BBType_g) #define EnCFG_ProtectMd BIT(5) /* Bits in the EnhanceCFG_1 register */ @@ -355,21 +355,21 @@ struct vnt_mac_set_key { u8 key[WLAN_KEY_LEN_CCMP]; } __packed; -void vnt_mac_set_filter(struct vnt_private *priv, u64 mc_filter); -void vnt_mac_shutdown(struct vnt_private *priv); -void vnt_mac_set_bb_type(struct vnt_private *priv, u8 type); -void vnt_mac_disable_keyentry(struct vnt_private *priv, u8 entry_idx); -void vnt_mac_set_keyentry(struct vnt_private *priv, u16 key_ctl, u32 entry_idx, - u32 key_idx, u8 *addr, u8 *key); +int vnt_mac_set_filter(struct vnt_private *priv, u64 mc_filter); +int vnt_mac_shutdown(struct vnt_private *priv); +int vnt_mac_set_bb_type(struct vnt_private *priv, u8 type); +int vnt_mac_disable_keyentry(struct vnt_private *priv, u8 entry_idx); +int vnt_mac_set_keyentry(struct vnt_private *priv, u16 key_ctl, u32 entry_idx, + u32 key_idx, u8 *addr, u8 *key); int vnt_mac_reg_bits_off(struct vnt_private *priv, u8 reg_ofs, u8 bits); int vnt_mac_reg_bits_on(struct vnt_private *priv, u8 reg_ofs, u8 bits); -void vnt_mac_write_word(struct vnt_private *priv, u8 reg_ofs, u16 word); -void vnt_mac_set_bssid_addr(struct vnt_private *priv, u8 *addr); -void vnt_mac_enable_protect_mode(struct vnt_private *priv); -void vnt_mac_disable_protect_mode(struct vnt_private *priv); -void vnt_mac_enable_barker_preamble_mode(struct vnt_private *priv); -void vnt_mac_disable_barker_preamble_mode(struct vnt_private *priv); -void vnt_mac_set_beacon_interval(struct vnt_private *priv, u16 interval); +int vnt_mac_write_word(struct vnt_private *priv, u8 reg_ofs, u16 word); +int vnt_mac_set_bssid_addr(struct vnt_private *priv, u8 *addr); +int vnt_mac_enable_protect_mode(struct vnt_private *priv); +int vnt_mac_disable_protect_mode(struct vnt_private *priv); +int vnt_mac_enable_barker_preamble_mode(struct vnt_private *priv); +int vnt_mac_disable_barker_preamble_mode(struct vnt_private *priv); +int vnt_mac_set_beacon_interval(struct vnt_private *priv, u16 interval); int vnt_mac_set_led(struct vnt_private *privpriv, u8 state, u8 led); #endif /* __MAC_H__ */ diff --git a/drivers/staging/vt6656/main_usb.c b/drivers/staging/vt6656/main_usb.c index 5f78cad3b647..8bf851c53f4e 100644 --- a/drivers/staging/vt6656/main_usb.c +++ b/drivers/staging/vt6656/main_usb.c @@ -33,7 +33,6 @@ #include "wcmd.h" #include "rxtx.h" #include "rf.h" -#include "firmware.h" #include "usbpipe.h" #include "channel.h" @@ -60,8 +59,6 @@ MODULE_PARM_DESC(tx_buffers, "Number of receive usb tx buffers"); #define RTS_THRESH_DEF 2347 #define FRAG_THRESH_DEF 2346 -#define SHORT_RETRY_DEF 8 -#define LONG_RETRY_DEF 4 /* BasebandType[] baseband type selected * 0: indicate 802.11a type @@ -94,15 +91,91 @@ static void vnt_set_options(struct vnt_private *priv) else priv->num_rcb = vnt_rx_buffers; - priv->short_retry_limit = SHORT_RETRY_DEF; - priv->long_retry_limit = LONG_RETRY_DEF; priv->op_mode = NL80211_IFTYPE_UNSPECIFIED; priv->bb_type = BBP_TYPE_DEF; priv->packet_type = priv->bb_type; - priv->preamble_type = 0; + priv->preamble_type = PREAMBLE_LONG; priv->exist_sw_net_addr = false; } +static int vnt_download_firmware(struct vnt_private *priv) +{ + struct device *dev = &priv->usb->dev; + const struct firmware *fw; + u16 length; + int ii; + int ret = 0; + + dev_dbg(dev, "---->Download firmware\n"); + + ret = request_firmware(&fw, FIRMWARE_NAME, dev); + if (ret) { + dev_err(dev, "firmware file %s request failed (%d)\n", + FIRMWARE_NAME, ret); + goto end; + } + + for (ii = 0; ii < fw->size; ii += FIRMWARE_CHUNK_SIZE) { + length = min_t(int, fw->size - ii, FIRMWARE_CHUNK_SIZE); + + ret = vnt_control_out(priv, 0, 0x1200 + ii, 0x0000, length, + fw->data + ii); + if (ret) + goto free_fw; + + dev_dbg(dev, "Download firmware...%d %zu\n", ii, fw->size); + } + +free_fw: + release_firmware(fw); +end: + return ret; +} + +static int vnt_firmware_branch_to_sram(struct vnt_private *priv) +{ + dev_dbg(&priv->usb->dev, "---->Branch to Sram\n"); + + return vnt_control_out(priv, 1, 0x1200, 0x0000, 0, NULL); +} + +static int vnt_check_firmware_version(struct vnt_private *priv) +{ + int ret = 0; + + ret = vnt_control_in(priv, MESSAGE_TYPE_READ, 0, + MESSAGE_REQUEST_VERSION, 2, + (u8 *)&priv->firmware_version); + if (ret) { + dev_dbg(&priv->usb->dev, + "Could not get firmware version: %d.\n", ret); + goto end; + } + + dev_dbg(&priv->usb->dev, "Firmware Version [%04x]\n", + priv->firmware_version); + + if (priv->firmware_version == 0xFFFF) { + dev_dbg(&priv->usb->dev, "In Loader.\n"); + ret = -EINVAL; + goto end; + } + + if (priv->firmware_version < FIRMWARE_VERSION) { + /* branch to loader for download new firmware */ + ret = vnt_firmware_branch_to_sram(priv); + if (ret) { + dev_dbg(&priv->usb->dev, + "Could not branch to SRAM: %d.\n", ret); + } else { + ret = -EINVAL; + } + } + +end: + return ret; +} + /* * initialization of MAC & BBP registers */ @@ -146,8 +219,8 @@ static int vnt_init_registers(struct vnt_private *priv) init_cmd->exist_sw_net_addr = priv->exist_sw_net_addr; for (ii = 0; ii < ARRAY_SIZE(init_cmd->sw_net_addr); ii++) init_cmd->sw_net_addr[ii] = priv->current_net_addr[ii]; - init_cmd->short_retry_limit = priv->short_retry_limit; - init_cmd->long_retry_limit = priv->long_retry_limit; + init_cmd->short_retry_limit = priv->hw->wiphy->retry_short; + init_cmd->long_retry_limit = priv->hw->wiphy->retry_long; /* issue card_init command to device */ ret = vnt_control_out(priv, MESSAGE_TYPE_CARDINIT, 0, 0, @@ -324,19 +397,6 @@ static int vnt_init_registers(struct vnt_private *priv) dev_dbg(&priv->usb->dev, "Network address = %pM\n", priv->current_net_addr); - /* - * set BB and packet type at the same time - * set Short Slot Time, xIFS, and RSPINF - */ - if (priv->bb_type == BB_TYPE_11A) - priv->short_slot_time = true; - else - priv->short_slot_time = false; - - ret = vnt_set_short_slot_time(priv); - if (ret) - goto end; - priv->radio_ctl = priv->eeprom[EEP_OFS_RADIOCTL]; if ((priv->radio_ctl & EEP_RADIOCTL_ENABLE) != 0) { @@ -385,17 +445,13 @@ static void vnt_free_tx_bufs(struct vnt_private *priv) struct vnt_usb_send_context *tx_context; int ii; + usb_kill_anchored_urbs(&priv->tx_submitted); + for (ii = 0; ii < priv->num_tx_context; ii++) { tx_context = priv->tx_context[ii]; if (!tx_context) continue; - /* deallocate URBs */ - if (tx_context->urb) { - usb_kill_urb(tx_context->urb); - usb_free_urb(tx_context->urb); - } - kfree(tx_context); } } @@ -436,6 +492,8 @@ static int vnt_alloc_bufs(struct vnt_private *priv) struct vnt_rcb *rcb; int ii; + init_usb_anchor(&priv->tx_submitted); + for (ii = 0; ii < priv->num_tx_context; ii++) { tx_context = kmalloc(sizeof(*tx_context), GFP_KERNEL); if (!tx_context) { @@ -446,14 +504,6 @@ static int vnt_alloc_bufs(struct vnt_private *priv) priv->tx_context[ii] = tx_context; tx_context->priv = priv; tx_context->pkt_no = ii; - - /* allocate URBs */ - tx_context->urb = usb_alloc_urb(0, GFP_KERNEL); - if (!tx_context->urb) { - ret = -ENOMEM; - goto free_tx; - } - tx_context->in_use = false; } @@ -683,15 +733,14 @@ static int vnt_config(struct ieee80211_hw *hw, u32 changed) priv->bb_type = BB_TYPE_11G; } - if (changed & IEEE80211_CONF_CHANGE_POWER) { - if (priv->bb_type == BB_TYPE_11B) - priv->current_rate = RATE_1M; - else - priv->current_rate = RATE_54M; + if (changed & IEEE80211_CONF_CHANGE_POWER) + vnt_rf_setpower(priv, conf->chandef.chan); - vnt_rf_setpower(priv, priv->current_rate, - conf->chandef.chan->hw_value); - } + if (conf->flags & (IEEE80211_CONF_OFFCHANNEL | IEEE80211_CONF_IDLE)) + /* Set max sensitivity*/ + vnt_update_pre_ed_threshold(priv, true); + else + vnt_update_pre_ed_threshold(priv, false); return 0; } @@ -718,10 +767,10 @@ static void vnt_bss_info_changed(struct ieee80211_hw *hw, if (changed & BSS_CHANGED_ERP_PREAMBLE) { if (conf->use_short_preamble) { vnt_mac_enable_barker_preamble_mode(priv); - priv->preamble_type = true; + priv->preamble_type = PREAMBLE_SHORT; } else { vnt_mac_disable_barker_preamble_mode(priv); - priv->preamble_type = false; + priv->preamble_type = PREAMBLE_LONG; } } @@ -740,16 +789,14 @@ static void vnt_bss_info_changed(struct ieee80211_hw *hw, vnt_set_short_slot_time(priv); vnt_set_vga_gain_offset(priv, priv->bb_vga[0]); - vnt_update_pre_ed_threshold(priv, false); } if (changed & (BSS_CHANGED_BASIC_RATES | BSS_CHANGED_ERP_PREAMBLE | BSS_CHANGED_ERP_SLOT)) vnt_set_bss_mode(priv); - if (changed & BSS_CHANGED_TXPOWER) - vnt_rf_setpower(priv, priv->current_rate, - conf->chandef.chan->hw_value); + if (changed & (BSS_CHANGED_TXPOWER | BSS_CHANGED_BANDWIDTH)) + vnt_rf_setpower(priv, conf->chandef.chan); if (changed & BSS_CHANGED_BEACON_ENABLED) { dev_dbg(&priv->usb->dev, @@ -767,10 +814,17 @@ static void vnt_bss_info_changed(struct ieee80211_hw *hw, if (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BEACON_INFO) && priv->op_mode != NL80211_IFTYPE_AP) { if (conf->assoc && conf->beacon_rate) { + u16 ps_beacon_int = conf->beacon_int; + + if (conf->dtim_period) + ps_beacon_int *= conf->dtim_period; + else if (hw->conf.listen_interval) + ps_beacon_int *= hw->conf.listen_interval; + vnt_mac_reg_bits_on(priv, MAC_REG_TFTCTL, TFTCTL_TSFCNTREN); - vnt_mac_set_beacon_interval(priv, conf->beacon_int); + vnt_mac_set_beacon_interval(priv, ps_beacon_int); vnt_reset_next_tbtt(priv, conf->beacon_int); @@ -778,7 +832,7 @@ static void vnt_bss_info_changed(struct ieee80211_hw *hw, conf->sync_tsf, priv->current_tsf); vnt_update_next_tbtt(priv, - conf->sync_tsf, conf->beacon_int); + conf->sync_tsf, ps_beacon_int); } else { vnt_clear_current_tsf(priv); @@ -868,25 +922,6 @@ static int vnt_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, return 0; } -static void vnt_sw_scan_start(struct ieee80211_hw *hw, - struct ieee80211_vif *vif, - const u8 *addr) -{ - struct vnt_private *priv = hw->priv; - - /* Set max sensitivity*/ - vnt_update_pre_ed_threshold(priv, true); -} - -static void vnt_sw_scan_complete(struct ieee80211_hw *hw, - struct ieee80211_vif *vif) -{ - struct vnt_private *priv = hw->priv; - - /* Return sensitivity to channel level*/ - vnt_update_pre_ed_threshold(priv, false); -} - static int vnt_get_stats(struct ieee80211_hw *hw, struct ieee80211_low_level_stats *stats) { @@ -932,8 +967,6 @@ static const struct ieee80211_ops vnt_mac_ops = { .prepare_multicast = vnt_prepare_multicast, .configure_filter = vnt_configure, .set_key = vnt_set_key, - .sw_scan_start = vnt_sw_scan_start, - .sw_scan_complete = vnt_sw_scan_complete, .get_stats = vnt_get_stats, .get_tsf = vnt_get_tsf, .set_tsf = vnt_set_tsf, @@ -1010,6 +1043,8 @@ vt6656_probe(struct usb_interface *intf, const struct usb_device_id *id) ieee80211_hw_set(priv->hw, SUPPORTS_PS); ieee80211_hw_set(priv->hw, PS_NULLFUNC_STACK); + priv->hw->extra_tx_headroom = + sizeof(struct vnt_tx_buffer) + sizeof(struct vnt_tx_usb_header); priv->hw->max_signal = 100; SET_IEEE80211_DEV(priv->hw, &intf->dev); @@ -1078,3 +1113,5 @@ static struct usb_driver vt6656_driver = { }; module_usb_driver(vt6656_driver); + +MODULE_FIRMWARE(FIRMWARE_NAME); diff --git a/drivers/staging/vt6656/power.c b/drivers/staging/vt6656/power.c index 7a086c72d5a8..2f49c870272a 100644 --- a/drivers/staging/vt6656/power.c +++ b/drivers/staging/vt6656/power.c @@ -63,41 +63,29 @@ void vnt_enable_power_saving(struct vnt_private *priv, u16 listen_interval) */ vnt_mac_reg_bits_on(priv, MAC_REG_PSCTL, PSCTL_GO2DOZE); - if (listen_interval >= 2) { - /* clear always listen beacon */ - vnt_mac_reg_bits_off(priv, MAC_REG_PSCTL, PSCTL_ALBCN); - - /* first time set listen next beacon */ - vnt_mac_reg_bits_on(priv, MAC_REG_PSCTL, PSCTL_LNBCN); - } else { - /* always listen beacon */ - vnt_mac_reg_bits_on(priv, MAC_REG_PSCTL, PSCTL_ALBCN); - } + /* always listen beacon */ + vnt_mac_reg_bits_on(priv, MAC_REG_PSCTL, PSCTL_ALBCN); dev_dbg(&priv->usb->dev, "PS:Power Saving Mode Enable...\n"); } -/* - * - * Routine Description: - * Disable hw power saving functions - * - * Return Value: - * None. - * - */ - -void vnt_disable_power_saving(struct vnt_private *priv) +int vnt_disable_power_saving(struct vnt_private *priv) { + int ret; + /* disable power saving hw function */ - vnt_control_out(priv, MESSAGE_TYPE_DISABLE_PS, 0, - 0, 0, NULL); + ret = vnt_control_out(priv, MESSAGE_TYPE_DISABLE_PS, 0, + 0, 0, NULL); + if (ret) + return ret; /* clear AutoSleep */ vnt_mac_reg_bits_off(priv, MAC_REG_PSCFG, PSCFG_AUTOSLEEP); /* set always listen beacon */ vnt_mac_reg_bits_on(priv, MAC_REG_PSCTL, PSCTL_ALBCN); + + return 0; } /* diff --git a/drivers/staging/vt6656/power.h b/drivers/staging/vt6656/power.h index 58755ae16e5a..160872026db3 100644 --- a/drivers/staging/vt6656/power.h +++ b/drivers/staging/vt6656/power.h @@ -18,7 +18,7 @@ #define C_PWBT 1000 /* micro sec. power up before TBTT */ -void vnt_disable_power_saving(struct vnt_private *priv); +int vnt_disable_power_saving(struct vnt_private *priv); void vnt_enable_power_saving(struct vnt_private *priv, u16 listen_interval); int vnt_next_tbtt_wakeup(struct vnt_private *priv); diff --git a/drivers/staging/vt6656/rf.c b/drivers/staging/vt6656/rf.c index 43237b7e1dbe..5b8da06e3916 100644 --- a/drivers/staging/vt6656/rf.c +++ b/drivers/staging/vt6656/rf.c @@ -21,22 +21,16 @@ * */ +#include #include "mac.h" #include "rf.h" #include "baseband.h" #include "usbpipe.h" #define CB_AL2230_INIT_SEQ 15 -#define AL2230_PWR_IDX_LEN 64 - #define CB_AL7230_INIT_SEQ 16 -#define AL7230_PWR_IDX_LEN 64 - #define CB_VT3226_INIT_SEQ 11 -#define VT3226_PWR_IDX_LEN 64 - #define CB_VT3342_INIT_SEQ 13 -#define VT3342_PWR_IDX_LEN 64 static u8 al2230_init_table[CB_AL2230_INIT_SEQ][3] = { {0x03, 0xf7, 0x90}, @@ -518,72 +512,45 @@ static u8 vt3342_channel_table1[CB_MAX_CHANNEL][3] = { {0x03, 0x00, 0x04} }; -/* Power Table */ -static const u32 al2230_power_table[AL2230_PWR_IDX_LEN] = { - 0x04040900, - 0x04041900, - 0x04042900, - 0x04043900, - 0x04044900, - 0x04045900, - 0x04046900, - 0x04047900, - 0x04048900, - 0x04049900, - 0x0404a900, - 0x0404b900, - 0x0404c900, - 0x0404d900, - 0x0404e900, - 0x0404f900, - 0x04050900, - 0x04051900, - 0x04052900, - 0x04053900, - 0x04054900, - 0x04055900, - 0x04056900, - 0x04057900, - 0x04058900, - 0x04059900, - 0x0405a900, - 0x0405b900, - 0x0405c900, - 0x0405d900, - 0x0405e900, - 0x0405f900, - 0x04060900, - 0x04061900, - 0x04062900, - 0x04063900, - 0x04064900, - 0x04065900, - 0x04066900, - 0x04067900, - 0x04068900, - 0x04069900, - 0x0406a900, - 0x0406b900, - 0x0406c900, - 0x0406d900, - 0x0406e900, - 0x0406f900, - 0x04070900, - 0x04071900, - 0x04072900, - 0x04073900, - 0x04074900, - 0x04075900, - 0x04076900, - 0x04077900, - 0x04078900, - 0x04079900, - 0x0407a900, - 0x0407b900, - 0x0407c900, - 0x0407d900, - 0x0407e900, - 0x0407f900 +enum { + VNT_TABLE_INIT = 0, + VNT_TABLE_INIT_2 = 0, + VNT_TABLE_0 = 1, + VNT_TABLE_1 = 2, + VNT_TABLE_2 = 1 +}; + +struct vnt_table_info { + u8 *addr; + int length; +}; + +static const struct vnt_table_info vnt_table_seq[][3] = { + { /* RF_AL2230, RF_AL2230S init table, channel table 0 and 1 */ + {&al2230_init_table[0][0], CB_AL2230_INIT_SEQ * 3}, + {&al2230_channel_table0[0][0], CB_MAX_CHANNEL_24G * 3}, + {&al2230_channel_table1[0][0], CB_MAX_CHANNEL_24G * 3} + }, { /* RF_AIROHA7230 init table, channel table 0 and 1 */ + {&al7230_init_table[0][0], CB_AL7230_INIT_SEQ * 3}, + {&al7230_channel_table0[0][0], CB_MAX_CHANNEL * 3}, + {&al7230_channel_table1[0][0], CB_MAX_CHANNEL * 3} + }, { /* RF_VT3226 init table, channel table 0 and 1 */ + {&vt3226_init_table[0][0], CB_VT3226_INIT_SEQ * 3}, + {&vt3226_channel_table0[0][0], CB_MAX_CHANNEL_24G * 3}, + {&vt3226_channel_table1[0][0], CB_MAX_CHANNEL_24G * 3} + }, { /* RF_VT3226D0 init table, channel table 0 and 1 */ + {&vt3226d0_init_table[0][0], CB_VT3226_INIT_SEQ * 3}, + {&vt3226_channel_table0[0][0], CB_MAX_CHANNEL_24G * 3}, + {&vt3226_channel_table1[0][0], CB_MAX_CHANNEL_24G * 3} + }, { /* RF_VT3342A0 init table, channel table 0 and 1 */ + {&vt3342a0_init_table[0][0], CB_VT3342_INIT_SEQ * 3}, + {&vt3342_channel_table0[0][0], CB_MAX_CHANNEL * 3}, + {&vt3342_channel_table1[0][0], CB_MAX_CHANNEL * 3} + }, { /* RF_AIROHA7230 init table 2 and channel table 2 */ + {&al7230_init_table_amode[0][0], CB_AL7230_INIT_SEQ * 3}, + {&al7230_channel_table2[0][0], CB_MAX_CHANNEL * 3}, + {NULL, 0} + } }; /* @@ -600,124 +567,90 @@ int vnt_rf_write_embedded(struct vnt_private *priv, u32 data) reg_data[2] = (u8)(data >> 16); reg_data[3] = (u8)(data >> 24); - vnt_control_out(priv, MESSAGE_TYPE_WRITE_IFRF, - 0, 0, ARRAY_SIZE(reg_data), reg_data); - - return true; -} - -/* Set Tx power by rate and channel number */ -int vnt_rf_setpower(struct vnt_private *priv, u32 rate, u32 channel) -{ - u8 power = priv->cck_pwr; - - if (channel == 0) - return -EINVAL; - - switch (rate) { - case RATE_1M: - case RATE_2M: - case RATE_5M: - case RATE_11M: - channel--; - - if (channel < sizeof(priv->cck_pwr_tbl)) - power = priv->cck_pwr_tbl[channel]; - break; - case RATE_6M: - case RATE_9M: - case RATE_12M: - case RATE_18M: - case RATE_24M: - case RATE_36M: - case RATE_48M: - case RATE_54M: - if (channel > CB_MAX_CHANNEL_24G) - power = priv->ofdm_a_pwr_tbl[channel - 15]; - else - power = priv->ofdm_pwr_tbl[channel - 1]; - break; - } - - return vnt_rf_set_txpower(priv, power, rate); + return vnt_control_out(priv, MESSAGE_TYPE_WRITE_IFRF, 0, 0, + ARRAY_SIZE(reg_data), reg_data); } static u8 vnt_rf_addpower(struct vnt_private *priv) { + int base; s32 rssi = -priv->current_rssi; if (!rssi) return 7; - if (priv->rf_type == RF_VT3226D0) { - if (rssi < -70) - return 9; - else if (rssi < -65) - return 7; - else if (rssi < -60) - return 5; - } else { - if (rssi < -80) - return 9; - else if (rssi < -75) - return 7; - else if (rssi < -70) - return 5; - } + if (priv->rf_type == RF_VT3226D0) + base = -60; + else + base = -70; + + if (rssi < base) + return ((rssi - base + 1) / -5) * 2 + 5; return 0; } /* Set Tx power by power level and rate */ -int vnt_rf_set_txpower(struct vnt_private *priv, u8 power, u32 rate) +static int vnt_rf_set_txpower(struct vnt_private *priv, u8 power, + struct ieee80211_channel *ch) { u32 power_setting = 0; - int ret = true; + int ret = 0; power += vnt_rf_addpower(priv); if (power > VNT_RF_MAX_POWER) power = VNT_RF_MAX_POWER; if (priv->power == power) - return true; + return 0; priv->power = power; switch (priv->rf_type) { case RF_AL2230: - if (power >= AL2230_PWR_IDX_LEN) - return false; + power_setting = 0x0404090 | (power << 12); - ret &= vnt_rf_write_embedded(priv, al2230_power_table[power]); + ret = vnt_rf_write_embedded(priv, power_setting); + if (ret) + return ret; - if (rate <= RATE_11M) - ret &= vnt_rf_write_embedded(priv, 0x0001b400); + if (ch->flags & IEEE80211_CHAN_NO_OFDM) + ret = vnt_rf_write_embedded(priv, 0x0001b400); else - ret &= vnt_rf_write_embedded(priv, 0x0005a400); + ret = vnt_rf_write_embedded(priv, 0x0005a400); + break; case RF_AL2230S: - if (power >= AL2230_PWR_IDX_LEN) - return false; + power_setting = 0x0404090 | (power << 12); - ret &= vnt_rf_write_embedded(priv, al2230_power_table[power]); + ret = vnt_rf_write_embedded(priv, power_setting); + if (ret) + return ret; - if (rate <= RATE_11M) { - ret &= vnt_rf_write_embedded(priv, 0x040c1400); - ret &= vnt_rf_write_embedded(priv, 0x00299b00); + if (ch->flags & IEEE80211_CHAN_NO_OFDM) { + ret = vnt_rf_write_embedded(priv, 0x040c1400); + if (ret) + return ret; + + ret = vnt_rf_write_embedded(priv, 0x00299b00); } else { - ret &= vnt_rf_write_embedded(priv, 0x0005a400); - ret &= vnt_rf_write_embedded(priv, 0x00099b00); + ret = vnt_rf_write_embedded(priv, 0x0005a400); + if (ret) + return ret; + + ret = vnt_rf_write_embedded(priv, 0x00099b00); } + break; case RF_AIROHA7230: - if (rate <= RATE_11M) - ret &= vnt_rf_write_embedded(priv, 0x111bb900); + if (ch->flags & IEEE80211_CHAN_NO_OFDM) + ret = vnt_rf_write_embedded(priv, 0x111bb900); else - ret &= vnt_rf_write_embedded(priv, 0x221bb900); + ret = vnt_rf_write_embedded(priv, 0x221bb900); - if (power >= AL7230_PWR_IDX_LEN) - return false; + if (ret) + return ret; /* * 0x080F1B00 for 3 wire control TxGain(D10) @@ -725,61 +658,68 @@ int vnt_rf_set_txpower(struct vnt_private *priv, u8 power, u32 rate) */ power_setting = 0x080c0b00 | (power << 12); - ret &= vnt_rf_write_embedded(priv, power_setting); - + ret = vnt_rf_write_embedded(priv, power_setting); break; case RF_VT3226: - if (power >= VT3226_PWR_IDX_LEN) - return false; power_setting = ((0x3f - power) << 20) | (0x17 << 8); - ret &= vnt_rf_write_embedded(priv, power_setting); - + ret = vnt_rf_write_embedded(priv, power_setting); break; case RF_VT3226D0: - if (power >= VT3226_PWR_IDX_LEN) - return false; - - if (rate <= RATE_11M) { - u16 hw_value = priv->hw->conf.chandef.chan->hw_value; + if (ch->flags & IEEE80211_CHAN_NO_OFDM) { + u16 hw_value = ch->hw_value; power_setting = ((0x3f - power) << 20) | (0xe07 << 8); - ret &= vnt_rf_write_embedded(priv, power_setting); - ret &= vnt_rf_write_embedded(priv, 0x03c6a200); + ret = vnt_rf_write_embedded(priv, power_setting); + if (ret) + return ret; + + ret = vnt_rf_write_embedded(priv, 0x03c6a200); + if (ret) + return ret; dev_dbg(&priv->usb->dev, "%s 11b channel [%d]\n", __func__, hw_value); hw_value--; - if (hw_value < ARRAY_SIZE(vt3226d0_lo_current_table)) - ret &= vnt_rf_write_embedded(priv, + if (hw_value < ARRAY_SIZE(vt3226d0_lo_current_table)) { + ret = vnt_rf_write_embedded(priv, vt3226d0_lo_current_table[hw_value]); + if (ret) + return ret; + } - ret &= vnt_rf_write_embedded(priv, 0x015C0800); + ret = vnt_rf_write_embedded(priv, 0x015C0800); } else { dev_dbg(&priv->usb->dev, "@@@@ %s> 11G mode\n", __func__); power_setting = ((0x3f - power) << 20) | (0x7 << 8); - ret &= vnt_rf_write_embedded(priv, power_setting); - ret &= vnt_rf_write_embedded(priv, 0x00C6A200); - ret &= vnt_rf_write_embedded(priv, 0x016BC600); - ret &= vnt_rf_write_embedded(priv, 0x00900800); + ret = vnt_rf_write_embedded(priv, power_setting); + if (ret) + return ret; + + ret = vnt_rf_write_embedded(priv, 0x00C6A200); + if (ret) + return ret; + + ret = vnt_rf_write_embedded(priv, 0x016BC600); + if (ret) + return ret; + + ret = vnt_rf_write_embedded(priv, 0x00900800); } + break; case RF_VT3342A0: - if (power >= VT3342_PWR_IDX_LEN) - return false; - power_setting = ((0x3f - power) << 20) | (0x27 << 8); - ret &= vnt_rf_write_embedded(priv, power_setting); - + ret = vnt_rf_write_embedded(priv, power_setting); break; default: break; @@ -787,6 +727,36 @@ int vnt_rf_set_txpower(struct vnt_private *priv, u8 power, u32 rate) return ret; } +/* Set Tx power by channel number type */ +int vnt_rf_setpower(struct vnt_private *priv, + struct ieee80211_channel *ch) +{ + u16 channel; + u8 power = priv->cck_pwr; + + if (!ch) + return -EINVAL; + + /* set channel number to array number */ + channel = ch->hw_value - 1; + + if (ch->flags & IEEE80211_CHAN_NO_OFDM) { + if (channel < ARRAY_SIZE(priv->cck_pwr_tbl)) + power = priv->cck_pwr_tbl[channel]; + } else if (ch->band == NL80211_BAND_5GHZ) { + /* remove 14 channels to array size */ + channel -= 14; + + if (channel < ARRAY_SIZE(priv->ofdm_a_pwr_tbl)) + power = priv->ofdm_a_pwr_tbl[channel]; + } else { + if (channel < ARRAY_SIZE(priv->ofdm_pwr_tbl)) + power = priv->ofdm_pwr_tbl[channel]; + } + + return vnt_rf_set_txpower(priv, power, ch); +} + /* Convert rssi to dbm */ void vnt_rf_rssi_to_dbm(struct vnt_private *priv, u8 rssi, long *dbm) { @@ -813,140 +783,73 @@ void vnt_rf_rssi_to_dbm(struct vnt_private *priv, u8 rssi, long *dbm) int vnt_rf_table_download(struct vnt_private *priv) { - int ret = 0; - u16 length1 = 0, length2 = 0, length3 = 0; - u8 *addr1 = NULL, *addr2 = NULL, *addr3 = NULL; - u16 length, value; - u8 array[256]; + int ret; + int idx = -1; + const struct vnt_table_info *table_seq; switch (priv->rf_type) { case RF_AL2230: case RF_AL2230S: - length1 = CB_AL2230_INIT_SEQ * 3; - length2 = CB_MAX_CHANNEL_24G * 3; - length3 = CB_MAX_CHANNEL_24G * 3; - addr1 = &al2230_init_table[0][0]; - addr2 = &al2230_channel_table0[0][0]; - addr3 = &al2230_channel_table1[0][0]; + idx = 0; break; case RF_AIROHA7230: - length1 = CB_AL7230_INIT_SEQ * 3; - length2 = CB_MAX_CHANNEL * 3; - length3 = CB_MAX_CHANNEL * 3; - addr1 = &al7230_init_table[0][0]; - addr2 = &al7230_channel_table0[0][0]; - addr3 = &al7230_channel_table1[0][0]; + idx = 1; break; case RF_VT3226: - length1 = CB_VT3226_INIT_SEQ * 3; - length2 = CB_MAX_CHANNEL_24G * 3; - length3 = CB_MAX_CHANNEL_24G * 3; - addr1 = &vt3226_init_table[0][0]; - addr2 = &vt3226_channel_table0[0][0]; - addr3 = &vt3226_channel_table1[0][0]; + idx = 2; break; case RF_VT3226D0: - length1 = CB_VT3226_INIT_SEQ * 3; - length2 = CB_MAX_CHANNEL_24G * 3; - length3 = CB_MAX_CHANNEL_24G * 3; - addr1 = &vt3226d0_init_table[0][0]; - addr2 = &vt3226_channel_table0[0][0]; - addr3 = &vt3226_channel_table1[0][0]; + idx = 3; break; case RF_VT3342A0: - length1 = CB_VT3342_INIT_SEQ * 3; - length2 = CB_MAX_CHANNEL * 3; - length3 = CB_MAX_CHANNEL * 3; - addr1 = &vt3342a0_init_table[0][0]; - addr2 = &vt3342_channel_table0[0][0]; - addr3 = &vt3342_channel_table1[0][0]; + idx = 4; break; } - /* Init Table */ - memcpy(array, addr1, length1); + if (idx < 0) + return 0; + table_seq = &vnt_table_seq[idx][0]; + + /* Init Table */ ret = vnt_control_out(priv, MESSAGE_TYPE_WRITE, 0, - MESSAGE_REQUEST_RF_INIT, length1, array); + MESSAGE_REQUEST_RF_INIT, + table_seq[VNT_TABLE_INIT].length, + table_seq[VNT_TABLE_INIT].addr); if (ret) - goto end; + return ret; /* Channel Table 0 */ - value = 0; - while (length2 > 0) { - if (length2 >= 64) - length = 64; - else - length = length2; + ret = vnt_control_out_blocks(priv, VNT_REG_BLOCK_SIZE, + MESSAGE_REQUEST_RF_CH0, + table_seq[VNT_TABLE_0].length, + table_seq[VNT_TABLE_0].addr); + if (ret) + return ret; - memcpy(array, addr2, length); - - ret = vnt_control_out(priv, MESSAGE_TYPE_WRITE, value, - MESSAGE_REQUEST_RF_CH0, length, array); - if (ret) - goto end; - - length2 -= length; - value += length; - addr2 += length; - } - - /* Channel table 1 */ - value = 0; - while (length3 > 0) { - if (length3 >= 64) - length = 64; - else - length = length3; - - memcpy(array, addr3, length); - - ret = vnt_control_out(priv, MESSAGE_TYPE_WRITE, value, - MESSAGE_REQUEST_RF_CH1, length, array); - if (ret) - goto end; - - length3 -= length; - value += length; - addr3 += length; - } + /* Channel Table 1 */ + ret = vnt_control_out_blocks(priv, VNT_REG_BLOCK_SIZE, + MESSAGE_REQUEST_RF_CH1, + table_seq[VNT_TABLE_1].length, + table_seq[VNT_TABLE_1].addr); if (priv->rf_type == RF_AIROHA7230) { - length1 = CB_AL7230_INIT_SEQ * 3; - length2 = CB_MAX_CHANNEL * 3; - addr1 = &al7230_init_table_amode[0][0]; - addr2 = &al7230_channel_table2[0][0]; - - memcpy(array, addr1, length1); + table_seq = &vnt_table_seq[5][0]; /* Init Table 2 */ ret = vnt_control_out(priv, MESSAGE_TYPE_WRITE, 0, - MESSAGE_REQUEST_RF_INIT2, length1, array); + MESSAGE_REQUEST_RF_INIT2, + table_seq[VNT_TABLE_INIT_2].length, + table_seq[VNT_TABLE_INIT_2].addr); if (ret) - goto end; + return ret; - /* Channel Table 0 */ - value = 0; - while (length2 > 0) { - if (length2 >= 64) - length = 64; - else - length = length2; - - memcpy(array, addr2, length); - - ret = vnt_control_out(priv, MESSAGE_TYPE_WRITE, value, - MESSAGE_REQUEST_RF_CH2, length, - array); - if (ret) - goto end; - - length2 -= length; - value += length; - addr2 += length; - } + /* Channel Table 2 */ + ret = vnt_control_out_blocks(priv, VNT_REG_BLOCK_SIZE, + MESSAGE_REQUEST_RF_CH2, + table_seq[VNT_TABLE_2].length, + table_seq[VNT_TABLE_2].addr); } -end: return ret; } diff --git a/drivers/staging/vt6656/rf.h b/drivers/staging/vt6656/rf.h index 7494546d71b8..493faaf4e2b5 100644 --- a/drivers/staging/vt6656/rf.h +++ b/drivers/staging/vt6656/rf.h @@ -41,8 +41,7 @@ #define VNT_RF_REG_LEN 0x17 /* 24 bit length */ int vnt_rf_write_embedded(struct vnt_private *priv, u32 data); -int vnt_rf_setpower(struct vnt_private *priv, u32 rate, u32 channel); -int vnt_rf_set_txpower(struct vnt_private *priv, u8 power, u32 rate); +int vnt_rf_setpower(struct vnt_private *priv, struct ieee80211_channel *ch); void vnt_rf_rssi_to_dbm(struct vnt_private *priv, u8 rssi, long *dbm); int vnt_rf_table_download(struct vnt_private *priv); diff --git a/drivers/staging/vt6656/rxtx.c b/drivers/staging/vt6656/rxtx.c index 9439d190f431..5dd6b4d2bf20 100644 --- a/drivers/staging/vt6656/rxtx.c +++ b/drivers/staging/vt6656/rxtx.c @@ -13,8 +13,6 @@ * * Functions: * vnt_generate_tx_parameter - Generate tx dma required parameter. - * vnt_get_rtscts_duration_le- get rtx/cts required duration - * vnt_get_rtscts_rsvtime_le- get rts/cts reserved time * vnt_get_rsvtime- get frame reserved time * vnt_fill_cts_head- fulfill CTS ctl header * @@ -38,13 +36,24 @@ static const u16 vnt_time_stampoff[2][MAX_RATE] = { {384, 192, 130, 113, 54, 43, 37, 31, 28, 25, 24, 23}, }; -#define RTSDUR_BB 0 -#define RTSDUR_BA 1 -#define RTSDUR_AA 2 -#define CTSDUR_BA 3 #define DATADUR_B 10 #define DATADUR_A 11 +static const u8 vnt_phy_signal[] = { + 0x00, /* RATE_1M */ + 0x01, /* RATE_2M */ + 0x02, /* RATE_5M */ + 0x03, /* RATE_11M */ + 0x8b, /* RATE_6M */ + 0x8f, /* RATE_9M */ + 0x8a, /* RATE_12M */ + 0x8e, /* RATE_18M */ + 0x89, /* RATE_24M */ + 0x8d, /* RATE_36M */ + 0x88, /* RATE_48M */ + 0x8c /* RATE_54M */ +}; + static struct vnt_usb_send_context *vnt_get_free_context(struct vnt_private *priv) { @@ -60,11 +69,6 @@ static struct vnt_usb_send_context context = priv->tx_context[ii]; if (!context->in_use) { context->in_use = true; - memset(context->data, 0, - MAX_TOTAL_SIZE_WITH_ALL_HEADERS); - - context->hdr = NULL; - return context; } } @@ -78,146 +82,105 @@ static struct vnt_usb_send_context return NULL; } +/* Get Length, Service, and Signal fields of Phy for Tx */ +static void vnt_get_phy_field(struct vnt_private *priv, u32 frame_length, + u16 tx_rate, u8 pkt_type, + struct vnt_phy_field *phy) +{ + u32 bit_count; + u32 count = 0; + u32 tmp; + int ext_bit; + int i; + u8 mask = 0; + u8 preamble_type = priv->preamble_type; + + bit_count = frame_length * 8; + ext_bit = false; + + switch (tx_rate) { + case RATE_1M: + count = bit_count; + break; + case RATE_2M: + count = bit_count / 2; + break; + case RATE_5M: + count = DIV_ROUND_UP(bit_count * 10, 55); + break; + case RATE_11M: + count = bit_count / 11; + tmp = count * 11; + + if (tmp != bit_count) { + count++; + + if ((bit_count - tmp) <= 3) + ext_bit = true; + } + + break; + } + + if (tx_rate > RATE_11M) { + if (pkt_type == PK_TYPE_11A) + mask = BIT(4); + } else if (tx_rate > RATE_1M) { + if (preamble_type == PREAMBLE_SHORT) + mask = BIT(3); + } + + i = tx_rate > RATE_54M ? RATE_54M : tx_rate; + phy->signal = vnt_phy_signal[i] | mask; + phy->service = 0x00; + + if (pkt_type == PK_TYPE_11B) { + if (ext_bit) + phy->service |= 0x80; + phy->len = cpu_to_le16((u16)count); + } else { + phy->len = cpu_to_le16((u16)frame_length); + } +} + static __le16 vnt_time_stamp_off(struct vnt_private *priv, u16 rate) { return cpu_to_le16(vnt_time_stampoff[priv->preamble_type % 2] [rate % MAX_RATE]); } -static u32 vnt_get_rsvtime(struct vnt_private *priv, u8 pkt_type, - u32 frame_length, u16 rate, int need_ack) -{ - u32 data_time, ack_time; - - data_time = vnt_get_frame_time(priv->preamble_type, pkt_type, - frame_length, rate); - - if (pkt_type == PK_TYPE_11B) - ack_time = vnt_get_frame_time(priv->preamble_type, pkt_type, 14, - (u16)priv->top_cck_basic_rate); - else - ack_time = vnt_get_frame_time(priv->preamble_type, pkt_type, 14, - (u16)priv->top_ofdm_basic_rate); - - if (need_ack) - return data_time + priv->sifs + ack_time; - - return data_time; -} - -static __le16 vnt_rxtx_rsvtime_le16(struct vnt_private *priv, u8 pkt_type, - u32 frame_length, u16 rate, int need_ack) -{ - return cpu_to_le16((u16)vnt_get_rsvtime(priv, pkt_type, - frame_length, rate, need_ack)); -} - -static __le16 vnt_get_rtscts_rsvtime_le(struct vnt_private *priv, u8 rsv_type, - u8 pkt_type, u32 frame_length, - u16 current_rate) -{ - u32 rrv_time, rts_time, cts_time, ack_time, data_time; - - rrv_time = 0; - rts_time = 0; - cts_time = 0; - ack_time = 0; - - data_time = vnt_get_frame_time(priv->preamble_type, pkt_type, - frame_length, current_rate); - - if (rsv_type == 0) { - rts_time = vnt_get_frame_time(priv->preamble_type, pkt_type, - 20, priv->top_cck_basic_rate); - ack_time = vnt_get_frame_time(priv->preamble_type, - pkt_type, 14, - priv->top_cck_basic_rate); - cts_time = ack_time; - - } else if (rsv_type == 1) { - rts_time = vnt_get_frame_time(priv->preamble_type, pkt_type, - 20, priv->top_cck_basic_rate); - cts_time = vnt_get_frame_time(priv->preamble_type, pkt_type, - 14, priv->top_cck_basic_rate); - ack_time = vnt_get_frame_time(priv->preamble_type, pkt_type, - 14, priv->top_ofdm_basic_rate); - } else if (rsv_type == 2) { - rts_time = vnt_get_frame_time(priv->preamble_type, pkt_type, - 20, priv->top_ofdm_basic_rate); - ack_time = vnt_get_frame_time(priv->preamble_type, - pkt_type, 14, - priv->top_ofdm_basic_rate); - cts_time = ack_time; - - } else if (rsv_type == 3) { - cts_time = vnt_get_frame_time(priv->preamble_type, pkt_type, - 14, priv->top_cck_basic_rate); - ack_time = vnt_get_frame_time(priv->preamble_type, pkt_type, - 14, priv->top_ofdm_basic_rate); - - rrv_time = cts_time + ack_time + data_time + 2 * priv->sifs; - - return cpu_to_le16((u16)rrv_time); - } - - rrv_time = rts_time + cts_time + ack_time + data_time + 3 * priv->sifs; - - return cpu_to_le16((u16)rrv_time); -} - -static __le16 vnt_get_rtscts_duration_le(struct vnt_usb_send_context *context, - u8 dur_type, u8 pkt_type, u16 rate) +static __le16 vnt_rxtx_rsvtime_le16(struct vnt_usb_send_context *context) { struct vnt_private *priv = context->priv; - u32 cts_time = 0, dur_time = 0; - u32 frame_length = context->frame_len; - u8 need_ack = context->need_ack; + struct ieee80211_tx_info *info = IEEE80211_SKB_CB(context->skb); + struct ieee80211_rate *rate = ieee80211_get_tx_rate(priv->hw, info); - switch (dur_type) { - case RTSDUR_BB: - case RTSDUR_BA: - cts_time = vnt_get_frame_time(priv->preamble_type, pkt_type, - 14, priv->top_cck_basic_rate); - dur_time = cts_time + 2 * priv->sifs + - vnt_get_rsvtime(priv, pkt_type, - frame_length, rate, need_ack); - break; - - case RTSDUR_AA: - cts_time = vnt_get_frame_time(priv->preamble_type, pkt_type, - 14, priv->top_ofdm_basic_rate); - dur_time = cts_time + 2 * priv->sifs + - vnt_get_rsvtime(priv, pkt_type, - frame_length, rate, need_ack); - break; - - case CTSDUR_BA: - dur_time = priv->sifs + vnt_get_rsvtime(priv, - pkt_type, frame_length, rate, need_ack); - break; - - default: - break; - } - - return cpu_to_le16((u16)dur_time); + return ieee80211_generic_frame_duration(priv->hw, + info->control.vif, info->band, + context->frame_len, + rate); } -static u16 vnt_mac_hdr_pos(struct vnt_usb_send_context *tx_context, - struct ieee80211_hdr *hdr) +static __le16 vnt_get_rts_duration(struct vnt_usb_send_context *context) { - u8 *head = tx_context->data + offsetof(struct vnt_tx_buffer, fifo_head); - u8 *hdr_pos = (u8 *)hdr; + struct vnt_private *priv = context->priv; + struct ieee80211_tx_info *info = IEEE80211_SKB_CB(context->skb); - tx_context->hdr = hdr; - if (!tx_context->hdr) - return 0; - - return (u16)(hdr_pos - head); + return ieee80211_rts_duration(priv->hw, priv->vif, + context->frame_len, info); } -static u16 vnt_rxtx_datahead_g(struct vnt_usb_send_context *tx_context, - struct vnt_tx_datahead_g *buf) +static __le16 vnt_get_cts_duration(struct vnt_usb_send_context *context) +{ + struct vnt_private *priv = context->priv; + struct ieee80211_tx_info *info = IEEE80211_SKB_CB(context->skb); + + return ieee80211_ctstoself_duration(priv->hw, priv->vif, + context->frame_len, info); +} + +static void vnt_rxtx_datahead_g(struct vnt_usb_send_context *tx_context, + struct vnt_tx_datahead_g *buf) { struct vnt_private *priv = tx_context->priv; struct ieee80211_hdr *hdr = @@ -236,14 +199,10 @@ static u16 vnt_rxtx_datahead_g(struct vnt_usb_send_context *tx_context, buf->time_stamp_off_a = vnt_time_stamp_off(priv, rate); buf->time_stamp_off_b = vnt_time_stamp_off(priv, priv->top_cck_basic_rate); - - tx_context->tx_hdr_size = vnt_mac_hdr_pos(tx_context, &buf->hdr); - - return le16_to_cpu(buf->duration_a); } -static u16 vnt_rxtx_datahead_ab(struct vnt_usb_send_context *tx_context, - struct vnt_tx_datahead_ab *buf) +static void vnt_rxtx_datahead_ab(struct vnt_usb_send_context *tx_context, + struct vnt_tx_datahead_ab *buf) { struct vnt_private *priv = tx_context->priv; struct ieee80211_hdr *hdr = @@ -258,14 +217,10 @@ static u16 vnt_rxtx_datahead_ab(struct vnt_usb_send_context *tx_context, /* Get Duration and TimeStampOff */ buf->duration = hdr->duration_id; buf->time_stamp_off = vnt_time_stamp_off(priv, rate); - - tx_context->tx_hdr_size = vnt_mac_hdr_pos(tx_context, &buf->hdr); - - return le16_to_cpu(buf->duration); } -static int vnt_fill_ieee80211_rts(struct vnt_usb_send_context *tx_context, - struct ieee80211_rts *rts, __le16 duration) +static void vnt_fill_ieee80211_rts(struct vnt_usb_send_context *tx_context, + struct ieee80211_rts *rts, __le16 duration) { struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_context->skb->data; @@ -276,72 +231,56 @@ static int vnt_fill_ieee80211_rts(struct vnt_usb_send_context *tx_context, ether_addr_copy(rts->ra, hdr->addr1); ether_addr_copy(rts->ta, hdr->addr2); - - return 0; } -static u16 vnt_rxtx_rts_g_head(struct vnt_usb_send_context *tx_context, - struct vnt_rts_g *buf) +static void vnt_rxtx_rts_g_head(struct vnt_usb_send_context *tx_context, + struct vnt_rts_g *buf) { struct vnt_private *priv = tx_context->priv; u16 rts_frame_len = 20; - u16 current_rate = tx_context->tx_rate; vnt_get_phy_field(priv, rts_frame_len, priv->top_cck_basic_rate, PK_TYPE_11B, &buf->b); vnt_get_phy_field(priv, rts_frame_len, priv->top_ofdm_basic_rate, tx_context->pkt_type, &buf->a); - buf->duration_bb = vnt_get_rtscts_duration_le(tx_context, RTSDUR_BB, - PK_TYPE_11B, - priv->top_cck_basic_rate); - buf->duration_aa = vnt_get_rtscts_duration_le(tx_context, RTSDUR_AA, - tx_context->pkt_type, - current_rate); - buf->duration_ba = vnt_get_rtscts_duration_le(tx_context, RTSDUR_BA, - tx_context->pkt_type, - current_rate); + buf->duration_bb = vnt_get_rts_duration(tx_context); + buf->duration_aa = buf->duration_bb; + buf->duration_ba = buf->duration_bb; vnt_fill_ieee80211_rts(tx_context, &buf->data, buf->duration_aa); - return vnt_rxtx_datahead_g(tx_context, &buf->data_head); + vnt_rxtx_datahead_g(tx_context, &buf->data_head); } -static u16 vnt_rxtx_rts_ab_head(struct vnt_usb_send_context *tx_context, - struct vnt_rts_ab *buf) +static void vnt_rxtx_rts_ab_head(struct vnt_usb_send_context *tx_context, + struct vnt_rts_ab *buf) { struct vnt_private *priv = tx_context->priv; - u16 current_rate = tx_context->tx_rate; u16 rts_frame_len = 20; vnt_get_phy_field(priv, rts_frame_len, priv->top_ofdm_basic_rate, tx_context->pkt_type, &buf->ab); - buf->duration = vnt_get_rtscts_duration_le(tx_context, RTSDUR_AA, - tx_context->pkt_type, - current_rate); + buf->duration = vnt_get_rts_duration(tx_context); vnt_fill_ieee80211_rts(tx_context, &buf->data, buf->duration); - return vnt_rxtx_datahead_ab(tx_context, &buf->data_head); + vnt_rxtx_datahead_ab(tx_context, &buf->data_head); } -static u16 vnt_fill_cts_head(struct vnt_usb_send_context *tx_context, - union vnt_tx_data_head *head) +static void vnt_fill_cts_head(struct vnt_usb_send_context *tx_context, + union vnt_tx_data_head *head) { struct vnt_private *priv = tx_context->priv; struct vnt_cts *buf = &head->cts_g; u32 cts_frame_len = 14; - u16 current_rate = tx_context->tx_rate; /* Get SignalField,ServiceField,Length */ vnt_get_phy_field(priv, cts_frame_len, priv->top_cck_basic_rate, PK_TYPE_11B, &buf->b); /* Get CTSDuration_ba */ - buf->duration_ba = - vnt_get_rtscts_duration_le(tx_context, CTSDUR_BA, - tx_context->pkt_type, - current_rate); + buf->duration_ba = vnt_get_cts_duration(tx_context); /*Get CTS Frame body*/ buf->data.duration = buf->duration_ba; buf->data.frame_control = @@ -349,127 +288,19 @@ static u16 vnt_fill_cts_head(struct vnt_usb_send_context *tx_context, ether_addr_copy(buf->data.ra, priv->current_net_addr); - return vnt_rxtx_datahead_g(tx_context, &buf->data_head); + vnt_rxtx_datahead_g(tx_context, &buf->data_head); } -static u16 vnt_rxtx_rts(struct vnt_usb_send_context *tx_context, - union vnt_tx_head *tx_head, bool need_mic) +/* returns true if mic_hdr is needed */ +static bool vnt_fill_txkey(struct vnt_tx_buffer *tx_buffer, struct sk_buff *skb) { - struct vnt_private *priv = tx_context->priv; - struct vnt_rrv_time_rts *buf = &tx_head->tx_rts.rts; - union vnt_tx_data_head *head = &tx_head->tx_rts.tx.head; - u32 frame_len = tx_context->frame_len; - u16 current_rate = tx_context->tx_rate; - u8 need_ack = tx_context->need_ack; - - buf->rts_rrv_time_aa = vnt_get_rtscts_rsvtime_le(priv, 2, - tx_context->pkt_type, frame_len, current_rate); - buf->rts_rrv_time_ba = vnt_get_rtscts_rsvtime_le(priv, 1, - tx_context->pkt_type, frame_len, current_rate); - buf->rts_rrv_time_bb = vnt_get_rtscts_rsvtime_le(priv, 0, - tx_context->pkt_type, frame_len, current_rate); - - buf->rrv_time_a = vnt_rxtx_rsvtime_le16(priv, tx_context->pkt_type, - frame_len, current_rate, - need_ack); - buf->rrv_time_b = vnt_rxtx_rsvtime_le16(priv, PK_TYPE_11B, frame_len, - priv->top_cck_basic_rate, need_ack); - - if (need_mic) - head = &tx_head->tx_rts.tx.mic.head; - - return vnt_rxtx_rts_g_head(tx_context, &head->rts_g); -} - -static u16 vnt_rxtx_cts(struct vnt_usb_send_context *tx_context, - union vnt_tx_head *tx_head, bool need_mic) -{ - struct vnt_private *priv = tx_context->priv; - struct vnt_rrv_time_cts *buf = &tx_head->tx_cts.cts; - union vnt_tx_data_head *head = &tx_head->tx_cts.tx.head; - u32 frame_len = tx_context->frame_len; - u16 current_rate = tx_context->tx_rate; - u8 need_ack = tx_context->need_ack; - - buf->rrv_time_a = vnt_rxtx_rsvtime_le16(priv, tx_context->pkt_type, - frame_len, current_rate, need_ack); - buf->rrv_time_b = vnt_rxtx_rsvtime_le16(priv, PK_TYPE_11B, - frame_len, priv->top_cck_basic_rate, need_ack); - - buf->cts_rrv_time_ba = vnt_get_rtscts_rsvtime_le(priv, 3, - tx_context->pkt_type, frame_len, current_rate); - - if (need_mic) - head = &tx_head->tx_cts.tx.mic.head; - - return vnt_fill_cts_head(tx_context, head); -} - -static u16 vnt_rxtx_ab(struct vnt_usb_send_context *tx_context, - union vnt_tx_head *tx_head, bool need_rts, bool need_mic) -{ - struct vnt_private *priv = tx_context->priv; - struct vnt_rrv_time_ab *buf = &tx_head->tx_ab.ab; - union vnt_tx_data_head *head = &tx_head->tx_ab.tx.head; - u32 frame_len = tx_context->frame_len; - u16 current_rate = tx_context->tx_rate; - u8 need_ack = tx_context->need_ack; - - buf->rrv_time = vnt_rxtx_rsvtime_le16(priv, tx_context->pkt_type, - frame_len, current_rate, need_ack); - - if (need_mic) - head = &tx_head->tx_ab.tx.mic.head; - - if (need_rts) { - if (tx_context->pkt_type == PK_TYPE_11B) - buf->rts_rrv_time = vnt_get_rtscts_rsvtime_le(priv, 0, - tx_context->pkt_type, frame_len, current_rate); - else /* PK_TYPE_11A */ - buf->rts_rrv_time = vnt_get_rtscts_rsvtime_le(priv, 2, - tx_context->pkt_type, frame_len, current_rate); - - return vnt_rxtx_rts_ab_head(tx_context, &head->rts_ab); - } - - return vnt_rxtx_datahead_ab(tx_context, &head->data_head_ab); -} - -static u16 vnt_generate_tx_parameter(struct vnt_usb_send_context *tx_context, - struct vnt_tx_buffer *tx_buffer, - struct vnt_mic_hdr **mic_hdr, u32 need_mic, - bool need_rts) -{ - if (tx_context->pkt_type == PK_TYPE_11GB || - tx_context->pkt_type == PK_TYPE_11GA) { - if (need_rts) { - if (need_mic) - *mic_hdr = - &tx_buffer->tx_head.tx_rts.tx.mic.hdr; - - return vnt_rxtx_rts(tx_context, &tx_buffer->tx_head, - need_mic); - } - - if (need_mic) - *mic_hdr = &tx_buffer->tx_head.tx_cts.tx.mic.hdr; - - return vnt_rxtx_cts(tx_context, &tx_buffer->tx_head, need_mic); - } - - if (need_mic) - *mic_hdr = &tx_buffer->tx_head.tx_ab.tx.mic.hdr; - - return vnt_rxtx_ab(tx_context, &tx_buffer->tx_head, need_rts, need_mic); -} - -static void vnt_fill_txkey(struct vnt_usb_send_context *tx_context, - u8 *key_buffer, struct ieee80211_key_conf *tx_key, - struct sk_buff *skb, u16 payload_len, - struct vnt_mic_hdr *mic_hdr) -{ - struct ieee80211_hdr *hdr = tx_context->hdr; + struct vnt_tx_fifo_head *fifo = &tx_buffer->fifo_head; + struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); + struct ieee80211_key_conf *tx_key = info->control.hw_key; + struct vnt_mic_hdr *mic_hdr; + struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; u64 pn64; + u16 payload_len = skb->len; u8 *iv = ((u8 *)hdr + ieee80211_get_hdrlen_from_skb(skb)); /* strip header and icv len from payload */ @@ -479,24 +310,31 @@ static void vnt_fill_txkey(struct vnt_usb_send_context *tx_context, switch (tx_key->cipher) { case WLAN_CIPHER_SUITE_WEP40: case WLAN_CIPHER_SUITE_WEP104: - memcpy(key_buffer, iv, 3); - memcpy(key_buffer + 3, tx_key->key, tx_key->keylen); + memcpy(fifo->tx_key, iv, 3); + memcpy(fifo->tx_key + 3, tx_key->key, tx_key->keylen); if (tx_key->keylen == WLAN_KEY_LEN_WEP40) { - memcpy(key_buffer + 8, iv, 3); - memcpy(key_buffer + 11, + memcpy(fifo->tx_key + 8, iv, 3); + memcpy(fifo->tx_key + 11, tx_key->key, WLAN_KEY_LEN_WEP40); } + fifo->frag_ctl |= cpu_to_le16(FRAGCTL_LEGACY); break; case WLAN_CIPHER_SUITE_TKIP: - ieee80211_get_tkip_p2k(tx_key, skb, key_buffer); + ieee80211_get_tkip_p2k(tx_key, skb, fifo->tx_key); + fifo->frag_ctl |= cpu_to_le16(FRAGCTL_TKIP); break; case WLAN_CIPHER_SUITE_CCMP: - - if (!mic_hdr) - return; + if (info->control.use_cts_prot) { + if (info->control.use_rts) + mic_hdr = &tx_buffer->tx_head.tx_rts.tx.mic.hdr; + else + mic_hdr = &tx_buffer->tx_head.tx_cts.tx.mic.hdr; + } else { + mic_hdr = &tx_buffer->tx_head.tx_ab.tx.mic.hdr; + } mic_hdr->id = 0x59; mic_hdr->payload_len = cpu_to_be16(payload_len); @@ -527,12 +365,137 @@ static void vnt_fill_txkey(struct vnt_usb_send_context *tx_context, if (ieee80211_has_a4(hdr->frame_control)) ether_addr_copy(mic_hdr->addr4, hdr->addr4); - memcpy(key_buffer, tx_key->key, WLAN_KEY_LEN_CCMP); + memcpy(fifo->tx_key, tx_key->key, WLAN_KEY_LEN_CCMP); - break; + fifo->frag_ctl |= cpu_to_le16(FRAGCTL_AES); + return true; default: break; } + + return false; +} + +static void vnt_rxtx_rts(struct vnt_usb_send_context *tx_context) +{ + struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_context->skb); + struct vnt_tx_buffer *tx_buffer = tx_context->tx_buffer; + union vnt_tx_head *tx_head = &tx_buffer->tx_head; + struct vnt_rrv_time_rts *buf = &tx_head->tx_rts.rts; + union vnt_tx_data_head *head = &tx_head->tx_rts.tx.head; + + buf->rts_rrv_time_aa = vnt_get_rts_duration(tx_context); + buf->rts_rrv_time_ba = buf->rts_rrv_time_aa; + buf->rts_rrv_time_bb = buf->rts_rrv_time_aa; + + buf->rrv_time_a = vnt_rxtx_rsvtime_le16(tx_context); + buf->rrv_time_b = buf->rrv_time_a; + + if (info->control.hw_key) { + if (vnt_fill_txkey(tx_buffer, tx_context->skb)) + head = &tx_head->tx_rts.tx.mic.head; + } + + vnt_rxtx_rts_g_head(tx_context, &head->rts_g); +} + +static void vnt_rxtx_cts(struct vnt_usb_send_context *tx_context) +{ + struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_context->skb); + struct vnt_tx_buffer *tx_buffer = tx_context->tx_buffer; + union vnt_tx_head *tx_head = &tx_buffer->tx_head; + struct vnt_rrv_time_cts *buf = &tx_head->tx_cts.cts; + union vnt_tx_data_head *head = &tx_head->tx_cts.tx.head; + + buf->rrv_time_a = vnt_rxtx_rsvtime_le16(tx_context); + buf->rrv_time_b = buf->rrv_time_a; + + buf->cts_rrv_time_ba = vnt_get_cts_duration(tx_context); + + if (info->control.hw_key) { + if (vnt_fill_txkey(tx_buffer, tx_context->skb)) + head = &tx_head->tx_cts.tx.mic.head; + } + + vnt_fill_cts_head(tx_context, head); +} + +static void vnt_rxtx_ab(struct vnt_usb_send_context *tx_context) +{ + struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_context->skb); + struct vnt_tx_buffer *tx_buffer = tx_context->tx_buffer; + union vnt_tx_head *tx_head = &tx_buffer->tx_head; + struct vnt_rrv_time_ab *buf = &tx_head->tx_ab.ab; + union vnt_tx_data_head *head = &tx_head->tx_ab.tx.head; + + buf->rrv_time = vnt_rxtx_rsvtime_le16(tx_context); + + if (info->control.hw_key) { + if (vnt_fill_txkey(tx_buffer, tx_context->skb)) + head = &tx_head->tx_ab.tx.mic.head; + } + + if (info->control.use_rts) { + buf->rts_rrv_time = vnt_get_rts_duration(tx_context); + + vnt_rxtx_rts_ab_head(tx_context, &head->rts_ab); + + return; + } + + vnt_rxtx_datahead_ab(tx_context, &head->data_head_ab); +} + +static void vnt_generate_tx_parameter(struct vnt_usb_send_context *tx_context) +{ + struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_context->skb); + + if (info->control.use_cts_prot) { + if (info->control.use_rts) { + vnt_rxtx_rts(tx_context); + + return; + } + + vnt_rxtx_cts(tx_context); + + return; + } + + vnt_rxtx_ab(tx_context); +} + +static u16 vnt_get_hdr_size(struct ieee80211_tx_info *info) +{ + u16 size = sizeof(struct vnt_tx_datahead_ab); + + if (info->control.use_cts_prot) { + if (info->control.use_rts) + size = sizeof(struct vnt_rts_g); + else + size = sizeof(struct vnt_cts); + } else if (info->control.use_rts) { + size = sizeof(struct vnt_rts_ab); + } + + if (info->control.hw_key) { + if (info->control.hw_key->cipher == WLAN_CIPHER_SUITE_CCMP) + size += sizeof(struct vnt_mic_hdr); + } + + /* Get rrv_time header */ + if (info->control.use_cts_prot) { + if (info->control.use_rts) + size += sizeof(struct vnt_rrv_time_rts); + else + size += sizeof(struct vnt_rrv_time_cts); + } else { + size += sizeof(struct vnt_rrv_time_ab); + } + + size += sizeof(struct vnt_tx_fifo_head); + + return size; } int vnt_tx_packet(struct vnt_private *priv, struct sk_buff *skb) @@ -540,30 +503,18 @@ int vnt_tx_packet(struct vnt_private *priv, struct sk_buff *skb) struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); struct ieee80211_tx_rate *tx_rate = &info->control.rates[0]; struct ieee80211_rate *rate; - struct ieee80211_key_conf *tx_key; struct ieee80211_hdr *hdr; - struct vnt_mic_hdr *mic_hdr = NULL; struct vnt_tx_buffer *tx_buffer; struct vnt_tx_fifo_head *tx_buffer_head; struct vnt_usb_send_context *tx_context; unsigned long flags; - u16 tx_bytes, tx_header_size, tx_body_size, current_rate, duration_id; u8 pkt_type; - bool need_rts = false; - bool need_mic = false; hdr = (struct ieee80211_hdr *)(skb->data); rate = ieee80211_get_tx_rate(priv->hw, info); - current_rate = rate->hw_value; - if (priv->current_rate != current_rate && - !(priv->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) { - priv->current_rate = current_rate; - vnt_schedule_command(priv, WLAN_CMD_SETPOWER); - } - - if (current_rate > RATE_11M) { + if (rate->hw_value > RATE_11M) { if (info->band == NL80211_BAND_5GHZ) { pkt_type = PK_TYPE_11A; } else { @@ -589,17 +540,23 @@ int vnt_tx_packet(struct vnt_private *priv, struct sk_buff *skb) return -ENOMEM; } - tx_context->skb = skb; tx_context->pkt_type = pkt_type; - tx_context->need_ack = false; tx_context->frame_len = skb->len + 4; - tx_context->tx_rate = current_rate; + tx_context->tx_rate = rate->hw_value; spin_unlock_irqrestore(&priv->lock, flags); - tx_buffer = (struct vnt_tx_buffer *)tx_context->data; + tx_context->skb = skb_clone(skb, GFP_ATOMIC); + if (!tx_context->skb) { + tx_context->in_use = false; + return -ENOMEM; + } + + tx_buffer = skb_push(skb, vnt_get_hdr_size(info)); + tx_context->tx_buffer = tx_buffer; tx_buffer_head = &tx_buffer->fifo_head; - tx_body_size = skb->len; + + tx_context->type = CONTEXT_DATA_PACKET; /*Set fifo controls */ if (pkt_type == PK_TYPE_11A) @@ -623,92 +580,43 @@ int vnt_tx_packet(struct vnt_private *priv, struct sk_buff *skb) cpu_to_le16(DEFAULT_MSDU_LIFETIME_RES_64us); } - if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { + if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) tx_buffer_head->fifo_ctl |= cpu_to_le16(FIFOCTL_NEEDACK); - tx_context->need_ack = true; - } if (ieee80211_has_retry(hdr->frame_control)) tx_buffer_head->fifo_ctl |= cpu_to_le16(FIFOCTL_LRETRY); - if (tx_rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) - priv->preamble_type = PREAMBLE_SHORT; - else - priv->preamble_type = PREAMBLE_LONG; - - if (tx_rate->flags & IEEE80211_TX_RC_USE_RTS_CTS) { - need_rts = true; + if (info->control.use_rts) tx_buffer_head->fifo_ctl |= cpu_to_le16(FIFOCTL_RTS); - } if (ieee80211_has_a4(hdr->frame_control)) tx_buffer_head->fifo_ctl |= cpu_to_le16(FIFOCTL_LHEAD); tx_buffer_head->frag_ctl = - cpu_to_le16(ieee80211_get_hdrlen_from_skb(skb) << 10); + cpu_to_le16(ieee80211_hdrlen(hdr->frame_control) << 10); - if (info->control.hw_key) { - tx_key = info->control.hw_key; - switch (info->control.hw_key->cipher) { - case WLAN_CIPHER_SUITE_WEP40: - case WLAN_CIPHER_SUITE_WEP104: - tx_buffer_head->frag_ctl |= cpu_to_le16(FRAGCTL_LEGACY); - break; - case WLAN_CIPHER_SUITE_TKIP: - tx_buffer_head->frag_ctl |= cpu_to_le16(FRAGCTL_TKIP); - break; - case WLAN_CIPHER_SUITE_CCMP: - tx_buffer_head->frag_ctl |= cpu_to_le16(FRAGCTL_AES); - need_mic = true; - default: - break; - } - tx_context->frame_len += tx_key->icv_len; - } + if (info->control.hw_key) + tx_context->frame_len += info->control.hw_key->icv_len; - tx_buffer_head->current_rate = cpu_to_le16(current_rate); + tx_buffer_head->current_rate = cpu_to_le16(rate->hw_value); - duration_id = vnt_generate_tx_parameter(tx_context, tx_buffer, &mic_hdr, - need_mic, need_rts); - - tx_header_size = tx_context->tx_hdr_size; - if (!tx_header_size) { - tx_context->in_use = false; - return -ENOMEM; - } + vnt_generate_tx_parameter(tx_context); tx_buffer_head->frag_ctl |= cpu_to_le16(FRAGCTL_NONFRAG); - tx_bytes = tx_header_size + tx_body_size; - - memcpy(tx_context->hdr, skb->data, tx_body_size); - - if (info->control.hw_key) { - tx_key = info->control.hw_key; - if (tx_key->keylen > 0) - vnt_fill_txkey(tx_context, tx_buffer_head->tx_key, - tx_key, skb, tx_body_size, mic_hdr); - } - priv->seq_counter = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4; - tx_buffer->tx_byte_count = cpu_to_le16(tx_bytes); - tx_buffer->pkt_no = tx_context->pkt_no; - tx_buffer->type = 0x00; - - tx_bytes += 4; - - tx_context->type = CONTEXT_DATA_PACKET; - tx_context->buf_len = tx_bytes; - spin_lock_irqsave(&priv->lock, flags); - if (vnt_tx_context(priv, tx_context)) { + if (vnt_tx_context(priv, tx_context, skb)) { + dev_kfree_skb(tx_context->skb); spin_unlock_irqrestore(&priv->lock, flags); return -EIO; } + dev_kfree_skb(skb); + spin_unlock_irqrestore(&priv->lock, flags); return 0; @@ -716,14 +624,13 @@ int vnt_tx_packet(struct vnt_private *priv, struct sk_buff *skb) static int vnt_beacon_xmit(struct vnt_private *priv, struct sk_buff *skb) { - struct vnt_beacon_buffer *beacon_buffer; struct vnt_tx_short_buf_head *short_head; struct ieee80211_tx_info *info; struct vnt_usb_send_context *context; struct ieee80211_mgmt *mgmt_hdr; unsigned long flags; u32 frame_size = skb->len + 4; - u16 current_rate, count; + u16 current_rate; spin_lock_irqsave(&priv->lock, flags); @@ -738,8 +645,8 @@ static int vnt_beacon_xmit(struct vnt_private *priv, struct sk_buff *skb) spin_unlock_irqrestore(&priv->lock, flags); - beacon_buffer = (struct vnt_beacon_buffer *)&context->data[0]; - short_head = &beacon_buffer->short_head; + mgmt_hdr = (struct ieee80211_mgmt *)skb->data; + short_head = skb_push(skb, sizeof(*short_head)); if (priv->bb_type == BB_TYPE_11A) { current_rate = RATE_6M; @@ -764,10 +671,6 @@ static int vnt_beacon_xmit(struct vnt_private *priv, struct sk_buff *skb) vnt_time_stamp_off(priv, current_rate); } - /* Generate Beacon Header */ - mgmt_hdr = &beacon_buffer->mgmt_hdr; - memcpy(mgmt_hdr, skb->data, skb->len); - /* Get Duration */ short_head->duration = mgmt_hdr->duration; @@ -786,18 +689,11 @@ static int vnt_beacon_xmit(struct vnt_private *priv, struct sk_buff *skb) if (priv->seq_counter > 0x0fff) priv->seq_counter = 0; - count = sizeof(struct vnt_tx_short_buf_head) + skb->len; - - beacon_buffer->tx_byte_count = cpu_to_le16(count); - beacon_buffer->pkt_no = context->pkt_no; - beacon_buffer->type = 0x01; - context->type = CONTEXT_BEACON_PACKET; - context->buf_len = count + 4; /* USB header */ spin_lock_irqsave(&priv->lock, flags); - if (vnt_tx_context(priv, context)) + if (vnt_tx_context(priv, context, skb)) ieee80211_free_txskb(priv->hw, context->skb); spin_unlock_irqrestore(&priv->lock, flags); diff --git a/drivers/staging/vt6656/rxtx.h b/drivers/staging/vt6656/rxtx.h index 0e6226af7d41..6ca2ca32d036 100644 --- a/drivers/staging/vt6656/rxtx.h +++ b/drivers/staging/vt6656/rxtx.h @@ -23,6 +23,13 @@ #define DEFAULT_MGN_LIFETIME_RES_64us 125 /* 64us */ #define DEFAULT_MSDU_LIFETIME_RES_64us 8000 +/* Length, Service, and Signal fields of Phy for Tx */ +struct vnt_phy_field { + u8 signal; + u8 service; + __le16 len; +} __packed; + /* MIC HDR data header */ struct vnt_mic_hdr { u8 id; @@ -70,14 +77,12 @@ struct vnt_tx_datahead_g { __le16 duration_a; __le16 time_stamp_off_b; __le16 time_stamp_off_a; - struct ieee80211_hdr hdr; } __packed; struct vnt_tx_datahead_ab { struct vnt_phy_field ab; __le16 duration; __le16 time_stamp_off; - struct ieee80211_hdr hdr; } __packed; /* RTS buffer header */ @@ -155,9 +160,6 @@ struct vnt_tx_fifo_head { } __packed; struct vnt_tx_buffer { - u8 type; - u8 pkt_no; - __le16 tx_byte_count; struct vnt_tx_fifo_head fifo_head; union vnt_tx_head tx_head; } __packed; @@ -170,14 +172,6 @@ struct vnt_tx_short_buf_head { __le16 time_stamp_off; } __packed; -struct vnt_beacon_buffer { - u8 type; - u8 pkt_no; - __le16 tx_byte_count; - struct vnt_tx_short_buf_head short_head; - struct ieee80211_mgmt mgmt_hdr; -} __packed; - int vnt_tx_packet(struct vnt_private *priv, struct sk_buff *skb); int vnt_beacon_make(struct vnt_private *priv, struct ieee80211_vif *vif); int vnt_beacon_enable(struct vnt_private *priv, struct ieee80211_vif *vif, diff --git a/drivers/staging/vt6656/usbpipe.c b/drivers/staging/vt6656/usbpipe.c index 91b62c3dff7b..82b774be6485 100644 --- a/drivers/staging/vt6656/usbpipe.c +++ b/drivers/staging/vt6656/usbpipe.c @@ -77,7 +77,7 @@ int vnt_control_out_u8(struct vnt_private *priv, u8 reg, u8 reg_off, u8 data) } int vnt_control_out_blocks(struct vnt_private *priv, - u16 block, u8 reg, u16 length, u8 *data) + u16 block, u8 reg, u16 length, const u8 *data) { int ret = 0, i; @@ -196,32 +196,18 @@ static void vnt_int_process_data(struct vnt_private *priv) if (int_data->tsr3 & TSR_VALID) vnt_int_report_rate(priv, int_data->pkt3, int_data->tsr3); - if (int_data->isr0 != 0) { - if (int_data->isr0 & ISR_BNTX && - priv->op_mode == NL80211_IFTYPE_AP) - vnt_schedule_command(priv, WLAN_CMD_BECON_SEND); + if (!int_data->isr0) + return; - if (int_data->isr0 & ISR_TBTT && - priv->hw->conf.flags & IEEE80211_CONF_PS) { - if (!priv->wake_up_count) - priv->wake_up_count = - priv->hw->conf.listen_interval; + if (int_data->isr0 & ISR_BNTX && priv->op_mode == NL80211_IFTYPE_AP) + vnt_schedule_command(priv, WLAN_CMD_BECON_SEND); - if (priv->wake_up_count) - --priv->wake_up_count; + priv->current_tsf = le64_to_cpu(int_data->tsf); - /* Turn on wake up to listen next beacon */ - if (priv->wake_up_count == 1) - vnt_schedule_command(priv, - WLAN_CMD_TBTT_WAKEUP); - } - priv->current_tsf = le64_to_cpu(int_data->tsf); - - low_stats->dot11RTSSuccessCount += int_data->rts_success; - low_stats->dot11RTSFailureCount += int_data->rts_fail; - low_stats->dot11ACKFailureCount += int_data->ack_fail; - low_stats->dot11FCSErrorCount += int_data->fcs_err; - } + low_stats->dot11RTSSuccessCount += int_data->rts_success; + low_stats->dot11RTSFailureCount += int_data->rts_fail; + low_stats->dot11ACKFailureCount += int_data->ack_fail; + low_stats->dot11FCSErrorCount += int_data->fcs_err; } static void vnt_start_interrupt_urb_complete(struct urb *urb) @@ -442,7 +428,8 @@ static void vnt_tx_context_complete(struct urb *urb) switch (urb->status) { case 0: - dev_dbg(&priv->usb->dev, "Write %d bytes\n", context->buf_len); + dev_dbg(&priv->usb->dev, + "Write %d bytes\n", urb->actual_length); break; case -ECONNRESET: case -ENOENT: @@ -467,30 +454,53 @@ static void vnt_tx_context_complete(struct urb *urb) } int vnt_tx_context(struct vnt_private *priv, - struct vnt_usb_send_context *context) + struct vnt_usb_send_context *context, + struct sk_buff *skb) { + struct vnt_tx_usb_header *usb; + struct urb *urb; int status; - struct urb *urb = context->urb; + u16 count = skb->len; + + usb = skb_push(skb, sizeof(*usb)); + usb->tx_byte_count = cpu_to_le16(count); + usb->pkt_no = context->pkt_no; + usb->type = context->type; if (test_bit(DEVICE_FLAGS_DISCONNECTED, &priv->flags)) { context->in_use = false; return -ENODEV; } + if (skb->len > MAX_TOTAL_SIZE_WITH_ALL_HEADERS) { + context->in_use = false; + return -E2BIG; + } + + urb = usb_alloc_urb(0, GFP_ATOMIC); + if (!urb) { + context->in_use = false; + return -ENOMEM; + } + usb_fill_bulk_urb(urb, priv->usb, usb_sndbulkpipe(priv->usb, 3), - context->data, - context->buf_len, + skb->data, + skb->len, vnt_tx_context_complete, context); + usb_anchor_urb(urb, &priv->tx_submitted); + status = usb_submit_urb(urb, GFP_ATOMIC); if (status) { dev_dbg(&priv->usb->dev, "Submit Tx URB failed %d\n", status); - + usb_unanchor_urb(urb); context->in_use = false; } + usb_free_urb(urb); + return status; } diff --git a/drivers/staging/vt6656/usbpipe.h b/drivers/staging/vt6656/usbpipe.h index 35697b58d748..52c2a928c9c1 100644 --- a/drivers/staging/vt6656/usbpipe.h +++ b/drivers/staging/vt6656/usbpipe.h @@ -41,6 +41,12 @@ struct vnt_interrupt_data { u8 sw[2]; } __packed; +struct vnt_tx_usb_header { + u8 type; + u8 pkt_no; + __le16 tx_byte_count; +} __packed; + #define VNT_REG_BLOCK_SIZE 64 int vnt_control_out(struct vnt_private *priv, u8 request, u16 value, @@ -52,11 +58,12 @@ int vnt_control_out_u8(struct vnt_private *priv, u8 reg, u8 ref_off, u8 data); int vnt_control_in_u8(struct vnt_private *priv, u8 reg, u8 reg_off, u8 *data); int vnt_control_out_blocks(struct vnt_private *priv, - u16 block, u8 reg, u16 len, u8 *data); + u16 block, u8 reg, u16 len, const u8 *data); int vnt_start_interrupt_urb(struct vnt_private *priv); int vnt_submit_rx_urb(struct vnt_private *priv, struct vnt_rcb *rcb); int vnt_tx_context(struct vnt_private *priv, - struct vnt_usb_send_context *context); + struct vnt_usb_send_context *context, + struct sk_buff *skb); #endif /* __USBPIPE_H__ */ diff --git a/drivers/staging/vt6656/wcmd.c b/drivers/staging/vt6656/wcmd.c index 2c5250ca2801..0ccc87da394e 100644 --- a/drivers/staging/vt6656/wcmd.c +++ b/drivers/staging/vt6656/wcmd.c @@ -122,8 +122,7 @@ void vnt_run_command(struct work_struct *work) case WLAN_CMD_SETPOWER_START: - vnt_rf_setpower(priv, priv->current_rate, - priv->hw->conf.chandef.chan->hw_value); + vnt_rf_setpower(priv, priv->hw->conf.chandef.chan); break; diff --git a/drivers/staging/wfx/Makefile b/drivers/staging/wfx/Makefile index 0d9c1ed092f6..0e0cc982ceab 100644 --- a/drivers/staging/wfx/Makefile +++ b/drivers/staging/wfx/Makefile @@ -7,6 +7,7 @@ wfx-y := \ bh.o \ hwio.o \ fwio.o \ + hif_tx_mib.o \ hif_tx.o \ hif_rx.o \ queue.o \ diff --git a/drivers/staging/wfx/TODO b/drivers/staging/wfx/TODO index efcb7c6a5aa7..42bf36d43970 100644 --- a/drivers/staging/wfx/TODO +++ b/drivers/staging/wfx/TODO @@ -1,60 +1,25 @@ This is a list of things that need to be done to get this driver out of the staging directory. - - All structures defined in hif_api_*.h are intended to sent/received to/from - hardware. All their members whould be declared __le32 or __le16. - See: - https://lore.kernel.org/lkml/20191111202852.GX26530@ZenIV.linux.org.uk + - The HIF API is not yet clean enough. - - Once previous item done, it will be possible to audit the driver with - `sparse'. It will probably find tons of problems with big endian - architectures. - - - hif_api_*.h whave been imported from firmware code. Some of the structures - are never used in driver. - - - Driver try to maintains power save status of the stations. However, this - work is already done by mac80211. sta_asleep_mask and pspoll_mask should be - dropped. - - - wfx_tx_queues_get() should be reworked. It currently try compute itself the - QoS policy. However, firmware already do the job. Firmware would prefer to - have a few packets in each queue and be able to choose itself which queue to - use. + - The code that check the corectness of received message (in rx_helper()) can + be improved. See: + https://lore.kernel.org/driverdev-devel/2302785.6C7ODC2LYm@pc-42/ - As suggested by Felix, rate control could be improved following this idea: https://lore.kernel.org/lkml/3099559.gv3Q75KnN1@pc-42/ - - When driver is about to loose BSS, it forge its own Null Func request (see - wfx_cqm_bssloss_sm()). It should use mechanism provided by mac80211. - - - AP is actually is setup after a call to wfx_bss_info_changed(). Yet, - ieee80211_ops provide callback start_ap(). - - - The current process for joining a network is incredibly complex. Should be - reworked. - - - Monitoring mode is not implemented despite being mandatory by mac80211. - - - "compatible" value are not correct. They should be "vendor,chip". See: - https://lore.kernel.org/driverdev-devel/5226570.CMH5hVlZcI@pc-42 - - - The "state" field from wfx_vif should be replaced by "vif->type". - - - It seems that wfx_upload_keys() is useless. - - - "event_queue" from wfx_vif seems overkill. These event are rare and they - probably could be handled in a simpler fashion. - - Feature called "secure link" should be either developed (using kernel crypto API) or dropped. + - The device allows to filter multicast traffic. The code to support these + filters exists in the driver but it is disabled because it has never been + tested. + - In wfx_cmd_send(), "async" allow to send command without waiting the reply. It may help in some situation, but it is not yet used. In add, it may cause some trouble: https://lore.kernel.org/driverdev-devel/alpine.DEB.2.21.1910041317381.2992@hadrien/ So, fix it (by replacing the mutex with a semaphore) or drop it. - - Chip support P2P, but driver does not implement it. - - - Chip support kind of Mesh, but driver does not implement it. diff --git a/drivers/staging/wfx/bh.c b/drivers/staging/wfx/bh.c index 9fcab00a3733..1cbaf8bb4fa3 100644 --- a/drivers/staging/wfx/bh.c +++ b/drivers/staging/wfx/bh.c @@ -70,7 +70,7 @@ static int rx_helper(struct wfx_dev *wdev, size_t read_len, int *is_cnf) if (wfx_data_read(wdev, skb->data, alloc_len)) goto err; - piggyback = le16_to_cpup((u16 *)(skb->data + alloc_len - 2)); + piggyback = le16_to_cpup((__le16 *)(skb->data + alloc_len - 2)); _trace_piggyback(piggyback, false); hif = (struct hif_msg *)skb->data; @@ -84,13 +84,12 @@ static int rx_helper(struct wfx_dev *wdev, size_t read_len, int *is_cnf) // piggyback is probably correct. return piggyback; } - le16_to_cpus(&hif->len); - computed_len = round_up(hif->len - sizeof(hif->len), 16) - + sizeof(struct hif_sl_msg) - + sizeof(struct hif_sl_tag); + computed_len = + round_up(le16_to_cpu(hif->len) - sizeof(hif->len), 16) + + sizeof(struct hif_sl_msg) + + sizeof(struct hif_sl_tag); } else { - le16_to_cpus(&hif->len); - computed_len = round_up(hif->len, 2); + computed_len = round_up(le16_to_cpu(hif->len), 2); } if (computed_len != read_len) { dev_err(wdev->dev, "inconsistent message length: %zu != %zu\n", @@ -103,13 +102,11 @@ static int rx_helper(struct wfx_dev *wdev, size_t read_len, int *is_cnf) if (!(hif->id & HIF_ID_IS_INDICATION)) { (*is_cnf)++; if (hif->id == HIF_CNF_ID_MULTI_TRANSMIT) - release_count = le32_to_cpu(((struct hif_cnf_multi_transmit *)hif->body)->num_tx_confs); + release_count = ((struct hif_cnf_multi_transmit *)hif->body)->num_tx_confs; else release_count = 1; WARN(wdev->hif.tx_buffers_used < release_count, "corrupted buffer counter"); wdev->hif.tx_buffers_used -= release_count; - if (!wdev->hif.tx_buffers_used) - wake_up(&wdev->hif.tx_buffers_empty); } _trace_hif_recv(hif, wdev->hif.tx_buffers_used); @@ -120,9 +117,11 @@ static int rx_helper(struct wfx_dev *wdev, size_t read_len, int *is_cnf) wdev->hif.rx_seqnum = (hif->seqnum + 1) % (HIF_COUNTER_MAX + 1); } - skb_put(skb, hif->len); + skb_put(skb, le16_to_cpu(hif->len)); // wfx_handle_rx takes care on SKB livetime wfx_handle_rx(wdev, skb); + if (!wdev->hif.tx_buffers_used) + wake_up(&wdev->hif.tx_buffers_empty); return piggyback; @@ -307,6 +306,35 @@ void wfx_bh_request_tx(struct wfx_dev *wdev) queue_work(system_highpri_wq, &wdev->hif.bh); } +/* + * If IRQ is not available, this function allow to manually poll the control + * register and simulate an IRQ ahen an event happened. + * + * Note that the device has a bug: If an IRQ raise while host read control + * register, the IRQ is lost. So, use this function carefully (only duing + * device initialisation). + */ +void wfx_bh_poll_irq(struct wfx_dev *wdev) +{ + ktime_t now, start; + u32 reg; + + WARN(!wdev->poll_irq, "unexpected IRQ polling can mask IRQ"); + start = ktime_get(); + for (;;) { + control_reg_read(wdev, ®); + now = ktime_get(); + if (reg & 0xFFF) + break; + if (ktime_after(now, ktime_add_ms(start, 1000))) { + dev_err(wdev->dev, "time out while polling control register\n"); + return; + } + udelay(200); + } + wfx_bh_request_rx(wdev); +} + void wfx_bh_register(struct wfx_dev *wdev) { INIT_WORK(&wdev->hif.bh, bh_work); diff --git a/drivers/staging/wfx/bh.h b/drivers/staging/wfx/bh.h index 93ca98424e0b..4b73437869e1 100644 --- a/drivers/staging/wfx/bh.h +++ b/drivers/staging/wfx/bh.h @@ -28,5 +28,6 @@ void wfx_bh_register(struct wfx_dev *wdev); void wfx_bh_unregister(struct wfx_dev *wdev); void wfx_bh_request_rx(struct wfx_dev *wdev); void wfx_bh_request_tx(struct wfx_dev *wdev); +void wfx_bh_poll_irq(struct wfx_dev *wdev); #endif /* WFX_BH_H */ diff --git a/drivers/staging/wfx/bus.h b/drivers/staging/wfx/bus.h index 62d6ecabe4cb..0370b6c59863 100644 --- a/drivers/staging/wfx/bus.h +++ b/drivers/staging/wfx/bus.h @@ -25,6 +25,8 @@ struct hwbus_ops { void *dst, size_t count); int (*copy_to_io)(void *bus_priv, unsigned int addr, const void *src, size_t count); + int (*irq_subscribe)(void *bus_priv); + int (*irq_unsubscribe)(void *bus_priv); void (*lock)(void *bus_priv); void (*unlock)(void *bus_priv); size_t (*align_size)(void *bus_priv, size_t size); diff --git a/drivers/staging/wfx/bus_sdio.c b/drivers/staging/wfx/bus_sdio.c index dedc3ff58d3e..496bfc8bbacc 100644 --- a/drivers/staging/wfx/bus_sdio.c +++ b/drivers/staging/wfx/bus_sdio.c @@ -6,10 +6,12 @@ * Copyright (c) 2010, ST-Ericsson */ #include +#include #include #include #include #include +#include #include "bus.h" #include "wfx.h" @@ -91,53 +93,58 @@ static void wfx_sdio_irq_handler(struct sdio_func *func) { struct wfx_sdio_priv *bus = sdio_get_drvdata(func); - if (bus->core) - wfx_bh_request_rx(bus->core); - else - WARN(!bus->core, "race condition in driver init/deinit"); + wfx_bh_request_rx(bus->core); } static irqreturn_t wfx_sdio_irq_handler_ext(int irq, void *priv) { struct wfx_sdio_priv *bus = priv; - if (!bus->core) { - WARN(!bus->core, "race condition in driver init/deinit"); - return IRQ_NONE; - } sdio_claim_host(bus->func); wfx_bh_request_rx(bus->core); sdio_release_host(bus->func); return IRQ_HANDLED; } -static int wfx_sdio_irq_subscribe(struct wfx_sdio_priv *bus) +static int wfx_sdio_irq_subscribe(void *priv) { + struct wfx_sdio_priv *bus = priv; + u32 flags; int ret; + u8 cccr; - if (bus->of_irq) { - ret = request_irq(bus->of_irq, wfx_sdio_irq_handler_ext, - IRQF_TRIGGER_RISING, "wfx", bus); - } else { + if (!bus->of_irq) { sdio_claim_host(bus->func); ret = sdio_claim_irq(bus->func, wfx_sdio_irq_handler); sdio_release_host(bus->func); + return ret; } - return ret; + + sdio_claim_host(bus->func); + cccr = sdio_f0_readb(bus->func, SDIO_CCCR_IENx, NULL); + cccr |= BIT(0); + cccr |= BIT(bus->func->num); + sdio_f0_writeb(bus->func, cccr, SDIO_CCCR_IENx, NULL); + sdio_release_host(bus->func); + flags = irq_get_trigger_type(bus->of_irq); + if (!flags) + flags = IRQF_TRIGGER_HIGH; + flags |= IRQF_ONESHOT; + return devm_request_threaded_irq(&bus->func->dev, bus->of_irq, NULL, + wfx_sdio_irq_handler_ext, flags, + "wfx", bus); } -static int wfx_sdio_irq_unsubscribe(struct wfx_sdio_priv *bus) +static int wfx_sdio_irq_unsubscribe(void *priv) { + struct wfx_sdio_priv *bus = priv; int ret; - if (bus->of_irq) { - free_irq(bus->of_irq, bus); - ret = 0; - } else { - sdio_claim_host(bus->func); - ret = sdio_release_irq(bus->func); - sdio_release_host(bus->func); - } + if (bus->of_irq) + devm_free_irq(&bus->func->dev, bus->of_irq, bus); + sdio_claim_host(bus->func); + ret = sdio_release_irq(bus->func); + sdio_release_host(bus->func); return ret; } @@ -151,12 +158,20 @@ static size_t wfx_sdio_align_size(void *priv, size_t size) static const struct hwbus_ops wfx_sdio_hwbus_ops = { .copy_from_io = wfx_sdio_copy_from_io, .copy_to_io = wfx_sdio_copy_to_io, + .irq_subscribe = wfx_sdio_irq_subscribe, + .irq_unsubscribe = wfx_sdio_irq_unsubscribe, .lock = wfx_sdio_lock, .unlock = wfx_sdio_unlock, .align_size = wfx_sdio_align_size, }; -static const struct of_device_id wfx_sdio_of_match[]; +static const struct of_device_id wfx_sdio_of_match[] = { + { .compatible = "silabs,wfx-sdio" }, + { .compatible = "silabs,wf200" }, + { }, +}; +MODULE_DEVICE_TABLE(of, wfx_sdio_of_match); + static int wfx_sdio_probe(struct sdio_func *func, const struct sdio_device_id *id) { @@ -165,7 +180,8 @@ static int wfx_sdio_probe(struct sdio_func *func, int ret; if (func->num != 1) { - dev_err(&func->dev, "SDIO function number is %d while it should always be 1 (unsupported chip?)\n", func->num); + dev_err(&func->dev, "SDIO function number is %d while it should always be 1 (unsupported chip?)\n", + func->num); return -ENODEV; } @@ -207,18 +223,12 @@ static int wfx_sdio_probe(struct sdio_func *func, goto err1; } - ret = wfx_sdio_irq_subscribe(bus); + ret = wfx_probe(bus->core); if (ret) goto err1; - ret = wfx_probe(bus->core); - if (ret) - goto err2; - return 0; -err2: - wfx_sdio_irq_unsubscribe(bus); err1: sdio_claim_host(func); sdio_disable_func(func); @@ -232,7 +242,6 @@ static void wfx_sdio_remove(struct sdio_func *func) struct wfx_sdio_priv *bus = sdio_get_drvdata(func); wfx_release(bus->core); - wfx_sdio_irq_unsubscribe(bus); sdio_claim_host(func); sdio_disable_func(func); sdio_release_host(func); @@ -248,15 +257,6 @@ static const struct sdio_device_id wfx_sdio_ids[] = { }; MODULE_DEVICE_TABLE(sdio, wfx_sdio_ids); -#ifdef CONFIG_OF -static const struct of_device_id wfx_sdio_of_match[] = { - { .compatible = "silabs,wfx-sdio" }, - { .compatible = "silabs,wf200" }, - { }, -}; -MODULE_DEVICE_TABLE(of, wfx_sdio_of_match); -#endif - struct sdio_driver wfx_sdio_driver = { .name = "wfx-sdio", .id_table = wfx_sdio_ids, @@ -264,6 +264,6 @@ struct sdio_driver wfx_sdio_driver = { .remove = wfx_sdio_remove, .drv = { .owner = THIS_MODULE, - .of_match_table = of_match_ptr(wfx_sdio_of_match), + .of_match_table = wfx_sdio_of_match, } }; diff --git a/drivers/staging/wfx/bus_spi.c b/drivers/staging/wfx/bus_spi.c index 61e99b09decb..e8da61fb096b 100644 --- a/drivers/staging/wfx/bus_spi.c +++ b/drivers/staging/wfx/bus_spi.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include "bus.h" @@ -39,7 +40,6 @@ struct wfx_spi_priv { struct spi_device *func; struct wfx_dev *core; struct gpio_desc *gpio_reset; - struct work_struct request_rx; bool need_swab; }; @@ -140,25 +140,30 @@ static irqreturn_t wfx_spi_irq_handler(int irq, void *priv) { struct wfx_spi_priv *bus = priv; - if (!bus->core) { - WARN(!bus->core, "race condition in driver init/deinit"); - return IRQ_NONE; - } - queue_work(system_highpri_wq, &bus->request_rx); + wfx_bh_request_rx(bus->core); return IRQ_HANDLED; } -static void wfx_spi_request_rx(struct work_struct *work) +static int wfx_spi_irq_subscribe(void *priv) { - struct wfx_spi_priv *bus = - container_of(work, struct wfx_spi_priv, request_rx); + struct wfx_spi_priv *bus = priv; + u32 flags; - wfx_bh_request_rx(bus->core); + flags = irq_get_trigger_type(bus->func->irq); + if (!flags) + flags = IRQF_TRIGGER_HIGH; + flags |= IRQF_ONESHOT; + return devm_request_threaded_irq(&bus->func->dev, bus->func->irq, NULL, + wfx_spi_irq_handler, IRQF_ONESHOT, + "wfx", bus); } -static void wfx_flush_irq_work(void *w) +static int wfx_spi_irq_unsubscribe(void *priv) { - flush_work(w); + struct wfx_spi_priv *bus = priv; + + devm_free_irq(&bus->func->dev, bus->func->irq, bus); + return 0; } static size_t wfx_spi_align_size(void *priv, size_t size) @@ -170,6 +175,8 @@ static size_t wfx_spi_align_size(void *priv, size_t size) static const struct hwbus_ops wfx_spi_hwbus_ops = { .copy_from_io = wfx_spi_copy_from_io, .copy_to_io = wfx_spi_copy_to_io, + .irq_subscribe = wfx_spi_irq_subscribe, + .irq_unsubscribe = wfx_spi_irq_unsubscribe, .lock = wfx_spi_lock, .unlock = wfx_spi_unlock, .align_size = wfx_spi_align_size, @@ -216,22 +223,11 @@ static int wfx_spi_probe(struct spi_device *func) usleep_range(2000, 2500); } - INIT_WORK(&bus->request_rx, wfx_spi_request_rx); bus->core = wfx_init_common(&func->dev, &wfx_spi_pdata, &wfx_spi_hwbus_ops, bus); if (!bus->core) return -EIO; - ret = devm_add_action_or_reset(&func->dev, wfx_flush_irq_work, - &bus->request_rx); - if (ret) - return ret; - - ret = devm_request_irq(&func->dev, func->irq, wfx_spi_irq_handler, - IRQF_TRIGGER_RISING, "wfx", bus); - if (ret) - return ret; - return wfx_probe(bus->core); } diff --git a/drivers/staging/wfx/data_rx.c b/drivers/staging/wfx/data_rx.c index c5b83fedeb55..0e959ebc38b5 100644 --- a/drivers/staging/wfx/data_rx.c +++ b/drivers/staging/wfx/data_rx.c @@ -49,7 +49,7 @@ static int wfx_drop_encrypt_data(struct wfx_dev *wdev, } /* Firmware strips ICV in case of MIC failure. */ - if (arg->status == HIF_STATUS_MICFAILURE) + if (arg->status == HIF_STATUS_RX_FAIL_MIC) icv_len = 0; if (skb->len < hdrlen + iv_len + icv_len) { @@ -79,7 +79,7 @@ void wfx_rx_cb(struct wfx_vif *wvif, ieee80211_is_beacon(frame->frame_control))) goto drop; - if (arg->status == HIF_STATUS_MICFAILURE) + if (arg->status == HIF_STATUS_RX_FAIL_MIC) hdr->flag |= RX_FLAG_MMIC_ERROR; else if (arg->status) goto drop; @@ -118,18 +118,6 @@ void wfx_rx_cb(struct wfx_vif *wvif, arg->rx_flags.match_uc_addr && mgmt->u.action.category == WLAN_CATEGORY_BACK) goto drop; - if (ieee80211_is_beacon(frame->frame_control) && - !arg->status && wvif->vif && - ether_addr_equal(ieee80211_get_SA(frame), - wvif->vif->bss_conf.bssid)) { - /* Disable beacon filter once we're associated... */ - if (wvif->disable_beacon_filter && - (wvif->vif->bss_conf.assoc || - wvif->vif->bss_conf.ibss_joined)) { - wvif->disable_beacon_filter = false; - schedule_work(&wvif->update_filtering_work); - } - } ieee80211_rx_irqsafe(wvif->wdev->hw, skb); return; diff --git a/drivers/staging/wfx/data_rx.h b/drivers/staging/wfx/data_rx.h index 61c28bfd2a37..125dbfc1f875 100644 --- a/drivers/staging/wfx/data_rx.h +++ b/drivers/staging/wfx/data_rx.h @@ -8,10 +8,9 @@ #ifndef WFX_DATA_RX_H #define WFX_DATA_RX_H -#include "hif_api_cmd.h" - struct wfx_vif; struct sk_buff; +struct hif_ind_rx; void wfx_rx_cb(struct wfx_vif *wvif, const struct hif_ind_rx *arg, struct sk_buff *skb); diff --git a/drivers/staging/wfx/data_tx.c b/drivers/staging/wfx/data_tx.c index 42183c70d4df..f042ef36b408 100644 --- a/drivers/staging/wfx/data_tx.c +++ b/drivers/staging/wfx/data_tx.c @@ -6,6 +6,7 @@ * Copyright (c) 2010, ST-Ericsson */ #include +#include #include "data_tx.h" #include "wfx.h" @@ -16,12 +17,11 @@ #include "traces.h" #include "hif_tx_mib.h" -#define WFX_INVALID_RATE_ID 15 -#define WFX_LINK_ID_GC_TIMEOUT ((unsigned long)(10 * HZ)) - static int wfx_get_hw_rate(struct wfx_dev *wdev, const struct ieee80211_tx_rate *rate) { + struct ieee80211_supported_band *band; + if (rate->idx < 0) return -1; if (rate->flags & IEEE80211_TX_RC_MCS) { @@ -33,7 +33,8 @@ static int wfx_get_hw_rate(struct wfx_dev *wdev, } // WFx only support 2GHz, else band information should be retrieved // from ieee80211_tx_info - return wdev->hw->wiphy->bands[NL80211_BAND_2GHZ]->bitrates[rate->idx].hw_value; + band = wdev->hw->wiphy->bands[NL80211_BAND_2GHZ]; + return band->bitrates[rate->idx].hw_value; } /* TX policy cache implementation */ @@ -41,73 +42,13 @@ static int wfx_get_hw_rate(struct wfx_dev *wdev, static void wfx_tx_policy_build(struct wfx_vif *wvif, struct tx_policy *policy, struct ieee80211_tx_rate *rates) { - int i; - size_t count; struct wfx_dev *wdev = wvif->wdev; + int i, rateid; + u8 count; WARN(rates[0].idx < 0, "invalid rate policy"); memset(policy, 0, sizeof(*policy)); - for (i = 1; i < IEEE80211_TX_MAX_RATES; i++) - if (rates[i].idx < 0) - break; - count = i; - - /* HACK!!! Device has problems (at least) switching from - * 54Mbps CTS to 1Mbps. This switch takes enormous amount - * of time (100-200 ms), leading to valuable throughput drop. - * As a workaround, additional g-rates are injected to the - * policy. - */ - if (count == 2 && !(rates[0].flags & IEEE80211_TX_RC_MCS) && - rates[0].idx > 4 && rates[0].count > 2 && - rates[1].idx < 2) { - int mid_rate = (rates[0].idx + 4) >> 1; - - /* Decrease number of retries for the initial rate */ - rates[0].count -= 2; - - if (mid_rate != 4) { - /* Keep fallback rate at 1Mbps. */ - rates[3] = rates[1]; - - /* Inject 1 transmission on lowest g-rate */ - rates[2].idx = 4; - rates[2].count = 1; - rates[2].flags = rates[1].flags; - - /* Inject 1 transmission on mid-rate */ - rates[1].idx = mid_rate; - rates[1].count = 1; - - /* Fallback to 1 Mbps is a really bad thing, - * so let's try to increase probability of - * successful transmission on the lowest g rate - * even more - */ - if (rates[0].count >= 3) { - --rates[0].count; - ++rates[2].count; - } - - /* Adjust amount of rates defined */ - count += 2; - } else { - /* Keep fallback rate at 1Mbps. */ - rates[2] = rates[1]; - - /* Inject 2 transmissions on lowest g-rate */ - rates[1].idx = 4; - rates[1].count = 2; - - /* Adjust amount of rates defined */ - count += 1; - } - } - for (i = 0; i < IEEE80211_TX_MAX_RATES; ++i) { - int rateid; - u8 count; - if (rates[i].idx < 0) break; WARN_ON(rates[i].count > 15); @@ -158,8 +99,7 @@ static int wfx_tx_policy_release(struct tx_policy_cache *cache, } static int wfx_tx_policy_get(struct wfx_vif *wvif, - struct ieee80211_tx_rate *rates, - bool *renew) + struct ieee80211_tx_rate *rates, bool *renew) { int idx; struct tx_policy_cache *cache = &wvif->tx_policy_cache; @@ -171,7 +111,7 @@ static int wfx_tx_policy_get(struct wfx_vif *wvif, if (list_empty(&cache->free)) { WARN(1, "unable to get a valid Tx policy"); spin_unlock_bh(&cache->lock); - return WFX_INVALID_RATE_ID; + return HIF_TX_RETRY_POLICY_INVALID; } idx = wfx_tx_policy_find(cache, &wanted); if (idx >= 0) { @@ -189,10 +129,8 @@ static int wfx_tx_policy_get(struct wfx_vif *wvif, idx = entry - cache->cache; } wfx_tx_policy_use(cache, &cache->cache[idx]); - if (list_empty(&cache->free)) { - /* Lock TX queues. */ - wfx_tx_queues_lock(wvif->wdev); - } + if (list_empty(&cache->free)) + ieee80211_stop_queues(wvif->wdev->hw); spin_unlock_bh(&cache->lock); return idx; } @@ -202,15 +140,13 @@ static void wfx_tx_policy_put(struct wfx_vif *wvif, int idx) int usage, locked; struct tx_policy_cache *cache = &wvif->tx_policy_cache; - if (idx == WFX_INVALID_RATE_ID) + if (idx == HIF_TX_RETRY_POLICY_INVALID) return; spin_lock_bh(&cache->lock); locked = list_empty(&cache->free); usage = wfx_tx_policy_release(cache, &cache->cache[idx]); - if (locked && !usage) { - /* Unlock TX queues. */ - wfx_tx_queues_unlock(wvif->wdev); - } + if (locked && !usage) + ieee80211_wake_queues(wvif->wdev->hw); spin_unlock_bh(&cache->lock); } @@ -218,15 +154,17 @@ static int wfx_tx_policy_upload(struct wfx_vif *wvif) { struct tx_policy *policies = wvif->tx_policy_cache.cache; u8 tmp_rates[12]; - int i; + int i, is_used; do { spin_lock_bh(&wvif->tx_policy_cache.lock); - for (i = 0; i < HIF_MIB_NUM_TX_RATE_RETRY_POLICIES; ++i) - if (!policies[i].uploaded && - memzcmp(policies[i].rates, sizeof(policies[i].rates))) + for (i = 0; i < ARRAY_SIZE(wvif->tx_policy_cache.cache); ++i) { + is_used = memzcmp(policies[i].rates, + sizeof(policies[i].rates)); + if (!policies[i].uploaded && is_used) break; - if (i < HIF_MIB_NUM_TX_RATE_RETRY_POLICIES) { + } + if (i < ARRAY_SIZE(wvif->tx_policy_cache.cache)) { policies[i].uploaded = true; memcpy(tmp_rates, policies[i].rates, sizeof(tmp_rates)); spin_unlock_bh(&wvif->tx_policy_cache.lock); @@ -234,7 +172,7 @@ static int wfx_tx_policy_upload(struct wfx_vif *wvif) } else { spin_unlock_bh(&wvif->tx_policy_cache.lock); } - } while (i < HIF_MIB_NUM_TX_RATE_RETRY_POLICIES); + } while (i < ARRAY_SIZE(wvif->tx_policy_cache.cache)); return 0; } @@ -244,9 +182,7 @@ void wfx_tx_policy_upload_work(struct work_struct *work) container_of(work, struct wfx_vif, tx_policy_upload_work); wfx_tx_policy_upload(wvif); - wfx_tx_unlock(wvif->wdev); - wfx_tx_queues_unlock(wvif->wdev); } void wfx_tx_policy_init(struct wfx_vif *wvif) @@ -260,7 +196,7 @@ void wfx_tx_policy_init(struct wfx_vif *wvif) INIT_LIST_HEAD(&cache->used); INIT_LIST_HEAD(&cache->free); - for (i = 0; i < HIF_MIB_NUM_TX_RATE_RETRY_POLICIES; ++i) + for (i = 0; i < ARRAY_SIZE(cache->cache); ++i) list_add(&cache->cache[i].link, &cache->free); } @@ -281,16 +217,11 @@ static void wfx_tx_manage_pm(struct wfx_vif *wvif, struct ieee80211_hdr *hdr, struct wfx_tx_priv *tx_priv, struct ieee80211_sta *sta) { - u32 mask = ~BIT(tx_priv->raw_link_id); struct wfx_sta_priv *sta_priv; int tid = ieee80211_get_tid(hdr); - spin_lock_bh(&wvif->ps_state_lock); - if (ieee80211_is_auth(hdr->frame_control)) - wvif->sta_asleep_mask &= mask; - spin_unlock_bh(&wvif->ps_state_lock); - if (sta) { + tx_priv->has_sta = true; sta_priv = (struct wfx_sta_priv *)&sta->drv_priv; spin_lock_bh(&sta_priv->lock); sta_priv->buffered[tid]++; @@ -299,9 +230,8 @@ static void wfx_tx_manage_pm(struct wfx_vif *wvif, struct ieee80211_hdr *hdr, } } -static u8 wfx_tx_get_raw_link_id(struct wfx_vif *wvif, - struct ieee80211_sta *sta, - struct ieee80211_hdr *hdr) +static u8 wfx_tx_get_link_id(struct wfx_vif *wvif, struct ieee80211_sta *sta, + struct ieee80211_hdr *hdr) { struct wfx_sta_priv *sta_priv = sta ? (struct wfx_sta_priv *)&sta->drv_priv : NULL; @@ -313,7 +243,7 @@ static u8 wfx_tx_get_raw_link_id(struct wfx_vif *wvif, return 0; if (is_multicast_ether_addr(da)) return 0; - return WFX_LINK_ID_NO_ASSOC; + return HIF_LINK_ID_NOT_ASSOCIATED; } static void wfx_tx_fixup_rates(struct ieee80211_tx_rate *rates) @@ -358,7 +288,8 @@ static void wfx_tx_fixup_rates(struct ieee80211_tx_rate *rates) if (rates[i].idx == -1) { rates[i].idx = 0; rates[i].count = 8; // == hw->max_rate_tries - rates[i].flags = rates[i - 1].flags & IEEE80211_TX_RC_MCS; + rates[i].flags = rates[i - 1].flags & + IEEE80211_TX_RC_MCS; break; } } @@ -375,24 +306,19 @@ static u8 wfx_tx_get_rate_id(struct wfx_vif *wvif, rate_id = wfx_tx_policy_get(wvif, tx_info->driver_rates, &tx_policy_renew); - if (rate_id == WFX_INVALID_RATE_ID) + if (rate_id == HIF_TX_RETRY_POLICY_INVALID) dev_warn(wvif->wdev->dev, "unable to get a valid Tx policy"); if (tx_policy_renew) { - /* FIXME: It's not so optimal to stop TX queues every now and - * then. Better to reimplement task scheduling with a counter. - */ wfx_tx_lock(wvif->wdev); - wfx_tx_queues_lock(wvif->wdev); - if (!schedule_work(&wvif->tx_policy_upload_work)) { - wfx_tx_queues_unlock(wvif->wdev); + if (!schedule_work(&wvif->tx_policy_upload_work)) wfx_tx_unlock(wvif->wdev); - } } return rate_id; } -static struct hif_ht_tx_parameters wfx_tx_get_tx_parms(struct wfx_dev *wdev, struct ieee80211_tx_info *tx_info) +static struct hif_ht_tx_parameters wfx_tx_get_tx_parms(struct wfx_dev *wdev, + struct ieee80211_tx_info *tx_info) { struct ieee80211_tx_rate *rate = &tx_info->driver_rates[0]; struct hif_ht_tx_parameters ret = { }; @@ -429,7 +355,7 @@ static int wfx_tx_inner(struct wfx_vif *wvif, struct ieee80211_sta *sta, struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); struct ieee80211_key_conf *hw_key = tx_info->control.hw_key; struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; - int queue_id = tx_info->hw_queue; + int queue_id = skb_get_queue_mapping(skb); size_t offset = (size_t)skb->data & 3; int wmsg_len = sizeof(struct hif_msg) + sizeof(struct hif_req_tx) + offset; @@ -441,14 +367,8 @@ static int wfx_tx_inner(struct wfx_vif *wvif, struct ieee80211_sta *sta, memset(tx_info->rate_driver_data, 0, sizeof(struct wfx_tx_priv)); // Fill tx_priv tx_priv = (struct wfx_tx_priv *)tx_info->rate_driver_data; - tx_priv->raw_link_id = wfx_tx_get_raw_link_id(wvif, sta, hdr); - tx_priv->link_id = tx_priv->raw_link_id; if (ieee80211_has_protected(hdr->frame_control)) tx_priv->hw_key = hw_key; - if (tx_info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) - tx_priv->link_id = WFX_LINK_ID_AFTER_DTIM; - if (sta && (sta->uapsd_queues & BIT(queue_id))) - tx_priv->link_id = WFX_LINK_ID_UAPSD; // Fill hif_msg WARN(skb_headroom(skb) < wmsg_len, "not enough space in skb"); @@ -461,7 +381,8 @@ static int wfx_tx_inner(struct wfx_vif *wvif, struct ieee80211_sta *sta, hif_msg->id = HIF_REQ_ID_TX; hif_msg->interface = wvif->id; if (skb->len > wvif->wdev->hw_caps.size_inp_ch_buf) { - dev_warn(wvif->wdev->dev, "requested frame size (%d) is larger than maximum supported (%d)\n", + dev_warn(wvif->wdev->dev, + "requested frame size (%d) is larger than maximum supported (%d)\n", skb->len, wvif->wdev->hw_caps.size_inp_ch_buf); skb_pull(skb, wmsg_len); return -EIO; @@ -472,13 +393,14 @@ static int wfx_tx_inner(struct wfx_vif *wvif, struct ieee80211_sta *sta, // packet_id just need to be unique on device. 32bits are more than // necessary for that task, so we tae advantage of it to add some extra // data for debug. - req->packet_id = queue_id << 28 | - IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)) << 16 | - (atomic_add_return(1, &wvif->wdev->packet_id) & 0xFFFF); + req->packet_id = atomic_add_return(1, &wvif->wdev->packet_id) & 0xFFFF; + req->packet_id |= IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)) << 16; + req->packet_id |= queue_id << 28; + req->data_flags.fc_offset = offset; if (tx_info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) req->data_flags.after_dtim = 1; - req->queue_id.peer_sta_id = tx_priv->raw_link_id; + req->queue_id.peer_sta_id = wfx_tx_get_link_id(wvif, sta, hdr); // Queue index are inverted between firmware and Linux req->queue_id.queue_id = 3 - queue_id; req->ht_tx_parameters = wfx_tx_get_tx_parms(wvif->wdev, tx_info); @@ -486,7 +408,7 @@ static int wfx_tx_inner(struct wfx_vif *wvif, struct ieee80211_sta *sta, // Auxiliary operations wfx_tx_manage_pm(wvif, hdr, tx_priv, sta); - wfx_tx_queue_put(wvif->wdev, &wvif->wdev->tx_queue[queue_id], skb); + wfx_tx_queues_put(wvif->wdev, skb); if (tx_info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) schedule_work(&wvif->update_tim_work); wfx_bh_request_tx(wvif->wdev); @@ -528,98 +450,19 @@ drop: ieee80211_tx_status_irqsafe(wdev->hw, skb); } -void wfx_tx_confirm_cb(struct wfx_vif *wvif, const struct hif_cnf_tx *arg) +static struct ieee80211_hdr *wfx_skb_hdr80211(struct sk_buff *skb) { - int i; - int tx_count; - struct sk_buff *skb; - struct ieee80211_tx_rate *rate; - struct ieee80211_tx_info *tx_info; - const struct wfx_tx_priv *tx_priv; + struct hif_msg *hif = (struct hif_msg *)skb->data; + struct hif_req_tx *req = (struct hif_req_tx *)hif->body; - skb = wfx_pending_get(wvif->wdev, arg->packet_id); - if (!skb) { - dev_warn(wvif->wdev->dev, - "received unknown packet_id (%#.8x) from chip\n", - arg->packet_id); - return; - } - tx_info = IEEE80211_SKB_CB(skb); - tx_priv = wfx_skb_tx_priv(skb); - _trace_tx_stats(arg, skb, - wfx_pending_get_pkt_us_delay(wvif->wdev, skb)); - - // You can touch to tx_priv, but don't touch to tx_info->status. - tx_count = arg->ack_failures; - if (!arg->status || arg->ack_failures) - tx_count += 1; // Also report success - for (i = 0; i < IEEE80211_TX_MAX_RATES; i++) { - rate = &tx_info->status.rates[i]; - if (rate->idx < 0) - break; - if (tx_count < rate->count && - arg->status == HIF_STATUS_RETRY_EXCEEDED && - arg->ack_failures) - dev_dbg(wvif->wdev->dev, "all retries were not consumed: %d != %d\n", - rate->count, tx_count); - if (tx_count <= rate->count && tx_count && - arg->txed_rate != wfx_get_hw_rate(wvif->wdev, rate)) - dev_dbg(wvif->wdev->dev, - "inconsistent tx_info rates: %d != %d\n", - arg->txed_rate, - wfx_get_hw_rate(wvif->wdev, rate)); - if (tx_count > rate->count) { - tx_count -= rate->count; - } else if (!tx_count) { - rate->count = 0; - rate->idx = -1; - } else { - rate->count = tx_count; - tx_count = 0; - } - } - if (tx_count) - dev_dbg(wvif->wdev->dev, - "%d more retries than expected\n", tx_count); - skb_trim(skb, skb->len - wfx_tx_get_icv_len(tx_priv->hw_key)); - - // From now, you can touch to tx_info->status, but do not touch to - // tx_priv anymore - // FIXME: use ieee80211_tx_info_clear_status() - memset(tx_info->rate_driver_data, 0, sizeof(tx_info->rate_driver_data)); - memset(tx_info->pad, 0, sizeof(tx_info->pad)); - - if (!arg->status) { - if (wvif->bss_loss_state && - arg->packet_id == wvif->bss_loss_confirm_id) - wfx_cqm_bssloss_sm(wvif, 0, 1, 0); - tx_info->status.tx_time = - arg->media_delay - arg->tx_queue_delay; - if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) - tx_info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; - else - tx_info->flags |= IEEE80211_TX_STAT_ACK; - } else if (arg->status == HIF_REQUEUE) { - WARN(!arg->tx_result_flags.requeue, "incoherent status and result_flags"); - if (tx_info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) { - wvif->after_dtim_tx_allowed = false; // DTIM period elapsed - schedule_work(&wvif->update_tim_work); - } - tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; - } else { - if (wvif->bss_loss_state && - arg->packet_id == wvif->bss_loss_confirm_id) - wfx_cqm_bssloss_sm(wvif, 0, 0, 1); - } - wfx_pending_remove(wvif->wdev, skb); + return (struct ieee80211_hdr *)(req->frame + req->data_flags.fc_offset); } -static void wfx_notify_buffered_tx(struct wfx_vif *wvif, struct sk_buff *skb) +static void wfx_tx_update_sta(struct wfx_vif *wvif, struct ieee80211_hdr *hdr) { - struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; - struct ieee80211_sta *sta; - struct wfx_sta_priv *sta_priv; int tid = ieee80211_get_tid(hdr); + struct wfx_sta_priv *sta_priv; + struct ieee80211_sta *sta; rcu_read_lock(); // protect sta sta = ieee80211_find_sta(wvif->vif, hdr->addr1); @@ -631,22 +474,153 @@ static void wfx_notify_buffered_tx(struct wfx_vif *wvif, struct sk_buff *skb) if (!sta_priv->buffered[tid]) ieee80211_sta_set_buffered(sta, tid, false); spin_unlock_bh(&sta_priv->lock); + } else { + dev_dbg(wvif->wdev->dev, "%s: sta does not exist anymore\n", + __func__); } rcu_read_unlock(); } -void wfx_skb_dtor(struct wfx_dev *wdev, struct sk_buff *skb) +static void wfx_skb_dtor(struct wfx_vif *wvif, struct sk_buff *skb) { struct hif_msg *hif = (struct hif_msg *)skb->data; struct hif_req_tx *req = (struct hif_req_tx *)hif->body; - struct wfx_vif *wvif = wdev_to_wvif(wdev, hif->interface); - unsigned int offset = sizeof(struct hif_req_tx) + - sizeof(struct hif_msg) + - req->data_flags.fc_offset; + unsigned int offset = sizeof(struct hif_msg) + + sizeof(struct hif_req_tx) + + req->data_flags.fc_offset; WARN_ON(!wvif); - skb_pull(skb, offset); - wfx_notify_buffered_tx(wvif, skb); wfx_tx_policy_put(wvif, req->tx_flags.retry_policy_index); - ieee80211_tx_status_irqsafe(wdev->hw, skb); + skb_pull(skb, offset); + ieee80211_tx_status_irqsafe(wvif->wdev->hw, skb); } + +static void wfx_tx_fill_rates(struct wfx_dev *wdev, + struct ieee80211_tx_info *tx_info, + const struct hif_cnf_tx *arg) +{ + struct ieee80211_tx_rate *rate; + int tx_count; + int i; + + tx_count = arg->ack_failures; + if (!arg->status || arg->ack_failures) + tx_count += 1; // Also report success + for (i = 0; i < IEEE80211_TX_MAX_RATES; i++) { + rate = &tx_info->status.rates[i]; + if (rate->idx < 0) + break; + if (tx_count < rate->count && + arg->status == HIF_STATUS_TX_FAIL_RETRIES && + arg->ack_failures) + dev_dbg(wdev->dev, "all retries were not consumed: %d != %d\n", + rate->count, tx_count); + if (tx_count <= rate->count && tx_count && + arg->txed_rate != wfx_get_hw_rate(wdev, rate)) + dev_dbg(wdev->dev, "inconsistent tx_info rates: %d != %d\n", + arg->txed_rate, wfx_get_hw_rate(wdev, rate)); + if (tx_count > rate->count) { + tx_count -= rate->count; + } else if (!tx_count) { + rate->count = 0; + rate->idx = -1; + } else { + rate->count = tx_count; + tx_count = 0; + } + } + if (tx_count) + dev_dbg(wdev->dev, "%d more retries than expected\n", tx_count); +} + +void wfx_tx_confirm_cb(struct wfx_vif *wvif, const struct hif_cnf_tx *arg) +{ + struct ieee80211_tx_info *tx_info; + const struct wfx_tx_priv *tx_priv; + struct sk_buff *skb; + + skb = wfx_pending_get(wvif->wdev, arg->packet_id); + if (!skb) { + dev_warn(wvif->wdev->dev, "received unknown packet_id (%#.8x) from chip\n", + arg->packet_id); + return; + } + tx_info = IEEE80211_SKB_CB(skb); + tx_priv = wfx_skb_tx_priv(skb); + _trace_tx_stats(arg, skb, + wfx_pending_get_pkt_us_delay(wvif->wdev, skb)); + + // You can touch to tx_priv, but don't touch to tx_info->status. + wfx_tx_fill_rates(wvif->wdev, tx_info, arg); + if (tx_priv->has_sta) + wfx_tx_update_sta(wvif, wfx_skb_hdr80211(skb)); + skb_trim(skb, skb->len - wfx_tx_get_icv_len(tx_priv->hw_key)); + + // From now, you can touch to tx_info->status, but do not touch to + // tx_priv anymore + // FIXME: use ieee80211_tx_info_clear_status() + memset(tx_info->rate_driver_data, 0, sizeof(tx_info->rate_driver_data)); + memset(tx_info->pad, 0, sizeof(tx_info->pad)); + + if (!arg->status) { + tx_info->status.tx_time = + le32_to_cpu(arg->media_delay) - + le32_to_cpu(arg->tx_queue_delay); + if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) + tx_info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; + else + tx_info->flags |= IEEE80211_TX_STAT_ACK; + } else if (arg->status == HIF_STATUS_TX_FAIL_REQUEUE) { + WARN(!arg->tx_result_flags.requeue, + "incoherent status and result_flags"); + if (tx_info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) { + wvif->after_dtim_tx_allowed = false; // DTIM period elapsed + schedule_work(&wvif->update_tim_work); + } + tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; + } + wfx_skb_dtor(wvif, skb); +} + +void wfx_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, + u32 queues, bool drop) +{ + struct wfx_dev *wdev = hw->priv; + struct sk_buff_head dropped; + struct wfx_queue *queue; + struct wfx_vif *wvif; + struct hif_msg *hif; + struct sk_buff *skb; + int vif_id = -1; + int i; + + if (vif) + vif_id = ((struct wfx_vif *)vif->drv_priv)->id; + skb_queue_head_init(&dropped); + for (i = 0; i < IEEE80211_NUM_ACS; i++) { + if (!(BIT(i) & queues)) + continue; + queue = &wdev->tx_queue[i]; + if (drop) + wfx_tx_queue_drop(wdev, queue, vif_id, &dropped); + if (wdev->chip_frozen) + continue; + if (wait_event_timeout(wdev->tx_dequeue, + wfx_tx_queue_empty(wdev, queue, vif_id), + msecs_to_jiffies(1000)) <= 0) + dev_warn(wdev->dev, + "frames queued while flushing tx queues?"); + } + wfx_tx_flush(wdev); + if (wdev->chip_frozen) + wfx_pending_drop(wdev, &dropped); + while ((skb = skb_dequeue(&dropped)) != NULL) { + hif = (struct hif_msg *)skb->data; + wvif = wdev_to_wvif(wdev, hif->interface); + if (wfx_skb_tx_priv(skb)->has_sta) + wfx_tx_update_sta(wvif, wfx_skb_hdr80211(skb)); + ieee80211_tx_info_clear_status(IEEE80211_SKB_CB(skb)); + wfx_skb_dtor(wvif, skb); + } +} + diff --git a/drivers/staging/wfx/data_tx.h b/drivers/staging/wfx/data_tx.h index c545dd75449b..54fff24508fb 100644 --- a/drivers/staging/wfx/data_tx.h +++ b/drivers/staging/wfx/data_tx.h @@ -26,7 +26,7 @@ struct tx_policy { }; struct tx_policy_cache { - struct tx_policy cache[HIF_MIB_NUM_TX_RATE_RETRY_POLICIES]; + struct tx_policy cache[HIF_TX_RETRY_POLICY_MAX]; // FIXME: use a trees and drop hash from tx_policy struct list_head used; struct list_head free; @@ -36,8 +36,7 @@ struct tx_policy_cache { struct wfx_tx_priv { ktime_t xmit_timestamp; struct ieee80211_key_conf *hw_key; - u8 link_id; - u8 raw_link_id; + bool has_sta; } __packed; void wfx_tx_policy_init(struct wfx_vif *wvif); @@ -46,7 +45,8 @@ void wfx_tx_policy_upload_work(struct work_struct *work); void wfx_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control, struct sk_buff *skb); void wfx_tx_confirm_cb(struct wfx_vif *wvif, const struct hif_cnf_tx *arg); -void wfx_skb_dtor(struct wfx_dev *wdev, struct sk_buff *skb); +void wfx_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, + u32 queues, bool drop); static inline struct wfx_tx_priv *wfx_skb_tx_priv(struct sk_buff *skb) { diff --git a/drivers/staging/wfx/debug.c b/drivers/staging/wfx/debug.c index 1164aba118a1..10d649985696 100644 --- a/drivers/staging/wfx/debug.c +++ b/drivers/staging/wfx/debug.c @@ -61,19 +61,26 @@ const char *get_reg_name(unsigned long id) static int wfx_counters_show(struct seq_file *seq, void *v) { - int ret; + int ret, i; struct wfx_dev *wdev = seq->private; - struct hif_mib_extended_count_table counters; + struct hif_mib_extended_count_table counters[3]; - ret = hif_get_counters_table(wdev, &counters); - if (ret < 0) - return ret; - if (ret > 0) - return -EIO; + for (i = 0; i < ARRAY_SIZE(counters); i++) { + ret = hif_get_counters_table(wdev, i, counters + i); + if (ret < 0) + return ret; + if (ret > 0) + return -EIO; + } + + seq_printf(seq, "%-24s %12s %12s %12s\n", + "", "global", "iface 0", "iface 1"); #define PUT_COUNTER(name) \ - seq_printf(seq, "%24s %d\n", #name ":",\ - le32_to_cpu(counters.count_##name)) + seq_printf(seq, "%-24s %12d %12d %12d\n", #name, \ + le32_to_cpu(counters[2].count_##name), \ + le32_to_cpu(counters[0].count_##name), \ + le32_to_cpu(counters[1].count_##name)) PUT_COUNTER(tx_packets); PUT_COUNTER(tx_multicast_frames); @@ -105,6 +112,12 @@ static int wfx_counters_show(struct seq_file *seq, void *v) #undef PUT_COUNTER + for (i = 0; i < ARRAY_SIZE(counters[0].reserved); i++) + seq_printf(seq, "reserved[%02d]%12s %12d %12d %12d\n", i, "", + le32_to_cpu(counters[2].reserved[i]), + le32_to_cpu(counters[0].reserved[i]), + le32_to_cpu(counters[1].reserved[i])); + return 0; } DEFINE_SHOW_ATTRIBUTE(wfx_counters); @@ -142,7 +155,7 @@ static int wfx_rx_stats_show(struct seq_file *seq, void *v) mutex_lock(&wdev->rx_stats_lock); seq_printf(seq, "Timestamp: %dus\n", st->date); seq_printf(seq, "Low power clock: frequency %uHz, external %s\n", - st->pwr_clk_freq, + le32_to_cpu(st->pwr_clk_freq), st->is_ext_pwr_clk ? "yes" : "no"); seq_printf(seq, "Num. of frames: %d, PER (x10e4): %d, Throughput: %dKbps/s\n", @@ -152,9 +165,12 @@ static int wfx_rx_stats_show(struct seq_file *seq, void *v) for (i = 0; i < ARRAY_SIZE(channel_names); i++) { if (channel_names[i]) seq_printf(seq, "%5s %8d %8d %8d %8d %8d\n", - channel_names[i], st->nb_rx_by_rate[i], - st->per[i], st->rssi[i] / 100, - st->snr[i] / 100, st->cfo[i]); + channel_names[i], + le32_to_cpu(st->nb_rx_by_rate[i]), + le16_to_cpu(st->per[i]), + (s16)le16_to_cpu(st->rssi[i]) / 100, + (s16)le16_to_cpu(st->snr[i]) / 100, + (s16)le16_to_cpu(st->cfo[i])); } mutex_unlock(&wdev->rx_stats_lock); @@ -162,6 +178,30 @@ static int wfx_rx_stats_show(struct seq_file *seq, void *v) } DEFINE_SHOW_ATTRIBUTE(wfx_rx_stats); +static int wfx_tx_power_loop_show(struct seq_file *seq, void *v) +{ + struct wfx_dev *wdev = seq->private; + struct hif_tx_power_loop_info *st = &wdev->tx_power_loop_info; + int tmp; + + mutex_lock(&wdev->tx_power_loop_info_lock); + tmp = le16_to_cpu(st->tx_gain_dig); + seq_printf(seq, "Tx gain digital: %d\n", tmp); + tmp = le16_to_cpu(st->tx_gain_pa); + seq_printf(seq, "Tx gain PA: %d\n", tmp); + tmp = (s16)le16_to_cpu(st->target_pout); + seq_printf(seq, "Target Pout: %d.%02d dBm\n", tmp / 4, (tmp % 4) * 25); + tmp = (s16)le16_to_cpu(st->p_estimation); + seq_printf(seq, "FEM Pout: %d.%02d dBm\n", tmp / 4, (tmp % 4) * 25); + tmp = le16_to_cpu(st->vpdet); + seq_printf(seq, "Vpdet: %d mV\n", tmp); + seq_printf(seq, "Measure index: %d\n", st->measurement_index); + mutex_unlock(&wdev->tx_power_loop_info_lock); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(wfx_tx_power_loop); + static ssize_t wfx_send_pds_write(struct file *file, const char __user *user_buf, size_t count, loff_t *ppos) @@ -234,7 +274,7 @@ static ssize_t wfx_send_hif_msg_write(struct file *file, request = memdup_user(user_buf, count); if (IS_ERR(request)) return PTR_ERR(request); - if (request->len != count) { + if (le16_to_cpu(request->len) != count) { kfree(request); return -EINVAL; } @@ -301,6 +341,8 @@ int wfx_debug_init(struct wfx_dev *wdev) d = debugfs_create_dir("wfx", wdev->hw->wiphy->debugfsdir); debugfs_create_file("counters", 0444, d, wdev, &wfx_counters_fops); debugfs_create_file("rx_stats", 0444, d, wdev, &wfx_rx_stats_fops); + debugfs_create_file("tx_power_loop", 0444, d, wdev, + &wfx_tx_power_loop_fops); debugfs_create_file("send_pds", 0200, d, wdev, &wfx_send_pds_fops); debugfs_create_file("burn_slk_key", 0200, d, wdev, &wfx_burn_slk_key_fops); diff --git a/drivers/staging/wfx/fwio.c b/drivers/staging/wfx/fwio.c index 9d61082c1e6c..72bb3d2a9613 100644 --- a/drivers/staging/wfx/fwio.c +++ b/drivers/staging/wfx/fwio.c @@ -99,16 +99,16 @@ static int sram_write_dma_safe(struct wfx_dev *wdev, u32 addr, const u8 *buf, return ret; } -int get_firmware(struct wfx_dev *wdev, u32 keyset_chip, - const struct firmware **fw, int *file_offset) +static int get_firmware(struct wfx_dev *wdev, u32 keyset_chip, + const struct firmware **fw, int *file_offset) { int keyset_file; char filename[256]; const char *data; int ret; - snprintf(filename, sizeof(filename), "%s_%02X.sec", wdev->pdata.file_fw, - keyset_chip); + snprintf(filename, sizeof(filename), "%s_%02X.sec", + wdev->pdata.file_fw, keyset_chip); ret = firmware_request_nowarn(fw, filename, wdev->dev); if (ret) { dev_info(wdev->dev, "can't load %s, falling back to %s.sec\n", @@ -325,8 +325,8 @@ static int init_gpr(struct wfx_dev *wdev) gpr_init[i].value); if (ret < 0) return ret; - dev_dbg(wdev->dev, " index %02x: %08x\n", gpr_init[i].index, - gpr_init[i].value); + dev_dbg(wdev->dev, " index %02x: %08x\n", + gpr_init[i].index, gpr_init[i].value); } return 0; } @@ -360,7 +360,7 @@ int wfx_init_device(struct wfx_dev *wdev) dev_dbg(wdev->dev, "initial config register value: %08x\n", reg); hw_revision = FIELD_GET(CFG_DEVICE_ID_MAJOR, reg); - if (hw_revision == 0 || hw_revision > 2) { + if (hw_revision == 0) { dev_err(wdev->dev, "bad hardware revision number: %d\n", hw_revision); return -ENODEV; diff --git a/drivers/staging/wfx/hif_api_cmd.h b/drivers/staging/wfx/hif_api_cmd.h index 071b71e2a107..21cde19cff75 100644 --- a/drivers/staging/wfx/hif_api_cmd.h +++ b/drivers/staging/wfx/hif_api_cmd.h @@ -10,56 +10,54 @@ #include "hif_api_general.h" -#define HIF_NUM_AC 4 - #define HIF_API_SSID_SIZE API_SSID_SIZE enum hif_requests_ids { - HIF_REQ_ID_RESET = 0x0a, - HIF_REQ_ID_READ_MIB = 0x05, - HIF_REQ_ID_WRITE_MIB = 0x06, - HIF_REQ_ID_START_SCAN = 0x07, - HIF_REQ_ID_STOP_SCAN = 0x08, - HIF_REQ_ID_TX = 0x04, - HIF_REQ_ID_JOIN = 0x0b, - HIF_REQ_ID_SET_PM_MODE = 0x10, - HIF_REQ_ID_SET_BSS_PARAMS = 0x11, - HIF_REQ_ID_ADD_KEY = 0x0c, - HIF_REQ_ID_REMOVE_KEY = 0x0d, - HIF_REQ_ID_EDCA_QUEUE_PARAMS = 0x13, - HIF_REQ_ID_START = 0x17, - HIF_REQ_ID_BEACON_TRANSMIT = 0x18, - HIF_REQ_ID_UPDATE_IE = 0x1b, - HIF_REQ_ID_MAP_LINK = 0x1c, + HIF_REQ_ID_RESET = 0x0a, + HIF_REQ_ID_READ_MIB = 0x05, + HIF_REQ_ID_WRITE_MIB = 0x06, + HIF_REQ_ID_START_SCAN = 0x07, + HIF_REQ_ID_STOP_SCAN = 0x08, + HIF_REQ_ID_TX = 0x04, + HIF_REQ_ID_JOIN = 0x0b, + HIF_REQ_ID_SET_PM_MODE = 0x10, + HIF_REQ_ID_SET_BSS_PARAMS = 0x11, + HIF_REQ_ID_ADD_KEY = 0x0c, + HIF_REQ_ID_REMOVE_KEY = 0x0d, + HIF_REQ_ID_EDCA_QUEUE_PARAMS = 0x13, + HIF_REQ_ID_START = 0x17, + HIF_REQ_ID_BEACON_TRANSMIT = 0x18, + HIF_REQ_ID_UPDATE_IE = 0x1b, + HIF_REQ_ID_MAP_LINK = 0x1c, }; enum hif_confirmations_ids { - HIF_CNF_ID_RESET = 0x0a, - HIF_CNF_ID_READ_MIB = 0x05, - HIF_CNF_ID_WRITE_MIB = 0x06, - HIF_CNF_ID_START_SCAN = 0x07, - HIF_CNF_ID_STOP_SCAN = 0x08, - HIF_CNF_ID_TX = 0x04, - HIF_CNF_ID_MULTI_TRANSMIT = 0x1e, - HIF_CNF_ID_JOIN = 0x0b, - HIF_CNF_ID_SET_PM_MODE = 0x10, - HIF_CNF_ID_SET_BSS_PARAMS = 0x11, - HIF_CNF_ID_ADD_KEY = 0x0c, - HIF_CNF_ID_REMOVE_KEY = 0x0d, - HIF_CNF_ID_EDCA_QUEUE_PARAMS = 0x13, - HIF_CNF_ID_START = 0x17, - HIF_CNF_ID_BEACON_TRANSMIT = 0x18, - HIF_CNF_ID_UPDATE_IE = 0x1b, - HIF_CNF_ID_MAP_LINK = 0x1c, + HIF_CNF_ID_RESET = 0x0a, + HIF_CNF_ID_READ_MIB = 0x05, + HIF_CNF_ID_WRITE_MIB = 0x06, + HIF_CNF_ID_START_SCAN = 0x07, + HIF_CNF_ID_STOP_SCAN = 0x08, + HIF_CNF_ID_TX = 0x04, + HIF_CNF_ID_MULTI_TRANSMIT = 0x1e, + HIF_CNF_ID_JOIN = 0x0b, + HIF_CNF_ID_SET_PM_MODE = 0x10, + HIF_CNF_ID_SET_BSS_PARAMS = 0x11, + HIF_CNF_ID_ADD_KEY = 0x0c, + HIF_CNF_ID_REMOVE_KEY = 0x0d, + HIF_CNF_ID_EDCA_QUEUE_PARAMS = 0x13, + HIF_CNF_ID_START = 0x17, + HIF_CNF_ID_BEACON_TRANSMIT = 0x18, + HIF_CNF_ID_UPDATE_IE = 0x1b, + HIF_CNF_ID_MAP_LINK = 0x1c, }; enum hif_indications_ids { - HIF_IND_ID_RX = 0x84, - HIF_IND_ID_SCAN_CMPL = 0x86, - HIF_IND_ID_JOIN_COMPLETE = 0x8f, - HIF_IND_ID_SET_PM_MODE_CMPL = 0x89, - HIF_IND_ID_SUSPEND_RESUME_TX = 0x8c, - HIF_IND_ID_EVENT = 0x85 + HIF_IND_ID_RX = 0x84, + HIF_IND_ID_SCAN_CMPL = 0x86, + HIF_IND_ID_JOIN_COMPLETE = 0x8f, + HIF_IND_ID_SET_PM_MODE_CMPL = 0x89, + HIF_IND_ID_SUSPEND_RESUME_TX = 0x8c, + HIF_IND_ID_EVENT = 0x85 }; union hif_commands_ids { @@ -68,27 +66,11 @@ union hif_commands_ids { enum hif_indications_ids indication; }; -enum hif_status { - HIF_STATUS_SUCCESS = 0x0, - HIF_STATUS_FAILURE = 0x1, - HIF_INVALID_PARAMETER = 0x2, - HIF_STATUS_WARNING = 0x3, - HIF_ERROR_UNSUPPORTED_MSG_ID = 0x4, - HIF_STATUS_DECRYPTFAILURE = 0x10, - HIF_STATUS_MICFAILURE = 0x11, - HIF_STATUS_NO_KEY_FOUND = 0x12, - HIF_STATUS_RETRY_EXCEEDED = 0x13, - HIF_STATUS_TX_LIFETIME_EXCEEDED = 0x14, - HIF_REQUEUE = 0x15, - HIF_STATUS_REFUSED = 0x16, - HIF_STATUS_BUSY = 0x17 -}; - struct hif_reset_flags { - u8 reset_stat:1; - u8 reset_all_int:1; - u8 reserved1:6; - u8 reserved2[3]; + u8 reset_stat:1; + u8 reset_all_int:1; + u8 reserved1:6; + u8 reserved2[3]; } __packed; struct hif_req_reset { @@ -96,117 +78,101 @@ struct hif_req_reset { } __packed; struct hif_req_read_mib { - u16 mib_id; - u16 reserved; + __le16 mib_id; + __le16 reserved; } __packed; struct hif_cnf_read_mib { - u32 status; - u16 mib_id; - u16 length; - u8 mib_data[]; + __le32 status; + __le16 mib_id; + __le16 length; + u8 mib_data[]; } __packed; struct hif_req_write_mib { - u16 mib_id; - u16 length; - u8 mib_data[]; + __le16 mib_id; + __le16 length; + u8 mib_data[]; } __packed; struct hif_cnf_write_mib { - u32 status; + __le32 status; } __packed; struct hif_ie_flags { - u8 beacon:1; - u8 probe_resp:1; - u8 probe_req:1; - u8 reserved1:5; - u8 reserved2; + u8 beacon:1; + u8 probe_resp:1; + u8 probe_req:1; + u8 reserved1:5; + u8 reserved2; } __packed; struct hif_ie_tlv { - u8 type; - u8 length; - u8 data[]; + u8 type; + u8 length; + u8 data[]; } __packed; struct hif_req_update_ie { struct hif_ie_flags ie_flags; - u16 num_ies; + __le16 num_ies; struct hif_ie_tlv ie[]; } __packed; struct hif_cnf_update_ie { - u32 status; + __le32 status; } __packed; struct hif_scan_type { - u8 type:1; - u8 mode:1; - u8 reserved:6; + u8 type:1; + u8 mode:1; + u8 reserved:6; } __packed; struct hif_scan_flags { - u8 fbg:1; - u8 reserved1:1; - u8 pre:1; - u8 reserved2:5; + u8 fbg:1; + u8 reserved1:1; + u8 pre:1; + u8 reserved2:5; } __packed; struct hif_auto_scan_param { - u16 interval; - u8 reserved; + __le16 interval; + u8 reserved; s8 rssi_thr; } __packed; struct hif_ssid_def { - u32 ssid_length; - u8 ssid[HIF_API_SSID_SIZE]; + __le32 ssid_length; + u8 ssid[HIF_API_SSID_SIZE]; } __packed; #define HIF_API_MAX_NB_SSIDS 2 #define HIF_API_MAX_NB_CHANNELS 14 -struct hif_req_start_scan { - u8 band; - struct hif_scan_type scan_type; - struct hif_scan_flags scan_flags; - u8 max_transmit_rate; - struct hif_auto_scan_param auto_scan_param; - u8 num_of_probe_requests; - u8 probe_delay; - u8 num_of_ssids; - u8 num_of_channels; - u32 min_channel_time; - u32 max_channel_time; - s32 tx_power_level; - u8 ssid_and_channel_lists[]; -} __packed; - struct hif_req_start_scan_alt { - u8 band; + u8 band; struct hif_scan_type scan_type; struct hif_scan_flags scan_flags; - u8 max_transmit_rate; + u8 max_transmit_rate; struct hif_auto_scan_param auto_scan_param; - u8 num_of_probe_requests; - u8 probe_delay; - u8 num_of_ssids; - u8 num_of_channels; - u32 min_channel_time; - u32 max_channel_time; - s32 tx_power_level; + u8 num_of_probe_requests; + u8 probe_delay; + u8 num_of_ssids; + u8 num_of_channels; + __le32 min_channel_time; + __le32 max_channel_time; + __le32 tx_power_level; // signed value struct hif_ssid_def ssid_def[HIF_API_MAX_NB_SSIDS]; - u8 channel_list[]; + u8 channel_list[]; } __packed; struct hif_cnf_start_scan { - u32 status; + __le32 status; } __packed; struct hif_cnf_stop_scan { - u32 status; + __le32 status; } __packed; enum hif_pm_mode_status { @@ -216,10 +182,10 @@ enum hif_pm_mode_status { }; struct hif_ind_scan_cmpl { - u32 status; - u8 pm_mode; - u8 num_channels_completed; - u16 reserved; + __le32 status; + u8 pm_mode; + u8 num_channels_completed; + __le16 reserved; } __packed; enum hif_queue_id { @@ -241,46 +207,48 @@ enum hif_stbc { }; struct hif_queue { - u8 queue_id:2; - u8 peer_sta_id:4; - u8 reserved:2; + u8 queue_id:2; + u8 peer_sta_id:4; + u8 reserved:2; } __packed; struct hif_data_flags { - u8 more:1; - u8 fc_offset:3; - u8 after_dtim:1; - u8 reserved:3; + u8 more:1; + u8 fc_offset:3; + u8 after_dtim:1; + u8 reserved:3; } __packed; struct hif_tx_flags { - u8 start_exp:1; - u8 reserved:3; - u8 retry_policy_index:4; + u8 start_exp:1; + u8 reserved:3; + u8 retry_policy_index:4; } __packed; struct hif_ht_tx_parameters { - u8 frame_format:4; - u8 fec_coding:1; - u8 short_gi:1; - u8 reserved1:1; - u8 stbc:1; - u8 reserved2; - u8 aggregation:1; - u8 reserved3:7; - u8 reserved4; + u8 frame_format:4; + u8 fec_coding:1; + u8 short_gi:1; + u8 reserved1:1; + u8 stbc:1; + u8 reserved2; + u8 aggregation:1; + u8 reserved3:7; + u8 reserved4; } __packed; struct hif_req_tx { - u32 packet_id; - u8 max_tx_rate; + // packet_id is not interpreted by the device, so it is not necessary to + // declare it little endian + u32 packet_id; + u8 max_tx_rate; struct hif_queue queue_id; struct hif_data_flags data_flags; struct hif_tx_flags tx_flags; - u32 reserved; - u32 expire_time; + __le32 reserved; + __le32 expire_time; struct hif_ht_tx_parameters ht_tx_parameters; - u8 frame[]; + u8 frame[]; } __packed; enum hif_qos_ackplcy { @@ -291,26 +259,29 @@ enum hif_qos_ackplcy { }; struct hif_tx_result_flags { - u8 aggr:1; - u8 requeue:1; - u8 ack_policy:2; - u8 txop_limit:1; - u8 reserved1:3; - u8 reserved2; + u8 aggr:1; + u8 requeue:1; + u8 ack_policy:2; + u8 txop_limit:1; + u8 reserved1:3; + u8 reserved2; } __packed; struct hif_cnf_tx { - u32 status; - u32 packet_id; - u8 txed_rate; - u8 ack_failures; + __le32 status; + // packet_id is copied from struct hif_req_tx without been interpreted + // by the device, so it is not necessary to declare it little endian + u32 packet_id; + u8 txed_rate; + u8 ack_failures; struct hif_tx_result_flags tx_result_flags; - u32 media_delay; - u32 tx_queue_delay; + __le32 media_delay; + __le32 tx_queue_delay; } __packed; struct hif_cnf_multi_transmit { - u32 num_tx_confs; + u8 num_tx_confs; + u8 reserved[3]; struct hif_cnf_tx tx_conf_payload[]; } __packed; @@ -323,147 +294,150 @@ enum hif_ri_flags_encrypt { }; struct hif_rx_flags { - u8 encryp:3; - u8 in_aggr:1; - u8 first_aggr:1; - u8 last_aggr:1; - u8 defrag:1; - u8 beacon:1; - u8 tim:1; - u8 bitmap:1; - u8 match_ssid:1; - u8 match_bssid:1; - u8 more:1; - u8 reserved1:1; - u8 ht:1; - u8 stbc:1; - u8 match_uc_addr:1; - u8 match_mc_addr:1; - u8 match_bc_addr:1; - u8 key_type:1; - u8 key_index:4; - u8 reserved2:1; - u8 peer_sta_id:4; - u8 reserved3:2; - u8 reserved4:1; + u8 encryp:3; + u8 in_aggr:1; + u8 first_aggr:1; + u8 last_aggr:1; + u8 defrag:1; + u8 beacon:1; + u8 tim:1; + u8 bitmap:1; + u8 match_ssid:1; + u8 match_bssid:1; + u8 more:1; + u8 reserved1:1; + u8 ht:1; + u8 stbc:1; + u8 match_uc_addr:1; + u8 match_mc_addr:1; + u8 match_bc_addr:1; + u8 key_type:1; + u8 key_index:4; + u8 reserved2:1; + u8 peer_sta_id:4; + u8 reserved3:2; + u8 reserved4:1; } __packed; struct hif_ind_rx { - u32 status; - u16 channel_number; - u8 rxed_rate; - u8 rcpi_rssi; + __le32 status; + u8 channel_number; + u8 reserved; + u8 rxed_rate; + u8 rcpi_rssi; struct hif_rx_flags rx_flags; - u8 frame[]; + u8 frame[]; } __packed; struct hif_req_edca_queue_params { - u8 queue_id; - u8 reserved1; - u8 aifsn; - u8 reserved2; - u16 cw_min; - u16 cw_max; - u16 tx_op_limit; - u16 allowed_medium_time; - u32 reserved3; + u8 queue_id; + u8 reserved1; + u8 aifsn; + u8 reserved2; + __le16 cw_min; + __le16 cw_max; + __le16 tx_op_limit; + __le16 allowed_medium_time; + __le32 reserved3; } __packed; struct hif_cnf_edca_queue_params { - u32 status; + __le32 status; } __packed; struct hif_join_flags { - u8 reserved1:2; - u8 force_no_beacon:1; - u8 force_with_ind:1; - u8 reserved2:4; + u8 reserved1:2; + u8 force_no_beacon:1; + u8 force_with_ind:1; + u8 reserved2:4; } __packed; struct hif_req_join { - u8 infrastructure_bss_mode:1; - u8 reserved1:7; - u8 band; - u16 channel_number; - u8 bssid[ETH_ALEN]; - u16 atim_window; - u8 short_preamble:1; - u8 reserved2:7; - u8 probe_for_join; - u8 reserved3; + u8 infrastructure_bss_mode:1; + u8 reserved1:7; + u8 band; + u8 channel_number; + u8 reserved; + u8 bssid[ETH_ALEN]; + __le16 atim_window; + u8 short_preamble:1; + u8 reserved2:7; + u8 probe_for_join; + u8 reserved3; struct hif_join_flags join_flags; - u32 ssid_length; - u8 ssid[HIF_API_SSID_SIZE]; - u32 beacon_interval; - u32 basic_rate_set; + __le32 ssid_length; + u8 ssid[HIF_API_SSID_SIZE]; + __le32 beacon_interval; + __le32 basic_rate_set; } __packed; struct hif_cnf_join { - u32 status; + __le32 status; } __packed; struct hif_ind_join_complete { - u32 status; + __le32 status; } __packed; struct hif_bss_flags { - u8 lost_count_only:1; - u8 reserved:7; + u8 lost_count_only:1; + u8 reserved:7; } __packed; struct hif_req_set_bss_params { struct hif_bss_flags bss_flags; - u8 beacon_lost_count; - u16 aid; - u32 operational_rate_set; + u8 beacon_lost_count; + __le16 aid; + __le32 operational_rate_set; } __packed; struct hif_cnf_set_bss_params { - u32 status; + __le32 status; } __packed; struct hif_pm_mode { - u8 enter_psm:1; - u8 reserved:6; - u8 fast_psm:1; + u8 enter_psm:1; + u8 reserved:6; + u8 fast_psm:1; } __packed; struct hif_req_set_pm_mode { struct hif_pm_mode pm_mode; - u8 fast_psm_idle_period; - u8 ap_psm_change_period; - u8 min_auto_ps_poll_period; + u8 fast_psm_idle_period; + u8 ap_psm_change_period; + u8 min_auto_ps_poll_period; } __packed; struct hif_cnf_set_pm_mode { - u32 status; + __le32 status; } __packed; struct hif_ind_set_pm_mode_cmpl { - u32 status; - u8 pm_mode; - u8 reserved[3]; + __le32 status; + u8 pm_mode; + u8 reserved[3]; } __packed; struct hif_req_start { - u8 mode; - u8 band; - u16 channel_number; - u32 reserved1; - u32 beacon_interval; - u8 dtim_period; - u8 short_preamble:1; - u8 reserved2:7; - u8 reserved3; - u8 ssid_length; - u8 ssid[HIF_API_SSID_SIZE]; - u32 basic_rate_set; + u8 mode; + u8 band; + u8 channel_number; + u8 reserved1; + __le32 reserved2; + __le32 beacon_interval; + u8 dtim_period; + u8 short_preamble:1; + u8 reserved3:7; + u8 reserved4; + u8 ssid_length; + u8 ssid[HIF_API_SSID_SIZE]; + __le32 basic_rate_set; } __packed; struct hif_cnf_start { - u32 status; + __le32 status; } __packed; enum hif_beacon { @@ -472,46 +446,49 @@ enum hif_beacon { }; struct hif_req_beacon_transmit { - u8 enable_beaconing; - u8 reserved[3]; + u8 enable_beaconing; + u8 reserved[3]; } __packed; struct hif_cnf_beacon_transmit { - u32 status; + __le32 status; } __packed; +#define HIF_LINK_ID_MAX 14 +#define HIF_LINK_ID_NOT_ASSOCIATED (HIF_LINK_ID_MAX + 1) + enum hif_sta_map_direction { HIF_STA_MAP = 0x0, HIF_STA_UNMAP = 0x1 }; struct hif_map_link_flags { - u8 map_direction:1; - u8 mfpc:1; - u8 reserved:6; + u8 map_direction:1; + u8 mfpc:1; + u8 reserved:6; } __packed; struct hif_req_map_link { - u8 mac_addr[ETH_ALEN]; + u8 mac_addr[ETH_ALEN]; struct hif_map_link_flags map_link_flags; - u8 peer_sta_id; + u8 peer_sta_id; } __packed; struct hif_cnf_map_link { - u32 status; + __le32 status; } __packed; struct hif_suspend_resume_flags { - u8 resume:1; - u8 reserved1:2; - u8 bc_mc_only:1; - u8 reserved2:4; - u8 reserved3; + u8 resume:1; + u8 reserved1:2; + u8 bc_mc_only:1; + u8 reserved2:4; + u8 reserved3; } __packed; struct hif_ind_suspend_resume_tx { struct hif_suspend_resume_flags suspend_resume_flags; - u16 peer_sta_set; + __le16 peer_sta_set; } __packed; @@ -541,102 +518,102 @@ enum hif_key_type { }; struct hif_wep_pairwise_key { - u8 peer_address[ETH_ALEN]; - u8 reserved; - u8 key_length; - u8 key_data[HIF_API_WEP_KEY_DATA_SIZE]; + u8 peer_address[ETH_ALEN]; + u8 reserved; + u8 key_length; + u8 key_data[HIF_API_WEP_KEY_DATA_SIZE]; } __packed; struct hif_wep_group_key { - u8 key_id; - u8 key_length; - u8 reserved[2]; - u8 key_data[HIF_API_WEP_KEY_DATA_SIZE]; + u8 key_id; + u8 key_length; + u8 reserved[2]; + u8 key_data[HIF_API_WEP_KEY_DATA_SIZE]; } __packed; struct hif_tkip_pairwise_key { - u8 peer_address[ETH_ALEN]; - u8 reserved[2]; - u8 tkip_key_data[HIF_API_TKIP_KEY_DATA_SIZE]; - u8 rx_mic_key[HIF_API_RX_MIC_KEY_SIZE]; - u8 tx_mic_key[HIF_API_TX_MIC_KEY_SIZE]; + u8 peer_address[ETH_ALEN]; + u8 reserved[2]; + u8 tkip_key_data[HIF_API_TKIP_KEY_DATA_SIZE]; + u8 rx_mic_key[HIF_API_RX_MIC_KEY_SIZE]; + u8 tx_mic_key[HIF_API_TX_MIC_KEY_SIZE]; } __packed; struct hif_tkip_group_key { - u8 tkip_key_data[HIF_API_TKIP_KEY_DATA_SIZE]; - u8 rx_mic_key[HIF_API_RX_MIC_KEY_SIZE]; - u8 key_id; - u8 reserved[3]; - u8 rx_sequence_counter[HIF_API_RX_SEQUENCE_COUNTER_SIZE]; + u8 tkip_key_data[HIF_API_TKIP_KEY_DATA_SIZE]; + u8 rx_mic_key[HIF_API_RX_MIC_KEY_SIZE]; + u8 key_id; + u8 reserved[3]; + u8 rx_sequence_counter[HIF_API_RX_SEQUENCE_COUNTER_SIZE]; } __packed; struct hif_aes_pairwise_key { - u8 peer_address[ETH_ALEN]; - u8 reserved[2]; - u8 aes_key_data[HIF_API_AES_KEY_DATA_SIZE]; + u8 peer_address[ETH_ALEN]; + u8 reserved[2]; + u8 aes_key_data[HIF_API_AES_KEY_DATA_SIZE]; } __packed; struct hif_aes_group_key { - u8 aes_key_data[HIF_API_AES_KEY_DATA_SIZE]; - u8 key_id; - u8 reserved[3]; - u8 rx_sequence_counter[HIF_API_RX_SEQUENCE_COUNTER_SIZE]; + u8 aes_key_data[HIF_API_AES_KEY_DATA_SIZE]; + u8 key_id; + u8 reserved[3]; + u8 rx_sequence_counter[HIF_API_RX_SEQUENCE_COUNTER_SIZE]; } __packed; struct hif_wapi_pairwise_key { - u8 peer_address[ETH_ALEN]; - u8 key_id; - u8 reserved; - u8 wapi_key_data[HIF_API_WAPI_KEY_DATA_SIZE]; - u8 mic_key_data[HIF_API_MIC_KEY_DATA_SIZE]; + u8 peer_address[ETH_ALEN]; + u8 key_id; + u8 reserved; + u8 wapi_key_data[HIF_API_WAPI_KEY_DATA_SIZE]; + u8 mic_key_data[HIF_API_MIC_KEY_DATA_SIZE]; } __packed; struct hif_wapi_group_key { - u8 wapi_key_data[HIF_API_WAPI_KEY_DATA_SIZE]; - u8 mic_key_data[HIF_API_MIC_KEY_DATA_SIZE]; - u8 key_id; - u8 reserved[3]; + u8 wapi_key_data[HIF_API_WAPI_KEY_DATA_SIZE]; + u8 mic_key_data[HIF_API_MIC_KEY_DATA_SIZE]; + u8 key_id; + u8 reserved[3]; } __packed; struct hif_igtk_group_key { - u8 igtk_key_data[HIF_API_IGTK_KEY_DATA_SIZE]; - u8 key_id; - u8 reserved[3]; - u8 ipn[HIF_API_IPN_SIZE]; + u8 igtk_key_data[HIF_API_IGTK_KEY_DATA_SIZE]; + u8 key_id; + u8 reserved[3]; + u8 ipn[HIF_API_IPN_SIZE]; } __packed; union hif_privacy_key_data { - struct hif_wep_pairwise_key wep_pairwise_key; - struct hif_wep_group_key wep_group_key; - struct hif_tkip_pairwise_key tkip_pairwise_key; - struct hif_tkip_group_key tkip_group_key; - struct hif_aes_pairwise_key aes_pairwise_key; - struct hif_aes_group_key aes_group_key; - struct hif_wapi_pairwise_key wapi_pairwise_key; - struct hif_wapi_group_key wapi_group_key; - struct hif_igtk_group_key igtk_group_key; + struct hif_wep_pairwise_key wep_pairwise_key; + struct hif_wep_group_key wep_group_key; + struct hif_tkip_pairwise_key tkip_pairwise_key; + struct hif_tkip_group_key tkip_group_key; + struct hif_aes_pairwise_key aes_pairwise_key; + struct hif_aes_group_key aes_group_key; + struct hif_wapi_pairwise_key wapi_pairwise_key; + struct hif_wapi_group_key wapi_group_key; + struct hif_igtk_group_key igtk_group_key; }; struct hif_req_add_key { - u8 type; - u8 entry_index; - u8 int_id:2; - u8 reserved1:6; - u8 reserved2; + u8 type; + u8 entry_index; + u8 int_id:2; + u8 reserved1:6; + u8 reserved2; union hif_privacy_key_data key; } __packed; struct hif_cnf_add_key { - u32 status; + __le32 status; } __packed; struct hif_req_remove_key { - u8 entry_index; - u8 reserved[3]; + u8 entry_index; + u8 reserved[3]; } __packed; struct hif_cnf_remove_key { - u32 status; + __le32 status; } __packed; enum hif_event_ind { @@ -656,13 +633,13 @@ enum hif_ps_mode_error { }; union hif_event_data { - u8 rcpi_rssi; - u32 ps_mode_error; - u32 peer_sta_set; + u8 rcpi_rssi; + __le32 ps_mode_error; + __le32 peer_sta_set; }; struct hif_ind_event { - u32 event_id; + __le32 event_id; union hif_event_data event_data; } __packed; diff --git a/drivers/staging/wfx/hif_api_general.h b/drivers/staging/wfx/hif_api_general.h index a069c3a21b4d..dba18a7ae919 100644 --- a/drivers/staging/wfx/hif_api_general.h +++ b/drivers/staging/wfx/hif_api_general.h @@ -17,13 +17,13 @@ #define __packed __attribute__((__packed__)) #endif -#define API_SSID_SIZE 32 +#define API_SSID_SIZE 32 -#define HIF_ID_IS_INDICATION 0x80 -#define HIF_COUNTER_MAX 7 +#define HIF_ID_IS_INDICATION 0x80 +#define HIF_COUNTER_MAX 7 struct hif_msg { - u16 len; + __le16 len; u8 id; u8 reserved:1; u8 interface:2; @@ -33,239 +33,252 @@ struct hif_msg { } __packed; enum hif_general_requests_ids { - HIF_REQ_ID_CONFIGURATION = 0x09, - HIF_REQ_ID_CONTROL_GPIO = 0x26, - HIF_REQ_ID_SET_SL_MAC_KEY = 0x27, - HIF_REQ_ID_SL_EXCHANGE_PUB_KEYS = 0x28, - HIF_REQ_ID_SL_CONFIGURE = 0x29, - HIF_REQ_ID_PREVENT_ROLLBACK = 0x2a, - HIF_REQ_ID_PTA_SETTINGS = 0x2b, - HIF_REQ_ID_PTA_PRIORITY = 0x2c, - HIF_REQ_ID_PTA_STATE = 0x2d, - HIF_REQ_ID_SHUT_DOWN = 0x32, + HIF_REQ_ID_CONFIGURATION = 0x09, + HIF_REQ_ID_CONTROL_GPIO = 0x26, + HIF_REQ_ID_SET_SL_MAC_KEY = 0x27, + HIF_REQ_ID_SL_EXCHANGE_PUB_KEYS = 0x28, + HIF_REQ_ID_SL_CONFIGURE = 0x29, + HIF_REQ_ID_PREVENT_ROLLBACK = 0x2a, + HIF_REQ_ID_PTA_SETTINGS = 0x2b, + HIF_REQ_ID_PTA_PRIORITY = 0x2c, + HIF_REQ_ID_PTA_STATE = 0x2d, + HIF_REQ_ID_SHUT_DOWN = 0x32, }; enum hif_general_confirmations_ids { - HIF_CNF_ID_CONFIGURATION = 0x09, - HIF_CNF_ID_CONTROL_GPIO = 0x26, - HIF_CNF_ID_SET_SL_MAC_KEY = 0x27, - HIF_CNF_ID_SL_EXCHANGE_PUB_KEYS = 0x28, - HIF_CNF_ID_SL_CONFIGURE = 0x29, - HIF_CNF_ID_PREVENT_ROLLBACK = 0x2a, - HIF_CNF_ID_PTA_SETTINGS = 0x2b, - HIF_CNF_ID_PTA_PRIORITY = 0x2c, - HIF_CNF_ID_PTA_STATE = 0x2d, - HIF_CNF_ID_SHUT_DOWN = 0x32, + HIF_CNF_ID_CONFIGURATION = 0x09, + HIF_CNF_ID_CONTROL_GPIO = 0x26, + HIF_CNF_ID_SET_SL_MAC_KEY = 0x27, + HIF_CNF_ID_SL_EXCHANGE_PUB_KEYS = 0x28, + HIF_CNF_ID_SL_CONFIGURE = 0x29, + HIF_CNF_ID_PREVENT_ROLLBACK = 0x2a, + HIF_CNF_ID_PTA_SETTINGS = 0x2b, + HIF_CNF_ID_PTA_PRIORITY = 0x2c, + HIF_CNF_ID_PTA_STATE = 0x2d, + HIF_CNF_ID_SHUT_DOWN = 0x32, }; enum hif_general_indications_ids { - HIF_IND_ID_EXCEPTION = 0xe0, - HIF_IND_ID_STARTUP = 0xe1, - HIF_IND_ID_WAKEUP = 0xe2, - HIF_IND_ID_GENERIC = 0xe3, - HIF_IND_ID_ERROR = 0xe4, - HIF_IND_ID_SL_EXCHANGE_PUB_KEYS = 0xe5 + HIF_IND_ID_EXCEPTION = 0xe0, + HIF_IND_ID_STARTUP = 0xe1, + HIF_IND_ID_WAKEUP = 0xe2, + HIF_IND_ID_GENERIC = 0xe3, + HIF_IND_ID_ERROR = 0xe4, + HIF_IND_ID_SL_EXCHANGE_PUB_KEYS = 0xe5 }; -enum hif_hi_status { - HI_STATUS_SUCCESS = 0x0000, - HI_STATUS_FAILURE = 0x0001, - HI_INVALID_PARAMETER = 0x0002, - HI_STATUS_GPIO_WARNING = 0x0003, - HI_ERROR_UNSUPPORTED_MSG_ID = 0x0004, - SL_MAC_KEY_STATUS_SUCCESS = 0x005A, - SL_MAC_KEY_STATUS_FAILED_KEY_ALREADY_BURNED = 0x006B, - SL_MAC_KEY_STATUS_FAILED_RAM_MODE_NOT_ALLOWED = 0x007C, - SL_MAC_KEY_STATUS_FAILED_UNKNOWN_MODE = 0x008D, - SL_PUB_KEY_EXCHANGE_STATUS_SUCCESS = 0x009E, - SL_PUB_KEY_EXCHANGE_STATUS_FAILED = 0x00AF, - PREVENT_ROLLBACK_CNF_SUCCESS = 0x1234, - PREVENT_ROLLBACK_CNF_WRONG_MAGIC_WORD = 0x1256 -}; +#define HIF_STATUS_SUCCESS (cpu_to_le32(0x0000)) +#define HIF_STATUS_FAIL (cpu_to_le32(0x0001)) +#define HIF_STATUS_INVALID_PARAMETER (cpu_to_le32(0x0002)) +#define HIF_STATUS_WARNING (cpu_to_le32(0x0003)) +#define HIF_STATUS_UNKNOWN_REQUEST (cpu_to_le32(0x0004)) +#define HIF_STATUS_RX_FAIL_DECRYPT (cpu_to_le32(0x0010)) +#define HIF_STATUS_RX_FAIL_MIC (cpu_to_le32(0x0011)) +#define HIF_STATUS_RX_FAIL_NO_KEY (cpu_to_le32(0x0012)) +#define HIF_STATUS_TX_FAIL_RETRIES (cpu_to_le32(0x0013)) +#define HIF_STATUS_TX_FAIL_TIMEOUT (cpu_to_le32(0x0014)) +#define HIF_STATUS_TX_FAIL_REQUEUE (cpu_to_le32(0x0015)) +#define HIF_STATUS_REFUSED (cpu_to_le32(0x0016)) +#define HIF_STATUS_BUSY (cpu_to_le32(0x0017)) +#define HIF_STATUS_SLK_SET_KEY_SUCCESS (cpu_to_le32(0x005A)) +#define HIF_STATUS_SLK_SET_KEY_ALREADY_BURNED (cpu_to_le32(0x006B)) +#define HIF_STATUS_SLK_SET_KEY_DISALLOWED_MODE (cpu_to_le32(0x007C)) +#define HIF_STATUS_SLK_SET_KEY_UNKNOWN_MODE (cpu_to_le32(0x008D)) +#define HIF_STATUS_SLK_NEGO_SUCCESS (cpu_to_le32(0x009E)) +#define HIF_STATUS_SLK_NEGO_FAILED (cpu_to_le32(0x00AF)) +#define HIF_STATUS_ROLLBACK_SUCCESS (cpu_to_le32(0x1234)) +#define HIF_STATUS_ROLLBACK_FAIL (cpu_to_le32(0x1256)) enum hif_api_rate_index { - API_RATE_INDEX_B_1MBPS = 0, - API_RATE_INDEX_B_2MBPS = 1, - API_RATE_INDEX_B_5P5MBPS = 2, - API_RATE_INDEX_B_11MBPS = 3, - API_RATE_INDEX_PBCC_22MBPS = 4, - API_RATE_INDEX_PBCC_33MBPS = 5, - API_RATE_INDEX_G_6MBPS = 6, - API_RATE_INDEX_G_9MBPS = 7, - API_RATE_INDEX_G_12MBPS = 8, - API_RATE_INDEX_G_18MBPS = 9, - API_RATE_INDEX_G_24MBPS = 10, - API_RATE_INDEX_G_36MBPS = 11, - API_RATE_INDEX_G_48MBPS = 12, - API_RATE_INDEX_G_54MBPS = 13, - API_RATE_INDEX_N_6P5MBPS = 14, - API_RATE_INDEX_N_13MBPS = 15, - API_RATE_INDEX_N_19P5MBPS = 16, - API_RATE_INDEX_N_26MBPS = 17, - API_RATE_INDEX_N_39MBPS = 18, - API_RATE_INDEX_N_52MBPS = 19, - API_RATE_INDEX_N_58P5MBPS = 20, - API_RATE_INDEX_N_65MBPS = 21, - API_RATE_NUM_ENTRIES = 22 + API_RATE_INDEX_B_1MBPS = 0, + API_RATE_INDEX_B_2MBPS = 1, + API_RATE_INDEX_B_5P5MBPS = 2, + API_RATE_INDEX_B_11MBPS = 3, + API_RATE_INDEX_PBCC_22MBPS = 4, + API_RATE_INDEX_PBCC_33MBPS = 5, + API_RATE_INDEX_G_6MBPS = 6, + API_RATE_INDEX_G_9MBPS = 7, + API_RATE_INDEX_G_12MBPS = 8, + API_RATE_INDEX_G_18MBPS = 9, + API_RATE_INDEX_G_24MBPS = 10, + API_RATE_INDEX_G_36MBPS = 11, + API_RATE_INDEX_G_48MBPS = 12, + API_RATE_INDEX_G_54MBPS = 13, + API_RATE_INDEX_N_6P5MBPS = 14, + API_RATE_INDEX_N_13MBPS = 15, + API_RATE_INDEX_N_19P5MBPS = 16, + API_RATE_INDEX_N_26MBPS = 17, + API_RATE_INDEX_N_39MBPS = 18, + API_RATE_INDEX_N_52MBPS = 19, + API_RATE_INDEX_N_58P5MBPS = 20, + API_RATE_INDEX_N_65MBPS = 21, + API_RATE_NUM_ENTRIES = 22 }; enum hif_fw_type { - HIF_FW_TYPE_ETF = 0x0, - HIF_FW_TYPE_WFM = 0x1, - HIF_FW_TYPE_WSM = 0x2 + HIF_FW_TYPE_ETF = 0x0, + HIF_FW_TYPE_WFM = 0x1, + HIF_FW_TYPE_WSM = 0x2 }; struct hif_capabilities { - u8 link_mode:2; - u8 reserved1:6; - u8 reserved2; - u8 reserved3; - u8 reserved4; + u8 link_mode:2; + u8 reserved1:6; + u8 reserved2; + u8 reserved3; + u8 reserved4; } __packed; struct hif_otp_regul_sel_mode_info { - u8 region_sel_mode:4; - u8 reserved:4; + u8 region_sel_mode:4; + u8 reserved:4; } __packed; struct hif_otp_phy_info { - u8 phy1_region:3; - u8 phy0_region:3; - u8 otp_phy_ver:2; + u8 phy1_region:3; + u8 phy0_region:3; + u8 otp_phy_ver:2; } __packed; -#define API_OPN_SIZE 14 -#define API_UID_SIZE 8 -#define API_DISABLED_CHANNEL_LIST_SIZE 2 -#define API_FIRMWARE_LABEL_SIZE 128 - struct hif_ind_startup { - u32 status; - u16 hardware_id; - u8 opn[API_OPN_SIZE]; - u8 uid[API_UID_SIZE]; - u16 num_inp_ch_bufs; - u16 size_inp_ch_buf; - u8 num_links_ap; - u8 num_interfaces; - u8 mac_addr[2][ETH_ALEN]; - u8 api_version_minor; - u8 api_version_major; + // As the others, this struct is interpreted as little endian by the + // device. However, this struct is also used by the driver. We prefer to + // declare it in native order and doing byte swap on reception. + __le32 status; + u16 hardware_id; + u8 opn[14]; + u8 uid[8]; + u16 num_inp_ch_bufs; + u16 size_inp_ch_buf; + u8 num_links_ap; + u8 num_interfaces; + u8 mac_addr[2][ETH_ALEN]; + u8 api_version_minor; + u8 api_version_major; struct hif_capabilities capabilities; - u8 firmware_build; - u8 firmware_minor; - u8 firmware_major; - u8 firmware_type; - u8 disabled_channel_list[API_DISABLED_CHANNEL_LIST_SIZE]; + u8 firmware_build; + u8 firmware_minor; + u8 firmware_major; + u8 firmware_type; + u8 disabled_channel_list[2]; struct hif_otp_regul_sel_mode_info regul_sel_mode_info; struct hif_otp_phy_info otp_phy_info; - u32 supported_rate_mask; - u8 firmware_label[API_FIRMWARE_LABEL_SIZE]; + u32 supported_rate_mask; + u8 firmware_label[128]; } __packed; struct hif_ind_wakeup { } __packed; struct hif_req_configuration { - u16 length; - u8 pds_data[]; + __le16 length; + u8 pds_data[]; } __packed; struct hif_cnf_configuration { - u32 status; + __le32 status; } __packed; enum hif_gpio_mode { - HIF_GPIO_MODE_D0 = 0x0, - HIF_GPIO_MODE_D1 = 0x1, - HIF_GPIO_MODE_OD0 = 0x2, - HIF_GPIO_MODE_OD1 = 0x3, - HIF_GPIO_MODE_TRISTATE = 0x4, - HIF_GPIO_MODE_TOGGLE = 0x5, - HIF_GPIO_MODE_READ = 0x6 + HIF_GPIO_MODE_D0 = 0x0, + HIF_GPIO_MODE_D1 = 0x1, + HIF_GPIO_MODE_OD0 = 0x2, + HIF_GPIO_MODE_OD1 = 0x3, + HIF_GPIO_MODE_TRISTATE = 0x4, + HIF_GPIO_MODE_TOGGLE = 0x5, + HIF_GPIO_MODE_READ = 0x6 }; struct hif_req_control_gpio { - u8 gpio_label; - u8 gpio_mode; + u8 gpio_label; + u8 gpio_mode; } __packed; -enum hif_gpio_error { - HIF_GPIO_ERROR_0 = 0x0, - HIF_GPIO_ERROR_1 = 0x1, - HIF_GPIO_ERROR_2 = 0x2 -}; - struct hif_cnf_control_gpio { - u32 status; - u32 value; + __le32 status; + __le32 value; } __packed; enum hif_generic_indication_type { - HIF_GENERIC_INDICATION_TYPE_RAW = 0x0, - HIF_GENERIC_INDICATION_TYPE_STRING = 0x1, - HIF_GENERIC_INDICATION_TYPE_RX_STATS = 0x2 + HIF_GENERIC_INDICATION_TYPE_RAW = 0x0, + HIF_GENERIC_INDICATION_TYPE_STRING = 0x1, + HIF_GENERIC_INDICATION_TYPE_RX_STATS = 0x2, + HIF_GENERIC_INDICATION_TYPE_TX_POWER_LOOP_INFO = 0x3, }; struct hif_rx_stats { - u32 nb_rx_frame; - u32 nb_crc_frame; - u32 per_total; - u32 throughput; - u32 nb_rx_by_rate[API_RATE_NUM_ENTRIES]; - u16 per[API_RATE_NUM_ENTRIES]; - s16 snr[API_RATE_NUM_ENTRIES]; - s16 rssi[API_RATE_NUM_ENTRIES]; - s16 cfo[API_RATE_NUM_ENTRIES]; - u32 date; - u32 pwr_clk_freq; - u8 is_ext_pwr_clk; + __le32 nb_rx_frame; + __le32 nb_crc_frame; + __le32 per_total; + __le32 throughput; + __le32 nb_rx_by_rate[API_RATE_NUM_ENTRIES]; + __le16 per[API_RATE_NUM_ENTRIES]; + __le16 snr[API_RATE_NUM_ENTRIES]; // signed value + __le16 rssi[API_RATE_NUM_ENTRIES]; // signed value + __le16 cfo[API_RATE_NUM_ENTRIES]; // signed value + __le32 date; + __le32 pwr_clk_freq; + u8 is_ext_pwr_clk; s8 current_temp; } __packed; +struct hif_tx_power_loop_info { + __le16 tx_gain_dig; + __le16 tx_gain_pa; + __le16 target_pout; // signed value + __le16 p_estimation; // signed value + __le16 vpdet; + u8 measurement_index; + u8 reserved; +} __packed; + union hif_indication_data { - struct hif_rx_stats rx_stats; - u8 raw_data[1]; + struct hif_rx_stats rx_stats; + struct hif_tx_power_loop_info tx_power_loop_info; + u8 raw_data[1]; }; struct hif_ind_generic { - u32 indication_type; + __le32 indication_type; union hif_indication_data indication_data; } __packed; - -#define HIF_EXCEPTION_DATA_SIZE 124 - -struct hif_ind_exception { - u8 data[HIF_EXCEPTION_DATA_SIZE]; -} __packed; - - enum hif_error { - HIF_ERROR_FIRMWARE_ROLLBACK = 0x0, - HIF_ERROR_FIRMWARE_DEBUG_ENABLED = 0x1, - HIF_ERROR_OUTDATED_SESSION_KEY = 0x2, - HIF_ERROR_INVALID_SESSION_KEY = 0x3, - HIF_ERROR_OOR_VOLTAGE = 0x4, - HIF_ERROR_PDS_VERSION = 0x5, - HIF_ERROR_OOR_TEMPERATURE = 0x6, - HIF_ERROR_REQ_DURING_KEY_EXCHANGE = 0x7, - HIF_ERROR_MULTI_TX_CNF_SECURELINK = 0x8, - HIF_ERROR_SECURELINK_OVERFLOW = 0x9, - HIF_ERROR_SECURELINK_DECRYPTION = 0xa + HIF_ERROR_FIRMWARE_ROLLBACK = 0x00, + HIF_ERROR_FIRMWARE_DEBUG_ENABLED = 0x01, + HIF_ERROR_SLK_OUTDATED_SESSION_KEY = 0x02, + HIF_ERROR_SLK_SESSION_KEY = 0x03, + HIF_ERROR_OOR_VOLTAGE = 0x04, + HIF_ERROR_PDS_PAYLOAD = 0x05, + HIF_ERROR_OOR_TEMPERATURE = 0x06, + HIF_ERROR_SLK_REQ_DURING_KEY_EXCHANGE = 0x07, + HIF_ERROR_SLK_MULTI_TX_UNSUPPORTED = 0x08, + HIF_ERROR_SLK_OVERFLOW = 0x09, + HIF_ERROR_SLK_DECRYPTION = 0x0a, + HIF_ERROR_SLK_WRONG_ENCRYPTION_STATE = 0x0b, + HIF_ERROR_HIF_BUS_FREQUENCY_TOO_LOW = 0x0c, + HIF_ERROR_HIF_RX_DATA_TOO_LARGE = 0x0e, + HIF_ERROR_HIF_TX_QUEUE_FULL = 0x0d, + HIF_ERROR_HIF_BUS = 0x0f, + HIF_ERROR_PDS_TESTFEATURE = 0x10, }; struct hif_ind_error { - u32 type; - u8 data[]; + __le32 type; + u8 data[]; +} __packed; + +struct hif_ind_exception { + __le32 type; + u8 data[]; } __packed; enum hif_secure_link_state { - SEC_LINK_UNAVAILABLE = 0x0, - SEC_LINK_RESERVED = 0x1, - SEC_LINK_EVAL = 0x2, - SEC_LINK_ENFORCED = 0x3 + SEC_LINK_UNAVAILABLE = 0x0, + SEC_LINK_RESERVED = 0x1, + SEC_LINK_EVAL = 0x2, + SEC_LINK_ENFORCED = 0x3 }; enum hif_sl_encryption_type { @@ -282,156 +295,70 @@ struct hif_sl_msg_hdr { struct hif_sl_msg { struct hif_sl_msg_hdr hdr; - u16 len; - u8 payload[]; + __le16 len; + u8 payload[]; } __packed; -#define AES_CCM_TAG_SIZE 16 +#define AES_CCM_TAG_SIZE 16 struct hif_sl_tag { - u8 tag[16]; + u8 tag[16]; } __packed; enum hif_sl_mac_key_dest { - SL_MAC_KEY_DEST_OTP = 0x78, - SL_MAC_KEY_DEST_RAM = 0x87 + SL_MAC_KEY_DEST_OTP = 0x78, + SL_MAC_KEY_DEST_RAM = 0x87 }; -#define API_KEY_VALUE_SIZE 32 +#define API_KEY_VALUE_SIZE 32 struct hif_req_set_sl_mac_key { - u8 otp_or_ram; - u8 key_value[API_KEY_VALUE_SIZE]; + u8 otp_or_ram; + u8 key_value[API_KEY_VALUE_SIZE]; } __packed; struct hif_cnf_set_sl_mac_key { - u32 status; + __le32 status; } __packed; -#define API_HOST_PUB_KEY_SIZE 32 -#define API_HOST_PUB_KEY_MAC_SIZE 64 - enum hif_sl_session_key_alg { - HIF_SL_CURVE25519 = 0x01, - HIF_SL_KDF = 0x02 + HIF_SL_CURVE25519 = 0x01, + HIF_SL_KDF = 0x02 }; +#define API_HOST_PUB_KEY_SIZE 32 +#define API_HOST_PUB_KEY_MAC_SIZE 64 + struct hif_req_sl_exchange_pub_keys { - u8 algorithm:2; - u8 reserved1:6; - u8 reserved2[3]; - u8 host_pub_key[API_HOST_PUB_KEY_SIZE]; - u8 host_pub_key_mac[API_HOST_PUB_KEY_MAC_SIZE]; + u8 algorithm:2; + u8 reserved1:6; + u8 reserved2[3]; + u8 host_pub_key[API_HOST_PUB_KEY_SIZE]; + u8 host_pub_key_mac[API_HOST_PUB_KEY_MAC_SIZE]; } __packed; struct hif_cnf_sl_exchange_pub_keys { - u32 status; + __le32 status; } __packed; -#define API_NCP_PUB_KEY_SIZE 32 -#define API_NCP_PUB_KEY_MAC_SIZE 64 +#define API_NCP_PUB_KEY_SIZE 32 +#define API_NCP_PUB_KEY_MAC_SIZE 64 struct hif_ind_sl_exchange_pub_keys { - u32 status; - u8 ncp_pub_key[API_NCP_PUB_KEY_SIZE]; - u8 ncp_pub_key_mac[API_NCP_PUB_KEY_MAC_SIZE]; + __le32 status; + u8 ncp_pub_key[API_NCP_PUB_KEY_SIZE]; + u8 ncp_pub_key_mac[API_NCP_PUB_KEY_MAC_SIZE]; } __packed; -#define API_ENCR_BMP_SIZE 32 - struct hif_req_sl_configure { - u8 encr_bmp[API_ENCR_BMP_SIZE]; - u8 disable_session_key_protection:1; - u8 reserved1:7; - u8 reserved2[3]; + u8 encr_bmp[32]; + u8 disable_session_key_protection:1; + u8 reserved1:7; + u8 reserved2[3]; } __packed; struct hif_cnf_sl_configure { - u32 status; -} __packed; - -struct hif_req_prevent_rollback { - u32 magic_word; -} __packed; - -struct hif_cnf_prevent_rollback { - u32 status; -} __packed; - -enum hif_pta_mode { - PTA_1W_WLAN_MASTER = 0, - PTA_1W_COEX_MASTER = 1, - PTA_2W = 2, - PTA_3W = 3, - PTA_4W = 4 -}; - -enum hif_signal_level { - SIGNAL_LOW = 0, - SIGNAL_HIGH = 1 -}; - -enum hif_coex_type { - COEX_TYPE_GENERIC = 0, - COEX_TYPE_BLE = 1 -}; - -enum hif_grant_state { - NO_GRANT = 0, - GRANT = 1 -}; - -struct hif_req_pta_settings { - u8 pta_mode; - u8 request_signal_active_level; - u8 priority_signal_active_level; - u8 freq_signal_active_level; - u8 grant_signal_active_level; - u8 coex_type; - u8 default_grant_state; - u8 simultaneous_rx_accesses; - u8 priority_sampling_time; - u8 tx_rx_sampling_time; - u8 freq_sampling_time; - u8 grant_valid_time; - u8 fem_control_time; - u8 first_slot_time; - u16 periodic_tx_rx_sampling_time; - u16 coex_quota; - u16 wlan_quota; -} __packed; - -struct hif_cnf_pta_settings { - u32 status; -} __packed; - -enum hif_pta_priority { - HIF_PTA_PRIORITY_COEX_MAXIMIZED = 0x00000562, - HIF_PTA_PRIORITY_COEX_HIGH = 0x00000462, - HIF_PTA_PRIORITY_BALANCED = 0x00001461, - HIF_PTA_PRIORITY_WLAN_HIGH = 0x00001851, - HIF_PTA_PRIORITY_WLAN_MAXIMIZED = 0x00001A51 -}; - -struct hif_req_pta_priority { - u32 priority; -} __packed; - -struct hif_cnf_pta_priority { - u32 status; -} __packed; - -enum hif_pta_state { - PTA_OFF = 0, - PTA_ON = 1 -}; - -struct hif_req_pta_state { - u32 pta_state; -} __packed; - -struct hif_cnf_pta_state { - u32 status; + __le32 status; } __packed; #endif diff --git a/drivers/staging/wfx/hif_api_mib.h b/drivers/staging/wfx/hif_api_mib.h index 0c67cd4c1593..6f1434795fa8 100644 --- a/drivers/staging/wfx/hif_api_mib.h +++ b/drivers/staging/wfx/hif_api_mib.h @@ -10,175 +10,88 @@ #include "hif_api_general.h" -#define HIF_API_IPV4_ADDRESS_SIZE 4 -#define HIF_API_IPV6_ADDRESS_SIZE 16 +#define HIF_API_IPV4_ADDRESS_SIZE 4 +#define HIF_API_IPV6_ADDRESS_SIZE 16 enum hif_mib_ids { - HIF_MIB_ID_GL_OPERATIONAL_POWER_MODE = 0x2000, - HIF_MIB_ID_GL_BLOCK_ACK_INFO = 0x2001, - HIF_MIB_ID_GL_SET_MULTI_MSG = 0x2002, - HIF_MIB_ID_CCA_CONFIG = 0x2003, - HIF_MIB_ID_ETHERTYPE_DATAFRAME_CONDITION = 0x2010, - HIF_MIB_ID_PORT_DATAFRAME_CONDITION = 0x2011, - HIF_MIB_ID_MAGIC_DATAFRAME_CONDITION = 0x2012, - HIF_MIB_ID_MAC_ADDR_DATAFRAME_CONDITION = 0x2013, - HIF_MIB_ID_IPV4_ADDR_DATAFRAME_CONDITION = 0x2014, - HIF_MIB_ID_IPV6_ADDR_DATAFRAME_CONDITION = 0x2015, - HIF_MIB_ID_UC_MC_BC_DATAFRAME_CONDITION = 0x2016, - HIF_MIB_ID_CONFIG_DATA_FILTER = 0x2017, - HIF_MIB_ID_SET_DATA_FILTERING = 0x2018, - HIF_MIB_ID_ARP_IP_ADDRESSES_TABLE = 0x2019, - HIF_MIB_ID_NS_IP_ADDRESSES_TABLE = 0x201A, - HIF_MIB_ID_RX_FILTER = 0x201B, - HIF_MIB_ID_BEACON_FILTER_TABLE = 0x201C, - HIF_MIB_ID_BEACON_FILTER_ENABLE = 0x201D, - HIF_MIB_ID_GRP_SEQ_COUNTER = 0x2030, - HIF_MIB_ID_TSF_COUNTER = 0x2031, - HIF_MIB_ID_STATISTICS_TABLE = 0x2032, - HIF_MIB_ID_COUNTERS_TABLE = 0x2033, - HIF_MIB_ID_MAX_TX_POWER_LEVEL = 0x2034, - HIF_MIB_ID_EXTENDED_COUNTERS_TABLE = 0x2035, - HIF_MIB_ID_DOT11_MAC_ADDRESS = 0x2040, + HIF_MIB_ID_GL_OPERATIONAL_POWER_MODE = 0x2000, + HIF_MIB_ID_GL_BLOCK_ACK_INFO = 0x2001, + HIF_MIB_ID_GL_SET_MULTI_MSG = 0x2002, + HIF_MIB_ID_CCA_CONFIG = 0x2003, + HIF_MIB_ID_ETHERTYPE_DATAFRAME_CONDITION = 0x2010, + HIF_MIB_ID_PORT_DATAFRAME_CONDITION = 0x2011, + HIF_MIB_ID_MAGIC_DATAFRAME_CONDITION = 0x2012, + HIF_MIB_ID_MAC_ADDR_DATAFRAME_CONDITION = 0x2013, + HIF_MIB_ID_IPV4_ADDR_DATAFRAME_CONDITION = 0x2014, + HIF_MIB_ID_IPV6_ADDR_DATAFRAME_CONDITION = 0x2015, + HIF_MIB_ID_UC_MC_BC_DATAFRAME_CONDITION = 0x2016, + HIF_MIB_ID_CONFIG_DATA_FILTER = 0x2017, + HIF_MIB_ID_SET_DATA_FILTERING = 0x2018, + HIF_MIB_ID_ARP_IP_ADDRESSES_TABLE = 0x2019, + HIF_MIB_ID_NS_IP_ADDRESSES_TABLE = 0x201A, + HIF_MIB_ID_RX_FILTER = 0x201B, + HIF_MIB_ID_BEACON_FILTER_TABLE = 0x201C, + HIF_MIB_ID_BEACON_FILTER_ENABLE = 0x201D, + HIF_MIB_ID_GRP_SEQ_COUNTER = 0x2030, + HIF_MIB_ID_TSF_COUNTER = 0x2031, + HIF_MIB_ID_STATISTICS_TABLE = 0x2032, + HIF_MIB_ID_COUNTERS_TABLE = 0x2033, + HIF_MIB_ID_MAX_TX_POWER_LEVEL = 0x2034, + HIF_MIB_ID_EXTENDED_COUNTERS_TABLE = 0x2035, + HIF_MIB_ID_DOT11_MAC_ADDRESS = 0x2040, HIF_MIB_ID_DOT11_MAX_TRANSMIT_MSDU_LIFETIME = 0x2041, - HIF_MIB_ID_DOT11_MAX_RECEIVE_LIFETIME = 0x2042, - HIF_MIB_ID_DOT11_WEP_DEFAULT_KEY_ID = 0x2043, - HIF_MIB_ID_DOT11_RTS_THRESHOLD = 0x2044, - HIF_MIB_ID_SLOT_TIME = 0x2045, - HIF_MIB_ID_CURRENT_TX_POWER_LEVEL = 0x2046, - HIF_MIB_ID_NON_ERP_PROTECTION = 0x2047, - HIF_MIB_ID_TEMPLATE_FRAME = 0x2048, - HIF_MIB_ID_BEACON_WAKEUP_PERIOD = 0x2049, - HIF_MIB_ID_RCPI_RSSI_THRESHOLD = 0x204A, - HIF_MIB_ID_BLOCK_ACK_POLICY = 0x204B, - HIF_MIB_ID_OVERRIDE_INTERNAL_TX_RATE = 0x204C, - HIF_MIB_ID_SET_ASSOCIATION_MODE = 0x204D, - HIF_MIB_ID_SET_UAPSD_INFORMATION = 0x204E, - HIF_MIB_ID_SET_TX_RATE_RETRY_POLICY = 0x204F, - HIF_MIB_ID_PROTECTED_MGMT_POLICY = 0x2050, - HIF_MIB_ID_SET_HT_PROTECTION = 0x2051, - HIF_MIB_ID_KEEP_ALIVE_PERIOD = 0x2052, - HIF_MIB_ID_ARP_KEEP_ALIVE_PERIOD = 0x2053, - HIF_MIB_ID_INACTIVITY_TIMER = 0x2054, - HIF_MIB_ID_INTERFACE_PROTECTION = 0x2055, - HIF_MIB_ID_BEACON_STATS = 0x2056, + HIF_MIB_ID_DOT11_MAX_RECEIVE_LIFETIME = 0x2042, + HIF_MIB_ID_DOT11_WEP_DEFAULT_KEY_ID = 0x2043, + HIF_MIB_ID_DOT11_RTS_THRESHOLD = 0x2044, + HIF_MIB_ID_SLOT_TIME = 0x2045, + HIF_MIB_ID_CURRENT_TX_POWER_LEVEL = 0x2046, + HIF_MIB_ID_NON_ERP_PROTECTION = 0x2047, + HIF_MIB_ID_TEMPLATE_FRAME = 0x2048, + HIF_MIB_ID_BEACON_WAKEUP_PERIOD = 0x2049, + HIF_MIB_ID_RCPI_RSSI_THRESHOLD = 0x204A, + HIF_MIB_ID_BLOCK_ACK_POLICY = 0x204B, + HIF_MIB_ID_OVERRIDE_INTERNAL_TX_RATE = 0x204C, + HIF_MIB_ID_SET_ASSOCIATION_MODE = 0x204D, + HIF_MIB_ID_SET_UAPSD_INFORMATION = 0x204E, + HIF_MIB_ID_SET_TX_RATE_RETRY_POLICY = 0x204F, + HIF_MIB_ID_PROTECTED_MGMT_POLICY = 0x2050, + HIF_MIB_ID_SET_HT_PROTECTION = 0x2051, + HIF_MIB_ID_KEEP_ALIVE_PERIOD = 0x2052, + HIF_MIB_ID_ARP_KEEP_ALIVE_PERIOD = 0x2053, + HIF_MIB_ID_INACTIVITY_TIMER = 0x2054, + HIF_MIB_ID_INTERFACE_PROTECTION = 0x2055, + HIF_MIB_ID_BEACON_STATS = 0x2056, }; -#define HIF_OP_POWER_MODE_MASK 0xf - enum hif_op_power_mode { - HIF_OP_POWER_MODE_ACTIVE = 0x0, - HIF_OP_POWER_MODE_DOZE = 0x1, - HIF_OP_POWER_MODE_QUIESCENT = 0x2 + HIF_OP_POWER_MODE_ACTIVE = 0x0, + HIF_OP_POWER_MODE_DOZE = 0x1, + HIF_OP_POWER_MODE_QUIESCENT = 0x2 }; struct hif_mib_gl_operational_power_mode { - u8 power_mode:4; - u8 reserved1:3; - u8 wup_ind_activation:1; - u8 reserved2[3]; -} __packed; - -struct hif_mib_gl_block_ack_info { - u8 rx_buffer_size; - u8 rx_max_num_agreements; - u8 tx_buffer_size; - u8 tx_max_num_agreements; + u8 power_mode:4; + u8 reserved1:3; + u8 wup_ind_activation:1; + u8 reserved2[3]; } __packed; struct hif_mib_gl_set_multi_msg { - u8 enable_multi_tx_conf:1; - u8 reserved1:7; - u8 reserved2[3]; -} __packed; - -enum hif_cca_thr_mode { - HIF_CCA_THR_MODE_RELATIVE = 0x0, - HIF_CCA_THR_MODE_ABSOLUTE = 0x1 -}; - -struct hif_mib_gl_cca_config { - u8 cca_thr_mode; - u8 reserved[3]; -} __packed; - -#define MAX_NUMBER_DATA_FILTERS 0xA - -#define MAX_NUMBER_IPV4_ADDR_CONDITIONS 0x4 -#define MAX_NUMBER_IPV6_ADDR_CONDITIONS 0x4 -#define MAX_NUMBER_MAC_ADDR_CONDITIONS 0x4 -#define MAX_NUMBER_UC_MC_BC_CONDITIONS 0x4 -#define MAX_NUMBER_ETHER_TYPE_CONDITIONS 0x4 -#define MAX_NUMBER_PORT_CONDITIONS 0x4 -#define MAX_NUMBER_MAGIC_CONDITIONS 0x4 -#define MAX_NUMBER_ARP_CONDITIONS 0x2 -#define MAX_NUMBER_NS_CONDITIONS 0x2 - -struct hif_mib_ethertype_data_frame_condition { - u8 condition_idx; - u8 reserved; - u16 ether_type; -} __packed; - -enum hif_udp_tcp_protocol { - HIF_PROTOCOL_UDP = 0x0, - HIF_PROTOCOL_TCP = 0x1, - HIF_PROTOCOL_BOTH_UDP_TCP = 0x2 -}; - -enum hif_which_port { - HIF_PORT_DST = 0x0, - HIF_PORT_SRC = 0x1, - HIF_PORT_SRC_OR_DST = 0x2 -}; - -struct hif_mib_ports_data_frame_condition { - u8 condition_idx; - u8 protocol; - u8 which_port; - u8 reserved1; - u16 port_number; - u8 reserved2[2]; -} __packed; - -#define HIF_API_MAGIC_PATTERN_SIZE 32 - -struct hif_mib_magic_data_frame_condition { - u8 condition_idx; - u8 offset; - u8 magic_pattern_length; - u8 reserved; - u8 magic_pattern[HIF_API_MAGIC_PATTERN_SIZE]; + u8 enable_multi_tx_conf:1; + u8 reserved1:7; + u8 reserved2[3]; } __packed; enum hif_mac_addr_type { - HIF_MAC_ADDR_A1 = 0x0, - HIF_MAC_ADDR_A2 = 0x1, - HIF_MAC_ADDR_A3 = 0x2 + HIF_MAC_ADDR_A1 = 0x0, + HIF_MAC_ADDR_A2 = 0x1, + HIF_MAC_ADDR_A3 = 0x2 }; struct hif_mib_mac_addr_data_frame_condition { - u8 condition_idx; - u8 address_type; - u8 mac_address[ETH_ALEN]; -} __packed; - -enum hif_ip_addr_mode { - HIF_IP_ADDR_SRC = 0x0, - HIF_IP_ADDR_DST = 0x1 -}; - -struct hif_mib_ipv4_addr_data_frame_condition { - u8 condition_idx; - u8 address_mode; - u8 reserved[2]; - u8 i_pv4_address[HIF_API_IPV4_ADDRESS_SIZE]; -} __packed; - -struct hif_mib_ipv6_addr_data_frame_condition { - u8 condition_idx; - u8 address_mode; - u8 reserved[2]; - u8 i_pv6_address[HIF_API_IPV6_ADDRESS_SIZE]; + u8 condition_idx; + u8 address_type; + u8 mac_address[ETH_ALEN]; } __packed; #define HIF_FILTER_UNICAST 0x1 @@ -186,365 +99,289 @@ struct hif_mib_ipv6_addr_data_frame_condition { #define HIF_FILTER_BROADCAST 0x4 struct hif_mib_uc_mc_bc_data_frame_condition { - u8 condition_idx; - u8 allowed_frames; - u8 reserved[2]; + u8 condition_idx; + u8 allowed_frames; + u8 reserved[2]; } __packed; struct hif_mib_config_data_filter { - u8 filter_idx; - u8 enable; - u8 reserved1[2]; - u8 eth_type_cond; - u8 port_cond; - u8 magic_cond; - u8 mac_cond; - u8 ipv4_cond; - u8 ipv6_cond; - u8 uc_mc_bc_cond; - u8 reserved2; + u8 filter_idx; + u8 enable; + u8 reserved1[2]; + u8 eth_type_cond; + u8 port_cond; + u8 magic_cond; + u8 mac_cond; + u8 ipv4_cond; + u8 ipv6_cond; + u8 uc_mc_bc_cond; + u8 reserved2; } __packed; struct hif_mib_set_data_filtering { - u8 invert_matching:1; - u8 reserved1:7; - u8 enable:1; - u8 reserved2:7; - u8 reserved3[2]; + u8 invert_matching:1; + u8 reserved1:7; + u8 enable:1; + u8 reserved2:7; + u8 reserved3[2]; } __packed; enum hif_arp_ns_frame_treatment { - HIF_ARP_NS_FILTERING_DISABLE = 0x0, - HIF_ARP_NS_FILTERING_ENABLE = 0x1, - HIF_ARP_NS_REPLY_ENABLE = 0x2 + HIF_ARP_NS_FILTERING_DISABLE = 0x0, + HIF_ARP_NS_FILTERING_ENABLE = 0x1, + HIF_ARP_NS_REPLY_ENABLE = 0x2 }; struct hif_mib_arp_ip_addr_table { - u8 condition_idx; - u8 arp_enable; - u8 reserved[2]; - u8 ipv4_address[HIF_API_IPV4_ADDRESS_SIZE]; -} __packed; - -struct hif_mib_ns_ip_addr_table { - u8 condition_idx; - u8 ns_enable; - u8 reserved[2]; - u8 ipv6_address[HIF_API_IPV6_ADDRESS_SIZE]; + u8 condition_idx; + u8 arp_enable; + u8 reserved[2]; + u8 ipv4_address[HIF_API_IPV4_ADDRESS_SIZE]; } __packed; struct hif_mib_rx_filter { - u8 reserved1:1; - u8 bssid_filter:1; - u8 reserved2:1; - u8 fwd_probe_req:1; - u8 keep_alive_filter:1; - u8 reserved3:3; - u8 reserved4[3]; + u8 reserved1:1; + u8 bssid_filter:1; + u8 reserved2:1; + u8 fwd_probe_req:1; + u8 keep_alive_filter:1; + u8 reserved3:3; + u8 reserved4[3]; } __packed; -#define HIF_API_OUI_SIZE 3 -#define HIF_API_MATCH_DATA_SIZE 3 - struct hif_ie_table_entry { - u8 ie_id; - u8 has_changed:1; - u8 no_longer:1; - u8 has_appeared:1; - u8 reserved:1; - u8 num_match_data:4; - u8 oui[HIF_API_OUI_SIZE]; - u8 match_data[HIF_API_MATCH_DATA_SIZE]; + u8 ie_id; + u8 has_changed:1; + u8 no_longer:1; + u8 has_appeared:1; + u8 reserved:1; + u8 num_match_data:4; + u8 oui[3]; + u8 match_data[3]; } __packed; struct hif_mib_bcn_filter_table { - u32 num_of_info_elmts; + __le32 num_of_info_elmts; struct hif_ie_table_entry ie_table[]; } __packed; enum hif_beacon_filter { - HIF_BEACON_FILTER_DISABLE = 0x0, - HIF_BEACON_FILTER_ENABLE = 0x1, - HIF_BEACON_FILTER_AUTO_ERP = 0x2 + HIF_BEACON_FILTER_DISABLE = 0x0, + HIF_BEACON_FILTER_ENABLE = 0x1, + HIF_BEACON_FILTER_AUTO_ERP = 0x2 }; struct hif_mib_bcn_filter_enable { - u32 enable; - u32 bcn_count; -} __packed; - -struct hif_mib_group_seq_counter { - u32 bits4716; - u16 bits1500; - u16 reserved; -} __packed; - -struct hif_mib_tsf_counter { - u32 tsf_counterlo; - u32 tsf_counterhi; -} __packed; - -struct hif_mib_stats_table { - s16 latest_snr; - u8 latest_rcpi; - s8 latest_rssi; + __le32 enable; + __le32 bcn_count; } __packed; struct hif_mib_extended_count_table { - u32 count_plcp_errors; - u32 count_fcs_errors; - u32 count_tx_packets; - u32 count_rx_packets; - u32 count_rx_packet_errors; - u32 count_rx_decryption_failures; - u32 count_rx_mic_failures; - u32 count_rx_no_key_failures; - u32 count_tx_multicast_frames; - u32 count_tx_frames_success; - u32 count_tx_frame_failures; - u32 count_tx_frames_retried; - u32 count_tx_frames_multi_retried; - u32 count_rx_frame_duplicates; - u32 count_rts_success; - u32 count_rts_failures; - u32 count_ack_failures; - u32 count_rx_multicast_frames; - u32 count_rx_frames_success; - u32 count_rx_cmacicv_errors; - u32 count_rx_cmac_replays; - u32 count_rx_mgmt_ccmp_replays; - u32 count_rx_bipmic_errors; - u32 count_rx_beacon; - u32 count_miss_beacon; - u32 reserved[15]; + __le32 count_plcp_errors; + __le32 count_fcs_errors; + __le32 count_tx_packets; + __le32 count_rx_packets; + __le32 count_rx_packet_errors; + __le32 count_rx_decryption_failures; + __le32 count_rx_mic_failures; + __le32 count_rx_no_key_failures; + __le32 count_tx_multicast_frames; + __le32 count_tx_frames_success; + __le32 count_tx_frame_failures; + __le32 count_tx_frames_retried; + __le32 count_tx_frames_multi_retried; + __le32 count_rx_frame_duplicates; + __le32 count_rts_success; + __le32 count_rts_failures; + __le32 count_ack_failures; + __le32 count_rx_multicast_frames; + __le32 count_rx_frames_success; + __le32 count_rx_cmacicv_errors; + __le32 count_rx_cmac_replays; + __le32 count_rx_mgmt_ccmp_replays; + __le32 count_rx_bipmic_errors; + __le32 count_rx_beacon; + __le32 count_miss_beacon; + __le32 reserved[15]; } __packed; struct hif_mib_count_table { - u32 count_plcp_errors; - u32 count_fcs_errors; - u32 count_tx_packets; - u32 count_rx_packets; - u32 count_rx_packet_errors; - u32 count_rx_decryption_failures; - u32 count_rx_mic_failures; - u32 count_rx_no_key_failures; - u32 count_tx_multicast_frames; - u32 count_tx_frames_success; - u32 count_tx_frame_failures; - u32 count_tx_frames_retried; - u32 count_tx_frames_multi_retried; - u32 count_rx_frame_duplicates; - u32 count_rts_success; - u32 count_rts_failures; - u32 count_ack_failures; - u32 count_rx_multicast_frames; - u32 count_rx_frames_success; - u32 count_rx_cmacicv_errors; - u32 count_rx_cmac_replays; - u32 count_rx_mgmt_ccmp_replays; - u32 count_rx_bipmic_errors; -} __packed; - -struct hif_mib_max_tx_power_level { - s32 max_tx_power_level_rf_port1; - s32 max_tx_power_level_rf_port2; -} __packed; - -struct hif_mib_beacon_stats { - s32 latest_tbtt_diff; - u32 reserved[4]; + __le32 count_plcp_errors; + __le32 count_fcs_errors; + __le32 count_tx_packets; + __le32 count_rx_packets; + __le32 count_rx_packet_errors; + __le32 count_rx_decryption_failures; + __le32 count_rx_mic_failures; + __le32 count_rx_no_key_failures; + __le32 count_tx_multicast_frames; + __le32 count_tx_frames_success; + __le32 count_tx_frame_failures; + __le32 count_tx_frames_retried; + __le32 count_tx_frames_multi_retried; + __le32 count_rx_frame_duplicates; + __le32 count_rts_success; + __le32 count_rts_failures; + __le32 count_ack_failures; + __le32 count_rx_multicast_frames; + __le32 count_rx_frames_success; + __le32 count_rx_cmacicv_errors; + __le32 count_rx_cmac_replays; + __le32 count_rx_mgmt_ccmp_replays; + __le32 count_rx_bipmic_errors; } __packed; struct hif_mib_mac_address { - u8 mac_addr[ETH_ALEN]; - u16 reserved; -} __packed; - -struct hif_mib_dot11_max_transmit_msdu_lifetime { - u32 max_life_time; -} __packed; - -struct hif_mib_dot11_max_receive_lifetime { - u32 max_life_time; + u8 mac_addr[ETH_ALEN]; + __le16 reserved; } __packed; struct hif_mib_wep_default_key_id { - u8 wep_default_key_id; - u8 reserved[3]; + u8 wep_default_key_id; + u8 reserved[3]; } __packed; struct hif_mib_dot11_rts_threshold { - u32 threshold; + __le32 threshold; } __packed; struct hif_mib_slot_time { - u32 slot_time; + __le32 slot_time; } __packed; struct hif_mib_current_tx_power_level { - s32 power_level; + __le32 power_level; // signed value } __packed; struct hif_mib_non_erp_protection { - u8 use_cts_to_self:1; - u8 reserved1:7; - u8 reserved2[3]; + u8 use_cts_to_self:1; + u8 reserved1:7; + u8 reserved2[3]; } __packed; enum hif_tmplt { - HIF_TMPLT_PRBREQ = 0x0, - HIF_TMPLT_BCN = 0x1, - HIF_TMPLT_NULL = 0x2, - HIF_TMPLT_QOSNUL = 0x3, - HIF_TMPLT_PSPOLL = 0x4, - HIF_TMPLT_PRBRES = 0x5, - HIF_TMPLT_ARP = 0x6, - HIF_TMPLT_NA = 0x7 + HIF_TMPLT_PRBREQ = 0x0, + HIF_TMPLT_BCN = 0x1, + HIF_TMPLT_NULL = 0x2, + HIF_TMPLT_QOSNUL = 0x3, + HIF_TMPLT_PSPOLL = 0x4, + HIF_TMPLT_PRBRES = 0x5, + HIF_TMPLT_ARP = 0x6, + HIF_TMPLT_NA = 0x7 }; -#define HIF_API_MAX_TEMPLATE_FRAME_SIZE 700 +#define HIF_API_MAX_TEMPLATE_FRAME_SIZE 700 struct hif_mib_template_frame { - u8 frame_type; - u8 init_rate:7; - u8 mode:1; - u16 frame_length; - u8 frame[HIF_API_MAX_TEMPLATE_FRAME_SIZE]; + u8 frame_type; + u8 init_rate:7; + u8 mode:1; + __le16 frame_length; + u8 frame[]; } __packed; struct hif_mib_beacon_wake_up_period { - u8 wakeup_period_min; - u8 receive_dtim:1; - u8 reserved1:7; - u8 wakeup_period_max; - u8 reserved2; + u8 wakeup_period_min; + u8 receive_dtim:1; + u8 reserved1:7; + u8 wakeup_period_max; + u8 reserved2; } __packed; struct hif_mib_rcpi_rssi_threshold { - u8 detection:1; - u8 rcpi_rssi:1; - u8 upperthresh:1; - u8 lowerthresh:1; - u8 reserved:4; - u8 lower_threshold; - u8 upper_threshold; - u8 rolling_average_count; + u8 detection:1; + u8 rcpi_rssi:1; + u8 upperthresh:1; + u8 lowerthresh:1; + u8 reserved:4; + u8 lower_threshold; + u8 upper_threshold; + u8 rolling_average_count; } __packed; #define DEFAULT_BA_MAX_RX_BUFFER_SIZE 16 struct hif_mib_block_ack_policy { - u8 block_ack_tx_tid_policy; - u8 reserved1; - u8 block_ack_rx_tid_policy; - u8 block_ack_rx_max_buffer_size; -} __packed; - -struct hif_mib_override_int_rate { - u8 internal_tx_rate; - u8 non_erp_internal_tx_rate; - u8 reserved[2]; + u8 block_ack_tx_tid_policy; + u8 reserved1; + u8 block_ack_rx_tid_policy; + u8 block_ack_rx_max_buffer_size; } __packed; enum hif_mpdu_start_spacing { - HIF_MPDU_START_SPACING_NO_RESTRIC = 0x0, - HIF_MPDU_START_SPACING_QUARTER = 0x1, - HIF_MPDU_START_SPACING_HALF = 0x2, - HIF_MPDU_START_SPACING_ONE = 0x3, - HIF_MPDU_START_SPACING_TWO = 0x4, - HIF_MPDU_START_SPACING_FOUR = 0x5, - HIF_MPDU_START_SPACING_EIGHT = 0x6, - HIF_MPDU_START_SPACING_SIXTEEN = 0x7 + HIF_MPDU_START_SPACING_NO_RESTRIC = 0x0, + HIF_MPDU_START_SPACING_QUARTER = 0x1, + HIF_MPDU_START_SPACING_HALF = 0x2, + HIF_MPDU_START_SPACING_ONE = 0x3, + HIF_MPDU_START_SPACING_TWO = 0x4, + HIF_MPDU_START_SPACING_FOUR = 0x5, + HIF_MPDU_START_SPACING_EIGHT = 0x6, + HIF_MPDU_START_SPACING_SIXTEEN = 0x7 }; struct hif_mib_set_association_mode { - u8 preambtype_use:1; - u8 mode:1; - u8 rateset:1; - u8 spacing:1; - u8 reserved1:4; - u8 short_preamble:1; - u8 reserved2:7; - u8 greenfield:1; - u8 reserved3:7; - u8 mpdu_start_spacing; - u32 basic_rate_set; + u8 preambtype_use:1; + u8 mode:1; + u8 rateset:1; + u8 spacing:1; + u8 reserved1:4; + u8 short_preamble:1; + u8 reserved2:7; + u8 greenfield:1; + u8 reserved3:7; + u8 mpdu_start_spacing; + __le32 basic_rate_set; } __packed; struct hif_mib_set_uapsd_information { - u8 trig_bckgrnd:1; - u8 trig_be:1; - u8 trig_video:1; - u8 trig_voice:1; - u8 reserved1:4; - u8 deliv_bckgrnd:1; - u8 deliv_be:1; - u8 deliv_video:1; - u8 deliv_voice:1; - u8 reserved2:4; - u16 min_auto_trigger_interval; - u16 max_auto_trigger_interval; - u16 auto_trigger_step; + u8 trig_bckgrnd:1; + u8 trig_be:1; + u8 trig_video:1; + u8 trig_voice:1; + u8 reserved1:4; + u8 deliv_bckgrnd:1; + u8 deliv_be:1; + u8 deliv_video:1; + u8 deliv_voice:1; + u8 reserved2:4; + __le16 min_auto_trigger_interval; + __le16 max_auto_trigger_interval; + __le16 auto_trigger_step; } __packed; struct hif_mib_tx_rate_retry_policy { - u8 policy_index; - u8 short_retry_count; - u8 long_retry_count; - u8 first_rate_sel:2; - u8 terminate:1; - u8 count_init:1; - u8 reserved1:4; - u8 rate_recovery_count; - u8 reserved2[3]; - u8 rates[12]; + u8 policy_index; + u8 short_retry_count; + u8 long_retry_count; + u8 first_rate_sel:2; + u8 terminate:1; + u8 count_init:1; + u8 reserved1:4; + u8 rate_recovery_count; + u8 reserved2[3]; + u8 rates[12]; } __packed; -#define HIF_MIB_NUM_TX_RATE_RETRY_POLICIES 15 +#define HIF_TX_RETRY_POLICY_MAX 15 +#define HIF_TX_RETRY_POLICY_INVALID HIF_TX_RETRY_POLICY_MAX struct hif_mib_set_tx_rate_retry_policy { - u8 num_tx_rate_policies; - u8 reserved[3]; + u8 num_tx_rate_policies; + u8 reserved[3]; struct hif_mib_tx_rate_retry_policy tx_rate_retry_policy[]; } __packed; struct hif_mib_protected_mgmt_policy { - u8 pmf_enable:1; - u8 unpmf_allowed:1; - u8 host_enc_auth_frames:1; - u8 reserved1:5; - u8 reserved2[3]; -} __packed; - -struct hif_mib_set_ht_protection { - u8 dual_cts_prot:1; - u8 reserved1:7; - u8 reserved2[3]; + u8 pmf_enable:1; + u8 unpmf_allowed:1; + u8 host_enc_auth_frames:1; + u8 reserved1:5; + u8 reserved2[3]; } __packed; struct hif_mib_keep_alive_period { - u16 keep_alive_period; - u8 reserved[2]; -} __packed; - -struct hif_mib_arp_keep_alive_period { - u16 arp_keep_alive_period; - u8 encr_type; - u8 reserved; - u8 sender_ipv4_address[HIF_API_IPV4_ADDRESS_SIZE]; - u8 target_ipv4_address[HIF_API_IPV4_ADDRESS_SIZE]; -} __packed; - -struct hif_mib_inactivity_timer { - u8 min_active_time; - u8 max_active_time; - u16 reserved; -} __packed; - -struct hif_mib_interface_protection { - u8 use_cts_prot:1; - u8 reserved1:7; - u8 reserved2[3]; + __le16 keep_alive_period; + u8 reserved[2]; } __packed; #endif diff --git a/drivers/staging/wfx/hif_rx.c b/drivers/staging/wfx/hif_rx.c index 33c22c5d629d..bb156033d1e1 100644 --- a/drivers/staging/wfx/hif_rx.c +++ b/drivers/staging/wfx/hif_rx.c @@ -22,9 +22,9 @@ static int hif_generic_confirm(struct wfx_dev *wdev, const struct hif_msg *hif, const void *buf) { // All confirm messages start with status - int status = le32_to_cpu(*((__le32 *) buf)); + int status = le32_to_cpup((__le32 *)buf); int cmd = hif->id; - int len = hif->len - 4; // drop header + int len = le16_to_cpu(hif->len) - 4; // drop header WARN(!mutex_is_locked(&wdev->hif_cmd.lock), "data locking error"); @@ -100,10 +100,10 @@ static int hif_startup_indication(struct wfx_dev *wdev, return -EINVAL; } memcpy(&wdev->hw_caps, body, sizeof(struct hif_ind_startup)); - le32_to_cpus(&wdev->hw_caps.status); - le16_to_cpus(&wdev->hw_caps.hardware_id); - le16_to_cpus(&wdev->hw_caps.num_inp_ch_bufs); - le16_to_cpus(&wdev->hw_caps.size_inp_ch_buf); + le16_to_cpus((__le16 *)&wdev->hw_caps.hardware_id); + le16_to_cpus((__le16 *)&wdev->hw_caps.num_inp_ch_bufs); + le16_to_cpus((__le16 *)&wdev->hw_caps.size_inp_ch_buf); + le32_to_cpus((__le32 *)&wdev->hw_caps.supported_rate_mask); complete(&wdev->firmware_ready); return 0; @@ -127,7 +127,7 @@ static int hif_keys_indication(struct wfx_dev *wdev, u8 pubkey[API_NCP_PUB_KEY_SIZE]; // SL_PUB_KEY_EXCHANGE_STATUS_SUCCESS is used by legacy secure link - if (body->status && body->status != SL_PUB_KEY_EXCHANGE_STATUS_SUCCESS) + if (body->status && body->status != HIF_STATUS_SLK_NEGO_SUCCESS) dev_warn(wdev->dev, "secure link negociation error\n"); memcpy(pubkey, body->ncp_pub_key, sizeof(pubkey)); memreverse(pubkey, sizeof(pubkey)); @@ -158,26 +158,39 @@ static int hif_event_indication(struct wfx_dev *wdev, { struct wfx_vif *wvif = wdev_to_wvif(wdev, hif->interface); const struct hif_ind_event *body = buf; - struct wfx_hif_event *event; - int first; + int type = le32_to_cpu(body->event_id); + int cause; - WARN_ON(!wvif); - if (!wvif) + if (!wvif) { + dev_warn(wdev->dev, "received event for non-existent vif\n"); return 0; + } - event = kzalloc(sizeof(*event), GFP_KERNEL); - if (!event) - return -ENOMEM; - - memcpy(&event->evt, body, sizeof(struct hif_ind_event)); - spin_lock(&wvif->event_queue_lock); - first = list_empty(&wvif->event_queue); - list_add_tail(&event->link, &wvif->event_queue); - spin_unlock(&wvif->event_queue_lock); - - if (first) - schedule_work(&wvif->event_handler_work); - + switch (type) { + case HIF_EVENT_IND_RCPI_RSSI: + wfx_event_report_rssi(wvif, body->event_data.rcpi_rssi); + break; + case HIF_EVENT_IND_BSSLOST: + schedule_delayed_work(&wvif->beacon_loss_work, 0); + break; + case HIF_EVENT_IND_BSSREGAINED: + cancel_delayed_work(&wvif->beacon_loss_work); + dev_dbg(wdev->dev, "ignore BSSREGAINED indication\n"); + break; + case HIF_EVENT_IND_PS_MODE_ERROR: + cause = le32_to_cpu(body->event_data.ps_mode_error); + dev_warn(wdev->dev, "error while processing power save request: %d\n", + cause); + if (cause == HIF_PS_ERROR_AP_NOT_RESP_TO_POLL) { + wvif->bss_not_support_ps_poll = true; + schedule_work(&wvif->update_pm_work); + } + break; + default: + dev_warn(wdev->dev, "unhandled event indication: %.2x\n", + type); + break; + } return 0; } @@ -224,53 +237,21 @@ static int hif_suspend_resume_indication(struct wfx_dev *wdev, struct wfx_vif *wvif = wdev_to_wvif(wdev, hif->interface); const struct hif_ind_suspend_resume_tx *body = buf; - WARN_ON(!wvif); - WARN(!body->suspend_resume_flags.bc_mc_only, "unsupported suspend/resume notification"); - if (body->suspend_resume_flags.resume) - wfx_suspend_resume_mc(wvif, STA_NOTIFY_AWAKE); - else - wfx_suspend_resume_mc(wvif, STA_NOTIFY_SLEEP); - - return 0; -} - -static int hif_error_indication(struct wfx_dev *wdev, - const struct hif_msg *hif, const void *buf) -{ - const struct hif_ind_error *body = buf; - u8 *pRollback = (u8 *) body->data; - u32 *pStatus = (u32 *) body->data; - - switch (body->type) { - case HIF_ERROR_FIRMWARE_ROLLBACK: - dev_err(wdev->dev, - "asynchronous error: firmware rollback error %d\n", - *pRollback); - break; - case HIF_ERROR_FIRMWARE_DEBUG_ENABLED: - dev_err(wdev->dev, "asynchronous error: firmware debug feature enabled\n"); - break; - case HIF_ERROR_OUTDATED_SESSION_KEY: - dev_err(wdev->dev, "asynchronous error: secure link outdated key: %#.8x\n", - *pStatus); - break; - case HIF_ERROR_INVALID_SESSION_KEY: - dev_err(wdev->dev, "asynchronous error: invalid session key\n"); - break; - case HIF_ERROR_OOR_VOLTAGE: - dev_err(wdev->dev, "asynchronous error: out-of-range overvoltage: %#.8x\n", - *pStatus); - break; - case HIF_ERROR_PDS_VERSION: - dev_err(wdev->dev, - "asynchronous error: wrong PDS payload or version: %#.8x\n", - *pStatus); - break; - default: - dev_err(wdev->dev, "asynchronous error: unknown (%d)\n", - body->type); - break; + if (body->suspend_resume_flags.bc_mc_only) { + WARN_ON(!wvif); + if (body->suspend_resume_flags.resume) + wfx_suspend_resume_mc(wvif, STA_NOTIFY_AWAKE); + else + wfx_suspend_resume_mc(wvif, STA_NOTIFY_SLEEP); + } else { + WARN(body->peer_sta_set, "misunderstood indication"); + WARN(hif->interface != 2, "misunderstood indication"); + if (body->suspend_resume_flags.resume) + wfx_suspend_hot_dev(wdev, STA_NOTIFY_AWAKE); + else + wfx_suspend_hot_dev(wdev, STA_NOTIFY_SLEEP); } + return 0; } @@ -278,13 +259,14 @@ static int hif_generic_indication(struct wfx_dev *wdev, const struct hif_msg *hif, const void *buf) { const struct hif_ind_generic *body = buf; + int type = le32_to_cpu(body->indication_type); - switch (body->indication_type) { + switch (type) { case HIF_GENERIC_INDICATION_TYPE_RAW: return 0; case HIF_GENERIC_INDICATION_TYPE_STRING: dev_info(wdev->dev, "firmware says: %s\n", - (char *) body->indication_data.raw_data); + (char *)body->indication_data.raw_data); return 0; case HIF_GENERIC_INDICATION_TYPE_RX_STATS: mutex_lock(&wdev->rx_stats_lock); @@ -296,22 +278,103 @@ static int hif_generic_indication(struct wfx_dev *wdev, sizeof(wdev->rx_stats)); mutex_unlock(&wdev->rx_stats_lock); return 0; + case HIF_GENERIC_INDICATION_TYPE_TX_POWER_LOOP_INFO: + mutex_lock(&wdev->tx_power_loop_info_lock); + memcpy(&wdev->tx_power_loop_info, + &body->indication_data.tx_power_loop_info, + sizeof(wdev->tx_power_loop_info)); + mutex_unlock(&wdev->tx_power_loop_info_lock); + return 0; default: - dev_err(wdev->dev, - "generic_indication: unknown indication type: %#.8x\n", - body->indication_type); + dev_err(wdev->dev, "generic_indication: unknown indication type: %#.8x\n", + type); return -EIO; } } +static const struct { + int val; + const char *str; + bool has_param; +} hif_errors[] = { + { HIF_ERROR_FIRMWARE_ROLLBACK, + "rollback status" }, + { HIF_ERROR_FIRMWARE_DEBUG_ENABLED, + "debug feature enabled" }, + { HIF_ERROR_PDS_PAYLOAD, + "PDS version is not supported" }, + { HIF_ERROR_PDS_TESTFEATURE, + "PDS ask for an unknown test mode" }, + { HIF_ERROR_OOR_VOLTAGE, + "out-of-range power supply voltage", true }, + { HIF_ERROR_OOR_TEMPERATURE, + "out-of-range temperature", true }, + { HIF_ERROR_SLK_REQ_DURING_KEY_EXCHANGE, + "secure link does not expect request during key exchange" }, + { HIF_ERROR_SLK_SESSION_KEY, + "secure link session key is invalid" }, + { HIF_ERROR_SLK_OVERFLOW, + "secure link overflow" }, + { HIF_ERROR_SLK_WRONG_ENCRYPTION_STATE, + "secure link messages list does not match message encryption" }, + { HIF_ERROR_HIF_BUS_FREQUENCY_TOO_LOW, + "bus clock is too slow (<1kHz)" }, + { HIF_ERROR_HIF_RX_DATA_TOO_LARGE, + "HIF message too large" }, + // Following errors only exists in old firmware versions: + { HIF_ERROR_HIF_TX_QUEUE_FULL, + "HIF messages queue is full" }, + { HIF_ERROR_HIF_BUS, + "HIF bus" }, + { HIF_ERROR_SLK_MULTI_TX_UNSUPPORTED, + "secure link does not support multi-tx confirmations" }, + { HIF_ERROR_SLK_OUTDATED_SESSION_KEY, + "secure link session key is outdated" }, + { HIF_ERROR_SLK_DECRYPTION, + "secure link params (nonce or tag) mismatch" }, +}; + +static int hif_error_indication(struct wfx_dev *wdev, + const struct hif_msg *hif, const void *buf) +{ + const struct hif_ind_error *body = buf; + int type = le32_to_cpu(body->type); + int param = (s8)body->data[0]; + int i; + + for (i = 0; i < ARRAY_SIZE(hif_errors); i++) + if (type == hif_errors[i].val) + break; + if (i < ARRAY_SIZE(hif_errors)) + if (hif_errors[i].has_param) + dev_err(wdev->dev, "asynchronous error: %s: %d\n", + hif_errors[i].str, param); + else + dev_err(wdev->dev, "asynchronous error: %s\n", + hif_errors[i].str); + else + dev_err(wdev->dev, "asynchronous error: unknown: %08x\n", type); + print_hex_dump(KERN_INFO, "hif: ", DUMP_PREFIX_OFFSET, + 16, 1, hif, le16_to_cpu(hif->len), false); + wdev->chip_frozen = true; + + return 0; +}; + static int hif_exception_indication(struct wfx_dev *wdev, const struct hif_msg *hif, const void *buf) { - size_t len = hif->len - 4; // drop header + const struct hif_ind_exception *body = buf; + int type = le32_to_cpu(body->type); - dev_err(wdev->dev, "firmware exception\n"); - print_hex_dump_bytes("Dump: ", DUMP_PREFIX_NONE, buf, len); - wdev->chip_frozen = 1; + if (type == 4) + dev_err(wdev->dev, "firmware assert %d\n", + le32_to_cpup((__le32 *)body->data)); + else + dev_err(wdev->dev, "firmware exception\n"); + print_hex_dump(KERN_INFO, "hif: ", DUMP_PREFIX_OFFSET, + 16, 1, hif, le16_to_cpu(hif->len), false); + wdev->chip_frozen = true; return -1; } diff --git a/drivers/staging/wfx/hif_tx.c b/drivers/staging/wfx/hif_tx.c index 77bca43aca42..893b67f2f792 100644 --- a/drivers/staging/wfx/hif_tx.c +++ b/drivers/staging/wfx/hif_tx.c @@ -23,8 +23,8 @@ void wfx_init_hif_cmd(struct wfx_hif_cmd *hif_cmd) mutex_init(&hif_cmd->key_renew_lock); } -static void wfx_fill_header(struct hif_msg *hif, int if_id, unsigned int cmd, - size_t size) +static void wfx_fill_header(struct hif_msg *hif, int if_id, + unsigned int cmd, size_t size) { if (if_id == -1) if_id = 2; @@ -47,8 +47,8 @@ static void *wfx_alloc_hif(size_t body_len, struct hif_msg **hif) return NULL; } -int wfx_cmd_send(struct wfx_dev *wdev, struct hif_msg *request, void *reply, - size_t reply_len, bool async) +int wfx_cmd_send(struct wfx_dev *wdev, struct hif_msg *request, + void *reply, size_t reply_len, bool async) { const char *mib_name = ""; const char *mib_sep = ""; @@ -82,6 +82,9 @@ int wfx_cmd_send(struct wfx_dev *wdev, struct hif_msg *request, void *reply, if (async) return 0; + if (wdev->poll_irq) + wfx_bh_poll_irq(wdev); + ret = wait_for_completion_timeout(&wdev->hif_cmd.done, 1 * HZ); if (!ret) { dev_err(wdev->dev, "chip is abnormally long to answer\n"); @@ -91,7 +94,7 @@ int wfx_cmd_send(struct wfx_dev *wdev, struct hif_msg *request, void *reply, if (!ret) { dev_err(wdev->dev, "chip did not answer\n"); wfx_pending_dump_old_frames(wdev, 3000); - wdev->chip_frozen = 1; + wdev->chip_frozen = true; reinit_completion(&wdev->hif_cmd.done); ret = -ETIMEDOUT; } else { @@ -103,7 +106,7 @@ int wfx_cmd_send(struct wfx_dev *wdev, struct hif_msg *request, void *reply, if (ret && (cmd == HIF_REQ_ID_READ_MIB || cmd == HIF_REQ_ID_WRITE_MIB)) { - mib_name = get_mib_name(((u16 *) request)[2]); + mib_name = get_mib_name(((u16 *)request)[2]); mib_sep = "/"; } if (ret < 0) @@ -128,7 +131,11 @@ int hif_shutdown(struct wfx_dev *wdev) int ret; struct hif_msg *hif; + if (wdev->chip_frozen) + return 0; wfx_alloc_hif(0, &hif); + if (!hif) + return -ENOMEM; wfx_fill_header(hif, -1, HIF_REQ_ID_SHUT_DOWN, 0); ret = wfx_cmd_send(wdev, hif, NULL, 0, true); // After this command, chip won't reply. Be sure to give enough time to @@ -152,6 +159,8 @@ int hif_configuration(struct wfx_dev *wdev, const u8 *conf, size_t len) struct hif_msg *hif; struct hif_req_configuration *body = wfx_alloc_hif(buf_len, &hif); + if (!hif) + return -ENOMEM; body->length = cpu_to_le16(len); memcpy(body->pds_data, conf, len); wfx_fill_header(hif, -1, HIF_REQ_ID_CONFIGURATION, buf_len); @@ -166,6 +175,8 @@ int hif_reset(struct wfx_vif *wvif, bool reset_stat) struct hif_msg *hif; struct hif_req_reset *body = wfx_alloc_hif(sizeof(*body), &hif); + if (!hif) + return -ENOMEM; body->reset_flags.reset_stat = reset_stat; wfx_fill_header(hif, wvif->id, HIF_REQ_ID_RESET, sizeof(*body)); ret = wfx_cmd_send(wvif->wdev, hif, NULL, 0, false); @@ -173,8 +184,8 @@ int hif_reset(struct wfx_vif *wvif, bool reset_stat) return ret; } -int hif_read_mib(struct wfx_dev *wdev, int vif_id, u16 mib_id, void *val, - size_t val_len) +int hif_read_mib(struct wfx_dev *wdev, int vif_id, u16 mib_id, + void *val, size_t val_len) { int ret; struct hif_msg *hif; @@ -182,36 +193,43 @@ int hif_read_mib(struct wfx_dev *wdev, int vif_id, u16 mib_id, void *val, struct hif_req_read_mib *body = wfx_alloc_hif(sizeof(*body), &hif); struct hif_cnf_read_mib *reply = kmalloc(buf_len, GFP_KERNEL); + if (!body || !reply) { + ret = -ENOMEM; + goto out; + } body->mib_id = cpu_to_le16(mib_id); wfx_fill_header(hif, vif_id, HIF_REQ_ID_READ_MIB, sizeof(*body)); ret = wfx_cmd_send(wdev, hif, reply, buf_len, false); - if (!ret && mib_id != reply->mib_id) { - dev_warn(wdev->dev, - "%s: confirmation mismatch request\n", __func__); + if (!ret && mib_id != le16_to_cpu(reply->mib_id)) { + dev_warn(wdev->dev, "%s: confirmation mismatch request\n", + __func__); ret = -EIO; } if (ret == -ENOMEM) - dev_err(wdev->dev, - "buffer is too small to receive %s (%zu < %d)\n", - get_mib_name(mib_id), val_len, reply->length); + dev_err(wdev->dev, "buffer is too small to receive %s (%zu < %d)\n", + get_mib_name(mib_id), val_len, + le16_to_cpu(reply->length)); if (!ret) - memcpy(val, &reply->mib_data, reply->length); + memcpy(val, &reply->mib_data, le16_to_cpu(reply->length)); else memset(val, 0xFF, val_len); +out: kfree(hif); kfree(reply); return ret; } -int hif_write_mib(struct wfx_dev *wdev, int vif_id, u16 mib_id, void *val, - size_t val_len) +int hif_write_mib(struct wfx_dev *wdev, int vif_id, u16 mib_id, + void *val, size_t val_len) { int ret; struct hif_msg *hif; int buf_len = sizeof(struct hif_req_write_mib) + val_len; struct hif_req_write_mib *body = wfx_alloc_hif(buf_len, &hif); + if (!hif) + return -ENOMEM; body->mib_id = cpu_to_le16(mib_id); body->length = cpu_to_le16(val_len); memcpy(&body->mib_data, val, val_len); @@ -236,6 +254,8 @@ int hif_scan(struct wfx_vif *wvif, struct cfg80211_scan_request *req, compiletime_assert(IEEE80211_MAX_SSID_LEN == HIF_API_SSID_SIZE, "API inconsistency"); + if (!hif) + return -ENOMEM; for (i = 0; i < req->n_ssids; i++) { memcpy(body->ssid_def[i].ssid, req->ssids[i].ssid, IEEE80211_MAX_SSID_LEN); @@ -268,7 +288,7 @@ int hif_scan(struct wfx_vif *wvif, struct cfg80211_scan_request *req, tmo_chan_bg = le32_to_cpu(body->max_channel_time) * USEC_PER_TU; tmo_chan_fg = 512 * USEC_PER_TU + body->probe_delay; tmo_chan_fg *= body->num_of_probe_requests; - tmo = chan_num * max(tmo_chan_bg, tmo_chan_fg); + tmo = chan_num * max(tmo_chan_bg, tmo_chan_fg) + 512 * USEC_PER_TU; wfx_fill_header(hif, wvif->id, HIF_REQ_ID_START_SCAN, buf_len); ret = wfx_cmd_send(wvif->wdev, hif, NULL, 0, false); @@ -283,6 +303,8 @@ int hif_stop_scan(struct wfx_vif *wvif) // body associated to HIF_REQ_ID_STOP_SCAN is empty wfx_alloc_hif(0, &hif); + if (!hif) + return -ENOMEM; wfx_fill_header(hif, wvif->id, HIF_REQ_ID_STOP_SCAN, 0); ret = wfx_cmd_send(wvif->wdev, hif, NULL, 0, false); kfree(hif); @@ -296,19 +318,24 @@ int hif_join(struct wfx_vif *wvif, const struct ieee80211_bss_conf *conf, struct hif_msg *hif; struct hif_req_join *body = wfx_alloc_hif(sizeof(*body), &hif); + WARN_ON(!conf->beacon_int); WARN_ON(!conf->basic_rates); + WARN_ON(sizeof(body->ssid) < ssidlen); + WARN(!conf->ibss_joined && !ssidlen, "joining an unknown BSS"); + if (!hif) + return -ENOMEM; body->infrastructure_bss_mode = !conf->ibss_joined; body->short_preamble = conf->use_short_preamble; if (channel && channel->flags & IEEE80211_CHAN_NO_IR) body->probe_for_join = 0; else body->probe_for_join = 1; - body->channel_number = cpu_to_le16(channel->hw_value); + body->channel_number = channel->hw_value; body->beacon_interval = cpu_to_le32(conf->beacon_int); body->basic_rate_set = cpu_to_le32(wfx_rate_mask_to_hw(wvif->wdev, conf->basic_rates)); memcpy(body->bssid, conf->bssid, sizeof(body->bssid)); - if (!conf->ibss_joined && ssid) { + if (ssid) { body->ssid_length = cpu_to_le32(ssidlen); memcpy(body->ssid, ssid, ssidlen); } @@ -318,17 +345,17 @@ int hif_join(struct wfx_vif *wvif, const struct ieee80211_bss_conf *conf, return ret; } -int hif_set_bss_params(struct wfx_vif *wvif, - const struct hif_req_set_bss_params *arg) +int hif_set_bss_params(struct wfx_vif *wvif, int aid, int beacon_lost_count) { int ret; struct hif_msg *hif; - struct hif_req_set_bss_params *body = wfx_alloc_hif(sizeof(*body), - &hif); + struct hif_req_set_bss_params *body = + wfx_alloc_hif(sizeof(*body), &hif); - memcpy(body, arg, sizeof(*body)); - cpu_to_le16s(&body->aid); - cpu_to_le32s(&body->operational_rate_set); + if (!hif) + return -ENOMEM; + body->aid = cpu_to_le16(aid); + body->beacon_lost_count = beacon_lost_count; wfx_fill_header(hif, wvif->id, HIF_REQ_ID_SET_BSS_PARAMS, sizeof(*body)); ret = wfx_cmd_send(wvif->wdev, hif, NULL, 0, false); @@ -343,6 +370,8 @@ int hif_add_key(struct wfx_dev *wdev, const struct hif_req_add_key *arg) // FIXME: only send necessary bits struct hif_req_add_key *body = wfx_alloc_hif(sizeof(*body), &hif); + if (!hif) + return -ENOMEM; // FIXME: swap bytes as necessary in body memcpy(body, arg, sizeof(*body)); if (wfx_api_older_than(wdev, 1, 5)) @@ -363,6 +392,8 @@ int hif_remove_key(struct wfx_dev *wdev, int idx) struct hif_msg *hif; struct hif_req_remove_key *body = wfx_alloc_hif(sizeof(*body), &hif); + if (!hif) + return -ENOMEM; body->entry_index = idx; wfx_fill_header(hif, -1, HIF_REQ_ID_REMOVE_KEY, sizeof(*body)); ret = wfx_cmd_send(wdev, hif, NULL, 0, false); @@ -382,6 +413,8 @@ int hif_set_edca_queue_params(struct wfx_vif *wvif, u16 queue, return -ENOMEM; WARN_ON(arg->aifs > 255); + if (!hif) + return -ENOMEM; body->aifsn = arg->aifs; body->cw_min = cpu_to_le16(arg->cw_min); body->cw_max = cpu_to_le16(arg->cw_max); @@ -408,6 +441,8 @@ int hif_set_pm(struct wfx_vif *wvif, bool ps, int dynamic_ps_timeout) if (!body) return -ENOMEM; + if (!hif) + return -ENOMEM; if (ps) { body->pm_mode.enter_psm = 1; // Firmware does not support more than 128ms @@ -428,9 +463,12 @@ int hif_start(struct wfx_vif *wvif, const struct ieee80211_bss_conf *conf, struct hif_msg *hif; struct hif_req_start *body = wfx_alloc_hif(sizeof(*body), &hif); + WARN_ON(!conf->beacon_int); + if (!hif) + return -ENOMEM; body->dtim_period = conf->dtim_period; body->short_preamble = conf->use_short_preamble; - body->channel_number = cpu_to_le16(channel->hw_value); + body->channel_number = channel->hw_value; body->beacon_interval = cpu_to_le32(conf->beacon_int); body->basic_rate_set = cpu_to_le32(wfx_rate_mask_to_hw(wvif->wdev, conf->basic_rates)); @@ -449,6 +487,8 @@ int hif_beacon_transmit(struct wfx_vif *wvif, bool enable) struct hif_req_beacon_transmit *body = wfx_alloc_hif(sizeof(*body), &hif); + if (!hif) + return -ENOMEM; body->enable_beaconing = enable ? 1 : 0; wfx_fill_header(hif, wvif->id, HIF_REQ_ID_BEACON_TRANSMIT, sizeof(*body)); @@ -463,9 +503,11 @@ int hif_map_link(struct wfx_vif *wvif, u8 *mac_addr, int flags, int sta_id) struct hif_msg *hif; struct hif_req_map_link *body = wfx_alloc_hif(sizeof(*body), &hif); + if (!hif) + return -ENOMEM; if (mac_addr) ether_addr_copy(body->mac_addr, mac_addr); - body->map_link_flags = *(struct hif_map_link_flags *) &flags; + body->map_link_flags = *(struct hif_map_link_flags *)&flags; body->peer_sta_id = sta_id; wfx_fill_header(hif, wvif->id, HIF_REQ_ID_MAP_LINK, sizeof(*body)); ret = wfx_cmd_send(wvif->wdev, hif, NULL, 0, false); @@ -480,6 +522,8 @@ int hif_update_ie_beacon(struct wfx_vif *wvif, const u8 *ies, size_t ies_len) int buf_len = sizeof(struct hif_req_update_ie) + ies_len; struct hif_req_update_ie *body = wfx_alloc_hif(buf_len, &hif); + if (!hif) + return -ENOMEM; body->ie_flags.beacon = 1; body->num_ies = cpu_to_le16(1); memcpy(body->ie, ies, ies_len); @@ -489,14 +533,16 @@ int hif_update_ie_beacon(struct wfx_vif *wvif, const u8 *ies, size_t ies_len) return ret; } -int hif_sl_send_pub_keys(struct wfx_dev *wdev, const uint8_t *pubkey, - const uint8_t *pubkey_hmac) +int hif_sl_send_pub_keys(struct wfx_dev *wdev, + const u8 *pubkey, const u8 *pubkey_hmac) { int ret; struct hif_msg *hif; struct hif_req_sl_exchange_pub_keys *body = wfx_alloc_hif(sizeof(*body), &hif); + if (!hif) + return -ENOMEM; body->algorithm = HIF_SL_CURVE25519; memcpy(body->host_pub_key, pubkey, sizeof(body->host_pub_key)); memcpy(body->host_pub_key_mac, pubkey_hmac, @@ -506,7 +552,7 @@ int hif_sl_send_pub_keys(struct wfx_dev *wdev, const uint8_t *pubkey, ret = wfx_cmd_send(wdev, hif, NULL, 0, false); kfree(hif); // Compatibility with legacy secure link - if (ret == SL_PUB_KEY_EXCHANGE_STATUS_SUCCESS) + if (ret == le32_to_cpu(HIF_STATUS_SLK_NEGO_SUCCESS)) ret = 0; return ret; } @@ -517,6 +563,8 @@ int hif_sl_config(struct wfx_dev *wdev, const unsigned long *bitmap) struct hif_msg *hif; struct hif_req_sl_configure *body = wfx_alloc_hif(sizeof(*body), &hif); + if (!hif) + return -ENOMEM; memcpy(body->encr_bmp, bitmap, sizeof(body->encr_bmp)); wfx_fill_header(hif, -1, HIF_REQ_ID_SL_CONFIGURE, sizeof(*body)); ret = wfx_cmd_send(wdev, hif, NULL, 0, false); @@ -524,21 +572,22 @@ int hif_sl_config(struct wfx_dev *wdev, const unsigned long *bitmap) return ret; } -int hif_sl_set_mac_key(struct wfx_dev *wdev, const u8 *slk_key, - int destination) +int hif_sl_set_mac_key(struct wfx_dev *wdev, const u8 *slk_key, int destination) { int ret; struct hif_msg *hif; struct hif_req_set_sl_mac_key *body = wfx_alloc_hif(sizeof(*body), &hif); + if (!hif) + return -ENOMEM; memcpy(body->key_value, slk_key, sizeof(body->key_value)); body->otp_or_ram = destination; wfx_fill_header(hif, -1, HIF_REQ_ID_SET_SL_MAC_KEY, sizeof(*body)); ret = wfx_cmd_send(wdev, hif, NULL, 0, false); kfree(hif); // Compatibility with legacy secure link - if (ret == SL_MAC_KEY_STATUS_SUCCESS) + if (ret == le32_to_cpu(HIF_STATUS_SLK_SET_KEY_SUCCESS)) ret = 0; return ret; } diff --git a/drivers/staging/wfx/hif_tx.h b/drivers/staging/wfx/hif_tx.h index f8520a14c14c..e9eca9330178 100644 --- a/drivers/staging/wfx/hif_tx.h +++ b/drivers/staging/wfx/hif_tx.h @@ -10,12 +10,11 @@ #ifndef WFX_HIF_TX_H #define WFX_HIF_TX_H -#include "hif_api_cmd.h" - struct ieee80211_channel; struct ieee80211_bss_conf; struct ieee80211_tx_queue_params; struct cfg80211_scan_request; +struct hif_req_add_key; struct wfx_dev; struct wfx_vif; @@ -48,8 +47,7 @@ int hif_stop_scan(struct wfx_vif *wvif); int hif_join(struct wfx_vif *wvif, const struct ieee80211_bss_conf *conf, struct ieee80211_channel *channel, const u8 *ssid, int ssidlen); int hif_set_pm(struct wfx_vif *wvif, bool ps, int dynamic_ps_timeout); -int hif_set_bss_params(struct wfx_vif *wvif, - const struct hif_req_set_bss_params *arg); +int hif_set_bss_params(struct wfx_vif *wvif, int aid, int beacon_lost_count); int hif_add_key(struct wfx_dev *wdev, const struct hif_req_add_key *arg); int hif_remove_key(struct wfx_dev *wdev, int idx); int hif_set_edca_queue_params(struct wfx_vif *wvif, u16 queue, @@ -59,8 +57,8 @@ int hif_start(struct wfx_vif *wvif, const struct ieee80211_bss_conf *conf, int hif_beacon_transmit(struct wfx_vif *wvif, bool enable); int hif_map_link(struct wfx_vif *wvif, u8 *mac_addr, int flags, int sta_id); int hif_update_ie_beacon(struct wfx_vif *wvif, const u8 *ies, size_t ies_len); -int hif_sl_set_mac_key(struct wfx_dev *wdev, const u8 *slk_key, - int destination); +int hif_sl_set_mac_key(struct wfx_dev *wdev, + const u8 *slk_key, int destination); int hif_sl_config(struct wfx_dev *wdev, const unsigned long *bitmap); int hif_sl_send_pub_keys(struct wfx_dev *wdev, const u8 *pubkey, const u8 *pubkey_hmac); diff --git a/drivers/staging/wfx/hif_tx_mib.c b/drivers/staging/wfx/hif_tx_mib.c new file mode 100644 index 000000000000..1689cb42acc0 --- /dev/null +++ b/drivers/staging/wfx/hif_tx_mib.c @@ -0,0 +1,386 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Implementation of host-to-chip MIBs of WFxxx Split Mac (WSM) API. + * + * Copyright (c) 2017-2019, Silicon Laboratories, Inc. + * Copyright (c) 2010, ST-Ericsson + * Copyright (C) 2010, ST-Ericsson SA + */ + +#include + +#include "wfx.h" +#include "hif_tx.h" +#include "hif_tx_mib.h" +#include "hif_api_mib.h" + +int hif_set_output_power(struct wfx_vif *wvif, int val) +{ + struct hif_mib_current_tx_power_level arg = { + .power_level = cpu_to_le32(val * 10), + }; + + return hif_write_mib(wvif->wdev, wvif->id, + HIF_MIB_ID_CURRENT_TX_POWER_LEVEL, + &arg, sizeof(arg)); +} + +int hif_set_beacon_wakeup_period(struct wfx_vif *wvif, + unsigned int dtim_interval, + unsigned int listen_interval) +{ + struct hif_mib_beacon_wake_up_period val = { + .wakeup_period_min = dtim_interval, + .receive_dtim = 0, + .wakeup_period_max = listen_interval, + }; + + if (dtim_interval > 0xFF || listen_interval > 0xFFFF) + return -EINVAL; + return hif_write_mib(wvif->wdev, wvif->id, + HIF_MIB_ID_BEACON_WAKEUP_PERIOD, + &val, sizeof(val)); +} + +int hif_set_rcpi_rssi_threshold(struct wfx_vif *wvif, + int rssi_thold, int rssi_hyst) +{ + struct hif_mib_rcpi_rssi_threshold arg = { + .rolling_average_count = 8, + .detection = 1, + }; + + if (!rssi_thold && !rssi_hyst) { + arg.upperthresh = 1; + arg.lowerthresh = 1; + } else { + arg.upper_threshold = rssi_thold + rssi_hyst; + arg.upper_threshold = (arg.upper_threshold + 110) * 2; + arg.lower_threshold = rssi_thold; + arg.lower_threshold = (arg.lower_threshold + 110) * 2; + } + + return hif_write_mib(wvif->wdev, wvif->id, + HIF_MIB_ID_RCPI_RSSI_THRESHOLD, &arg, sizeof(arg)); +} + +int hif_get_counters_table(struct wfx_dev *wdev, int vif_id, + struct hif_mib_extended_count_table *arg) +{ + if (wfx_api_older_than(wdev, 1, 3)) { + // extended_count_table is wider than count_table + memset(arg, 0xFF, sizeof(*arg)); + return hif_read_mib(wdev, vif_id, HIF_MIB_ID_COUNTERS_TABLE, + arg, sizeof(struct hif_mib_count_table)); + } else { + return hif_read_mib(wdev, vif_id, + HIF_MIB_ID_EXTENDED_COUNTERS_TABLE, arg, + sizeof(struct hif_mib_extended_count_table)); + } +} + +int hif_set_macaddr(struct wfx_vif *wvif, u8 *mac) +{ + struct hif_mib_mac_address msg = { }; + + if (mac) + ether_addr_copy(msg.mac_addr, mac); + return hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_DOT11_MAC_ADDRESS, + &msg, sizeof(msg)); +} + +int hif_set_rx_filter(struct wfx_vif *wvif, + bool filter_bssid, bool filter_prbreq) +{ + struct hif_mib_rx_filter val = { }; + + if (filter_bssid) + val.bssid_filter = 1; + if (!filter_prbreq) + val.fwd_probe_req = 1; + return hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_RX_FILTER, + &val, sizeof(val)); +} + +int hif_set_beacon_filter_table(struct wfx_vif *wvif, int tbl_len, + const struct hif_ie_table_entry *tbl) +{ + int ret; + struct hif_mib_bcn_filter_table *val; + int buf_len = struct_size(val, ie_table, tbl_len); + + val = kzalloc(buf_len, GFP_KERNEL); + if (!val) + return -ENOMEM; + val->num_of_info_elmts = cpu_to_le32(tbl_len); + memcpy(val->ie_table, tbl, tbl_len * sizeof(*tbl)); + ret = hif_write_mib(wvif->wdev, wvif->id, + HIF_MIB_ID_BEACON_FILTER_TABLE, val, buf_len); + kfree(val); + return ret; +} + +int hif_beacon_filter_control(struct wfx_vif *wvif, + int enable, int beacon_count) +{ + struct hif_mib_bcn_filter_enable arg = { + .enable = cpu_to_le32(enable), + .bcn_count = cpu_to_le32(beacon_count), + }; + return hif_write_mib(wvif->wdev, wvif->id, + HIF_MIB_ID_BEACON_FILTER_ENABLE, + &arg, sizeof(arg)); +} + +int hif_set_operational_mode(struct wfx_dev *wdev, enum hif_op_power_mode mode) +{ + struct hif_mib_gl_operational_power_mode val = { + .power_mode = mode, + .wup_ind_activation = 1, + }; + + return hif_write_mib(wdev, -1, HIF_MIB_ID_GL_OPERATIONAL_POWER_MODE, + &val, sizeof(val)); +} + +int hif_set_template_frame(struct wfx_vif *wvif, struct sk_buff *skb, + u8 frame_type, int init_rate) +{ + struct hif_mib_template_frame *arg; + + WARN(skb->len > HIF_API_MAX_TEMPLATE_FRAME_SIZE, "frame is too big"); + skb_push(skb, 4); + arg = (struct hif_mib_template_frame *)skb->data; + skb_pull(skb, 4); + arg->init_rate = init_rate; + arg->frame_type = frame_type; + arg->frame_length = cpu_to_le16(skb->len); + return hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_TEMPLATE_FRAME, + arg, sizeof(*arg) + skb->len); +} + +int hif_set_mfp(struct wfx_vif *wvif, bool capable, bool required) +{ + struct hif_mib_protected_mgmt_policy val = { }; + + WARN(required && !capable, "incoherent arguments"); + if (capable) { + val.pmf_enable = 1; + val.host_enc_auth_frames = 1; + } + if (!required) + val.unpmf_allowed = 1; + return hif_write_mib(wvif->wdev, wvif->id, + HIF_MIB_ID_PROTECTED_MGMT_POLICY, + &val, sizeof(val)); +} + +int hif_set_block_ack_policy(struct wfx_vif *wvif, + u8 tx_tid_policy, u8 rx_tid_policy) +{ + struct hif_mib_block_ack_policy val = { + .block_ack_tx_tid_policy = tx_tid_policy, + .block_ack_rx_tid_policy = rx_tid_policy, + }; + + return hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_BLOCK_ACK_POLICY, + &val, sizeof(val)); +} + +int hif_set_association_mode(struct wfx_vif *wvif, + struct ieee80211_bss_conf *info) +{ + struct ieee80211_sta *sta = NULL; + struct hif_mib_set_association_mode val = { + .preambtype_use = 1, + .mode = 1, + .spacing = 1, + .short_preamble = info->use_short_preamble, + }; + + rcu_read_lock(); // protect sta + if (info->bssid && !info->ibss_joined) + sta = ieee80211_find_sta(wvif->vif, info->bssid); + + // FIXME: it is strange to not retrieve all information from bss_info + if (sta && sta->ht_cap.ht_supported) { + val.mpdu_start_spacing = sta->ht_cap.ampdu_density; + if (!(info->ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT)) + val.greenfield = !!(sta->ht_cap.cap & IEEE80211_HT_CAP_GRN_FLD); + } + rcu_read_unlock(); + + return hif_write_mib(wvif->wdev, wvif->id, + HIF_MIB_ID_SET_ASSOCIATION_MODE, &val, sizeof(val)); +} + +int hif_set_tx_rate_retry_policy(struct wfx_vif *wvif, + int policy_index, u8 *rates) +{ + struct hif_mib_set_tx_rate_retry_policy *arg; + size_t size = struct_size(arg, tx_rate_retry_policy, 1); + int ret; + + arg = kzalloc(size, GFP_KERNEL); + if (!arg) + return -ENOMEM; + arg->num_tx_rate_policies = 1; + arg->tx_rate_retry_policy[0].policy_index = policy_index; + arg->tx_rate_retry_policy[0].short_retry_count = 255; + arg->tx_rate_retry_policy[0].long_retry_count = 255; + arg->tx_rate_retry_policy[0].first_rate_sel = 1; + arg->tx_rate_retry_policy[0].terminate = 1; + arg->tx_rate_retry_policy[0].count_init = 1; + memcpy(&arg->tx_rate_retry_policy[0].rates, rates, + sizeof(arg->tx_rate_retry_policy[0].rates)); + ret = hif_write_mib(wvif->wdev, wvif->id, + HIF_MIB_ID_SET_TX_RATE_RETRY_POLICY, arg, size); + kfree(arg); + return ret; +} + +int hif_set_mac_addr_condition(struct wfx_vif *wvif, + int idx, const u8 *mac_addr) +{ + struct hif_mib_mac_addr_data_frame_condition val = { + .condition_idx = idx, + .address_type = HIF_MAC_ADDR_A1, + }; + + ether_addr_copy(val.mac_address, mac_addr); + return hif_write_mib(wvif->wdev, wvif->id, + HIF_MIB_ID_MAC_ADDR_DATAFRAME_CONDITION, + &val, sizeof(val)); +} + +int hif_set_uc_mc_bc_condition(struct wfx_vif *wvif, int idx, u8 allowed_frames) +{ + struct hif_mib_uc_mc_bc_data_frame_condition val = { + .condition_idx = idx, + .allowed_frames = allowed_frames, + }; + + return hif_write_mib(wvif->wdev, wvif->id, + HIF_MIB_ID_UC_MC_BC_DATAFRAME_CONDITION, + &val, sizeof(val)); +} + +int hif_set_config_data_filter(struct wfx_vif *wvif, bool enable, int idx, + int mac_filters, int frames_types_filters) +{ + struct hif_mib_config_data_filter val = { + .enable = enable, + .filter_idx = idx, + .mac_cond = mac_filters, + .uc_mc_bc_cond = frames_types_filters, + }; + + return hif_write_mib(wvif->wdev, wvif->id, + HIF_MIB_ID_CONFIG_DATA_FILTER, &val, sizeof(val)); +} + +int hif_set_data_filtering(struct wfx_vif *wvif, bool enable, bool invert) +{ + struct hif_mib_set_data_filtering val = { + .enable = enable, + .invert_matching = invert, + }; + + return hif_write_mib(wvif->wdev, wvif->id, + HIF_MIB_ID_SET_DATA_FILTERING, &val, sizeof(val)); +} + +int hif_keep_alive_period(struct wfx_vif *wvif, int period) +{ + struct hif_mib_keep_alive_period arg = { + .keep_alive_period = cpu_to_le16(period), + }; + + return hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_KEEP_ALIVE_PERIOD, + &arg, sizeof(arg)); +}; + +int hif_set_arp_ipv4_filter(struct wfx_vif *wvif, int idx, __be32 *addr) +{ + struct hif_mib_arp_ip_addr_table arg = { + .condition_idx = idx, + .arp_enable = HIF_ARP_NS_FILTERING_DISABLE, + }; + + if (addr) { + // Caution: type of addr is __be32 + memcpy(arg.ipv4_address, addr, sizeof(arg.ipv4_address)); + arg.arp_enable = HIF_ARP_NS_FILTERING_ENABLE; + } + return hif_write_mib(wvif->wdev, wvif->id, + HIF_MIB_ID_ARP_IP_ADDRESSES_TABLE, + &arg, sizeof(arg)); +} + +int hif_use_multi_tx_conf(struct wfx_dev *wdev, bool enable) +{ + struct hif_mib_gl_set_multi_msg arg = { + .enable_multi_tx_conf = enable, + }; + + return hif_write_mib(wdev, -1, HIF_MIB_ID_GL_SET_MULTI_MSG, + &arg, sizeof(arg)); +} + +int hif_set_uapsd_info(struct wfx_vif *wvif, unsigned long val) +{ + struct hif_mib_set_uapsd_information arg = { }; + + if (val & BIT(IEEE80211_AC_VO)) + arg.trig_voice = 1; + if (val & BIT(IEEE80211_AC_VI)) + arg.trig_video = 1; + if (val & BIT(IEEE80211_AC_BE)) + arg.trig_be = 1; + if (val & BIT(IEEE80211_AC_BK)) + arg.trig_bckgrnd = 1; + return hif_write_mib(wvif->wdev, wvif->id, + HIF_MIB_ID_SET_UAPSD_INFORMATION, + &arg, sizeof(arg)); +} + +int hif_erp_use_protection(struct wfx_vif *wvif, bool enable) +{ + struct hif_mib_non_erp_protection arg = { + .use_cts_to_self = enable, + }; + + return hif_write_mib(wvif->wdev, wvif->id, + HIF_MIB_ID_NON_ERP_PROTECTION, &arg, sizeof(arg)); +} + +int hif_slot_time(struct wfx_vif *wvif, int val) +{ + struct hif_mib_slot_time arg = { + .slot_time = cpu_to_le32(val), + }; + + return hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_SLOT_TIME, + &arg, sizeof(arg)); +} + +int hif_wep_default_key_id(struct wfx_vif *wvif, int val) +{ + struct hif_mib_wep_default_key_id arg = { + .wep_default_key_id = val, + }; + + return hif_write_mib(wvif->wdev, wvif->id, + HIF_MIB_ID_DOT11_WEP_DEFAULT_KEY_ID, + &arg, sizeof(arg)); +} + +int hif_rts_threshold(struct wfx_vif *wvif, int val) +{ + struct hif_mib_dot11_rts_threshold arg = { + .threshold = cpu_to_le32(val >= 0 ? val : 0xFFFF), + }; + + return hif_write_mib(wvif->wdev, wvif->id, + HIF_MIB_ID_DOT11_RTS_THRESHOLD, &arg, sizeof(arg)); +} diff --git a/drivers/staging/wfx/hif_tx_mib.h b/drivers/staging/wfx/hif_tx_mib.h index 26b1406f9f6c..86683de7de7c 100644 --- a/drivers/staging/wfx/hif_tx_mib.h +++ b/drivers/staging/wfx/hif_tx_mib.h @@ -9,398 +9,48 @@ #ifndef WFX_HIF_TX_MIB_H #define WFX_HIF_TX_MIB_H -#include +struct wfx_vif; +struct sk_buff; -#include "wfx.h" -#include "hif_tx.h" -#include "hif_api_mib.h" - -static inline int hif_set_output_power(struct wfx_vif *wvif, int val) -{ - struct hif_mib_current_tx_power_level arg = { - .power_level = cpu_to_le32(val * 10), - }; - - return hif_write_mib(wvif->wdev, wvif->id, - HIF_MIB_ID_CURRENT_TX_POWER_LEVEL, - &arg, sizeof(arg)); -} - -static inline int hif_set_beacon_wakeup_period(struct wfx_vif *wvif, - unsigned int dtim_interval, - unsigned int listen_interval) -{ - struct hif_mib_beacon_wake_up_period val = { - .wakeup_period_min = dtim_interval, - .receive_dtim = 0, - .wakeup_period_max = cpu_to_le16(listen_interval), - }; - - if (dtim_interval > 0xFF || listen_interval > 0xFFFF) - return -EINVAL; - return hif_write_mib(wvif->wdev, wvif->id, - HIF_MIB_ID_BEACON_WAKEUP_PERIOD, - &val, sizeof(val)); -} - -static inline int hif_set_rcpi_rssi_threshold(struct wfx_vif *wvif, - int rssi_thold, int rssi_hyst) -{ - struct hif_mib_rcpi_rssi_threshold arg = { - .rolling_average_count = 8, - .detection = 1, - }; - - if (!rssi_thold && !rssi_hyst) { - arg.upperthresh = 1; - arg.lowerthresh = 1; - } else { - arg.upper_threshold = rssi_thold + rssi_hyst; - arg.upper_threshold = (arg.upper_threshold + 110) * 2; - arg.lower_threshold = rssi_thold; - arg.lower_threshold = (arg.lower_threshold + 110) * 2; - } - - return hif_write_mib(wvif->wdev, wvif->id, - HIF_MIB_ID_RCPI_RSSI_THRESHOLD, &arg, sizeof(arg)); -} - -static inline int hif_get_counters_table(struct wfx_dev *wdev, - struct hif_mib_extended_count_table *arg) -{ - if (wfx_api_older_than(wdev, 1, 3)) { - // extended_count_table is wider than count_table - memset(arg, 0xFF, sizeof(*arg)); - return hif_read_mib(wdev, 0, HIF_MIB_ID_COUNTERS_TABLE, - arg, sizeof(struct hif_mib_count_table)); - } else { - return hif_read_mib(wdev, 0, - HIF_MIB_ID_EXTENDED_COUNTERS_TABLE, arg, - sizeof(struct hif_mib_extended_count_table)); - } -} - -static inline int hif_set_macaddr(struct wfx_vif *wvif, u8 *mac) -{ - struct hif_mib_mac_address msg = { }; - - if (mac) - ether_addr_copy(msg.mac_addr, mac); - return hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_DOT11_MAC_ADDRESS, - &msg, sizeof(msg)); -} - -static inline int hif_set_rx_filter(struct wfx_vif *wvif, bool filter_bssid, - bool fwd_probe_req) -{ - struct hif_mib_rx_filter val = { }; - - if (filter_bssid) - val.bssid_filter = 1; - if (fwd_probe_req) - val.fwd_probe_req = 1; - return hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_RX_FILTER, - &val, sizeof(val)); -} - -static inline int hif_set_beacon_filter_table(struct wfx_vif *wvif, - int tbl_len, - struct hif_ie_table_entry *tbl) -{ - int ret; - struct hif_mib_bcn_filter_table *val; - int buf_len = struct_size(val, ie_table, tbl_len); - - val = kzalloc(buf_len, GFP_KERNEL); - if (!val) - return -ENOMEM; - val->num_of_info_elmts = cpu_to_le32(tbl_len); - memcpy(val->ie_table, tbl, tbl_len * sizeof(*tbl)); - ret = hif_write_mib(wvif->wdev, wvif->id, - HIF_MIB_ID_BEACON_FILTER_TABLE, val, buf_len); - kfree(val); - return ret; -} - -static inline int hif_beacon_filter_control(struct wfx_vif *wvif, - int enable, int beacon_count) -{ - struct hif_mib_bcn_filter_enable arg = { - .enable = cpu_to_le32(enable), - .bcn_count = cpu_to_le32(beacon_count), - }; - return hif_write_mib(wvif->wdev, wvif->id, - HIF_MIB_ID_BEACON_FILTER_ENABLE, - &arg, sizeof(arg)); -} - -static inline int hif_set_operational_mode(struct wfx_dev *wdev, - enum hif_op_power_mode mode) -{ - struct hif_mib_gl_operational_power_mode val = { - .power_mode = mode, - .wup_ind_activation = 1, - }; - - return hif_write_mib(wdev, -1, HIF_MIB_ID_GL_OPERATIONAL_POWER_MODE, - &val, sizeof(val)); -} - -static inline int hif_set_template_frame(struct wfx_vif *wvif, - struct sk_buff *skb, - u8 frame_type, int init_rate) -{ - struct hif_mib_template_frame *arg; - - skb_push(skb, 4); - arg = (struct hif_mib_template_frame *)skb->data; - skb_pull(skb, 4); - arg->init_rate = init_rate; - arg->frame_type = frame_type; - arg->frame_length = cpu_to_le16(skb->len); - return hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_TEMPLATE_FRAME, - arg, sizeof(*arg)); -} - -static inline int hif_set_mfp(struct wfx_vif *wvif, bool capable, bool required) -{ - struct hif_mib_protected_mgmt_policy val = { }; - - WARN(required && !capable, "incoherent arguments"); - if (capable) { - val.pmf_enable = 1; - val.host_enc_auth_frames = 1; - } - if (!required) - val.unpmf_allowed = 1; - return hif_write_mib(wvif->wdev, wvif->id, - HIF_MIB_ID_PROTECTED_MGMT_POLICY, - &val, sizeof(val)); -} - -static inline int hif_set_block_ack_policy(struct wfx_vif *wvif, - u8 tx_tid_policy, u8 rx_tid_policy) -{ - struct hif_mib_block_ack_policy val = { - .block_ack_tx_tid_policy = tx_tid_policy, - .block_ack_rx_tid_policy = rx_tid_policy, - }; - - return hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_BLOCK_ACK_POLICY, - &val, sizeof(val)); -} - -static inline int hif_set_association_mode(struct wfx_vif *wvif, - struct ieee80211_bss_conf *info) -{ - int basic_rates = wfx_rate_mask_to_hw(wvif->wdev, info->basic_rates); - struct ieee80211_sta *sta = NULL; - struct hif_mib_set_association_mode val = { - .preambtype_use = 1, - .mode = 1, - .rateset = 1, - .spacing = 1, - .short_preamble = info->use_short_preamble, - .basic_rate_set = cpu_to_le32(basic_rates) - }; - - rcu_read_lock(); // protect sta - if (info->bssid && !info->ibss_joined) - sta = ieee80211_find_sta(wvif->vif, info->bssid); - - // FIXME: it is strange to not retrieve all information from bss_info - if (sta && sta->ht_cap.ht_supported) { - val.mpdu_start_spacing = sta->ht_cap.ampdu_density; - if (!(info->ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT)) - val.greenfield = !!(sta->ht_cap.cap & IEEE80211_HT_CAP_GRN_FLD); - } - rcu_read_unlock(); - - return hif_write_mib(wvif->wdev, wvif->id, - HIF_MIB_ID_SET_ASSOCIATION_MODE, &val, sizeof(val)); -} - -static inline int hif_set_tx_rate_retry_policy(struct wfx_vif *wvif, - int policy_index, uint8_t *rates) -{ - struct hif_mib_set_tx_rate_retry_policy *arg; - size_t size = struct_size(arg, tx_rate_retry_policy, 1); - int ret; - - arg = kzalloc(size, GFP_KERNEL); - arg->num_tx_rate_policies = 1; - arg->tx_rate_retry_policy[0].policy_index = policy_index; - arg->tx_rate_retry_policy[0].short_retry_count = 255; - arg->tx_rate_retry_policy[0].long_retry_count = 255; - arg->tx_rate_retry_policy[0].first_rate_sel = 1; - arg->tx_rate_retry_policy[0].terminate = 1; - arg->tx_rate_retry_policy[0].count_init = 1; - memcpy(&arg->tx_rate_retry_policy[0].rates, rates, - sizeof(arg->tx_rate_retry_policy[0].rates)); - ret = hif_write_mib(wvif->wdev, wvif->id, - HIF_MIB_ID_SET_TX_RATE_RETRY_POLICY, arg, size); - kfree(arg); - return ret; -} - -static inline int hif_set_mac_addr_condition(struct wfx_vif *wvif, - int idx, const u8 *mac_addr) -{ - struct hif_mib_mac_addr_data_frame_condition val = { - .condition_idx = idx, - .address_type = HIF_MAC_ADDR_A1, - }; - - ether_addr_copy(val.mac_address, mac_addr); - return hif_write_mib(wvif->wdev, wvif->id, - HIF_MIB_ID_MAC_ADDR_DATAFRAME_CONDITION, - &val, sizeof(val)); -} - -static inline int hif_set_uc_mc_bc_condition(struct wfx_vif *wvif, - int idx, u8 allowed_frames) -{ - struct hif_mib_uc_mc_bc_data_frame_condition val = { - .condition_idx = idx, - .allowed_frames = allowed_frames, - }; - - return hif_write_mib(wvif->wdev, wvif->id, - HIF_MIB_ID_UC_MC_BC_DATAFRAME_CONDITION, - &val, sizeof(val)); -} - -static inline int hif_set_config_data_filter(struct wfx_vif *wvif, bool enable, - int idx, int mac_filters, - int frames_types_filters) -{ - struct hif_mib_config_data_filter val = { - .enable = enable, - .filter_idx = idx, - .mac_cond = mac_filters, - .uc_mc_bc_cond = frames_types_filters, - }; - - return hif_write_mib(wvif->wdev, wvif->id, - HIF_MIB_ID_CONFIG_DATA_FILTER, &val, sizeof(val)); -} - -static inline int hif_set_data_filtering(struct wfx_vif *wvif, - bool enable, bool invert) -{ - struct hif_mib_set_data_filtering val = { - .enable = enable, - .invert_matching = invert, - }; - - return hif_write_mib(wvif->wdev, wvif->id, - HIF_MIB_ID_SET_DATA_FILTERING, &val, sizeof(val)); -} - -static inline int hif_keep_alive_period(struct wfx_vif *wvif, int period) -{ - struct hif_mib_keep_alive_period arg = { - .keep_alive_period = cpu_to_le16(period), - }; - - return hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_KEEP_ALIVE_PERIOD, - &arg, sizeof(arg)); -}; - -static inline int hif_set_arp_ipv4_filter(struct wfx_vif *wvif, int idx, - __be32 *addr) -{ - struct hif_mib_arp_ip_addr_table arg = { - .condition_idx = idx, - .arp_enable = HIF_ARP_NS_FILTERING_DISABLE, - }; - - if (addr) { - // Caution: type of addr is __be32 - memcpy(arg.ipv4_address, addr, sizeof(arg.ipv4_address)); - arg.arp_enable = HIF_ARP_NS_FILTERING_ENABLE; - } - return hif_write_mib(wvif->wdev, wvif->id, - HIF_MIB_ID_ARP_IP_ADDRESSES_TABLE, - &arg, sizeof(arg)); -} - -static inline int hif_use_multi_tx_conf(struct wfx_dev *wdev, bool enable) -{ - struct hif_mib_gl_set_multi_msg arg = { - .enable_multi_tx_conf = enable, - }; - - return hif_write_mib(wdev, -1, HIF_MIB_ID_GL_SET_MULTI_MSG, - &arg, sizeof(arg)); -} - -static inline int hif_set_uapsd_info(struct wfx_vif *wvif, unsigned long val) -{ - struct hif_mib_set_uapsd_information arg = { }; - - if (val & BIT(IEEE80211_AC_VO)) - arg.trig_voice = 1; - if (val & BIT(IEEE80211_AC_VI)) - arg.trig_video = 1; - if (val & BIT(IEEE80211_AC_BE)) - arg.trig_be = 1; - if (val & BIT(IEEE80211_AC_BK)) - arg.trig_bckgrnd = 1; - return hif_write_mib(wvif->wdev, wvif->id, - HIF_MIB_ID_SET_UAPSD_INFORMATION, - &arg, sizeof(arg)); -} - -static inline int hif_erp_use_protection(struct wfx_vif *wvif, bool enable) -{ - struct hif_mib_non_erp_protection arg = { - .use_cts_to_self = enable, - }; - - return hif_write_mib(wvif->wdev, wvif->id, - HIF_MIB_ID_NON_ERP_PROTECTION, &arg, sizeof(arg)); -} - -static inline int hif_slot_time(struct wfx_vif *wvif, int val) -{ - struct hif_mib_slot_time arg = { - .slot_time = cpu_to_le32(val), - }; - - return hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_SLOT_TIME, - &arg, sizeof(arg)); -} - -static inline int hif_dual_cts_protection(struct wfx_vif *wvif, bool enable) -{ - struct hif_mib_set_ht_protection arg = { - .dual_cts_prot = enable, - }; - - return hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_SET_HT_PROTECTION, - &arg, sizeof(arg)); -} - -static inline int hif_wep_default_key_id(struct wfx_vif *wvif, int val) -{ - struct hif_mib_wep_default_key_id arg = { - .wep_default_key_id = val, - }; - - return hif_write_mib(wvif->wdev, wvif->id, - HIF_MIB_ID_DOT11_WEP_DEFAULT_KEY_ID, - &arg, sizeof(arg)); -} - -static inline int hif_rts_threshold(struct wfx_vif *wvif, int val) -{ - struct hif_mib_dot11_rts_threshold arg = { - .threshold = cpu_to_le32(val >= 0 ? val : 0xFFFF), - }; - - return hif_write_mib(wvif->wdev, wvif->id, - HIF_MIB_ID_DOT11_RTS_THRESHOLD, &arg, sizeof(arg)); -} +int hif_set_output_power(struct wfx_vif *wvif, int val); +int hif_set_beacon_wakeup_period(struct wfx_vif *wvif, + unsigned int dtim_interval, + unsigned int listen_interval); +int hif_set_rcpi_rssi_threshold(struct wfx_vif *wvif, + int rssi_thold, int rssi_hyst); +int hif_get_counters_table(struct wfx_dev *wdev, int vif_id, + struct hif_mib_extended_count_table *arg); +int hif_set_macaddr(struct wfx_vif *wvif, u8 *mac); +int hif_set_rx_filter(struct wfx_vif *wvif, + bool filter_bssid, bool fwd_probe_req); +int hif_set_beacon_filter_table(struct wfx_vif *wvif, int tbl_len, + const struct hif_ie_table_entry *tbl); +int hif_beacon_filter_control(struct wfx_vif *wvif, + int enable, int beacon_count); +int hif_set_operational_mode(struct wfx_dev *wdev, enum hif_op_power_mode mode); +int hif_set_template_frame(struct wfx_vif *wvif, struct sk_buff *skb, + u8 frame_type, int init_rate); +int hif_set_mfp(struct wfx_vif *wvif, bool capable, bool required); +int hif_set_block_ack_policy(struct wfx_vif *wvif, + u8 tx_tid_policy, u8 rx_tid_policy); +int hif_set_association_mode(struct wfx_vif *wvif, + struct ieee80211_bss_conf *info); +int hif_set_tx_rate_retry_policy(struct wfx_vif *wvif, + int policy_index, u8 *rates); +int hif_set_mac_addr_condition(struct wfx_vif *wvif, + int idx, const u8 *mac_addr); +int hif_set_uc_mc_bc_condition(struct wfx_vif *wvif, + int idx, u8 allowed_frames); +int hif_set_config_data_filter(struct wfx_vif *wvif, bool enable, int idx, + int mac_filters, int frames_types_filters); +int hif_set_data_filtering(struct wfx_vif *wvif, bool enable, bool invert); +int hif_keep_alive_period(struct wfx_vif *wvif, int period); +int hif_set_arp_ipv4_filter(struct wfx_vif *wvif, int idx, __be32 *addr); +int hif_use_multi_tx_conf(struct wfx_dev *wdev, bool enable); +int hif_set_uapsd_info(struct wfx_vif *wvif, unsigned long val); +int hif_erp_use_protection(struct wfx_vif *wvif, bool enable); +int hif_slot_time(struct wfx_vif *wvif, int val); +int hif_wep_default_key_id(struct wfx_vif *wvif, int val); +int hif_rts_threshold(struct wfx_vif *wvif, int val); #endif diff --git a/drivers/staging/wfx/hwio.c b/drivers/staging/wfx/hwio.c index d3a141d95a0e..777217cdf9a7 100644 --- a/drivers/staging/wfx/hwio.c +++ b/drivers/staging/wfx/hwio.c @@ -106,8 +106,8 @@ err: return ret; } -static int indirect_read(struct wfx_dev *wdev, int reg, u32 addr, void *buf, - size_t len) +static int indirect_read(struct wfx_dev *wdev, int reg, u32 addr, + void *buf, size_t len) { int ret; int i; @@ -195,8 +195,8 @@ static int indirect_write_locked(struct wfx_dev *wdev, int reg, u32 addr, return ret; } -static int indirect_read32_locked(struct wfx_dev *wdev, int reg, u32 addr, - u32 *val) +static int indirect_read32_locked(struct wfx_dev *wdev, int reg, + u32 addr, u32 *val) { int ret; __le32 *tmp = kmalloc(sizeof(u32), GFP_KERNEL); @@ -205,15 +205,15 @@ static int indirect_read32_locked(struct wfx_dev *wdev, int reg, u32 addr, return -ENOMEM; wdev->hwbus_ops->lock(wdev->hwbus_priv); ret = indirect_read(wdev, reg, addr, tmp, sizeof(u32)); - *val = cpu_to_le32(*tmp); + *val = le32_to_cpu(*tmp); _trace_io_ind_read32(reg, addr, *val); wdev->hwbus_ops->unlock(wdev->hwbus_priv); kfree(tmp); return ret; } -static int indirect_write32_locked(struct wfx_dev *wdev, int reg, u32 addr, - u32 val) +static int indirect_write32_locked(struct wfx_dev *wdev, int reg, + u32 addr, u32 val) { int ret; __le32 *tmp = kmalloc(sizeof(u32), GFP_KERNEL); @@ -233,7 +233,7 @@ int wfx_data_read(struct wfx_dev *wdev, void *buf, size_t len) { int ret; - WARN((long) buf & 3, "%s: unaligned buffer", __func__); + WARN((long)buf & 3, "%s: unaligned buffer", __func__); wdev->hwbus_ops->lock(wdev->hwbus_priv); ret = wdev->hwbus_ops->copy_from_io(wdev->hwbus_priv, WFX_REG_IN_OUT_QUEUE, buf, len); @@ -249,7 +249,7 @@ int wfx_data_write(struct wfx_dev *wdev, const void *buf, size_t len) { int ret; - WARN((long) buf & 3, "%s: unaligned buffer", __func__); + WARN((long)buf & 3, "%s: unaligned buffer", __func__); wdev->hwbus_ops->lock(wdev->hwbus_priv); ret = wdev->hwbus_ops->copy_to_io(wdev->hwbus_priv, WFX_REG_IN_OUT_QUEUE, buf, len); diff --git a/drivers/staging/wfx/key.c b/drivers/staging/wfx/key.c index 96adfa330604..5ee2ffc5f935 100644 --- a/drivers/staging/wfx/key.c +++ b/drivers/staging/wfx/key.c @@ -5,6 +5,7 @@ * Copyright (c) 2017-2019, Silicon Laboratories, Inc. * Copyright (c) 2010, ST-Ericsson */ +#include #include #include "key.h" @@ -20,14 +21,12 @@ static int wfx_alloc_key(struct wfx_dev *wdev) return -1; wdev->key_map |= BIT(idx); - wdev->keys[idx].entry_index = idx; return idx; } static void wfx_free_key(struct wfx_dev *wdev, int idx) { WARN(!(wdev->key_map & BIT(idx)), "inconsistent key allocation"); - memset(&wdev->keys[idx], 0, sizeof(wdev->keys[idx])); wdev->key_map &= ~BIT(idx); } @@ -159,7 +158,7 @@ static int wfx_add_key(struct wfx_vif *wvif, struct ieee80211_sta *sta, struct ieee80211_key_conf *key) { int ret; - struct hif_req_add_key *k; + struct hif_req_add_key k = { }; struct ieee80211_key_seq seq; struct wfx_dev *wdev = wvif->wdev; int idx = wfx_alloc_key(wvif->wdev); @@ -169,44 +168,44 @@ static int wfx_add_key(struct wfx_vif *wvif, struct ieee80211_sta *sta, ieee80211_get_key_rx_seq(key, 0, &seq); if (idx < 0) return -EINVAL; - k = &wdev->keys[idx]; - k->int_id = wvif->id; + k.int_id = wvif->id; + k.entry_index = idx; if (key->cipher == WLAN_CIPHER_SUITE_WEP40 || key->cipher == WLAN_CIPHER_SUITE_WEP104) { if (pairwise) - k->type = fill_wep_pair(&k->key.wep_pairwise_key, key, - sta->addr); + k.type = fill_wep_pair(&k.key.wep_pairwise_key, key, + sta->addr); else - k->type = fill_wep_group(&k->key.wep_group_key, key); + k.type = fill_wep_group(&k.key.wep_group_key, key); } else if (key->cipher == WLAN_CIPHER_SUITE_TKIP) { if (pairwise) - k->type = fill_tkip_pair(&k->key.tkip_pairwise_key, key, - sta->addr); + k.type = fill_tkip_pair(&k.key.tkip_pairwise_key, key, + sta->addr); else - k->type = fill_tkip_group(&k->key.tkip_group_key, key, - &seq, wvif->vif->type); + k.type = fill_tkip_group(&k.key.tkip_group_key, key, + &seq, wvif->vif->type); } else if (key->cipher == WLAN_CIPHER_SUITE_CCMP) { if (pairwise) - k->type = fill_ccmp_pair(&k->key.aes_pairwise_key, key, - sta->addr); + k.type = fill_ccmp_pair(&k.key.aes_pairwise_key, key, + sta->addr); else - k->type = fill_ccmp_group(&k->key.aes_group_key, key, - &seq); + k.type = fill_ccmp_group(&k.key.aes_group_key, key, + &seq); } else if (key->cipher == WLAN_CIPHER_SUITE_SMS4) { if (pairwise) - k->type = fill_sms4_pair(&k->key.wapi_pairwise_key, key, - sta->addr); + k.type = fill_sms4_pair(&k.key.wapi_pairwise_key, key, + sta->addr); else - k->type = fill_sms4_group(&k->key.wapi_group_key, key); + k.type = fill_sms4_group(&k.key.wapi_group_key, key); } else if (key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) { - k->type = fill_aes_cmac_group(&k->key.igtk_group_key, key, - &seq); + k.type = fill_aes_cmac_group(&k.key.igtk_group_key, key, + &seq); } else { dev_warn(wdev->dev, "unsupported key type %d\n", key->cipher); wfx_free_key(wdev, idx); return -EOPNOTSUPP; } - ret = hif_add_key(wdev, k); + ret = hif_add_key(wdev, &k); if (ret) { wfx_free_key(wdev, idx); return -EOPNOTSUPP; @@ -229,7 +228,7 @@ int wfx_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, struct ieee80211_key_conf *key) { int ret = -EOPNOTSUPP; - struct wfx_vif *wvif = (struct wfx_vif *) vif->drv_priv; + struct wfx_vif *wvif = (struct wfx_vif *)vif->drv_priv; mutex_lock(&wvif->wdev->conf_mutex); if (cmd == SET_KEY) @@ -240,29 +239,3 @@ int wfx_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, return ret; } -int wfx_upload_keys(struct wfx_vif *wvif) -{ - int i; - struct hif_req_add_key *key; - struct wfx_dev *wdev = wvif->wdev; - - for (i = 0; i < ARRAY_SIZE(wdev->keys); i++) { - if (wdev->key_map & BIT(i)) { - key = &wdev->keys[i]; - if (key->int_id == wvif->id) - hif_add_key(wdev, key); - } - } - return 0; -} - -void wfx_wep_key_work(struct work_struct *work) -{ - struct wfx_vif *wvif = container_of(work, struct wfx_vif, wep_key_work); - - wfx_tx_flush(wvif->wdev); - hif_wep_default_key_id(wvif, wvif->wep_default_key_id); - wfx_pending_requeue(wvif->wdev, wvif->wep_pending_skb); - wvif->wep_pending_skb = NULL; - wfx_tx_unlock(wvif->wdev); -} diff --git a/drivers/staging/wfx/key.h b/drivers/staging/wfx/key.h index 9436ccdf4d3b..ff31fc9c565a 100644 --- a/drivers/staging/wfx/key.h +++ b/drivers/staging/wfx/key.h @@ -16,7 +16,5 @@ struct wfx_vif; int wfx_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, struct ieee80211_vif *vif, struct ieee80211_sta *sta, struct ieee80211_key_conf *key); -int wfx_upload_keys(struct wfx_vif *wvif); -void wfx_wep_key_work(struct work_struct *work); #endif /* WFX_STA_H */ diff --git a/drivers/staging/wfx/main.c b/drivers/staging/wfx/main.c index 3c4c240229ad..6bd96f476388 100644 --- a/drivers/staging/wfx/main.c +++ b/drivers/staging/wfx/main.c @@ -28,6 +28,7 @@ #include "bh.h" #include "sta.h" #include "key.h" +#include "scan.h" #include "debug.h" #include "data_tx.h" #include "secure_link.h" @@ -106,7 +107,7 @@ static const struct ieee80211_supported_band wfx_band_2ghz = { .ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE, .mcs = { .rx_mask = { 0xFF }, // MCS0 to MCS7 - .rx_highest = 65, + .rx_highest = cpu_to_le16(72), .tx_params = IEEE80211_HT_MCS_TX_DEFINED, }, }, @@ -133,15 +134,19 @@ static const struct ieee80211_ops wfx_ops = { .remove_interface = wfx_remove_interface, .config = wfx_config, .tx = wfx_tx, + .join_ibss = wfx_join_ibss, + .leave_ibss = wfx_leave_ibss, .conf_tx = wfx_conf_tx, .hw_scan = wfx_hw_scan, .cancel_hw_scan = wfx_cancel_hw_scan, + .start_ap = wfx_start_ap, + .stop_ap = wfx_stop_ap, .sta_add = wfx_sta_add, .sta_remove = wfx_sta_remove, - .sta_notify = wfx_sta_notify, .set_tim = wfx_set_tim, .set_key = wfx_set_key, .set_rts_threshold = wfx_set_rts_threshold, + .set_default_unicast_key = wfx_set_default_unicast_key, .bss_info_changed = wfx_bss_info_changed, .prepare_multicast = wfx_prepare_multicast, .configure_filter = wfx_configure_filter, @@ -165,8 +170,8 @@ bool wfx_api_older_than(struct wfx_dev *wdev, int major, int minor) return false; } -struct gpio_desc *wfx_get_gpio(struct device *dev, int override, - const char *label) +struct gpio_desc *wfx_get_gpio(struct device *dev, + int override, const char *label) { struct gpio_desc *ret; char label_buf[256]; @@ -187,18 +192,18 @@ struct gpio_desc *wfx_get_gpio(struct device *dev, int override, if (!ret || PTR_ERR(ret) == -ENOENT) dev_warn(dev, "gpio %s is not defined\n", label); else - dev_warn(dev, - "error while requesting gpio %s\n", label); + dev_warn(dev, "error while requesting gpio %s\n", + label); ret = NULL; } else { - dev_dbg(dev, - "using gpio %d for %s\n", desc_to_gpio(ret), label); + dev_dbg(dev, "using gpio %d for %s\n", + desc_to_gpio(ret), label); } return ret; } /* NOTE: wfx_send_pds() destroy buf */ -int wfx_send_pds(struct wfx_dev *wdev, unsigned char *buf, size_t len) +int wfx_send_pds(struct wfx_dev *wdev, u8 *buf, size_t len) { int ret; int start, brace_level, i; @@ -224,16 +229,19 @@ int wfx_send_pds(struct wfx_dev *wdev, unsigned char *buf, size_t len) buf[i] = '}'; ret = hif_configuration(wdev, buf + start, i - start + 1); - if (ret == HIF_STATUS_FAILURE) { - dev_err(wdev->dev, "PDS bytes %d to %d: invalid data (unsupported options?)\n", start, i); + if (ret > 0) { + dev_err(wdev->dev, "PDS bytes %d to %d: invalid data (unsupported options?)\n", + start, i); return -EINVAL; } if (ret == -ETIMEDOUT) { - dev_err(wdev->dev, "PDS bytes %d to %d: chip didn't reply (corrupted file?)\n", start, i); + dev_err(wdev->dev, "PDS bytes %d to %d: chip didn't reply (corrupted file?)\n", + start, i); return ret; } if (ret) { - dev_err(wdev->dev, "PDS bytes %d to %d: chip returned an unknown error\n", start, i); + dev_err(wdev->dev, "PDS bytes %d to %d: chip returned an unknown error\n", + start, i); return -EIO; } buf[i] = ','; @@ -247,7 +255,7 @@ static int wfx_send_pdata_pds(struct wfx_dev *wdev) { int ret = 0; const struct firmware *pds; - unsigned char *tmp_buf; + u8 *tmp_buf; ret = request_firmware(&pds, wdev->pdata.file_pds, wdev->dev); if (ret) { @@ -266,9 +274,9 @@ static void wfx_free_common(void *data) { struct wfx_dev *wdev = data; + mutex_destroy(&wdev->tx_power_loop_info_lock); mutex_destroy(&wdev->rx_stats_lock); mutex_destroy(&wdev->conf_mutex); - wfx_tx_queues_deinit(wdev); ieee80211_free_hw(wdev->hw); } @@ -286,7 +294,6 @@ struct wfx_dev *wfx_init_common(struct device *dev, SET_IEEE80211_DEV(hw, dev); - ieee80211_hw_set(hw, NEED_DTIM_BEFORE_ASSOC); ieee80211_hw_set(hw, TX_AMPDU_SETUP_IN_HW); ieee80211_hw_set(hw, AMPDU_AGGREGATION); ieee80211_hw_set(hw, CONNECTION_MONITOR); @@ -315,7 +322,7 @@ struct wfx_dev *wfx_init_common(struct device *dev, hw->wiphy->flags |= WIPHY_FLAG_AP_PROBE_RESP_OFFLOAD; hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD; hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; - hw->wiphy->max_ap_assoc_sta = WFX_MAX_STA_IN_AP_MODE; + hw->wiphy->max_ap_assoc_sta = HIF_LINK_ID_MAX; hw->wiphy->max_scan_ssids = 2; hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; hw->wiphy->n_iface_combinations = ARRAY_SIZE(wfx_iface_combinations); @@ -338,7 +345,10 @@ struct wfx_dev *wfx_init_common(struct device *dev, mutex_init(&wdev->conf_mutex); mutex_init(&wdev->rx_stats_lock); + mutex_init(&wdev->tx_power_loop_info_lock); init_completion(&wdev->firmware_ready); + INIT_DELAYED_WORK(&wdev->cooling_timeout_work, + wfx_cooling_timeout_work); wfx_init_hif_cmd(&wdev->hif_cmd); wfx_tx_queues_init(wdev); @@ -359,23 +369,24 @@ int wfx_probe(struct wfx_dev *wdev) // prevent bh() to touch it. gpio_saved = wdev->pdata.gpio_wakeup; wdev->pdata.gpio_wakeup = NULL; + wdev->poll_irq = true; wfx_bh_register(wdev); err = wfx_init_device(wdev); if (err) - goto err1; + goto err0; - err = wait_for_completion_interruptible_timeout(&wdev->firmware_ready, - 10 * HZ); + wfx_bh_poll_irq(wdev); + err = wait_for_completion_timeout(&wdev->firmware_ready, 1 * HZ); if (err <= 0) { if (err == 0) { - dev_err(wdev->dev, "timeout while waiting for startup indication. IRQ configuration error?\n"); + dev_err(wdev->dev, "timeout while waiting for startup indication\n"); err = -ETIMEDOUT; } else if (err == -ERESTARTSYS) { dev_info(wdev->dev, "probe interrupted by user\n"); } - goto err1; + goto err0; } // FIXME: fill wiphy::hw_version @@ -384,7 +395,7 @@ int wfx_probe(struct wfx_dev *wdev) wdev->hw_caps.firmware_build, wdev->hw_caps.firmware_label, wdev->hw_caps.api_version_major, wdev->hw_caps.api_version_minor, - wdev->keyset, *((u32 *) &wdev->hw_caps.capabilities)); + wdev->keyset, *((u32 *)&wdev->hw_caps.capabilities)); snprintf(wdev->hw->wiphy->fw_version, sizeof(wdev->hw->wiphy->fw_version), "%d.%d.%d", @@ -397,14 +408,14 @@ int wfx_probe(struct wfx_dev *wdev) "unsupported firmware API version (expect 1 while firmware returns %d)\n", wdev->hw_caps.api_version_major); err = -ENOTSUPP; - goto err1; + goto err0; } err = wfx_sl_init(wdev); if (err && wdev->hw_caps.capabilities.link_mode == SEC_LINK_ENFORCED) { dev_err(wdev->dev, "chip require secure_link, but can't negociate it\n"); - goto err1; + goto err0; } if (wdev->hw_caps.regul_sel_mode_info.region_sel_mode) { @@ -417,7 +428,16 @@ int wfx_probe(struct wfx_dev *wdev) wdev->pdata.file_pds); err = wfx_send_pdata_pds(wdev); if (err < 0) - goto err1; + goto err0; + + wdev->poll_irq = false; + err = wdev->hwbus_ops->irq_subscribe(wdev->hwbus_priv); + if (err) + goto err0; + + err = hif_use_multi_tx_conf(wdev, true); + if (err) + dev_err(wdev->dev, "misconfigured IRQ?\n"); wdev->pdata.gpio_wakeup = gpio_saved; if (wdev->pdata.gpio_wakeup) { @@ -432,8 +452,6 @@ int wfx_probe(struct wfx_dev *wdev) hif_set_operational_mode(wdev, HIF_OP_POWER_MODE_DOZE); } - hif_use_multi_tx_conf(wdev, true); - for (i = 0; i < ARRAY_SIZE(wdev->addresses); i++) { eth_zero_addr(wdev->addresses[i].addr); macaddr = of_get_mac_address(wdev->dev->of_node); @@ -466,8 +484,9 @@ int wfx_probe(struct wfx_dev *wdev) err2: ieee80211_unregister_hw(wdev->hw); - ieee80211_free_hw(wdev->hw); err1: + wdev->hwbus_ops->irq_unsubscribe(wdev->hwbus_priv); +err0: wfx_bh_unregister(wdev); return err; } @@ -476,6 +495,7 @@ void wfx_release(struct wfx_dev *wdev) { ieee80211_unregister_hw(wdev->hw); hif_shutdown(wdev); + wdev->hwbus_ops->irq_unsubscribe(wdev->hwbus_priv); wfx_bh_unregister(wdev); wfx_sl_deinit(wdev); } diff --git a/drivers/staging/wfx/main.h b/drivers/staging/wfx/main.h index 9c9410072def..f832ce409fda 100644 --- a/drivers/staging/wfx/main.h +++ b/drivers/staging/wfx/main.h @@ -13,10 +13,10 @@ #include #include -#include "bus.h" #include "hif_api_general.h" struct wfx_dev; +struct hwbus_ops; struct wfx_platform_data { /* Keyset and ".sec" extention will appended to this string */ @@ -41,6 +41,6 @@ void wfx_release(struct wfx_dev *wdev); struct gpio_desc *wfx_get_gpio(struct device *dev, int override, const char *label); bool wfx_api_older_than(struct wfx_dev *wdev, int major, int minor); -int wfx_send_pds(struct wfx_dev *wdev, unsigned char *buf, size_t len); +int wfx_send_pds(struct wfx_dev *wdev, u8 *buf, size_t len); #endif diff --git a/drivers/staging/wfx/queue.c b/drivers/staging/wfx/queue.c index 39d9127ce4b9..3248ecefda56 100644 --- a/drivers/staging/wfx/queue.c +++ b/drivers/staging/wfx/queue.c @@ -35,6 +35,7 @@ void wfx_tx_flush(struct wfx_dev *wdev) if (wdev->chip_frozen) return; + wfx_tx_lock(wdev); mutex_lock(&wdev->hif_cmd.lock); ret = wait_event_timeout(wdev->hif.tx_buffers_empty, !wdev->hif.tx_buffers_used, @@ -44,9 +45,10 @@ void wfx_tx_flush(struct wfx_dev *wdev) wdev->hif.tx_buffers_used); wfx_pending_dump_old_frames(wdev, 3000); // FIXME: drop pending frames here - wdev->chip_frozen = 1; + wdev->chip_frozen = true; } mutex_unlock(&wdev->hif_cmd.lock); + wfx_tx_unlock(wdev); } void wfx_tx_lock_flush(struct wfx_dev *wdev) @@ -55,261 +57,142 @@ void wfx_tx_lock_flush(struct wfx_dev *wdev) wfx_tx_flush(wdev); } -void wfx_tx_queues_lock(struct wfx_dev *wdev) -{ - int i; - struct wfx_queue *queue; - - for (i = 0; i < IEEE80211_NUM_ACS; ++i) { - queue = &wdev->tx_queue[i]; - spin_lock_bh(&queue->queue.lock); - if (queue->tx_locked_cnt++ == 0) - ieee80211_stop_queue(wdev->hw, queue->queue_id); - spin_unlock_bh(&queue->queue.lock); - } -} - -void wfx_tx_queues_unlock(struct wfx_dev *wdev) -{ - int i; - struct wfx_queue *queue; - - for (i = 0; i < IEEE80211_NUM_ACS; ++i) { - queue = &wdev->tx_queue[i]; - spin_lock_bh(&queue->queue.lock); - WARN(!queue->tx_locked_cnt, "queue already unlocked"); - if (--queue->tx_locked_cnt == 0) - ieee80211_wake_queue(wdev->hw, queue->queue_id); - spin_unlock_bh(&queue->queue.lock); - } -} - -/* If successful, LOCKS the TX queue! */ -void wfx_tx_queues_wait_empty_vif(struct wfx_vif *wvif) -{ - int i; - bool done; - struct wfx_queue *queue; - struct sk_buff *item; - struct wfx_dev *wdev = wvif->wdev; - struct hif_msg *hif; - - if (wvif->wdev->chip_frozen) { - wfx_tx_lock_flush(wdev); - wfx_tx_queues_clear(wdev); - return; - } - - do { - done = true; - wfx_tx_lock_flush(wdev); - for (i = 0; i < IEEE80211_NUM_ACS && done; ++i) { - queue = &wdev->tx_queue[i]; - spin_lock_bh(&queue->queue.lock); - skb_queue_walk(&queue->queue, item) { - hif = (struct hif_msg *) item->data; - if (hif->interface == wvif->id) - done = false; - } - spin_unlock_bh(&queue->queue.lock); - } - if (!done) { - wfx_tx_unlock(wdev); - msleep(20); - } - } while (!done); -} - -static void wfx_tx_queue_clear(struct wfx_dev *wdev, struct wfx_queue *queue, - struct sk_buff_head *gc_list) -{ - int i; - struct sk_buff *item; - struct wfx_queue_stats *stats = &wdev->tx_queue_stats; - - spin_lock_bh(&queue->queue.lock); - while ((item = __skb_dequeue(&queue->queue)) != NULL) - skb_queue_head(gc_list, item); - spin_lock_nested(&stats->pending.lock, 1); - for (i = 0; i < ARRAY_SIZE(stats->link_map_cache); ++i) { - stats->link_map_cache[i] -= queue->link_map_cache[i]; - queue->link_map_cache[i] = 0; - } - spin_unlock(&stats->pending.lock); - spin_unlock_bh(&queue->queue.lock); -} - -void wfx_tx_queues_clear(struct wfx_dev *wdev) -{ - int i; - struct sk_buff *item; - struct sk_buff_head gc_list; - struct wfx_queue_stats *stats = &wdev->tx_queue_stats; - - skb_queue_head_init(&gc_list); - for (i = 0; i < IEEE80211_NUM_ACS; ++i) - wfx_tx_queue_clear(wdev, &wdev->tx_queue[i], &gc_list); - wake_up(&stats->wait_link_id_empty); - while ((item = skb_dequeue(&gc_list)) != NULL) - wfx_skb_dtor(wdev, item); -} - void wfx_tx_queues_init(struct wfx_dev *wdev) { int i; - memset(&wdev->tx_queue_stats, 0, sizeof(wdev->tx_queue_stats)); - memset(wdev->tx_queue, 0, sizeof(wdev->tx_queue)); - skb_queue_head_init(&wdev->tx_queue_stats.pending); - init_waitqueue_head(&wdev->tx_queue_stats.wait_link_id_empty); - + skb_queue_head_init(&wdev->tx_pending); + init_waitqueue_head(&wdev->tx_dequeue); for (i = 0; i < IEEE80211_NUM_ACS; ++i) { - wdev->tx_queue[i].queue_id = i; - skb_queue_head_init(&wdev->tx_queue[i].queue); + skb_queue_head_init(&wdev->tx_queue[i].normal); + skb_queue_head_init(&wdev->tx_queue[i].cab); } } -void wfx_tx_queues_deinit(struct wfx_dev *wdev) +void wfx_tx_queues_check_empty(struct wfx_dev *wdev) { - WARN_ON(!skb_queue_empty(&wdev->tx_queue_stats.pending)); - wfx_tx_queues_clear(wdev); -} + int i; -int wfx_tx_queue_get_num_queued(struct wfx_queue *queue, u32 link_id_map) -{ - int ret, i; - - if (!link_id_map) - return 0; - - spin_lock_bh(&queue->queue.lock); - if (link_id_map == (u32)-1) { - ret = skb_queue_len(&queue->queue); - } else { - ret = 0; - for (i = 0; i < ARRAY_SIZE(queue->link_map_cache); i++) - if (link_id_map & BIT(i)) - ret += queue->link_map_cache[i]; + WARN_ON(!skb_queue_empty_lockless(&wdev->tx_pending)); + for (i = 0; i < IEEE80211_NUM_ACS; ++i) { + WARN_ON(atomic_read(&wdev->tx_queue[i].pending_frames)); + WARN_ON(!skb_queue_empty_lockless(&wdev->tx_queue[i].normal)); + WARN_ON(!skb_queue_empty_lockless(&wdev->tx_queue[i].cab)); } - spin_unlock_bh(&queue->queue.lock); - return ret; } -void wfx_tx_queue_put(struct wfx_dev *wdev, struct wfx_queue *queue, - struct sk_buff *skb) +static bool __wfx_tx_queue_empty(struct wfx_dev *wdev, + struct sk_buff_head *skb_queue, int vif_id) { - struct wfx_queue_stats *stats = &wdev->tx_queue_stats; - struct wfx_tx_priv *tx_priv = wfx_skb_tx_priv(skb); + struct hif_msg *hif_msg; + struct sk_buff *skb; - WARN(tx_priv->link_id >= ARRAY_SIZE(stats->link_map_cache), "invalid link-id value"); - spin_lock_bh(&queue->queue.lock); - __skb_queue_tail(&queue->queue, skb); - - ++queue->link_map_cache[tx_priv->link_id]; - - spin_lock_nested(&stats->pending.lock, 1); - ++stats->link_map_cache[tx_priv->link_id]; - spin_unlock(&stats->pending.lock); - spin_unlock_bh(&queue->queue.lock); -} - -static struct sk_buff *wfx_tx_queue_get(struct wfx_dev *wdev, - struct wfx_queue *queue, - u32 link_id_map) -{ - struct sk_buff *skb = NULL; - struct sk_buff *item; - struct wfx_queue_stats *stats = &wdev->tx_queue_stats; - struct wfx_tx_priv *tx_priv; - bool wakeup_stats = false; - - spin_lock_bh(&queue->queue.lock); - skb_queue_walk(&queue->queue, item) { - tx_priv = wfx_skb_tx_priv(item); - if (link_id_map & BIT(tx_priv->link_id)) { - skb = item; - break; + spin_lock_bh(&skb_queue->lock); + skb_queue_walk(skb_queue, skb) { + hif_msg = (struct hif_msg *)skb->data; + if (vif_id < 0 || hif_msg->interface == vif_id) { + spin_unlock_bh(&skb_queue->lock); + return false; } } - if (skb) { - tx_priv = wfx_skb_tx_priv(skb); - tx_priv->xmit_timestamp = ktime_get(); - __skb_unlink(skb, &queue->queue); - --queue->link_map_cache[tx_priv->link_id]; + spin_unlock_bh(&skb_queue->lock); + return true; +} - spin_lock_nested(&stats->pending.lock, 1); - __skb_queue_tail(&stats->pending, skb); - if (!--stats->link_map_cache[tx_priv->link_id]) - wakeup_stats = true; - spin_unlock(&stats->pending.lock); +bool wfx_tx_queue_empty(struct wfx_dev *wdev, + struct wfx_queue *queue, int vif_id) +{ + return __wfx_tx_queue_empty(wdev, &queue->normal, vif_id) && + __wfx_tx_queue_empty(wdev, &queue->cab, vif_id); +} + +static void __wfx_tx_queue_drop(struct wfx_dev *wdev, + struct sk_buff_head *skb_queue, int vif_id, + struct sk_buff_head *dropped) +{ + struct sk_buff *skb, *tmp; + struct hif_msg *hif_msg; + + spin_lock_bh(&skb_queue->lock); + skb_queue_walk_safe(skb_queue, skb, tmp) { + hif_msg = (struct hif_msg *)skb->data; + if (vif_id < 0 || hif_msg->interface == vif_id) { + __skb_unlink(skb, skb_queue); + skb_queue_head(dropped, skb); + } } - spin_unlock_bh(&queue->queue.lock); - if (wakeup_stats) - wake_up(&stats->wait_link_id_empty); - return skb; + spin_unlock_bh(&skb_queue->lock); } -int wfx_pending_requeue(struct wfx_dev *wdev, struct sk_buff *skb) +void wfx_tx_queue_drop(struct wfx_dev *wdev, struct wfx_queue *queue, + int vif_id, struct sk_buff_head *dropped) +{ + __wfx_tx_queue_drop(wdev, &queue->cab, vif_id, dropped); + __wfx_tx_queue_drop(wdev, &queue->normal, vif_id, dropped); + wake_up(&wdev->tx_dequeue); +} + +void wfx_tx_queues_put(struct wfx_dev *wdev, struct sk_buff *skb) { - struct wfx_queue_stats *stats = &wdev->tx_queue_stats; - struct wfx_tx_priv *tx_priv = wfx_skb_tx_priv(skb); struct wfx_queue *queue = &wdev->tx_queue[skb_get_queue_mapping(skb)]; + struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); - WARN_ON(skb_get_queue_mapping(skb) > 3); - spin_lock_bh(&queue->queue.lock); - ++queue->link_map_cache[tx_priv->link_id]; - - spin_lock_nested(&stats->pending.lock, 1); - ++stats->link_map_cache[tx_priv->link_id]; - __skb_unlink(skb, &stats->pending); - spin_unlock(&stats->pending.lock); - __skb_queue_tail(&queue->queue, skb); - spin_unlock_bh(&queue->queue.lock); - return 0; + if (tx_info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) + skb_queue_tail(&queue->cab, skb); + else + skb_queue_tail(&queue->normal, skb); } -int wfx_pending_remove(struct wfx_dev *wdev, struct sk_buff *skb) +void wfx_pending_drop(struct wfx_dev *wdev, struct sk_buff_head *dropped) { - struct wfx_queue_stats *stats = &wdev->tx_queue_stats; + struct wfx_queue *queue; + struct sk_buff *skb; - spin_lock_bh(&stats->pending.lock); - __skb_unlink(skb, &stats->pending); - spin_unlock_bh(&stats->pending.lock); - wfx_skb_dtor(wdev, skb); - - return 0; + WARN(!wdev->chip_frozen, "%s should only be used to recover a frozen device", + __func__); + while ((skb = skb_dequeue(&wdev->tx_pending)) != NULL) { + queue = &wdev->tx_queue[skb_get_queue_mapping(skb)]; + WARN_ON(skb_get_queue_mapping(skb) > 3); + WARN_ON(!atomic_read(&queue->pending_frames)); + atomic_dec(&queue->pending_frames); + skb_queue_head(dropped, skb); + } } struct sk_buff *wfx_pending_get(struct wfx_dev *wdev, u32 packet_id) { - struct sk_buff *skb; + struct wfx_queue *queue; struct hif_req_tx *req; - struct wfx_queue_stats *stats = &wdev->tx_queue_stats; + struct sk_buff *skb; - spin_lock_bh(&stats->pending.lock); - skb_queue_walk(&stats->pending, skb) { + spin_lock_bh(&wdev->tx_pending.lock); + skb_queue_walk(&wdev->tx_pending, skb) { req = wfx_skb_txreq(skb); if (req->packet_id == packet_id) { - spin_unlock_bh(&stats->pending.lock); + spin_unlock_bh(&wdev->tx_pending.lock); + queue = &wdev->tx_queue[skb_get_queue_mapping(skb)]; + WARN_ON(skb_get_queue_mapping(skb) > 3); + WARN_ON(!atomic_read(&queue->pending_frames)); + atomic_dec(&queue->pending_frames); + skb_unlink(skb, &wdev->tx_pending); return skb; } } - spin_unlock_bh(&stats->pending.lock); + spin_unlock_bh(&wdev->tx_pending.lock); WARN(1, "cannot find packet in pending queue"); return NULL; } void wfx_pending_dump_old_frames(struct wfx_dev *wdev, unsigned int limit_ms) { - struct wfx_queue_stats *stats = &wdev->tx_queue_stats; ktime_t now = ktime_get(); struct wfx_tx_priv *tx_priv; struct hif_req_tx *req; struct sk_buff *skb; bool first = true; - spin_lock_bh(&stats->pending.lock); - skb_queue_walk(&stats->pending, skb) { + spin_lock_bh(&wdev->tx_pending.lock); + skb_queue_walk(&wdev->tx_pending, skb) { tx_priv = wfx_skb_tx_priv(skb); req = wfx_skb_txreq(skb); if (ktime_after(now, ktime_add_ms(tx_priv->xmit_timestamp, @@ -324,7 +207,7 @@ void wfx_pending_dump_old_frames(struct wfx_dev *wdev, unsigned int limit_ms) ktime_ms_delta(now, tx_priv->xmit_timestamp)); } } - spin_unlock_bh(&stats->pending.lock); + spin_unlock_bh(&wdev->tx_pending.lock); } unsigned int wfx_pending_get_pkt_us_delay(struct wfx_dev *wdev, @@ -336,138 +219,66 @@ unsigned int wfx_pending_get_pkt_us_delay(struct wfx_dev *wdev, return ktime_us_delta(now, tx_priv->xmit_timestamp); } -bool wfx_tx_queues_is_empty(struct wfx_dev *wdev) -{ - int i; - struct sk_buff_head *queue; - bool ret = true; - - for (i = 0; i < IEEE80211_NUM_ACS; i++) { - queue = &wdev->tx_queue[i].queue; - spin_lock_bh(&queue->lock); - if (!skb_queue_empty(queue)) - ret = false; - spin_unlock_bh(&queue->lock); - } - return ret; -} - -static bool hif_handle_tx_data(struct wfx_vif *wvif, struct sk_buff *skb, - struct wfx_queue *queue) -{ - struct hif_req_tx *req = wfx_skb_txreq(skb); - struct ieee80211_key_conf *hw_key = wfx_skb_tx_priv(skb)->hw_key; - struct ieee80211_hdr *frame = - (struct ieee80211_hdr *)(req->frame + req->data_flags.fc_offset); - - // FIXME: mac80211 is smart enough to handle BSS loss. Driver should not - // try to do anything about that. - if (ieee80211_is_nullfunc(frame->frame_control)) { - mutex_lock(&wvif->bss_loss_lock); - if (wvif->bss_loss_state) { - wvif->bss_loss_confirm_id = req->packet_id; - req->queue_id.queue_id = HIF_QUEUE_ID_VOICE; - } - mutex_unlock(&wvif->bss_loss_lock); - } - - // FIXME: identify the exact scenario matched by this condition. Does it - // happen yet? - if (ieee80211_has_protected(frame->frame_control) && - hw_key && hw_key->keyidx != wvif->wep_default_key_id && - (hw_key->cipher == WLAN_CIPHER_SUITE_WEP40 || - hw_key->cipher == WLAN_CIPHER_SUITE_WEP104)) { - wfx_tx_lock(wvif->wdev); - WARN_ON(wvif->wep_pending_skb); - wvif->wep_default_key_id = hw_key->keyidx; - wvif->wep_pending_skb = skb; - if (!schedule_work(&wvif->wep_key_work)) - wfx_tx_unlock(wvif->wdev); - return true; - } else { - return false; - } -} - -static int wfx_get_prio_queue(struct wfx_vif *wvif, - u32 tx_allowed_mask, int *total) -{ - static const int urgent = BIT(WFX_LINK_ID_AFTER_DTIM) | - BIT(WFX_LINK_ID_UAPSD); - const struct ieee80211_tx_queue_params *edca; - unsigned int score, best = -1; - int winner = -1; - int i; - - /* search for a winner using edca params */ - for (i = 0; i < IEEE80211_NUM_ACS; ++i) { - int queued; - - edca = &wvif->edca_params[i]; - queued = wfx_tx_queue_get_num_queued(&wvif->wdev->tx_queue[i], - tx_allowed_mask); - if (!queued) - continue; - *total += queued; - score = ((edca->aifs + edca->cw_min) << 16) + - ((edca->cw_max - edca->cw_min) * - (get_random_int() & 0xFFFF)); - if (score < best && (winner < 0 || i != 3)) { - best = score; - winner = i; - } - } - - /* override winner if bursting */ - if (winner >= 0 && wvif->wdev->tx_burst_idx >= 0 && - winner != wvif->wdev->tx_burst_idx && - !wfx_tx_queue_get_num_queued(&wvif->wdev->tx_queue[winner], - tx_allowed_mask & urgent) && - wfx_tx_queue_get_num_queued(&wvif->wdev->tx_queue[wvif->wdev->tx_burst_idx], tx_allowed_mask)) - winner = wvif->wdev->tx_burst_idx; - - return winner; -} - -static int wfx_tx_queue_mask_get(struct wfx_vif *wvif, - struct wfx_queue **queue_p, - u32 *tx_allowed_mask_p) -{ - int idx; - u32 tx_allowed_mask; - int total = 0; - - /* Search for unicast traffic */ - tx_allowed_mask = ~wvif->sta_asleep_mask; - tx_allowed_mask |= BIT(WFX_LINK_ID_UAPSD); - if (wvif->sta_asleep_mask) - tx_allowed_mask &= ~BIT(WFX_LINK_ID_AFTER_DTIM); - else - tx_allowed_mask |= BIT(WFX_LINK_ID_AFTER_DTIM); - idx = wfx_get_prio_queue(wvif, tx_allowed_mask, &total); - if (idx < 0) - return -ENOENT; - - *queue_p = &wvif->wdev->tx_queue[idx]; - *tx_allowed_mask_p = tx_allowed_mask; - return 0; -} - -struct hif_msg *wfx_tx_queues_get_after_dtim(struct wfx_vif *wvif) +bool wfx_tx_queues_has_cab(struct wfx_vif *wvif) { struct wfx_dev *wdev = wvif->wdev; - struct ieee80211_tx_info *tx_info; - struct hif_msg *hif; - struct sk_buff *skb; int i; - for (i = 0; i < IEEE80211_NUM_ACS; ++i) { - skb_queue_walk(&wdev->tx_queue[i].queue, skb) { - tx_info = IEEE80211_SKB_CB(skb); + if (wvif->vif->type != NL80211_IFTYPE_AP) + return false; + for (i = 0; i < IEEE80211_NUM_ACS; ++i) + // Note: since only AP can have mcast frames in queue and only + // one vif can be AP, all queued frames has same interface id + if (!skb_queue_empty_lockless(&wdev->tx_queue[i].cab)) + return true; + return false; +} + +static struct sk_buff *wfx_tx_queues_get_skb(struct wfx_dev *wdev) +{ + struct wfx_queue *sorted_queues[IEEE80211_NUM_ACS]; + struct wfx_vif *wvif; + struct hif_msg *hif; + struct sk_buff *skb; + int i, j; + + // bubble sort + for (i = 0; i < IEEE80211_NUM_ACS; i++) { + sorted_queues[i] = &wdev->tx_queue[i]; + for (j = i; j > 0; j--) + if (atomic_read(&sorted_queues[j]->pending_frames) > + atomic_read(&sorted_queues[j - 1]->pending_frames)) + swap(sorted_queues[j - 1], sorted_queues[j]); + } + wvif = NULL; + while ((wvif = wvif_iterate(wdev, wvif)) != NULL) { + if (!wvif->after_dtim_tx_allowed) + continue; + for (i = 0; i < IEEE80211_NUM_ACS; i++) { + skb = skb_dequeue(&sorted_queues[i]->cab); + if (!skb) + continue; + // Note: since only AP can have mcast frames in queue + // and only one vif can be AP, all queued frames has + // same interface id hif = (struct hif_msg *)skb->data; - if ((tx_info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) && - (hif->interface == wvif->id)) - return (struct hif_msg *)skb->data; + WARN_ON(hif->interface != wvif->id); + WARN_ON(sorted_queues[i] != + &wdev->tx_queue[skb_get_queue_mapping(skb)]); + atomic_inc(&sorted_queues[i]->pending_frames); + return skb; + } + // No more multicast to sent + wvif->after_dtim_tx_allowed = false; + schedule_work(&wvif->update_tim_work); + } + for (i = 0; i < IEEE80211_NUM_ACS; i++) { + skb = skb_dequeue(&sorted_queues[i]->normal); + if (skb) { + WARN_ON(sorted_queues[i] != + &wdev->tx_queue[skb_get_queue_mapping(skb)]); + atomic_inc(&sorted_queues[i]->pending_frames); + return skb; } } return NULL; @@ -475,90 +286,20 @@ struct hif_msg *wfx_tx_queues_get_after_dtim(struct wfx_vif *wvif) struct hif_msg *wfx_tx_queues_get(struct wfx_dev *wdev) { + struct wfx_tx_priv *tx_priv; struct sk_buff *skb; - struct hif_msg *hif = NULL; - struct wfx_queue *queue = NULL; - struct wfx_queue *vif_queue = NULL; - u32 tx_allowed_mask = 0; - u32 vif_tx_allowed_mask = 0; - struct wfx_vif *wvif; - int not_found; - int burst; - int i; if (atomic_read(&wdev->tx_lock)) return NULL; - wvif = NULL; - while ((wvif = wvif_iterate(wdev, wvif)) != NULL) { - if (wvif->after_dtim_tx_allowed) { - for (i = 0; i < IEEE80211_NUM_ACS; ++i) { - skb = wfx_tx_queue_get(wvif->wdev, - &wdev->tx_queue[i], - BIT(WFX_LINK_ID_AFTER_DTIM)); - if (skb) { - hif = (struct hif_msg *)skb->data; - // Cannot happen since only one vif can - // be AP at time - WARN_ON(wvif->id != hif->interface); - return hif; - } - } - // No more multicast to sent - wvif->after_dtim_tx_allowed = false; - schedule_work(&wvif->update_tim_work); - } - } - for (;;) { - int ret = -ENOENT; - int queue_num; - - wvif = NULL; - while ((wvif = wvif_iterate(wdev, wvif)) != NULL) { - spin_lock_bh(&wvif->ps_state_lock); - - not_found = wfx_tx_queue_mask_get(wvif, &vif_queue, - &vif_tx_allowed_mask); - - spin_unlock_bh(&wvif->ps_state_lock); - - if (!not_found) { - if (queue && queue != vif_queue) - dev_info(wdev->dev, "vifs disagree about queue priority\n"); - tx_allowed_mask |= vif_tx_allowed_mask; - queue = vif_queue; - ret = 0; - } - } - - if (ret) - return NULL; - - queue_num = queue - wdev->tx_queue; - - skb = wfx_tx_queue_get(wdev, queue, tx_allowed_mask); + skb = wfx_tx_queues_get_skb(wdev); if (!skb) - continue; - hif = (struct hif_msg *)skb->data; - wvif = wdev_to_wvif(wdev, hif->interface); - WARN_ON(!wvif); - - if (hif_handle_tx_data(wvif, skb, queue)) - continue; /* Handled by WSM */ - - /* allow bursting if txop is set */ - if (wvif->edca_params[queue_num].txop) - burst = wfx_tx_queue_get_num_queued(queue, tx_allowed_mask) + 1; - else - burst = 1; - - /* store index of bursting queue */ - if (burst > 1) - wdev->tx_burst_idx = queue_num; - else - wdev->tx_burst_idx = -1; - - return hif; + return NULL; + skb_queue_tail(&wdev->tx_pending, skb); + wake_up(&wdev->tx_dequeue); + tx_priv = wfx_skb_tx_priv(skb); + tx_priv->xmit_timestamp = ktime_get(); + return (struct hif_msg *)skb->data; } } diff --git a/drivers/staging/wfx/queue.h b/drivers/staging/wfx/queue.h index 90bb060d1204..0c3b7244498e 100644 --- a/drivers/staging/wfx/queue.h +++ b/drivers/staging/wfx/queue.h @@ -9,29 +9,15 @@ #define WFX_QUEUE_H #include - -#include "hif_api_cmd.h" - -#define WFX_MAX_STA_IN_AP_MODE 14 -#define WFX_LINK_ID_NO_ASSOC 15 -#define WFX_LINK_ID_AFTER_DTIM (WFX_LINK_ID_NO_ASSOC + 1) -#define WFX_LINK_ID_UAPSD (WFX_LINK_ID_NO_ASSOC + 2) -#define WFX_LINK_ID_MAX (WFX_LINK_ID_NO_ASSOC + 3) +#include struct wfx_dev; struct wfx_vif; struct wfx_queue { - struct sk_buff_head queue; - int tx_locked_cnt; - int link_map_cache[WFX_LINK_ID_MAX]; - u8 queue_id; -}; - -struct wfx_queue_stats { - int link_map_cache[WFX_LINK_ID_MAX]; - struct sk_buff_head pending; - wait_queue_head_t wait_link_id_empty; + struct sk_buff_head normal; + struct sk_buff_head cab; // Content After (DTIM) Beacon + atomic_t pending_frames; }; void wfx_tx_lock(struct wfx_dev *wdev); @@ -40,22 +26,18 @@ void wfx_tx_flush(struct wfx_dev *wdev); void wfx_tx_lock_flush(struct wfx_dev *wdev); void wfx_tx_queues_init(struct wfx_dev *wdev); -void wfx_tx_queues_deinit(struct wfx_dev *wdev); -void wfx_tx_queues_lock(struct wfx_dev *wdev); -void wfx_tx_queues_unlock(struct wfx_dev *wdev); -void wfx_tx_queues_clear(struct wfx_dev *wdev); -bool wfx_tx_queues_is_empty(struct wfx_dev *wdev); -void wfx_tx_queues_wait_empty_vif(struct wfx_vif *wvif); +void wfx_tx_queues_check_empty(struct wfx_dev *wdev); +bool wfx_tx_queues_has_cab(struct wfx_vif *wvif); +void wfx_tx_queues_put(struct wfx_dev *wdev, struct sk_buff *skb); struct hif_msg *wfx_tx_queues_get(struct wfx_dev *wdev); -struct hif_msg *wfx_tx_queues_get_after_dtim(struct wfx_vif *wvif); -void wfx_tx_queue_put(struct wfx_dev *wdev, struct wfx_queue *queue, - struct sk_buff *skb); -int wfx_tx_queue_get_num_queued(struct wfx_queue *queue, u32 link_id_map); +bool wfx_tx_queue_empty(struct wfx_dev *wdev, struct wfx_queue *queue, + int vif_id); +void wfx_tx_queue_drop(struct wfx_dev *wdev, struct wfx_queue *queue, + int vif_id, struct sk_buff_head *dropped); struct sk_buff *wfx_pending_get(struct wfx_dev *wdev, u32 packet_id); -int wfx_pending_remove(struct wfx_dev *wdev, struct sk_buff *skb); -int wfx_pending_requeue(struct wfx_dev *wdev, struct sk_buff *skb); +void wfx_pending_drop(struct wfx_dev *wdev, struct sk_buff_head *dropped); unsigned int wfx_pending_get_pkt_us_delay(struct wfx_dev *wdev, struct sk_buff *skb); void wfx_pending_dump_old_frames(struct wfx_dev *wdev, unsigned int limit_ms); diff --git a/drivers/staging/wfx/scan.c b/drivers/staging/wfx/scan.c index 9aa14331affd..57ea9997800b 100644 --- a/drivers/staging/wfx/scan.c +++ b/drivers/staging/wfx/scan.c @@ -88,18 +88,22 @@ void wfx_hw_scan_work(struct work_struct *work) struct ieee80211_scan_request *hw_req = wvif->scan_req; int chan_cur, ret; - mutex_lock(&wvif->scan_lock); mutex_lock(&wvif->wdev->conf_mutex); + mutex_lock(&wvif->scan_lock); + if (wvif->join_in_progress) { + dev_info(wvif->wdev->dev, "%s: abort in-progress REQ_JOIN", + __func__); + wfx_reset(wvif); + } update_probe_tmpl(wvif, &hw_req->req); - wfx_fwd_probe_req(wvif, true); chan_cur = 0; do { ret = send_scan_req(wvif, &hw_req->req, chan_cur); if (ret > 0) chan_cur += ret; } while (ret > 0 && chan_cur < hw_req->req.n_channels); - mutex_unlock(&wvif->wdev->conf_mutex); mutex_unlock(&wvif->scan_lock); + mutex_unlock(&wvif->wdev->conf_mutex); __ieee80211_scan_completed_compat(wvif->wdev->hw, ret < 0); } @@ -113,9 +117,6 @@ int wfx_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, if (vif->type == NL80211_IFTYPE_AP) return -EOPNOTSUPP; - if (wvif->state == WFX_STATE_PRE_STA) - return -EBUSY; - wvif->scan_req = hw_req; schedule_work(&wvif->scan_work); return 0; diff --git a/drivers/staging/wfx/sta.c b/drivers/staging/wfx/sta.c index 9d430346a58b..12e8a5b638f1 100644 --- a/drivers/staging/wfx/sta.c +++ b/drivers/staging/wfx/sta.c @@ -5,6 +5,7 @@ * Copyright (c) 2017-2019, Silicon Laboratories, Inc. * Copyright (c) 2010, ST-Ericsson */ +#include #include #include "sta.h" @@ -37,117 +38,32 @@ u32 wfx_rate_mask_to_hw(struct wfx_dev *wdev, u32 rates) return ret; } -static void __wfx_free_event_queue(struct list_head *list) +void wfx_cooling_timeout_work(struct work_struct *work) { - struct wfx_hif_event *event, *tmp; + struct wfx_dev *wdev = container_of(to_delayed_work(work), + struct wfx_dev, + cooling_timeout_work); - list_for_each_entry_safe(event, tmp, list, link) { - list_del(&event->link); - kfree(event); - } + wdev->chip_frozen = true; + wfx_tx_unlock(wdev); } -static void wfx_free_event_queue(struct wfx_vif *wvif) +void wfx_suspend_hot_dev(struct wfx_dev *wdev, enum sta_notify_cmd cmd) { - LIST_HEAD(list); - - spin_lock(&wvif->event_queue_lock); - list_splice_init(&wvif->event_queue, &list); - spin_unlock(&wvif->event_queue_lock); - - __wfx_free_event_queue(&list); -} - -void wfx_cqm_bssloss_sm(struct wfx_vif *wvif, int init, int good, int bad) -{ - int tx = 0; - - mutex_lock(&wvif->bss_loss_lock); - cancel_work_sync(&wvif->bss_params_work); - - if (init) { - schedule_delayed_work(&wvif->bss_loss_work, HZ); - wvif->bss_loss_state = 0; - - if (!atomic_read(&wvif->wdev->tx_lock)) - tx = 1; - } else if (good) { - cancel_delayed_work_sync(&wvif->bss_loss_work); - wvif->bss_loss_state = 0; - schedule_work(&wvif->bss_params_work); - } else if (bad) { - /* FIXME Should we just keep going until we time out? */ - if (wvif->bss_loss_state < 3) - tx = 1; + if (cmd == STA_NOTIFY_AWAKE) { + // Device recover normal temperature + if (cancel_delayed_work(&wdev->cooling_timeout_work)) + wfx_tx_unlock(wdev); } else { - cancel_delayed_work_sync(&wvif->bss_loss_work); - wvif->bss_loss_state = 0; + // Device is too hot + schedule_delayed_work(&wdev->cooling_timeout_work, 10 * HZ); + wfx_tx_lock(wdev); } - - /* Spit out a NULL packet to our AP if necessary */ - // FIXME: call ieee80211_beacon_loss/ieee80211_connection_loss instead - if (tx) { - struct sk_buff *skb; - struct ieee80211_hdr *hdr; - struct ieee80211_tx_control control = { }; - - wvif->bss_loss_state++; - - skb = ieee80211_nullfunc_get(wvif->wdev->hw, wvif->vif, false); - if (!skb) - goto end; - hdr = (struct ieee80211_hdr *)skb->data; - memset(IEEE80211_SKB_CB(skb), 0, - sizeof(*IEEE80211_SKB_CB(skb))); - IEEE80211_SKB_CB(skb)->control.vif = wvif->vif; - IEEE80211_SKB_CB(skb)->driver_rates[0].idx = 0; - IEEE80211_SKB_CB(skb)->driver_rates[0].count = 1; - IEEE80211_SKB_CB(skb)->driver_rates[1].idx = -1; - rcu_read_lock(); // protect control.sta - control.sta = ieee80211_find_sta(wvif->vif, hdr->addr1); - wfx_tx(wvif->wdev->hw, &control, skb); - rcu_read_unlock(); - } -end: - mutex_unlock(&wvif->bss_loss_lock); } -int wfx_fwd_probe_req(struct wfx_vif *wvif, bool enable) +static void wfx_filter_beacon(struct wfx_vif *wvif, bool filter_beacon) { - wvif->fwd_probe_req = enable; - return hif_set_rx_filter(wvif, wvif->filter_bssid, - wvif->fwd_probe_req); -} - -static int wfx_set_mcast_filter(struct wfx_vif *wvif, - struct wfx_grp_addr_table *fp) -{ - int i; - - // Temporary workaround for filters - return hif_set_data_filtering(wvif, false, true); - - if (!fp->enable) - return hif_set_data_filtering(wvif, false, true); - - for (i = 0; i < fp->num_addresses; i++) - hif_set_mac_addr_condition(wvif, i, fp->address_list[i]); - hif_set_uc_mc_bc_condition(wvif, 0, - HIF_FILTER_UNICAST | HIF_FILTER_BROADCAST); - hif_set_config_data_filter(wvif, true, 0, BIT(1), - BIT(fp->num_addresses) - 1); - hif_set_data_filtering(wvif, true, true); - - return 0; -} - -void wfx_update_filtering(struct wfx_vif *wvif) -{ - int ret; - int bf_enable; - int bf_count; - int n_filter_ies; - struct hif_ie_table_entry filter_ies[] = { + const struct hif_ie_table_entry filter_ies[] = { { .ie_id = WLAN_EID_VENDOR_SPECIFIC, .has_changed = 1, @@ -167,40 +83,33 @@ void wfx_update_filtering(struct wfx_vif *wvif) } }; - if (wvif->state == WFX_STATE_PASSIVE) - return; - - if (wvif->disable_beacon_filter) { - bf_enable = 0; - bf_count = 1; - n_filter_ies = 0; - } else if (wvif->vif->type != NL80211_IFTYPE_STATION) { - bf_enable = HIF_BEACON_FILTER_ENABLE | HIF_BEACON_FILTER_AUTO_ERP; - bf_count = 0; - n_filter_ies = 2; + if (!filter_beacon) { + hif_beacon_filter_control(wvif, 0, 1); } else { - bf_enable = HIF_BEACON_FILTER_ENABLE; - bf_count = 0; - n_filter_ies = 3; + hif_set_beacon_filter_table(wvif, 3, filter_ies); + hif_beacon_filter_control(wvif, HIF_BEACON_FILTER_ENABLE, 0); } - - ret = hif_set_rx_filter(wvif, wvif->filter_bssid, wvif->fwd_probe_req); - if (!ret) - ret = hif_set_beacon_filter_table(wvif, n_filter_ies, filter_ies); - if (!ret) - ret = hif_beacon_filter_control(wvif, bf_enable, bf_count); - if (!ret) - ret = wfx_set_mcast_filter(wvif, &wvif->mcast_filter); - if (ret) - dev_err(wvif->wdev->dev, "update filtering failed: %d\n", ret); } -static void wfx_update_filtering_work(struct work_struct *work) +static void wfx_filter_mcast(struct wfx_vif *wvif, bool filter_mcast) { - struct wfx_vif *wvif = container_of(work, struct wfx_vif, - update_filtering_work); + int i; - wfx_update_filtering(wvif); + // Temporary workaround for filters + hif_set_data_filtering(wvif, false, true); + return; + + if (!filter_mcast) { + hif_set_data_filtering(wvif, false, true); + return; + } + for (i = 0; i < wvif->filter_mcast_count; i++) + hif_set_mac_addr_condition(wvif, i, wvif->filter_mcast_addr[i]); + hif_set_uc_mc_bc_condition(wvif, 0, + HIF_FILTER_UNICAST | HIF_FILTER_BROADCAST); + hif_set_config_data_filter(wvif, true, 0, BIT(1), + BIT(wvif->filter_mcast_count) - 1); + hif_set_data_filtering(wvif, true, true); } u64 wfx_prepare_multicast(struct ieee80211_hw *hw, @@ -213,72 +122,127 @@ u64 wfx_prepare_multicast(struct ieee80211_hw *hw, int count = netdev_hw_addr_list_count(mc_list); while ((wvif = wvif_iterate(wdev, wvif)) != NULL) { - memset(&wvif->mcast_filter, 0x00, sizeof(wvif->mcast_filter)); - if (!count || - count > ARRAY_SIZE(wvif->mcast_filter.address_list)) + if (count > ARRAY_SIZE(wvif->filter_mcast_addr)) { + wvif->filter_mcast_count = 0; continue; + } + wvif->filter_mcast_count = count; i = 0; netdev_hw_addr_list_for_each(ha, mc_list) { - ether_addr_copy(wvif->mcast_filter.address_list[i], - ha->addr); + ether_addr_copy(wvif->filter_mcast_addr[i], ha->addr); i++; } - wvif->mcast_filter.enable = true; - wvif->mcast_filter.num_addresses = count; } return 0; } -void wfx_configure_filter(struct ieee80211_hw *hw, - unsigned int changed_flags, - unsigned int *total_flags, - u64 unused) +void wfx_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags, + unsigned int *total_flags, u64 unused) { struct wfx_vif *wvif = NULL; struct wfx_dev *wdev = hw->priv; + bool filter_bssid, filter_prbreq, filter_beacon, filter_mcast; - *total_flags &= FIF_OTHER_BSS | FIF_FCSFAIL | FIF_PROBE_REQ; + // Notes: + // - Probe responses (FIF_BCN_PRBRESP_PROMISC) are never filtered + // - PS-Poll (FIF_PSPOLL) are never filtered + // - RTS, CTS and Ack (FIF_CONTROL) are always filtered + // - Broken frames (FIF_FCSFAIL and FIF_PLCPFAIL) are always filtered + // - Firmware does (yet) allow to forward unicast traffic sent to + // other stations (aka. promiscuous mode) + *total_flags &= FIF_BCN_PRBRESP_PROMISC | FIF_ALLMULTI | FIF_OTHER_BSS | + FIF_PROBE_REQ | FIF_PSPOLL; + mutex_lock(&wdev->conf_mutex); while ((wvif = wvif_iterate(wdev, wvif)) != NULL) { mutex_lock(&wvif->scan_lock); - wvif->filter_bssid = (*total_flags & - (FIF_OTHER_BSS | FIF_PROBE_REQ)) ? 0 : 1; - wvif->disable_beacon_filter = !(*total_flags & FIF_PROBE_REQ); - wfx_fwd_probe_req(wvif, true); - wfx_update_filtering(wvif); + + // Note: FIF_BCN_PRBRESP_PROMISC covers probe response and + // beacons from other BSS + if (*total_flags & FIF_BCN_PRBRESP_PROMISC) + filter_beacon = false; + else + filter_beacon = true; + wfx_filter_beacon(wvif, filter_beacon); + + if (*total_flags & FIF_ALLMULTI) { + filter_mcast = false; + } else if (!wvif->filter_mcast_count) { + dev_dbg(wdev->dev, "disabling unconfigured multicast filter"); + filter_mcast = false; + } else { + filter_mcast = true; + } + wfx_filter_mcast(wvif, filter_mcast); + + if (*total_flags & FIF_OTHER_BSS) + filter_bssid = false; + else + filter_bssid = true; + + // In AP mode, chip can reply to probe request itself + if (*total_flags & FIF_PROBE_REQ && + wvif->vif->type == NL80211_IFTYPE_AP) { + dev_dbg(wdev->dev, "do not forward probe request in AP mode\n"); + *total_flags &= ~FIF_PROBE_REQ; + } + + if (*total_flags & FIF_PROBE_REQ) + filter_prbreq = false; + else + filter_prbreq = true; + hif_set_rx_filter(wvif, filter_bssid, filter_prbreq); + mutex_unlock(&wvif->scan_lock); } + mutex_unlock(&wdev->conf_mutex); } -static int wfx_update_pm(struct wfx_vif *wvif) +int wfx_get_ps_timeout(struct wfx_vif *wvif, bool *enable_ps) { - struct ieee80211_conf *conf = &wvif->wdev->hw->conf; - bool ps = conf->flags & IEEE80211_CONF_PS; - int ps_timeout = conf->dynamic_ps_timeout; struct ieee80211_channel *chan0 = NULL, *chan1 = NULL; + struct ieee80211_conf *conf = &wvif->wdev->hw->conf; - WARN_ON(conf->dynamic_ps_timeout < 0); - if (wvif->state != WFX_STATE_STA || !wvif->bss_params.aid) - return 0; - if (!ps) - ps_timeout = 0; - if (wvif->uapsd_mask) - ps_timeout = 0; - - // Kernel disable powersave when an AP is in use. In contrary, it is - // absolutely necessary to enable legacy powersave for WF200 if channels - // are differents. + WARN(!wvif->vif->bss_conf.assoc && enable_ps, + "enable_ps is reliable only if associated"); if (wdev_to_wvif(wvif->wdev, 0)) chan0 = wdev_to_wvif(wvif->wdev, 0)->vif->bss_conf.chandef.chan; if (wdev_to_wvif(wvif->wdev, 1)) chan1 = wdev_to_wvif(wvif->wdev, 1)->vif->bss_conf.chandef.chan; if (chan0 && chan1 && chan0->hw_value != chan1->hw_value && wvif->vif->type != NL80211_IFTYPE_AP) { - ps = true; - ps_timeout = 0; + // It is necessary to enable powersave if channels + // are differents. + if (enable_ps) + *enable_ps = true; + if (wvif->bss_not_support_ps_poll) + return 30; + else + return 0; } + if (enable_ps) + *enable_ps = wvif->vif->bss_conf.ps; + if (wvif->vif->bss_conf.assoc && wvif->vif->bss_conf.ps) + return conf->dynamic_ps_timeout; + else + return -1; +} + +int wfx_update_pm(struct wfx_vif *wvif) +{ + int ps_timeout; + bool ps; + + if (!wvif->vif->bss_conf.assoc) + return 0; + ps_timeout = wfx_get_ps_timeout(wvif, &ps); + if (!ps) + ps_timeout = 0; + WARN_ON(ps_timeout < 0); + if (wvif->uapsd_mask) + ps_timeout = 0; if (!wait_for_completion_timeout(&wvif->set_pm_mode_complete, TU_TO_JIFFIES(512))) @@ -287,18 +251,25 @@ static int wfx_update_pm(struct wfx_vif *wvif) return hif_set_pm(wvif, ps, ps_timeout); } +static void wfx_update_pm_work(struct work_struct *work) +{ + struct wfx_vif *wvif = container_of(work, struct wfx_vif, + update_pm_work); + + wfx_update_pm(wvif); +} + int wfx_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u16 queue, const struct ieee80211_tx_queue_params *params) { struct wfx_dev *wdev = hw->priv; - struct wfx_vif *wvif = (struct wfx_vif *) vif->drv_priv; + struct wfx_vif *wvif = (struct wfx_vif *)vif->drv_priv; int old_uapsd = wvif->uapsd_mask; WARN_ON(queue >= hw->queues); mutex_lock(&wdev->conf_mutex); assign_bit(queue, &wvif->uapsd_mask, params->uapsd); - memcpy(&wvif->edca_params[queue], params, sizeof(*params)); hif_set_edca_queue_params(wvif, queue, params); if (wvif->vif->type == NL80211_IFTYPE_STATION && old_uapsd != wvif->uapsd_mask) { @@ -319,32 +290,9 @@ int wfx_set_rts_threshold(struct ieee80211_hw *hw, u32 value) return 0; } -static int __wfx_flush(struct wfx_dev *wdev, bool drop) -{ - for (;;) { - if (drop) - wfx_tx_queues_clear(wdev); - if (wait_event_timeout(wdev->tx_queue_stats.wait_link_id_empty, - wfx_tx_queues_is_empty(wdev), - 2 * HZ) <= 0) - return -ETIMEDOUT; - wfx_tx_flush(wdev); - if (wfx_tx_queues_is_empty(wdev)) - return 0; - dev_warn(wdev->dev, "frames queued while flushing tx queues"); - } -} - -void wfx_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, - u32 queues, bool drop) -{ - // FIXME: only flush requested vif and queues - __wfx_flush(hw->priv, drop); -} - /* WSM callbacks */ -static void wfx_event_report_rssi(struct wfx_vif *wvif, u8 raw_rcpi_rssi) +void wfx_event_report_rssi(struct wfx_vif *wvif, u8 raw_rcpi_rssi) { /* RSSI: signed Q8.0, RCPI: unsigned Q7.1 * RSSI = RCPI / 2 - 110 @@ -360,100 +308,23 @@ static void wfx_event_report_rssi(struct wfx_vif *wvif, u8 raw_rcpi_rssi) ieee80211_cqm_rssi_notify(wvif->vif, cqm_evt, rcpi_rssi, GFP_KERNEL); } -static void wfx_event_handler_work(struct work_struct *work) +static void wfx_beacon_loss_work(struct work_struct *work) { - struct wfx_vif *wvif = - container_of(work, struct wfx_vif, event_handler_work); - struct wfx_hif_event *event; + struct wfx_vif *wvif = container_of(to_delayed_work(work), + struct wfx_vif, beacon_loss_work); + struct ieee80211_bss_conf *bss_conf = &wvif->vif->bss_conf; - LIST_HEAD(list); - - spin_lock(&wvif->event_queue_lock); - list_splice_init(&wvif->event_queue, &list); - spin_unlock(&wvif->event_queue_lock); - - list_for_each_entry(event, &list, link) { - switch (event->evt.event_id) { - case HIF_EVENT_IND_BSSLOST: - cancel_work_sync(&wvif->unjoin_work); - mutex_lock(&wvif->scan_lock); - wfx_cqm_bssloss_sm(wvif, 1, 0, 0); - mutex_unlock(&wvif->scan_lock); - break; - case HIF_EVENT_IND_BSSREGAINED: - wfx_cqm_bssloss_sm(wvif, 0, 0, 0); - cancel_work_sync(&wvif->unjoin_work); - break; - case HIF_EVENT_IND_RCPI_RSSI: - wfx_event_report_rssi(wvif, - event->evt.event_data.rcpi_rssi); - break; - case HIF_EVENT_IND_PS_MODE_ERROR: - dev_warn(wvif->wdev->dev, - "error while processing power save request\n"); - break; - default: - dev_warn(wvif->wdev->dev, - "unhandled event indication: %.2x\n", - event->evt.event_id); - break; - } - } - __wfx_free_event_queue(&list); + ieee80211_beacon_loss(wvif->vif); + schedule_delayed_work(to_delayed_work(work), + msecs_to_jiffies(bss_conf->beacon_int)); } -static void wfx_bss_loss_work(struct work_struct *work) +void wfx_set_default_unicast_key(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, int idx) { - struct wfx_vif *wvif = container_of(work, struct wfx_vif, - bss_loss_work.work); + struct wfx_vif *wvif = (struct wfx_vif *)vif->drv_priv; - ieee80211_connection_loss(wvif->vif); -} - -static void wfx_bss_params_work(struct work_struct *work) -{ - struct wfx_vif *wvif = container_of(work, struct wfx_vif, - bss_params_work); - - mutex_lock(&wvif->wdev->conf_mutex); - wvif->bss_params.bss_flags.lost_count_only = 1; - hif_set_bss_params(wvif, &wvif->bss_params); - wvif->bss_params.bss_flags.lost_count_only = 0; - mutex_unlock(&wvif->wdev->conf_mutex); -} - -static void wfx_do_unjoin(struct wfx_vif *wvif) -{ - mutex_lock(&wvif->wdev->conf_mutex); - - if (!wvif->state) - goto done; - - if (wvif->state == WFX_STATE_AP) - goto done; - - cancel_work_sync(&wvif->update_filtering_work); - wvif->state = WFX_STATE_PASSIVE; - - /* Unjoin is a reset. */ - wfx_tx_flush(wvif->wdev); - hif_keep_alive_period(wvif, 0); - hif_reset(wvif, false); - wfx_tx_policy_init(wvif); - hif_set_macaddr(wvif, wvif->vif->addr); - wfx_free_event_queue(wvif); - cancel_work_sync(&wvif->event_handler_work); - wfx_cqm_bssloss_sm(wvif, 0, 0, 0); - - /* Disable Block ACKs */ - hif_set_block_ack_policy(wvif, 0, 0); - - wvif->disable_beacon_filter = false; - wfx_update_filtering(wvif); - memset(&wvif->bss_params, 0, sizeof(wvif->bss_params)); - -done: - mutex_unlock(&wvif->wdev->conf_mutex); + hif_wep_default_key_id(wvif, idx); } static void wfx_set_mfp(struct wfx_vif *wvif, @@ -472,8 +343,7 @@ static void wfx_set_mfp(struct wfx_vif *wvif, rcu_read_lock(); if (bss) - ptr = (const u16 *) ieee80211_bss_get_ie(bss, - WLAN_EID_RSN); + ptr = (const u16 *)ieee80211_bss_get_ie(bss, WLAN_EID_RSN); if (ptr) { ptr += pairwise_cipher_suite_count_offset; @@ -487,6 +357,24 @@ static void wfx_set_mfp(struct wfx_vif *wvif, hif_set_mfp(wvif, mfpc, mfpr); } +void wfx_reset(struct wfx_vif *wvif) +{ + struct wfx_dev *wdev = wvif->wdev; + + wfx_tx_lock_flush(wdev); + hif_reset(wvif, false); + wfx_tx_policy_init(wvif); + if (wvif_count(wdev) <= 1) + hif_set_block_ack_policy(wvif, 0xFF, 0xFF); + wfx_tx_unlock(wdev); + wvif->join_in_progress = false; + wvif->bss_not_support_ps_poll = false; + cancel_delayed_work_sync(&wvif->beacon_loss_work); + wvif = NULL; + while ((wvif = wvif_iterate(wdev, wvif)) != NULL) + wfx_update_pm(wvif); +} + static void wfx_do_join(struct wfx_vif *wvif) { int ret; @@ -498,9 +386,6 @@ static void wfx_do_join(struct wfx_vif *wvif) wfx_tx_lock_flush(wvif->wdev); - if (wvif->state) - wfx_do_unjoin(wvif); - bss = cfg80211_get_bss(wvif->wdev->hw->wiphy, wvif->channel, conf->bssid, NULL, 0, IEEE80211_BSS_TYPE_ANY, IEEE80211_PRIVACY_ANY); @@ -509,109 +394,72 @@ static void wfx_do_join(struct wfx_vif *wvif) return; } - mutex_lock(&wvif->wdev->conf_mutex); - - /* Sanity check beacon interval */ - if (!wvif->beacon_int) - wvif->beacon_int = 1; - rcu_read_lock(); // protect ssidie - if (!conf->ibss_joined) + if (bss) ssidie = ieee80211_bss_get_ie(bss, WLAN_EID_SSID); if (ssidie) { ssidlen = ssidie[1]; - memcpy(ssid, &ssidie[2], ssidie[1]); + if (ssidlen > IEEE80211_MAX_SSID_LEN) + ssidlen = IEEE80211_MAX_SSID_LEN; + memcpy(ssid, &ssidie[2], ssidlen); } rcu_read_unlock(); - wfx_tx_flush(wvif->wdev); - - if (wvif_count(wvif->wdev) <= 1) - hif_set_block_ack_policy(wvif, 0xFF, 0xFF); - wfx_set_mfp(wvif, bss); + cfg80211_put_bss(wvif->wdev->hw->wiphy, bss); - wvif->wdev->tx_burst_idx = -1; + wvif->join_in_progress = true; ret = hif_join(wvif, conf, wvif->channel, ssid, ssidlen); if (ret) { ieee80211_connection_loss(wvif->vif); - wvif->join_complete_status = -1; - /* Tx lock still held, unjoin will clear it. */ - if (!schedule_work(&wvif->unjoin_work)) - wfx_tx_unlock(wvif->wdev); + wfx_reset(wvif); } else { - wvif->join_complete_status = 0; - if (wvif->vif->type == NL80211_IFTYPE_ADHOC) - wvif->state = WFX_STATE_IBSS; - else - wvif->state = WFX_STATE_PRE_STA; - wfx_tx_unlock(wvif->wdev); - - /* Upload keys */ - wfx_upload_keys(wvif); - /* Due to beacon filtering it is possible that the * AP's beacon is not known for the mac80211 stack. * Disable filtering temporary to make sure the stack * receives at least one */ - wvif->disable_beacon_filter = true; + wfx_filter_beacon(wvif, false); } - wfx_update_filtering(wvif); - - mutex_unlock(&wvif->wdev->conf_mutex); - if (bss) - cfg80211_put_bss(wvif->wdev->hw->wiphy, bss); -} - -static void wfx_unjoin_work(struct work_struct *work) -{ - struct wfx_vif *wvif = container_of(work, struct wfx_vif, unjoin_work); - - wfx_do_unjoin(wvif); wfx_tx_unlock(wvif->wdev); } int wfx_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_sta *sta) { - struct wfx_vif *wvif = (struct wfx_vif *) vif->drv_priv; - struct wfx_sta_priv *sta_priv = (struct wfx_sta_priv *) &sta->drv_priv; + struct wfx_vif *wvif = (struct wfx_vif *)vif->drv_priv; + struct wfx_sta_priv *sta_priv = (struct wfx_sta_priv *)&sta->drv_priv; spin_lock_init(&sta_priv->lock); sta_priv->vif_id = wvif->id; - // FIXME: in station mode, the current API interprets new link-id as a - // tdls peer. - if (vif->type == NL80211_IFTYPE_STATION) + // In station mode, the firmware interprets new link-id as a TDLS peer. + if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) return 0; sta_priv->link_id = ffz(wvif->link_id_map); wvif->link_id_map |= BIT(sta_priv->link_id); WARN_ON(!sta_priv->link_id); - WARN_ON(sta_priv->link_id >= WFX_MAX_STA_IN_AP_MODE); + WARN_ON(sta_priv->link_id >= HIF_LINK_ID_MAX); hif_map_link(wvif, sta->addr, 0, sta_priv->link_id); - spin_lock_bh(&wvif->ps_state_lock); - if ((sta->uapsd_queues & IEEE80211_WMM_IE_STA_QOSINFO_AC_MASK) == - IEEE80211_WMM_IE_STA_QOSINFO_AC_MASK) - wvif->sta_asleep_mask |= BIT(sta_priv->link_id); - spin_unlock_bh(&wvif->ps_state_lock); return 0; } int wfx_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_sta *sta) { - struct wfx_vif *wvif = (struct wfx_vif *) vif->drv_priv; - struct wfx_sta_priv *sta_priv = (struct wfx_sta_priv *) &sta->drv_priv; + struct wfx_vif *wvif = (struct wfx_vif *)vif->drv_priv; + struct wfx_sta_priv *sta_priv = (struct wfx_sta_priv *)&sta->drv_priv; int i; for (i = 0; i < ARRAY_SIZE(sta_priv->buffered); i++) if (sta_priv->buffered[i]) - dev_warn(wvif->wdev->dev, "release station while %d pending frame on queue %d", - sta_priv->buffered[i], i); - // FIXME: see note in wfx_sta_add() - if (vif->type == NL80211_IFTYPE_STATION) + // Not an error if paired with trace in + // wfx_tx_update_sta() + dev_dbg(wvif->wdev->dev, "release station while %d pending frame on queue %d", + sta_priv->buffered[i], i); + // See note in wfx_sta_add() + if (!sta_priv->link_id) return 0; // FIXME add a mutex? hif_map_link(wvif, sta->addr, 1, sta_priv->link_id); @@ -619,50 +467,10 @@ int wfx_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, return 0; } -static int wfx_start_ap(struct wfx_vif *wvif) -{ - int ret; - - wvif->beacon_int = wvif->vif->bss_conf.beacon_int; - wvif->wdev->tx_burst_idx = -1; - ret = hif_start(wvif, &wvif->vif->bss_conf, wvif->channel); - if (ret) - return ret; - ret = wfx_upload_keys(wvif); - if (ret) - return ret; - if (wvif_count(wvif->wdev) <= 1) - hif_set_block_ack_policy(wvif, 0xFF, 0xFF); - wvif->state = WFX_STATE_AP; - wfx_update_filtering(wvif); - return 0; -} - -static int wfx_update_beaconing(struct wfx_vif *wvif) -{ - if (wvif->vif->type != NL80211_IFTYPE_AP) - return 0; - if (wvif->state == WFX_STATE_AP && - wvif->beacon_int == wvif->vif->bss_conf.beacon_int) - return 0; - wfx_tx_lock_flush(wvif->wdev); - hif_reset(wvif, false); - wfx_tx_policy_init(wvif); - wvif->state = WFX_STATE_PASSIVE; - wfx_start_ap(wvif); - wfx_tx_unlock(wvif->wdev); - return 0; -} - static int wfx_upload_ap_templates(struct wfx_vif *wvif) { struct sk_buff *skb; - if (wvif->vif->type == NL80211_IFTYPE_STATION || - wvif->vif->type == NL80211_IFTYPE_MONITOR || - wvif->vif->type == NL80211_IFTYPE_UNSPECIFIED) - return 0; - skb = ieee80211_beacon_get(wvif->wdev->hw, wvif->vif); if (!skb) return -ENOMEM; @@ -679,52 +487,77 @@ static int wfx_upload_ap_templates(struct wfx_vif *wvif) return 0; } +int wfx_start_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif) +{ + struct wfx_vif *wvif = (struct wfx_vif *)vif->drv_priv; + struct wfx_dev *wdev = wvif->wdev; + int ret; + + wvif = NULL; + while ((wvif = wvif_iterate(wdev, wvif)) != NULL) + wfx_update_pm(wvif); + wvif = (struct wfx_vif *)vif->drv_priv; + wfx_upload_ap_templates(wvif); + ret = hif_start(wvif, &vif->bss_conf, wvif->channel); + if (ret > 0) + return -EIO; + return ret; +} + +void wfx_stop_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif) +{ + struct wfx_vif *wvif = (struct wfx_vif *)vif->drv_priv; + + wfx_reset(wvif); +} + static void wfx_join_finalize(struct wfx_vif *wvif, struct ieee80211_bss_conf *info) { - struct ieee80211_sta *sta = NULL; - - wvif->beacon_int = info->beacon_int; - rcu_read_lock(); // protect sta - if (info->bssid && !info->ibss_joined) - sta = ieee80211_find_sta(wvif->vif, info->bssid); - if (sta) - wvif->bss_params.operational_rate_set = - wfx_rate_mask_to_hw(wvif->wdev, sta->supp_rates[wvif->channel->band]); - else - wvif->bss_params.operational_rate_set = -1; - rcu_read_unlock(); - if (sta && - info->ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT) - hif_dual_cts_protection(wvif, true); - else - hif_dual_cts_protection(wvif, false); - - wfx_cqm_bssloss_sm(wvif, 0, 0, 0); - cancel_work_sync(&wvif->unjoin_work); - - wvif->bss_params.beacon_lost_count = 20; - wvif->bss_params.aid = info->aid; - + wvif->join_in_progress = false; hif_set_association_mode(wvif, info); - - if (!info->ibss_joined) { - hif_keep_alive_period(wvif, 30 /* sec */); - hif_set_bss_params(wvif, &wvif->bss_params); - hif_set_beacon_wakeup_period(wvif, info->dtim_period, - info->dtim_period); - wfx_update_pm(wvif); - } + hif_keep_alive_period(wvif, 0); + // beacon_loss_count is defined to 7 in net/mac80211/mlme.c. Let's use + // the same value. + hif_set_bss_params(wvif, info->aid, 7); + hif_set_beacon_wakeup_period(wvif, 1, 1); + wfx_update_pm(wvif); } -void wfx_bss_info_changed(struct ieee80211_hw *hw, - struct ieee80211_vif *vif, - struct ieee80211_bss_conf *info, - u32 changed) +int wfx_join_ibss(struct ieee80211_hw *hw, struct ieee80211_vif *vif) +{ + struct wfx_vif *wvif = (struct wfx_vif *)vif->drv_priv; + + wfx_upload_ap_templates(wvif); + wfx_do_join(wvif); + return 0; +} + +void wfx_leave_ibss(struct ieee80211_hw *hw, struct ieee80211_vif *vif) +{ + struct wfx_vif *wvif = (struct wfx_vif *)vif->drv_priv; + + wfx_reset(wvif); +} + +static void wfx_enable_beacon(struct wfx_vif *wvif, bool enable) +{ + // Driver has Content After DTIM Beacon in queue. Driver is waiting for + // a signal from the firmware. Since we are going to stop to send + // beacons, this signal will never happens. See also + // wfx_suspend_resume_mc() + if (!enable && wfx_tx_queues_has_cab(wvif)) { + wvif->after_dtim_tx_allowed = true; + wfx_bh_request_tx(wvif->wdev); + } + hif_beacon_transmit(wvif, enable); +} + +void wfx_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif, + struct ieee80211_bss_conf *info, u32 changed) { struct wfx_dev *wdev = hw->priv; - struct wfx_vif *wvif = (struct wfx_vif *) vif->drv_priv; - bool do_join = false; + struct wfx_vif *wvif = (struct wfx_vif *)vif->drv_priv; int i; mutex_lock(&wdev->conf_mutex); @@ -742,92 +575,52 @@ void wfx_bss_info_changed(struct ieee80211_hw *hw, } } - if (changed & BSS_CHANGED_BEACON || - changed & BSS_CHANGED_AP_PROBE_RESP || - changed & BSS_CHANGED_BSSID || - changed & BSS_CHANGED_SSID || - changed & BSS_CHANGED_IBSS) { - wvif->beacon_int = info->beacon_int; - wfx_update_beaconing(wvif); - wfx_upload_ap_templates(wvif); - wfx_fwd_probe_req(wvif, false); + if (changed & BSS_CHANGED_BASIC_RATES || + changed & BSS_CHANGED_BEACON_INT || + changed & BSS_CHANGED_BSSID) { + if (vif->type == NL80211_IFTYPE_STATION) + wfx_do_join(wvif); } - if (changed & BSS_CHANGED_BEACON_ENABLED && - wvif->state != WFX_STATE_IBSS) - hif_beacon_transmit(wvif, info->enable_beacon); + if (changed & BSS_CHANGED_AP_PROBE_RESP || + changed & BSS_CHANGED_BEACON) + wfx_upload_ap_templates(wvif); - if (changed & BSS_CHANGED_BEACON_INFO) + if (changed & BSS_CHANGED_BEACON_ENABLED) + wfx_enable_beacon(wvif, info->enable_beacon); + + if (changed & BSS_CHANGED_BEACON_INFO) { + if (vif->type != NL80211_IFTYPE_STATION) + dev_warn(wdev->dev, "%s: misunderstood change: BEACON_INFO\n", + __func__); hif_set_beacon_wakeup_period(wvif, info->dtim_period, info->dtim_period); + // We temporary forwarded beacon for join process. It is now no + // more necessary. + wfx_filter_beacon(wvif, true); + } - /* assoc/disassoc, or maybe AID changed */ if (changed & BSS_CHANGED_ASSOC) { - wfx_tx_lock_flush(wdev); - wvif->wep_default_key_id = -1; - wfx_tx_unlock(wdev); + if (info->assoc || info->ibss_joined) + wfx_join_finalize(wvif, info); + else if (!info->assoc && vif->type == NL80211_IFTYPE_STATION) + wfx_reset(wvif); + else + dev_warn(wdev->dev, "%s: misunderstood change: ASSOC\n", + __func__); } - if (changed & BSS_CHANGED_ASSOC && !info->assoc && - (wvif->state == WFX_STATE_STA || wvif->state == WFX_STATE_IBSS)) { - /* Shedule unjoin work */ - wfx_tx_lock(wdev); - if (!schedule_work(&wvif->unjoin_work)) - wfx_tx_unlock(wdev); - } else { - if (changed & BSS_CHANGED_BEACON_INT) { - if (info->ibss_joined) - do_join = true; - else if (wvif->state == WFX_STATE_AP) - wfx_update_beaconing(wvif); - } - - if (changed & BSS_CHANGED_BSSID) - do_join = true; - - if (changed & BSS_CHANGED_ASSOC || - changed & BSS_CHANGED_BSSID || - changed & BSS_CHANGED_IBSS || - changed & BSS_CHANGED_BASIC_RATES || - changed & BSS_CHANGED_HT) { - if (info->assoc) { - if (wvif->state < WFX_STATE_PRE_STA) { - ieee80211_connection_loss(vif); - mutex_unlock(&wdev->conf_mutex); - return; - } else if (wvif->state == WFX_STATE_PRE_STA) { - wvif->state = WFX_STATE_STA; - } - } else { - do_join = true; - } - - if (info->assoc || info->ibss_joined) - wfx_join_finalize(wvif, info); - else - memset(&wvif->bss_params, 0, - sizeof(wvif->bss_params)); - } - } - - if (changed & BSS_CHANGED_ASSOC || - changed & BSS_CHANGED_ERP_CTS_PROT || - changed & BSS_CHANGED_ERP_PREAMBLE) { - u8 erp_ie[3] = { WLAN_EID_ERP_INFO, 1, 0 }; + if (changed & BSS_CHANGED_KEEP_ALIVE) + hif_keep_alive_period(wvif, info->max_idle_period * + USEC_PER_TU / USEC_PER_MSEC); + if (changed & BSS_CHANGED_ERP_CTS_PROT) hif_erp_use_protection(wvif, info->use_cts_prot); - if (info->use_cts_prot) - erp_ie[2] |= WLAN_ERP_USE_PROTECTION; - if (info->use_short_preamble) - erp_ie[2] |= WLAN_ERP_BARKER_PREAMBLE; - if (wvif->vif->type != NL80211_IFTYPE_STATION) - hif_update_ie_beacon(wvif, erp_ie, sizeof(erp_ie)); - } - if (changed & BSS_CHANGED_ASSOC || changed & BSS_CHANGED_ERP_SLOT) + if (changed & BSS_CHANGED_ERP_SLOT) hif_slot_time(wvif, info->use_short_slot ? 9 : 20); - if (changed & BSS_CHANGED_ASSOC || changed & BSS_CHANGED_CQM) + if (changed & BSS_CHANGED_CQM) hif_set_rcpi_rssi_threshold(wvif, info->cqm_rssi_thold, info->cqm_rssi_hyst); @@ -838,31 +631,6 @@ void wfx_bss_info_changed(struct ieee80211_hw *hw, wfx_update_pm(wvif); mutex_unlock(&wdev->conf_mutex); - - if (do_join) - wfx_do_join(wvif); -} - -static void wfx_ps_notify_sta(struct wfx_vif *wvif, - enum sta_notify_cmd notify_cmd, int link_id) -{ - spin_lock_bh(&wvif->ps_state_lock); - if (notify_cmd == STA_NOTIFY_SLEEP) - wvif->sta_asleep_mask |= BIT(link_id); - else // notify_cmd == STA_NOTIFY_AWAKE - wvif->sta_asleep_mask &= ~BIT(link_id); - spin_unlock_bh(&wvif->ps_state_lock); - if (notify_cmd == STA_NOTIFY_AWAKE) - wfx_bh_request_tx(wvif->wdev); -} - -void wfx_sta_notify(struct ieee80211_hw *hw, struct ieee80211_vif *vif, - enum sta_notify_cmd notify_cmd, struct ieee80211_sta *sta) -{ - struct wfx_vif *wvif = (struct wfx_vif *) vif->drv_priv; - struct wfx_sta_priv *sta_priv = (struct wfx_sta_priv *) &sta->drv_priv; - - wfx_ps_notify_sta(wvif, notify_cmd, sta_priv->link_id); } static int wfx_update_tim(struct wfx_vif *wvif) @@ -873,10 +641,8 @@ static int wfx_update_tim(struct wfx_vif *wvif) skb = ieee80211_beacon_get_tim(wvif->wdev->hw, wvif->vif, &tim_offset, &tim_length); - if (!skb) { - __wfx_flush(wvif->wdev, true); + if (!skb) return -ENOENT; - } tim_ptr = skb->data + tim_offset; if (tim_offset && tim_length >= 6) { @@ -886,7 +652,7 @@ static int wfx_update_tim(struct wfx_vif *wvif) tim_ptr[2] = 0; /* Set/reset aid0 bit */ - if (wfx_tx_queues_get_after_dtim(wvif)) + if (wfx_tx_queues_has_cab(wvif)) tim_ptr[4] |= 1; else tim_ptr[4] &= ~1; @@ -917,7 +683,9 @@ int wfx_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set) void wfx_suspend_resume_mc(struct wfx_vif *wvif, enum sta_notify_cmd notify_cmd) { - WARN(!wfx_tx_queues_get_after_dtim(wvif), "incorrect sequence"); + if (notify_cmd != STA_NOTIFY_AWAKE) + return; + WARN(!wfx_tx_queues_has_cab(wvif), "incorrect sequence"); WARN(wvif->after_dtim_tx_allowed, "incorrect sequence"); wvif->after_dtim_tx_allowed = true; wfx_bh_request_tx(wvif->wdev); @@ -958,7 +726,7 @@ void wfx_change_chanctx(struct ieee80211_hw *hw, int wfx_assign_vif_chanctx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_chanctx_conf *conf) { - struct wfx_vif *wvif = (struct wfx_vif *) vif->drv_priv; + struct wfx_vif *wvif = (struct wfx_vif *)vif->drv_priv; struct ieee80211_channel *ch = conf->def.chan; WARN(wvif->channel, "channel overwrite"); @@ -971,7 +739,7 @@ void wfx_unassign_vif_chanctx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_chanctx_conf *conf) { - struct wfx_vif *wvif = (struct wfx_vif *) vif->drv_priv; + struct wfx_vif *wvif = (struct wfx_vif *)vif->drv_priv; struct ieee80211_channel *ch = conf->def.chan; WARN(wvif->channel != ch, "channel mismatch"); @@ -987,7 +755,7 @@ int wfx_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif) { int i, ret = 0; struct wfx_dev *wdev = hw->priv; - struct wfx_vif *wvif = (struct wfx_vif *) vif->drv_priv; + struct wfx_vif *wvif = (struct wfx_vif *)vif->drv_priv; vif->driver_flags |= IEEE80211_VIF_BEACON_FILTER | IEEE80211_VIF_SUPPORTS_UAPSD | @@ -1021,33 +789,18 @@ int wfx_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif) wvif->wdev = wdev; wvif->link_id_map = 1; // link-id 0 is reserved for multicast - spin_lock_init(&wvif->ps_state_lock); INIT_WORK(&wvif->update_tim_work, wfx_update_tim_work); - - memset(&wvif->bss_params, 0, sizeof(wvif->bss_params)); - - mutex_init(&wvif->bss_loss_lock); - INIT_DELAYED_WORK(&wvif->bss_loss_work, wfx_bss_loss_work); - - wvif->wep_default_key_id = -1; - INIT_WORK(&wvif->wep_key_work, wfx_wep_key_work); - - spin_lock_init(&wvif->event_queue_lock); - INIT_LIST_HEAD(&wvif->event_queue); - INIT_WORK(&wvif->event_handler_work, wfx_event_handler_work); + INIT_DELAYED_WORK(&wvif->beacon_loss_work, wfx_beacon_loss_work); init_completion(&wvif->set_pm_mode_complete); complete(&wvif->set_pm_mode_complete); - INIT_WORK(&wvif->update_filtering_work, wfx_update_filtering_work); - INIT_WORK(&wvif->bss_params_work, wfx_bss_params_work); - INIT_WORK(&wvif->unjoin_work, wfx_unjoin_work); + INIT_WORK(&wvif->update_pm_work, wfx_update_pm_work); INIT_WORK(&wvif->tx_policy_upload_work, wfx_tx_policy_upload_work); mutex_init(&wvif->scan_lock); init_completion(&wvif->scan_complete); INIT_WORK(&wvif->scan_work, wfx_hw_scan_work); - INIT_WORK(&wvif->tx_policy_upload_work, wfx_tx_policy_upload_work); mutex_unlock(&wdev->conf_mutex); hif_set_macaddr(wvif, vif->addr); @@ -1060,50 +813,25 @@ int wfx_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif) hif_set_block_ack_policy(wvif, 0xFF, 0xFF); else hif_set_block_ack_policy(wvif, 0x00, 0x00); - // Combo force powersave mode. We can re-enable it now - ret = wfx_update_pm(wvif); } return ret; } -void wfx_remove_interface(struct ieee80211_hw *hw, - struct ieee80211_vif *vif) +void wfx_remove_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif) { struct wfx_dev *wdev = hw->priv; - struct wfx_vif *wvif = (struct wfx_vif *) vif->drv_priv; + struct wfx_vif *wvif = (struct wfx_vif *)vif->drv_priv; wait_for_completion_timeout(&wvif->set_pm_mode_complete, msecs_to_jiffies(300)); mutex_lock(&wdev->conf_mutex); WARN(wvif->link_id_map != 1, "corrupted state"); - switch (wvif->state) { - case WFX_STATE_PRE_STA: - case WFX_STATE_STA: - case WFX_STATE_IBSS: - wfx_tx_lock_flush(wdev); - if (!schedule_work(&wvif->unjoin_work)) - wfx_tx_unlock(wdev); - break; - case WFX_STATE_AP: - wvif->sta_asleep_mask = 0; - /* reset.link_id = 0; */ - hif_reset(wvif, false); - break; - default: - break; - } - wvif->state = WFX_STATE_PASSIVE; - wfx_tx_queues_wait_empty_vif(wvif); - wfx_tx_unlock(wdev); - - /* FIXME: In add to reset MAC address, try to reset interface */ + hif_reset(wvif, false); hif_set_macaddr(wvif, NULL); + wfx_tx_policy_init(wvif); - wfx_cqm_bssloss_sm(wvif, 0, 0, 0); - cancel_work_sync(&wvif->unjoin_work); - wfx_free_event_queue(wvif); - + cancel_delayed_work_sync(&wvif->beacon_loss_work); wdev->vif[wvif->id] = NULL; wvif->vif = NULL; @@ -1115,8 +843,6 @@ void wfx_remove_interface(struct ieee80211_hw *hw, hif_set_block_ack_policy(wvif, 0xFF, 0xFF); else hif_set_block_ack_policy(wvif, 0x00, 0x00); - // Combo force powersave mode. We can re-enable it now - wfx_update_pm(wvif); } } @@ -1129,10 +855,5 @@ void wfx_stop(struct ieee80211_hw *hw) { struct wfx_dev *wdev = hw->priv; - wfx_tx_lock_flush(wdev); - mutex_lock(&wdev->conf_mutex); - wfx_tx_queues_clear(wdev); - mutex_unlock(&wdev->conf_mutex); - wfx_tx_unlock(wdev); - WARN(atomic_read(&wdev->tx_lock), "tx_lock is locked"); + wfx_tx_queues_check_empty(wdev); } diff --git a/drivers/staging/wfx/sta.h b/drivers/staging/wfx/sta.h index cf99a8a74a81..8a20ad9ae017 100644 --- a/drivers/staging/wfx/sta.h +++ b/drivers/staging/wfx/sta.h @@ -10,34 +10,13 @@ #include -#include "hif_api_cmd.h" - struct wfx_dev; struct wfx_vif; -enum wfx_state { - WFX_STATE_PASSIVE = 0, - WFX_STATE_PRE_STA, - WFX_STATE_STA, - WFX_STATE_IBSS, - WFX_STATE_AP, -}; - -struct wfx_hif_event { - struct list_head link; - struct hif_ind_event evt; -}; - -struct wfx_grp_addr_table { - bool enable; - int num_addresses; - u8 address_list[8][ETH_ALEN]; -}; - struct wfx_sta_priv { int link_id; int vif_id; - u8 buffered[IEEE80211_NUM_TIDS]; + int buffered[IEEE80211_NUM_TIDS]; // Ensure atomicity of "buffered" and calls to ieee80211_sta_set_buffered() spinlock_t lock; }; @@ -47,6 +26,8 @@ int wfx_start(struct ieee80211_hw *hw); void wfx_stop(struct ieee80211_hw *hw); int wfx_config(struct ieee80211_hw *hw, u32 changed); int wfx_set_rts_threshold(struct ieee80211_hw *hw, u32 value); +void wfx_set_default_unicast_key(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, int idx); u64 wfx_prepare_multicast(struct ieee80211_hw *hw, struct netdev_hw_addr_list *mc_list); void wfx_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags, @@ -54,8 +35,10 @@ void wfx_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags, int wfx_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif); void wfx_remove_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif); -void wfx_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, - u32 queues, bool drop); +int wfx_start_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif); +void wfx_stop_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif); +int wfx_join_ibss(struct ieee80211_hw *hw, struct ieee80211_vif *vif); +void wfx_leave_ibss(struct ieee80211_hw *hw, struct ieee80211_vif *vif); int wfx_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u16 queue, const struct ieee80211_tx_queue_params *params); void wfx_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif, @@ -82,12 +65,13 @@ void wfx_unassign_vif_chanctx(struct ieee80211_hw *hw, struct ieee80211_chanctx_conf *conf); // WSM Callbacks +void wfx_cooling_timeout_work(struct work_struct *work); +void wfx_suspend_hot_dev(struct wfx_dev *wdev, enum sta_notify_cmd cmd); void wfx_suspend_resume_mc(struct wfx_vif *wvif, enum sta_notify_cmd cmd); +void wfx_event_report_rssi(struct wfx_vif *wvif, u8 raw_rcpi_rssi); // Other Helpers -void wfx_cqm_bssloss_sm(struct wfx_vif *wvif, int init, int good, int bad); -void wfx_update_filtering(struct wfx_vif *wvif); -int wfx_fwd_probe_req(struct wfx_vif *wvif, bool enable); +void wfx_reset(struct wfx_vif *wvif); u32 wfx_rate_mask_to_hw(struct wfx_dev *wdev, u32 rates); #endif /* WFX_STA_H */ diff --git a/drivers/staging/wfx/traces.h b/drivers/staging/wfx/traces.h index 30c6a13f0e22..0b6fbd518638 100644 --- a/drivers/staging/wfx/traces.h +++ b/drivers/staging/wfx/traces.h @@ -32,16 +32,16 @@ * xxx_name(XXX) \ * ... * - * 3. Instanciate that list_names: + * 3. Instantiate that list_names: * * list_names * - * 4. Redefine xxx_name() as a entry of array for __print_symbolic() + * 4. Redefine xxx_name() as an entry of array for __print_symbolic() * * #undef xxx_name * #define xxx_name(msg) { msg, #msg }, * - * 5. list_name can now nearlu be used with __print_symbolic() but, + * 5. list_name can now nearly be used with __print_symbolic() but, * __print_symbolic() dislike last comma of list. So we define a new list * with a dummy element: * @@ -104,8 +104,10 @@ hif_msg_list_enum hif_mib_name(ARP_KEEP_ALIVE_PERIOD) \ hif_mib_name(BEACON_FILTER_ENABLE) \ hif_mib_name(BEACON_FILTER_TABLE) \ + hif_mib_name(BEACON_STATS) \ hif_mib_name(BEACON_WAKEUP_PERIOD) \ hif_mib_name(BLOCK_ACK_POLICY) \ + hif_mib_name(CCA_CONFIG) \ hif_mib_name(CONFIG_DATA_FILTER) \ hif_mib_name(COUNTERS_TABLE) \ hif_mib_name(CURRENT_TX_POWER_LEVEL) \ @@ -114,29 +116,32 @@ hif_msg_list_enum hif_mib_name(DOT11_MAX_TRANSMIT_MSDU_LIFETIME) \ hif_mib_name(DOT11_RTS_THRESHOLD) \ hif_mib_name(DOT11_WEP_DEFAULT_KEY_ID) \ + hif_mib_name(ETHERTYPE_DATAFRAME_CONDITION) \ + hif_mib_name(EXTENDED_COUNTERS_TABLE) \ hif_mib_name(GL_BLOCK_ACK_INFO) \ hif_mib_name(GL_OPERATIONAL_POWER_MODE) \ hif_mib_name(GL_SET_MULTI_MSG) \ + hif_mib_name(GRP_SEQ_COUNTER) \ hif_mib_name(INACTIVITY_TIMER) \ hif_mib_name(INTERFACE_PROTECTION) \ hif_mib_name(IPV4_ADDR_DATAFRAME_CONDITION) \ hif_mib_name(IPV6_ADDR_DATAFRAME_CONDITION) \ hif_mib_name(KEEP_ALIVE_PERIOD) \ hif_mib_name(MAC_ADDR_DATAFRAME_CONDITION) \ + hif_mib_name(MAGIC_DATAFRAME_CONDITION) \ + hif_mib_name(MAX_TX_POWER_LEVEL) \ hif_mib_name(NON_ERP_PROTECTION) \ hif_mib_name(NS_IP_ADDRESSES_TABLE) \ hif_mib_name(OVERRIDE_INTERNAL_TX_RATE) \ + hif_mib_name(PORT_DATAFRAME_CONDITION) \ hif_mib_name(PROTECTED_MGMT_POLICY) \ - hif_mib_name(RX_FILTER) \ hif_mib_name(RCPI_RSSI_THRESHOLD) \ + hif_mib_name(RX_FILTER) \ hif_mib_name(SET_ASSOCIATION_MODE) \ hif_mib_name(SET_DATA_FILTERING) \ - hif_mib_name(ETHERTYPE_DATAFRAME_CONDITION) \ hif_mib_name(SET_HT_PROTECTION) \ - hif_mib_name(MAGIC_DATAFRAME_CONDITION) \ hif_mib_name(SET_TX_RATE_RETRY_POLICY) \ hif_mib_name(SET_UAPSD_INFORMATION) \ - hif_mib_name(PORT_DATAFRAME_CONDITION) \ hif_mib_name(SLOT_TIME) \ hif_mib_name(STATISTICS_TABLE) \ hif_mib_name(TEMPLATE_FRAME) \ @@ -169,7 +174,7 @@ DECLARE_EVENT_CLASS(hif_data, int header_len; __entry->tx_fill_level = tx_fill_level; - __entry->msg_len = hif->len; + __entry->msg_len = le16_to_cpu(hif->len); __entry->msg_id = hif->id; __entry->if_id = hif->interface; if (is_recv) @@ -179,7 +184,7 @@ DECLARE_EVENT_CLASS(hif_data, if (!is_recv && (__entry->msg_id == HIF_REQ_ID_READ_MIB || __entry->msg_id == HIF_REQ_ID_WRITE_MIB)) { - __entry->mib = le16_to_cpup((u16 *) hif->body); + __entry->mib = le16_to_cpup((__le16 *)hif->body); header_len = 4; } else { __entry->mib = -1; @@ -193,8 +198,8 @@ DECLARE_EVENT_CLASS(hif_data, TP_printk("%d:%d:%s_%s%s%s: %s%s (%d bytes)", __entry->tx_fill_level, __entry->if_id, - __print_symbolic(__entry->msg_id, hif_msg_list), __entry->msg_type, + __print_symbolic(__entry->msg_id, hif_msg_list), __entry->mib != -1 ? "/" : "", __entry->mib != -1 ? __print_symbolic(__entry->mib, hif_mib_list) : "", __print_hex(__entry->buf, __entry->buf_len), @@ -382,8 +387,8 @@ TRACE_EVENT(tx_stats, int i; __entry->pkt_id = tx_cnf->packet_id; - __entry->delay_media = tx_cnf->media_delay; - __entry->delay_queue = tx_cnf->tx_queue_delay; + __entry->delay_media = le32_to_cpu(tx_cnf->media_delay); + __entry->delay_queue = le32_to_cpu(tx_cnf->tx_queue_delay); __entry->delay_fw = delay; __entry->ack_failures = tx_cnf->ack_failures; if (!tx_cnf->status || __entry->ack_failures) @@ -409,7 +414,7 @@ TRACE_EVENT(tx_stats, __entry->flags |= 0x10; if (tx_cnf->status) __entry->flags |= 0x20; - if (tx_cnf->status == HIF_REQUEUE) + if (tx_cnf->status == HIF_STATUS_TX_FAIL_REQUEUE) __entry->flags |= 0x40; ), TP_printk("packet ID: %08x, rate policy: %s %d|%d %d|%d %d|%d %d|%d -> %d attempt, Delays media/queue/total: %4dus/%4dus/%4dus", diff --git a/drivers/staging/wfx/wfx.h b/drivers/staging/wfx/wfx.h index 8b85bb1abb9c..73e216733ce4 100644 --- a/drivers/staging/wfx/wfx.h +++ b/drivers/staging/wfx/wfx.h @@ -21,10 +21,7 @@ #include "main.h" #include "queue.h" #include "secure_link.h" -#include "sta.h" -#include "scan.h" #include "hif_tx.h" -#include "hif_api_general.h" #define USEC_PER_TXOP 32 // see struct ieee80211_tx_queue_params #define USEC_PER_TU 1024 @@ -45,21 +42,24 @@ struct wfx_dev { struct hif_ind_startup hw_caps; struct wfx_hif hif; struct sl_context sl; - int chip_frozen; + struct delayed_work cooling_timeout_work; + bool poll_irq; + bool chip_frozen; struct mutex conf_mutex; struct wfx_hif_cmd hif_cmd; struct wfx_queue tx_queue[4]; - struct wfx_queue_stats tx_queue_stats; - int tx_burst_idx; + struct sk_buff_head tx_pending; + wait_queue_head_t tx_dequeue; atomic_t tx_lock; atomic_t packet_id; u32 key_map; - struct hif_req_add_key keys[MAX_KEY_ENTRIES]; struct hif_rx_stats rx_stats; struct mutex rx_stats_lock; + struct hif_tx_power_loop_info tx_power_loop_info; + struct mutex tx_power_loop_info_lock; }; struct wfx_vif { @@ -67,42 +67,23 @@ struct wfx_vif { struct ieee80211_vif *vif; struct ieee80211_channel *channel; int id; - enum wfx_state state; - - int bss_loss_state; - u32 bss_loss_confirm_id; - struct mutex bss_loss_lock; - struct delayed_work bss_loss_work; u32 link_id_map; bool after_dtim_tx_allowed; - struct wfx_grp_addr_table mcast_filter; + bool join_in_progress; - s8 wep_default_key_id; - struct sk_buff *wep_pending_skb; - struct work_struct wep_key_work; + struct delayed_work beacon_loss_work; struct tx_policy_cache tx_policy_cache; struct work_struct tx_policy_upload_work; - u32 sta_asleep_mask; - spinlock_t ps_state_lock; struct work_struct update_tim_work; - int beacon_int; - bool filter_bssid; - bool fwd_probe_req; - bool disable_beacon_filter; - struct work_struct update_filtering_work; + int filter_mcast_count; + u8 filter_mcast_addr[8][ETH_ALEN]; unsigned long uapsd_mask; - struct ieee80211_tx_queue_params edca_params[IEEE80211_NUM_ACS]; - struct hif_req_set_bss_params bss_params; - struct work_struct bss_params_work; - - int join_complete_status; - struct work_struct unjoin_work; /* avoid some operations in parallel with scan */ struct mutex scan_lock; @@ -111,11 +92,9 @@ struct wfx_vif { bool scan_abort; struct ieee80211_scan_request *scan_req; + bool bss_not_support_ps_poll; + struct work_struct update_pm_work; struct completion set_pm_mode_complete; - - struct list_head event_queue; - spinlock_t event_queue_lock; - struct work_struct event_handler_work; }; static inline struct wfx_vif *wdev_to_wvif(struct wfx_dev *wdev, int vif_id) diff --git a/drivers/staging/wilc1000/hif.c b/drivers/staging/wilc1000/hif.c index 6c7de2f8d3f2..d025a3093015 100644 --- a/drivers/staging/wilc1000/hif.c +++ b/drivers/staging/wilc1000/hif.c @@ -11,6 +11,8 @@ #define WILC_FALSE_FRMWR_CHANNEL 100 +#define WILC_SCAN_WID_LIST_SIZE 6 + struct wilc_rcvd_mac_info { u8 status; }; @@ -151,7 +153,7 @@ int wilc_scan(struct wilc_vif *vif, u8 scan_source, u8 scan_type, void *user_arg, struct cfg80211_scan_request *request) { int result = 0; - struct wid wid_list[5]; + struct wid wid_list[WILC_SCAN_WID_LIST_SIZE]; u32 index = 0; u32 i, scan_timeout; u8 *buffer; diff --git a/drivers/tty/hvc/hvc_console.c b/drivers/tty/hvc/hvc_console.c index 436cc51c92c3..cdcc64ea2554 100644 --- a/drivers/tty/hvc/hvc_console.c +++ b/drivers/tty/hvc/hvc_console.c @@ -371,15 +371,14 @@ static int hvc_open(struct tty_struct *tty, struct file * filp) * tty fields and return the kref reference. */ if (rc) { - tty_port_tty_set(&hp->port, NULL); - tty->driver_data = NULL; - tty_port_put(&hp->port); printk(KERN_ERR "hvc_open: request_irq failed with rc %d.\n", rc); - } else + } else { /* We are ready... raise DTR/RTS */ if (C_BAUD(tty)) if (hp->ops->dtr_rts) hp->ops->dtr_rts(hp, 1); + tty_port_set_initialized(&hp->port, true); + } /* Force wakeup of the polling thread */ hvc_kick(); @@ -389,22 +388,12 @@ static int hvc_open(struct tty_struct *tty, struct file * filp) static void hvc_close(struct tty_struct *tty, struct file * filp) { - struct hvc_struct *hp; + struct hvc_struct *hp = tty->driver_data; unsigned long flags; if (tty_hung_up_p(filp)) return; - /* - * No driver_data means that this close was issued after a failed - * hvc_open by the tty layer's release_dev() function and we can just - * exit cleanly because the kref reference wasn't made. - */ - if (!tty->driver_data) - return; - - hp = tty->driver_data; - spin_lock_irqsave(&hp->port.lock, flags); if (--hp->port.count == 0) { @@ -412,6 +401,9 @@ static void hvc_close(struct tty_struct *tty, struct file * filp) /* We are done with the tty pointer now. */ tty_port_tty_set(&hp->port, NULL); + if (!tty_port_initialized(&hp->port)) + return; + if (C_HUPCL(tty)) if (hp->ops->dtr_rts) hp->ops->dtr_rts(hp, 0); @@ -428,6 +420,7 @@ static void hvc_close(struct tty_struct *tty, struct file * filp) * waking periodically to check chars_in_buffer(). */ tty_wait_until_sent(tty, HVC_CLOSE_WAIT); + tty_port_set_initialized(&hp->port, false); } else { if (hp->port.count < 0) printk(KERN_ERR "hvc_close %X: oops, count is %d\n", diff --git a/drivers/tty/hvc/hvcs.c b/drivers/tty/hvc/hvcs.c index ee0604cd9c6b..55105ac38f89 100644 --- a/drivers/tty/hvc/hvcs.c +++ b/drivers/tty/hvc/hvcs.c @@ -196,8 +196,6 @@ module_param(hvcs_parm_num_devs, int, 0); static const char hvcs_driver_name[] = "hvcs"; static const char hvcs_device_node[] = "hvcs"; -static const char hvcs_driver_string[] - = "IBM hvcs (Hypervisor Virtual Console Server) Driver"; /* Status of partner info rescan triggered via sysfs. */ static int hvcs_rescan_status; diff --git a/drivers/tty/mxser.c b/drivers/tty/mxser.c index 9d00ff5ef961..3703987c4666 100644 --- a/drivers/tty/mxser.c +++ b/drivers/tty/mxser.c @@ -638,16 +638,15 @@ static int mxser_set_baud(struct tty_struct *tty, long newspd) * This routine is called to set the UART divisor registers to match * the specified baud rate for a serial port. */ -static int mxser_change_speed(struct tty_struct *tty) +static void mxser_change_speed(struct tty_struct *tty) { struct mxser_port *info = tty->driver_data; unsigned cflag, cval, fcr; - int ret = 0; unsigned char status; cflag = tty->termios.c_cflag; if (!info->ioaddr) - return ret; + return; if (mxser_set_baud_method[tty->index] == 0) mxser_set_baud(tty, tty_get_baud_rate(tty)); @@ -803,8 +802,6 @@ static int mxser_change_speed(struct tty_struct *tty) outb(fcr, info->ioaddr + UART_FCR); /* set fcr */ outb(cval, info->ioaddr + UART_LCR); - - return ret; } static void mxser_check_modem_status(struct tty_struct *tty, diff --git a/drivers/tty/n_gsm.c b/drivers/tty/n_gsm.c index d77ed82a4840..0a29a94ec438 100644 --- a/drivers/tty/n_gsm.c +++ b/drivers/tty/n_gsm.c @@ -504,18 +504,7 @@ static void gsm_print_packet(const char *hdr, int addr, int cr, else pr_cont("(F)"); - if (dlen) { - int ct = 0; - while (dlen--) { - if (ct % 8 == 0) { - pr_cont("\n"); - pr_debug(" "); - } - pr_cont("%02X ", *data++); - ct++; - } - } - pr_cont("\n"); + print_hex_dump_bytes("", DUMP_PREFIX_NONE, data, dlen); } @@ -673,11 +662,10 @@ static struct gsm_msg *gsm_data_alloc(struct gsm_mux *gsm, u8 addr, int len, * FIXME: lock against link layer control transmissions */ -static void gsm_data_kick(struct gsm_mux *gsm) +static void gsm_data_kick(struct gsm_mux *gsm, struct gsm_dlci *dlci) { struct gsm_msg *msg, *nmsg; int len; - int skip_sof = 0; list_for_each_entry_safe(msg, nmsg, &gsm->tx_list, list) { if (gsm->constipated && msg->addr) @@ -699,18 +687,23 @@ static void gsm_data_kick(struct gsm_mux *gsm) print_hex_dump_bytes("gsm_data_kick: ", DUMP_PREFIX_OFFSET, gsm->txframe, len); - - if (gsm->output(gsm, gsm->txframe + skip_sof, - len - skip_sof) < 0) + if (gsm->output(gsm, gsm->txframe, len) < 0) break; /* FIXME: Can eliminate one SOF in many more cases */ gsm->tx_bytes -= msg->len; - /* For a burst of frames skip the extra SOF within the - burst */ - skip_sof = 1; list_del(&msg->list); kfree(msg); + + if (dlci) { + tty_port_tty_wakeup(&dlci->port); + } else { + int i = 0; + + for (i = 0; i < NUM_DLCI; i++) + if (gsm->dlci[i]) + tty_port_tty_wakeup(&gsm->dlci[i]->port); + } } } @@ -762,7 +755,7 @@ static void __gsm_data_queue(struct gsm_dlci *dlci, struct gsm_msg *msg) /* Add to the actual output queue */ list_add_tail(&msg->list, &gsm->tx_list); gsm->tx_bytes += msg->len; - gsm_data_kick(gsm); + gsm_data_kick(gsm, dlci); } /** @@ -1223,7 +1216,7 @@ static void gsm_control_message(struct gsm_mux *gsm, unsigned int command, gsm_control_reply(gsm, CMD_FCON, NULL, 0); /* Kick the link in case it is idling */ spin_lock_irqsave(&gsm->tx_lock, flags); - gsm_data_kick(gsm); + gsm_data_kick(gsm, NULL); spin_unlock_irqrestore(&gsm->tx_lock, flags); break; case CMD_FCOFF: @@ -2545,7 +2538,7 @@ static void gsmld_write_wakeup(struct tty_struct *tty) /* Queue poll */ clear_bit(TTY_DO_WRITE_WAKEUP, &tty->flags); spin_lock_irqsave(&gsm->tx_lock, flags); - gsm_data_kick(gsm); + gsm_data_kick(gsm, NULL); if (gsm->tx_bytes < TX_THRESH_LO) { gsm_dlci_data_sweep(gsm); } diff --git a/drivers/tty/rocket.c b/drivers/tty/rocket.c index e2138e7d5dc6..2540b2e4c8e8 100644 --- a/drivers/tty/rocket.c +++ b/drivers/tty/rocket.c @@ -1885,7 +1885,7 @@ static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum, */ static __init int register_PCI(int i, struct pci_dev *dev) { - int num_aiops, aiop, max_num_aiops, num_chan, chan; + int num_aiops, aiop, max_num_aiops, chan; unsigned int aiopio[MAX_AIOPS_PER_BOARD]; CONTROLLER_t *ctlp; @@ -2157,8 +2157,7 @@ static __init int register_PCI(int i, struct pci_dev *dev) /* Reset the AIOPIC, init the serial ports */ for (aiop = 0; aiop < num_aiops; aiop++) { sResetAiopByNum(ctlp, aiop); - num_chan = ports_per_aiop; - for (chan = 0; chan < num_chan; chan++) + for (chan = 0; chan < ports_per_aiop; chan++) init_r_port(i, aiop, chan, dev); } @@ -2166,11 +2165,10 @@ static __init int register_PCI(int i, struct pci_dev *dev) if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII) || (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) { - num_chan = ports_per_aiop; - for (chan = 0; chan < num_chan; chan++) + for (chan = 0; chan < ports_per_aiop; chan++) sPCIModemReset(ctlp, chan, 1); msleep(500); - for (chan = 0; chan < num_chan; chan++) + for (chan = 0; chan < ports_per_aiop; chan++) sPCIModemReset(ctlp, chan, 0); msleep(500); rmSpeakerReset(ctlp, rocketModel[i].model); diff --git a/drivers/tty/serial/8250/8250_core.c b/drivers/tty/serial/8250/8250_core.c index 45d9117cab68..fc118f649887 100644 --- a/drivers/tty/serial/8250/8250_core.c +++ b/drivers/tty/serial/8250/8250_core.c @@ -1026,7 +1026,9 @@ int serial8250_register_8250_port(struct uart_8250_port *up) if (up->port.dev) { uart->port.dev = up->port.dev; - uart_get_rs485_mode(uart->port.dev, &uart->port.rs485); + ret = uart_get_rs485_mode(&uart->port); + if (ret) + goto err; } if (up->port.flags & UPF_FIXED_TYPE) @@ -1040,7 +1042,7 @@ int serial8250_register_8250_port(struct uart_8250_port *up) gpios = mctrl_gpio_init(&uart->port, 0); if (IS_ERR(gpios)) { ret = PTR_ERR(gpios); - goto out_unlock; + goto err; } else { uart->gpios = gpios; } @@ -1089,8 +1091,10 @@ int serial8250_register_8250_port(struct uart_8250_port *up) serial8250_apply_quirks(uart); ret = uart_add_one_port(&serial8250_reg, &uart->port); - if (ret == 0) - ret = uart->port.line; + if (ret) + goto err; + + ret = uart->port.line; } else { dev_info(uart->port.dev, "skipping CIR port at 0x%lx / 0x%llx, IRQ %d\n", @@ -1112,10 +1116,14 @@ int serial8250_register_8250_port(struct uart_8250_port *up) } } -out_unlock: mutex_unlock(&serial_mutex); return ret; + +err: + uart->port.dev = NULL; + mutex_unlock(&serial_mutex); + return ret; } EXPORT_SYMBOL(serial8250_register_8250_port); diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/8250_exar.c index 59449b6500cd..ddb6aeb76dc5 100644 --- a/drivers/tty/serial/8250/8250_exar.c +++ b/drivers/tty/serial/8250/8250_exar.c @@ -25,13 +25,13 @@ #include "8250.h" -#define PCI_DEVICE_ID_ACCES_COM_2S 0x1052 -#define PCI_DEVICE_ID_ACCES_COM_4S 0x105d -#define PCI_DEVICE_ID_ACCES_COM_8S 0x106c -#define PCI_DEVICE_ID_ACCES_COM232_8 0x10a8 -#define PCI_DEVICE_ID_ACCES_COM_2SM 0x10d2 -#define PCI_DEVICE_ID_ACCES_COM_4SM 0x10db -#define PCI_DEVICE_ID_ACCES_COM_8SM 0x10ea +#define PCI_DEVICE_ID_ACCESSIO_COM_2S 0x1052 +#define PCI_DEVICE_ID_ACCESSIO_COM_4S 0x105d +#define PCI_DEVICE_ID_ACCESSIO_COM_8S 0x106c +#define PCI_DEVICE_ID_ACCESSIO_COM232_8 0x10a8 +#define PCI_DEVICE_ID_ACCESSIO_COM_2SM 0x10d2 +#define PCI_DEVICE_ID_ACCESSIO_COM_4SM 0x10db +#define PCI_DEVICE_ID_ACCESSIO_COM_8SM 0x10ea #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004 @@ -755,9 +755,7 @@ static const struct exar8250_board pbn_exar_XR17V8358 = { (kernel_ulong_t)&bd \ } -#define EXAR_DEVICE(vend, devid, bd) { \ - PCI_VDEVICE(vend, PCI_DEVICE_ID_##devid), (kernel_ulong_t)&bd \ - } +#define EXAR_DEVICE(vend, devid, bd) { PCI_DEVICE_DATA(vend, devid, &bd) } #define IBM_DEVICE(devid, sdevid, bd) { \ PCI_DEVICE_SUB( \ @@ -769,14 +767,13 @@ static const struct exar8250_board pbn_exar_XR17V8358 = { } static const struct pci_device_id exar_pci_tbl[] = { - EXAR_DEVICE(ACCESSIO, ACCES_COM_2S, acces_com_2x), - EXAR_DEVICE(ACCESSIO, ACCES_COM_4S, acces_com_4x), - EXAR_DEVICE(ACCESSIO, ACCES_COM_8S, acces_com_8x), - EXAR_DEVICE(ACCESSIO, ACCES_COM232_8, acces_com_8x), - EXAR_DEVICE(ACCESSIO, ACCES_COM_2SM, acces_com_2x), - EXAR_DEVICE(ACCESSIO, ACCES_COM_4SM, acces_com_4x), - EXAR_DEVICE(ACCESSIO, ACCES_COM_8SM, acces_com_8x), - + EXAR_DEVICE(ACCESSIO, COM_2S, acces_com_2x), + EXAR_DEVICE(ACCESSIO, COM_4S, acces_com_4x), + EXAR_DEVICE(ACCESSIO, COM_8S, acces_com_8x), + EXAR_DEVICE(ACCESSIO, COM232_8, acces_com_8x), + EXAR_DEVICE(ACCESSIO, COM_2SM, acces_com_2x), + EXAR_DEVICE(ACCESSIO, COM_4SM, acces_com_4x), + EXAR_DEVICE(ACCESSIO, COM_8SM, acces_com_8x), CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect), CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect), @@ -794,24 +791,24 @@ static const struct pci_device_id exar_pci_tbl[] = { IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn), /* Exar Corp. XR17C15[248] Dual/Quad/Octal UART */ - EXAR_DEVICE(EXAR, EXAR_XR17C152, pbn_exar_XR17C15x), - EXAR_DEVICE(EXAR, EXAR_XR17C154, pbn_exar_XR17C15x), - EXAR_DEVICE(EXAR, EXAR_XR17C158, pbn_exar_XR17C15x), + EXAR_DEVICE(EXAR, XR17C152, pbn_exar_XR17C15x), + EXAR_DEVICE(EXAR, XR17C154, pbn_exar_XR17C15x), + EXAR_DEVICE(EXAR, XR17C158, pbn_exar_XR17C15x), /* Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs */ - EXAR_DEVICE(EXAR, EXAR_XR17V352, pbn_exar_XR17V35x), - EXAR_DEVICE(EXAR, EXAR_XR17V354, pbn_exar_XR17V35x), - EXAR_DEVICE(EXAR, EXAR_XR17V358, pbn_exar_XR17V35x), - EXAR_DEVICE(EXAR, EXAR_XR17V4358, pbn_exar_XR17V4358), - EXAR_DEVICE(EXAR, EXAR_XR17V8358, pbn_exar_XR17V8358), - EXAR_DEVICE(COMMTECH, COMMTECH_4222PCIE, pbn_exar_XR17V35x), - EXAR_DEVICE(COMMTECH, COMMTECH_4224PCIE, pbn_exar_XR17V35x), - EXAR_DEVICE(COMMTECH, COMMTECH_4228PCIE, pbn_exar_XR17V35x), + EXAR_DEVICE(EXAR, XR17V352, pbn_exar_XR17V35x), + EXAR_DEVICE(EXAR, XR17V354, pbn_exar_XR17V35x), + EXAR_DEVICE(EXAR, XR17V358, pbn_exar_XR17V35x), + EXAR_DEVICE(EXAR, XR17V4358, pbn_exar_XR17V4358), + EXAR_DEVICE(EXAR, XR17V8358, pbn_exar_XR17V8358), + EXAR_DEVICE(COMMTECH, 4222PCIE, pbn_exar_XR17V35x), + EXAR_DEVICE(COMMTECH, 4224PCIE, pbn_exar_XR17V35x), + EXAR_DEVICE(COMMTECH, 4228PCIE, pbn_exar_XR17V35x), - EXAR_DEVICE(COMMTECH, COMMTECH_4222PCI335, pbn_fastcom335_2), - EXAR_DEVICE(COMMTECH, COMMTECH_4224PCI335, pbn_fastcom335_4), - EXAR_DEVICE(COMMTECH, COMMTECH_2324PCI335, pbn_fastcom335_4), - EXAR_DEVICE(COMMTECH, COMMTECH_2328PCI335, pbn_fastcom335_8), + EXAR_DEVICE(COMMTECH, 4222PCI335, pbn_fastcom335_2), + EXAR_DEVICE(COMMTECH, 4224PCI335, pbn_fastcom335_4), + EXAR_DEVICE(COMMTECH, 2324PCI335, pbn_fastcom335_4), + EXAR_DEVICE(COMMTECH, 2328PCI335, pbn_fastcom335_8), { 0, } }; MODULE_DEVICE_TABLE(pci, exar_pci_tbl); diff --git a/drivers/tty/serial/8250/8250_fintek.c b/drivers/tty/serial/8250/8250_fintek.c index 31c91c2f8c6e..d1d253c4b518 100644 --- a/drivers/tty/serial/8250/8250_fintek.c +++ b/drivers/tty/serial/8250/8250_fintek.c @@ -19,6 +19,7 @@ #define CHIP_ID2 0x21 #define CHIP_ID_F81865 0x0407 #define CHIP_ID_F81866 0x1010 +#define CHIP_ID_F81966 0x0215 #define CHIP_ID_F81216AD 0x1602 #define CHIP_ID_F81216H 0x0501 #define CHIP_ID_F81216 0x0802 @@ -62,9 +63,9 @@ #define F81216_LDN_HIGH 0x4 /* - * F81866 registers + * F81866/966 registers * - * The IRQ setting mode of F81866 is not the same with F81216 series. + * The IRQ setting mode of F81866/966 is not the same with F81216 series. * Level/Low: IRQ_MODE0:0, IRQ_MODE1:0 * Edge/High: IRQ_MODE0:1, IRQ_MODE1:0 * @@ -155,6 +156,7 @@ static int fintek_8250_check_id(struct fintek_8250 *pdata) switch (chip) { case CHIP_ID_F81865: case CHIP_ID_F81866: + case CHIP_ID_F81966: case CHIP_ID_F81216AD: case CHIP_ID_F81216H: case CHIP_ID_F81216: @@ -171,6 +173,7 @@ static int fintek_8250_get_ldn_range(struct fintek_8250 *pdata, int *min, int *max) { switch (pdata->pid) { + case CHIP_ID_F81966: case CHIP_ID_F81865: case CHIP_ID_F81866: *min = F81866_LDN_LOW; @@ -248,6 +251,7 @@ static void fintek_8250_set_irq_mode(struct fintek_8250 *pdata, bool is_level) sio_write_reg(pdata, LDN, pdata->index); switch (pdata->pid) { + case CHIP_ID_F81966: case CHIP_ID_F81866: sio_write_mask_reg(pdata, F81866_FIFO_CTRL, F81866_IRQ_MODE1, 0); @@ -274,6 +278,7 @@ static void fintek_8250_set_max_fifo(struct fintek_8250 *pdata) { switch (pdata->pid) { case CHIP_ID_F81216H: /* 128Bytes FIFO */ + case CHIP_ID_F81966: case CHIP_ID_F81866: sio_write_mask_reg(pdata, FIFO_CTRL, FIFO_MODE_MASK | RXFTHR_MODE_MASK, @@ -291,6 +296,7 @@ static void fintek_8250_goto_highspeed(struct uart_8250_port *uart, sio_write_reg(pdata, LDN, pdata->index); switch (pdata->pid) { + case CHIP_ID_F81966: case CHIP_ID_F81866: /* set uart clock for high speed serial mode */ sio_write_mask_reg(pdata, F81866_UART_CLK, F81866_UART_CLK_MASK, @@ -327,6 +333,7 @@ static void fintek_8250_set_termios(struct uart_port *port, case CHIP_ID_F81216H: reg = RS485; break; + case CHIP_ID_F81966: case CHIP_ID_F81866: reg = F81866_UART_CLK; break; @@ -373,6 +380,7 @@ static void fintek_8250_set_termios_handler(struct uart_8250_port *uart) switch (pdata->pid) { case CHIP_ID_F81216H: + case CHIP_ID_F81966: case CHIP_ID_F81866: uart->port.set_termios = fintek_8250_set_termios; break; @@ -443,6 +451,7 @@ static void fintek_8250_set_rs485_handler(struct uart_8250_port *uart) switch (pdata->pid) { case CHIP_ID_F81216AD: case CHIP_ID_F81216H: + case CHIP_ID_F81966: case CHIP_ID_F81866: case CHIP_ID_F81865: uart->port.rs485_config = fintek_8250_rs485_config; diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c index f77bf820b7a3..1632f7d25acc 100644 --- a/drivers/tty/serial/8250/8250_port.c +++ b/drivers/tty/serial/8250/8250_port.c @@ -681,6 +681,9 @@ int serial8250_em485_config(struct uart_port *port, struct serial_rs485 *rs485) memset(rs485->padding, 0, sizeof(rs485->padding)); port->rs485 = *rs485; + gpiod_set_value(port->rs485_term_gpio, + rs485->flags & SER_RS485_TERMINATE_BUS); + /* * Both serial8250_em485_init() and serial8250_em485_destroy() * are idempotent. @@ -1432,7 +1435,7 @@ static void serial8250_stop_rx(struct uart_port *port) /** * serial8250_em485_stop_tx() - generic ->rs485_stop_tx() callback - * @up: uart 8250 port + * @p: uart 8250 port * * Generic callback usable by 8250 uart drivers to stop rs485 transmission. */ @@ -2615,6 +2618,8 @@ static unsigned int serial8250_get_baud_rate(struct uart_port *port, struct ktermios *termios, struct ktermios *old) { + unsigned int tolerance = port->uartclk / 100; + /* * Ask the core to calculate the divisor for us. * Allow 1% tolerance at the upper limit so uart clks marginally @@ -2623,7 +2628,7 @@ static unsigned int serial8250_get_baud_rate(struct uart_port *port, */ return uart_get_baud_rate(port, termios, old, port->uartclk / 16 / UART_DIV_MAX, - port->uartclk); + (port->uartclk + tolerance) / 16); } void diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig index af0688156dd0..8195a31519ea 100644 --- a/drivers/tty/serial/8250/Kconfig +++ b/drivers/tty/serial/8250/Kconfig @@ -63,6 +63,7 @@ config SERIAL_8250_PNP config SERIAL_8250_16550A_VARIANTS bool "Support for variants of the 16550A serial port" depends on SERIAL_8250 + default !X86 help The 8250 driver can probe for many variants of the venerable 16550A serial port. Doing so takes additional time at boot. diff --git a/drivers/tty/serial/8250/serial_cs.c b/drivers/tty/serial/8250/serial_cs.c index c8186a05a453..e3d10794dbba 100644 --- a/drivers/tty/serial/8250/serial_cs.c +++ b/drivers/tty/serial/8250/serial_cs.c @@ -440,7 +440,7 @@ static int simple_config_check_notpicky(struct pcmcia_device *p_dev, static int simple_config(struct pcmcia_device *link) { struct serial_info *info = link->priv; - int i = -ENODEV, try; + int ret, try; /* * First pass: look for a config entry that looks normal. @@ -472,8 +472,8 @@ found_port: if (info->quirk && info->quirk->config) info->quirk->config(link); - i = pcmcia_enable_device(link); - if (i != 0) + ret = pcmcia_enable_device(link); + if (ret != 0) return -1; return setup_serial(link, info, link->resource[0]->start, link->irq); } diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index adf9e80e7dc9..0282ad9cdaa7 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -1034,13 +1034,22 @@ config SERIAL_SIFIVE_CONSOLE boot time.) config SERIAL_LANTIQ - bool "Lantiq serial driver" - depends on LANTIQ + tristate "Lantiq serial driver" + depends on (LANTIQ || X86) || COMPILE_TEST select SERIAL_CORE + help + Support for UART on Lantiq and Intel SoCs. + To compile this driver as a module, select M here. The + module will be called lantiq. + +config SERIAL_LANTIQ_CONSOLE + bool "Console on Lantiq UART" + depends on SERIAL_LANTIQ=y select SERIAL_CORE_CONSOLE select SERIAL_EARLYCON help - Support for console and UART on Lantiq SoCs. + Select this option if you would like to use a Lantiq UART as the + system console. config SERIAL_QE tristate "Freescale QUICC Engine serial port support" @@ -1462,6 +1471,7 @@ config SERIAL_STM32 tristate "STMicroelectronics STM32 serial port support" select SERIAL_CORE depends on ARCH_STM32 || COMPILE_TEST + select SERIAL_MCTRL_GPIO if GPIOLIB help This driver is for the on-chip Serial Controller on STMicroelectronics STM32 MCUs. diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c index c010f639298d..8efd7c2a34fe 100644 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c @@ -2607,6 +2607,7 @@ static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap, uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE); uap->port.flags = UPF_BOOT_AUTOCONF; uap->port.line = index; + spin_lock_init(&uap->port.lock); amba_ports[index] = uap; diff --git a/drivers/tty/serial/ar933x_uart.c b/drivers/tty/serial/ar933x_uart.c index 7e7f1398019f..0c80a79d7442 100644 --- a/drivers/tty/serial/ar933x_uart.c +++ b/drivers/tty/serial/ar933x_uart.c @@ -766,8 +766,6 @@ static int ar933x_uart_probe(struct platform_device *pdev) goto err_disable_clk; } - uart_get_rs485_mode(&pdev->dev, &port->rs485); - port->mapbase = mem_res->start; port->line = id; port->irq = irq_res->start; @@ -786,6 +784,10 @@ static int ar933x_uart_probe(struct platform_device *pdev) baud = ar933x_uart_get_baud(port->uartclk, 0, AR933X_UART_MAX_STEP); up->max_baud = min_t(unsigned int, baud, AR933X_UART_MAX_BAUD); + ret = uart_get_rs485_mode(port); + if (ret) + goto err_disable_clk; + up->gpios = mctrl_gpio_init(port, 0); if (IS_ERR(up->gpios) && PTR_ERR(up->gpios) != -ENOSYS) return PTR_ERR(up->gpios); diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c index 8d7080efad9b..e43471b33710 100644 --- a/drivers/tty/serial/atmel_serial.c +++ b/drivers/tty/serial/atmel_serial.c @@ -2491,8 +2491,6 @@ static int atmel_init_port(struct atmel_uart_port *atmel_port, atmel_init_property(atmel_port, pdev); atmel_set_ops(port); - uart_get_rs485_mode(&mpdev->dev, &port->rs485); - port->iotype = UPIO_MEM; port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP; port->ops = &atmel_pops; @@ -2506,6 +2504,10 @@ static int atmel_init_port(struct atmel_uart_port *atmel_port, memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring)); + ret = uart_get_rs485_mode(port); + if (ret) + return ret; + /* for console, the clock could already be configured */ if (!atmel_port->clk) { atmel_port->clk = clk_get(&mpdev->dev, "usart"); diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c index 5d41075964f2..90298c403042 100644 --- a/drivers/tty/serial/fsl_lpuart.c +++ b/drivers/tty/serial/fsl_lpuart.c @@ -1231,9 +1231,7 @@ static void lpuart_dma_rx_free(struct uart_port *port) struct lpuart_port, port); struct dma_chan *chan = sport->dma_rx_chan; - if (chan) - dmaengine_terminate_all(chan); - + dmaengine_terminate_all(chan); dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); kfree(sport->rx_ring.buf); sport->rx_ring.tail = 0; @@ -1514,17 +1512,17 @@ static void lpuart_request_dma(struct lpuart_port *sport) { sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx"); if (IS_ERR(sport->dma_tx_chan)) { - dev_info_once(sport->port.dev, - "DMA tx channel request failed, operating without tx DMA (%ld)\n", - PTR_ERR(sport->dma_tx_chan)); + dev_dbg_once(sport->port.dev, + "DMA tx channel request failed, operating without tx DMA (%ld)\n", + PTR_ERR(sport->dma_tx_chan)); sport->dma_tx_chan = NULL; } sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx"); if (IS_ERR(sport->dma_rx_chan)) { - dev_info_once(sport->port.dev, - "DMA rx channel request failed, operating without rx DMA (%ld)\n", - PTR_ERR(sport->dma_rx_chan)); + dev_dbg_once(sport->port.dev, + "DMA rx channel request failed, operating without rx DMA (%ld)\n", + PTR_ERR(sport->dma_rx_chan)); sport->dma_rx_chan = NULL; } } @@ -2621,7 +2619,9 @@ static int lpuart_probe(struct platform_device *pdev) if (ret) goto failed_attach_port; - uart_get_rs485_mode(&pdev->dev, &sport->port.rs485); + ret = uart_get_rs485_mode(&sport->port); + if (ret) + goto failed_get_rs485; if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX) dev_err(&pdev->dev, "driver doesn't support RX during TX\n"); @@ -2634,6 +2634,7 @@ static int lpuart_probe(struct platform_device *pdev) return 0; +failed_get_rs485: failed_attach_port: failed_irq_request: lpuart_disable_clks(sport); @@ -2664,8 +2665,7 @@ static int lpuart_remove(struct platform_device *pdev) return 0; } -#ifdef CONFIG_PM_SLEEP -static int lpuart_suspend(struct device *dev) +static int __maybe_unused lpuart_suspend(struct device *dev) { struct lpuart_port *sport = dev_get_drvdata(dev); unsigned long temp; @@ -2723,7 +2723,7 @@ static int lpuart_suspend(struct device *dev) return 0; } -static int lpuart_resume(struct device *dev) +static int __maybe_unused lpuart_resume(struct device *dev) { struct lpuart_port *sport = dev_get_drvdata(dev); bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); @@ -2754,7 +2754,6 @@ static int lpuart_resume(struct device *dev) return 0; } -#endif static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume); diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c index f4d68109bc8b..1265e8d86d8a 100644 --- a/drivers/tty/serial/imx.c +++ b/drivers/tty/serial/imx.c @@ -909,6 +909,8 @@ static irqreturn_t imx_uart_int(int irq, void *dev_id) usr2 &= ~USR2_ORE; if (usr1 & (USR1_RRDY | USR1_AGTIM)) { + imx_uart_writel(sport, USR1_AGTIM, USR1); + __imx_uart_rxint(irq, dev_id); ret = IRQ_HANDLED; } @@ -2252,6 +2254,8 @@ static int imx_uart_probe(struct platform_device *pdev) return PTR_ERR(base); rxirq = platform_get_irq(pdev, 0); + if (rxirq < 0) + return rxirq; txirq = platform_get_irq_optional(pdev, 1); rtsirq = platform_get_irq_optional(pdev, 2); @@ -2302,7 +2306,11 @@ static int imx_uart_probe(struct platform_device *pdev) sport->ucr4 = readl(sport->port.membase + UCR4); sport->ufcr = readl(sport->port.membase + UFCR); - uart_get_rs485_mode(&pdev->dev, &sport->port.rs485); + ret = uart_get_rs485_mode(&sport->port); + if (ret) { + clk_disable_unprepare(sport->clk_ipg); + return ret; + } if (sport->port.rs485.flags & SER_RS485_ENABLED && (!sport->have_rtscts && !sport->have_rtsgpio)) @@ -2398,6 +2406,9 @@ static int imx_uart_probe(struct platform_device *pdev) } } + /* We need to initialize lock even for non-registered console */ + spin_lock_init(&sport->port.lock); + imx_uart_ports[sport->port.line] = sport; platform_set_drvdata(pdev, sport); diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c index c5e46ff972e4..62813e421f12 100644 --- a/drivers/tty/serial/lantiq.c +++ b/drivers/tty/serial/lantiq.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -597,6 +598,7 @@ static const struct uart_ops lqasc_pops = { .verify_port = lqasc_verify_port, }; +#ifdef CONFIG_SERIAL_LANTIQ_CONSOLE static void lqasc_console_putchar(struct uart_port *port, int ch) { @@ -705,6 +707,14 @@ lqasc_serial_early_console_setup(struct earlycon_device *device, OF_EARLYCON_DECLARE(lantiq, "lantiq,asc", lqasc_serial_early_console_setup); OF_EARLYCON_DECLARE(lantiq, "intel,lgm-asc", lqasc_serial_early_console_setup); +#define LANTIQ_SERIAL_CONSOLE (&lqasc_console) + +#else + +#define LANTIQ_SERIAL_CONSOLE NULL + +#endif /* CONFIG_SERIAL_LANTIQ_CONSOLE */ + static struct uart_driver lqasc_reg = { .owner = THIS_MODULE, .driver_name = DRVNAME, @@ -712,7 +722,7 @@ static struct uart_driver lqasc_reg = { .major = 0, .minor = 0, .nr = MAXPORTS, - .cons = &lqasc_console, + .cons = LANTIQ_SERIAL_CONSOLE, }; static int fetch_irq_lantiq(struct device *dev, struct ltq_uart_port *ltq_port) @@ -814,8 +824,7 @@ static void free_irq_intel(struct uart_port *port) free_irq(ltq_port->common_irq, port); } -static int __init -lqasc_probe(struct platform_device *pdev) +static int lqasc_probe(struct platform_device *pdev) { struct device_node *node = pdev->dev.of_node; struct ltq_uart_port *ltq_port; @@ -899,6 +908,13 @@ lqasc_probe(struct platform_device *pdev) return ret; } +static int lqasc_remove(struct platform_device *pdev) +{ + struct uart_port *port = platform_get_drvdata(pdev); + + return uart_remove_one_port(&lqasc_reg, port); +} + static const struct ltq_soc_data soc_data_lantiq = { .fetch_irq = fetch_irq_lantiq, .request_irq = request_irq_lantiq, @@ -916,8 +932,11 @@ static const struct of_device_id ltq_asc_match[] = { { .compatible = "intel,lgm-asc", .data = &soc_data_intel }, {}, }; +MODULE_DEVICE_TABLE(of, ltq_asc_match); static struct platform_driver lqasc_driver = { + .probe = lqasc_probe, + .remove = lqasc_remove, .driver = { .name = DRVNAME, .of_match_table = ltq_asc_match, @@ -933,10 +952,21 @@ init_lqasc(void) if (ret != 0) return ret; - ret = platform_driver_probe(&lqasc_driver, lqasc_probe); + ret = platform_driver_register(&lqasc_driver); if (ret != 0) uart_unregister_driver(&lqasc_reg); return ret; } -device_initcall(init_lqasc); + +static void __exit exit_lqasc(void) +{ + platform_driver_unregister(&lqasc_driver); + uart_unregister_driver(&lqasc_reg); +} + +module_init(init_lqasc); +module_exit(exit_lqasc); + +MODULE_DESCRIPTION("Serial driver for Lantiq & Intel gateway SoCs"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/tty/serial/lpc32xx_hs.c b/drivers/tty/serial/lpc32xx_hs.c index 9a836dcac157..b5898c932036 100644 --- a/drivers/tty/serial/lpc32xx_hs.c +++ b/drivers/tty/serial/lpc32xx_hs.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c index f7d6b3c9ea45..8573fc9cb0cd 100644 --- a/drivers/tty/serial/omap-serial.c +++ b/drivers/tty/serial/omap-serial.c @@ -33,8 +33,7 @@ #include #include #include -#include -#include +#include #include #define OMAP_MAX_HSUART_PORTS 10 @@ -153,7 +152,7 @@ struct uart_omap_port { u32 errata; u32 features; - int rts_gpio; + struct gpio_desc *rts_gpiod; struct pm_qos_request pm_qos_request; u32 latency; @@ -303,11 +302,11 @@ static void serial_omap_stop_tx(struct uart_port *port) serial_out(up, UART_OMAP_SCR, up->scr); res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ? 1 : 0; - if (gpio_get_value(up->rts_gpio) != res) { + if (gpiod_get_value(up->rts_gpiod) != res) { if (port->rs485.delay_rts_after_send > 0) mdelay( port->rs485.delay_rts_after_send); - gpio_set_value(up->rts_gpio, res); + gpiod_set_value(up->rts_gpiod, res); } } else { /* We're asked to stop, but there's still stuff in the @@ -412,8 +411,8 @@ static void serial_omap_start_tx(struct uart_port *port) /* if rts not already enabled */ res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0; - if (gpio_get_value(up->rts_gpio) != res) { - gpio_set_value(up->rts_gpio, res); + if (gpiod_get_value(up->rts_gpiod) != res) { + gpiod_set_value(up->rts_gpiod, res); if (port->rs485.delay_rts_before_send > 0) mdelay(port->rs485.delay_rts_before_send); } @@ -1414,12 +1413,12 @@ serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485) * Just as a precaution, only allow rs485 * to be enabled if the gpio pin is valid */ - if (gpio_is_valid(up->rts_gpio)) { + if (up->rts_gpiod) { /* enable / disable rts */ val = (port->rs485.flags & SER_RS485_ENABLED) ? SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND; val = (port->rs485.flags & val) ? 1 : 0; - gpio_set_value(up->rts_gpio, val); + gpiod_set_value(up->rts_gpiod, val); } else port->rs485.flags &= ~SER_RS485_ENABLED; @@ -1596,18 +1595,22 @@ static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev) } static int serial_omap_probe_rs485(struct uart_omap_port *up, - struct device_node *np) + struct device *dev) { struct serial_rs485 *rs485conf = &up->port.rs485; + struct device_node *np = dev->of_node; + enum gpiod_flags gflags; int ret; rs485conf->flags = 0; - up->rts_gpio = -EINVAL; + up->rts_gpiod = NULL; if (!np) return 0; - uart_get_rs485_mode(up->dev, rs485conf); + ret = uart_get_rs485_mode(&up->port); + if (ret) + return ret; if (of_property_read_bool(np, "rs485-rts-active-high")) { rs485conf->flags |= SER_RS485_RTS_ON_SEND; @@ -1618,19 +1621,20 @@ static int serial_omap_probe_rs485(struct uart_omap_port *up, } /* check for tx enable gpio */ - up->rts_gpio = of_get_named_gpio(np, "rts-gpio", 0); - if (gpio_is_valid(up->rts_gpio)) { - ret = devm_gpio_request(up->dev, up->rts_gpio, "omap-serial"); - if (ret < 0) + gflags = rs485conf->flags & SER_RS485_RTS_AFTER_SEND ? + GPIOD_OUT_HIGH : GPIOD_OUT_LOW; + up->rts_gpiod = devm_gpiod_get_optional(dev, "rts", gflags); + if (IS_ERR(up->rts_gpiod)) { + ret = PTR_ERR(up->rts_gpiod); + if (ret == -EPROBE_DEFER) return ret; - ret = rs485conf->flags & SER_RS485_RTS_AFTER_SEND ? 1 : 0; - ret = gpio_direction_output(up->rts_gpio, ret); - if (ret < 0) - return ret; - } else if (up->rts_gpio == -EPROBE_DEFER) { - return -EPROBE_DEFER; + /* + * FIXME: the code historically ignored any other error than + * -EPROBE_DEFER and just went on without GPIO. + */ + up->rts_gpiod = NULL; } else { - up->rts_gpio = -EINVAL; + gpiod_set_consumer_name(up->rts_gpiod, "omap-serial"); } return 0; @@ -1703,7 +1707,7 @@ static int serial_omap_probe(struct platform_device *pdev) dev_info(up->port.dev, "no wakeirq for uart%d\n", up->port.line); - ret = serial_omap_probe_rs485(up, pdev->dev.of_node); + ret = serial_omap_probe_rs485(up, &pdev->dev); if (ret < 0) goto err_rs485; diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index 6bace1c6bb09..457c0bf8cbf8 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -141,9 +141,10 @@ static void qcom_geni_serial_stop_rx(struct uart_port *uport); static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop); static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200, - 32000000, 48000000, 64000000, 80000000, - 96000000, 100000000, 102400000, - 112000000, 120000000, 128000000}; + 32000000, 48000000, 51200000, 64000000, + 80000000, 96000000, 100000000, + 102400000, 112000000, 120000000, + 128000000}; #define to_dev_port(ptr, member) \ container_of(ptr, struct qcom_geni_serial_port, member) diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c index 73f951d65b93..d913d9b2762a 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -154,10 +154,33 @@ struct s3c24xx_uart_port { #define portaddrl(port, reg) \ ((unsigned long *)(unsigned long)((port)->membase + (reg))) -#define rd_regb(port, reg) (readb_relaxed(portaddr(port, reg))) +static u32 rd_reg(struct uart_port *port, u32 reg) +{ + switch (port->iotype) { + case UPIO_MEM: + return readb_relaxed(portaddr(port, reg)); + case UPIO_MEM32: + return readl_relaxed(portaddr(port, reg)); + default: + return 0; + } + return 0; +} + #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg))) -#define wr_regb(port, reg, val) writeb_relaxed(val, portaddr(port, reg)) +static void wr_reg(struct uart_port *port, u32 reg, u32 val) +{ + switch (port->iotype) { + case UPIO_MEM: + writeb_relaxed(val, portaddr(port, reg)); + break; + case UPIO_MEM32: + writel_relaxed(val, portaddr(port, reg)); + break; + } +} + #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg)) /* Byte-order aware bit setting/clearing functions. */ @@ -714,7 +737,7 @@ static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport) fifocnt--; uerstat = rd_regl(port, S3C2410_UERSTAT); - ch = rd_regb(port, S3C2410_URXH); + ch = rd_reg(port, S3C2410_URXH); if (port->flags & UPF_CONS_FLOW) { int txe = s3c24xx_serial_txempty_nofifo(port); @@ -826,7 +849,7 @@ static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id) } if (port->x_char) { - wr_regb(port, S3C2410_UTXH, port->x_char); + wr_reg(port, S3C2410_UTXH, port->x_char); port->icount.tx++; port->x_char = 0; goto out; @@ -852,7 +875,7 @@ static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id) if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull) break; - wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]); + wr_reg(port, S3C2410_UTXH, xmit->buf[xmit->tail]); xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); port->icount.tx++; count--; @@ -916,7 +939,7 @@ static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port) /* no modem control lines */ static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port) { - unsigned int umstat = rd_regb(port, S3C2410_UMSTAT); + unsigned int umstat = rd_reg(port, S3C2410_UMSTAT); if (umstat & S3C2410_UMSTAT_CTS) return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; @@ -1281,14 +1304,14 @@ static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport, struct s3c24xx_uart_info *info = ourport->info; struct clk *clk; unsigned long rate; - unsigned int cnt, baud, quot, clk_sel, best_quot = 0; + unsigned int cnt, baud, quot, best_quot = 0; char clkname[MAX_CLK_NAME_LENGTH]; int calc_deviation, deviation = (1 << 30) - 1; - clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel : - ourport->info->def_clk_sel; for (cnt = 0; cnt < info->num_clks; cnt++) { - if (!(clk_sel & (1 << cnt))) + /* Keep selected clock if provided */ + if (ourport->cfg->clk_sel && + !(ourport->cfg->clk_sel & (1 << cnt))) continue; sprintf(clkname, "clk_uart_baud%d", cnt); @@ -1974,7 +1997,7 @@ static int s3c24xx_serial_probe(struct platform_device *pdev) struct device_node *np = pdev->dev.of_node; struct s3c24xx_uart_port *ourport; int index = probe_index; - int ret; + int ret, prop = 0; if (np) { ret = of_alias_get_id(np, "serial"); @@ -2000,10 +2023,27 @@ static int s3c24xx_serial_probe(struct platform_device *pdev) dev_get_platdata(&pdev->dev) : ourport->drv_data->def_cfg; - if (np) + if (np) { of_property_read_u32(np, "samsung,uart-fifosize", &ourport->port.fifosize); + if (of_property_read_u32(np, "reg-io-width", &prop) == 0) { + switch (prop) { + case 1: + ourport->port.iotype = UPIO_MEM; + break; + case 4: + ourport->port.iotype = UPIO_MEM32; + break; + default: + dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n", + prop); + ret = -EINVAL; + break; + } + } + } + if (ourport->drv_data->fifosize[index]) ourport->port.fifosize = ourport->drv_data->fifosize[index]; else if (ourport->info->fifosize) @@ -2185,7 +2225,7 @@ static int s3c24xx_serial_get_poll_char(struct uart_port *port) if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0) return NO_POLL_CHAR; - return rd_regb(port, S3C2410_URXH); + return rd_reg(port, S3C2410_URXH); } static void s3c24xx_serial_put_poll_char(struct uart_port *port, @@ -2200,7 +2240,7 @@ static void s3c24xx_serial_put_poll_char(struct uart_port *port, while (!s3c24xx_serial_console_txrdy(port, ufcon)) cpu_relax(); - wr_regb(port, S3C2410_UTXH, c); + wr_reg(port, S3C2410_UTXH, c); } #endif /* CONFIG_CONSOLE_POLL */ @@ -2212,7 +2252,7 @@ s3c24xx_serial_console_putchar(struct uart_port *port, int ch) while (!s3c24xx_serial_console_txrdy(port, ufcon)) cpu_relax(); - wr_regb(port, S3C2410_UTXH, ch); + wr_reg(port, S3C2410_UTXH, ch); } static void @@ -2587,6 +2627,18 @@ module_platform_driver(samsung_serial_driver); * Early console. */ +static void wr_reg_barrier(struct uart_port *port, u32 reg, u32 val) +{ + switch (port->iotype) { + case UPIO_MEM: + writeb(val, portaddr(port, reg)); + break; + case UPIO_MEM32: + writel(val, portaddr(port, reg)); + break; + } +} + struct samsung_early_console_data { u32 txfull_mask; }; @@ -2612,7 +2664,7 @@ static void samsung_early_putc(struct uart_port *port, int c) else samsung_early_busyuart(port); - writeb(c, port->membase + S3C2410_UTXH); + wr_reg_barrier(port, S3C2410_UTXH, c); } static void samsung_early_write(struct console *con, const char *s, diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.c index 06e8071d5601..d2e5c6c86643 100644 --- a/drivers/tty/serial/sc16is7xx.c +++ b/drivers/tty/serial/sc16is7xx.c @@ -315,6 +315,7 @@ struct sc16is7xx_one { struct kthread_work tx_work; struct kthread_work reg_work; struct sc16is7xx_one_config config; + bool irda_mode; }; struct sc16is7xx_port { @@ -327,7 +328,6 @@ struct sc16is7xx_port { unsigned char buf[SC16IS7XX_FIFO_SIZE]; struct kthread_worker kworker; struct task_struct *kworker_task; - struct kthread_work irq_work; struct mutex efr_lock; struct sc16is7xx_one p[]; }; @@ -710,9 +710,9 @@ static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno) return true; } -static void sc16is7xx_ist(struct kthread_work *ws) +static irqreturn_t sc16is7xx_irq(int irq, void *dev_id) { - struct sc16is7xx_port *s = to_sc16is7xx_port(ws, irq_work); + struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id; mutex_lock(&s->efr_lock); @@ -727,13 +727,6 @@ static void sc16is7xx_ist(struct kthread_work *ws) } mutex_unlock(&s->efr_lock); -} - -static irqreturn_t sc16is7xx_irq(int irq, void *dev_id) -{ - struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id; - - kthread_queue_work(&s->kworker, &s->irq_work); return IRQ_HANDLED; } @@ -994,6 +987,7 @@ static int sc16is7xx_config_rs485(struct uart_port *port, static int sc16is7xx_startup(struct uart_port *port) { + struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); struct sc16is7xx_port *s = dev_get_drvdata(port->dev); unsigned int val; @@ -1032,6 +1026,13 @@ static int sc16is7xx_startup(struct uart_port *port) /* Now, initialize the UART */ sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8); + /* Enable IrDA mode if requested in DT */ + /* This bit must be written with LCR[7] = 0 */ + sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, + SC16IS7XX_MCR_IRDA_BIT, + one->irda_mode ? + SC16IS7XX_MCR_IRDA_BIT : 0); + /* Enable the Rx and Tx FIFO */ sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, SC16IS7XX_EFCR_RXDISABLE_BIT | @@ -1176,10 +1177,11 @@ static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip, static int sc16is7xx_probe(struct device *dev, const struct sc16is7xx_devtype *devtype, - struct regmap *regmap, int irq, unsigned long flags) + struct regmap *regmap, int irq) { struct sched_param sched_param = { .sched_priority = MAX_RT_PRIO / 2 }; unsigned long freq = 0, *pfreq = dev_get_platdata(dev); + unsigned int val; u32 uartclk = 0; int i, ret; struct sc16is7xx_port *s; @@ -1187,6 +1189,16 @@ static int sc16is7xx_probe(struct device *dev, if (IS_ERR(regmap)) return PTR_ERR(regmap); + /* + * This device does not have an identification register that would + * tell us if we are really connected to the correct device. + * The best we can do is to check if communication is at all possible. + */ + ret = regmap_read(regmap, + SC16IS7XX_LSR_REG << SC16IS7XX_REG_SHIFT, &val); + if (ret < 0) + return ret; + /* Alloc port structure */ s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL); if (!s) { @@ -1221,7 +1233,6 @@ static int sc16is7xx_probe(struct device *dev, mutex_init(&s->efr_lock); kthread_init_worker(&s->kworker); - kthread_init_work(&s->irq_work, sc16is7xx_ist); s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker, "sc16is7xx"); if (IS_ERR(s->kworker_task)) { @@ -1302,9 +1313,33 @@ static int sc16is7xx_probe(struct device *dev, sc16is7xx_power(&s->p[i].port, 0); } - /* Setup interrupt */ - ret = devm_request_irq(dev, irq, sc16is7xx_irq, - flags, dev_name(dev), s); + if (dev->of_node) { + struct property *prop; + const __be32 *p; + u32 u; + + of_property_for_each_u32(dev->of_node, "irda-mode-ports", + prop, p, u) + if (u < devtype->nr_uart) + s->p[u].irda_mode = true; + } + + /* + * Setup interrupt. We first try to acquire the IRQ line as level IRQ. + * If that succeeds, we can allow sharing the interrupt as well. + * In case the interrupt controller doesn't support that, we fall + * back to a non-shared falling-edge trigger. + */ + ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq, + IRQF_TRIGGER_LOW | IRQF_SHARED | + IRQF_ONESHOT, + dev_name(dev), s); + if (!ret) + return 0; + + ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq, + IRQF_TRIGGER_FALLING | IRQF_ONESHOT, + dev_name(dev), s); if (!ret) return 0; @@ -1378,7 +1413,6 @@ static struct regmap_config regcfg = { static int sc16is7xx_spi_probe(struct spi_device *spi) { const struct sc16is7xx_devtype *devtype; - unsigned long flags = 0; struct regmap *regmap; int ret; @@ -1399,14 +1433,13 @@ static int sc16is7xx_spi_probe(struct spi_device *spi) const struct spi_device_id *id_entry = spi_get_device_id(spi); devtype = (struct sc16is7xx_devtype *)id_entry->driver_data; - flags = IRQF_TRIGGER_FALLING; } regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) | (devtype->nr_uart - 1); regmap = devm_regmap_init_spi(spi, ®cfg); - return sc16is7xx_probe(&spi->dev, devtype, regmap, spi->irq, flags); + return sc16is7xx_probe(&spi->dev, devtype, regmap, spi->irq); } static int sc16is7xx_spi_remove(struct spi_device *spi) @@ -1445,7 +1478,6 @@ static int sc16is7xx_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id) { const struct sc16is7xx_devtype *devtype; - unsigned long flags = 0; struct regmap *regmap; if (i2c->dev.of_node) { @@ -1454,14 +1486,13 @@ static int sc16is7xx_i2c_probe(struct i2c_client *i2c, return -ENODEV; } else { devtype = (struct sc16is7xx_devtype *)id->driver_data; - flags = IRQF_TRIGGER_FALLING; } regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) | (devtype->nr_uart - 1); regmap = devm_regmap_init_i2c(i2c, ®cfg); - return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq, flags); + return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq); } static int sc16is7xx_i2c_remove(struct i2c_client *client) diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c index 66a5e2faf57e..57840cf90388 100644 --- a/drivers/tty/serial/serial_core.c +++ b/drivers/tty/serial/serial_core.c @@ -3295,8 +3295,10 @@ EXPORT_SYMBOL(uart_remove_one_port); * This function implements the device tree binding described in * Documentation/devicetree/bindings/serial/rs485.txt. */ -void uart_get_rs485_mode(struct device *dev, struct serial_rs485 *rs485conf) +int uart_get_rs485_mode(struct uart_port *port) { + struct serial_rs485 *rs485conf = &port->rs485; + struct device *dev = port->dev; u32 rs485_delay[2]; int ret; @@ -3315,6 +3317,7 @@ void uart_get_rs485_mode(struct device *dev, struct serial_rs485 *rs485conf) * to get to a defined state with the following properties: */ rs485conf->flags &= ~(SER_RS485_RX_DURING_TX | SER_RS485_ENABLED | + SER_RS485_TERMINATE_BUS | SER_RS485_RTS_AFTER_SEND); rs485conf->flags |= SER_RS485_RTS_ON_SEND; @@ -3328,6 +3331,23 @@ void uart_get_rs485_mode(struct device *dev, struct serial_rs485 *rs485conf) rs485conf->flags &= ~SER_RS485_RTS_ON_SEND; rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; } + + /* + * Disabling termination by default is the safe choice: Else if many + * bus participants enable it, no communication is possible at all. + * Works fine for short cables and users may enable for longer cables. + */ + port->rs485_term_gpio = devm_gpiod_get_optional(dev, "rs485-term", + GPIOD_OUT_LOW); + if (IS_ERR(port->rs485_term_gpio)) { + ret = PTR_ERR(port->rs485_term_gpio); + port->rs485_term_gpio = NULL; + if (ret != -EPROBE_DEFER) + dev_err(dev, "Cannot get rs485-term-gpios\n"); + return ret; + } + + return 0; } EXPORT_SYMBOL_GPL(uart_get_rs485_mode); diff --git a/drivers/tty/serial/sh-sci.h b/drivers/tty/serial/sh-sci.h index 0b9e804e61a9..c0dfe4382898 100644 --- a/drivers/tty/serial/sh-sci.h +++ b/drivers/tty/serial/sh-sci.h @@ -2,7 +2,6 @@ #include #include #include -#include #define SCI_MAJOR 204 #define SCI_MINOR_START 8 diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c index 5e93e8d40f59..8602ff357321 100644 --- a/drivers/tty/serial/stm32-usart.c +++ b/drivers/tty/serial/stm32-usart.c @@ -31,6 +31,7 @@ #include #include +#include "serial_mctrl_gpio.h" #include "stm32-usart.h" static void stm32_stop_tx(struct uart_port *port); @@ -158,9 +159,7 @@ static int stm32_init_rs485(struct uart_port *port, if (!pdev->dev.of_node) return -ENODEV; - uart_get_rs485_mode(&pdev->dev, rs485conf); - - return 0; + return uart_get_rs485_mode(port); } static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res, @@ -510,12 +509,29 @@ static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl) stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE); else stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE); + + mctrl_gpio_set(stm32_port->gpios, mctrl); } static unsigned int stm32_get_mctrl(struct uart_port *port) { + struct stm32_port *stm32_port = to_stm32_port(port); + unsigned int ret; + /* This routine is used to get signals of: DCD, DSR, RI, and CTS */ - return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; + ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; + + return mctrl_gpio_get(stm32_port->gpios, &ret); +} + +static void stm32_enable_ms(struct uart_port *port) +{ + mctrl_gpio_enable_ms(to_stm32_port(port)->gpios); +} + +static void stm32_disable_ms(struct uart_port *port) +{ + mctrl_gpio_disable_ms(to_stm32_port(port)->gpios); } /* Transmit stop */ @@ -626,6 +642,9 @@ static void stm32_shutdown(struct uart_port *port) u32 val, isr; int ret; + /* Disable modem control interrupts */ + stm32_disable_ms(port); + val = USART_CR1_TXEIE | USART_CR1_TE; val |= stm32_port->cr1_irq | USART_CR1_RE; val |= BIT(cfg->uart_enable_bit); @@ -764,6 +783,12 @@ static void stm32_set_termios(struct uart_port *port, struct ktermios *termios, cr3 |= USART_CR3_CTSE | USART_CR3_RTSE; } + /* Handle modem control interrupts */ + if (UART_ENABLE_MS(port, termios->c_cflag)) + stm32_enable_ms(port); + else + stm32_disable_ms(port); + usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); /* @@ -898,6 +923,7 @@ static const struct uart_ops stm32_uart_ops = { .throttle = stm32_throttle, .unthrottle = stm32_unthrottle, .stop_rx = stm32_stop_rx, + .enable_ms = stm32_enable_ms, .break_ctl = stm32_break_ctl, .startup = stm32_startup, .shutdown = stm32_shutdown, @@ -931,7 +957,9 @@ static int stm32_init_port(struct stm32_port *stm32port, port->rs485_config = stm32_config_rs485; - stm32_init_rs485(port, pdev); + ret = stm32_init_rs485(port, pdev); + if (ret) + return ret; if (stm32port->info->cfg.has_wakeup) { stm32port->wakeirq = platform_get_irq(pdev, 1); @@ -960,10 +988,31 @@ static int stm32_init_port(struct stm32_port *stm32port, stm32port->port.uartclk = clk_get_rate(stm32port->clk); if (!stm32port->port.uartclk) { - clk_disable_unprepare(stm32port->clk); ret = -EINVAL; + goto err_clk; } + stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0); + if (IS_ERR(stm32port->gpios)) { + ret = PTR_ERR(stm32port->gpios); + goto err_clk; + } + + /* Both CTS/RTS gpios and "st,hw-flow-ctrl" should not be specified */ + if (stm32port->hw_flow_control) { + if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) || + mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) { + dev_err(&pdev->dev, "Conflicting RTS/CTS config\n"); + ret = -EINVAL; + goto err_clk; + } + } + + return ret; + +err_clk: + clk_disable_unprepare(stm32port->clk); + return ret; } @@ -1375,7 +1424,18 @@ static int __maybe_unused stm32_serial_suspend(struct device *dev) else stm32_serial_enable_wakeup(port, false); - pinctrl_pm_select_sleep_state(dev); + /* + * When "no_console_suspend" is enabled, keep the pinctrl default state + * and rely on bootloader stage to restore this state upon resume. + * Otherwise, apply the idle or sleep states depending on wakeup + * capabilities. + */ + if (console_suspend_enabled || !uart_console(port)) { + if (device_may_wakeup(dev)) + pinctrl_pm_select_idle_state(dev); + else + pinctrl_pm_select_sleep_state(dev); + } return 0; } diff --git a/drivers/tty/serial/stm32-usart.h b/drivers/tty/serial/stm32-usart.h index db8bf0d4982d..d4c916e78d40 100644 --- a/drivers/tty/serial/stm32-usart.h +++ b/drivers/tty/serial/stm32-usart.h @@ -274,6 +274,7 @@ struct stm32_port { bool fifoen; int wakeirq; int rdr_mask; /* receive data register mask */ + struct mctrl_gpios *gpios; /* modem control gpios */ }; static struct stm32_port stm32_ports[STM32_MAX_PORTS]; diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c index 35e9e8faf8de..b9d672af8b65 100644 --- a/drivers/tty/serial/xilinx_uartps.c +++ b/drivers/tty/serial/xilinx_uartps.c @@ -1235,9 +1235,7 @@ static void cdns_uart_console_write(struct console *co, const char *s, writel(ctrl, port->membase + CDNS_UART_CR); uart_console_write(port, s, count, cdns_uart_console_putchar); - while ((readl(port->membase + CDNS_UART_SR) & - (CDNS_UART_SR_TXEMPTY | CDNS_UART_SR_TACTIVE)) != - CDNS_UART_SR_TXEMPTY) + while (cdns_uart_tx_empty(port) != TIOCSER_TEMT) cpu_relax(); /* restore interrupt state */ @@ -1262,6 +1260,7 @@ static int cdns_uart_console_setup(struct console *co, char *options) int bits = 8; int parity = 'n'; int flow = 'n'; + unsigned long time_out; if (!port->membase) { pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n", @@ -1272,6 +1271,13 @@ static int cdns_uart_console_setup(struct console *co, char *options) if (options) uart_parse_options(options, &baud, &parity, &bits, &flow); + /* Wait for tx_empty before setting up the console */ + time_out = jiffies + usecs_to_jiffies(TX_TIMEOUT); + + while (time_before(jiffies, time_out) && + cdns_uart_tx_empty(port) != TIOCSER_TEMT) + cpu_relax(); + return uart_set_options(port, co, baud, parity, bits, flow); } diff --git a/drivers/tty/sysrq.c b/drivers/tty/sysrq.c index 0dc3878794fd..477cdc1e9cf3 100644 --- a/drivers/tty/sysrq.c +++ b/drivers/tty/sysrq.c @@ -106,7 +106,7 @@ static void sysrq_handle_loglevel(int key) pr_info("Loglevel set to %d\n", i); console_loglevel = i; } -static struct sysrq_key_op sysrq_loglevel_op = { +static const struct sysrq_key_op sysrq_loglevel_op = { .handler = sysrq_handle_loglevel, .help_msg = "loglevel(0-9)", .action_msg = "Changing Loglevel", @@ -119,14 +119,14 @@ static void sysrq_handle_SAK(int key) struct work_struct *SAK_work = &vc_cons[fg_console].SAK_work; schedule_work(SAK_work); } -static struct sysrq_key_op sysrq_SAK_op = { +static const struct sysrq_key_op sysrq_SAK_op = { .handler = sysrq_handle_SAK, .help_msg = "sak(k)", .action_msg = "SAK", .enable_mask = SYSRQ_ENABLE_KEYBOARD, }; #else -#define sysrq_SAK_op (*(struct sysrq_key_op *)NULL) +#define sysrq_SAK_op (*(const struct sysrq_key_op *)NULL) #endif #ifdef CONFIG_VT @@ -135,14 +135,14 @@ static void sysrq_handle_unraw(int key) vt_reset_unicode(fg_console); } -static struct sysrq_key_op sysrq_unraw_op = { +static const struct sysrq_key_op sysrq_unraw_op = { .handler = sysrq_handle_unraw, .help_msg = "unraw(r)", .action_msg = "Keyboard mode set to system default", .enable_mask = SYSRQ_ENABLE_KEYBOARD, }; #else -#define sysrq_unraw_op (*(struct sysrq_key_op *)NULL) +#define sysrq_unraw_op (*(const struct sysrq_key_op *)NULL) #endif /* CONFIG_VT */ static void sysrq_handle_crash(int key) @@ -152,7 +152,7 @@ static void sysrq_handle_crash(int key) panic("sysrq triggered crash\n"); } -static struct sysrq_key_op sysrq_crash_op = { +static const struct sysrq_key_op sysrq_crash_op = { .handler = sysrq_handle_crash, .help_msg = "crash(c)", .action_msg = "Trigger a crash", @@ -165,18 +165,20 @@ static void sysrq_handle_reboot(int key) local_irq_enable(); emergency_restart(); } -static struct sysrq_key_op sysrq_reboot_op = { +static const struct sysrq_key_op sysrq_reboot_op = { .handler = sysrq_handle_reboot, .help_msg = "reboot(b)", .action_msg = "Resetting", .enable_mask = SYSRQ_ENABLE_BOOT, }; +const struct sysrq_key_op *__sysrq_reboot_op = &sysrq_reboot_op; + static void sysrq_handle_sync(int key) { emergency_sync(); } -static struct sysrq_key_op sysrq_sync_op = { +static const struct sysrq_key_op sysrq_sync_op = { .handler = sysrq_handle_sync, .help_msg = "sync(s)", .action_msg = "Emergency Sync", @@ -188,7 +190,7 @@ static void sysrq_handle_show_timers(int key) sysrq_timer_list_show(); } -static struct sysrq_key_op sysrq_show_timers_op = { +static const struct sysrq_key_op sysrq_show_timers_op = { .handler = sysrq_handle_show_timers, .help_msg = "show-all-timers(q)", .action_msg = "Show clockevent devices & pending hrtimers (no others)", @@ -198,7 +200,7 @@ static void sysrq_handle_mountro(int key) { emergency_remount(); } -static struct sysrq_key_op sysrq_mountro_op = { +static const struct sysrq_key_op sysrq_mountro_op = { .handler = sysrq_handle_mountro, .help_msg = "unmount(u)", .action_msg = "Emergency Remount R/O", @@ -211,13 +213,13 @@ static void sysrq_handle_showlocks(int key) debug_show_all_locks(); } -static struct sysrq_key_op sysrq_showlocks_op = { +static const struct sysrq_key_op sysrq_showlocks_op = { .handler = sysrq_handle_showlocks, .help_msg = "show-all-locks(d)", .action_msg = "Show Locks Held", }; #else -#define sysrq_showlocks_op (*(struct sysrq_key_op *)NULL) +#define sysrq_showlocks_op (*(const struct sysrq_key_op *)NULL) #endif #ifdef CONFIG_SMP @@ -264,7 +266,7 @@ static void sysrq_handle_showallcpus(int key) } } -static struct sysrq_key_op sysrq_showallcpus_op = { +static const struct sysrq_key_op sysrq_showallcpus_op = { .handler = sysrq_handle_showallcpus, .help_msg = "show-backtrace-all-active-cpus(l)", .action_msg = "Show backtrace of all active CPUs", @@ -282,7 +284,7 @@ static void sysrq_handle_showregs(int key) show_regs(regs); perf_event_print_debug(); } -static struct sysrq_key_op sysrq_showregs_op = { +static const struct sysrq_key_op sysrq_showregs_op = { .handler = sysrq_handle_showregs, .help_msg = "show-registers(p)", .action_msg = "Show Regs", @@ -294,7 +296,7 @@ static void sysrq_handle_showstate(int key) show_state(); show_workqueue_state(); } -static struct sysrq_key_op sysrq_showstate_op = { +static const struct sysrq_key_op sysrq_showstate_op = { .handler = sysrq_handle_showstate, .help_msg = "show-task-states(t)", .action_msg = "Show State", @@ -305,7 +307,7 @@ static void sysrq_handle_showstate_blocked(int key) { show_state_filter(TASK_UNINTERRUPTIBLE); } -static struct sysrq_key_op sysrq_showstate_blocked_op = { +static const struct sysrq_key_op sysrq_showstate_blocked_op = { .handler = sysrq_handle_showstate_blocked, .help_msg = "show-blocked-tasks(w)", .action_msg = "Show Blocked State", @@ -319,21 +321,21 @@ static void sysrq_ftrace_dump(int key) { ftrace_dump(DUMP_ALL); } -static struct sysrq_key_op sysrq_ftrace_dump_op = { +static const struct sysrq_key_op sysrq_ftrace_dump_op = { .handler = sysrq_ftrace_dump, .help_msg = "dump-ftrace-buffer(z)", .action_msg = "Dump ftrace buffer", .enable_mask = SYSRQ_ENABLE_DUMP, }; #else -#define sysrq_ftrace_dump_op (*(struct sysrq_key_op *)NULL) +#define sysrq_ftrace_dump_op (*(const struct sysrq_key_op *)NULL) #endif static void sysrq_handle_showmem(int key) { show_mem(0, NULL); } -static struct sysrq_key_op sysrq_showmem_op = { +static const struct sysrq_key_op sysrq_showmem_op = { .handler = sysrq_handle_showmem, .help_msg = "show-memory-usage(m)", .action_msg = "Show Memory", @@ -364,7 +366,7 @@ static void sysrq_handle_term(int key) send_sig_all(SIGTERM); console_loglevel = CONSOLE_LOGLEVEL_DEBUG; } -static struct sysrq_key_op sysrq_term_op = { +static const struct sysrq_key_op sysrq_term_op = { .handler = sysrq_handle_term, .help_msg = "terminate-all-tasks(e)", .action_msg = "Terminate All Tasks", @@ -394,7 +396,7 @@ static void sysrq_handle_moom(int key) { schedule_work(&moom_work); } -static struct sysrq_key_op sysrq_moom_op = { +static const struct sysrq_key_op sysrq_moom_op = { .handler = sysrq_handle_moom, .help_msg = "memory-full-oom-kill(f)", .action_msg = "Manual OOM execution", @@ -406,7 +408,7 @@ static void sysrq_handle_thaw(int key) { emergency_thaw_all(); } -static struct sysrq_key_op sysrq_thaw_op = { +static const struct sysrq_key_op sysrq_thaw_op = { .handler = sysrq_handle_thaw, .help_msg = "thaw-filesystems(j)", .action_msg = "Emergency Thaw of all frozen filesystems", @@ -419,7 +421,7 @@ static void sysrq_handle_kill(int key) send_sig_all(SIGKILL); console_loglevel = CONSOLE_LOGLEVEL_DEBUG; } -static struct sysrq_key_op sysrq_kill_op = { +static const struct sysrq_key_op sysrq_kill_op = { .handler = sysrq_handle_kill, .help_msg = "kill-all-tasks(i)", .action_msg = "Kill All Tasks", @@ -430,7 +432,7 @@ static void sysrq_handle_unrt(int key) { normalize_rt_tasks(); } -static struct sysrq_key_op sysrq_unrt_op = { +static const struct sysrq_key_op sysrq_unrt_op = { .handler = sysrq_handle_unrt, .help_msg = "nice-all-RT-tasks(n)", .action_msg = "Nice All RT Tasks", @@ -440,7 +442,7 @@ static struct sysrq_key_op sysrq_unrt_op = { /* Key Operations table and lock */ static DEFINE_SPINLOCK(sysrq_key_table_lock); -static struct sysrq_key_op *sysrq_key_table[36] = { +static const struct sysrq_key_op *sysrq_key_table[36] = { &sysrq_loglevel_op, /* 0 */ &sysrq_loglevel_op, /* 1 */ &sysrq_loglevel_op, /* 2 */ @@ -516,9 +518,9 @@ static int sysrq_key_table_key2index(int key) /* * get and put functions for the table, exposed to modules. */ -struct sysrq_key_op *__sysrq_get_key_op(int key) +static const struct sysrq_key_op *__sysrq_get_key_op(int key) { - struct sysrq_key_op *op_p = NULL; + const struct sysrq_key_op *op_p = NULL; int i; i = sysrq_key_table_key2index(key); @@ -528,7 +530,7 @@ struct sysrq_key_op *__sysrq_get_key_op(int key) return op_p; } -static void __sysrq_put_key_op(int key, struct sysrq_key_op *op_p) +static void __sysrq_put_key_op(int key, const struct sysrq_key_op *op_p) { int i = sysrq_key_table_key2index(key); @@ -538,7 +540,7 @@ static void __sysrq_put_key_op(int key, struct sysrq_key_op *op_p) void __handle_sysrq(int key, bool check_mask) { - struct sysrq_key_op *op_p; + const struct sysrq_key_op *op_p; int orig_log_level; int orig_suppress_printk; int i; @@ -1061,8 +1063,8 @@ int sysrq_toggle_support(int enable_mask) } EXPORT_SYMBOL_GPL(sysrq_toggle_support); -static int __sysrq_swap_key_ops(int key, struct sysrq_key_op *insert_op_p, - struct sysrq_key_op *remove_op_p) +static int __sysrq_swap_key_ops(int key, const struct sysrq_key_op *insert_op_p, + const struct sysrq_key_op *remove_op_p) { int retval; @@ -1085,13 +1087,13 @@ static int __sysrq_swap_key_ops(int key, struct sysrq_key_op *insert_op_p, return retval; } -int register_sysrq_key(int key, struct sysrq_key_op *op_p) +int register_sysrq_key(int key, const struct sysrq_key_op *op_p) { return __sysrq_swap_key_ops(key, op_p, NULL); } EXPORT_SYMBOL(register_sysrq_key); -int unregister_sysrq_key(int key, struct sysrq_key_op *op_p) +int unregister_sysrq_key(int key, const struct sysrq_key_op *op_p) { return __sysrq_swap_key_ops(key, NULL, op_p); } diff --git a/drivers/tty/vcc.c b/drivers/tty/vcc.c index d2a1e1228c82..9ffd42e333b8 100644 --- a/drivers/tty/vcc.c +++ b/drivers/tty/vcc.c @@ -605,6 +605,7 @@ static int vcc_probe(struct vio_dev *vdev, const struct vio_device_id *id) port->index = vcc_table_add(port); if (port->index == -1) { pr_err("VCC: no more TTY indices left for allocation\n"); + rv = -ENOMEM; goto free_ldc; } diff --git a/drivers/tty/vt/keyboard.c b/drivers/tty/vt/keyboard.c index 15d33fa0c925..568b2171f335 100644 --- a/drivers/tty/vt/keyboard.c +++ b/drivers/tty/vt/keyboard.c @@ -127,7 +127,11 @@ static DEFINE_SPINLOCK(func_buf_lock); /* guard 'func_buf' and friends */ static unsigned long key_down[BITS_TO_LONGS(KEY_CNT)]; /* keyboard key bitmap */ static unsigned char shift_down[NR_SHIFT]; /* shift state counters.. */ static bool dead_key_next; -static int npadch = -1; /* -1 or number assembled on pad */ + +/* Handles a number being assembled on the number pad */ +static bool npadch_active; +static unsigned int npadch_value; + static unsigned int diacr; static char rep; /* flag telling character repeat */ @@ -845,12 +849,12 @@ static void k_shift(struct vc_data *vc, unsigned char value, char up_flag) shift_state &= ~(1 << value); /* kludge */ - if (up_flag && shift_state != old_state && npadch != -1) { + if (up_flag && shift_state != old_state && npadch_active) { if (kbd->kbdmode == VC_UNICODE) - to_utf8(vc, npadch); + to_utf8(vc, npadch_value); else - put_queue(vc, npadch & 0xff); - npadch = -1; + put_queue(vc, npadch_value & 0xff); + npadch_active = false; } } @@ -868,7 +872,7 @@ static void k_meta(struct vc_data *vc, unsigned char value, char up_flag) static void k_ascii(struct vc_data *vc, unsigned char value, char up_flag) { - int base; + unsigned int base; if (up_flag) return; @@ -882,10 +886,12 @@ static void k_ascii(struct vc_data *vc, unsigned char value, char up_flag) base = 16; } - if (npadch == -1) - npadch = value; - else - npadch = npadch * base + value; + if (!npadch_active) { + npadch_value = 0; + npadch_active = true; + } + + npadch_value = npadch_value * base + value; } static void k_lock(struct vc_data *vc, unsigned char value, char up_flag) diff --git a/drivers/tty/vt/selection.c b/drivers/tty/vt/selection.c index d54a549c5892..31bb3647a99c 100644 --- a/drivers/tty/vt/selection.c +++ b/drivers/tty/vt/selection.c @@ -185,47 +185,54 @@ int set_selection_user(const struct tiocl_selection __user *sel, return set_selection_kernel(&v, tty); } -static int __set_selection_kernel(struct tiocl_selection *v, struct tty_struct *tty) +static int vc_selection_store_chars(struct vc_data *vc, bool unicode) { - struct vc_data *vc = vc_cons[fg_console].d; - int new_sel_start, new_sel_end, spc; char *bp, *obp; - int i, ps, pe; - u32 c; - int ret = 0; - bool unicode; + unsigned int i; - poke_blanked_console(); - - v->xs = min_t(u16, v->xs - 1, vc->vc_cols - 1); - v->ys = min_t(u16, v->ys - 1, vc->vc_rows - 1); - v->xe = min_t(u16, v->xe - 1, vc->vc_cols - 1); - v->ye = min_t(u16, v->ye - 1, vc->vc_rows - 1); - ps = v->ys * vc->vc_size_row + (v->xs << 1); - pe = v->ye * vc->vc_size_row + (v->xe << 1); - - if (v->sel_mode == TIOCL_SELCLEAR) { - /* useful for screendump without selection highlights */ + /* Allocate a new buffer before freeing the old one ... */ + /* chars can take up to 4 bytes with unicode */ + bp = kmalloc_array((vc_sel.end - vc_sel.start) / 2 + 1, unicode ? 4 : 1, + GFP_KERNEL); + if (!bp) { + printk(KERN_WARNING "selection: kmalloc() failed\n"); clear_selection(); - return 0; + return -ENOMEM; } + kfree(vc_sel.buffer); + vc_sel.buffer = bp; - if (mouse_reporting() && (v->sel_mode & TIOCL_SELMOUSEREPORT)) { - mouse_report(tty, v->sel_mode & TIOCL_SELBUTTONMASK, v->xs, - v->ys); - return 0; + obp = bp; + for (i = vc_sel.start; i <= vc_sel.end; i += 2) { + u32 c = sel_pos(i, unicode); + if (unicode) + bp += store_utf8(c, bp); + else + *bp++ = c; + if (!isspace(c)) + obp = bp; + if (!((i + 2) % vc->vc_size_row)) { + /* strip trailing blanks from line and add newline, + unless non-space at end of line. */ + if (obp != bp) { + bp = obp; + *bp++ = '\r'; + } + obp = bp; + } } + vc_sel.buf_len = bp - vc_sel.buffer; - if (ps > pe) /* make vc_sel.start <= vc_sel.end */ - swap(ps, pe); + return 0; +} - if (vc_sel.cons != vc_cons[fg_console].d) { - clear_selection(); - vc_sel.cons = vc_cons[fg_console].d; - } - unicode = vt_do_kdgkbmode(fg_console) == K_UNICODE; +static int vc_do_selection(struct vc_data *vc, unsigned short mode, int ps, + int pe) +{ + int new_sel_start, new_sel_end, spc; + bool unicode = vt_do_kdgkbmode(fg_console) == K_UNICODE; - switch (v->sel_mode) { + switch (mode) { case TIOCL_SELCHAR: /* character-by-character selection */ new_sel_start = ps; new_sel_end = pe; @@ -303,40 +310,44 @@ static int __set_selection_kernel(struct tiocl_selection *v, struct tty_struct * vc_sel.start = new_sel_start; vc_sel.end = new_sel_end; - /* Allocate a new buffer before freeing the old one ... */ - /* chars can take up to 4 bytes with unicode */ - bp = kmalloc_array((vc_sel.end - vc_sel.start) / 2 + 1, unicode ? 4 : 1, - GFP_KERNEL); - if (!bp) { - printk(KERN_WARNING "selection: kmalloc() failed\n"); + return vc_selection_store_chars(vc, unicode); +} + +static int vc_selection(struct vc_data *vc, struct tiocl_selection *v, + struct tty_struct *tty) +{ + int ps, pe; + + poke_blanked_console(); + + if (v->sel_mode == TIOCL_SELCLEAR) { + /* useful for screendump without selection highlights */ clear_selection(); - return -ENOMEM; + return 0; } - kfree(vc_sel.buffer); - vc_sel.buffer = bp; - obp = bp; - for (i = vc_sel.start; i <= vc_sel.end; i += 2) { - c = sel_pos(i, unicode); - if (unicode) - bp += store_utf8(c, bp); - else - *bp++ = c; - if (!isspace(c)) - obp = bp; - if (! ((i + 2) % vc->vc_size_row)) { - /* strip trailing blanks from line and add newline, - unless non-space at end of line. */ - if (obp != bp) { - bp = obp; - *bp++ = '\r'; - } - obp = bp; - } + v->xs = min_t(u16, v->xs - 1, vc->vc_cols - 1); + v->ys = min_t(u16, v->ys - 1, vc->vc_rows - 1); + v->xe = min_t(u16, v->xe - 1, vc->vc_cols - 1); + v->ye = min_t(u16, v->ye - 1, vc->vc_rows - 1); + + if (mouse_reporting() && (v->sel_mode & TIOCL_SELMOUSEREPORT)) { + mouse_report(tty, v->sel_mode & TIOCL_SELBUTTONMASK, v->xs, + v->ys); + return 0; } - vc_sel.buf_len = bp - vc_sel.buffer; - return ret; + ps = v->ys * vc->vc_size_row + (v->xs << 1); + pe = v->ye * vc->vc_size_row + (v->xe << 1); + if (ps > pe) /* make vc_sel.start <= vc_sel.end */ + swap(ps, pe); + + if (vc_sel.cons != vc) { + clear_selection(); + vc_sel.cons = vc; + } + + return vc_do_selection(vc, v->sel_mode, ps, pe); } int set_selection_kernel(struct tiocl_selection *v, struct tty_struct *tty) @@ -345,7 +356,7 @@ int set_selection_kernel(struct tiocl_selection *v, struct tty_struct *tty) mutex_lock(&vc_sel.lock); console_lock(); - ret = __set_selection_kernel(v, tty); + ret = vc_selection(vc_cons[fg_console].d, v, tty); console_unlock(); mutex_unlock(&vc_sel.lock); diff --git a/drivers/uio/uio.c b/drivers/uio/uio.c index 6e725c6c6256..73efb80815db 100644 --- a/drivers/uio/uio.c +++ b/drivers/uio/uio.c @@ -398,7 +398,7 @@ static void uio_dev_del_attributes(struct uio_device *idev) static int uio_get_minor(struct uio_device *idev) { - int retval = -ENOMEM; + int retval; mutex_lock(&minor_lock); retval = idr_alloc(&uio_idr, idev, 0, UIO_MAX_DEVICES, GFP_KERNEL); diff --git a/drivers/uio/uio_dmem_genirq.c b/drivers/uio/uio_dmem_genirq.c index f6ab3f28c838..6e27fe4fcca3 100644 --- a/drivers/uio/uio_dmem_genirq.c +++ b/drivers/uio/uio_dmem_genirq.c @@ -44,7 +44,6 @@ static int uio_dmem_genirq_open(struct uio_info *info, struct inode *inode) { struct uio_dmem_genirq_platdata *priv = info->priv; struct uio_mem *uiomem; - int ret = 0; int dmem_region = priv->dmem_region_start; uiomem = &priv->uioinfo->mem[priv->dmem_region_start]; @@ -68,7 +67,7 @@ static int uio_dmem_genirq_open(struct uio_info *info, struct inode *inode) mutex_unlock(&priv->alloc_lock); /* Wait until the Runtime PM code has woken up the device */ pm_runtime_get_sync(&priv->pdev->dev); - return ret; + return 0; } static int uio_dmem_genirq_release(struct uio_info *info, struct inode *inode) diff --git a/drivers/uio/uio_hv_generic.c b/drivers/uio/uio_hv_generic.c index 3c5169eb23f5..4dae2320b103 100644 --- a/drivers/uio/uio_hv_generic.c +++ b/drivers/uio/uio_hv_generic.c @@ -361,6 +361,7 @@ hv_uio_remove(struct hv_device *dev) if (!pdata) return 0; + sysfs_remove_bin_file(&dev->channel->kobj, &ring_buffer_bin_attr); uio_unregister_device(&pdata->info); hv_uio_cleanup(dev, pdata); hv_set_drvdata(dev, NULL); diff --git a/drivers/visorbus/controlvmchannel.h b/drivers/visorbus/controlvmchannel.h index 8c57562a070a..c87213554427 100644 --- a/drivers/visorbus/controlvmchannel.h +++ b/drivers/visorbus/controlvmchannel.h @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2010 - 2015 UNISYS CORPORATION * All rights reserved. diff --git a/drivers/visorbus/vbuschannel.h b/drivers/visorbus/vbuschannel.h index b1dce26166bf..4aaf6564eb9f 100644 --- a/drivers/visorbus/vbuschannel.h +++ b/drivers/visorbus/vbuschannel.h @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2010 - 2015 UNISYS CORPORATION * All rights reserved. diff --git a/drivers/visorbus/visorbus_private.h b/drivers/visorbus/visorbus_private.h index 366380b7f8d9..6956de605827 100644 --- a/drivers/visorbus/visorbus_private.h +++ b/drivers/visorbus/visorbus_private.h @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2010 - 2015 UNISYS CORPORATION * All rights reserved. diff --git a/drivers/w1/masters/omap_hdq.c b/drivers/w1/masters/omap_hdq.c index aa09f8527776..bf2ec59c1f9d 100644 --- a/drivers/w1/masters/omap_hdq.c +++ b/drivers/w1/masters/omap_hdq.c @@ -54,10 +54,10 @@ MODULE_PARM_DESC(w1_id, "1-wire id for the slave detection in HDQ mode"); struct hdq_data { struct device *dev; void __iomem *hdq_base; - /* lock status update */ + /* lock read/write/break operations */ struct mutex hdq_mutex; + /* interrupt status and a lock for it */ u8 hdq_irqstatus; - /* device lock */ spinlock_t hdq_spinlock; /* mode: 0-HDQ 1-W1 */ int mode; @@ -120,13 +120,18 @@ static int hdq_wait_for_flag(struct hdq_data *hdq_data, u32 offset, } /* Clear saved irqstatus after using an interrupt */ -static void hdq_reset_irqstatus(struct hdq_data *hdq_data) +static u8 hdq_reset_irqstatus(struct hdq_data *hdq_data, u8 bits) { unsigned long irqflags; + u8 status; spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags); - hdq_data->hdq_irqstatus = 0; + status = hdq_data->hdq_irqstatus; + /* this is a read-modify-write */ + hdq_data->hdq_irqstatus &= ~bits; spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags); + + return status; } /* write out a byte and fill *status with HDQ_INT_STATUS */ @@ -135,6 +140,16 @@ static int hdq_write_byte(struct hdq_data *hdq_data, u8 val, u8 *status) int ret; u8 tmp_status; + ret = mutex_lock_interruptible(&hdq_data->hdq_mutex); + if (ret < 0) { + ret = -EINTR; + goto rtn; + } + + if (hdq_data->hdq_irqstatus) + dev_err(hdq_data->dev, "TX irqstatus not cleared (%02x)\n", + hdq_data->hdq_irqstatus); + *status = 0; hdq_reg_out(hdq_data, OMAP_HDQ_TX_DATA, val); @@ -144,18 +159,19 @@ static int hdq_write_byte(struct hdq_data *hdq_data, u8 val, u8 *status) OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO); /* wait for the TXCOMPLETE bit */ ret = wait_event_timeout(hdq_wait_queue, - hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT); + (hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_TXCOMPLETE), + OMAP_HDQ_TIMEOUT); + *status = hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_TXCOMPLETE); if (ret == 0) { dev_dbg(hdq_data->dev, "TX wait elapsed\n"); ret = -ETIMEDOUT; goto out; } - *status = hdq_data->hdq_irqstatus; /* check irqstatus */ if (!(*status & OMAP_HDQ_INT_STATUS_TXCOMPLETE)) { dev_dbg(hdq_data->dev, "timeout waiting for" - " TXCOMPLETE/RXCOMPLETE, %x", *status); + " TXCOMPLETE/RXCOMPLETE, %x\n", *status); ret = -ETIMEDOUT; goto out; } @@ -166,11 +182,12 @@ static int hdq_write_byte(struct hdq_data *hdq_data, u8 val, u8 *status) OMAP_HDQ_FLAG_CLEAR, &tmp_status); if (ret) { dev_dbg(hdq_data->dev, "timeout waiting GO bit" - " return to zero, %x", tmp_status); + " return to zero, %x\n", tmp_status); } out: - hdq_reset_irqstatus(hdq_data); + mutex_unlock(&hdq_data->hdq_mutex); +rtn: return ret; } @@ -181,9 +198,9 @@ static irqreturn_t hdq_isr(int irq, void *_hdq) unsigned long irqflags; spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags); - hdq_data->hdq_irqstatus = hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS); + hdq_data->hdq_irqstatus |= hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS); spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags); - dev_dbg(hdq_data->dev, "hdq_isr: %x", hdq_data->hdq_irqstatus); + dev_dbg(hdq_data->dev, "hdq_isr: %x\n", hdq_data->hdq_irqstatus); if (hdq_data->hdq_irqstatus & (OMAP_HDQ_INT_STATUS_TXCOMPLETE | OMAP_HDQ_INT_STATUS_RXCOMPLETE @@ -230,6 +247,10 @@ static int omap_hdq_break(struct hdq_data *hdq_data) goto rtn; } + if (hdq_data->hdq_irqstatus) + dev_err(hdq_data->dev, "break irqstatus not cleared (%02x)\n", + hdq_data->hdq_irqstatus); + /* set the INIT and GO bit */ hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, OMAP_HDQ_CTRL_STATUS_INITIALIZATION | OMAP_HDQ_CTRL_STATUS_GO, @@ -238,18 +259,19 @@ static int omap_hdq_break(struct hdq_data *hdq_data) /* wait for the TIMEOUT bit */ ret = wait_event_timeout(hdq_wait_queue, - hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT); + (hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_TIMEOUT), + OMAP_HDQ_TIMEOUT); + tmp_status = hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_TIMEOUT); if (ret == 0) { dev_dbg(hdq_data->dev, "break wait elapsed\n"); ret = -EINTR; goto out; } - tmp_status = hdq_data->hdq_irqstatus; /* check irqstatus */ if (!(tmp_status & OMAP_HDQ_INT_STATUS_TIMEOUT)) { - dev_dbg(hdq_data->dev, "timeout waiting for TIMEOUT, %x", - tmp_status); + dev_dbg(hdq_data->dev, "timeout waiting for TIMEOUT, %x\n", + tmp_status); ret = -ETIMEDOUT; goto out; } @@ -275,10 +297,9 @@ static int omap_hdq_break(struct hdq_data *hdq_data) &tmp_status); if (ret) dev_dbg(hdq_data->dev, "timeout waiting INIT&GO bits" - " return to zero, %x", tmp_status); + " return to zero, %x\n", tmp_status); out: - hdq_reset_irqstatus(hdq_data); mutex_unlock(&hdq_data->hdq_mutex); rtn: return ret; @@ -309,12 +330,15 @@ static int hdq_read_byte(struct hdq_data *hdq_data, u8 *val) */ wait_event_timeout(hdq_wait_queue, (hdq_data->hdq_irqstatus - & OMAP_HDQ_INT_STATUS_RXCOMPLETE), + & (OMAP_HDQ_INT_STATUS_RXCOMPLETE | + OMAP_HDQ_INT_STATUS_TIMEOUT)), OMAP_HDQ_TIMEOUT); - + status = hdq_reset_irqstatus(hdq_data, + OMAP_HDQ_INT_STATUS_RXCOMPLETE | + OMAP_HDQ_INT_STATUS_TIMEOUT); hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, 0, OMAP_HDQ_CTRL_STATUS_DIR); - status = hdq_data->hdq_irqstatus; + /* check irqstatus */ if (!(status & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) { dev_dbg(hdq_data->dev, "timeout waiting for" @@ -322,11 +346,12 @@ static int hdq_read_byte(struct hdq_data *hdq_data, u8 *val) ret = -ETIMEDOUT; goto out; } + } else { /* interrupt had occurred before hdq_read_byte was called */ + hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_RXCOMPLETE); } /* the data is ready. Read it in! */ *val = hdq_reg_in(hdq_data, OMAP_HDQ_RX_DATA); out: - hdq_reset_irqstatus(hdq_data); mutex_unlock(&hdq_data->hdq_mutex); rtn: return ret; @@ -367,15 +392,15 @@ static u8 omap_w1_triplet(void *_hdq, u8 bdir) (hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_RXCOMPLETE), OMAP_HDQ_TIMEOUT); + /* Must clear irqstatus for another RXCOMPLETE interrupt */ + hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_RXCOMPLETE); + if (err == 0) { dev_dbg(hdq_data->dev, "RX wait elapsed\n"); goto out; } id_bit = (hdq_reg_in(_hdq, OMAP_HDQ_RX_DATA) & 0x01); - /* Must clear irqstatus for another RXCOMPLETE interrupt */ - hdq_reset_irqstatus(hdq_data); - /* read comp_bit */ hdq_reg_merge(_hdq, OMAP_HDQ_CTRL_STATUS, ctrl | OMAP_HDQ_CTRL_STATUS_DIR, mask); @@ -383,6 +408,9 @@ static u8 omap_w1_triplet(void *_hdq, u8 bdir) (hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_RXCOMPLETE), OMAP_HDQ_TIMEOUT); + /* Must clear irqstatus for another RXCOMPLETE interrupt */ + hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_RXCOMPLETE); + if (err == 0) { dev_dbg(hdq_data->dev, "RX wait elapsed\n"); goto out; @@ -409,6 +437,9 @@ static u8 omap_w1_triplet(void *_hdq, u8 bdir) (hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_TXCOMPLETE), OMAP_HDQ_TIMEOUT); + /* Must clear irqstatus for another TXCOMPLETE interrupt */ + hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_TXCOMPLETE); + if (err == 0) { dev_dbg(hdq_data->dev, "TX wait elapsed\n"); goto out; @@ -418,7 +449,6 @@ static u8 omap_w1_triplet(void *_hdq, u8 bdir) OMAP_HDQ_CTRL_STATUS_SINGLE); out: - hdq_reset_irqstatus(hdq_data); mutex_unlock(&hdq_data->hdq_mutex); rtn: pm_runtime_mark_last_busy(hdq_data->dev); @@ -464,7 +494,7 @@ static u8 omap_w1_read_byte(void *_hdq) ret = hdq_read_byte(hdq_data, &val); if (ret) - ret = -1; + val = -1; pm_runtime_mark_last_busy(hdq_data->dev); pm_runtime_put_autosuspend(hdq_data->dev); diff --git a/drivers/w1/slaves/w1_ds2430.c b/drivers/w1/slaves/w1_ds2430.c index 6fb0563fb2ae..75bb8a88620b 100644 --- a/drivers/w1/slaves/w1_ds2430.c +++ b/drivers/w1/slaves/w1_ds2430.c @@ -290,6 +290,6 @@ static struct w1_family w1_family_14 = { module_w1_family(w1_family_14); MODULE_AUTHOR("Angelo Dureghello "); -MODULE_DESCRIPTION("w1 family 14 driver for DS2430, 256kb EEPROM"); +MODULE_DESCRIPTION("w1 family 14 driver for DS2430, 256b EEPROM"); MODULE_LICENSE("GPL"); MODULE_ALIAS("w1-family-" __stringify(W1_EEPROM_DS2430)); diff --git a/drivers/w1/slaves/w1_therm.c b/drivers/w1/slaves/w1_therm.c index e028e0092799..c1b4eda16719 100644 --- a/drivers/w1/slaves/w1_therm.c +++ b/drivers/w1/slaves/w1_therm.c @@ -16,6 +16,7 @@ #include #include #include +#include #include @@ -25,7 +26,8 @@ #define W1_THERM_DS1825 0x3B #define W1_THERM_DS28EA00 0x42 -/* Allow the strong pullup to be disabled, but default to enabled. +/* + * Allow the strong pullup to be disabled, but default to enabled. * If it was disabled a parasite powered device might not get the require * current to do a temperature conversion. If it is enabled parasite powered * devices have a better chance of getting the current required. @@ -41,42 +43,211 @@ static int w1_strong_pullup = 1; module_param_named(strong_pullup, w1_strong_pullup, int, 0); +/* Counter for devices supporting bulk reading */ +static u16 bulk_read_device_counter; /* =0 as per C standard */ + +/* This command should be in public header w1.h but is not */ +#define W1_RECALL_EEPROM 0xB8 + +/* Nb of try for an operation */ +#define W1_THERM_MAX_TRY 5 + +/* ms delay to retry bus mutex */ +#define W1_THERM_RETRY_DELAY 20 + +/* delay in ms to write in EEPROM */ +#define W1_THERM_EEPROM_WRITE_DELAY 10 + +#define EEPROM_CMD_WRITE "save" /* cmd for write eeprom sysfs */ +#define EEPROM_CMD_READ "restore" /* cmd for read eeprom sysfs */ +#define BULK_TRIGGER_CMD "trigger" /* cmd to trigger a bulk read */ + +#define MIN_TEMP -55 /* min temperature that can be mesured */ +#define MAX_TEMP 125 /* max temperature that can be mesured */ + +/* Helpers Macros */ + +/* + * return a pointer on the slave w1_therm_family_converter struct: + * always test family data existence before using this macro + */ +#define SLAVE_SPECIFIC_FUNC(sl) \ + (((struct w1_therm_family_data *)(sl->family_data))->specific_functions) + +/* + * return the power mode of the sl slave : 1-ext, 0-parasite, <0 unknown + * always test family data existence before using this macro + */ +#define SLAVE_POWERMODE(sl) \ + (((struct w1_therm_family_data *)(sl->family_data))->external_powered) + +/* + * return the resolution in bit of the sl slave : <0 unknown + * always test family data existence before using this macro + */ +#define SLAVE_RESOLUTION(sl) \ + (((struct w1_therm_family_data *)(sl->family_data))->resolution) + +/* + * return whether or not a converT command has been issued to the slave + * * 0: no bulk read is pending + * * -1: conversion is in progress + * * 1: conversion done, result to be read + */ +#define SLAVE_CONVERT_TRIGGERED(sl) \ + (((struct w1_therm_family_data *)(sl->family_data))->convert_triggered) + +/* return the address of the refcnt in the family data */ +#define THERM_REFCNT(family_data) \ + (&((struct w1_therm_family_data *)family_data)->refcnt) + +/* Structs definition */ + +/** + * struct w1_therm_family_converter - bind device specific functions + * @broken: flag for non-registred families + * @reserved: not used here + * @f: pointer to the device binding structure + * @convert: pointer to the device conversion function + * @get_conversion_time: pointer to the device conversion time function + * @set_resolution: pointer to the device set_resolution function + * @get_resolution: pointer to the device get_resolution function + * @write_data: pointer to the device writing function (2 or 3 bytes) + * @bulk_read: true if device family support bulk read, false otherwise + */ +struct w1_therm_family_converter { + u8 broken; + u16 reserved; + struct w1_family *f; + int (*convert)(u8 rom[9]); + int (*get_conversion_time)(struct w1_slave *sl); + int (*set_resolution)(struct w1_slave *sl, int val); + int (*get_resolution)(struct w1_slave *sl); + int (*write_data)(struct w1_slave *sl, const u8 *data); + bool bulk_read; +}; + +/** + * struct w1_therm_family_data - device data + * @rom: ROM device id (64bit Lasered ROM code + 1 CRC byte) + * @refcnt: ref count + * @external_powered: 1 device powered externally, + * 0 device parasite powered, + * -x error or undefined + * @resolution: current device resolution + * @convert_triggered: conversion state of the device + * @specific_functions: pointer to struct of device specific function + */ struct w1_therm_family_data { uint8_t rom[9]; atomic_t refcnt; + int external_powered; + int resolution; + int convert_triggered; + struct w1_therm_family_converter *specific_functions; }; +/** + * struct therm_info - store temperature reading + * @rom: read device data (8 data bytes + 1 CRC byte) + * @crc: computed crc from rom + * @verdict: 1 crc checked, 0 crc not matching + */ struct therm_info { u8 rom[9]; u8 crc; u8 verdict; }; -/* return the address of the refcnt in the family data */ -#define THERM_REFCNT(family_data) \ - (&((struct w1_therm_family_data *)family_data)->refcnt) +/* Hardware Functions declaration */ -static int w1_therm_add_slave(struct w1_slave *sl) -{ - sl->family_data = kzalloc(sizeof(struct w1_therm_family_data), - GFP_KERNEL); - if (!sl->family_data) - return -ENOMEM; - atomic_set(THERM_REFCNT(sl->family_data), 1); - return 0; -} +/** + * reset_select_slave() - reset and select a slave + * @sl: the slave to select + * + * Resets the bus and select the slave by sending a ROM MATCH cmd + * w1_reset_select_slave() from w1_io.c could not be used here because + * it sent a SKIP ROM command if only one device is on the line. + * At the beginning of the such process, sl->master->slave_count is 1 even if + * more devices are on the line, causing collision on the line. + * + * Context: The w1 master lock must be held. + * + * Return: 0 if success, negative kernel error code otherwise. + */ +static int reset_select_slave(struct w1_slave *sl); -static void w1_therm_remove_slave(struct w1_slave *sl) -{ - int refcnt = atomic_sub_return(1, THERM_REFCNT(sl->family_data)); +/** + * convert_t() - Query the device for temperature conversion and read + * @sl: pointer to the slave to read + * @info: pointer to a structure to store the read results + * + * Return: 0 if success, -kernel error code otherwise + */ +static int convert_t(struct w1_slave *sl, struct therm_info *info); - while (refcnt) { - msleep(1000); - refcnt = atomic_read(THERM_REFCNT(sl->family_data)); - } - kfree(sl->family_data); - sl->family_data = NULL; -} +/** + * read_scratchpad() - read the data in device RAM + * @sl: pointer to the slave to read + * @info: pointer to a structure to store the read results + * + * Return: 0 if success, -kernel error code otherwise + */ +static int read_scratchpad(struct w1_slave *sl, struct therm_info *info); + +/** + * write_scratchpad() - write nb_bytes in the device RAM + * @sl: pointer to the slave to write in + * @data: pointer to an array of 3 bytes, as 3 bytes MUST be written + * @nb_bytes: number of bytes to be written (2 for DS18S20, 3 otherwise) + * + * Return: 0 if success, -kernel error code otherwise + */ +static int write_scratchpad(struct w1_slave *sl, const u8 *data, u8 nb_bytes); + +/** + * copy_scratchpad() - Copy the content of scratchpad in device EEPROM + * @sl: slave involved + * + * Return: 0 if success, -kernel error code otherwise + */ +static int copy_scratchpad(struct w1_slave *sl); + +/** + * recall_eeprom() - Restore EEPROM data to device RAM + * @sl: slave involved + * + * Return: 0 if success, -kernel error code otherwise + */ +static int recall_eeprom(struct w1_slave *sl); + +/** + * read_powermode() - Query the power mode of the slave + * @sl: slave to retrieve the power mode + * + * Ask the device to get its power mode (external or parasite) + * and store the power status in the &struct w1_therm_family_data. + * + * Return: + * * 0 parasite powered device + * * 1 externally powered device + * * <0 kernel error code + */ +static int read_powermode(struct w1_slave *sl); + +/** + * trigger_bulk_read() - function to trigger a bulk read on the bus + * @dev_master: the device master of the bus + * + * Send a SKIP ROM follow by a CONVERT T commmand on the bus. + * It also set the status flag in each slave &struct w1_therm_family_data + * to signal that a conversion is in progress. + * + * Return: 0 if success, -kernel error code otherwise + */ +static int trigger_bulk_read(struct w1_master *dev_master); + +/* Sysfs interface declaration */ static ssize_t w1_slave_show(struct device *device, struct device_attribute *attr, char *buf); @@ -87,21 +258,103 @@ static ssize_t w1_slave_store(struct device *device, static ssize_t w1_seq_show(struct device *device, struct device_attribute *attr, char *buf); +static ssize_t temperature_show(struct device *device, + struct device_attribute *attr, char *buf); + +static ssize_t ext_power_show(struct device *device, + struct device_attribute *attr, char *buf); + +static ssize_t resolution_show(struct device *device, + struct device_attribute *attr, char *buf); + +static ssize_t resolution_store(struct device *device, + struct device_attribute *attr, const char *buf, size_t size); + +static ssize_t eeprom_store(struct device *device, + struct device_attribute *attr, const char *buf, size_t size); + +static ssize_t alarms_store(struct device *device, + struct device_attribute *attr, const char *buf, size_t size); + +static ssize_t alarms_show(struct device *device, + struct device_attribute *attr, char *buf); + +static ssize_t therm_bulk_read_store(struct device *device, + struct device_attribute *attr, const char *buf, size_t size); + +static ssize_t therm_bulk_read_show(struct device *device, + struct device_attribute *attr, char *buf); + +/* Attributes declarations */ + static DEVICE_ATTR_RW(w1_slave); static DEVICE_ATTR_RO(w1_seq); +static DEVICE_ATTR_RO(temperature); +static DEVICE_ATTR_RO(ext_power); +static DEVICE_ATTR_RW(resolution); +static DEVICE_ATTR_WO(eeprom); +static DEVICE_ATTR_RW(alarms); + +static DEVICE_ATTR_RW(therm_bulk_read); /* attribut at master level */ + +/* Interface Functions declaration */ + +/** + * w1_therm_add_slave() - Called when a new slave is discovered + * @sl: slave just discovered by the master. + * + * Called by the master when the slave is discovered on the bus. Used to + * initialize slave state before the beginning of any communication. + * + * Return: 0 - If success, negative kernel code otherwise + */ +static int w1_therm_add_slave(struct w1_slave *sl); + +/** + * w1_therm_remove_slave() - Called when a slave is removed + * @sl: slave to be removed. + * + * Called by the master when the slave is considered not to be on the bus + * anymore. Used to free memory. + */ +static void w1_therm_remove_slave(struct w1_slave *sl); + +/* Family attributes */ static struct attribute *w1_therm_attrs[] = { &dev_attr_w1_slave.attr, + &dev_attr_temperature.attr, + &dev_attr_ext_power.attr, + &dev_attr_resolution.attr, + &dev_attr_eeprom.attr, + &dev_attr_alarms.attr, + NULL, +}; + +static struct attribute *w1_ds18s20_attrs[] = { + &dev_attr_w1_slave.attr, + &dev_attr_temperature.attr, + &dev_attr_ext_power.attr, + &dev_attr_eeprom.attr, + &dev_attr_alarms.attr, NULL, }; static struct attribute *w1_ds28ea00_attrs[] = { &dev_attr_w1_slave.attr, &dev_attr_w1_seq.attr, + &dev_attr_temperature.attr, + &dev_attr_ext_power.attr, + &dev_attr_resolution.attr, + &dev_attr_eeprom.attr, + &dev_attr_alarms.attr, NULL, }; +/* Attribute groups */ + ATTRIBUTE_GROUPS(w1_therm); +ATTRIBUTE_GROUPS(w1_ds18s20); ATTRIBUTE_GROUPS(w1_ds28ea00); #if IS_REACHABLE(CONFIG_HWMON) @@ -154,6 +407,8 @@ static const struct hwmon_chip_info w1_chip_info = { #define W1_CHIPINFO NULL #endif +/* Family operations */ + static struct w1_family_ops w1_therm_fops = { .add_slave = w1_therm_add_slave, .remove_slave = w1_therm_remove_slave, @@ -161,6 +416,13 @@ static struct w1_family_ops w1_therm_fops = { .chip_info = W1_CHIPINFO, }; +static struct w1_family_ops w1_ds18s20_fops = { + .add_slave = w1_therm_add_slave, + .remove_slave = w1_therm_remove_slave, + .groups = w1_ds18s20_groups, + .chip_info = W1_CHIPINFO, +}; + static struct w1_family_ops w1_ds28ea00_fops = { .add_slave = w1_therm_add_slave, .remove_slave = w1_therm_remove_slave, @@ -168,9 +430,11 @@ static struct w1_family_ops w1_ds28ea00_fops = { .chip_info = W1_CHIPINFO, }; +/* Family binding operations struct */ + static struct w1_family w1_therm_family_DS18S20 = { .fid = W1_THERM_DS18S20, - .fops = &w1_therm_fops, + .fops = &w1_ds18s20_fops, }; static struct w1_family w1_therm_family_DS18B20 = { @@ -193,220 +457,111 @@ static struct w1_family w1_therm_family_DS1825 = { .fops = &w1_therm_fops, }; -struct w1_therm_family_converter { - u8 broken; - u16 reserved; - struct w1_family *f; - int (*convert)(u8 rom[9]); - int (*precision)(struct device *device, int val); - int (*eeprom)(struct device *device); -}; +/* Device dependent func */ -/* write configuration to eeprom */ -static inline int w1_therm_eeprom(struct device *device); - -/* Set precision for conversion */ -static inline int w1_DS18B20_precision(struct device *device, int val); -static inline int w1_DS18S20_precision(struct device *device, int val); - -/* The return value is millidegrees Centigrade. */ -static inline int w1_DS18B20_convert_temp(u8 rom[9]); -static inline int w1_DS18S20_convert_temp(u8 rom[9]); - -static struct w1_therm_family_converter w1_therm_families[] = { - { - .f = &w1_therm_family_DS18S20, - .convert = w1_DS18S20_convert_temp, - .precision = w1_DS18S20_precision, - .eeprom = w1_therm_eeprom - }, - { - .f = &w1_therm_family_DS1822, - .convert = w1_DS18B20_convert_temp, - .precision = w1_DS18S20_precision, - .eeprom = w1_therm_eeprom - }, - { - .f = &w1_therm_family_DS18B20, - .convert = w1_DS18B20_convert_temp, - .precision = w1_DS18B20_precision, - .eeprom = w1_therm_eeprom - }, - { - .f = &w1_therm_family_DS28EA00, - .convert = w1_DS18B20_convert_temp, - .precision = w1_DS18S20_precision, - .eeprom = w1_therm_eeprom - }, - { - .f = &w1_therm_family_DS1825, - .convert = w1_DS18B20_convert_temp, - .precision = w1_DS18S20_precision, - .eeprom = w1_therm_eeprom - } -}; - -static inline int w1_therm_eeprom(struct device *device) +static inline int w1_DS18B20_convert_time(struct w1_slave *sl) { - struct w1_slave *sl = dev_to_w1_slave(device); - struct w1_master *dev = sl->master; - u8 rom[9], external_power; - int ret, max_trying = 10; - u8 *family_data = sl->family_data; + int ret; - if (!sl->family_data) { - ret = -ENODEV; - goto error; - } + if (!sl->family_data) + return -ENODEV; /* device unknown */ - /* prevent the slave from going away in sleep */ - atomic_inc(THERM_REFCNT(family_data)); - - ret = mutex_lock_interruptible(&dev->bus_mutex); - if (ret != 0) - goto dec_refcnt; - - memset(rom, 0, sizeof(rom)); - - while (max_trying--) { - if (!w1_reset_select_slave(sl)) { - unsigned int tm = 10; - unsigned long sleep_rem; - - /* check if in parasite mode */ - w1_write_8(dev, W1_READ_PSUPPLY); - external_power = w1_read_8(dev); - - if (w1_reset_select_slave(sl)) - continue; - - /* 10ms strong pullup/delay after the copy command */ - if (w1_strong_pullup == 2 || - (!external_power && w1_strong_pullup)) - w1_next_pullup(dev, tm); - - w1_write_8(dev, W1_COPY_SCRATCHPAD); - - if (external_power) { - mutex_unlock(&dev->bus_mutex); - - sleep_rem = msleep_interruptible(tm); - if (sleep_rem != 0) { - ret = -EINTR; - goto dec_refcnt; - } - - ret = mutex_lock_interruptible(&dev->bus_mutex); - if (ret != 0) - goto dec_refcnt; - } else if (!w1_strong_pullup) { - sleep_rem = msleep_interruptible(tm); - if (sleep_rem != 0) { - ret = -EINTR; - goto mt_unlock; - } - } - - break; - } - } - -mt_unlock: - mutex_unlock(&dev->bus_mutex); -dec_refcnt: - atomic_dec(THERM_REFCNT(family_data)); -error: - return ret; -} - -/* DS18S20 does not feature configuration register */ -static inline int w1_DS18S20_precision(struct device *device, int val) -{ - return 0; -} - -static inline int w1_DS18B20_precision(struct device *device, int val) -{ - struct w1_slave *sl = dev_to_w1_slave(device); - struct w1_master *dev = sl->master; - u8 rom[9], crc; - int ret, max_trying = 10; - u8 *family_data = sl->family_data; - uint8_t precision_bits; - uint8_t mask = 0x60; - - if (val > 12 || val < 9) { - pr_warn("Unsupported precision\n"); - ret = -EINVAL; - goto error; - } - - if (!sl->family_data) { - ret = -ENODEV; - goto error; - } - - /* prevent the slave from going away in sleep */ - atomic_inc(THERM_REFCNT(family_data)); - - ret = mutex_lock_interruptible(&dev->bus_mutex); - if (ret != 0) - goto dec_refcnt; - - memset(rom, 0, sizeof(rom)); - - /* translate precision to bitmask (see datasheet page 9) */ - switch (val) { + /* return time in ms for conversion operation */ + switch (SLAVE_RESOLUTION(sl)) { case 9: - precision_bits = 0x00; + ret = 95; break; case 10: - precision_bits = 0x20; + ret = 190; break; case 11: - precision_bits = 0x40; + ret = 375; break; case 12: default: - precision_bits = 0x60; - break; + ret = 750; } - - while (max_trying--) { - crc = 0; - - if (!w1_reset_select_slave(sl)) { - int count = 0; - - /* read values to only alter precision bits */ - w1_write_8(dev, W1_READ_SCRATCHPAD); - count = w1_read_block(dev, rom, 9); - if (count != 9) - dev_warn(device, "w1_read_block() returned %u instead of 9.\n", count); - - crc = w1_calc_crc8(rom, 8); - if (rom[8] == crc) { - rom[4] = (rom[4] & ~mask) | (precision_bits & mask); - - if (!w1_reset_select_slave(sl)) { - w1_write_8(dev, W1_WRITE_SCRATCHPAD); - w1_write_8(dev, rom[2]); - w1_write_8(dev, rom[3]); - w1_write_8(dev, rom[4]); - - break; - } - } - } - } - - mutex_unlock(&dev->bus_mutex); -dec_refcnt: - atomic_dec(THERM_REFCNT(family_data)); -error: return ret; } +static inline int w1_DS18S20_convert_time(struct w1_slave *sl) +{ + (void)(sl); + return 750; /* always 750ms for DS18S20 */ +} + +static inline int w1_DS18B20_write_data(struct w1_slave *sl, + const u8 *data) +{ + return write_scratchpad(sl, data, 3); +} + +static inline int w1_DS18S20_write_data(struct w1_slave *sl, + const u8 *data) +{ + /* No config register */ + return write_scratchpad(sl, data, 2); +} + +static inline int w1_DS18B20_set_resolution(struct w1_slave *sl, int val) +{ + int ret; + u8 new_config_register[3]; /* array of data to be written */ + struct therm_info info; + + /* resolution of DS18B20 is in the range [9..12] bits */ + if (val < 9 || val > 12) + return -EINVAL; + + val -= 9; /* soustract 9 the lowest resolution in bit */ + val = (val << 5); /* shift to position bit 5 & bit 6 */ + + /* + * Read the scratchpad to change only the required bits + * (bit5 & bit 6 from byte 4) + */ + ret = read_scratchpad(sl, &info); + if (!ret) { + new_config_register[0] = info.rom[2]; + new_config_register[1] = info.rom[3]; + /* config register is byte 4 & mask 0b10011111*/ + new_config_register[2] = (info.rom[4] & 0x9F) | + (u8) val; + } else + return ret; + + /* Write data in the device RAM */ + ret = w1_DS18B20_write_data(sl, new_config_register); + + return ret; +} + +static inline int w1_DS18B20_get_resolution(struct w1_slave *sl) +{ + int ret; + u8 config_register; + struct therm_info info; + + ret = read_scratchpad(sl, &info); + + if (!ret) { + config_register = info.rom[4]; /* config register is byte 4 */ + config_register &= 0x60; /* 0b01100000 keep only bit 5 & 6 */ + config_register = (config_register >> 5); /* shift */ + config_register += 9; /* add 9 the lowest resolution in bit */ + ret = (int) config_register; + } + return ret; +} + +/** + * w1_DS18B20_convert_temp() - temperature computation for DS18B20 + * @rom: data read from device RAM (8 data bytes + 1 CRC byte) + * + * Can be called for any DS18B20 compliant device. + * + * Return: value in millidegrees Celsius. + */ static inline int w1_DS18B20_convert_temp(u8 rom[9]) { s16 t = le16_to_cpup((__le16 *)rom); @@ -414,12 +569,22 @@ static inline int w1_DS18B20_convert_temp(u8 rom[9]) return t*1000/16; } +/** + * w1_DS18S20_convert_temp() - temperature computation for DS18S20 + * @rom: data read from device RAM (8 data bytes + 1 CRC byte) + * + * Can be called for any DS18S20 compliant device. + * + * Return: value in millidegrees Celsius. + */ static inline int w1_DS18S20_convert_temp(u8 rom[9]) { int t, h; - if (!rom[7]) + if (!rom[7]) { + pr_debug("%s: Invalid argument for conversion\n", __func__); return 0; + } if (rom[1] == 0) t = ((s32)rom[0] >> 1)*1000; @@ -434,136 +599,671 @@ static inline int w1_DS18S20_convert_temp(u8 rom[9]) return t; } -static inline int w1_convert_temp(u8 rom[9], u8 fid) +/* Device capability description */ + +static struct w1_therm_family_converter w1_therm_families[] = { + { + .f = &w1_therm_family_DS18S20, + .convert = w1_DS18S20_convert_temp, + .get_conversion_time = w1_DS18S20_convert_time, + .set_resolution = NULL, /* no config register */ + .get_resolution = NULL, /* no config register */ + .write_data = w1_DS18S20_write_data, + .bulk_read = true + }, + { + .f = &w1_therm_family_DS1822, + .convert = w1_DS18B20_convert_temp, + .get_conversion_time = w1_DS18B20_convert_time, + .set_resolution = w1_DS18B20_set_resolution, + .get_resolution = w1_DS18B20_get_resolution, + .write_data = w1_DS18B20_write_data, + .bulk_read = true + }, + { + .f = &w1_therm_family_DS18B20, + .convert = w1_DS18B20_convert_temp, + .get_conversion_time = w1_DS18B20_convert_time, + .set_resolution = w1_DS18B20_set_resolution, + .get_resolution = w1_DS18B20_get_resolution, + .write_data = w1_DS18B20_write_data, + .bulk_read = true + }, + { + .f = &w1_therm_family_DS28EA00, + .convert = w1_DS18B20_convert_temp, + .get_conversion_time = w1_DS18B20_convert_time, + .set_resolution = w1_DS18B20_set_resolution, + .get_resolution = w1_DS18B20_get_resolution, + .write_data = w1_DS18B20_write_data, + .bulk_read = false + }, + { + .f = &w1_therm_family_DS1825, + .convert = w1_DS18B20_convert_temp, + .get_conversion_time = w1_DS18B20_convert_time, + .set_resolution = w1_DS18B20_set_resolution, + .get_resolution = w1_DS18B20_get_resolution, + .write_data = w1_DS18B20_write_data, + .bulk_read = true + } +}; + +/* Helpers Functions */ + +/** + * device_family() - Retrieve a pointer on &struct w1_therm_family_converter + * @sl: slave to retrieve the device specific structure + * + * Return: pointer to the slaves's family converter, NULL if not known + */ +static struct w1_therm_family_converter *device_family(struct w1_slave *sl) { + struct w1_therm_family_converter *ret = NULL; int i; - for (i = 0; i < ARRAY_SIZE(w1_therm_families); ++i) - if (w1_therm_families[i].f->fid == fid) - return w1_therm_families[i].convert(rom); + for (i = 0; i < ARRAY_SIZE(w1_therm_families); ++i) { + if (w1_therm_families[i].f->fid == sl->family->fid) { + ret = &w1_therm_families[i]; + break; + } + } + return ret; +} + +/** + * bus_mutex_lock() - Acquire the mutex + * @lock: w1 bus mutex to acquire + * + * It try to acquire the mutex W1_THERM_MAX_TRY times and wait + * W1_THERM_RETRY_DELAY between 2 attempts. + * + * Return: true is mutex is acquired and lock, false otherwise + */ +static inline bool bus_mutex_lock(struct mutex *lock) +{ + int max_trying = W1_THERM_MAX_TRY; + + /* try to acquire the mutex, if not, sleep retry_delay before retry) */ + while (mutex_lock_interruptible(lock) != 0 && max_trying > 0) { + unsigned long sleep_rem; + + sleep_rem = msleep_interruptible(W1_THERM_RETRY_DELAY); + if (!sleep_rem) + max_trying--; + } + + if (!max_trying) + return false; /* Didn't acquire the bus mutex */ + + return true; +} + +/** + * support_bulk_read() - check if slave support bulk read + * @sl: device to check the ability + * + * Return: true if bulk read is supported, false if not or error + */ +static inline bool bulk_read_support(struct w1_slave *sl) +{ + if (SLAVE_SPECIFIC_FUNC(sl)) + return SLAVE_SPECIFIC_FUNC(sl)->bulk_read; + + dev_info(&sl->dev, + "%s: Device not supported by the driver\n", __func__); + + return false; /* No device family */ +} + +/** + * conversion_time() - get the Tconv for the slave + * @sl: device to get the conversion time + * + * On device supporting resolution settings, conversion time depend + * on the resolution setting. This helper function get the slave timing, + * depending on its current setting. + * + * Return: conversion time in ms, negative values are kernel error code + */ +static inline int conversion_time(struct w1_slave *sl) +{ + if (SLAVE_SPECIFIC_FUNC(sl)) + return SLAVE_SPECIFIC_FUNC(sl)->get_conversion_time(sl); + + dev_info(&sl->dev, + "%s: Device not supported by the driver\n", __func__); + + return -ENODEV; /* No device family */ +} + +/** + * temperature_from_RAM() - Convert the read info to temperature + * @sl: device that sent the RAM data + * @rom: read value on the slave device RAM + * + * Device dependent, the function bind the correct computation method. + * + * Return: temperature in 1/1000degC, 0 on error. + */ +static inline int temperature_from_RAM(struct w1_slave *sl, u8 rom[9]) +{ + if (SLAVE_SPECIFIC_FUNC(sl)) + return SLAVE_SPECIFIC_FUNC(sl)->convert(rom); + + dev_info(&sl->dev, + "%s: Device not supported by the driver\n", __func__); + + return 0; /* No device family */ +} + +/** + * int_to_short() - Safe casting of int to short + * + * @i: integer to be converted to short + * + * Device register use 1 byte to store signed integer. + * This helper function convert the int in a signed short, + * using the min/max values that device can measure as limits. + * min/max values are defined by macro. + * + * Return: a short in the range of min/max value + */ +static inline s8 int_to_short(int i) +{ + /* Prepare to cast to short by eliminating out of range values */ + i = i > MAX_TEMP ? MAX_TEMP : i; + i = i < MIN_TEMP ? MIN_TEMP : i; + return (s8) i; +} + +/* Interface Functions */ + +static int w1_therm_add_slave(struct w1_slave *sl) +{ + struct w1_therm_family_converter *sl_family_conv; + + /* Allocate memory */ + sl->family_data = kzalloc(sizeof(struct w1_therm_family_data), + GFP_KERNEL); + if (!sl->family_data) + return -ENOMEM; + + atomic_set(THERM_REFCNT(sl->family_data), 1); + + /* Get a pointer to the device specific function struct */ + sl_family_conv = device_family(sl); + if (!sl_family_conv) { + kfree(sl->family_data); + return -ENODEV; + } + /* save this pointer to the device structure */ + SLAVE_SPECIFIC_FUNC(sl) = sl_family_conv; + + if (bulk_read_support(sl)) { + /* + * add the sys entry to trigger bulk_read + * at master level only the 1st time + */ + if (!bulk_read_device_counter) { + int err = device_create_file(&sl->master->dev, + &dev_attr_therm_bulk_read); + + if (err) + dev_warn(&sl->dev, + "%s: Device has been added, but bulk read is unavailable. err=%d\n", + __func__, err); + } + /* Increment the counter */ + bulk_read_device_counter++; + } + + /* Getting the power mode of the device {external, parasite} */ + SLAVE_POWERMODE(sl) = read_powermode(sl); + + if (SLAVE_POWERMODE(sl) < 0) { + /* no error returned as device has been added */ + dev_warn(&sl->dev, + "%s: Device has been added, but power_mode may be corrupted. err=%d\n", + __func__, SLAVE_POWERMODE(sl)); + } + + /* Getting the resolution of the device */ + if (SLAVE_SPECIFIC_FUNC(sl)->get_resolution) { + SLAVE_RESOLUTION(sl) = + SLAVE_SPECIFIC_FUNC(sl)->get_resolution(sl); + if (SLAVE_RESOLUTION(sl) < 0) { + /* no error returned as device has been added */ + dev_warn(&sl->dev, + "%s:Device has been added, but resolution may be corrupted. err=%d\n", + __func__, SLAVE_RESOLUTION(sl)); + } + } + + /* Finally initialize convert_triggered flag */ + SLAVE_CONVERT_TRIGGERED(sl) = 0; return 0; } -static ssize_t w1_slave_store(struct device *device, - struct device_attribute *attr, const char *buf, - size_t size) +static void w1_therm_remove_slave(struct w1_slave *sl) { - int val, ret; - struct w1_slave *sl = dev_to_w1_slave(device); - int i; + int refcnt = atomic_sub_return(1, THERM_REFCNT(sl->family_data)); - ret = kstrtoint(buf, 0, &val); - if (ret) - return ret; - - for (i = 0; i < ARRAY_SIZE(w1_therm_families); ++i) { - if (w1_therm_families[i].f->fid == sl->family->fid) { - /* zero value indicates to write current configuration to eeprom */ - if (val == 0) - ret = w1_therm_families[i].eeprom(device); - else - ret = w1_therm_families[i].precision(device, val); - break; - } + if (bulk_read_support(sl)) { + bulk_read_device_counter--; + /* Delete the entry if no more device support the feature */ + if (!bulk_read_device_counter) + device_remove_file(&sl->master->dev, + &dev_attr_therm_bulk_read); } - return ret ? : size; + + while (refcnt) { + msleep(1000); + refcnt = atomic_read(THERM_REFCNT(sl->family_data)); + } + kfree(sl->family_data); + sl->family_data = NULL; } -static ssize_t read_therm(struct device *device, - struct w1_slave *sl, struct therm_info *info) +/* Hardware Functions */ + +/* Safe version of reset_select_slave - avoid using the one in w_io.c */ +static int reset_select_slave(struct w1_slave *sl) { - struct w1_master *dev = sl->master; - u8 external_power; - int ret, max_trying = 10; - u8 *family_data = sl->family_data; + u8 match[9] = { W1_MATCH_ROM, }; + u64 rn = le64_to_cpu(*((u64 *)&sl->reg_num)); - if (!family_data) { - ret = -ENODEV; + if (w1_reset_bus(sl->master)) + return -ENODEV; + + memcpy(&match[1], &rn, 8); + w1_write_block(sl->master, match, 9); + + return 0; +} + +static int convert_t(struct w1_slave *sl, struct therm_info *info) +{ + struct w1_master *dev_master = sl->master; + int max_trying = W1_THERM_MAX_TRY; + int t_conv; + int ret = -ENODEV; + bool strong_pullup; + + if (!sl->family_data) goto error; - } - /* prevent the slave from going away in sleep */ - atomic_inc(THERM_REFCNT(family_data)); + strong_pullup = (w1_strong_pullup == 2 || + (!SLAVE_POWERMODE(sl) && + w1_strong_pullup)); - ret = mutex_lock_interruptible(&dev->bus_mutex); - if (ret != 0) - goto dec_refcnt; + /* get conversion duration device and id dependent */ + t_conv = conversion_time(sl); memset(info->rom, 0, sizeof(info->rom)); - while (max_trying--) { + /* prevent the slave from going away in sleep */ + atomic_inc(THERM_REFCNT(sl->family_data)); + + if (!bus_mutex_lock(&dev_master->bus_mutex)) { + ret = -EAGAIN; /* Didn't acquire the mutex */ + goto dec_refcnt; + } + + while (max_trying-- && ret) { /* ret should be 0 */ info->verdict = 0; info->crc = 0; - - if (!w1_reset_select_slave(sl)) { - int count = 0; - unsigned int tm = 750; + /* safe version to select slave */ + if (!reset_select_slave(sl)) { unsigned long sleep_rem; - w1_write_8(dev, W1_READ_PSUPPLY); - external_power = w1_read_8(dev); - - if (w1_reset_select_slave(sl)) - continue; - /* 750ms strong pullup (or delay) after the convert */ - if (w1_strong_pullup == 2 || - (!external_power && w1_strong_pullup)) - w1_next_pullup(dev, tm); + if (strong_pullup) + w1_next_pullup(dev_master, t_conv); - w1_write_8(dev, W1_CONVERT_TEMP); + w1_write_8(dev_master, W1_CONVERT_TEMP); - if (external_power) { - mutex_unlock(&dev->bus_mutex); + if (strong_pullup) { /*some device need pullup */ + sleep_rem = msleep_interruptible(t_conv); + if (sleep_rem != 0) { + ret = -EINTR; + goto mt_unlock; + } + mutex_unlock(&dev_master->bus_mutex); + } else { /*no device need pullup */ + mutex_unlock(&dev_master->bus_mutex); - sleep_rem = msleep_interruptible(tm); + sleep_rem = msleep_interruptible(t_conv); if (sleep_rem != 0) { ret = -EINTR; goto dec_refcnt; } + } + ret = read_scratchpad(sl, info); + goto dec_refcnt; + } - ret = mutex_lock_interruptible(&dev->bus_mutex); - if (ret != 0) - goto dec_refcnt; - } else if (!w1_strong_pullup) { - sleep_rem = msleep_interruptible(tm); + } + +mt_unlock: + mutex_unlock(&dev_master->bus_mutex); +dec_refcnt: + atomic_dec(THERM_REFCNT(sl->family_data)); +error: + return ret; +} + +static int read_scratchpad(struct w1_slave *sl, struct therm_info *info) +{ + struct w1_master *dev_master = sl->master; + int max_trying = W1_THERM_MAX_TRY; + int ret = -ENODEV; + + info->verdict = 0; + + if (!sl->family_data) + goto error; + + memset(info->rom, 0, sizeof(info->rom)); + + /* prevent the slave from going away in sleep */ + atomic_inc(THERM_REFCNT(sl->family_data)); + + if (!bus_mutex_lock(&dev_master->bus_mutex)) { + ret = -EAGAIN; /* Didn't acquire the mutex */ + goto dec_refcnt; + } + + while (max_trying-- && ret) { /* ret should be 0 */ + /* safe version to select slave */ + if (!reset_select_slave(sl)) { + u8 nb_bytes_read; + + w1_write_8(dev_master, W1_READ_SCRATCHPAD); + + nb_bytes_read = w1_read_block(dev_master, info->rom, 9); + if (nb_bytes_read != 9) { + dev_warn(&sl->dev, + "w1_read_block(): returned %u instead of 9.\n", + nb_bytes_read); + ret = -EIO; + } + + info->crc = w1_calc_crc8(info->rom, 8); + + if (info->rom[8] == info->crc) { + info->verdict = 1; + ret = 0; + } else + ret = -EIO; /* CRC not checked */ + } + + } + mutex_unlock(&dev_master->bus_mutex); + +dec_refcnt: + atomic_dec(THERM_REFCNT(sl->family_data)); +error: + return ret; +} + +static int write_scratchpad(struct w1_slave *sl, const u8 *data, u8 nb_bytes) +{ + struct w1_master *dev_master = sl->master; + int max_trying = W1_THERM_MAX_TRY; + int ret = -ENODEV; + + if (!sl->family_data) + goto error; + + /* prevent the slave from going away in sleep */ + atomic_inc(THERM_REFCNT(sl->family_data)); + + if (!bus_mutex_lock(&dev_master->bus_mutex)) { + ret = -EAGAIN; /* Didn't acquire the mutex */ + goto dec_refcnt; + } + + while (max_trying-- && ret) { /* ret should be 0 */ + /* safe version to select slave */ + if (!reset_select_slave(sl)) { + w1_write_8(dev_master, W1_WRITE_SCRATCHPAD); + w1_write_block(dev_master, data, nb_bytes); + ret = 0; + } + } + mutex_unlock(&dev_master->bus_mutex); + +dec_refcnt: + atomic_dec(THERM_REFCNT(sl->family_data)); +error: + return ret; +} + +static int copy_scratchpad(struct w1_slave *sl) +{ + struct w1_master *dev_master = sl->master; + int max_trying = W1_THERM_MAX_TRY; + int t_write, ret = -ENODEV; + bool strong_pullup; + + if (!sl->family_data) + goto error; + + t_write = W1_THERM_EEPROM_WRITE_DELAY; + strong_pullup = (w1_strong_pullup == 2 || + (!SLAVE_POWERMODE(sl) && + w1_strong_pullup)); + + /* prevent the slave from going away in sleep */ + atomic_inc(THERM_REFCNT(sl->family_data)); + + if (!bus_mutex_lock(&dev_master->bus_mutex)) { + ret = -EAGAIN; /* Didn't acquire the mutex */ + goto dec_refcnt; + } + + while (max_trying-- && ret) { /* ret should be 0 */ + /* safe version to select slave */ + if (!reset_select_slave(sl)) { + unsigned long sleep_rem; + + /* 10ms strong pullup (or delay) after the convert */ + if (strong_pullup) + w1_next_pullup(dev_master, t_write); + + w1_write_8(dev_master, W1_COPY_SCRATCHPAD); + + if (strong_pullup) { + sleep_rem = msleep_interruptible(t_write); if (sleep_rem != 0) { ret = -EINTR; goto mt_unlock; } } - - if (!w1_reset_select_slave(sl)) { - - w1_write_8(dev, W1_READ_SCRATCHPAD); - count = w1_read_block(dev, info->rom, 9); - if (count != 9) { - dev_warn(device, "w1_read_block() " - "returned %u instead of 9.\n", - count); - } - - info->crc = w1_calc_crc8(info->rom, 8); - - if (info->rom[8] == info->crc) - info->verdict = 1; - } + ret = 0; } - if (info->verdict) - break; } mt_unlock: - mutex_unlock(&dev->bus_mutex); + mutex_unlock(&dev_master->bus_mutex); dec_refcnt: - atomic_dec(THERM_REFCNT(family_data)); + atomic_dec(THERM_REFCNT(sl->family_data)); error: return ret; } +static int recall_eeprom(struct w1_slave *sl) +{ + struct w1_master *dev_master = sl->master; + int max_trying = W1_THERM_MAX_TRY; + int ret = -ENODEV; + + if (!sl->family_data) + goto error; + + /* prevent the slave from going away in sleep */ + atomic_inc(THERM_REFCNT(sl->family_data)); + + if (!bus_mutex_lock(&dev_master->bus_mutex)) { + ret = -EAGAIN; /* Didn't acquire the mutex */ + goto dec_refcnt; + } + + while (max_trying-- && ret) { /* ret should be 0 */ + /* safe version to select slave */ + if (!reset_select_slave(sl)) { + + w1_write_8(dev_master, W1_RECALL_EEPROM); + + ret = 1; /* Slave will pull line to 0 */ + while (ret) + ret = 1 - w1_touch_bit(dev_master, 1); + } + + } + + mutex_unlock(&dev_master->bus_mutex); + +dec_refcnt: + atomic_dec(THERM_REFCNT(sl->family_data)); +error: + return ret; +} + +static int read_powermode(struct w1_slave *sl) +{ + struct w1_master *dev_master = sl->master; + int max_trying = W1_THERM_MAX_TRY; + int ret = -ENODEV; + + if (!sl->family_data) + goto error; + + /* prevent the slave from going away in sleep */ + atomic_inc(THERM_REFCNT(sl->family_data)); + + if (!bus_mutex_lock(&dev_master->bus_mutex)) { + ret = -EAGAIN; /* Didn't acquire the mutex */ + goto dec_refcnt; + } + + while ((max_trying--) && (ret < 0)) { + /* safe version to select slave */ + if (!reset_select_slave(sl)) { + w1_write_8(dev_master, W1_READ_PSUPPLY); + /* + * Emit a read time slot and read only one bit, + * 1 is externally powered, + * 0 is parasite powered + */ + ret = w1_touch_bit(dev_master, 1); + /* ret should be either 1 either 0 */ + } + } + mutex_unlock(&dev_master->bus_mutex); + +dec_refcnt: + atomic_dec(THERM_REFCNT(sl->family_data)); +error: + return ret; +} + +static int trigger_bulk_read(struct w1_master *dev_master) +{ + struct w1_slave *sl = NULL; /* used to iterate through slaves */ + int max_trying = W1_THERM_MAX_TRY; + int t_conv = 0; + int ret = -ENODEV; + bool strong_pullup = false; + + /* + * Check whether there are parasite powered device on the bus, + * and compute duration of conversion for these devices + * so we can apply a strong pullup if required + */ + list_for_each_entry(sl, &dev_master->slist, w1_slave_entry) { + if (!sl->family_data) + goto error; + if (bulk_read_support(sl)) { + int t_cur = conversion_time(sl); + + t_conv = t_cur > t_conv ? t_cur : t_conv; + strong_pullup = strong_pullup || + (w1_strong_pullup == 2 || + (!SLAVE_POWERMODE(sl) && + w1_strong_pullup)); + } + } + + /* + * t_conv is the max conversion time required on the bus + * If its 0, no device support the bulk read feature + */ + if (!t_conv) + goto error; + + if (!bus_mutex_lock(&dev_master->bus_mutex)) { + ret = -EAGAIN; /* Didn't acquire the mutex */ + goto error; + } + + while ((max_trying--) && (ret < 0)) { /* ret should be either 0 */ + + if (!w1_reset_bus(dev_master)) { /* Just reset the bus */ + unsigned long sleep_rem; + + w1_write_8(dev_master, W1_SKIP_ROM); + + if (strong_pullup) /* Apply pullup if required */ + w1_next_pullup(dev_master, t_conv); + + w1_write_8(dev_master, W1_CONVERT_TEMP); + + /* set a flag to instruct that converT pending */ + list_for_each_entry(sl, + &dev_master->slist, w1_slave_entry) { + if (bulk_read_support(sl)) + SLAVE_CONVERT_TRIGGERED(sl) = -1; + } + + if (strong_pullup) { /* some device need pullup */ + sleep_rem = msleep_interruptible(t_conv); + if (sleep_rem != 0) { + ret = -EINTR; + goto mt_unlock; + } + mutex_unlock(&dev_master->bus_mutex); + } else { + mutex_unlock(&dev_master->bus_mutex); + sleep_rem = msleep_interruptible(t_conv); + if (sleep_rem != 0) { + ret = -EINTR; + goto set_flag; + } + } + ret = 0; + goto set_flag; + } + } + +mt_unlock: + mutex_unlock(&dev_master->bus_mutex); +set_flag: + /* set a flag to register convsersion is done */ + list_for_each_entry(sl, &dev_master->slist, w1_slave_entry) { + if (bulk_read_support(sl)) + SLAVE_CONVERT_TRIGGERED(sl) = 1; + } +error: + return ret; +} + +/* Sysfs Interface definition */ + static ssize_t w1_slave_show(struct device *device, struct device_attribute *attr, char *buf) { @@ -572,43 +1272,405 @@ static ssize_t w1_slave_show(struct device *device, u8 *family_data = sl->family_data; int ret, i; ssize_t c = PAGE_SIZE; - u8 fid = sl->family->fid; - ret = read_therm(device, sl, &info); - if (ret) - return ret; + if (bulk_read_support(sl)) { + if (SLAVE_CONVERT_TRIGGERED(sl) < 0) { + dev_dbg(device, + "%s: Conversion in progress, retry later\n", + __func__); + return 0; + } else if (SLAVE_CONVERT_TRIGGERED(sl) > 0) { + /* A bulk read has been issued, read the device RAM */ + ret = read_scratchpad(sl, &info); + SLAVE_CONVERT_TRIGGERED(sl) = 0; + } else + ret = convert_t(sl, &info); + } else + ret = convert_t(sl, &info); + + if (ret < 0) { + dev_dbg(device, + "%s: Temperature data may be corrupted. err=%d\n", + __func__, ret); + return 0; + } for (i = 0; i < 9; ++i) c -= snprintf(buf + PAGE_SIZE - c, c, "%02x ", info.rom[i]); c -= snprintf(buf + PAGE_SIZE - c, c, ": crc=%02x %s\n", info.crc, (info.verdict) ? "YES" : "NO"); + if (info.verdict) memcpy(family_data, info.rom, sizeof(info.rom)); else - dev_warn(device, "Read failed CRC check\n"); + dev_warn(device, "%s:Read failed CRC check\n", __func__); for (i = 0; i < 9; ++i) c -= snprintf(buf + PAGE_SIZE - c, c, "%02x ", ((u8 *)family_data)[i]); c -= snprintf(buf + PAGE_SIZE - c, c, "t=%d\n", - w1_convert_temp(info.rom, fid)); + temperature_from_RAM(sl, info.rom)); + ret = PAGE_SIZE - c; return ret; } +static ssize_t w1_slave_store(struct device *device, + struct device_attribute *attr, const char *buf, + size_t size) +{ + int val, ret = 0; + struct w1_slave *sl = dev_to_w1_slave(device); + + ret = kstrtoint(buf, 10, &val); /* converting user entry to int */ + + if (ret) { /* conversion error */ + dev_info(device, + "%s: conversion error. err= %d\n", __func__, ret); + return size; /* return size to avoid call back again */ + } + + if ((!sl->family_data) || (!SLAVE_SPECIFIC_FUNC(sl))) { + dev_info(device, + "%s: Device not supported by the driver\n", __func__); + return size; /* No device family */ + } + + if (val == 0) /* val=0 : trigger a EEPROM save */ + ret = copy_scratchpad(sl); + else { + if (SLAVE_SPECIFIC_FUNC(sl)->set_resolution) + ret = SLAVE_SPECIFIC_FUNC(sl)->set_resolution(sl, val); + } + + if (ret) { + dev_info(device, + "%s: writing error %d\n", __func__, ret); + /* return size to avoid call back again */ + } else + SLAVE_RESOLUTION(sl) = val; + + return size; /* always return size to avoid infinite calling */ +} + +static ssize_t temperature_show(struct device *device, + struct device_attribute *attr, char *buf) +{ + struct w1_slave *sl = dev_to_w1_slave(device); + struct therm_info info; + int ret = 0; + + if ((!sl->family_data) || (!SLAVE_SPECIFIC_FUNC(sl))) { + dev_info(device, + "%s: Device not supported by the driver\n", __func__); + return 0; /* No device family */ + } + + if (bulk_read_support(sl)) { + if (SLAVE_CONVERT_TRIGGERED(sl) < 0) { + dev_dbg(device, + "%s: Conversion in progress, retry later\n", + __func__); + return 0; + } else if (SLAVE_CONVERT_TRIGGERED(sl) > 0) { + /* A bulk read has been issued, read the device RAM */ + ret = read_scratchpad(sl, &info); + SLAVE_CONVERT_TRIGGERED(sl) = 0; + } else + ret = convert_t(sl, &info); + } else + ret = convert_t(sl, &info); + + if (ret < 0) { + dev_dbg(device, + "%s: Temperature data may be corrupted. err=%d\n", + __func__, ret); + return 0; + } + + return sprintf(buf, "%d\n", temperature_from_RAM(sl, info.rom)); +} + +static ssize_t ext_power_show(struct device *device, + struct device_attribute *attr, char *buf) +{ + struct w1_slave *sl = dev_to_w1_slave(device); + + if (!sl->family_data) { + dev_info(device, + "%s: Device not supported by the driver\n", __func__); + return 0; /* No device family */ + } + + /* Getting the power mode of the device {external, parasite} */ + SLAVE_POWERMODE(sl) = read_powermode(sl); + + if (SLAVE_POWERMODE(sl) < 0) { + dev_dbg(device, + "%s: Power_mode may be corrupted. err=%d\n", + __func__, SLAVE_POWERMODE(sl)); + } + return sprintf(buf, "%d\n", SLAVE_POWERMODE(sl)); +} + +static ssize_t resolution_show(struct device *device, + struct device_attribute *attr, char *buf) +{ + struct w1_slave *sl = dev_to_w1_slave(device); + + if ((!sl->family_data) || (!SLAVE_SPECIFIC_FUNC(sl))) { + dev_info(device, + "%s: Device not supported by the driver\n", __func__); + return 0; /* No device family */ + } + + /* get the correct function depending on the device */ + SLAVE_RESOLUTION(sl) = SLAVE_SPECIFIC_FUNC(sl)->get_resolution(sl); + if (SLAVE_RESOLUTION(sl) < 0) { + dev_dbg(device, + "%s: Resolution may be corrupted. err=%d\n", + __func__, SLAVE_RESOLUTION(sl)); + } + + return sprintf(buf, "%d\n", SLAVE_RESOLUTION(sl)); +} + +static ssize_t resolution_store(struct device *device, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct w1_slave *sl = dev_to_w1_slave(device); + int val; + int ret = 0; + + ret = kstrtoint(buf, 10, &val); /* converting user entry to int */ + + if (ret) { /* conversion error */ + dev_info(device, + "%s: conversion error. err= %d\n", __func__, ret); + return size; /* return size to avoid call back again */ + } + + if ((!sl->family_data) || (!SLAVE_SPECIFIC_FUNC(sl))) { + dev_info(device, + "%s: Device not supported by the driver\n", __func__); + return size; /* No device family */ + } + + /* + * Don't deal with the val enterd by user, + * only device knows what is correct or not + */ + + /* get the correct function depending on the device */ + ret = SLAVE_SPECIFIC_FUNC(sl)->set_resolution(sl, val); + + if (ret) { + dev_info(device, + "%s: writing error %d\n", __func__, ret); + /* return size to avoid call back again */ + } else + SLAVE_RESOLUTION(sl) = val; + + return size; +} + +static ssize_t eeprom_store(struct device *device, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct w1_slave *sl = dev_to_w1_slave(device); + int ret = -EINVAL; /* Invalid argument */ + + if (size == sizeof(EEPROM_CMD_WRITE)) { + if (!strncmp(buf, EEPROM_CMD_WRITE, sizeof(EEPROM_CMD_WRITE)-1)) + ret = copy_scratchpad(sl); + } else if (size == sizeof(EEPROM_CMD_READ)) { + if (!strncmp(buf, EEPROM_CMD_READ, sizeof(EEPROM_CMD_READ)-1)) + ret = recall_eeprom(sl); + } + + if (ret) + dev_info(device, "%s: error in process %d\n", __func__, ret); + + return size; +} + +static ssize_t alarms_show(struct device *device, + struct device_attribute *attr, char *buf) +{ + struct w1_slave *sl = dev_to_w1_slave(device); + int ret; + s8 th = 0, tl = 0; + struct therm_info scratchpad; + + ret = read_scratchpad(sl, &scratchpad); + + if (!ret) { + th = scratchpad.rom[2]; /* TH is byte 2 */ + tl = scratchpad.rom[3]; /* TL is byte 3 */ + } else { + dev_info(device, + "%s: error reading alarms register %d\n", + __func__, ret); + } + + return sprintf(buf, "%hd %hd\n", tl, th); +} + +static ssize_t alarms_store(struct device *device, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct w1_slave *sl = dev_to_w1_slave(device); + struct therm_info info; + u8 new_config_register[3]; /* array of data to be written */ + int temp, ret; + char *token = NULL; + s8 tl, th, tt; /* 1 byte per value + temp ring order */ + char *p_args, *orig; + + p_args = orig = kmalloc(size, GFP_KERNEL); + /* Safe string copys as buf is const */ + if (!p_args) { + dev_warn(device, + "%s: error unable to allocate memory %d\n", + __func__, -ENOMEM); + return size; + } + strcpy(p_args, buf); + + /* Split string using space char */ + token = strsep(&p_args, " "); + + if (!token) { + dev_info(device, + "%s: error parsing args %d\n", __func__, -EINVAL); + goto free_m; + } + + /* Convert 1st entry to int */ + ret = kstrtoint (token, 10, &temp); + if (ret) { + dev_info(device, + "%s: error parsing args %d\n", __func__, ret); + goto free_m; + } + + tl = int_to_short(temp); + + /* Split string using space char */ + token = strsep(&p_args, " "); + if (!token) { + dev_info(device, + "%s: error parsing args %d\n", __func__, -EINVAL); + goto free_m; + } + /* Convert 2nd entry to int */ + ret = kstrtoint (token, 10, &temp); + if (ret) { + dev_info(device, + "%s: error parsing args %d\n", __func__, ret); + goto free_m; + } + + /* Prepare to cast to short by eliminating out of range values */ + th = int_to_short(temp); + + /* Reorder if required th and tl */ + if (tl > th) { + tt = tl; tl = th; th = tt; + } + + /* + * Read the scratchpad to change only the required bits + * (th : byte 2 - tl: byte 3) + */ + ret = read_scratchpad(sl, &info); + if (!ret) { + new_config_register[0] = th; /* Byte 2 */ + new_config_register[1] = tl; /* Byte 3 */ + new_config_register[2] = info.rom[4];/* Byte 4 */ + } else { + dev_info(device, + "%s: error reading from the slave device %d\n", + __func__, ret); + goto free_m; + } + + /* Write data in the device RAM */ + if (!SLAVE_SPECIFIC_FUNC(sl)) { + dev_info(device, + "%s: Device not supported by the driver %d\n", + __func__, -ENODEV); + goto free_m; + } + + ret = SLAVE_SPECIFIC_FUNC(sl)->write_data(sl, new_config_register); + if (ret) + dev_info(device, + "%s: error writing to the slave device %d\n", + __func__, ret); + +free_m: + /* free allocated memory */ + kfree(orig); + + return size; +} + +static ssize_t therm_bulk_read_store(struct device *device, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct w1_master *dev_master = dev_to_w1_master(device); + int ret = -EINVAL; /* Invalid argument */ + + if (size == sizeof(BULK_TRIGGER_CMD)) + if (!strncmp(buf, BULK_TRIGGER_CMD, + sizeof(BULK_TRIGGER_CMD)-1)) + ret = trigger_bulk_read(dev_master); + + if (ret) + dev_info(device, + "%s: unable to trigger a bulk read on the bus. err=%d\n", + __func__, ret); + + return size; +} + +static ssize_t therm_bulk_read_show(struct device *device, + struct device_attribute *attr, char *buf) +{ + struct w1_master *dev_master = dev_to_w1_master(device); + struct w1_slave *sl = NULL; + int ret = 0; + + list_for_each_entry(sl, &dev_master->slist, w1_slave_entry) { + if (sl->family_data) { + if (bulk_read_support(sl)) { + if (SLAVE_CONVERT_TRIGGERED(sl) == -1) { + ret = -1; + goto show_result; + } + if (SLAVE_CONVERT_TRIGGERED(sl) == 1) + /* continue to check other slaves */ + ret = 1; + } + } + } +show_result: + return sprintf(buf, "%d\n", ret); +} + #if IS_REACHABLE(CONFIG_HWMON) static int w1_read_temp(struct device *device, u32 attr, int channel, long *val) { struct w1_slave *sl = dev_get_drvdata(device); struct therm_info info; - u8 fid = sl->family->fid; int ret; switch (attr) { case hwmon_temp_input: - ret = read_therm(device, sl, &info); + ret = convert_t(sl, &info); if (ret) return ret; @@ -617,7 +1679,7 @@ static int w1_read_temp(struct device *device, u32 attr, int channel, return ret; } - *val = w1_convert_temp(info.rom, fid); + *val = temperature_from_RAM(sl, info.rom); ret = 0; break; default: @@ -666,7 +1728,7 @@ static ssize_t w1_seq_show(struct device *device, if (ack != W1_42_SUCCESS_CONFIRM_BYTE) goto error; - /* In case the bus fails to send 0xFF, limit*/ + /* In case the bus fails to send 0xFF, limit */ for (i = 0; i <= 64; i++) { if (w1_reset_bus(sl->master)) goto error; diff --git a/fs/debugfs/internal.h b/fs/debugfs/internal.h index f0d73d86cc1a..034e6973cead 100644 --- a/fs/debugfs/internal.h +++ b/fs/debugfs/internal.h @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +/* SPDX-License-Identifier: GPL-2.0 */ /* * internal.h - declarations internal to debugfs * diff --git a/fs/kernfs/file.c b/fs/kernfs/file.c index 34366db3620d..fd6ddfe4cd94 100644 --- a/fs/kernfs/file.c +++ b/fs/kernfs/file.c @@ -1010,7 +1010,7 @@ struct kernfs_node *__kernfs_create_file(struct kernfs_node *parent, #ifdef CONFIG_DEBUG_LOCK_ALLOC if (key) { - lockdep_init_map(&kn->dep_map, "kn->count", key, 0); + lockdep_init_map(&kn->dep_map, "kn->active", key, 0); kn->flags |= KERNFS_LOCKDEP; } #endif diff --git a/fs/proc/base.c b/fs/proc/base.c index 7a4241c1858b..93291bcdc7e9 100644 --- a/fs/proc/base.c +++ b/fs/proc/base.c @@ -2779,6 +2779,15 @@ static const struct pid_entry smack_attr_dir_stuff[] = { LSM_DIR_OPS(smack); #endif +#ifdef CONFIG_SECURITY_APPARMOR +static const struct pid_entry apparmor_attr_dir_stuff[] = { + ATTR("apparmor", "current", 0666), + ATTR("apparmor", "prev", 0444), + ATTR("apparmor", "exec", 0666), +}; +LSM_DIR_OPS(apparmor); +#endif + static const struct pid_entry attr_dir_stuff[] = { ATTR(NULL, "current", 0666), ATTR(NULL, "prev", 0444), @@ -2790,6 +2799,10 @@ static const struct pid_entry attr_dir_stuff[] = { DIR("smack", 0555, proc_smack_attr_dir_inode_ops, proc_smack_attr_dir_ops), #endif +#ifdef CONFIG_SECURITY_APPARMOR + DIR("apparmor", 0555, + proc_apparmor_attr_dir_inode_ops, proc_apparmor_attr_dir_ops), +#endif }; static int proc_attr_dir_readdir(struct file *file, struct dir_context *ctx) diff --git a/include/dt-bindings/interconnect/imx8mm.h b/include/dt-bindings/interconnect/imx8mm.h new file mode 100644 index 000000000000..8f10bb06cb59 --- /dev/null +++ b/include/dt-bindings/interconnect/imx8mm.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Interconnect framework driver for i.MX SoC + * + * Copyright (c) 2019, BayLibre + * Copyright (c) 2019-2020, NXP + * Author: Alexandre Bailon + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MM_H +#define __DT_BINDINGS_INTERCONNECT_IMX8MM_H + +#define IMX8MM_ICN_NOC 1 +#define IMX8MM_ICS_DRAM 2 +#define IMX8MM_ICS_OCRAM 3 +#define IMX8MM_ICM_A53 4 + +#define IMX8MM_ICM_VPU_H1 5 +#define IMX8MM_ICM_VPU_G1 6 +#define IMX8MM_ICM_VPU_G2 7 +#define IMX8MM_ICN_VIDEO 8 + +#define IMX8MM_ICM_GPU2D 9 +#define IMX8MM_ICM_GPU3D 10 +#define IMX8MM_ICN_GPU 11 + +#define IMX8MM_ICM_CSI 12 +#define IMX8MM_ICM_LCDIF 13 +#define IMX8MM_ICN_MIPI 14 + +#define IMX8MM_ICM_USB1 15 +#define IMX8MM_ICM_USB2 16 +#define IMX8MM_ICM_PCIE 17 +#define IMX8MM_ICN_HSIO 18 + +#define IMX8MM_ICM_SDMA2 19 +#define IMX8MM_ICM_SDMA3 20 +#define IMX8MM_ICN_AUDIO 21 + +#define IMX8MM_ICN_ENET 22 +#define IMX8MM_ICM_ENET 23 + +#define IMX8MM_ICN_MAIN 24 +#define IMX8MM_ICM_NAND 25 +#define IMX8MM_ICM_SDMA1 26 +#define IMX8MM_ICM_USDHC1 27 +#define IMX8MM_ICM_USDHC2 28 +#define IMX8MM_ICM_USDHC3 29 + +#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MM_H */ diff --git a/include/dt-bindings/interconnect/imx8mn.h b/include/dt-bindings/interconnect/imx8mn.h new file mode 100644 index 000000000000..307b977100b6 --- /dev/null +++ b/include/dt-bindings/interconnect/imx8mn.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Interconnect framework driver for i.MX SoC + * + * Copyright (c) 2019-2020, NXP + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MN_H +#define __DT_BINDINGS_INTERCONNECT_IMX8MN_H + +#define IMX8MN_ICN_NOC 1 +#define IMX8MN_ICS_DRAM 2 +#define IMX8MN_ICS_OCRAM 3 +#define IMX8MN_ICM_A53 4 + +#define IMX8MN_ICM_GPU 5 +#define IMX8MN_ICN_GPU 6 + +#define IMX8MN_ICM_CSI1 7 +#define IMX8MN_ICM_CSI2 8 +#define IMX8MN_ICM_ISI 9 +#define IMX8MN_ICM_LCDIF 10 +#define IMX8MN_ICN_MIPI 11 + +#define IMX8MN_ICM_USB 12 + +#define IMX8MN_ICM_SDMA2 13 +#define IMX8MN_ICM_SDMA3 14 +#define IMX8MN_ICN_AUDIO 15 + +#define IMX8MN_ICN_ENET 16 +#define IMX8MN_ICM_ENET 17 + +#define IMX8MN_ICM_NAND 18 +#define IMX8MN_ICM_SDMA1 19 +#define IMX8MN_ICM_USDHC1 20 +#define IMX8MN_ICM_USDHC2 21 +#define IMX8MN_ICM_USDHC3 22 +#define IMX8MN_ICN_MAIN 23 + +#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MN_H */ diff --git a/include/dt-bindings/interconnect/imx8mq.h b/include/dt-bindings/interconnect/imx8mq.h new file mode 100644 index 000000000000..1a4cae7f8be2 --- /dev/null +++ b/include/dt-bindings/interconnect/imx8mq.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Interconnect framework driver for i.MX SoC + * + * Copyright (c) 2019-2020, NXP + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MQ_H +#define __DT_BINDINGS_INTERCONNECT_IMX8MQ_H + +#define IMX8MQ_ICN_NOC 1 +#define IMX8MQ_ICS_DRAM 2 +#define IMX8MQ_ICS_OCRAM 3 +#define IMX8MQ_ICM_A53 4 + +#define IMX8MQ_ICM_VPU 5 +#define IMX8MQ_ICN_VIDEO 6 + +#define IMX8MQ_ICM_GPU 7 +#define IMX8MQ_ICN_GPU 8 + +#define IMX8MQ_ICM_DCSS 9 +#define IMX8MQ_ICN_DCSS 10 + +#define IMX8MQ_ICM_USB1 11 +#define IMX8MQ_ICM_USB2 12 +#define IMX8MQ_ICN_USB 13 + +#define IMX8MQ_ICM_CSI1 14 +#define IMX8MQ_ICM_CSI2 15 +#define IMX8MQ_ICM_LCDIF 16 +#define IMX8MQ_ICN_DISPLAY 17 + +#define IMX8MQ_ICM_SDMA2 18 +#define IMX8MQ_ICN_AUDIO 19 + +#define IMX8MQ_ICN_ENET 20 +#define IMX8MQ_ICM_ENET 21 + +#define IMX8MQ_ICM_SDMA1 22 +#define IMX8MQ_ICM_NAND 23 +#define IMX8MQ_ICM_USDHC1 24 +#define IMX8MQ_ICM_USDHC2 25 +#define IMX8MQ_ICM_PCIE1 26 +#define IMX8MQ_ICM_PCIE2 27 +#define IMX8MQ_ICN_MAIN 28 + +#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MQ_H */ diff --git a/include/dt-bindings/pinctrl/pads-imx8dxl.h b/include/dt-bindings/pinctrl/pads-imx8dxl.h new file mode 100644 index 000000000000..b1d7b84c3e0a --- /dev/null +++ b/include/dt-bindings/pinctrl/pads-imx8dxl.h @@ -0,0 +1,639 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019~2020 NXP + */ + +#ifndef _IMX8DXL_PADS_H +#define _IMX8DXL_PADS_H + +/* pin id */ +#define IMX8DXL_PCIE_CTRL0_PERST_B 0 +#define IMX8DXL_PCIE_CTRL0_CLKREQ_B 1 +#define IMX8DXL_PCIE_CTRL0_WAKE_B 2 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 +#define IMX8DXL_USB_SS3_TC0 4 +#define IMX8DXL_USB_SS3_TC1 5 +#define IMX8DXL_USB_SS3_TC2 6 +#define IMX8DXL_USB_SS3_TC3 7 +#define IMX8DXL_COMP_CTL_GPIO_3V3_USB3IO 8 +#define IMX8DXL_EMMC0_CLK 9 +#define IMX8DXL_EMMC0_CMD 10 +#define IMX8DXL_EMMC0_DATA0 11 +#define IMX8DXL_EMMC0_DATA1 12 +#define IMX8DXL_EMMC0_DATA2 13 +#define IMX8DXL_EMMC0_DATA3 14 +#define IMX8DXL_EMMC0_DATA4 15 +#define IMX8DXL_EMMC0_DATA5 16 +#define IMX8DXL_EMMC0_DATA6 17 +#define IMX8DXL_EMMC0_DATA7 18 +#define IMX8DXL_EMMC0_STROBE 19 +#define IMX8DXL_EMMC0_RESET_B 20 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 21 +#define IMX8DXL_USDHC1_RESET_B 22 +#define IMX8DXL_USDHC1_VSELECT 23 +#define IMX8DXL_CTL_NAND_RE_P_N 24 +#define IMX8DXL_USDHC1_WP 25 +#define IMX8DXL_USDHC1_CD_B 26 +#define IMX8DXL_CTL_NAND_DQS_P_N 27 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_VSELSEP 28 +#define IMX8DXL_ENET0_RGMII_TXC 29 +#define IMX8DXL_ENET0_RGMII_TX_CTL 30 +#define IMX8DXL_ENET0_RGMII_TXD0 31 +#define IMX8DXL_ENET0_RGMII_TXD1 32 +#define IMX8DXL_ENET0_RGMII_TXD2 33 +#define IMX8DXL_ENET0_RGMII_TXD3 34 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 35 +#define IMX8DXL_ENET0_RGMII_RXC 36 +#define IMX8DXL_ENET0_RGMII_RX_CTL 37 +#define IMX8DXL_ENET0_RGMII_RXD0 38 +#define IMX8DXL_ENET0_RGMII_RXD1 39 +#define IMX8DXL_ENET0_RGMII_RXD2 40 +#define IMX8DXL_ENET0_RGMII_RXD3 41 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 42 +#define IMX8DXL_ENET0_REFCLK_125M_25M 43 +#define IMX8DXL_ENET0_MDIO 44 +#define IMX8DXL_ENET0_MDC 45 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT 46 +#define IMX8DXL_ENET1_RGMII_TXC 47 +#define IMX8DXL_ENET1_RGMII_TXD2 48 +#define IMX8DXL_ENET1_RGMII_TX_CTL 49 +#define IMX8DXL_ENET1_RGMII_TXD3 50 +#define IMX8DXL_ENET1_RGMII_RXC 51 +#define IMX8DXL_ENET1_RGMII_RXD3 52 +#define IMX8DXL_ENET1_RGMII_RXD2 53 +#define IMX8DXL_ENET1_RGMII_RXD1 54 +#define IMX8DXL_ENET1_RGMII_TXD0 55 +#define IMX8DXL_ENET1_RGMII_TXD1 56 +#define IMX8DXL_ENET1_RGMII_RXD0 57 +#define IMX8DXL_ENET1_RGMII_RX_CTL 58 +#define IMX8DXL_ENET1_REFCLK_125M_25M 59 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB 60 +#define IMX8DXL_SPI3_SCK 61 +#define IMX8DXL_SPI3_SDO 62 +#define IMX8DXL_SPI3_SDI 63 +#define IMX8DXL_SPI3_CS0 64 +#define IMX8DXL_SPI3_CS1 65 +#define IMX8DXL_MCLK_IN1 66 +#define IMX8DXL_MCLK_IN0 67 +#define IMX8DXL_MCLK_OUT0 68 +#define IMX8DXL_UART1_TX 69 +#define IMX8DXL_UART1_RX 70 +#define IMX8DXL_UART1_RTS_B 71 +#define IMX8DXL_UART1_CTS_B 72 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK 73 +#define IMX8DXL_SPI0_SCK 74 +#define IMX8DXL_SPI0_SDI 75 +#define IMX8DXL_SPI0_SDO 76 +#define IMX8DXL_SPI0_CS1 77 +#define IMX8DXL_SPI0_CS0 78 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHT 79 +#define IMX8DXL_ADC_IN1 80 +#define IMX8DXL_ADC_IN0 81 +#define IMX8DXL_ADC_IN3 82 +#define IMX8DXL_ADC_IN2 83 +#define IMX8DXL_ADC_IN5 84 +#define IMX8DXL_ADC_IN4 85 +#define IMX8DXL_FLEXCAN0_RX 86 +#define IMX8DXL_FLEXCAN0_TX 87 +#define IMX8DXL_FLEXCAN1_RX 88 +#define IMX8DXL_FLEXCAN1_TX 89 +#define IMX8DXL_FLEXCAN2_RX 90 +#define IMX8DXL_FLEXCAN2_TX 91 +#define IMX8DXL_UART0_RX 92 +#define IMX8DXL_UART0_TX 93 +#define IMX8DXL_UART2_TX 94 +#define IMX8DXL_UART2_RX 95 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOLH 96 +#define IMX8DXL_JTAG_TRST_B 97 +#define IMX8DXL_PMIC_I2C_SCL 98 +#define IMX8DXL_PMIC_I2C_SDA 99 +#define IMX8DXL_PMIC_INT_B 100 +#define IMX8DXL_SCU_GPIO0_00 101 +#define IMX8DXL_SCU_GPIO0_01 102 +#define IMX8DXL_SCU_PMIC_STANDBY 103 +#define IMX8DXL_SCU_BOOT_MODE1 104 +#define IMX8DXL_SCU_BOOT_MODE0 105 +#define IMX8DXL_SCU_BOOT_MODE2 106 +#define IMX8DXL_SNVS_TAMPER_OUT1 107 +#define IMX8DXL_SNVS_TAMPER_OUT2 108 +#define IMX8DXL_SNVS_TAMPER_OUT3 109 +#define IMX8DXL_SNVS_TAMPER_OUT4 110 +#define IMX8DXL_SNVS_TAMPER_IN0 111 +#define IMX8DXL_SNVS_TAMPER_IN1 112 +#define IMX8DXL_SNVS_TAMPER_IN2 113 +#define IMX8DXL_SNVS_TAMPER_IN3 114 +#define IMX8DXL_SPI1_SCK 115 +#define IMX8DXL_SPI1_SDO 116 +#define IMX8DXL_SPI1_SDI 117 +#define IMX8DXL_SPI1_CS0 118 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHD 119 +#define IMX8DXL_QSPI0A_DATA1 120 +#define IMX8DXL_QSPI0A_DATA0 121 +#define IMX8DXL_QSPI0A_DATA3 122 +#define IMX8DXL_QSPI0A_DATA2 123 +#define IMX8DXL_QSPI0A_SS0_B 124 +#define IMX8DXL_QSPI0A_DQS 125 +#define IMX8DXL_QSPI0A_SCLK 126 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0A 127 +#define IMX8DXL_QSPI0B_SCLK 128 +#define IMX8DXL_QSPI0B_DQS 129 +#define IMX8DXL_QSPI0B_DATA1 130 +#define IMX8DXL_QSPI0B_DATA0 131 +#define IMX8DXL_QSPI0B_DATA3 132 +#define IMX8DXL_QSPI0B_DATA2 133 +#define IMX8DXL_QSPI0B_SS0_B 134 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0B 135 + +/* format: */ +#define IMX8DXL_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B IMX8DXL_PCIE_CTRL0_PERST_B 0 +#define IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 IMX8DXL_PCIE_CTRL0_PERST_B 4 +#define IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO7_IO00 IMX8DXL_PCIE_CTRL0_PERST_B 5 +#define IMX8DXL_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B IMX8DXL_PCIE_CTRL0_CLKREQ_B 0 +#define IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 IMX8DXL_PCIE_CTRL0_CLKREQ_B 4 +#define IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO7_IO01 IMX8DXL_PCIE_CTRL0_CLKREQ_B 5 +#define IMX8DXL_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B IMX8DXL_PCIE_CTRL0_WAKE_B 0 +#define IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 IMX8DXL_PCIE_CTRL0_WAKE_B 4 +#define IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO7_IO02 IMX8DXL_PCIE_CTRL0_WAKE_B 5 +#define IMX8DXL_USB_SS3_TC0_ADMA_I2C1_SCL IMX8DXL_USB_SS3_TC0 0 +#define IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR IMX8DXL_USB_SS3_TC0 1 +#define IMX8DXL_USB_SS3_TC0_CONN_USB_OTG2_PWR IMX8DXL_USB_SS3_TC0 2 +#define IMX8DXL_USB_SS3_TC0_LSIO_GPIO4_IO03 IMX8DXL_USB_SS3_TC0 4 +#define IMX8DXL_USB_SS3_TC0_LSIO_GPIO7_IO03 IMX8DXL_USB_SS3_TC0 5 +#define IMX8DXL_USB_SS3_TC1_ADMA_I2C1_SCL IMX8DXL_USB_SS3_TC1 0 +#define IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR IMX8DXL_USB_SS3_TC1 1 +#define IMX8DXL_USB_SS3_TC1_LSIO_GPIO4_IO04 IMX8DXL_USB_SS3_TC1 4 +#define IMX8DXL_USB_SS3_TC1_LSIO_GPIO7_IO04 IMX8DXL_USB_SS3_TC1 5 +#define IMX8DXL_USB_SS3_TC2_ADMA_I2C1_SDA IMX8DXL_USB_SS3_TC2 0 +#define IMX8DXL_USB_SS3_TC2_CONN_USB_OTG1_OC IMX8DXL_USB_SS3_TC2 1 +#define IMX8DXL_USB_SS3_TC2_CONN_USB_OTG2_OC IMX8DXL_USB_SS3_TC2 2 +#define IMX8DXL_USB_SS3_TC2_LSIO_GPIO4_IO05 IMX8DXL_USB_SS3_TC2 4 +#define IMX8DXL_USB_SS3_TC2_LSIO_GPIO7_IO05 IMX8DXL_USB_SS3_TC2 5 +#define IMX8DXL_USB_SS3_TC3_ADMA_I2C1_SDA IMX8DXL_USB_SS3_TC3 0 +#define IMX8DXL_USB_SS3_TC3_CONN_USB_OTG2_OC IMX8DXL_USB_SS3_TC3 1 +#define IMX8DXL_USB_SS3_TC3_LSIO_GPIO4_IO06 IMX8DXL_USB_SS3_TC3 4 +#define IMX8DXL_USB_SS3_TC3_LSIO_GPIO7_IO06 IMX8DXL_USB_SS3_TC3 5 +#define IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK IMX8DXL_EMMC0_CLK 0 +#define IMX8DXL_EMMC0_CLK_CONN_NAND_READY_B IMX8DXL_EMMC0_CLK 1 +#define IMX8DXL_EMMC0_CLK_LSIO_GPIO4_IO07 IMX8DXL_EMMC0_CLK 4 +#define IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD IMX8DXL_EMMC0_CMD 0 +#define IMX8DXL_EMMC0_CMD_CONN_NAND_DQS IMX8DXL_EMMC0_CMD 1 +#define IMX8DXL_EMMC0_CMD_LSIO_GPIO4_IO08 IMX8DXL_EMMC0_CMD 4 +#define IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 IMX8DXL_EMMC0_DATA0 0 +#define IMX8DXL_EMMC0_DATA0_CONN_NAND_DATA00 IMX8DXL_EMMC0_DATA0 1 +#define IMX8DXL_EMMC0_DATA0_LSIO_GPIO4_IO09 IMX8DXL_EMMC0_DATA0 4 +#define IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 IMX8DXL_EMMC0_DATA1 0 +#define IMX8DXL_EMMC0_DATA1_CONN_NAND_DATA01 IMX8DXL_EMMC0_DATA1 1 +#define IMX8DXL_EMMC0_DATA1_LSIO_GPIO4_IO10 IMX8DXL_EMMC0_DATA1 4 +#define IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 IMX8DXL_EMMC0_DATA2 0 +#define IMX8DXL_EMMC0_DATA2_CONN_NAND_DATA02 IMX8DXL_EMMC0_DATA2 1 +#define IMX8DXL_EMMC0_DATA2_LSIO_GPIO4_IO11 IMX8DXL_EMMC0_DATA2 4 +#define IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 IMX8DXL_EMMC0_DATA3 0 +#define IMX8DXL_EMMC0_DATA3_CONN_NAND_DATA03 IMX8DXL_EMMC0_DATA3 1 +#define IMX8DXL_EMMC0_DATA3_LSIO_GPIO4_IO12 IMX8DXL_EMMC0_DATA3 4 +#define IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 IMX8DXL_EMMC0_DATA4 0 +#define IMX8DXL_EMMC0_DATA4_CONN_NAND_DATA04 IMX8DXL_EMMC0_DATA4 1 +#define IMX8DXL_EMMC0_DATA4_LSIO_GPIO4_IO13 IMX8DXL_EMMC0_DATA4 4 +#define IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 IMX8DXL_EMMC0_DATA5 0 +#define IMX8DXL_EMMC0_DATA5_CONN_NAND_DATA05 IMX8DXL_EMMC0_DATA5 1 +#define IMX8DXL_EMMC0_DATA5_LSIO_GPIO4_IO14 IMX8DXL_EMMC0_DATA5 4 +#define IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 IMX8DXL_EMMC0_DATA6 0 +#define IMX8DXL_EMMC0_DATA6_CONN_NAND_DATA06 IMX8DXL_EMMC0_DATA6 1 +#define IMX8DXL_EMMC0_DATA6_LSIO_GPIO4_IO15 IMX8DXL_EMMC0_DATA6 4 +#define IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 IMX8DXL_EMMC0_DATA7 0 +#define IMX8DXL_EMMC0_DATA7_CONN_NAND_DATA07 IMX8DXL_EMMC0_DATA7 1 +#define IMX8DXL_EMMC0_DATA7_LSIO_GPIO4_IO16 IMX8DXL_EMMC0_DATA7 4 +#define IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE IMX8DXL_EMMC0_STROBE 0 +#define IMX8DXL_EMMC0_STROBE_CONN_NAND_CLE IMX8DXL_EMMC0_STROBE 1 +#define IMX8DXL_EMMC0_STROBE_LSIO_GPIO4_IO17 IMX8DXL_EMMC0_STROBE 4 +#define IMX8DXL_EMMC0_RESET_B_CONN_EMMC0_RESET_B IMX8DXL_EMMC0_RESET_B 0 +#define IMX8DXL_EMMC0_RESET_B_CONN_NAND_WP_B IMX8DXL_EMMC0_RESET_B 1 +#define IMX8DXL_EMMC0_RESET_B_LSIO_GPIO4_IO18 IMX8DXL_EMMC0_RESET_B 4 +#define IMX8DXL_USDHC1_RESET_B_CONN_USDHC1_RESET_B IMX8DXL_USDHC1_RESET_B 0 +#define IMX8DXL_USDHC1_RESET_B_CONN_NAND_RE_N IMX8DXL_USDHC1_RESET_B 1 +#define IMX8DXL_USDHC1_RESET_B_ADMA_SPI2_SCK IMX8DXL_USDHC1_RESET_B 2 +#define IMX8DXL_USDHC1_RESET_B_CONN_NAND_WE_B IMX8DXL_USDHC1_RESET_B 3 +#define IMX8DXL_USDHC1_RESET_B_LSIO_GPIO4_IO19 IMX8DXL_USDHC1_RESET_B 4 +#define IMX8DXL_USDHC1_RESET_B_LSIO_GPIO7_IO08 IMX8DXL_USDHC1_RESET_B 5 +#define IMX8DXL_USDHC1_VSELECT_CONN_USDHC1_VSELECT IMX8DXL_USDHC1_VSELECT 0 +#define IMX8DXL_USDHC1_VSELECT_CONN_NAND_RE_P IMX8DXL_USDHC1_VSELECT 1 +#define IMX8DXL_USDHC1_VSELECT_ADMA_SPI2_SDO IMX8DXL_USDHC1_VSELECT 2 +#define IMX8DXL_USDHC1_VSELECT_CONN_NAND_RE_B IMX8DXL_USDHC1_VSELECT 3 +#define IMX8DXL_USDHC1_VSELECT_LSIO_GPIO4_IO20 IMX8DXL_USDHC1_VSELECT 4 +#define IMX8DXL_USDHC1_VSELECT_LSIO_GPIO7_IO09 IMX8DXL_USDHC1_VSELECT 5 +#define IMX8DXL_USDHC1_WP_CONN_USDHC1_WP IMX8DXL_USDHC1_WP 0 +#define IMX8DXL_USDHC1_WP_CONN_NAND_DQS_N IMX8DXL_USDHC1_WP 1 +#define IMX8DXL_USDHC1_WP_ADMA_SPI2_SDI IMX8DXL_USDHC1_WP 2 +#define IMX8DXL_USDHC1_WP_CONN_NAND_ALE IMX8DXL_USDHC1_WP 3 +#define IMX8DXL_USDHC1_WP_LSIO_GPIO4_IO21 IMX8DXL_USDHC1_WP 4 +#define IMX8DXL_USDHC1_WP_LSIO_GPIO7_IO10 IMX8DXL_USDHC1_WP 5 +#define IMX8DXL_USDHC1_CD_B_CONN_USDHC1_CD_B IMX8DXL_USDHC1_CD_B 0 +#define IMX8DXL_USDHC1_CD_B_CONN_NAND_DQS_P IMX8DXL_USDHC1_CD_B 1 +#define IMX8DXL_USDHC1_CD_B_ADMA_SPI2_CS0 IMX8DXL_USDHC1_CD_B 2 +#define IMX8DXL_USDHC1_CD_B_CONN_NAND_DQS IMX8DXL_USDHC1_CD_B 3 +#define IMX8DXL_USDHC1_CD_B_LSIO_GPIO4_IO22 IMX8DXL_USDHC1_CD_B 4 +#define IMX8DXL_USDHC1_CD_B_LSIO_GPIO7_IO11 IMX8DXL_USDHC1_CD_B 5 +#define IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC IMX8DXL_ENET0_RGMII_TXC 0 +#define IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT IMX8DXL_ENET0_RGMII_TXC 1 +#define IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN IMX8DXL_ENET0_RGMII_TXC 2 +#define IMX8DXL_ENET0_RGMII_TXC_CONN_NAND_CE1_B IMX8DXL_ENET0_RGMII_TXC 3 +#define IMX8DXL_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 IMX8DXL_ENET0_RGMII_TXC 4 +#define IMX8DXL_ENET0_RGMII_TXC_CONN_USDHC2_CLK IMX8DXL_ENET0_RGMII_TXC 5 +#define IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL IMX8DXL_ENET0_RGMII_TX_CTL 0 +#define IMX8DXL_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B IMX8DXL_ENET0_RGMII_TX_CTL 3 +#define IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 IMX8DXL_ENET0_RGMII_TX_CTL 4 +#define IMX8DXL_ENET0_RGMII_TX_CTL_CONN_USDHC2_CMD IMX8DXL_ENET0_RGMII_TX_CTL 5 +#define IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 IMX8DXL_ENET0_RGMII_TXD0 0 +#define IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT IMX8DXL_ENET0_RGMII_TXD0 3 +#define IMX8DXL_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 IMX8DXL_ENET0_RGMII_TXD0 4 +#define IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC2_DATA0 IMX8DXL_ENET0_RGMII_TXD0 5 +#define IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 IMX8DXL_ENET0_RGMII_TXD1 0 +#define IMX8DXL_ENET0_RGMII_TXD1_CONN_USDHC1_WP IMX8DXL_ENET0_RGMII_TXD1 3 +#define IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 IMX8DXL_ENET0_RGMII_TXD1 4 +#define IMX8DXL_ENET0_RGMII_TXD1_CONN_USDHC2_DATA1 IMX8DXL_ENET0_RGMII_TXD1 5 +#define IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 IMX8DXL_ENET0_RGMII_TXD2 0 +#define IMX8DXL_ENET0_RGMII_TXD2_CONN_NAND_CE0_B IMX8DXL_ENET0_RGMII_TXD2 2 +#define IMX8DXL_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B IMX8DXL_ENET0_RGMII_TXD2 3 +#define IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 IMX8DXL_ENET0_RGMII_TXD2 4 +#define IMX8DXL_ENET0_RGMII_TXD2_CONN_USDHC2_DATA2 IMX8DXL_ENET0_RGMII_TXD2 5 +#define IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 IMX8DXL_ENET0_RGMII_TXD3 0 +#define IMX8DXL_ENET0_RGMII_TXD3_CONN_NAND_RE_B IMX8DXL_ENET0_RGMII_TXD3 2 +#define IMX8DXL_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 IMX8DXL_ENET0_RGMII_TXD3 4 +#define IMX8DXL_ENET0_RGMII_TXD3_CONN_USDHC2_DATA3 IMX8DXL_ENET0_RGMII_TXD3 5 +#define IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC IMX8DXL_ENET0_RGMII_RXC 0 +#define IMX8DXL_ENET0_RGMII_RXC_CONN_NAND_WE_B IMX8DXL_ENET0_RGMII_RXC 2 +#define IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK IMX8DXL_ENET0_RGMII_RXC 3 +#define IMX8DXL_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 IMX8DXL_ENET0_RGMII_RXC 4 +#define IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL IMX8DXL_ENET0_RGMII_RX_CTL 0 +#define IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD IMX8DXL_ENET0_RGMII_RX_CTL 3 +#define IMX8DXL_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 IMX8DXL_ENET0_RGMII_RX_CTL 4 +#define IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 IMX8DXL_ENET0_RGMII_RXD0 0 +#define IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 IMX8DXL_ENET0_RGMII_RXD0 3 +#define IMX8DXL_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 IMX8DXL_ENET0_RGMII_RXD0 4 +#define IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 IMX8DXL_ENET0_RGMII_RXD1 0 +#define IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 IMX8DXL_ENET0_RGMII_RXD1 3 +#define IMX8DXL_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 IMX8DXL_ENET0_RGMII_RXD1 4 +#define IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 IMX8DXL_ENET0_RGMII_RXD2 0 +#define IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER IMX8DXL_ENET0_RGMII_RXD2 1 +#define IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 IMX8DXL_ENET0_RGMII_RXD2 3 +#define IMX8DXL_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 IMX8DXL_ENET0_RGMII_RXD2 4 +#define IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 IMX8DXL_ENET0_RGMII_RXD3 0 +#define IMX8DXL_ENET0_RGMII_RXD3_CONN_NAND_ALE IMX8DXL_ENET0_RGMII_RXD3 2 +#define IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 IMX8DXL_ENET0_RGMII_RXD3 3 +#define IMX8DXL_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 IMX8DXL_ENET0_RGMII_RXD3 4 +#define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M IMX8DXL_ENET0_REFCLK_125M_25M 0 +#define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS IMX8DXL_ENET0_REFCLK_125M_25M 1 +#define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_EQOS_PPS_IN IMX8DXL_ENET0_REFCLK_125M_25M 2 +#define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_EQOS_PPS_OUT IMX8DXL_ENET0_REFCLK_125M_25M 3 +#define IMX8DXL_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 IMX8DXL_ENET0_REFCLK_125M_25M 4 +#define IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO IMX8DXL_ENET0_MDIO 0 +#define IMX8DXL_ENET0_MDIO_ADMA_I2C3_SDA IMX8DXL_ENET0_MDIO 1 +#define IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO IMX8DXL_ENET0_MDIO 2 +#define IMX8DXL_ENET0_MDIO_LSIO_GPIO5_IO10 IMX8DXL_ENET0_MDIO 4 +#define IMX8DXL_ENET0_MDIO_LSIO_GPIO7_IO16 IMX8DXL_ENET0_MDIO 5 +#define IMX8DXL_ENET0_MDC_CONN_ENET0_MDC IMX8DXL_ENET0_MDC 0 +#define IMX8DXL_ENET0_MDC_ADMA_I2C3_SCL IMX8DXL_ENET0_MDC 1 +#define IMX8DXL_ENET0_MDC_CONN_EQOS_MDC IMX8DXL_ENET0_MDC 2 +#define IMX8DXL_ENET0_MDC_LSIO_GPIO5_IO11 IMX8DXL_ENET0_MDC 4 +#define IMX8DXL_ENET0_MDC_LSIO_GPIO7_IO17 IMX8DXL_ENET0_MDC 5 +#define IMX8DXL_ENET1_RGMII_TXC_LSIO_GPIO0_IO00 IMX8DXL_ENET1_RGMII_TXC 0 +#define IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RCLK50M_OUT IMX8DXL_ENET1_RGMII_TXC 1 +#define IMX8DXL_ENET1_RGMII_TXC_ADMA_LCDIF_D00 IMX8DXL_ENET1_RGMII_TXC 2 +#define IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC IMX8DXL_ENET1_RGMII_TXC 3 +#define IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RCLK50M_IN IMX8DXL_ENET1_RGMII_TXC 4 +#define IMX8DXL_ENET1_RGMII_TXD2_ADMA_LCDIF_D01 IMX8DXL_ENET1_RGMII_TXD2 2 +#define IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 IMX8DXL_ENET1_RGMII_TXD2 3 +#define IMX8DXL_ENET1_RGMII_TXD2_LSIO_GPIO0_IO01 IMX8DXL_ENET1_RGMII_TXD2 4 +#define IMX8DXL_ENET1_RGMII_TX_CTL_ADMA_LCDIF_D02 IMX8DXL_ENET1_RGMII_TX_CTL 2 +#define IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL IMX8DXL_ENET1_RGMII_TX_CTL 3 +#define IMX8DXL_ENET1_RGMII_TX_CTL_LSIO_GPIO0_IO02 IMX8DXL_ENET1_RGMII_TX_CTL 4 +#define IMX8DXL_ENET1_RGMII_TXD3_ADMA_LCDIF_D03 IMX8DXL_ENET1_RGMII_TXD3 2 +#define IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 IMX8DXL_ENET1_RGMII_TXD3 3 +#define IMX8DXL_ENET1_RGMII_TXD3_LSIO_GPIO0_IO03 IMX8DXL_ENET1_RGMII_TXD3 4 +#define IMX8DXL_ENET1_RGMII_RXC_ADMA_LCDIF_D04 IMX8DXL_ENET1_RGMII_RXC 2 +#define IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC IMX8DXL_ENET1_RGMII_RXC 3 +#define IMX8DXL_ENET1_RGMII_RXC_LSIO_GPIO0_IO04 IMX8DXL_ENET1_RGMII_RXC 4 +#define IMX8DXL_ENET1_RGMII_RXD3_ADMA_LCDIF_D05 IMX8DXL_ENET1_RGMII_RXD3 2 +#define IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 IMX8DXL_ENET1_RGMII_RXD3 3 +#define IMX8DXL_ENET1_RGMII_RXD3_LSIO_GPIO0_IO05 IMX8DXL_ENET1_RGMII_RXD3 4 +#define IMX8DXL_ENET1_RGMII_RXD2_ADMA_LCDIF_D06 IMX8DXL_ENET1_RGMII_RXD2 2 +#define IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 IMX8DXL_ENET1_RGMII_RXD2 3 +#define IMX8DXL_ENET1_RGMII_RXD2_LSIO_GPIO0_IO06 IMX8DXL_ENET1_RGMII_RXD2 4 +#define IMX8DXL_ENET1_RGMII_RXD2_LSIO_GPIO6_IO00 IMX8DXL_ENET1_RGMII_RXD2 5 +#define IMX8DXL_ENET1_RGMII_RXD1_ADMA_LCDIF_D07 IMX8DXL_ENET1_RGMII_RXD1 2 +#define IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 IMX8DXL_ENET1_RGMII_RXD1 3 +#define IMX8DXL_ENET1_RGMII_RXD1_LSIO_GPIO0_IO07 IMX8DXL_ENET1_RGMII_RXD1 4 +#define IMX8DXL_ENET1_RGMII_RXD1_LSIO_GPIO6_IO01 IMX8DXL_ENET1_RGMII_RXD1 5 +#define IMX8DXL_ENET1_RGMII_TXD0_ADMA_LCDIF_D08 IMX8DXL_ENET1_RGMII_TXD0 2 +#define IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 IMX8DXL_ENET1_RGMII_TXD0 3 +#define IMX8DXL_ENET1_RGMII_TXD0_LSIO_GPIO0_IO08 IMX8DXL_ENET1_RGMII_TXD0 4 +#define IMX8DXL_ENET1_RGMII_TXD0_LSIO_GPIO6_IO02 IMX8DXL_ENET1_RGMII_TXD0 5 +#define IMX8DXL_ENET1_RGMII_TXD1_ADMA_LCDIF_D09 IMX8DXL_ENET1_RGMII_TXD1 2 +#define IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 IMX8DXL_ENET1_RGMII_TXD1 3 +#define IMX8DXL_ENET1_RGMII_TXD1_LSIO_GPIO0_IO09 IMX8DXL_ENET1_RGMII_TXD1 4 +#define IMX8DXL_ENET1_RGMII_TXD1_LSIO_GPIO6_IO03 IMX8DXL_ENET1_RGMII_TXD1 5 +#define IMX8DXL_ENET1_RGMII_RXD0_ADMA_SPDIF0_RX IMX8DXL_ENET1_RGMII_RXD0 0 +#define IMX8DXL_ENET1_RGMII_RXD0_ADMA_MQS_R IMX8DXL_ENET1_RGMII_RXD0 1 +#define IMX8DXL_ENET1_RGMII_RXD0_ADMA_LCDIF_D10 IMX8DXL_ENET1_RGMII_RXD0 2 +#define IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 IMX8DXL_ENET1_RGMII_RXD0 3 +#define IMX8DXL_ENET1_RGMII_RXD0_LSIO_GPIO0_IO10 IMX8DXL_ENET1_RGMII_RXD0 4 +#define IMX8DXL_ENET1_RGMII_RXD0_LSIO_GPIO6_IO04 IMX8DXL_ENET1_RGMII_RXD0 5 +#define IMX8DXL_ENET1_RGMII_RX_CTL_ADMA_SPDIF0_TX IMX8DXL_ENET1_RGMII_RX_CTL 0 +#define IMX8DXL_ENET1_RGMII_RX_CTL_ADMA_MQS_L IMX8DXL_ENET1_RGMII_RX_CTL 1 +#define IMX8DXL_ENET1_RGMII_RX_CTL_ADMA_LCDIF_D11 IMX8DXL_ENET1_RGMII_RX_CTL 2 +#define IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL IMX8DXL_ENET1_RGMII_RX_CTL 3 +#define IMX8DXL_ENET1_RGMII_RX_CTL_LSIO_GPIO0_IO11 IMX8DXL_ENET1_RGMII_RX_CTL 4 +#define IMX8DXL_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO05 IMX8DXL_ENET1_RGMII_RX_CTL 5 +#define IMX8DXL_ENET1_REFCLK_125M_25M_ADMA_SPDIF0_EXT_CLK IMX8DXL_ENET1_REFCLK_125M_25M 0 +#define IMX8DXL_ENET1_REFCLK_125M_25M_ADMA_LCDIF_D12 IMX8DXL_ENET1_REFCLK_125M_25M 2 +#define IMX8DXL_ENET1_REFCLK_125M_25M_CONN_EQOS_REFCLK_125M_25M IMX8DXL_ENET1_REFCLK_125M_25M 3 +#define IMX8DXL_ENET1_REFCLK_125M_25M_LSIO_GPIO0_IO12 IMX8DXL_ENET1_REFCLK_125M_25M 4 +#define IMX8DXL_ENET1_REFCLK_125M_25M_LSIO_GPIO6_IO06 IMX8DXL_ENET1_REFCLK_125M_25M 5 +#define IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK IMX8DXL_SPI3_SCK 0 +#define IMX8DXL_SPI3_SCK_ADMA_LCDIF_D13 IMX8DXL_SPI3_SCK 2 +#define IMX8DXL_SPI3_SCK_LSIO_GPIO0_IO13 IMX8DXL_SPI3_SCK 4 +#define IMX8DXL_SPI3_SCK_ADMA_LCDIF_D00 IMX8DXL_SPI3_SCK 5 +#define IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO IMX8DXL_SPI3_SDO 0 +#define IMX8DXL_SPI3_SDO_ADMA_LCDIF_D14 IMX8DXL_SPI3_SDO 2 +#define IMX8DXL_SPI3_SDO_LSIO_GPIO0_IO14 IMX8DXL_SPI3_SDO 4 +#define IMX8DXL_SPI3_SDO_ADMA_LCDIF_D01 IMX8DXL_SPI3_SDO 5 +#define IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI IMX8DXL_SPI3_SDI 0 +#define IMX8DXL_SPI3_SDI_ADMA_LCDIF_D15 IMX8DXL_SPI3_SDI 2 +#define IMX8DXL_SPI3_SDI_LSIO_GPIO0_IO15 IMX8DXL_SPI3_SDI 4 +#define IMX8DXL_SPI3_SDI_ADMA_LCDIF_D02 IMX8DXL_SPI3_SDI 5 +#define IMX8DXL_SPI3_CS0_ADMA_SPI3_CS0 IMX8DXL_SPI3_CS0 0 +#define IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1 IMX8DXL_SPI3_CS0 1 +#define IMX8DXL_SPI3_CS0_ADMA_LCDIF_HSYNC IMX8DXL_SPI3_CS0 2 +#define IMX8DXL_SPI3_CS0_LSIO_GPIO0_IO16 IMX8DXL_SPI3_CS0 4 +#define IMX8DXL_SPI3_CS0_ADMA_LCDIF_CS IMX8DXL_SPI3_CS0 5 +#define IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 IMX8DXL_SPI3_CS1 0 +#define IMX8DXL_SPI3_CS1_ADMA_I2C3_SCL IMX8DXL_SPI3_CS1 1 +#define IMX8DXL_SPI3_CS1_ADMA_LCDIF_RESET IMX8DXL_SPI3_CS1 2 +#define IMX8DXL_SPI3_CS1_ADMA_SPI2_CS0 IMX8DXL_SPI3_CS1 3 +#define IMX8DXL_SPI3_CS1_ADMA_LCDIF_D16 IMX8DXL_SPI3_CS1 4 +#define IMX8DXL_SPI3_CS1_ADMA_LCDIF_RD_E IMX8DXL_SPI3_CS1 5 +#define IMX8DXL_MCLK_IN1_ADMA_ACM_MCLK_IN1 IMX8DXL_MCLK_IN1 0 +#define IMX8DXL_MCLK_IN1_ADMA_I2C3_SDA IMX8DXL_MCLK_IN1 1 +#define IMX8DXL_MCLK_IN1_ADMA_LCDIF_EN IMX8DXL_MCLK_IN1 2 +#define IMX8DXL_MCLK_IN1_ADMA_SPI2_SCK IMX8DXL_MCLK_IN1 3 +#define IMX8DXL_MCLK_IN1_ADMA_LCDIF_D17 IMX8DXL_MCLK_IN1 4 +#define IMX8DXL_MCLK_IN1_ADMA_LCDIF_D03 IMX8DXL_MCLK_IN1 5 +#define IMX8DXL_MCLK_IN0_ADMA_ACM_MCLK_IN0 IMX8DXL_MCLK_IN0 0 +#define IMX8DXL_MCLK_IN0_ADMA_LCDIF_VSYNC IMX8DXL_MCLK_IN0 2 +#define IMX8DXL_MCLK_IN0_ADMA_SPI2_SDI IMX8DXL_MCLK_IN0 3 +#define IMX8DXL_MCLK_IN0_LSIO_GPIO0_IO19 IMX8DXL_MCLK_IN0 4 +#define IMX8DXL_MCLK_IN0_ADMA_LCDIF_RS IMX8DXL_MCLK_IN0 5 +#define IMX8DXL_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 IMX8DXL_MCLK_OUT0 0 +#define IMX8DXL_MCLK_OUT0_ADMA_LCDIF_CLK IMX8DXL_MCLK_OUT0 2 +#define IMX8DXL_MCLK_OUT0_ADMA_SPI2_SDO IMX8DXL_MCLK_OUT0 3 +#define IMX8DXL_MCLK_OUT0_LSIO_GPIO0_IO20 IMX8DXL_MCLK_OUT0 4 +#define IMX8DXL_MCLK_OUT0_ADMA_LCDIF_WR_RWN IMX8DXL_MCLK_OUT0 5 +#define IMX8DXL_UART1_TX_ADMA_UART1_TX IMX8DXL_UART1_TX 0 +#define IMX8DXL_UART1_TX_LSIO_PWM0_OUT IMX8DXL_UART1_TX 1 +#define IMX8DXL_UART1_TX_LSIO_GPT0_CAPTURE IMX8DXL_UART1_TX 2 +#define IMX8DXL_UART1_TX_LSIO_GPIO0_IO21 IMX8DXL_UART1_TX 4 +#define IMX8DXL_UART1_TX_ADMA_LCDIF_D04 IMX8DXL_UART1_TX 5 +#define IMX8DXL_UART1_RX_ADMA_UART1_RX IMX8DXL_UART1_RX 0 +#define IMX8DXL_UART1_RX_LSIO_PWM1_OUT IMX8DXL_UART1_RX 1 +#define IMX8DXL_UART1_RX_LSIO_GPT0_COMPARE IMX8DXL_UART1_RX 2 +#define IMX8DXL_UART1_RX_LSIO_GPT1_CLK IMX8DXL_UART1_RX 3 +#define IMX8DXL_UART1_RX_LSIO_GPIO0_IO22 IMX8DXL_UART1_RX 4 +#define IMX8DXL_UART1_RX_ADMA_LCDIF_D05 IMX8DXL_UART1_RX 5 +#define IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B IMX8DXL_UART1_RTS_B 0 +#define IMX8DXL_UART1_RTS_B_LSIO_PWM2_OUT IMX8DXL_UART1_RTS_B 1 +#define IMX8DXL_UART1_RTS_B_ADMA_LCDIF_D16 IMX8DXL_UART1_RTS_B 2 +#define IMX8DXL_UART1_RTS_B_LSIO_GPT1_CAPTURE IMX8DXL_UART1_RTS_B 3 +#define IMX8DXL_UART1_RTS_B_LSIO_GPT0_CLK IMX8DXL_UART1_RTS_B 4 +#define IMX8DXL_UART1_RTS_B_ADMA_LCDIF_D06 IMX8DXL_UART1_RTS_B 5 +#define IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B IMX8DXL_UART1_CTS_B 0 +#define IMX8DXL_UART1_CTS_B_LSIO_PWM3_OUT IMX8DXL_UART1_CTS_B 1 +#define IMX8DXL_UART1_CTS_B_ADMA_LCDIF_D17 IMX8DXL_UART1_CTS_B 2 +#define IMX8DXL_UART1_CTS_B_LSIO_GPT1_COMPARE IMX8DXL_UART1_CTS_B 3 +#define IMX8DXL_UART1_CTS_B_LSIO_GPIO0_IO24 IMX8DXL_UART1_CTS_B 4 +#define IMX8DXL_UART1_CTS_B_ADMA_LCDIF_D07 IMX8DXL_UART1_CTS_B 5 +#define IMX8DXL_SPI0_SCK_ADMA_SPI0_SCK IMX8DXL_SPI0_SCK 0 +#define IMX8DXL_SPI0_SCK_ADMA_SAI0_TXC IMX8DXL_SPI0_SCK 1 +#define IMX8DXL_SPI0_SCK_M40_I2C0_SCL IMX8DXL_SPI0_SCK 2 +#define IMX8DXL_SPI0_SCK_M40_GPIO0_IO00 IMX8DXL_SPI0_SCK 3 +#define IMX8DXL_SPI0_SCK_LSIO_GPIO1_IO04 IMX8DXL_SPI0_SCK 4 +#define IMX8DXL_SPI0_SCK_ADMA_LCDIF_D08 IMX8DXL_SPI0_SCK 5 +#define IMX8DXL_SPI0_SDI_ADMA_SPI0_SDI IMX8DXL_SPI0_SDI 0 +#define IMX8DXL_SPI0_SDI_ADMA_SAI0_TXD IMX8DXL_SPI0_SDI 1 +#define IMX8DXL_SPI0_SDI_M40_TPM0_CH0 IMX8DXL_SPI0_SDI 2 +#define IMX8DXL_SPI0_SDI_M40_GPIO0_IO02 IMX8DXL_SPI0_SDI 3 +#define IMX8DXL_SPI0_SDI_LSIO_GPIO1_IO05 IMX8DXL_SPI0_SDI 4 +#define IMX8DXL_SPI0_SDI_ADMA_LCDIF_D09 IMX8DXL_SPI0_SDI 5 +#define IMX8DXL_SPI0_SDO_ADMA_SPI0_SDO IMX8DXL_SPI0_SDO 0 +#define IMX8DXL_SPI0_SDO_ADMA_SAI0_TXFS IMX8DXL_SPI0_SDO 1 +#define IMX8DXL_SPI0_SDO_M40_I2C0_SDA IMX8DXL_SPI0_SDO 2 +#define IMX8DXL_SPI0_SDO_M40_GPIO0_IO01 IMX8DXL_SPI0_SDO 3 +#define IMX8DXL_SPI0_SDO_LSIO_GPIO1_IO06 IMX8DXL_SPI0_SDO 4 +#define IMX8DXL_SPI0_SDO_ADMA_LCDIF_D10 IMX8DXL_SPI0_SDO 5 +#define IMX8DXL_SPI0_CS1_ADMA_SPI0_CS1 IMX8DXL_SPI0_CS1 0 +#define IMX8DXL_SPI0_CS1_ADMA_SAI0_RXC IMX8DXL_SPI0_CS1 1 +#define IMX8DXL_SPI0_CS1_ADMA_SAI1_TXD IMX8DXL_SPI0_CS1 2 +#define IMX8DXL_SPI0_CS1_ADMA_LCD_PWM0_OUT IMX8DXL_SPI0_CS1 3 +#define IMX8DXL_SPI0_CS1_LSIO_GPIO1_IO07 IMX8DXL_SPI0_CS1 4 +#define IMX8DXL_SPI0_CS1_ADMA_LCDIF_D11 IMX8DXL_SPI0_CS1 5 +#define IMX8DXL_SPI0_CS0_ADMA_SPI0_CS0 IMX8DXL_SPI0_CS0 0 +#define IMX8DXL_SPI0_CS0_ADMA_SAI0_RXD IMX8DXL_SPI0_CS0 1 +#define IMX8DXL_SPI0_CS0_M40_TPM0_CH1 IMX8DXL_SPI0_CS0 2 +#define IMX8DXL_SPI0_CS0_M40_GPIO0_IO03 IMX8DXL_SPI0_CS0 3 +#define IMX8DXL_SPI0_CS0_LSIO_GPIO1_IO08 IMX8DXL_SPI0_CS0 4 +#define IMX8DXL_SPI0_CS0_ADMA_LCDIF_D12 IMX8DXL_SPI0_CS0 5 +#define IMX8DXL_ADC_IN1_ADMA_ADC_IN1 IMX8DXL_ADC_IN1 0 +#define IMX8DXL_ADC_IN1_M40_I2C0_SDA IMX8DXL_ADC_IN1 1 +#define IMX8DXL_ADC_IN1_M40_GPIO0_IO01 IMX8DXL_ADC_IN1 2 +#define IMX8DXL_ADC_IN1_ADMA_I2C0_SDA IMX8DXL_ADC_IN1 3 +#define IMX8DXL_ADC_IN1_LSIO_GPIO1_IO09 IMX8DXL_ADC_IN1 4 +#define IMX8DXL_ADC_IN1_ADMA_LCDIF_D13 IMX8DXL_ADC_IN1 5 +#define IMX8DXL_ADC_IN0_ADMA_ADC_IN0 IMX8DXL_ADC_IN0 0 +#define IMX8DXL_ADC_IN0_M40_I2C0_SCL IMX8DXL_ADC_IN0 1 +#define IMX8DXL_ADC_IN0_M40_GPIO0_IO00 IMX8DXL_ADC_IN0 2 +#define IMX8DXL_ADC_IN0_ADMA_I2C0_SCL IMX8DXL_ADC_IN0 3 +#define IMX8DXL_ADC_IN0_LSIO_GPIO1_IO10 IMX8DXL_ADC_IN0 4 +#define IMX8DXL_ADC_IN0_ADMA_LCDIF_D14 IMX8DXL_ADC_IN0 5 +#define IMX8DXL_ADC_IN3_ADMA_ADC_IN3 IMX8DXL_ADC_IN3 0 +#define IMX8DXL_ADC_IN3_M40_UART0_TX IMX8DXL_ADC_IN3 1 +#define IMX8DXL_ADC_IN3_M40_GPIO0_IO03 IMX8DXL_ADC_IN3 2 +#define IMX8DXL_ADC_IN3_ADMA_ACM_MCLK_OUT0 IMX8DXL_ADC_IN3 3 +#define IMX8DXL_ADC_IN3_LSIO_GPIO1_IO11 IMX8DXL_ADC_IN3 4 +#define IMX8DXL_ADC_IN3_ADMA_LCDIF_D15 IMX8DXL_ADC_IN3 5 +#define IMX8DXL_ADC_IN2_ADMA_ADC_IN2 IMX8DXL_ADC_IN2 0 +#define IMX8DXL_ADC_IN2_M40_UART0_RX IMX8DXL_ADC_IN2 1 +#define IMX8DXL_ADC_IN2_M40_GPIO0_IO02 IMX8DXL_ADC_IN2 2 +#define IMX8DXL_ADC_IN2_ADMA_ACM_MCLK_IN0 IMX8DXL_ADC_IN2 3 +#define IMX8DXL_ADC_IN2_LSIO_GPIO1_IO12 IMX8DXL_ADC_IN2 4 +#define IMX8DXL_ADC_IN2_ADMA_LCDIF_D16 IMX8DXL_ADC_IN2 5 +#define IMX8DXL_ADC_IN5_ADMA_ADC_IN5 IMX8DXL_ADC_IN5 0 +#define IMX8DXL_ADC_IN5_M40_TPM0_CH1 IMX8DXL_ADC_IN5 1 +#define IMX8DXL_ADC_IN5_M40_GPIO0_IO05 IMX8DXL_ADC_IN5 2 +#define IMX8DXL_ADC_IN5_ADMA_LCDIF_LCDBUSY IMX8DXL_ADC_IN5 3 +#define IMX8DXL_ADC_IN5_LSIO_GPIO1_IO13 IMX8DXL_ADC_IN5 4 +#define IMX8DXL_ADC_IN5_ADMA_LCDIF_D17 IMX8DXL_ADC_IN5 5 +#define IMX8DXL_ADC_IN4_ADMA_ADC_IN4 IMX8DXL_ADC_IN4 0 +#define IMX8DXL_ADC_IN4_M40_TPM0_CH0 IMX8DXL_ADC_IN4 1 +#define IMX8DXL_ADC_IN4_M40_GPIO0_IO04 IMX8DXL_ADC_IN4 2 +#define IMX8DXL_ADC_IN4_ADMA_LCDIF_LCDRESET IMX8DXL_ADC_IN4 3 +#define IMX8DXL_ADC_IN4_LSIO_GPIO1_IO14 IMX8DXL_ADC_IN4 4 +#define IMX8DXL_FLEXCAN0_RX_ADMA_FLEXCAN0_RX IMX8DXL_FLEXCAN0_RX 0 +#define IMX8DXL_FLEXCAN0_RX_ADMA_SAI2_RXC IMX8DXL_FLEXCAN0_RX 1 +#define IMX8DXL_FLEXCAN0_RX_ADMA_UART0_RTS_B IMX8DXL_FLEXCAN0_RX 2 +#define IMX8DXL_FLEXCAN0_RX_ADMA_SAI1_TXC IMX8DXL_FLEXCAN0_RX 3 +#define IMX8DXL_FLEXCAN0_RX_LSIO_GPIO1_IO15 IMX8DXL_FLEXCAN0_RX 4 +#define IMX8DXL_FLEXCAN0_RX_LSIO_GPIO6_IO08 IMX8DXL_FLEXCAN0_RX 5 +#define IMX8DXL_FLEXCAN0_TX_ADMA_FLEXCAN0_TX IMX8DXL_FLEXCAN0_TX 0 +#define IMX8DXL_FLEXCAN0_TX_ADMA_SAI2_RXD IMX8DXL_FLEXCAN0_TX 1 +#define IMX8DXL_FLEXCAN0_TX_ADMA_UART0_CTS_B IMX8DXL_FLEXCAN0_TX 2 +#define IMX8DXL_FLEXCAN0_TX_ADMA_SAI1_TXFS IMX8DXL_FLEXCAN0_TX 3 +#define IMX8DXL_FLEXCAN0_TX_LSIO_GPIO1_IO16 IMX8DXL_FLEXCAN0_TX 4 +#define IMX8DXL_FLEXCAN0_TX_LSIO_GPIO6_IO09 IMX8DXL_FLEXCAN0_TX 5 +#define IMX8DXL_FLEXCAN1_RX_ADMA_FLEXCAN1_RX IMX8DXL_FLEXCAN1_RX 0 +#define IMX8DXL_FLEXCAN1_RX_ADMA_SAI2_RXFS IMX8DXL_FLEXCAN1_RX 1 +#define IMX8DXL_FLEXCAN1_RX_ADMA_FTM_CH2 IMX8DXL_FLEXCAN1_RX 2 +#define IMX8DXL_FLEXCAN1_RX_ADMA_SAI1_TXD IMX8DXL_FLEXCAN1_RX 3 +#define IMX8DXL_FLEXCAN1_RX_LSIO_GPIO1_IO17 IMX8DXL_FLEXCAN1_RX 4 +#define IMX8DXL_FLEXCAN1_RX_LSIO_GPIO6_IO10 IMX8DXL_FLEXCAN1_RX 5 +#define IMX8DXL_FLEXCAN1_TX_ADMA_FLEXCAN1_TX IMX8DXL_FLEXCAN1_TX 0 +#define IMX8DXL_FLEXCAN1_TX_ADMA_SAI3_RXC IMX8DXL_FLEXCAN1_TX 1 +#define IMX8DXL_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0 IMX8DXL_FLEXCAN1_TX 2 +#define IMX8DXL_FLEXCAN1_TX_ADMA_SAI1_RXD IMX8DXL_FLEXCAN1_TX 3 +#define IMX8DXL_FLEXCAN1_TX_LSIO_GPIO1_IO18 IMX8DXL_FLEXCAN1_TX 4 +#define IMX8DXL_FLEXCAN1_TX_LSIO_GPIO6_IO11 IMX8DXL_FLEXCAN1_TX 5 +#define IMX8DXL_FLEXCAN2_RX_ADMA_FLEXCAN2_RX IMX8DXL_FLEXCAN2_RX 0 +#define IMX8DXL_FLEXCAN2_RX_ADMA_SAI3_RXD IMX8DXL_FLEXCAN2_RX 1 +#define IMX8DXL_FLEXCAN2_RX_ADMA_UART3_RX IMX8DXL_FLEXCAN2_RX 2 +#define IMX8DXL_FLEXCAN2_RX_ADMA_SAI1_RXFS IMX8DXL_FLEXCAN2_RX 3 +#define IMX8DXL_FLEXCAN2_RX_LSIO_GPIO1_IO19 IMX8DXL_FLEXCAN2_RX 4 +#define IMX8DXL_FLEXCAN2_RX_LSIO_GPIO6_IO12 IMX8DXL_FLEXCAN2_RX 5 +#define IMX8DXL_FLEXCAN2_TX_ADMA_FLEXCAN2_TX IMX8DXL_FLEXCAN2_TX 0 +#define IMX8DXL_FLEXCAN2_TX_ADMA_SAI3_RXFS IMX8DXL_FLEXCAN2_TX 1 +#define IMX8DXL_FLEXCAN2_TX_ADMA_UART3_TX IMX8DXL_FLEXCAN2_TX 2 +#define IMX8DXL_FLEXCAN2_TX_ADMA_SAI1_RXC IMX8DXL_FLEXCAN2_TX 3 +#define IMX8DXL_FLEXCAN2_TX_LSIO_GPIO1_IO20 IMX8DXL_FLEXCAN2_TX 4 +#define IMX8DXL_FLEXCAN2_TX_LSIO_GPIO6_IO13 IMX8DXL_FLEXCAN2_TX 5 +#define IMX8DXL_UART0_RX_ADMA_UART0_RX IMX8DXL_UART0_RX 0 +#define IMX8DXL_UART0_RX_ADMA_MQS_R IMX8DXL_UART0_RX 1 +#define IMX8DXL_UART0_RX_ADMA_FLEXCAN0_RX IMX8DXL_UART0_RX 2 +#define IMX8DXL_UART0_RX_SCU_UART0_RX IMX8DXL_UART0_RX 3 +#define IMX8DXL_UART0_RX_LSIO_GPIO1_IO21 IMX8DXL_UART0_RX 4 +#define IMX8DXL_UART0_RX_LSIO_GPIO6_IO14 IMX8DXL_UART0_RX 5 +#define IMX8DXL_UART0_TX_ADMA_UART0_TX IMX8DXL_UART0_TX 0 +#define IMX8DXL_UART0_TX_ADMA_MQS_L IMX8DXL_UART0_TX 1 +#define IMX8DXL_UART0_TX_ADMA_FLEXCAN0_TX IMX8DXL_UART0_TX 2 +#define IMX8DXL_UART0_TX_SCU_UART0_TX IMX8DXL_UART0_TX 3 +#define IMX8DXL_UART0_TX_LSIO_GPIO1_IO22 IMX8DXL_UART0_TX 4 +#define IMX8DXL_UART0_TX_LSIO_GPIO6_IO15 IMX8DXL_UART0_TX 5 +#define IMX8DXL_UART2_TX_ADMA_UART2_TX IMX8DXL_UART2_TX 0 +#define IMX8DXL_UART2_TX_ADMA_FTM_CH1 IMX8DXL_UART2_TX 1 +#define IMX8DXL_UART2_TX_ADMA_FLEXCAN1_TX IMX8DXL_UART2_TX 2 +#define IMX8DXL_UART2_TX_LSIO_GPIO1_IO23 IMX8DXL_UART2_TX 4 +#define IMX8DXL_UART2_TX_LSIO_GPIO6_IO16 IMX8DXL_UART2_TX 5 +#define IMX8DXL_UART2_RX_ADMA_UART2_RX IMX8DXL_UART2_RX 0 +#define IMX8DXL_UART2_RX_ADMA_FTM_CH0 IMX8DXL_UART2_RX 1 +#define IMX8DXL_UART2_RX_ADMA_FLEXCAN1_RX IMX8DXL_UART2_RX 2 +#define IMX8DXL_UART2_RX_LSIO_GPIO1_IO24 IMX8DXL_UART2_RX 4 +#define IMX8DXL_UART2_RX_LSIO_GPIO6_IO17 IMX8DXL_UART2_RX 5 +#define IMX8DXL_JTAG_TRST_B_SCU_JTAG_TRST_B IMX8DXL_JTAG_TRST_B 0 +#define IMX8DXL_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT IMX8DXL_JTAG_TRST_B 1 +#define IMX8DXL_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL IMX8DXL_PMIC_I2C_SCL 0 +#define IMX8DXL_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON IMX8DXL_PMIC_I2C_SCL 1 +#define IMX8DXL_PMIC_I2C_SCL_LSIO_GPIO2_IO01 IMX8DXL_PMIC_I2C_SCL 4 +#define IMX8DXL_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA IMX8DXL_PMIC_I2C_SDA 0 +#define IMX8DXL_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON IMX8DXL_PMIC_I2C_SDA 1 +#define IMX8DXL_PMIC_I2C_SDA_LSIO_GPIO2_IO02 IMX8DXL_PMIC_I2C_SDA 4 +#define IMX8DXL_PMIC_INT_B_SCU_DSC_PMIC_INT_B IMX8DXL_PMIC_INT_B 0 +#define IMX8DXL_SCU_GPIO0_00_SCU_GPIO0_IO00 IMX8DXL_SCU_GPIO0_00 0 +#define IMX8DXL_SCU_GPIO0_00_SCU_UART0_RX IMX8DXL_SCU_GPIO0_00 1 +#define IMX8DXL_SCU_GPIO0_00_M40_UART0_RX IMX8DXL_SCU_GPIO0_00 2 +#define IMX8DXL_SCU_GPIO0_00_ADMA_UART3_RX IMX8DXL_SCU_GPIO0_00 3 +#define IMX8DXL_SCU_GPIO0_00_LSIO_GPIO2_IO03 IMX8DXL_SCU_GPIO0_00 4 +#define IMX8DXL_SCU_GPIO0_01_SCU_GPIO0_IO01 IMX8DXL_SCU_GPIO0_01 0 +#define IMX8DXL_SCU_GPIO0_01_SCU_UART0_TX IMX8DXL_SCU_GPIO0_01 1 +#define IMX8DXL_SCU_GPIO0_01_M40_UART0_TX IMX8DXL_SCU_GPIO0_01 2 +#define IMX8DXL_SCU_GPIO0_01_ADMA_UART3_TX IMX8DXL_SCU_GPIO0_01 3 +#define IMX8DXL_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT IMX8DXL_SCU_GPIO0_01 4 +#define IMX8DXL_SCU_PMIC_STANDBY_SCU_DSC_PMIC_STANDBY IMX8DXL_SCU_PMIC_STANDBY 0 +#define IMX8DXL_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 IMX8DXL_SCU_BOOT_MODE1 0 +#define IMX8DXL_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 IMX8DXL_SCU_BOOT_MODE0 0 +#define IMX8DXL_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 IMX8DXL_SCU_BOOT_MODE2 0 +#define IMX8DXL_SCU_BOOT_MODE2_SCU_DSC_RTC_CLOCK_OUTPUT_32K IMX8DXL_SCU_BOOT_MODE2 1 +#define IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN IMX8DXL_SNVS_TAMPER_OUT1 4 +#define IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO6_IO19_IN IMX8DXL_SNVS_TAMPER_OUT1 5 +#define IMX8DXL_SNVS_TAMPER_OUT2_LSIO_GPIO2_IO06_IN IMX8DXL_SNVS_TAMPER_OUT2 4 +#define IMX8DXL_SNVS_TAMPER_OUT2_LSIO_GPIO6_IO20_IN IMX8DXL_SNVS_TAMPER_OUT2 5 +#define IMX8DXL_SNVS_TAMPER_OUT3_ADMA_SAI2_RXC IMX8DXL_SNVS_TAMPER_OUT3 2 +#define IMX8DXL_SNVS_TAMPER_OUT3_LSIO_GPIO2_IO07_IN IMX8DXL_SNVS_TAMPER_OUT3 4 +#define IMX8DXL_SNVS_TAMPER_OUT3_LSIO_GPIO6_IO21_IN IMX8DXL_SNVS_TAMPER_OUT3 5 +#define IMX8DXL_SNVS_TAMPER_OUT4_ADMA_SAI2_RXD IMX8DXL_SNVS_TAMPER_OUT4 2 +#define IMX8DXL_SNVS_TAMPER_OUT4_LSIO_GPIO2_IO08_IN IMX8DXL_SNVS_TAMPER_OUT4 4 +#define IMX8DXL_SNVS_TAMPER_OUT4_LSIO_GPIO6_IO22_IN IMX8DXL_SNVS_TAMPER_OUT4 5 +#define IMX8DXL_SNVS_TAMPER_IN0_ADMA_SAI2_RXFS IMX8DXL_SNVS_TAMPER_IN0 2 +#define IMX8DXL_SNVS_TAMPER_IN0_LSIO_GPIO2_IO09_IN IMX8DXL_SNVS_TAMPER_IN0 4 +#define IMX8DXL_SNVS_TAMPER_IN0_LSIO_GPIO6_IO23_IN IMX8DXL_SNVS_TAMPER_IN0 5 +#define IMX8DXL_SNVS_TAMPER_IN1_ADMA_SAI3_RXC IMX8DXL_SNVS_TAMPER_IN1 2 +#define IMX8DXL_SNVS_TAMPER_IN1_LSIO_GPIO2_IO10_IN IMX8DXL_SNVS_TAMPER_IN1 4 +#define IMX8DXL_SNVS_TAMPER_IN1_LSIO_GPIO6_IO24_IN IMX8DXL_SNVS_TAMPER_IN1 5 +#define IMX8DXL_SNVS_TAMPER_IN2_ADMA_SAI3_RXD IMX8DXL_SNVS_TAMPER_IN2 2 +#define IMX8DXL_SNVS_TAMPER_IN2_LSIO_GPIO2_IO11_IN IMX8DXL_SNVS_TAMPER_IN2 4 +#define IMX8DXL_SNVS_TAMPER_IN2_LSIO_GPIO6_IO25_IN IMX8DXL_SNVS_TAMPER_IN2 5 +#define IMX8DXL_SNVS_TAMPER_IN3_ADMA_SAI3_RXFS IMX8DXL_SNVS_TAMPER_IN3 2 +#define IMX8DXL_SNVS_TAMPER_IN3_LSIO_GPIO2_IO12_IN IMX8DXL_SNVS_TAMPER_IN3 4 +#define IMX8DXL_SNVS_TAMPER_IN3_LSIO_GPIO6_IO26_IN IMX8DXL_SNVS_TAMPER_IN3 5 +#define IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA IMX8DXL_SPI1_SCK 2 +#define IMX8DXL_SPI1_SCK_ADMA_SPI1_SCK IMX8DXL_SPI1_SCK 3 +#define IMX8DXL_SPI1_SCK_LSIO_GPIO3_IO00 IMX8DXL_SPI1_SCK 4 +#define IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL IMX8DXL_SPI1_SDO 2 +#define IMX8DXL_SPI1_SDO_ADMA_SPI1_SDO IMX8DXL_SPI1_SDO 3 +#define IMX8DXL_SPI1_SDO_LSIO_GPIO3_IO01 IMX8DXL_SPI1_SDO 4 +#define IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL IMX8DXL_SPI1_SDI 2 +#define IMX8DXL_SPI1_SDI_ADMA_SPI1_SDI IMX8DXL_SPI1_SDI 3 +#define IMX8DXL_SPI1_SDI_LSIO_GPIO3_IO02 IMX8DXL_SPI1_SDI 4 +#define IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA IMX8DXL_SPI1_CS0 2 +#define IMX8DXL_SPI1_CS0_ADMA_SPI1_CS0 IMX8DXL_SPI1_CS0 3 +#define IMX8DXL_SPI1_CS0_LSIO_GPIO3_IO03 IMX8DXL_SPI1_CS0 4 +#define IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 IMX8DXL_QSPI0A_DATA1 0 +#define IMX8DXL_QSPI0A_DATA1_LSIO_GPIO3_IO10 IMX8DXL_QSPI0A_DATA1 4 +#define IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 IMX8DXL_QSPI0A_DATA0 0 +#define IMX8DXL_QSPI0A_DATA0_LSIO_GPIO3_IO09 IMX8DXL_QSPI0A_DATA0 4 +#define IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 IMX8DXL_QSPI0A_DATA3 0 +#define IMX8DXL_QSPI0A_DATA3_LSIO_GPIO3_IO12 IMX8DXL_QSPI0A_DATA3 4 +#define IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 IMX8DXL_QSPI0A_DATA2 0 +#define IMX8DXL_QSPI0A_DATA2_LSIO_GPIO3_IO11 IMX8DXL_QSPI0A_DATA2 4 +#define IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B IMX8DXL_QSPI0A_SS0_B 0 +#define IMX8DXL_QSPI0A_SS0_B_LSIO_GPIO3_IO14 IMX8DXL_QSPI0A_SS0_B 4 +#define IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS IMX8DXL_QSPI0A_DQS 0 +#define IMX8DXL_QSPI0A_DQS_LSIO_GPIO3_IO13 IMX8DXL_QSPI0A_DQS 4 +#define IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK IMX8DXL_QSPI0A_SCLK 0 +#define IMX8DXL_QSPI0A_SCLK_LSIO_GPIO3_IO16 IMX8DXL_QSPI0A_SCLK 4 +#define IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK IMX8DXL_QSPI0B_SCLK 0 +#define IMX8DXL_QSPI0B_SCLK_LSIO_GPIO3_IO17 IMX8DXL_QSPI0B_SCLK 4 +#define IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS IMX8DXL_QSPI0B_DQS 0 +#define IMX8DXL_QSPI0B_DQS_LSIO_GPIO3_IO22 IMX8DXL_QSPI0B_DQS 4 +#define IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 IMX8DXL_QSPI0B_DATA1 0 +#define IMX8DXL_QSPI0B_DATA1_LSIO_GPIO3_IO19 IMX8DXL_QSPI0B_DATA1 4 +#define IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 IMX8DXL_QSPI0B_DATA0 0 +#define IMX8DXL_QSPI0B_DATA0_LSIO_GPIO3_IO18 IMX8DXL_QSPI0B_DATA0 4 +#define IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 IMX8DXL_QSPI0B_DATA3 0 +#define IMX8DXL_QSPI0B_DATA3_LSIO_GPIO3_IO21 IMX8DXL_QSPI0B_DATA3 4 +#define IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 IMX8DXL_QSPI0B_DATA2 0 +#define IMX8DXL_QSPI0B_DATA2_LSIO_GPIO3_IO20 IMX8DXL_QSPI0B_DATA2 4 +#define IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B IMX8DXL_QSPI0B_SS0_B 0 +#define IMX8DXL_QSPI0B_SS0_B_LSIO_GPIO3_IO23 IMX8DXL_QSPI0B_SS0_B 4 +#define IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0A_SS1_B IMX8DXL_QSPI0B_SS0_B 5 + +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_PCIESEP_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_PCIESEP 0 +#define IMX8DXL_COMP_CTL_GPIO_3V3_USB3IO_PAD IMX8DXL_COMP_CTL_GPIO_3V3_USB3IO 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_VSELSEP_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_VSELSEP 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHT_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHT 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOLH_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOLH 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHD_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHD 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0A_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0A 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0B_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0B 0 + +#endif diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 193cc9dbf448..e3e9f0e3a878 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -100,10 +100,12 @@ union coresight_dev_subtype { }; /** - * struct coresight_platform_data - data harvested from the DT specification - * @nr_inport: number of input ports for this component. - * @nr_outport: number of output ports for this component. - * @conns: Array of nr_outport connections from this component + * struct coresight_platform_data - data harvested from the firmware + * specification. + * + * @nr_inport: Number of elements for the input connections. + * @nr_outport: Number of elements for the output connections. + * @conns: Sparse array of nr_outport connections from this component. */ struct coresight_platform_data { int nr_inport; @@ -140,12 +142,28 @@ struct coresight_desc { * @chid_fwnode: remote component's fwnode handle. * @child_dev: a @coresight_device representation of the component connected to @outport. + * @link: Representation of the connection as a sysfs link. */ struct coresight_connection { int outport; int child_port; struct fwnode_handle *child_fwnode; struct coresight_device *child_dev; + struct coresight_sysfs_link *link; +}; + +/** + * struct coresight_sysfs_link - representation of a connection in sysfs. + * @orig: Originating (master) coresight device for the link. + * @orig_name: Name to use for the link orig->target. + * @target: Target (slave) coresight device for the link. + * @target_name: Name to use for the link target->orig. + */ +struct coresight_sysfs_link { + struct coresight_device *orig; + const char *orig_name; + struct coresight_device *target; + const char *target_name; }; /** @@ -165,6 +183,9 @@ struct coresight_connection { * @ea: Device attribute for sink representation under PMU directory. * @ect_dev: Associated cross trigger device. Not part of the trace data * path or connections. + * @nr_links: number of sysfs links created to other components from this + * device. These will appear in the "connections" group. + * @has_conns_grp: Have added a "connections" group for sysfs links. */ struct coresight_device { struct coresight_platform_data *pdata; @@ -180,6 +201,9 @@ struct coresight_device { struct dev_ext_attribute *ea; /* cross trigger handling */ struct coresight_device *ect_dev; + /* sysfs links between components */ + int nr_links; + bool has_conns_grp; }; /* diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index 24b3a77810b6..8377afef8806 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -142,6 +142,7 @@ enum cpuhp_state { CPUHP_AP_ARM_XEN_STARTING, CPUHP_AP_ARM_KVMPV_STARTING, CPUHP_AP_ARM_CORESIGHT_STARTING, + CPUHP_AP_ARM_CORESIGHT_CTI_STARTING, CPUHP_AP_ARM64_ISNDEP_STARTING, CPUHP_AP_SMPCFD_DYING, CPUHP_AP_X86_TBOOT_DYING, diff --git a/include/linux/firmware.h b/include/linux/firmware.h index 4bbd0afd91b7..cb3e2c06ed8a 100644 --- a/include/linux/firmware.h +++ b/include/linux/firmware.h @@ -12,7 +12,6 @@ struct firmware { size_t size; const u8 *data; - struct page **pages; /* firmware loader private fields */ void *priv; diff --git a/include/linux/firmware/intel/stratix10-smc.h b/include/linux/firmware/intel/stratix10-smc.h index 013ae4819deb..682dbf694007 100644 --- a/include/linux/firmware/intel/stratix10-smc.h +++ b/include/linux/firmware/intel/stratix10-smc.h @@ -54,32 +54,25 @@ * Secure monitor software doesn't recognize the request. * * INTEL_SIP_SMC_STATUS_OK: - * FPGA configuration completed successfully, - * In case of FPGA configuration write operation, it means secure monitor - * software can accept the next chunk of FPGA configuration data. + * Secure monitor software accepts the service client's request. * - * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY: - * In case of FPGA configuration write operation, it means secure monitor - * software is still processing previous data & can't accept the next chunk - * of data. Service driver needs to issue - * INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE call to query the - * completed block(s). + * INTEL_SIP_SMC_STATUS_BUSY: + * Secure monitor software is still processing service client's request. * - * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR: - * There is error during the FPGA configuration process. + * INTEL_SIP_SMC_STATUS_REJECTED: + * Secure monitor software reject the service client's request. * - * INTEL_SIP_SMC_REG_ERROR: - * There is error during a read or write operation of the protected registers. + * INTEL_SIP_SMC_STATUS_ERROR: + * There is error during the process of service request. * * INTEL_SIP_SMC_RSU_ERROR: - * There is error during a remote status update. + * There is error during the process of remote status update request. */ #define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION 0xFFFFFFFF #define INTEL_SIP_SMC_STATUS_OK 0x0 -#define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY 0x1 -#define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_REJECTED 0x2 -#define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR 0x4 -#define INTEL_SIP_SMC_REG_ERROR 0x5 +#define INTEL_SIP_SMC_STATUS_BUSY 0x1 +#define INTEL_SIP_SMC_STATUS_REJECTED 0x2 +#define INTEL_SIP_SMC_STATUS_ERROR 0x4 #define INTEL_SIP_SMC_RSU_ERROR 0x7 /** @@ -95,7 +88,7 @@ * a2-7: not used. * * Return status: - * a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR. + * a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_STATUS_ERROR. * a1-3: not used. */ #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START 1 @@ -115,8 +108,8 @@ * a3-7: not used. * * Return status: - * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY or - * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR. + * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY or + * INTEL_SIP_SMC_STATUS_ERROR. * a1: 64bit physical address of 1st completed memory block if any completed * block, otherwise zero value. * a2: 64bit physical address of 2nd completed memory block if any completed @@ -133,15 +126,15 @@ * * Sync call used by service driver at EL1 to track the completed write * transactions. This request is called after INTEL_SIP_SMC_FPGA_CONFIG_WRITE - * call returns INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY. + * call returns INTEL_SIP_SMC_STATUS_BUSY. * * Call register usage: * a0: INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE. * a1-7: not used. * * Return status: - * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY or - * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR. + * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FPGA_BUSY or + * INTEL_SIP_SMC_STATUS_ERROR. * a1: 64bit physical address of 1st completed memory block. * a2: 64bit physical address of 2nd completed memory block if * any completed block, otherwise zero value. @@ -164,8 +157,8 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE) * a1-7: not used. * * Return status: - * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY or - * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR. + * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY or + * INTEL_SIP_SMC_STATUS_ERROR. * a1-3: not used. */ #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE 4 @@ -183,7 +176,7 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE) * a1-7: not used. * * Return status: - * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR. + * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR. * a1: start of physical address of reserved memory block. * a2: size of reserved memory block. * a3: not used. @@ -203,7 +196,7 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE) * a1-7: not used. * * Return status: - * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR. + * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR. * a1-3: not used. */ #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK 6 diff --git a/include/linux/firmware/intel/stratix10-svc-client.h b/include/linux/firmware/intel/stratix10-svc-client.h index 59bc6e2af693..64213c3e82f5 100644 --- a/include/linux/firmware/intel/stratix10-svc-client.h +++ b/include/linux/firmware/intel/stratix10-svc-client.h @@ -18,45 +18,37 @@ /** * Status of the sent command, in bit number * - * SVC_COMMAND_STATUS_RECONFIG_REQUEST_OK: - * Secure firmware accepts the request of FPGA reconfiguration. + * SVC_STATUS_OK: + * Secure firmware accepts the request issued by one of service clients. * - * SVC_STATUS_RECONFIG_BUFFER_SUBMITTED: - * Service client successfully submits FPGA configuration - * data buffer to secure firmware. + * SVC_STATUS_BUFFER_SUBMITTED: + * Service client successfully submits data buffer to secure firmware. * - * SVC_COMMAND_STATUS_RECONFIG_BUFFER_DONE: + * SVC_STATUS_BUFFER_DONE: * Secure firmware completes data process, ready to accept the * next WRITE transaction. * - * SVC_COMMAND_STATUS_RECONFIG_COMPLETED: - * Secure firmware completes FPGA configuration successfully, FPGA should - * be in user mode. + * SVC_STATUS_COMPLETED: + * Secure firmware completes service request successfully. In case of + * FPGA configuration, FPGA should be in user mode. * - * SVC_COMMAND_STATUS_RECONFIG_BUSY: - * FPGA configuration is still in process. + * SVC_COMMAND_STATUS_BUSY: + * Service request is still in process. * - * SVC_COMMAND_STATUS_RECONFIG_ERROR: - * Error encountered during FPGA configuration. + * SVC_COMMAND_STATUS_ERROR: + * Error encountered during the process of the service request. * - * SVC_STATUS_RSU_OK: - * Secure firmware accepts the request of remote status update (RSU). - * - * SVC_STATUS_RSU_ERROR: - * Error encountered during remote system update. - * - * SVC_STATUS_RSU_NO_SUPPORT: - * Secure firmware doesn't support RSU retry or notify feature. + * SVC_STATUS_NO_SUPPORT: + * Secure firmware doesn't support requested features such as RSU retry + * or RSU notify. */ -#define SVC_STATUS_RECONFIG_REQUEST_OK 0 -#define SVC_STATUS_RECONFIG_BUFFER_SUBMITTED 1 -#define SVC_STATUS_RECONFIG_BUFFER_DONE 2 -#define SVC_STATUS_RECONFIG_COMPLETED 3 -#define SVC_STATUS_RECONFIG_BUSY 4 -#define SVC_STATUS_RECONFIG_ERROR 5 -#define SVC_STATUS_RSU_OK 6 -#define SVC_STATUS_RSU_ERROR 7 -#define SVC_STATUS_RSU_NO_SUPPORT 8 +#define SVC_STATUS_OK 0 +#define SVC_STATUS_BUFFER_SUBMITTED 1 +#define SVC_STATUS_BUFFER_DONE 2 +#define SVC_STATUS_COMPLETED 3 +#define SVC_STATUS_BUSY 4 +#define SVC_STATUS_ERROR 5 +#define SVC_STATUS_NO_SUPPORT 6 /** * Flag bit for COMMAND_RECONFIG @@ -84,32 +76,29 @@ struct stratix10_svc_chan; * @COMMAND_NOOP: do 'dummy' request for integration/debug/trouble-shooting * * @COMMAND_RECONFIG: ask for FPGA configuration preparation, return status - * is SVC_STATUS_RECONFIG_REQUEST_OK + * is SVC_STATUS_OK * * @COMMAND_RECONFIG_DATA_SUBMIT: submit buffer(s) of bit-stream data for the - * FPGA configuration, return status is SVC_STATUS_RECONFIG_BUFFER_SUBMITTED, - * or SVC_STATUS_RECONFIG_ERROR + * FPGA configuration, return status is SVC_STATUS_SUBMITTED or SVC_STATUS_ERROR * * @COMMAND_RECONFIG_DATA_CLAIM: check the status of the configuration, return - * status is SVC_STATUS_RECONFIG_COMPLETED, or SVC_STATUS_RECONFIG_BUSY, or - * SVC_STATUS_RECONFIG_ERROR + * status is SVC_STATUS_COMPLETED, or SVC_STATUS_BUSY, or SVC_STATUS_ERROR * * @COMMAND_RECONFIG_STATUS: check the status of the configuration, return - * status is SVC_STATUS_RECONFIG_COMPLETED, or SVC_STATUS_RECONFIG_BUSY, or - * SVC_STATUS_RECONFIG_ERROR + * status is SVC_STATUS_COMPLETED, or SVC_STATUS_BUSY, or SVC_STATUS_ERROR * * @COMMAND_RSU_STATUS: request remote system update boot log, return status * is log data or SVC_STATUS_RSU_ERROR * * @COMMAND_RSU_UPDATE: set the offset of the bitstream to boot after reboot, - * return status is SVC_STATUS_RSU_OK or SVC_STATUS_RSU_ERROR + * return status is SVC_STATUS_OK or SVC_STATUS_ERROR * * @COMMAND_RSU_NOTIFY: report the status of hard processor system - * software to firmware, return status is SVC_STATUS_RSU_OK or - * SVC_STATUS_RSU_ERROR + * software to firmware, return status is SVC_STATUS_OK or + * SVC_STATUS_ERROR * * @COMMAND_RSU_RETRY: query firmware for the current image's retry counter, - * return status is SVC_STATUS_RSU_OK or SVC_STATUS_RSU_ERROR + * return status is SVC_STATUS_OK or SVC_STATUS_ERROR */ enum stratix10_svc_command_code { COMMAND_NOOP = 0, diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 8efa5ac22d7e..5968df82b991 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -42,6 +42,8 @@ #define ZYNQMP_PM_MAX_QOS 100U +#define GSS_NUM_REGS (4) + /* Node capabilities */ #define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U #define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U @@ -62,6 +64,7 @@ enum pm_api_id { PM_GET_API_VERSION = 1, + PM_SYSTEM_SHUTDOWN = 12, PM_REQUEST_NODE = 13, PM_RELEASE_NODE, PM_SET_REQUIREMENT, @@ -107,6 +110,12 @@ enum pm_ioctl_id { IOCTL_GET_PLL_FRAC_MODE, IOCTL_SET_PLL_FRAC_DATA, IOCTL_GET_PLL_FRAC_DATA, + IOCTL_WRITE_GGS = 12, + IOCTL_READ_GGS = 13, + IOCTL_WRITE_PGGS = 14, + IOCTL_READ_PGGS = 15, + /* Set healthy bit value */ + IOCTL_SET_BOOT_HEALTH_STATUS = 17, }; enum pm_query_id { @@ -279,6 +288,18 @@ enum dll_reset_type { PM_DLL_RESET_PULSE, }; +enum zynqmp_pm_shutdown_type { + ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN, + ZYNQMP_PM_SHUTDOWN_TYPE_RESET, + ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY, +}; + +enum zynqmp_pm_shutdown_subtype { + ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM, + ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY, + ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM, +}; + /** * struct zynqmp_pm_query_data - PM query data * @qid: query ID @@ -293,49 +314,199 @@ struct zynqmp_pm_query_data { u32 arg3; }; -struct zynqmp_eemi_ops { - int (*get_api_version)(u32 *version); - int (*get_chipid)(u32 *idcode, u32 *version); - int (*fpga_load)(const u64 address, const u32 size, const u32 flags); - int (*fpga_get_status)(u32 *value); - int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out); - int (*clock_enable)(u32 clock_id); - int (*clock_disable)(u32 clock_id); - int (*clock_getstate)(u32 clock_id, u32 *state); - int (*clock_setdivider)(u32 clock_id, u32 divider); - int (*clock_getdivider)(u32 clock_id, u32 *divider); - int (*clock_setrate)(u32 clock_id, u64 rate); - int (*clock_getrate)(u32 clock_id, u64 *rate); - int (*clock_setparent)(u32 clock_id, u32 parent_id); - int (*clock_getparent)(u32 clock_id, u32 *parent_id); - int (*ioctl)(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, u32 *out); - int (*reset_assert)(const enum zynqmp_pm_reset reset, - const enum zynqmp_pm_reset_action assert_flag); - int (*reset_get_status)(const enum zynqmp_pm_reset reset, u32 *status); - int (*init_finalize)(void); - int (*set_suspend_mode)(u32 mode); - int (*request_node)(const u32 node, - const u32 capabilities, - const u32 qos, - const enum zynqmp_pm_request_ack ack); - int (*release_node)(const u32 node); - int (*set_requirement)(const u32 node, - const u32 capabilities, - const u32 qos, - const enum zynqmp_pm_request_ack ack); - int (*aes)(const u64 address, u32 *out); -}; int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 *ret_payload); #if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE) -const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void); +int zynqmp_pm_get_api_version(u32 *version); +int zynqmp_pm_get_chipid(u32 *idcode, u32 *version); +int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out); +int zynqmp_pm_clock_enable(u32 clock_id); +int zynqmp_pm_clock_disable(u32 clock_id); +int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state); +int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider); +int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider); +int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate); +int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate); +int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id); +int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id); +int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode); +int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode); +int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data); +int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data); +int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value); +int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type); +int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset, + const enum zynqmp_pm_reset_action assert_flag); +int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status); +int zynqmp_pm_init_finalize(void); +int zynqmp_pm_set_suspend_mode(u32 mode); +int zynqmp_pm_request_node(const u32 node, const u32 capabilities, + const u32 qos, const enum zynqmp_pm_request_ack ack); +int zynqmp_pm_release_node(const u32 node); +int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, + const u32 qos, + const enum zynqmp_pm_request_ack ack); +int zynqmp_pm_aes_engine(const u64 address, u32 *out); +int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags); +int zynqmp_pm_fpga_get_status(u32 *value); +int zynqmp_pm_write_ggs(u32 index, u32 value); +int zynqmp_pm_read_ggs(u32 index, u32 *value); +int zynqmp_pm_write_pggs(u32 index, u32 value); +int zynqmp_pm_read_pggs(u32 index, u32 *value); +int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype); +int zynqmp_pm_set_boot_health_status(u32 value); #else static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void) { return ERR_PTR(-ENODEV); } +static inline int zynqmp_pm_get_api_version(u32 *version) +{ + return -ENODEV; +} +static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version) +{ + return -ENODEV; +} +static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, + u32 *out) +{ + return -ENODEV; +} +static inline int zynqmp_pm_clock_enable(u32 clock_id) +{ + return -ENODEV; +} +static inline int zynqmp_pm_clock_disable(u32 clock_id) +{ + return -ENODEV; +} +static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state) +{ + return -ENODEV; +} +static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider) +{ + return -ENODEV; +} +static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider) +{ + return -ENODEV; +} +static inline int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate) +{ + return -ENODEV; +} +static inline int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate) +{ + return -ENODEV; +} +static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id) +{ + return -ENODEV; +} +static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id) +{ + return -ENODEV; +} +static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode) +{ + return -ENODEV; +} +static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode) +{ + return -ENODEV; +} +static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data) +{ + return -ENODEV; +} +static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data) +{ + return -ENODEV; +} +static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value) +{ + return -ENODEV; +} +static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type) +{ + return -ENODEV; +} +static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset, + const enum zynqmp_pm_reset_action assert_flag) +{ + return -ENODEV; +} +static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, + u32 *status) +{ + return -ENODEV; +} +static inline int zynqmp_pm_init_finalize(void) +{ + return -ENODEV; +} +static inline int zynqmp_pm_set_suspend_mode(u32 mode) +{ + return -ENODEV; +} +static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities, + const u32 qos, + const enum zynqmp_pm_request_ack ack) +{ + return -ENODEV; +} +static inline int zynqmp_pm_release_node(const u32 node) +{ + return -ENODEV; +} +static inline int zynqmp_pm_set_requirement(const u32 node, + const u32 capabilities, + const u32 qos, + const enum zynqmp_pm_request_ack ack) +{ + return -ENODEV; +} +static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out) +{ + return -ENODEV; +} +static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size, + const u32 flags) +{ + return -ENODEV; +} +static inline int zynqmp_pm_fpga_get_status(u32 *value) +{ + return -ENODEV; +} +static inline int zynqmp_pm_write_ggs(u32 index, u32 value) +{ + return -ENODEV; +} +static inline int zynqmp_pm_read_ggs(u32 index, u32 *value) +{ + return -ENODEV; +} +static inline int zynqmp_pm_write_pggs(u32 index, u32 value) +{ + return -ENODEV; +} +static inline int zynqmp_pm_read_pggs(u32 index, u32 *value) +{ + return -ENODEV; +} +static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype) +{ + return -ENODEV; +} +static inline int zynqmp_pm_set_boot_health_status(u32 value) +{ + return -ENODEV; +} #endif #endif /* __FIRMWARE_ZYNQMP_H__ */ diff --git a/include/linux/fpga/adi-axi-common.h b/include/linux/fpga/adi-axi-common.h index 7fc95d5c95bb..141ac3f251e6 100644 --- a/include/linux/fpga/adi-axi-common.h +++ b/include/linux/fpga/adi-axi-common.h @@ -11,9 +11,13 @@ #ifndef ADI_AXI_COMMON_H_ #define ADI_AXI_COMMON_H_ -#define ADI_AXI_REG_VERSION 0x0000 +#define ADI_AXI_REG_VERSION 0x0000 #define ADI_AXI_PCORE_VER(major, minor, patch) \ (((major) << 16) | ((minor) << 8) | (patch)) +#define ADI_AXI_PCORE_VER_MAJOR(version) (((version) >> 16) & 0xff) +#define ADI_AXI_PCORE_VER_MINOR(version) (((version) >> 8) & 0xff) +#define ADI_AXI_PCORE_VER_PATCH(version) ((version) & 0xff) + #endif /* ADI_AXI_COMMON_H_ */ diff --git a/include/linux/fwnode.h b/include/linux/fwnode.h index e0abafbb17f8..9506f8ec0974 100644 --- a/include/linux/fwnode.h +++ b/include/linux/fwnode.h @@ -171,5 +171,7 @@ struct fwnode_operations { #define get_dev_from_fwnode(fwnode) get_device((fwnode)->dev) extern u32 fw_devlink_get_flags(void); +void fw_devlink_pause(void); +void fw_devlink_resume(void); #endif diff --git a/include/linux/greybus/greybus_protocols.h b/include/linux/greybus/greybus_protocols.h index dfbc6c39a74b..aeb8f9243545 100644 --- a/include/linux/greybus/greybus_protocols.h +++ b/include/linux/greybus/greybus_protocols.h @@ -345,7 +345,7 @@ struct gb_cap_get_ims_certificate_request { struct gb_cap_get_ims_certificate_response { __u8 result_code; - __u8 certificate[0]; + __u8 certificate[]; } __packed; /* CAP authenticate request/response */ @@ -358,7 +358,7 @@ struct gb_cap_authenticate_request { struct gb_cap_authenticate_response { __u8 result_code; __u8 response[64]; - __u8 signature[0]; + __u8 signature[]; } __packed; @@ -642,7 +642,7 @@ struct gb_hid_get_report_request { struct gb_hid_set_report_request { __u8 report_type; __u8 report_id; - __u8 report[0]; + __u8 report[]; } __packed; /* HID input report request, via interrupt pipe */ @@ -680,7 +680,7 @@ struct gb_i2c_transfer_op { struct gb_i2c_transfer_request { __le16 op_count; - struct gb_i2c_transfer_op ops[0]; /* op_count of these */ + struct gb_i2c_transfer_op ops[]; /* op_count of these */ } __packed; struct gb_i2c_transfer_response { __u8 data[0]; /* inbound data */ @@ -908,7 +908,7 @@ struct gb_spi_transfer_request { __u8 chip_select; /* of the spi device */ __u8 mode; /* of the spi device */ __le16 count; - struct gb_spi_transfer transfers[0]; /* count of these */ + struct gb_spi_transfer transfers[]; /* count of these */ } __packed; struct gb_spi_transfer_response { @@ -1188,7 +1188,7 @@ struct gb_svc_pwrmon_rail_count_get_response { struct gb_svc_pwrmon_rail_names_get_response { __u8 status; - __u8 name[0][GB_SVC_PWRMON_RAIL_NAME_BUFSIZE]; + __u8 name[][GB_SVC_PWRMON_RAIL_NAME_BUFSIZE]; } __packed; #define GB_SVC_PWRMON_TYPE_CURR 0x01 @@ -1281,7 +1281,7 @@ struct gb_svc_intf_oops_request { struct gb_raw_send_request { __le32 len; - __u8 data[0]; + __u8 data[]; } __packed; @@ -1300,7 +1300,7 @@ struct gb_raw_send_request { /* Represents data from AP -> Module */ struct gb_uart_send_data_request { __le16 size; - __u8 data[0]; + __u8 data[]; } __packed; /* recv-data-request flags */ @@ -1313,7 +1313,7 @@ struct gb_uart_send_data_request { struct gb_uart_recv_data_request { __le16 size; __u8 flags; - __u8 data[0]; + __u8 data[]; } __packed; struct gb_uart_receive_credits_request { @@ -1382,14 +1382,14 @@ struct gb_loopback_transfer_request { __le32 len; __le32 reserved0; __le32 reserved1; - __u8 data[0]; + __u8 data[]; } __packed; struct gb_loopback_transfer_response { __le32 len; __le32 reserved0; __le32 reserved1; - __u8 data[0]; + __u8 data[]; } __packed; /* SDIO */ @@ -1530,13 +1530,13 @@ struct gb_sdio_transfer_request { __le16 data_blocks; __le16 data_blksz; - __u8 data[0]; + __u8 data[]; } __packed; struct gb_sdio_transfer_response { __le16 data_blocks; __le16 data_blksz; - __u8 data[0]; + __u8 data[]; } __packed; /* event request: generated by module and is defined as unidirectional */ @@ -1572,7 +1572,7 @@ struct gb_camera_configure_streams_request { __u8 flags; #define GB_CAMERA_CONFIGURE_STREAMS_TEST_ONLY 0x01 __le16 padding; - struct gb_camera_stream_config_request config[0]; + struct gb_camera_stream_config_request config[]; } __packed; /* Greybus Camera Configure Streams response payload */ @@ -1593,7 +1593,7 @@ struct gb_camera_configure_streams_response { __u8 flags; __u8 padding[2]; __le32 data_rate; - struct gb_camera_stream_config_response config[0]; + struct gb_camera_stream_config_response config[]; }; /* Greybus Camera Capture request payload - response has no payload */ @@ -1602,7 +1602,7 @@ struct gb_camera_capture_request { __u8 streams; __u8 padding; __le16 num_frames; - __u8 settings[0]; + __u8 settings[]; } __packed; /* Greybus Camera Flush response payload - request has no payload */ @@ -1616,7 +1616,7 @@ struct gb_camera_metadata_request { __le16 frame_number; __u8 stream; __u8 padding; - __u8 metadata[0]; + __u8 metadata[]; } __packed; /* Lights */ @@ -1993,7 +1993,7 @@ struct gb_audio_integer64 { struct gb_audio_enumerated { __le32 items; __le16 names_length; - __u8 names[0]; + __u8 names[]; } __packed; struct gb_audio_ctl_elem_info { /* See snd_ctl_elem_info in Linux source */ @@ -2033,7 +2033,7 @@ struct gb_audio_widget { __u8 type; /* GB_AUDIO_WIDGET_TYPE_* */ __u8 state; /* GB_AUDIO_WIDGET_STATE_* */ __u8 ncontrols; - struct gb_audio_control ctl[0]; /* 'ncontrols' entries */ + struct gb_audio_control ctl[]; /* 'ncontrols' entries */ } __packed; struct gb_audio_route { @@ -2059,7 +2059,7 @@ struct gb_audio_topology { * struct gb_audio_widget widgets[num_widgets]; * struct gb_audio_route routes[num_routes]; */ - __u8 data[0]; + __u8 data[]; } __packed; struct gb_audio_get_topology_size_response { @@ -2157,7 +2157,7 @@ struct gb_audio_streaming_event_request { struct gb_audio_send_data_request { __le64 timestamp; - __u8 data[0]; + __u8 data[]; } __packed; @@ -2171,7 +2171,7 @@ struct gb_audio_send_data_request { struct gb_log_send_log_request { __le16 len; - __u8 msg[0]; + __u8 msg[]; } __packed; #endif /* __GREYBUS_PROTOCOLS_H */ diff --git a/include/linux/iio/adc/ad_sigma_delta.h b/include/linux/iio/adc/ad_sigma_delta.h index 5a127c0ed200..a3a838dcf8e4 100644 --- a/include/linux/iio/adc/ad_sigma_delta.h +++ b/include/linux/iio/adc/ad_sigma_delta.h @@ -133,62 +133,4 @@ void ad_sd_cleanup_buffer_and_trigger(struct iio_dev *indio_dev); int ad_sd_validate_trigger(struct iio_dev *indio_dev, struct iio_trigger *trig); -#define __AD_SD_CHANNEL(_si, _channel1, _channel2, _address, _bits, \ - _storagebits, _shift, _extend_name, _type, _mask_all) \ - { \ - .type = (_type), \ - .differential = (_channel2 == -1 ? 0 : 1), \ - .indexed = 1, \ - .channel = (_channel1), \ - .channel2 = (_channel2), \ - .address = (_address), \ - .extend_name = (_extend_name), \ - .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ - BIT(IIO_CHAN_INFO_OFFSET), \ - .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ - .info_mask_shared_by_all = _mask_all, \ - .scan_index = (_si), \ - .scan_type = { \ - .sign = 'u', \ - .realbits = (_bits), \ - .storagebits = (_storagebits), \ - .shift = (_shift), \ - .endianness = IIO_BE, \ - }, \ - } - -#define AD_SD_DIFF_CHANNEL(_si, _channel1, _channel2, _address, _bits, \ - _storagebits, _shift) \ - __AD_SD_CHANNEL(_si, _channel1, _channel2, _address, _bits, \ - _storagebits, _shift, NULL, IIO_VOLTAGE, \ - BIT(IIO_CHAN_INFO_SAMP_FREQ)) - -#define AD_SD_SHORTED_CHANNEL(_si, _channel, _address, _bits, \ - _storagebits, _shift) \ - __AD_SD_CHANNEL(_si, _channel, _channel, _address, _bits, \ - _storagebits, _shift, "shorted", IIO_VOLTAGE, \ - BIT(IIO_CHAN_INFO_SAMP_FREQ)) - -#define AD_SD_CHANNEL(_si, _channel, _address, _bits, \ - _storagebits, _shift) \ - __AD_SD_CHANNEL(_si, _channel, -1, _address, _bits, \ - _storagebits, _shift, NULL, IIO_VOLTAGE, \ - BIT(IIO_CHAN_INFO_SAMP_FREQ)) - -#define AD_SD_CHANNEL_NO_SAMP_FREQ(_si, _channel, _address, _bits, \ - _storagebits, _shift) \ - __AD_SD_CHANNEL(_si, _channel, -1, _address, _bits, \ - _storagebits, _shift, NULL, IIO_VOLTAGE, 0) - -#define AD_SD_TEMP_CHANNEL(_si, _address, _bits, _storagebits, _shift) \ - __AD_SD_CHANNEL(_si, 0, -1, _address, _bits, \ - _storagebits, _shift, NULL, IIO_TEMP, \ - BIT(IIO_CHAN_INFO_SAMP_FREQ)) - -#define AD_SD_SUPPLY_CHANNEL(_si, _channel, _address, _bits, _storagebits, \ - _shift) \ - __AD_SD_CHANNEL(_si, _channel, -1, _address, _bits, \ - _storagebits, _shift, "supply", IIO_VOLTAGE, \ - BIT(IIO_CHAN_INFO_SAMP_FREQ)) - #endif diff --git a/include/linux/iio/adc/adi-axi-adc.h b/include/linux/iio/adc/adi-axi-adc.h new file mode 100644 index 000000000000..c5d48e1c2d36 --- /dev/null +++ b/include/linux/iio/adc/adi-axi-adc.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Analog Devices Generic AXI ADC IP core driver/library + * Link: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip + * + * Copyright 2012-2020 Analog Devices Inc. + */ +#ifndef __ADI_AXI_ADC_H__ +#define __ADI_AXI_ADC_H__ + +struct device; +struct iio_chan_spec; + +/** + * struct adi_axi_adc_chip_info - Chip specific information + * @name Chip name + * @id Chip ID (usually product ID) + * @channels Channel specifications of type @struct axi_adc_chan_spec + * @num_channels Number of @channels + * @scale_table Supported scales by the chip; tuples of 2 ints + * @num_scales Number of scales in the table + * @max_rate Maximum sampling rate supported by the device + */ +struct adi_axi_adc_chip_info { + const char *name; + unsigned int id; + + const struct iio_chan_spec *channels; + unsigned int num_channels; + + const unsigned int (*scale_table)[2]; + int num_scales; + + unsigned long max_rate; +}; + +/** + * struct adi_axi_adc_conv - data of the ADC attached to the AXI ADC + * @chip_info chip info details for the client ADC + * @preenable_setup op to run in the client before enabling the AXI ADC + * @reg_access IIO debugfs_reg_access hook for the client ADC + * @read_raw IIO read_raw hook for the client ADC + * @write_raw IIO write_raw hook for the client ADC + */ +struct adi_axi_adc_conv { + const struct adi_axi_adc_chip_info *chip_info; + + int (*preenable_setup)(struct adi_axi_adc_conv *conv); + int (*reg_access)(struct adi_axi_adc_conv *conv, unsigned int reg, + unsigned int writeval, unsigned int *readval); + int (*read_raw)(struct adi_axi_adc_conv *conv, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask); + int (*write_raw)(struct adi_axi_adc_conv *conv, + struct iio_chan_spec const *chan, + int val, int val2, long mask); +}; + +struct adi_axi_adc_conv *devm_adi_axi_adc_conv_register(struct device *dev, + size_t sizeof_priv); + +void *adi_axi_adc_conv_priv(struct adi_axi_adc_conv *conv); + +#endif diff --git a/include/linux/iio/buffer-dma.h b/include/linux/iio/buffer-dma.h index 016d8a068353..ff15c61bf319 100644 --- a/include/linux/iio/buffer-dma.h +++ b/include/linux/iio/buffer-dma.h @@ -11,7 +11,7 @@ #include #include #include -#include +#include struct iio_dma_buffer_queue; struct iio_dma_buffer_ops; diff --git a/include/linux/iio/buffer-dmaengine.h b/include/linux/iio/buffer-dmaengine.h index b3a57444a886..0e503db71289 100644 --- a/include/linux/iio/buffer-dmaengine.h +++ b/include/linux/iio/buffer-dmaengine.h @@ -14,4 +14,7 @@ struct iio_buffer *iio_dmaengine_buffer_alloc(struct device *dev, const char *channel); void iio_dmaengine_buffer_free(struct iio_buffer *buffer); +struct iio_buffer *devm_iio_dmaengine_buffer_alloc(struct device *dev, + const char *channel); + #endif diff --git a/include/linux/iio/buffer_impl.h b/include/linux/iio/buffer_impl.h index a4d2d8061ef6..a63dc07b7350 100644 --- a/include/linux/iio/buffer_impl.h +++ b/include/linux/iio/buffer_impl.h @@ -94,12 +94,6 @@ struct iio_buffer { unsigned int watermark; /* private: */ - /* - * @scan_el_attrs: Control of scan elements if that scan mode - * control method is used. - */ - struct attribute_group *scan_el_attrs; - /* @scan_timestamp: Does the scan mode include a timestamp. */ bool scan_timestamp; @@ -115,9 +109,6 @@ struct iio_buffer { */ struct attribute_group scan_el_group; - /* @stufftoread: Flag to indicate new data. */ - bool stufftoread; - /* @attrs: Standard attributes of the buffer. */ const struct attribute **attrs; diff --git a/include/linux/iio/consumer.h b/include/linux/iio/consumer.h index 2bde8c912d4d..c4118dcb8e05 100644 --- a/include/linux/iio/consumer.h +++ b/include/linux/iio/consumer.h @@ -63,15 +63,6 @@ void iio_channel_release(struct iio_channel *chan); */ struct iio_channel *devm_iio_channel_get(struct device *dev, const char *consumer_channel); -/** - * devm_iio_channel_release() - Resource managed version of - * iio_channel_release(). - * @dev: Pointer to consumer device for which resource - * is allocared. - * @chan: The channel to be released. - */ -void devm_iio_channel_release(struct device *dev, struct iio_channel *chan); - /** * iio_channel_get_all() - get all channels associated with a client * @dev: Pointer to consumer device. @@ -106,15 +97,6 @@ void iio_channel_release_all(struct iio_channel *chan); */ struct iio_channel *devm_iio_channel_get_all(struct device *dev); -/** - * devm_iio_channel_release_all() - Resource managed version of - * iio_channel_release_all(). - * @dev: Pointer to consumer device for which resource - * is allocared. - * @chan: Array channel to be released. - */ -void devm_iio_channel_release_all(struct device *dev, struct iio_channel *chan); - struct iio_cb_buffer; /** * iio_channel_get_all_cb() - register callback for triggered capture diff --git a/include/linux/iio/hw-consumer.h b/include/linux/iio/hw-consumer.h index 44d48bb1d39f..e8255c2e33bc 100644 --- a/include/linux/iio/hw-consumer.h +++ b/include/linux/iio/hw-consumer.h @@ -14,7 +14,6 @@ struct iio_hw_consumer; struct iio_hw_consumer *iio_hw_consumer_alloc(struct device *dev); void iio_hw_consumer_free(struct iio_hw_consumer *hwc); struct iio_hw_consumer *devm_iio_hw_consumer_alloc(struct device *dev); -void devm_iio_hw_consumer_free(struct device *dev, struct iio_hw_consumer *hwc); int iio_hw_consumer_enable(struct iio_hw_consumer *hwc); void iio_hw_consumer_disable(struct iio_hw_consumer *hwc); diff --git a/include/linux/iio/iio.h b/include/linux/iio/iio.h index 25c87507a1fa..a1be82e74c93 100644 --- a/include/linux/iio/iio.h +++ b/include/linux/iio/iio.h @@ -492,7 +492,7 @@ struct iio_buffer_setup_ops { * @buffer: [DRIVER] any buffer present * @buffer_list: [INTERN] list of all buffers currently attached * @scan_bytes: [INTERN] num bytes captured to be fed to buffer demux - * @mlock: [DRIVER] lock used to prevent simultaneous device state + * @mlock: [INTERN] lock used to prevent simultaneous device state * changes * @available_scan_masks: [DRIVER] optional array of allowed bitmasks * @masklength: [INTERN] the length of the mask established from @@ -593,9 +593,6 @@ void iio_device_unregister(struct iio_dev *indio_dev); * calls iio_device_register() internally. Refer to that function for more * information. * - * If an iio_dev registered with this function needs to be unregistered - * separately, devm_iio_device_unregister() must be used. - * * RETURNS: * 0 on success, negative error number on failure. */ @@ -603,7 +600,6 @@ void iio_device_unregister(struct iio_dev *indio_dev); __devm_iio_device_register((dev), (indio_dev), THIS_MODULE) int __devm_iio_device_register(struct device *dev, struct iio_dev *indio_dev, struct module *this_mod); -void devm_iio_device_unregister(struct device *dev, struct iio_dev *indio_dev); int iio_push_event(struct iio_dev *indio_dev, u64 ev_code, s64 timestamp); int iio_device_claim_direct_mode(struct iio_dev *indio_dev); void iio_device_release_direct_mode(struct iio_dev *indio_dev); @@ -694,13 +690,9 @@ static inline struct iio_dev *iio_priv_to_dev(void *priv) } void iio_device_free(struct iio_dev *indio_dev); -int devm_iio_device_match(struct device *dev, void *res, void *data); struct iio_dev *devm_iio_device_alloc(struct device *dev, int sizeof_priv); -void devm_iio_device_free(struct device *dev, struct iio_dev *indio_dev); struct iio_trigger *devm_iio_trigger_alloc(struct device *dev, const char *fmt, ...); -void devm_iio_trigger_free(struct device *dev, struct iio_trigger *iio_trig); - /** * iio_buffer_enabled() - helper function to test if the buffer is enabled * @indio_dev: IIO device structure for device diff --git a/include/linux/iio/imu/adis.h b/include/linux/iio/imu/adis.h index dd8219138c2e..2df67448f0d1 100644 --- a/include/linux/iio/imu/adis.h +++ b/include/linux/iio/imu/adis.h @@ -83,10 +83,13 @@ struct adis_data { * @trig: IIO trigger object data * @data: ADIS chip variant specific data * @burst: ADIS burst transfer information + * @burst_extra_len: Burst extra length. Should only be used by devices that can + * dynamically change their burst mode length. * @state_lock: Lock used by the device to protect state * @msg: SPI message object * @xfer: SPI transfer objects to be used for a @msg * @current_page: Some ADIS devices have registers, this selects current page + * @irq_flag: IRQ handling flags as passed to request_irq() * @buffer: Data buffer for information read from the device * @tx: DMA safe TX buffer for SPI transfers * @rx: DMA safe RX buffer for SPI transfers @@ -97,7 +100,7 @@ struct adis { const struct adis_data *data; struct adis_burst *burst; - + unsigned int burst_extra_len; /** * The state_lock is meant to be used during operations that require * a sequence of SPI R/W in order to protect the SPI transfer @@ -113,6 +116,7 @@ struct adis { struct spi_message msg; struct spi_transfer *xfer; unsigned int current_page; + unsigned long irq_flag; void *buffer; uint8_t tx[10] ____cacheline_aligned; @@ -331,6 +335,65 @@ static inline int adis_read_reg_32(struct adis *adis, unsigned int reg, return ret; } +int __adis_update_bits_base(struct adis *adis, unsigned int reg, const u32 mask, + const u32 val, u8 size); +/** + * adis_update_bits_base() - ADIS Update bits function - Locked version + * @adis: The adis device + * @reg: The address of the lower of the two registers + * @mask: Bitmask to change + * @val: Value to be written + * @size: Size of the register to update + * + * Updates the desired bits of @reg in accordance with @mask and @val. + */ +static inline int adis_update_bits_base(struct adis *adis, unsigned int reg, + const u32 mask, const u32 val, u8 size) +{ + int ret; + + mutex_lock(&adis->state_lock); + ret = __adis_update_bits_base(adis, reg, mask, val, size); + mutex_unlock(&adis->state_lock); + return ret; +} + +/** + * adis_update_bits() - Wrapper macro for adis_update_bits_base - Locked version + * @adis: The adis device + * @reg: The address of the lower of the two registers + * @mask: Bitmask to change + * @val: Value to be written + * + * This macro evaluates the sizeof of @val at compile time and calls + * adis_update_bits_base() accordingly. Be aware that using MACROS/DEFINES for + * @val can lead to undesired behavior if the register to update is 16bit. + */ +#define adis_update_bits(adis, reg, mask, val) ({ \ + BUILD_BUG_ON(sizeof(val) == 1 || sizeof(val) == 8); \ + __builtin_choose_expr(sizeof(val) == 4, \ + adis_update_bits_base(adis, reg, mask, val, 4), \ + adis_update_bits_base(adis, reg, mask, val, 2)); \ +}) + +/** + * adis_update_bits() - Wrapper macro for adis_update_bits_base + * @adis: The adis device + * @reg: The address of the lower of the two registers + * @mask: Bitmask to change + * @val: Value to be written + * + * This macro evaluates the sizeof of @val at compile time and calls + * adis_update_bits_base() accordingly. Be aware that using MACROS/DEFINES for + * @val can lead to undesired behavior if the register to update is 16bit. + */ +#define __adis_update_bits(adis, reg, mask, val) ({ \ + BUILD_BUG_ON(sizeof(val) == 1 || sizeof(val) == 8); \ + __builtin_choose_expr(sizeof(val) == 4, \ + __adis_update_bits_base(adis, reg, mask, val, 4), \ + __adis_update_bits_base(adis, reg, mask, val, 2)); \ +}) + int adis_enable_irq(struct adis *adis, bool enable); int __adis_check_status(struct adis *adis); int __adis_initial_startup(struct adis *adis); @@ -441,18 +504,25 @@ int adis_single_conversion(struct iio_dev *indio_dev, * @en burst mode enabled * @reg_cmd register command that triggers burst * @extra_len extra length to account in the SPI RX buffer + * @burst_max_len holds the maximum burst size when the device supports + * more than one burst mode with different sizes */ struct adis_burst { bool en; unsigned int reg_cmd; - unsigned int extra_len; + const u32 extra_len; + const u32 burst_max_len; }; +int +devm_adis_setup_buffer_and_trigger(struct adis *adis, struct iio_dev *indio_dev, + irq_handler_t trigger_handler); int adis_setup_buffer_and_trigger(struct adis *adis, struct iio_dev *indio_dev, irqreturn_t (*trigger_handler)(int, void *)); void adis_cleanup_buffer_and_trigger(struct adis *adis, struct iio_dev *indio_dev); +int devm_adis_probe_trigger(struct adis *adis, struct iio_dev *indio_dev); int adis_probe_trigger(struct adis *adis, struct iio_dev *indio_dev); void adis_remove_trigger(struct adis *adis); @@ -461,6 +531,13 @@ int adis_update_scan_mode(struct iio_dev *indio_dev, #else /* CONFIG_IIO_BUFFER */ +static inline int +devm_adis_setup_buffer_and_trigger(struct adis *adis, struct iio_dev *indio_dev, + irq_handler_t trigger_handler) +{ + return 0; +} + static inline int adis_setup_buffer_and_trigger(struct adis *adis, struct iio_dev *indio_dev, irqreturn_t (*trigger_handler)(int, void *)) { @@ -472,6 +549,12 @@ static inline void adis_cleanup_buffer_and_trigger(struct adis *adis, { } +static inline int devm_adis_probe_trigger(struct adis *adis, + struct iio_dev *indio_dev) +{ + return 0; +} + static inline int adis_probe_trigger(struct adis *adis, struct iio_dev *indio_dev) { diff --git a/include/linux/iio/kfifo_buf.h b/include/linux/iio/kfifo_buf.h index 764659e01b68..1fc1efa7799d 100644 --- a/include/linux/iio/kfifo_buf.h +++ b/include/linux/iio/kfifo_buf.h @@ -9,6 +9,5 @@ struct iio_buffer *iio_kfifo_allocate(void); void iio_kfifo_free(struct iio_buffer *r); struct iio_buffer *devm_iio_kfifo_allocate(struct device *dev); -void devm_iio_kfifo_free(struct device *dev, struct iio_buffer *r); #endif diff --git a/include/linux/iio/trigger.h b/include/linux/iio/trigger.h index 84995e2967ac..cad8325903f9 100644 --- a/include/linux/iio/trigger.h +++ b/include/linux/iio/trigger.h @@ -141,9 +141,6 @@ int __devm_iio_trigger_register(struct device *dev, **/ void iio_trigger_unregister(struct iio_trigger *trig_info); -void devm_iio_trigger_unregister(struct device *dev, - struct iio_trigger *trig_info); - /** * iio_trigger_set_immutable() - set an immutable trigger on destination * diff --git a/include/linux/iio/triggered_buffer.h b/include/linux/iio/triggered_buffer.h index 238ad30ce166..e99c91799359 100644 --- a/include/linux/iio/triggered_buffer.h +++ b/include/linux/iio/triggered_buffer.h @@ -18,7 +18,5 @@ int devm_iio_triggered_buffer_setup(struct device *dev, irqreturn_t (*h)(int irq, void *p), irqreturn_t (*thread)(int irq, void *p), const struct iio_buffer_setup_ops *ops); -void devm_iio_triggered_buffer_cleanup(struct device *dev, - struct iio_dev *indio_dev); #endif diff --git a/include/linux/interconnect.h b/include/linux/interconnect.h index d70a914cba11..d8c29049f066 100644 --- a/include/linux/interconnect.h +++ b/include/linux/interconnect.h @@ -28,7 +28,11 @@ struct device; struct icc_path *icc_get(struct device *dev, const int src_id, const int dst_id); struct icc_path *of_icc_get(struct device *dev, const char *name); +struct icc_path *devm_of_icc_get(struct device *dev, const char *name); +struct icc_path *of_icc_get_by_index(struct device *dev, int idx); void icc_put(struct icc_path *path); +int icc_enable(struct icc_path *path); +int icc_disable(struct icc_path *path); int icc_set_bw(struct icc_path *path, u32 avg_bw, u32 peak_bw); void icc_set_tag(struct icc_path *path, u32 tag); @@ -46,10 +50,31 @@ static inline struct icc_path *of_icc_get(struct device *dev, return NULL; } +static inline struct icc_path *devm_of_icc_get(struct device *dev, + const char *name) +{ + return NULL; +} + +static inline struct icc_path *of_icc_get_by_index(struct device *dev, int idx) +{ + return NULL; +} + static inline void icc_put(struct icc_path *path) { } +static inline int icc_enable(struct icc_path *path) +{ + return 0; +} + +static inline int icc_disable(struct icc_path *path) +{ + return 0; +} + static inline int icc_set_bw(struct icc_path *path, u32 avg_bw, u32 peak_bw) { return 0; diff --git a/include/linux/ioport.h b/include/linux/ioport.h index cc9a5b4593ca..6c2b06fe8beb 100644 --- a/include/linux/ioport.h +++ b/include/linux/ioport.h @@ -302,5 +302,11 @@ struct resource *devm_request_free_mem_region(struct device *dev, struct resource *request_free_mem_region(struct resource *base, unsigned long size, const char *name); +#ifdef CONFIG_IO_STRICT_DEVMEM +void revoke_devmem(struct resource *res); +#else +static inline void revoke_devmem(struct resource *res) { }; +#endif + #endif /* __ASSEMBLY__ */ #endif /* _LINUX_IOPORT_H */ diff --git a/include/linux/mhi.h b/include/linux/mhi.h index 3d7c3c26eeb9..c4a940d98912 100644 --- a/include/linux/mhi.h +++ b/include/linux/mhi.h @@ -331,8 +331,6 @@ struct mhi_controller_config { * @wlock: Lock for protecting device wakeup * @mhi_link_info: Device bandwidth info * @st_worker: State transition worker - * @fw_worker: Firmware download worker - * @syserr_worker: System error worker * @state_event: State change event * @status_cb: CB function to notify power states of the device (required) * @wake_get: CB function to assert device wake (optional) @@ -412,8 +410,6 @@ struct mhi_controller { spinlock_t wlock; struct mhi_link_info mhi_link_info; struct work_struct st_worker; - struct work_struct fw_worker; - struct work_struct syserr_worker; wait_queue_head_t state_event; void (*status_cb)(struct mhi_controller *mhi_cntrl, @@ -572,6 +568,13 @@ void mhi_driver_unregister(struct mhi_driver *mhi_drv); void mhi_set_mhi_state(struct mhi_controller *mhi_cntrl, enum mhi_state state); +/** + * mhi_notify - Notify the MHI client driver about client device status + * @mhi_dev: MHI device instance + * @cb_reason: MHI callback reason + */ +void mhi_notify(struct mhi_device *mhi_dev, enum mhi_callback cb_reason); + /** * mhi_prepare_for_power_up - Do pre-initialization before power up. * This is optional, call this before power up if @@ -608,6 +611,18 @@ void mhi_power_down(struct mhi_controller *mhi_cntrl, bool graceful); */ void mhi_unprepare_after_power_down(struct mhi_controller *mhi_cntrl); +/** + * mhi_pm_suspend - Move MHI into a suspended state + * @mhi_cntrl: MHI controller + */ +int mhi_pm_suspend(struct mhi_controller *mhi_cntrl); + +/** + * mhi_pm_resume - Resume MHI from suspended state + * @mhi_cntrl: MHI controller + */ +int mhi_pm_resume(struct mhi_controller *mhi_cntrl); + /** * mhi_download_rddm_img - Download ramdump image from device for * debugging purpose. diff --git a/include/linux/ntb.h b/include/linux/ntb.h index 8c13538aeffe..191b524e5c0d 100644 --- a/include/linux/ntb.h +++ b/include/linux/ntb.h @@ -478,7 +478,7 @@ void ntb_unregister_client(struct ntb_client *client); int ntb_register_device(struct ntb_dev *ntb); /** - * ntb_register_device() - unregister a ntb device + * ntb_unregister_device() - unregister a ntb device * @ntb: NTB device context. * * The device will be removed from the list of ntb devices. If the ntb device @@ -1351,7 +1351,7 @@ static inline int ntb_spad_write(struct ntb_dev *ntb, int sidx, u32 val) * @sidx: Scratchpad index. * @spad_addr: OUT - The address of the peer scratchpad register. * - * Return the address of the peer doorbell register. This may be used, for + * Return the address of the peer scratchpad register. This may be used, for * example, by drivers that offload memory copy operations to a dma engine. * * Return: Zero on success, otherwise an error number. @@ -1373,7 +1373,7 @@ static inline int ntb_peer_spad_addr(struct ntb_dev *ntb, int pidx, int sidx, * * Read the peer scratchpad register, and return the value. * - * Return: The value of the local scratchpad register. + * Return: The value of the peer scratchpad register. */ static inline u32 ntb_peer_spad_read(struct ntb_dev *ntb, int pidx, int sidx) { diff --git a/include/linux/parport.h b/include/linux/parport.h index 13932ce8b37b..1fb508c19e83 100644 --- a/include/linux/parport.h +++ b/include/linux/parport.h @@ -325,18 +325,10 @@ struct pardev_cb { unsigned int flags; }; -/* parport_register_device declares that a device is connected to a - port, and tells the kernel all it needs to know. - - pf is the preemption function (may be NULL for no callback) - - kf is the wake-up function (may be NULL for no callback) - - irq_func is the interrupt handler (may be NULL for no interrupts) - - handle is a user pointer that gets handed to callback functions. */ -struct pardevice *parport_register_device(struct parport *port, - const char *name, - int (*pf)(void *), void (*kf)(void *), - void (*irq_func)(void *), - int flags, void *handle); - +/* + * parport_register_dev_model declares that a device is connected to a + * port, and tells the kernel all it needs to know. + */ struct pardevice * parport_register_dev_model(struct parport *port, const char *name, const struct pardev_cb *par_dev_cb, int cnt); diff --git a/include/linux/property.h b/include/linux/property.h index c7b5f3db36aa..10d03572f52e 100644 --- a/include/linux/property.h +++ b/include/linux/property.h @@ -444,6 +444,7 @@ int software_node_register_node_group(const struct software_node **node_group); void software_node_unregister_node_group(const struct software_node **node_group); int software_node_register(const struct software_node *node); +void software_node_unregister(const struct software_node *node); int software_node_notify(struct device *dev, unsigned long action); diff --git a/include/linux/rtsx_pci.h b/include/linux/rtsx_pci.h index 65b8142a7fed..e8780d4e4636 100644 --- a/include/linux/rtsx_pci.h +++ b/include/linux/rtsx_pci.h @@ -1080,11 +1080,7 @@ struct pcr_ops { void (*stop_cmd)(struct rtsx_pcr *pcr); void (*set_aspm)(struct rtsx_pcr *pcr, bool enable); - int (*set_ltr_latency)(struct rtsx_pcr *pcr, u32 latency); - int (*set_l1off_sub)(struct rtsx_pcr *pcr, u8 val); void (*set_l1off_cfg_sub_d0)(struct rtsx_pcr *pcr, int active); - void (*full_on)(struct rtsx_pcr *pcr); - void (*power_saving)(struct rtsx_pcr *pcr); void (*enable_ocp)(struct rtsx_pcr *pcr); void (*disable_ocp)(struct rtsx_pcr *pcr); void (*init_ocp)(struct rtsx_pcr *pcr); @@ -1108,13 +1104,6 @@ enum PDEV_STAT {PDEV_STAT_IDLE, PDEV_STAT_RUN}; #define L1_SNOOZE_TEST_EN BIT(5) #define LTR_L1SS_PWR_GATE_CHECK_CARD_EN BIT(6) -enum dev_aspm_mode { - DEV_ASPM_DYNAMIC, - DEV_ASPM_BACKDOOR, - DEV_ASPM_STATIC, - DEV_ASPM_DISABLE, -}; - /* * struct rtsx_cr_option - card reader option * @dev_flags: device flags @@ -1125,7 +1114,6 @@ enum dev_aspm_mode { * @ltr_active_latency: ltr mode active latency * @ltr_idle_latency: ltr mode idle latency * @ltr_l1off_latency: ltr mode l1off latency - * @dev_aspm_mode: device aspm mode * @l1_snooze_delay: l1 snooze delay * @ltr_l1off_sspwrgate: ltr l1off sspwrgate * @ltr_l1off_snooze_sspwrgate: ltr l1off snooze sspwrgate @@ -1142,7 +1130,6 @@ struct rtsx_cr_option { u32 ltr_active_latency; u32 ltr_idle_latency; u32 ltr_l1off_latency; - enum dev_aspm_mode dev_aspm_mode; u32 l1_snooze_delay; u8 ltr_l1off_sspwrgate; u8 ltr_l1off_snooze_sspwrgate; @@ -1320,18 +1307,6 @@ static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr) return (u8 *)(pcr->host_cmds_ptr); } -static inline int rtsx_pci_update_cfg_byte(struct rtsx_pcr *pcr, int addr, - u8 mask, u8 append) -{ - int err; - u8 val; - - err = pci_read_config_byte(pcr->pci, addr, &val); - if (err < 0) - return err; - return pci_write_config_byte(pcr->pci, addr, (val & mask) | append); -} - static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val) { rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg, 0xFF, val >> 24); diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h index 92f5eba86052..9fd550e7946a 100644 --- a/include/linux/serial_core.h +++ b/include/linux/serial_core.h @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -251,6 +252,7 @@ struct uart_port { struct attribute_group *attr_group; /* port specific attributes */ const struct attribute_group **tty_groups; /* all attributes (serial core use only) */ struct serial_rs485 rs485; + struct gpio_desc *rs485_term_gpio; /* enable RS485 bus termination */ struct serial_iso7816 iso7816; void *private_data; /* generic platform data pointer */ }; @@ -472,5 +474,5 @@ extern int uart_handle_break(struct uart_port *port); (cflag) & CRTSCTS || \ !((cflag) & CLOCAL)) -void uart_get_rs485_mode(struct device *dev, struct serial_rs485 *rs485conf); +int uart_get_rs485_mode(struct uart_port *port); #endif /* LINUX_SERIAL_CORE_H */ diff --git a/include/linux/soundwire/sdw.h b/include/linux/soundwire/sdw.h index 00f5826092e3..9c27a32df9bb 100644 --- a/include/linux/soundwire/sdw.h +++ b/include/linux/soundwire/sdw.h @@ -291,8 +291,8 @@ struct sdw_dpn_audio_mode { * implementation-defined interrupts * @max_ch: Maximum channels supported * @min_ch: Minimum channels supported - * @num_ch: Number of discrete channels supported - * @ch: Discrete channels supported + * @num_channels: Number of discrete channels supported + * @channels: Discrete channels supported * @num_ch_combinations: Number of channel combinations supported * @ch_combinations: Channel combinations supported * @modes: SDW mode supported @@ -316,8 +316,8 @@ struct sdw_dpn_prop { u32 imp_def_interrupts; u32 max_ch; u32 min_ch; - u32 num_ch; - u32 *ch; + u32 num_channels; + u32 *channels; u32 num_ch_combinations; u32 *ch_combinations; u32 modes; @@ -632,6 +632,19 @@ struct sdw_slave { #define dev_to_sdw_dev(_dev) container_of(_dev, struct sdw_slave, dev) +/** + * struct sdw_master_device - SoundWire 'Master Device' representation + * @dev: Linux device for this Master + * @bus: Bus handle shortcut + */ +struct sdw_master_device { + struct device dev; + struct sdw_bus *bus; +}; + +#define dev_to_sdw_master_device(d) \ + container_of(d, struct sdw_master_device, dev) + struct sdw_driver { const char *name; @@ -787,8 +800,10 @@ struct sdw_master_ops { /** * struct sdw_bus - SoundWire bus - * @dev: Master linux device + * @dev: Shortcut to &bus->md->dev to avoid changing the entire code. + * @md: Master device * @link_id: Link id number, can be 0 to N, unique for each Master + * @id: bus system-wide unique id * @slaves: list of Slaves on this bus * @assigned: Bitmap for Slave device numbers. * Bit set implies used number, bit clear implies unused number. @@ -812,7 +827,9 @@ struct sdw_master_ops { */ struct sdw_bus { struct device *dev; + struct sdw_master_device *md; unsigned int link_id; + int id; struct list_head slaves; DECLARE_BITMAP(assigned, SDW_MAX_DEVICES); struct mutex bus_lock; @@ -832,8 +849,9 @@ struct sdw_bus { bool multi_link; }; -int sdw_add_bus_master(struct sdw_bus *bus); -void sdw_delete_bus_master(struct sdw_bus *bus); +int sdw_bus_master_add(struct sdw_bus *bus, struct device *parent, + struct fwnode_handle *fwnode); +void sdw_bus_master_delete(struct sdw_bus *bus); /** * sdw_port_config: Master or Slave Port configuration diff --git a/include/linux/soundwire/sdw_type.h b/include/linux/soundwire/sdw_type.h index aaa7f4267c14..52eb66cd11bc 100644 --- a/include/linux/soundwire/sdw_type.h +++ b/include/linux/soundwire/sdw_type.h @@ -5,6 +5,13 @@ #define __SOUNDWIRE_TYPES_H extern struct bus_type sdw_bus_type; +extern struct device_type sdw_slave_type; +extern struct device_type sdw_master_type; + +static inline int is_sdw_slave(const struct device *dev) +{ + return dev->type == &sdw_slave_type; +} #define drv_to_sdw_driver(_drv) container_of(_drv, struct sdw_driver, driver) @@ -14,7 +21,7 @@ extern struct bus_type sdw_bus_type; int __sdw_register_driver(struct sdw_driver *drv, struct module *owner); void sdw_unregister_driver(struct sdw_driver *drv); -int sdw_slave_modalias(const struct sdw_slave *slave, char *buf, size_t size); +int sdw_slave_uevent(struct device *dev, struct kobj_uevent_env *env); /** * module_sdw_driver() - Helper macro for registering a Soundwire driver diff --git a/include/linux/spi/mcp23s08.h b/include/linux/spi/mcp23s08.h deleted file mode 100644 index 738a45b435f2..000000000000 --- a/include/linux/spi/mcp23s08.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -struct mcp23s08_platform_data { - /* For mcp23s08, up to 4 slaves (numbered 0..3) can share one SPI - * chipselect, each providing 1 gpio_chip instance with 8 gpios. - * For mpc23s17, up to 8 slaves (numbered 0..7) can share one SPI - * chipselect, each providing 1 gpio_chip (port A + port B) with - * 16 gpios. - */ - u32 spi_present_mask; - - /* "base" is the number of the first GPIO or -1 for dynamic - * assignment. If there are gaps in chip addressing the GPIO - * numbers are sequential .. so for example if only slaves 0 - * and 3 are present, their GPIOs range from base to base+15 - * (or base+31 for s17 variant). - */ - unsigned base; -}; diff --git a/include/linux/sysrq.h b/include/linux/sysrq.h index 8e159e16850f..3a582ec7a2f1 100644 --- a/include/linux/sysrq.h +++ b/include/linux/sysrq.h @@ -30,10 +30,10 @@ #define SYSRQ_ENABLE_RTNICE 0x0100 struct sysrq_key_op { - void (*handler)(int); - char *help_msg; - char *action_msg; - int enable_mask; + void (* const handler)(int); + const char * const help_msg; + const char * const action_msg; + const int enable_mask; }; #ifdef CONFIG_MAGIC_SYSRQ @@ -45,9 +45,9 @@ struct sysrq_key_op { void handle_sysrq(int key); void __handle_sysrq(int key, bool check_mask); -int register_sysrq_key(int key, struct sysrq_key_op *op); -int unregister_sysrq_key(int key, struct sysrq_key_op *op); -struct sysrq_key_op *__sysrq_get_key_op(int key); +int register_sysrq_key(int key, const struct sysrq_key_op *op); +int unregister_sysrq_key(int key, const struct sysrq_key_op *op); +extern const struct sysrq_key_op *__sysrq_reboot_op; int sysrq_toggle_support(int enable_mask); int sysrq_mask(void); @@ -62,12 +62,12 @@ static inline void __handle_sysrq(int key, bool check_mask) { } -static inline int register_sysrq_key(int key, struct sysrq_key_op *op) +static inline int register_sysrq_key(int key, const struct sysrq_key_op *op) { return -EINVAL; } -static inline int unregister_sysrq_key(int key, struct sysrq_key_op *op) +static inline int unregister_sysrq_key(int key, const struct sysrq_key_op *op) { return -EINVAL; } diff --git a/include/uapi/linux/magic.h b/include/uapi/linux/magic.h index d78064007b17..f3956fc11de6 100644 --- a/include/uapi/linux/magic.h +++ b/include/uapi/linux/magic.h @@ -94,6 +94,7 @@ #define BALLOON_KVM_MAGIC 0x13661366 #define ZSMALLOC_MAGIC 0x58295829 #define DMA_BUF_MAGIC 0x444d4142 /* "DMAB" */ +#define DEVMEM_MAGIC 0x454d444d /* "DMEM" */ #define Z3FOLD_MAGIC 0x33 #define PPC_CMM_MAGIC 0xc7571590 diff --git a/include/uapi/linux/rtc.h b/include/uapi/linux/rtc.h index 83bba58d47f4..fa9aff91cbf2 100644 --- a/include/uapi/linux/rtc.h +++ b/include/uapi/linux/rtc.h @@ -99,6 +99,7 @@ struct rtc_pll_info { #define RTC_VL_BACKUP_LOW _BITUL(1) /* Backup voltage is low */ #define RTC_VL_BACKUP_EMPTY _BITUL(2) /* Backup empty or not present */ #define RTC_VL_ACCURACY_LOW _BITUL(3) /* Voltage is low, RTC accuracy is reduced */ +#define RTC_VL_BACKUP_SWITCH _BITUL(4) /* Backup switchover happened */ #define RTC_VL_READ _IOR('p', 0x13, unsigned int) /* Voltage low detection */ #define RTC_VL_CLR _IO('p', 0x14) /* Clear voltage low information */ diff --git a/include/uapi/misc/habanalabs.h b/include/uapi/misc/habanalabs.h index 4faa2c9767e5..f6267a8d7416 100644 --- a/include/uapi/misc/habanalabs.h +++ b/include/uapi/misc/habanalabs.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note * - * Copyright 2016-2019 HabanaLabs, Ltd. + * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ @@ -15,10 +15,13 @@ * Defines that are asic-specific but constitutes as ABI between kernel driver * and userspace */ -#define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0x8000 /* 32KB */ +#define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0x8000 /* 32KB */ +#define GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START 0x80 /* 128 bytes */ +#define GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT 48 +#define GAUDI_FIRST_AVAILABLE_W_S_MONITOR 24 /* - * Queue Numbering + * Goya queue Numbering * * The external queues (PCI DMA channels) MUST be before the internal queues * and each group (PCI DMA channels and internal) must be contiguous inside @@ -45,6 +48,129 @@ enum goya_queue_id { GOYA_QUEUE_ID_SIZE }; +/* + * Gaudi queue Numbering + * External queues (PCI DMA channels) are DMA_0_*, DMA_1_* and DMA_5_*. + * Except one CPU queue, all the rest are internal queues. + */ + +enum gaudi_queue_id { + GAUDI_QUEUE_ID_DMA_0_0 = 0, /* external */ + GAUDI_QUEUE_ID_DMA_0_1 = 1, /* external */ + GAUDI_QUEUE_ID_DMA_0_2 = 2, /* external */ + GAUDI_QUEUE_ID_DMA_0_3 = 3, /* external */ + GAUDI_QUEUE_ID_DMA_1_0 = 4, /* external */ + GAUDI_QUEUE_ID_DMA_1_1 = 5, /* external */ + GAUDI_QUEUE_ID_DMA_1_2 = 6, /* external */ + GAUDI_QUEUE_ID_DMA_1_3 = 7, /* external */ + GAUDI_QUEUE_ID_CPU_PQ = 8, /* CPU */ + GAUDI_QUEUE_ID_DMA_2_0 = 9, /* internal */ + GAUDI_QUEUE_ID_DMA_2_1 = 10, /* internal */ + GAUDI_QUEUE_ID_DMA_2_2 = 11, /* internal */ + GAUDI_QUEUE_ID_DMA_2_3 = 12, /* internal */ + GAUDI_QUEUE_ID_DMA_3_0 = 13, /* internal */ + GAUDI_QUEUE_ID_DMA_3_1 = 14, /* internal */ + GAUDI_QUEUE_ID_DMA_3_2 = 15, /* internal */ + GAUDI_QUEUE_ID_DMA_3_3 = 16, /* internal */ + GAUDI_QUEUE_ID_DMA_4_0 = 17, /* internal */ + GAUDI_QUEUE_ID_DMA_4_1 = 18, /* internal */ + GAUDI_QUEUE_ID_DMA_4_2 = 19, /* internal */ + GAUDI_QUEUE_ID_DMA_4_3 = 20, /* internal */ + GAUDI_QUEUE_ID_DMA_5_0 = 21, /* external */ + GAUDI_QUEUE_ID_DMA_5_1 = 22, /* external */ + GAUDI_QUEUE_ID_DMA_5_2 = 23, /* external */ + GAUDI_QUEUE_ID_DMA_5_3 = 24, /* external */ + GAUDI_QUEUE_ID_DMA_6_0 = 25, /* internal */ + GAUDI_QUEUE_ID_DMA_6_1 = 26, /* internal */ + GAUDI_QUEUE_ID_DMA_6_2 = 27, /* internal */ + GAUDI_QUEUE_ID_DMA_6_3 = 28, /* internal */ + GAUDI_QUEUE_ID_DMA_7_0 = 29, /* internal */ + GAUDI_QUEUE_ID_DMA_7_1 = 30, /* internal */ + GAUDI_QUEUE_ID_DMA_7_2 = 31, /* internal */ + GAUDI_QUEUE_ID_DMA_7_3 = 32, /* internal */ + GAUDI_QUEUE_ID_MME_0_0 = 33, /* internal */ + GAUDI_QUEUE_ID_MME_0_1 = 34, /* internal */ + GAUDI_QUEUE_ID_MME_0_2 = 35, /* internal */ + GAUDI_QUEUE_ID_MME_0_3 = 36, /* internal */ + GAUDI_QUEUE_ID_MME_1_0 = 37, /* internal */ + GAUDI_QUEUE_ID_MME_1_1 = 38, /* internal */ + GAUDI_QUEUE_ID_MME_1_2 = 39, /* internal */ + GAUDI_QUEUE_ID_MME_1_3 = 40, /* internal */ + GAUDI_QUEUE_ID_TPC_0_0 = 41, /* internal */ + GAUDI_QUEUE_ID_TPC_0_1 = 42, /* internal */ + GAUDI_QUEUE_ID_TPC_0_2 = 43, /* internal */ + GAUDI_QUEUE_ID_TPC_0_3 = 44, /* internal */ + GAUDI_QUEUE_ID_TPC_1_0 = 45, /* internal */ + GAUDI_QUEUE_ID_TPC_1_1 = 46, /* internal */ + GAUDI_QUEUE_ID_TPC_1_2 = 47, /* internal */ + GAUDI_QUEUE_ID_TPC_1_3 = 48, /* internal */ + GAUDI_QUEUE_ID_TPC_2_0 = 49, /* internal */ + GAUDI_QUEUE_ID_TPC_2_1 = 50, /* internal */ + GAUDI_QUEUE_ID_TPC_2_2 = 51, /* internal */ + GAUDI_QUEUE_ID_TPC_2_3 = 52, /* internal */ + GAUDI_QUEUE_ID_TPC_3_0 = 53, /* internal */ + GAUDI_QUEUE_ID_TPC_3_1 = 54, /* internal */ + GAUDI_QUEUE_ID_TPC_3_2 = 55, /* internal */ + GAUDI_QUEUE_ID_TPC_3_3 = 56, /* internal */ + GAUDI_QUEUE_ID_TPC_4_0 = 57, /* internal */ + GAUDI_QUEUE_ID_TPC_4_1 = 58, /* internal */ + GAUDI_QUEUE_ID_TPC_4_2 = 59, /* internal */ + GAUDI_QUEUE_ID_TPC_4_3 = 60, /* internal */ + GAUDI_QUEUE_ID_TPC_5_0 = 61, /* internal */ + GAUDI_QUEUE_ID_TPC_5_1 = 62, /* internal */ + GAUDI_QUEUE_ID_TPC_5_2 = 63, /* internal */ + GAUDI_QUEUE_ID_TPC_5_3 = 64, /* internal */ + GAUDI_QUEUE_ID_TPC_6_0 = 65, /* internal */ + GAUDI_QUEUE_ID_TPC_6_1 = 66, /* internal */ + GAUDI_QUEUE_ID_TPC_6_2 = 67, /* internal */ + GAUDI_QUEUE_ID_TPC_6_3 = 68, /* internal */ + GAUDI_QUEUE_ID_TPC_7_0 = 69, /* internal */ + GAUDI_QUEUE_ID_TPC_7_1 = 70, /* internal */ + GAUDI_QUEUE_ID_TPC_7_2 = 71, /* internal */ + GAUDI_QUEUE_ID_TPC_7_3 = 72, /* internal */ + GAUDI_QUEUE_ID_NIC_0_0 = 73, /* internal */ + GAUDI_QUEUE_ID_NIC_0_1 = 74, /* internal */ + GAUDI_QUEUE_ID_NIC_0_2 = 75, /* internal */ + GAUDI_QUEUE_ID_NIC_0_3 = 76, /* internal */ + GAUDI_QUEUE_ID_NIC_1_0 = 77, /* internal */ + GAUDI_QUEUE_ID_NIC_1_1 = 78, /* internal */ + GAUDI_QUEUE_ID_NIC_1_2 = 79, /* internal */ + GAUDI_QUEUE_ID_NIC_1_3 = 80, /* internal */ + GAUDI_QUEUE_ID_NIC_2_0 = 81, /* internal */ + GAUDI_QUEUE_ID_NIC_2_1 = 82, /* internal */ + GAUDI_QUEUE_ID_NIC_2_2 = 83, /* internal */ + GAUDI_QUEUE_ID_NIC_2_3 = 84, /* internal */ + GAUDI_QUEUE_ID_NIC_3_0 = 85, /* internal */ + GAUDI_QUEUE_ID_NIC_3_1 = 86, /* internal */ + GAUDI_QUEUE_ID_NIC_3_2 = 87, /* internal */ + GAUDI_QUEUE_ID_NIC_3_3 = 88, /* internal */ + GAUDI_QUEUE_ID_NIC_4_0 = 89, /* internal */ + GAUDI_QUEUE_ID_NIC_4_1 = 90, /* internal */ + GAUDI_QUEUE_ID_NIC_4_2 = 91, /* internal */ + GAUDI_QUEUE_ID_NIC_4_3 = 92, /* internal */ + GAUDI_QUEUE_ID_NIC_5_0 = 93, /* internal */ + GAUDI_QUEUE_ID_NIC_5_1 = 94, /* internal */ + GAUDI_QUEUE_ID_NIC_5_2 = 95, /* internal */ + GAUDI_QUEUE_ID_NIC_5_3 = 96, /* internal */ + GAUDI_QUEUE_ID_NIC_6_0 = 97, /* internal */ + GAUDI_QUEUE_ID_NIC_6_1 = 98, /* internal */ + GAUDI_QUEUE_ID_NIC_6_2 = 99, /* internal */ + GAUDI_QUEUE_ID_NIC_6_3 = 100, /* internal */ + GAUDI_QUEUE_ID_NIC_7_0 = 101, /* internal */ + GAUDI_QUEUE_ID_NIC_7_1 = 102, /* internal */ + GAUDI_QUEUE_ID_NIC_7_2 = 103, /* internal */ + GAUDI_QUEUE_ID_NIC_7_3 = 104, /* internal */ + GAUDI_QUEUE_ID_NIC_8_0 = 105, /* internal */ + GAUDI_QUEUE_ID_NIC_8_1 = 106, /* internal */ + GAUDI_QUEUE_ID_NIC_8_2 = 107, /* internal */ + GAUDI_QUEUE_ID_NIC_8_3 = 108, /* internal */ + GAUDI_QUEUE_ID_NIC_9_0 = 109, /* internal */ + GAUDI_QUEUE_ID_NIC_9_1 = 110, /* internal */ + GAUDI_QUEUE_ID_NIC_9_2 = 111, /* internal */ + GAUDI_QUEUE_ID_NIC_9_3 = 112, /* internal */ + GAUDI_QUEUE_ID_SIZE +}; + /* * Engine Numbering * @@ -69,6 +195,40 @@ enum goya_engine_id { GOYA_ENGINE_ID_SIZE }; +enum gaudi_engine_id { + GAUDI_ENGINE_ID_DMA_0 = 0, + GAUDI_ENGINE_ID_DMA_1, + GAUDI_ENGINE_ID_DMA_2, + GAUDI_ENGINE_ID_DMA_3, + GAUDI_ENGINE_ID_DMA_4, + GAUDI_ENGINE_ID_DMA_5, + GAUDI_ENGINE_ID_DMA_6, + GAUDI_ENGINE_ID_DMA_7, + GAUDI_ENGINE_ID_MME_0, + GAUDI_ENGINE_ID_MME_1, + GAUDI_ENGINE_ID_MME_2, + GAUDI_ENGINE_ID_MME_3, + GAUDI_ENGINE_ID_TPC_0, + GAUDI_ENGINE_ID_TPC_1, + GAUDI_ENGINE_ID_TPC_2, + GAUDI_ENGINE_ID_TPC_3, + GAUDI_ENGINE_ID_TPC_4, + GAUDI_ENGINE_ID_TPC_5, + GAUDI_ENGINE_ID_TPC_6, + GAUDI_ENGINE_ID_TPC_7, + GAUDI_ENGINE_ID_NIC_0, + GAUDI_ENGINE_ID_NIC_1, + GAUDI_ENGINE_ID_NIC_2, + GAUDI_ENGINE_ID_NIC_3, + GAUDI_ENGINE_ID_NIC_4, + GAUDI_ENGINE_ID_NIC_5, + GAUDI_ENGINE_ID_NIC_6, + GAUDI_ENGINE_ID_NIC_7, + GAUDI_ENGINE_ID_NIC_8, + GAUDI_ENGINE_ID_NIC_9, + GAUDI_ENGINE_ID_SIZE +}; + enum hl_device_status { HL_DEVICE_STATUS_OPERATIONAL, HL_DEVICE_STATUS_IN_RESET, @@ -101,6 +261,8 @@ enum hl_device_status { * HL_INFO_RESET_COUNT - Retrieve the counts of the soft and hard reset * operations performed on the device since the last * time the driver was loaded. + * HL_INFO_TIME_SYNC - Retrieve the device's time alongside the host's time + * for synchronization. */ #define HL_INFO_HW_IP_INFO 0 #define HL_INFO_HW_EVENTS 1 @@ -111,6 +273,7 @@ enum hl_device_status { #define HL_INFO_HW_EVENTS_AGGREGATE 7 #define HL_INFO_CLK_RATE 8 #define HL_INFO_RESET_COUNT 9 +#define HL_INFO_TIME_SYNC 10 #define HL_INFO_VERSION_MAX_LEN 128 #define HL_INFO_CARD_NAME_MAX_LEN 16 @@ -122,7 +285,8 @@ struct hl_info_hw_ip_info { __u32 sram_size; __u32 num_of_events; __u32 device_id; /* PCI Device ID */ - __u32 reserved[3]; + __u32 module_id; /* For mezzanine cards in servers (From OCP spec.) */ + __u32 reserved[2]; __u32 armcp_cpld_version; __u32 psoc_pci_pll_nr; __u32 psoc_pci_pll_nf; @@ -169,6 +333,11 @@ struct hl_info_reset_count { __u32 soft_reset_cnt; }; +struct hl_info_time_sync { + __u64 device_time; + __u64 host_time; +}; + struct hl_info_args { /* Location of relevant struct in userspace */ __u64 return_pointer; @@ -201,7 +370,8 @@ struct hl_info_args { /* Opcode to destroy previously created command buffer */ #define HL_CB_OP_DESTROY 1 -#define HL_MAX_CB_SIZE 0x200000 /* 2MB */ +/* 2MB minus 32 bytes for 2xMSG_PROT */ +#define HL_MAX_CB_SIZE (0x200000 - 32) struct hl_cb_in { /* Handle of CB or 0 if we want to create one */ @@ -232,52 +402,87 @@ union hl_cb_args { * compatibility */ struct hl_cs_chunk { - /* - * For external queue, this represents a Handle of CB on the Host - * For internal queue, this represents an SRAM or DRAM address of the - * internal CB - */ - __u64 cb_handle; + union { + /* For external queue, this represents a Handle of CB on the + * Host. + * For internal queue in Goya, this represents an SRAM or + * a DRAM address of the internal CB. In Gaudi, this might also + * represent a mapped host address of the CB. + * + * A mapped host address is in the device address space, after + * a host address was mapped by the device MMU. + */ + __u64 cb_handle; + + /* Relevant only when HL_CS_FLAGS_WAIT is set. + * This holds address of array of u64 values that contain + * signal CS sequence numbers. The wait described by this job + * will listen on all those signals (wait event per signal) + */ + __u64 signal_seq_arr; + }; + /* Index of queue to put the CB on */ __u32 queue_index; - /* - * Size of command buffer with valid packets - * Can be smaller then actual CB size - */ - __u32 cb_size; + + union { + /* + * Size of command buffer with valid packets + * Can be smaller then actual CB size + */ + __u32 cb_size; + + /* Relevant only when HL_CS_FLAGS_WAIT is set. + * Number of entries in signal_seq_arr + */ + __u32 num_signal_seq_arr; + }; + /* HL_CS_CHUNK_FLAGS_* */ __u32 cs_chunk_flags; + /* Align structure to 64 bytes */ __u32 pad[11]; }; +/* SIGNAL and WAIT flags are mutually exclusive */ #define HL_CS_FLAGS_FORCE_RESTORE 0x1 +#define HL_CS_FLAGS_SIGNAL 0x2 +#define HL_CS_FLAGS_WAIT 0x4 #define HL_CS_STATUS_SUCCESS 0 #define HL_MAX_JOBS_PER_CS 512 struct hl_cs_in { + /* this holds address of array of hl_cs_chunk for restore phase */ __u64 chunks_restore; - /* this holds address of array of hl_cs_chunk for execution phase */ + + /* holds address of array of hl_cs_chunk for execution phase */ __u64 chunks_execute; + /* this holds address of array of hl_cs_chunk for store phase - * Currently not in use */ __u64 chunks_store; + /* Number of chunks in restore phase array. Maximum number is * HL_MAX_JOBS_PER_CS */ __u32 num_chunks_restore; + /* Number of chunks in execution array. Maximum number is * HL_MAX_JOBS_PER_CS */ __u32 num_chunks_execute; + /* Number of chunks in restore phase array - Currently not in use */ __u32 num_chunks_store; + /* HL_CS_FLAGS_* */ __u32 cs_flags; + /* Context ID - Currently not in use */ __u32 ctx_id; }; @@ -588,8 +793,8 @@ struct hl_debug_args { * For jobs on external queues, the user needs to create command buffers * through the CB ioctl and give the CB's handle to the CS ioctl. For jobs on * internal queues, the user needs to prepare a "command buffer" with packets - * on either the SRAM or DRAM, and give the device address of that buffer to - * the CS ioctl. + * on either the device SRAM/DRAM or the host, and give the device address of + * that buffer to the CS ioctl. * * This IOCTL is asynchronous in regard to the actual execution of the CS. This * means it returns immediately after ALL the JOBS were enqueued on their @@ -601,7 +806,7 @@ struct hl_debug_args { * external JOBS have been completed. Note that if the CS has internal JOBS * which can execute AFTER the external JOBS have finished, the driver might * report that the CS has finished executing BEFORE the internal JOBS have - * actually finish executing. + * actually finished executing. * * Even though the sequence number increments per CS, the user can NOT * automatically assume that if CS with sequence number N finished, then CS diff --git a/kernel/debug/debug_core.c b/kernel/debug/debug_core.c index c200d4936679..ccc0f98abdd4 100644 --- a/kernel/debug/debug_core.c +++ b/kernel/debug/debug_core.c @@ -935,7 +935,7 @@ static void sysrq_handle_dbg(int key) kgdb_breakpoint(); } -static struct sysrq_key_op sysrq_dbg_op = { +static const struct sysrq_key_op sysrq_dbg_op = { .handler = sysrq_handle_dbg, .help_msg = "debug(g)", .action_msg = "DEBUG", diff --git a/kernel/power/poweroff.c b/kernel/power/poweroff.c index 6d475281c730..562aa0e450ed 100644 --- a/kernel/power/poweroff.c +++ b/kernel/power/poweroff.c @@ -29,7 +29,7 @@ static void handle_poweroff(int key) schedule_work_on(cpumask_first(cpu_online_mask), &poweroff_work); } -static struct sysrq_key_op sysrq_poweroff_op = { +static const struct sysrq_key_op sysrq_poweroff_op = { .handler = handle_poweroff, .help_msg = "poweroff(o)", .action_msg = "Power Off", diff --git a/kernel/rcu/tree_stall.h b/kernel/rcu/tree_stall.h index ae76bd329582..54a6dba0280d 100644 --- a/kernel/rcu/tree_stall.h +++ b/kernel/rcu/tree_stall.h @@ -807,7 +807,7 @@ static void sysrq_show_rcu(int key) show_rcu_gp_kthreads(); } -static struct sysrq_key_op sysrq_rcudump_op = { +static const struct sysrq_key_op sysrq_rcudump_op = { .handler = sysrq_show_rcu, .help_msg = "show-rcu(y)", .action_msg = "Show RCU tree", diff --git a/kernel/resource.c b/kernel/resource.c index 76036a41143b..841737bbda9e 100644 --- a/kernel/resource.c +++ b/kernel/resource.c @@ -1126,6 +1126,7 @@ struct resource * __request_region(struct resource *parent, { DECLARE_WAITQUEUE(wait, current); struct resource *res = alloc_resource(GFP_KERNEL); + struct resource *orig_parent = parent; if (!res) return NULL; @@ -1176,6 +1177,10 @@ struct resource * __request_region(struct resource *parent, break; } write_unlock(&resource_lock); + + if (res && orig_parent == &iomem_resource) + revoke_devmem(res); + return res; } EXPORT_SYMBOL(__request_region); diff --git a/lib/kobject.c b/lib/kobject.c index 65fa7bf70c57..1e4b7382a88e 100644 --- a/lib/kobject.c +++ b/lib/kobject.c @@ -620,6 +620,13 @@ void kobject_del(struct kobject *kobj) if (ktype) sysfs_remove_groups(kobj, ktype->default_groups); + /* send "remove" if the caller did not do it but sent "add" */ + if (kobj->state_add_uevent_sent && !kobj->state_remove_uevent_sent) { + pr_debug("kobject: '%s' (%p): auto cleanup 'remove' event\n", + kobject_name(kobj), kobj); + kobject_uevent(kobj, KOBJ_REMOVE); + } + sysfs_remove_dir(kobj); sysfs_put(sd); @@ -673,13 +680,6 @@ static void kobject_cleanup(struct kobject *kobj) pr_debug("kobject: '%s' (%p): does not have a release() function, it is broken and must be fixed. See Documentation/core-api/kobject.rst.\n", kobject_name(kobj), kobj); - /* send "remove" if the caller did not do it but sent "add" */ - if (kobj->state_add_uevent_sent && !kobj->state_remove_uevent_sent) { - pr_debug("kobject: '%s' (%p): auto cleanup 'remove' event\n", - kobject_name(kobj), kobj); - kobject_uevent(kobj, KOBJ_REMOVE); - } - /* remove from sysfs if the caller did not do it */ if (kobj->state_in_sysfs) { pr_debug("kobject: '%s' (%p): auto cleanup kobject_del\n", diff --git a/lib/test_firmware.c b/lib/test_firmware.c index 0c7fbcf07ac5..9fee2b93a8d1 100644 --- a/lib/test_firmware.c +++ b/lib/test_firmware.c @@ -310,27 +310,13 @@ static int test_dev_config_update_bool(const char *buf, size_t size, return ret; } -static ssize_t -test_dev_config_show_bool(char *buf, - bool config) +static ssize_t test_dev_config_show_bool(char *buf, bool val) { - bool val; - - mutex_lock(&test_fw_mutex); - val = config; - mutex_unlock(&test_fw_mutex); - return snprintf(buf, PAGE_SIZE, "%d\n", val); } -static ssize_t test_dev_config_show_int(char *buf, int cfg) +static ssize_t test_dev_config_show_int(char *buf, int val) { - int val; - - mutex_lock(&test_fw_mutex); - val = cfg; - mutex_unlock(&test_fw_mutex); - return snprintf(buf, PAGE_SIZE, "%d\n", val); } @@ -354,14 +340,8 @@ static int test_dev_config_update_u8(const char *buf, size_t size, u8 *cfg) return size; } -static ssize_t test_dev_config_show_u8(char *buf, u8 cfg) +static ssize_t test_dev_config_show_u8(char *buf, u8 val) { - u8 val; - - mutex_lock(&test_fw_mutex); - val = cfg; - mutex_unlock(&test_fw_mutex); - return snprintf(buf, PAGE_SIZE, "%u\n", val); } diff --git a/lib/test_printf.c b/lib/test_printf.c index 7d60f24240a4..7ac87f18a10f 100644 --- a/lib/test_printf.c +++ b/lib/test_printf.c @@ -644,7 +644,9 @@ static void __init fwnode_pointer(void) test(second_name, "%pfwP", software_node_fwnode(&softnodes[1])); test(third_name, "%pfwP", software_node_fwnode(&softnodes[2])); - software_node_unregister_nodes(softnodes); + software_node_unregister(&softnodes[2]); + software_node_unregister(&softnodes[1]); + software_node_unregister(&softnodes[0]); } static void __init diff --git a/security/apparmor/apparmorfs.c b/security/apparmor/apparmorfs.c index f6a3ecfadf80..5fd4a64e431f 100644 --- a/security/apparmor/apparmorfs.c +++ b/security/apparmor/apparmorfs.c @@ -340,38 +340,6 @@ static struct dentry *aafs_create_dir(const char *name, struct dentry *parent) NULL); } -/** - * aafs_create_symlink - create a symlink in the apparmorfs filesystem - * @name: name of dentry to create - * @parent: parent directory for this dentry - * @target: if symlink, symlink target string - * @private: private data - * @iops: struct of inode_operations that should be used - * - * If @target parameter is %NULL, then the @iops parameter needs to be - * setup to handle .readlink and .get_link inode_operations. - */ -static struct dentry *aafs_create_symlink(const char *name, - struct dentry *parent, - const char *target, - void *private, - const struct inode_operations *iops) -{ - struct dentry *dent; - char *link = NULL; - - if (target) { - if (!link) - return ERR_PTR(-ENOMEM); - } - dent = aafs_create(name, S_IFLNK | 0444, parent, private, link, NULL, - iops); - if (IS_ERR(dent)) - kfree(link); - - return dent; -} - /** * aafs_remove - removes a file or directory from the apparmorfs filesystem * @@ -624,7 +592,7 @@ static __poll_t ns_revision_poll(struct file *file, poll_table *pt) void __aa_bump_ns_revision(struct aa_ns *ns) { - WRITE_ONCE(ns->revision, ns->revision + 1); + WRITE_ONCE(ns->revision, READ_ONCE(ns->revision) + 1); wake_up_interruptible(&ns->wait); } @@ -840,7 +808,7 @@ static ssize_t query_label(char *buf, size_t buf_len, struct multi_transaction { struct kref count; ssize_t size; - char data[0]; + char data[]; }; #define MULTI_TRANSACTION_LIMIT (PAGE_SIZE - sizeof(struct multi_transaction)) @@ -1763,25 +1731,25 @@ int __aafs_profile_mkdir(struct aa_profile *profile, struct dentry *parent) } if (profile->rawdata) { - dent = aafs_create_symlink("raw_sha1", dir, NULL, - profile->label.proxy, - &rawdata_link_sha1_iops); + dent = aafs_create("raw_sha1", S_IFLNK | 0444, dir, + profile->label.proxy, NULL, NULL, + &rawdata_link_sha1_iops); if (IS_ERR(dent)) goto fail; aa_get_proxy(profile->label.proxy); profile->dents[AAFS_PROF_RAW_HASH] = dent; - dent = aafs_create_symlink("raw_abi", dir, NULL, - profile->label.proxy, - &rawdata_link_abi_iops); + dent = aafs_create("raw_abi", S_IFLNK | 0444, dir, + profile->label.proxy, NULL, NULL, + &rawdata_link_abi_iops); if (IS_ERR(dent)) goto fail; aa_get_proxy(profile->label.proxy); profile->dents[AAFS_PROF_RAW_ABI] = dent; - dent = aafs_create_symlink("raw_data", dir, NULL, - profile->label.proxy, - &rawdata_link_data_iops); + dent = aafs_create("raw_data", S_IFLNK | 0444, dir, + profile->label.proxy, NULL, NULL, + &rawdata_link_data_iops); if (IS_ERR(dent)) goto fail; aa_get_proxy(profile->label.proxy); @@ -2364,6 +2332,8 @@ static struct aa_sfs_entry aa_sfs_entry_versions[] = { static struct aa_sfs_entry aa_sfs_entry_policy[] = { AA_SFS_DIR("versions", aa_sfs_entry_versions), AA_SFS_FILE_BOOLEAN("set_load", 1), + /* number of out of band transitions supported */ + AA_SFS_FILE_U64("outofband", MAX_OOB_SUPPORTED), { } }; diff --git a/security/apparmor/domain.c b/security/apparmor/domain.c index 745a1cf49003..1c898055a476 100644 --- a/security/apparmor/domain.c +++ b/security/apparmor/domain.c @@ -320,8 +320,7 @@ static int aa_xattrs_match(const struct linux_binprm *bprm, might_sleep(); /* transition from exec match to xattr set */ - state = aa_dfa_null_transition(profile->xmatch, state); - + state = aa_dfa_outofband_transition(profile->xmatch, state); d = bprm->file->f_path.dentry; for (i = 0; i < profile->xattr_count; i++) { @@ -330,7 +329,13 @@ static int aa_xattrs_match(const struct linux_binprm *bprm, if (size >= 0) { u32 perm; - /* Check the xattr value, not just presence */ + /* + * Check the xattr presence before value. This ensure + * that not present xattr can be distinguished from a 0 + * length value or rule that matches any value + */ + state = aa_dfa_null_transition(profile->xmatch, state); + /* Check xattr value */ state = aa_dfa_match_len(profile->xmatch, state, value, size); perm = dfa_user_allow(profile->xmatch, state); @@ -340,7 +345,7 @@ static int aa_xattrs_match(const struct linux_binprm *bprm, } } /* transition to next element */ - state = aa_dfa_null_transition(profile->xmatch, state); + state = aa_dfa_outofband_transition(profile->xmatch, state); if (size < 0) { /* * No xattr match, so verify if transition to @@ -620,8 +625,6 @@ static struct aa_label *profile_transition(struct aa_profile *profile, bool *secure_exec) { struct aa_label *new = NULL; - struct aa_profile *component; - struct label_it i; const char *info = NULL, *name = NULL, *target = NULL; unsigned int state = profile->file.start; struct aa_perms perms = {}; @@ -670,21 +673,6 @@ static struct aa_label *profile_transition(struct aa_profile *profile, info = "profile transition not found"; /* remove MAY_EXEC to audit as failure */ perms.allow &= ~MAY_EXEC; - } else { - /* verify that each component's xattr requirements are - * met, and fail execution otherwise - */ - label_for_each(i, new, component) { - if (aa_xattrs_match(bprm, component, state) < - 0) { - error = -EACCES; - info = "required xattrs not present"; - perms.allow &= ~MAY_EXEC; - aa_put_label(new); - new = NULL; - goto audit; - } - } } } else if (COMPLAIN_MODE(profile)) { /* no exec permission - learning mode */ @@ -926,7 +914,8 @@ int apparmor_bprm_creds_for_exec(struct linux_binprm *bprm) * aways results in a further reduction of permissions. */ if ((bprm->unsafe & LSM_UNSAFE_NO_NEW_PRIVS) && - !unconfined(label) && !aa_label_is_subset(new, ctx->nnp)) { + !unconfined(label) && + !aa_label_is_unconfined_subset(new, ctx->nnp)) { error = -EPERM; info = "no new privs"; goto audit; @@ -1204,7 +1193,7 @@ int aa_change_hat(const char *hats[], int count, u64 token, int flags) * reduce restrictions. */ if (task_no_new_privs(current) && !unconfined(label) && - !aa_label_is_subset(new, ctx->nnp)) { + !aa_label_is_unconfined_subset(new, ctx->nnp)) { /* not an apparmor denial per se, so don't log it */ AA_DEBUG("no_new_privs - change_hat denied"); error = -EPERM; @@ -1225,7 +1214,7 @@ int aa_change_hat(const char *hats[], int count, u64 token, int flags) * reduce restrictions. */ if (task_no_new_privs(current) && !unconfined(label) && - !aa_label_is_subset(previous, ctx->nnp)) { + !aa_label_is_unconfined_subset(previous, ctx->nnp)) { /* not an apparmor denial per se, so don't log it */ AA_DEBUG("no_new_privs - change_hat denied"); error = -EPERM; @@ -1420,7 +1409,7 @@ check: * reduce restrictions. */ if (task_no_new_privs(current) && !unconfined(label) && - !aa_label_is_subset(new, ctx->nnp)) { + !aa_label_is_unconfined_subset(new, ctx->nnp)) { /* not an apparmor denial per se, so don't log it */ AA_DEBUG("no_new_privs - change_hat denied"); error = -EPERM; diff --git a/security/apparmor/file.c b/security/apparmor/file.c index f1caf3674e1c..9a2d14b7c9f8 100644 --- a/security/apparmor/file.c +++ b/security/apparmor/file.c @@ -154,13 +154,13 @@ int aa_audit_file(struct aa_profile *profile, struct aa_perms *perms, * is_deleted - test if a file has been completely unlinked * @dentry: dentry of file to test for deletion (NOT NULL) * - * Returns: %1 if deleted else %0 + * Returns: true if deleted else false */ static inline bool is_deleted(struct dentry *dentry) { if (d_unlinked(dentry) && d_backing_inode(dentry)->i_nlink == 0) - return 1; - return 0; + return true; + return false; } static int path_name(const char *op, struct aa_label *label, @@ -353,15 +353,15 @@ int aa_path_perm(const char *op, struct aa_label *label, * this is done as part of the subset test, where a hardlink must have * a subset of permissions that the target has. * - * Returns: %1 if subset else %0 + * Returns: true if subset else false */ static inline bool xindex_is_subset(u32 link, u32 target) { if (((link & ~AA_X_UNSAFE) != (target & ~AA_X_UNSAFE)) || ((link & AA_X_UNSAFE) && !(target & AA_X_UNSAFE))) - return 0; + return false; - return 1; + return true; } static int profile_path_link(struct aa_profile *profile, diff --git a/security/apparmor/include/label.h b/security/apparmor/include/label.h index 47942c4ba7ca..1e90384b1523 100644 --- a/security/apparmor/include/label.h +++ b/security/apparmor/include/label.h @@ -275,12 +275,14 @@ void aa_labelset_destroy(struct aa_labelset *ls); void aa_labelset_init(struct aa_labelset *ls); void __aa_labelset_update_subtree(struct aa_ns *ns); +void aa_label_destroy(struct aa_label *label); void aa_label_free(struct aa_label *label); void aa_label_kref(struct kref *kref); bool aa_label_init(struct aa_label *label, int size, gfp_t gfp); struct aa_label *aa_label_alloc(int size, struct aa_proxy *proxy, gfp_t gfp); bool aa_label_is_subset(struct aa_label *set, struct aa_label *sub); +bool aa_label_is_unconfined_subset(struct aa_label *set, struct aa_label *sub); struct aa_profile *__aa_label_next_not_in_set(struct label_it *I, struct aa_label *set, struct aa_label *sub); diff --git a/security/apparmor/include/match.h b/security/apparmor/include/match.h index e23f4aadc1ff..884489590588 100644 --- a/security/apparmor/include/match.h +++ b/security/apparmor/include/match.h @@ -37,6 +37,10 @@ #define YYTH_MAGIC 0x1B5E783D #define YYTH_FLAG_DIFF_ENCODE 1 +#define YYTH_FLAG_OOB_TRANS 2 +#define YYTH_FLAGS (YYTH_FLAG_DIFF_ENCODE | YYTH_FLAG_OOB_TRANS) + +#define MAX_OOB_SUPPORTED 1 struct table_set_header { u32 th_magic; /* YYTH_MAGIC */ @@ -94,6 +98,7 @@ struct table_header { struct aa_dfa { struct kref count; u16 flags; + u32 max_oob; struct table_header *tables[YYTD_ID_TSIZE]; }; @@ -127,6 +132,8 @@ unsigned int aa_dfa_match(struct aa_dfa *dfa, unsigned int start, const char *str); unsigned int aa_dfa_next(struct aa_dfa *dfa, unsigned int state, const char c); +unsigned int aa_dfa_outofband_transition(struct aa_dfa *dfa, + unsigned int state); unsigned int aa_dfa_match_until(struct aa_dfa *dfa, unsigned int start, const char *str, const char **retpos); unsigned int aa_dfa_matchn_until(struct aa_dfa *dfa, unsigned int start, @@ -181,5 +188,9 @@ static inline void aa_put_dfa(struct aa_dfa *dfa) #define MATCH_FLAG_DIFF_ENCODE 0x80000000 #define MARK_DIFF_ENCODE 0x40000000 +#define MATCH_FLAG_OOB_TRANSITION 0x20000000 +#define MATCH_FLAGS_MASK 0xff000000 +#define MATCH_FLAGS_VALID (MATCH_FLAG_DIFF_ENCODE | MATCH_FLAG_OOB_TRANSITION) +#define MATCH_FLAGS_INVALID (MATCH_FLAGS_MASK & ~MATCH_FLAGS_VALID) #endif /* __AA_MATCH_H */ diff --git a/security/apparmor/label.c b/security/apparmor/label.c index 470693239e64..e68bcedca976 100644 --- a/security/apparmor/label.c +++ b/security/apparmor/label.c @@ -309,10 +309,8 @@ out: } -static void label_destroy(struct aa_label *label) +void aa_label_destroy(struct aa_label *label) { - struct aa_label *tmp; - AA_BUG(!label); if (!label_isprofile(label)) { @@ -328,16 +326,13 @@ static void label_destroy(struct aa_label *label) } } - if (rcu_dereference_protected(label->proxy->label, true) == label) - rcu_assign_pointer(label->proxy->label, NULL); - + if (label->proxy) { + if (rcu_dereference_protected(label->proxy->label, true) == label) + rcu_assign_pointer(label->proxy->label, NULL); + aa_put_proxy(label->proxy); + } aa_free_secid(label->secid); - tmp = rcu_dereference_protected(label->proxy->label, true); - if (tmp == label) - rcu_assign_pointer(label->proxy->label, NULL); - - aa_put_proxy(label->proxy); label->proxy = (struct aa_proxy *) PROXY_POISON + 1; } @@ -346,7 +341,7 @@ void aa_label_free(struct aa_label *label) if (!label) return; - label_destroy(label); + aa_label_destroy(label); kfree(label); } @@ -550,6 +545,39 @@ bool aa_label_is_subset(struct aa_label *set, struct aa_label *sub) return __aa_label_next_not_in_set(&i, set, sub) == NULL; } +/** + * aa_label_is_unconfined_subset - test if @sub is a subset of @set + * @set: label to test against + * @sub: label to test if is subset of @set + * + * This checks for subset but taking into account unconfined. IF + * @sub contains an unconfined profile that does not have a matching + * unconfined in @set then this will not cause the test to fail. + * Conversely we don't care about an unconfined in @set that is not in + * @sub + * + * Returns: true if @sub is special_subset of @set + * else false + */ +bool aa_label_is_unconfined_subset(struct aa_label *set, struct aa_label *sub) +{ + struct label_it i = { }; + struct aa_profile *p; + + AA_BUG(!set); + AA_BUG(!sub); + + if (sub == set) + return true; + + do { + p = __aa_label_next_not_in_set(&i, set, sub); + if (p && !profile_unconfined(p)) + break; + } while (p); + + return p == NULL; +} /** @@ -1531,13 +1559,13 @@ static const char *label_modename(struct aa_ns *ns, struct aa_label *label, label_for_each(i, label, profile) { if (aa_ns_visible(ns, profile->ns, flags & FLAG_VIEW_SUBNS)) { - if (profile->mode == APPARMOR_UNCONFINED) + count++; + if (profile == profile->ns->unconfined) /* special case unconfined so stacks with * unconfined don't report as mixed. ie. * profile_foo//&:ns1:unconfined (mixed) */ continue; - count++; if (mode == -1) mode = profile->mode; else if (mode != profile->mode) @@ -1749,13 +1777,13 @@ void aa_label_seq_xprint(struct seq_file *f, struct aa_ns *ns, AA_DEBUG("label print error"); return; } - seq_printf(f, "%s", str); + seq_puts(f, str); kfree(str); } else if (display_mode(ns, label, flags)) seq_printf(f, "%s (%s)", label->hname, label_modename(ns, label, flags)); else - seq_printf(f, "%s", label->hname); + seq_puts(f, label->hname); } void aa_label_xprintk(struct aa_ns *ns, struct aa_label *label, int flags, diff --git a/security/apparmor/lsm.c b/security/apparmor/lsm.c index ef6f7002af28..ffeaee5ed968 100644 --- a/security/apparmor/lsm.c +++ b/security/apparmor/lsm.c @@ -804,7 +804,12 @@ static void apparmor_sk_clone_security(const struct sock *sk, struct aa_sk_ctx *ctx = SK_CTX(sk); struct aa_sk_ctx *new = SK_CTX(newsk); + if (new->label) + aa_put_label(new->label); new->label = aa_get_label(ctx->label); + + if (new->peer) + aa_put_label(new->peer); new->peer = aa_get_label(ctx->peer); } diff --git a/security/apparmor/match.c b/security/apparmor/match.c index 525ce22dc0e9..3e9e1eaf990e 100644 --- a/security/apparmor/match.c +++ b/security/apparmor/match.c @@ -97,6 +97,9 @@ static struct table_header *unpack_table(char *blob, size_t bsize) th.td_flags == YYTD_DATA8)) goto out; + /* if we have a table it must have some entries */ + if (th.td_lolen == 0) + goto out; tsize = table_size(th.td_lolen, th.td_flags); if (bsize < tsize) goto out; @@ -198,10 +201,32 @@ static int verify_dfa(struct aa_dfa *dfa) state_count = dfa->tables[YYTD_ID_BASE]->td_lolen; trans_count = dfa->tables[YYTD_ID_NXT]->td_lolen; + if (state_count == 0) + goto out; for (i = 0; i < state_count; i++) { if (!(BASE_TABLE(dfa)[i] & MATCH_FLAG_DIFF_ENCODE) && (DEFAULT_TABLE(dfa)[i] >= state_count)) goto out; + if (BASE_TABLE(dfa)[i] & MATCH_FLAGS_INVALID) { + pr_err("AppArmor DFA state with invalid match flags"); + goto out; + } + if ((BASE_TABLE(dfa)[i] & MATCH_FLAG_DIFF_ENCODE)) { + if (!(dfa->flags & YYTH_FLAG_DIFF_ENCODE)) { + pr_err("AppArmor DFA diff encoded transition state without header flag"); + goto out; + } + } + if ((BASE_TABLE(dfa)[i] & MATCH_FLAG_OOB_TRANSITION)) { + if (base_idx(BASE_TABLE(dfa)[i]) < dfa->max_oob) { + pr_err("AppArmor DFA out of bad transition out of range"); + goto out; + } + if (!(dfa->flags & YYTH_FLAG_OOB_TRANS)) { + pr_err("AppArmor DFA out of bad transition state without header flag"); + goto out; + } + } if (base_idx(BASE_TABLE(dfa)[i]) + 255 >= trans_count) { pr_err("AppArmor DFA next/check upper bounds error\n"); goto out; @@ -304,9 +329,23 @@ struct aa_dfa *aa_dfa_unpack(void *blob, size_t size, int flags) goto fail; dfa->flags = ntohs(*(__be16 *) (data + 12)); - if (dfa->flags != 0 && dfa->flags != YYTH_FLAG_DIFF_ENCODE) + if (dfa->flags & ~(YYTH_FLAGS)) goto fail; + /* + * TODO: needed for dfa to support more than 1 oob + * if (dfa->flags & YYTH_FLAGS_OOB_TRANS) { + * if (hsize < 16 + 4) + * goto fail; + * dfa->max_oob = ntol(*(__be32 *) (data + 16)); + * if (dfa->max <= MAX_OOB_SUPPORTED) { + * pr_err("AppArmor DFA OOB greater than supported\n"); + * goto fail; + * } + * } + */ + dfa->max_oob = 1; + data += hsize; size -= hsize; @@ -495,6 +534,23 @@ unsigned int aa_dfa_next(struct aa_dfa *dfa, unsigned int state, return state; } +unsigned int aa_dfa_outofband_transition(struct aa_dfa *dfa, unsigned int state) +{ + u16 *def = DEFAULT_TABLE(dfa); + u32 *base = BASE_TABLE(dfa); + u16 *next = NEXT_TABLE(dfa); + u16 *check = CHECK_TABLE(dfa); + u32 b = (base)[(state)]; + + if (!(b & MATCH_FLAG_OOB_TRANSITION)) + return DFA_NOMATCH; + + /* No Equivalence class remapping for outofband transitions */ + match_char(state, def, base, next, check, -1); + + return state; +} + /** * aa_dfa_match_until - traverse @dfa until accept state or end of input * @dfa: the dfa to match @str against (NOT NULL) diff --git a/security/apparmor/path.c b/security/apparmor/path.c index c6da542de27b..b02dfdbff7cd 100644 --- a/security/apparmor/path.c +++ b/security/apparmor/path.c @@ -142,7 +142,7 @@ static int d_namespace_path(const struct path *path, char *buf, char **name, error = PTR_ERR(res); *name = buf; goto out; - }; + } } else if (!our_mnt(path->mnt)) connected = 0; diff --git a/security/apparmor/policy.c b/security/apparmor/policy.c index 269f2f53c0b1..af4f50fda9e3 100644 --- a/security/apparmor/policy.c +++ b/security/apparmor/policy.c @@ -242,6 +242,7 @@ void aa_free_profile(struct aa_profile *profile) kzfree(profile->hash); aa_put_loaddata(profile->rawdata); + aa_label_destroy(&profile->label); kzfree(profile); } diff --git a/security/apparmor/policy_unpack.c b/security/apparmor/policy_unpack.c index 2d743c004bc4..b67322abcc33 100644 --- a/security/apparmor/policy_unpack.c +++ b/security/apparmor/policy_unpack.c @@ -243,11 +243,11 @@ fail: static bool unpack_X(struct aa_ext *e, enum aa_code code) { if (!inbounds(e, 1)) - return 0; + return false; if (*(u8 *) e->pos != code) - return 0; + return false; e->pos++; - return 1; + return true; } /** @@ -261,10 +261,10 @@ static bool unpack_X(struct aa_ext *e, enum aa_code code) * name element in the stream. If @name is NULL any name element will be * skipped and only the typecode will be tested. * - * Returns 1 on success (both type code and name tests match) and the read + * Returns true on success (both type code and name tests match) and the read * head is advanced past the headers * - * Returns: 0 if either match fails, the read head does not move + * Returns: false if either match fails, the read head does not move */ static bool unpack_nameX(struct aa_ext *e, enum aa_code code, const char *name) { @@ -289,11 +289,11 @@ static bool unpack_nameX(struct aa_ext *e, enum aa_code code, const char *name) /* now check if type code matches */ if (unpack_X(e, code)) - return 1; + return true; fail: e->pos = pos; - return 0; + return false; } static bool unpack_u8(struct aa_ext *e, u8 *data, const char *name) @@ -306,12 +306,12 @@ static bool unpack_u8(struct aa_ext *e, u8 *data, const char *name) if (data) *data = get_unaligned((u8 *)e->pos); e->pos += sizeof(u8); - return 1; + return true; } fail: e->pos = pos; - return 0; + return false; } static bool unpack_u32(struct aa_ext *e, u32 *data, const char *name) @@ -324,12 +324,12 @@ static bool unpack_u32(struct aa_ext *e, u32 *data, const char *name) if (data) *data = le32_to_cpu(get_unaligned((__le32 *) e->pos)); e->pos += sizeof(u32); - return 1; + return true; } fail: e->pos = pos; - return 0; + return false; } static bool unpack_u64(struct aa_ext *e, u64 *data, const char *name) @@ -342,12 +342,12 @@ static bool unpack_u64(struct aa_ext *e, u64 *data, const char *name) if (data) *data = le64_to_cpu(get_unaligned((__le64 *) e->pos)); e->pos += sizeof(u64); - return 1; + return true; } fail: e->pos = pos; - return 0; + return false; } static size_t unpack_array(struct aa_ext *e, const char *name) @@ -472,7 +472,7 @@ static struct aa_dfa *unpack_dfa(struct aa_ext *e) * @e: serialized data extent information (NOT NULL) * @profile: profile to add the accept table to (NOT NULL) * - * Returns: 1 if table successfully unpacked + * Returns: true if table successfully unpacked */ static bool unpack_trans_table(struct aa_ext *e, struct aa_profile *profile) { @@ -535,12 +535,12 @@ static bool unpack_trans_table(struct aa_ext *e, struct aa_profile *profile) if (!unpack_nameX(e, AA_STRUCTEND, NULL)) goto fail; } - return 1; + return true; fail: aa_free_domain_entries(&profile->file.trans); e->pos = saved_pos; - return 0; + return false; } static bool unpack_xattrs(struct aa_ext *e, struct aa_profile *profile) @@ -565,11 +565,11 @@ static bool unpack_xattrs(struct aa_ext *e, struct aa_profile *profile) goto fail; } - return 1; + return true; fail: e->pos = pos; - return 0; + return false; } static bool unpack_secmark(struct aa_ext *e, struct aa_profile *profile) @@ -601,7 +601,7 @@ static bool unpack_secmark(struct aa_ext *e, struct aa_profile *profile) goto fail; } - return 1; + return true; fail: if (profile->secmark) { @@ -613,7 +613,7 @@ fail: } e->pos = pos; - return 0; + return false; } static bool unpack_rlimits(struct aa_ext *e, struct aa_profile *profile) @@ -643,11 +643,11 @@ static bool unpack_rlimits(struct aa_ext *e, struct aa_profile *profile) if (!unpack_nameX(e, AA_STRUCTEND, NULL)) goto fail; } - return 1; + return true; fail: e->pos = pos; - return 0; + return false; } static u32 strhash(const void *data, u32 len, u32 seed) @@ -748,10 +748,14 @@ static struct aa_profile *unpack_profile(struct aa_ext *e, char **ns_name) goto fail; if (tmp == PACKED_MODE_COMPLAIN || (e->version & FORCE_COMPLAIN_FLAG)) profile->mode = APPARMOR_COMPLAIN; + else if (tmp == PACKED_MODE_ENFORCE) + profile->mode = APPARMOR_ENFORCE; else if (tmp == PACKED_MODE_KILL) profile->mode = APPARMOR_KILL; else if (tmp == PACKED_MODE_UNCONFINED) profile->mode = APPARMOR_UNCONFINED; + else + goto fail; if (!unpack_u32(e, &tmp, NULL)) goto fail; if (tmp) @@ -990,8 +994,8 @@ static bool verify_xindex(int xindex, int table_size) xtype = xindex & AA_X_TYPE_MASK; index = xindex & AA_X_INDEX_MASK; if (xtype == AA_X_TABLE && index >= table_size) - return 0; - return 1; + return false; + return true; } /* verify dfa xindexes are in range of transition tables */ @@ -1000,11 +1004,11 @@ static bool verify_dfa_xindex(struct aa_dfa *dfa, int table_size) int i; for (i = 0; i < dfa->tables[YYTD_ID_ACCEPT]->td_lolen; i++) { if (!verify_xindex(dfa_user_xindex(dfa, i), table_size)) - return 0; + return false; if (!verify_xindex(dfa_other_xindex(dfa, i), table_size)) - return 0; + return false; } - return 1; + return true; } /** diff --git a/security/integrity/ima/ima_crypto.c b/security/integrity/ima/ima_crypto.c index ba5cc3264240..220b14920c37 100644 --- a/security/integrity/ima/ima_crypto.c +++ b/security/integrity/ima/ima_crypto.c @@ -786,7 +786,7 @@ int ima_calc_buffer_hash(const void *buf, loff_t len, return calc_buffer_shash(buf, len, hash); } -static void __init ima_pcrread(u32 idx, struct tpm_digest *d) +static void ima_pcrread(u32 idx, struct tpm_digest *d) { if (!ima_tpm_chip) return; diff --git a/tools/testing/selftests/ntb/ntb_test.sh b/tools/testing/selftests/ntb/ntb_test.sh index 9c60337317c6..020137b61407 100755 --- a/tools/testing/selftests/ntb/ntb_test.sh +++ b/tools/testing/selftests/ntb/ntb_test.sh @@ -241,7 +241,7 @@ function get_files_count() split_remote $LOC if [[ "$REMOTE" == "" ]]; then - echo $(ls -1 "$LOC"/${NAME}* 2>/dev/null | wc -l) + echo $(ls -1 "$VPATH"/${NAME}* 2>/dev/null | wc -l) else echo $(ssh "$REMOTE" "ls -1 \"$VPATH\"/${NAME}* | \ wc -l" 2> /dev/null)