From 884b17df32ed6552013e4750a15d3deccf64dd9d Mon Sep 17 00:00:00 2001
From: Wyon bi <bivvy.bi@rock-chips.com>
Date: Sat, 8 Jan 2022 12:18:06 +0800
Subject: [PATCH] drm/bridge: analogix_dp: Check return value of
 analogix_dp_get_max_rx_{bandwidth,lane_count}()

Signed-off-by: Wyon bi <bivvy.bi@rock-chips.com>
Change-Id: I5ab9ddad5afe1ece5da270f59f6ef533540f1cb3
---
 .../drm/bridge/analogix/analogix_dp_core.c    | 41 +++++++++++++++----
 1 file changed, 32 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index b3d7756df457..4a1e90bdd8ab 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -625,10 +625,11 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
 	return 0;
 }
 
-static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
-					     u8 *bandwidth)
+static int analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
+					    u8 *bandwidth)
 {
 	u8 data;
+	int ret;
 
 	/*
 	 * For DP rev.1.1, Maximum link rate of Main Link lanes
@@ -636,21 +637,32 @@ static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
 	 * For DP rev.1.2, Maximum link rate of Main Link lanes
 	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
 	 */
-	drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data);
+	ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data);
+	if (ret < 0)
+		return ret;
+
 	*bandwidth = data;
+
+	return 0;
 }
 
-static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
-					      u8 *lane_count)
+static int analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
+					     u8 *lane_count)
 {
 	u8 data;
+	int ret;
 
 	/*
 	 * For DP rev.1.1, Maximum number of Main Link lanes
 	 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 	 */
-	drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
+	ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
+	if (ret < 0)
+		return ret;
+
 	*lane_count = DPCD_MAX_LANE_COUNT(data);
+
+	return 0;
 }
 
 static int analogix_dp_full_link_train(struct analogix_dp_device *dp,
@@ -1171,6 +1183,7 @@ static enum drm_connector_status
 analogix_dp_detect(struct analogix_dp_device *dp)
 {
 	enum drm_connector_status status = connector_status_disconnected;
+	int ret;
 
 	if (dp->plat_data->panel)
 		analogix_dp_panel_prepare(dp);
@@ -1178,12 +1191,22 @@ analogix_dp_detect(struct analogix_dp_device *dp)
 	pm_runtime_get_sync(dp->dev);
 
 	if (!analogix_dp_detect_hpd(dp)) {
-		status = connector_status_connected;
+		ret = analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
+		if (ret) {
+			dev_err(dp->dev, "failed to read max link rate\n");
+			goto out;
+		}
 
-		analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
-		analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
+		ret = analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
+		if (ret) {
+			dev_err(dp->dev, "failed to read max lane count\n");
+			goto out;
+		}
+
+		status = connector_status_connected;
 	}
 
+out:
 	pm_runtime_put(dp->dev);
 
 	return status;