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rk2928&rk30&rk3066b: new iomux support

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kfx
2012-12-25 11:50:21 +08:00
parent 8e031bb647
commit 889b469633
10 changed files with 759 additions and 5 deletions
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129
arch/arm/mach-rk2928/include/mach/iomux-rk2928.h Normal file
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@@ -0,0 +1,129 @@
#ifndef __MACH_RK2928_IOMUX_H
#define __MACH_RK2928_IOMUX_H
#include <mach/io.h>
#include <plat/iomux.h>
#define GRF_IOMUX_BASE (RK2928_GRF_BASE + 0x00a8)
#define GPIO_BANKS 4
enum{
/* GPIO0_A */
GPIO0_A0 = 0x0a00, I2C0_SCL,
GPIO0_A1 = 0x0a10, I2C0_SDA,
GPIO0_A2 = 0x0a20, I2C1_SCL,
GPIO0_A3 = 0x0a30, I2C1_SDA,
GPIO0_A6 = 0x0a60, I2C3_SCL, HDMI_DDCSCL,
GPIO0_A7 = 0x0a70, I2C3_SDA, HDMI_DDCSDA,
/* GPIO0_B */
GPIO0_B0 = 0x0b00, MMC1_CMD,
GPIO0_B1 = 0x0b10, MMC1_CLKOUT,
GPIO0_B2 = 0x0b20, MMC1_DETN,
GPIO0_B3 = 0x0b30, MMC1_D0,
GPIO0_B4 = 0x0b40, MMC1_D1,
GPIO0_B5 = 0x0b50, MMC1_D2,
GPIO0_B6 = 0x0b60, MMC1_D3,
GPIO0_B7 = 0x0b70, HDMI_HOTPLUGIN,
/* GPIO0_C */
GPIO0_C0 = 0x0c00, UART0_SOUT,
GPIO0_C1 = 0x0c10, UART0_SIN,
GPIO0_C2 = 0x0c20, UART0_RTSN,
GPIO0_C3 = 0x0c30, UART0_CTSN,
GPIO0_C4 = 0x0c40, HDMI_CECSDA,
GPIO0_C7 = 0x0c70, NAND_CS1,
/* GPIO0_D */
GPIO0_D0 = 0x0d00, UART2_RTSN,
GPIO0_D1 = 0x0d10, UART2_CTSN,
GPIO0_D2 = 0x0d20, PWM0,
GPIO0_D3 = 0x0d30, PWM1,
GPIO0_D4 = 0x0d40, PWM2,
GPIO0_D5 = 0x0d50, MMC1_WRPRT,
GPIO0_D6 = 0x0d60, MMC1_PWREN,
GPIO0_D7 = 0x0d70, MMC1_BKEPWR,
/* GPIO1_A */
GPIO1_A0 = 0x1a00, I2S0_MCLK,
GPIO1_A1 = 0x1a10, I2S0_SCLK,
GPIO1_A2 = 0x1a20, I2S0_LRCKRX, GPS_CLK,
GPIO1_A3 = 0x1a30, I2S0_LRCKTX,
GPIO1_A4 = 0x1a40, I2S0_SDO, GPS_MAG,
GPIO1_A5 = 0x1a50, I2S0_SDI, GPS_SIGN,
GPIO1_A6 = 0x1a60, MMC1_INTN,
GPIO1_A7 = 0x1a70, MMC0_WRPRT,
/* GPIO1_B */
GPIO1_B0 = 0x1b00, SPI0_CLK, UART1_CTSN,
GPIO1_B1 = 0x1b10, SPI0_TXD, UART1_SOUT,
GPIO1_B2 = 0x1b20, SPI0_RXD, UART1_SIN,
GPIO1_B3 = 0x1b30, SPI0_CS0, UART1_RTSN,
GPIO1_B4 = 0x1b40, SPI0_CS1,
GPIO1_B5 = 0x1b50, MMC0_RSTNOUT,
GPIO1_B6 = 0x1b60, MMC0_PWREN,
GPIO1_B7 = 0x1b70, MMC0_CMD,
/* GPIO1_C */
GPIO1_C0 = 0x1c00, MMC0_CLKOUT,
GPIO1_C1 = 0x1c10, MMC0_DETN,
GPIO1_C2 = 0x1c20, MMC0_D0,
GPIO1_C3 = 0x1c30, MMC0_D1,
GPIO1_C4 = 0x1c40, MMC0_D2,
GPIO1_C5 = 0x1c50, MMC0_D3,
GPIO1_C6 = 0x1c60, NAND_CS2, EMMC_CMD,
GPIO1_C7 = 0x1c70, NAND_CS3, EMMC_RSTNOUT,
/* GPIO1_D */
GPIO1_D0 = 0x1d00, NAND_D0, EMMC_D0,
GPIO1_D1 = 0x1d10, NAND_D1, EMMC_D1,
GPIO1_D2 = 0x1d20, NAND_D2, EMMC_D2,
GPIO1_D3 = 0x1d30, NAND_D3, EMMC_D3,
GPIO1_D4 = 0x1d40, NAND_D4, EMMC_D4,
GPIO1_D5 = 0x1d50, NAND_D5, EMMC_D5,
GPIO1_D6 = 0x1d60, NAND_D6, EMMC_D6,
GPIO1_D7 = 0x1d70, NAND_D7, EMMC_D7,
/* GPIO2_A */
GPIO2_A0 = 0x2a00, NAND_ALE,
GPIO2_A1 = 0x2a10, NAND_CLE,
GPIO2_A2 = 0x2a20, NAND_WRN,
GPIO2_A3 = 0x2a30, NAND_RDN,
GPIO2_A4 = 0x2a40, NAND_RDY,
GPIO2_A5 = 0x2a50, NAND_WP, EMMC_PWREN,
GPIO2_A6 = 0x2a60, NAND_CS0,
GPIO2_A7 = 0x2a70, NAND_DQS, EMMC_CLKOUT,
/* GPIO2_B */
GPIO2_B0 = 0x2b00, LCDC0_DCLK, LCDC1_DCLK,
GPIO2_B1 = 0x2b10, LCDC0_HSYNC, LCDC1_HSYNC,
GPIO2_B2 = 0x2b20, LCDC0_VSYNC, LCDC1_VSYNC,
GPIO2_B3 = 0x2b30, LCDC0_DEN, LCDC1_DEN,
GPIO2_B4 = 0x2b40, LCDC0_D10, LCDC1_D10,
GPIO2_B5 = 0x2b50, LCDC0_D11, LCDC1_D11,
GPIO2_B6 = 0x2b60, LCDC0_D12, LCDC1_D12,
GPIO2_B7 = 0x2b70, LCDC0_D13, LCDC1_D13,
/* GPIO2_C */
GPIO2_C0 = 0x2c00, LCDC0_D14, LCDC1_D14,
GPIO2_C1 = 0x2c10, LCDC0_D15, LCDC1_D15,
GPIO2_C2 = 0x2c20, LCDC0_D16, LCDC1_D16,
GPIO2_C3 = 0x2c30, LCDC0_D17, LCDC1_D17,
GPIO2_C4 = 0x2c40, LCDC0_D18, LCDC1_D18, I2C2_SDA,
GPIO2_C5 = 0x2c50, LCDC0_D19, LCDC1_D19, I2C2_SCL,
GPIO2_C6 = 0x2c60, LCDC0_D20, LCDC1_D20, UART2_SIN,
GPIO2_C7 = 0x2c70, LCDC0_D21, LCDC1_D21, UART2_SOUT,
/* GPIO2_D */
GPIO2_D0 = 0x2d00, LCDC0_D22, LCDC1_D22,
GPIO2_D1 = 0x2d10, LCDC0_D23, LCDC1_D23,
/* GPIO3_A */
/* GPIO3_B */
/* GPIO3_C */
GPIO3_C1 = 0x3c10, OTG_DRVVBUS,
/* GPIO3_D */
GPIO3_D7 = 0x3d70, TEST_CLK_OUT,
};
void __init iomux_init(void);
#endif

2
arch/arm/mach-rk2928/include/mach/iomux.h
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@@ -17,7 +17,7 @@
#define __RK2928_IOMUX_H__
#include <linux/init.h>
#include <mach/iomux-rk2928.h>
//gpio0a
#define GPIO0A_GPIO0A0 0
#define GPIO0A_I2C0_SCL 1

57
arch/arm/mach-rk2928/iomux.c
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@@ -23,6 +23,60 @@
#include <mach/iomux.h>
#include <mach/gpio.h>
/******************** new iomux ********************/
static unsigned int default_mode[] = {
#if defined(CONFIG_UART0_RK29) || (CONFIG_RK_DEBUG_UART == 0)
UART0_SOUT, UART0_SIN,
#ifdef CONFIG_UART0_CTS_RTS_RK29
UART0_RTSN, UART0_CTSN,
#endif
#endif
#if defined(CONFIG_UART1_RK29) || (CONFIG_RK_DEBUG_UART == 1)
UART1_SIN, UART1_SOUT,
#ifdef CONFIG_UART1_CTS_RTS_RK29
UART1_CTSN, UART1_RTSN,
#endif
#endif
#if defined(CONFIG_UART2_RK29) || (CONFIG_RK_DEBUG_UART == 2)
UART2_SIN, UART2_SOUT,
#ifdef CONFIG_UART2_CTS_RTS_RK29
UART2_RTSN, UART2_CTSN,
#endif
#endif
#ifdef CONFIG_SPIM0_RK29
SPI0_CLK, SPI0_TXD, SPI0_RXD, SPI0_CSN0,
#endif
#ifdef CONFIG_I2C0_RK30
I2C0_SCL, I2C0_SDA,
#endif
#ifdef CONFIG_I2C1_RK30
I2C1_SCL, I2C1_SDA,
#endif
#ifdef CONFIG_I2C2_RK30
I2C2_SDA, I2C2_SCL,
#endif
#ifdef CONFIG_I2C3_RK30
I2C3_SDA, I2C3_SCL,
#endif
};
void __init iomux_init(void)
{
int i, len;
len = ARRAY_SIZE(default_mode);
for(i = 0; i < len; i++)
iomux_set(default_mode[i]);
return;
}
/***************************************************/
//#define IOMUX_DBG
#define INVALID_MUX "invalid"
static struct mux_config rk30_muxs[] = {
@@ -215,6 +269,9 @@ int __init rk2928_iomux_init(void)
{
int i;
printk("%s\n",__func__);
iomux_init();
for(i=0;i<ARRAY_SIZE(rk30_muxs);i++)
{
if(rk30_muxs[i].flags != DEFAULT)

367
arch/arm/mach-rk30/include/mach/iomux-rk30.h Normal file
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@@ -0,0 +1,367 @@
#ifndef __MACH_RK30_IOMUX_H
#define __MACH_RK30_IOMUX_H
#include <mach/io.h>
#include <plat/iomux.h>
#if defined(CONFIG_ARCH_RK30)
#define GRF_IOMUX_BASE (RK30_GRF_BASE + 0x00a8)
#define GPIO_BANKS 7
enum{
/* GPIO0_A */
GPIO0_A0 = 0x0a00, HDMI_HOTPLUGIN,
GPIO0_A1 = 0x0a10, HDMI_DDCSCL,
GPIO0_A2 = 0x0a20, HDMI_DDCSDA,
GPIO0_A3 = 0x0a30, PWM0,
GPIO0_A4 = 0x0a40, PWM1,
GPIO0_A5 = 0x0a50, OTG_DRV_VBUS,
GPIO0_A6 = 0x0a60, HOST_DRV_VBUS,
GPIO0_A7 = 0x0a70, I2S0_SDI,
/* GPIO0_B */
GPIO0_B0 = 0x0b00, I2S0_CLK,
GPIO0_B1 = 0x0b10, I2S0_SCLK,
GPIO0_B2 = 0x0b20, I2S0_LRCKRX,
GPIO0_B3 = 0x0b30, I2S0_LRCKTX,
GPIO0_B4 = 0x0b40, I2S0_SDO0,
GPIO0_B5 = 0x0b50, I2S0_SDO1,
GPIO0_B6 = 0x0b60, I2S0_SDO2,
GPIO0_B7 = 0x0b70, I2S0_SDO3,
/* GPIO0_C */
GPIO0_C0 = 0x0c00, I2S1_CLK,
GPIO0_C1 = 0x0c10, I2S1_SCLK,
GPIO0_C2 = 0x0c20, I2S1_LRCKRX,
GPIO0_C3 = 0x0c30, I2S1_LRCKTX,
GPIO0_C4 = 0x0c40, I2S1_SDI,
GPIO0_C5 = 0x0c50, I2S1_SDO,
GPIO0_C6 = 0x0c60, TRACE_CLK, SMC_R2,
GPIO0_C7 = 0x0c70, TRACE_CTL, SMC_R3,
/* GPIO0_D */
GPIO0_D0 = 0x0d00, I2S2_CLK, SMC_CS0,
GPIO0_D1 = 0x0d10, I2S2_SCLK, SMC_WEN,
GPIO0_D2 = 0x0d20, I2S2_LRCKRX, SMC_OEN,
GPIO0_D3 = 0x0d30, I2S2_LRCKTX, SMC_ADVN,
GPIO0_D4 = 0x0d40, I2S2_SDI, SMC_R0,
GPIO0_D5 = 0x0d50, I2S2_SDO, SMC_R1,
GPIO0_D6 = 0x0d60, PWM2,
GPIO0_D7 = 0x0d70, PWM3,
/* GPIO1_A */
GPIO1_A0 = 0x1a00, UART0_SIN,
GPIO1_A1 = 0x1a10, UART0_SOUT,
GPIO1_A2 = 0x1a20, UART0_CTSN,
GPIO1_A3 = 0x1a30, UART0_RTSN,
GPIO1_A4 = 0x1a40, UART1_SIN, SPI0_CS0,
GPIO1_A5 = 0x1a50, UART1_SOUT, SPI0_CLK,
GPIO1_A6 = 0x1a60, UART1_CTSN, SPI0_RXD,
GPIO1_A7 = 0x1a70, UART1_RTSN, SPI0_TXD,
/* GPIO1_B */
GPIO1_B0 = 0x1b00, UART2_SIN,
GPIO1_B1 = 0x1b10, UART2_SOUT,
GPIO1_B2 = 0x1b20, SPDIF_TX,
GPIO1_B3 = 0x1b30, CIF0_CLKOUT,
GPIO1_B4 = 0x1b40, CIF0_D0,
GPIO1_B5 = 0x1b50, CIF0_D1,
GPIO1_B6 = 0x1b60, CIF0_D10,
GPIO1_B7 = 0x1b70, CIF0_D11,
/* GPIO1_C */
GPIO1_C0 = 0x1c00, CIF1_D2, RMII_CLKOUT, RMII_CLKIN,
GPIO1_C1 = 0x1c10, CIF1_D3, RMII_TXEN,
GPIO1_C2 = 0x1c20, CIF1_D4, RMII_TXD1,
GPIO1_C3 = 0x1c30, CIF1_D5, RMII_TXD0,
GPIO1_C4 = 0x1c40, CIF1_D6, RMII_RXERR,
GPIO1_C5 = 0x1c50, CIF1_D7, RMII_CRS,
GPIO1_C6 = 0x1c60, CIF1_D8, RMII_RXD1,
GPIO1_C7 = 0x1c70, CIF1_D9, RMII_RXD0,
/* GPIO1_D */
GPIO1_D0 = 0x1d00, CIF1_VSYNC, RMII_MD,
GPIO1_D1 = 0x1d10, CIF1_HREF, RMII_MDCLK,
GPIO1_D2 = 0x1d20, CIF1_CLKIN,
GPIO1_D3 = 0x1d30, CIF1_D0,
GPIO1_D4 = 0x1d40, CIF1_D1,
GPIO1_D5 = 0x1d50, CIF1_D10,
GPIO1_D6 = 0x1d60, CIF1_D11,
GPIO1_D7 = 0x1d70, CIF1_CLKOUT,
/* GPIO2_A */
GPIO2_A0 = 0x2a00, LCDC1_D0, SMC_R4,
GPIO2_A1 = 0x2a10, LCDC1_D1, SMC_R5,
GPIO2_A2 = 0x2a20, LCDC1_D2, SMC_R6,
GPIO2_A3 = 0x2a30, LCDC1_D3, SMC_R7,
GPIO2_A4 = 0x2a40, LCDC1_D4, SMC_R8,
GPIO2_A5 = 0x2a50, LCDC1_D5, SMC_R9,
GPIO2_A6 = 0x2a60, LCDC1_D6, SMC_R10,
GPIO2_A7 = 0x2a70, LCDC1_D7, SMC_R11,
/* GPIO2_B */
GPIO2_B0 = 0x2b00, LCDC1_D8, SMC_R12,
GPIO2_B1 = 0x2b10, LCDC1_D9, SMC_R13,
GPIO2_B2 = 0x2b20, LCDC1_D10, SMC_R14,
GPIO2_B3 = 0x2b30, LCDC1_D11, SMC_R15,
GPIO2_B4 = 0x2b40, LCDC1_D12, SMC_R16, HSADC_D9,
GPIO2_B5 = 0x2b50, LCDC1_D13, SMC_R17, HSADC_D8,
GPIO2_B6 = 0x2b60, LCDC1_D14, SMC_R18, TS_SYNC,
GPIO2_B7 = 0x2b70, LCDC1_D15, SMC_R19, HSADC_D7,
/* GPIO2_C */
GPIO2_C0 = 0x2c00, LCDC1_D16, GPS_CLK, HSADC_CLKOUT,
GPIO2_C1 = 0x2c10, LCDC1_D17, SMC_BLSN0, HSADC_D6,
GPIO2_C2 = 0x2c20, LCDC1_D18, SMC_BLSN1, HSADC_D5,
GPIO2_C3 = 0x2c30, LCDC1_D19, SPI1_CLK, HSADC_D0,
GPIO2_C4 = 0x2c40, LCDC1_D20, SPI1_CS0, HSADC_D1,
GPIO2_C5 = 0x2c50, LCDC1_D21, SPI1_TXD, HSADC_D2,
GPIO2_C6 = 0x2c60, LCDC1_D22, SPI1_RXD, HSADC_D3,
GPIO2_C7 = 0x2c70, LCDC1_D23, SPI1_CS1, HSADC_D4,
/* GPIO2_D */
GPIO2_D0 = 0x2d00, LCDC1_DCLK,
GPIO2_D1 = 0x2d10, LCDC1_DEN, SMC_CS1,
GPIO2_D2 = 0x2d20, LCDC1_HSYNC,
GPIO2_D3 = 0x2d30, LCDC1_VSYNC,
GPIO2_D4 = 0x2d40, I2C0_SDA,
GPIO2_D5 = 0x2d50, I2C0_SCL,
GPIO2_D6 = 0x2d60, I2C1_SDA,
GPIO2_D7 = 0x2d70, I2C1_SCL,
/* GPIO3_A */
GPIO3_A0 = 0x3a00, I2C2_SDA,
GPIO3_A1 = 0x3a10, I2C2_SCL,
GPIO3_A2 = 0x3a20, I2C3_SDA,
GPIO3_A3 = 0x3a30, I2C3_SCL,
GPIO3_A4 = 0x3a40, I2C4_SDA,
GPIO3_A5 = 0x3a50, I2C4_SCL,
GPIO3_A6 = 0x3a60, MMC0_RSTNOUT,
GPIO3_A7 = 0x3a70, MMC0_PWREN,
/* GPIO3_B */
GPIO3_B0 = 0x3b00, MMC0_CLKOUT,
GPIO3_B1 = 0x3b10, MMC0_CMD,
GPIO3_B2 = 0x3b20, MMC0_D0,
GPIO3_B3 = 0x3b30, MMC0_D1,
GPIO3_B4 = 0x3b40, MMC0_D2,
GPIO3_B5 = 0x3b50, MMC0_D3,
GPIO3_B6 = 0x3b60, MMC0_DETN,
GPIO3_B7 = 0x3b70, MMC0_WRPRT,
/* GPIO3_C */
GPIO3_C0 = 0x3c00, MMC1_CMD,
GPIO3_C1 = 0x3c10, MMC1_D0,
GPIO3_C2 = 0x3c20, MMC1_D1,
GPIO3_C3 = 0x3c30, MMC1_D2,
GPIO3_C4 = 0x3c40, MMC1_D3,
GPIO3_C5 = 0x3c50, MMC1_CLKOUT,
GPIO3_C6 = 0x3c60, MMC1_DETN,
GPIO3_C7 = 0x3c70, MMC1_WRPRT,
/* GPIO3_D */
GPIO3_D0 = 0x3d00, MMC1_PWREN,
GPIO3_D1 = 0x3d10, MMC1_BKEPWR,
GPIO3_D2 = 0x3d20, MMC1_INTN,
GPIO3_D3 = 0x3d30, UART3_SIN,
GPIO3_D4 = 0x3d40, UART3_SOUT,
GPIO3_D5 = 0x3d50, UART3_CTSN,
GPIO3_D6 = 0x3d60, UART3_RTSN,
GPIO3_D7 = 0x3d70, NAND_DQS, EMMC_CLKOUT,
/* GPIO4_A */
GPIO4_A0 = 0x4a00, NAND_D8,
GPIO4_A1 = 0x4a10, NAND_D9,
GPIO4_A2 = 0x4a20, NAND_D10,
GPIO4_A3 = 0x4a30, NAND_D11,
GPIO4_A4 = 0x4a40, NAND_D12,
GPIO4_A5 = 0x4a50, NAND_D13,
GPIO4_A6 = 0x4a60, NAND_D14,
GPIO4_A7 = 0x4a70, NAND_D15,
/* GPIO4_B */
GPIO4_B0 = 0x4b00, NAND_CS1,
GPIO4_B1 = 0x4b10, NAND_CS2, EMMC_CMD,
GPIO4_B2 = 0x4b20, NAND_CS3, EMMC_RSTNOUT,
GPIO4_B3 = 0x4b30, NAND_CS4,
GPIO4_B4 = 0x4b40, NAND_CS5,
GPIO4_B5 = 0x4b50, NAND_CS6,
GPIO4_B6 = 0x4b60, NAND_CS7,
GPIO4_B7 = 0x4b70, SPI0_CS1,
/* GPIO4_C */
GPIO4_C0 = 0x4c00, SMC_D0, TRACE_D0,
GPIO4_C1 = 0x4c10, SMC_D1, TRACE_D1,
GPIO4_C2 = 0x4c20, SMC_D2, TRACE_D2,
GPIO4_C3 = 0x4c30, SMC_D3, TRACE_D3,
GPIO4_C4 = 0x4c40, SMC_D4, TRACE_D4,
GPIO4_C5 = 0x4c50, SMC_D5, TRACE_D5,
GPIO4_C6 = 0x4c60, SMC_D6, TRACE_D6,
GPIO4_C7 = 0x4c70, SMC_D7, TRACE_D7,
/* GPIO4_D */
GPIO4_D0 = 0x4d00, SMC_D8, TRACE_D8,
GPIO4_D1 = 0x4d10, SMC_D9, TRACE_D9,
GPIO4_D2 = 0x4d20, SMC_D10, TRACE_D10,
GPIO4_D3 = 0x4d30, SMC_D11, TRACE_D11,
GPIO4_D4 = 0x4d40, SMC_D12, TRACE_D12,
GPIO4_D5 = 0x4d50, SMC_D13, TRACE_D13,
GPIO4_D6 = 0x4d60, SMC_D14, TRACE_D14,
GPIO4_D7 = 0x4d70, SMC_D15, TRACE_D15,
/* GPIO6_A */
/* GPIO6_B */
GPIO6_B7 = 0x6b70, TEST_CLOCK_OUT,
/* GPIO6_C */
/* GPIO6_D */
};
#elif defined(CONFIG_ARCH_RK3066B)
#define GRF_IOMUX_BASE (RK3066B_GRF_BASE + 0x0060)
#define GPIO_BANKS 4
enum{
/* GPIO0_A */
/* GPIO0_B */
/* GPIO0_C */
GPIO0_C0 = 0x0c00, NAND_D8,
GPIO0_C1 = 0x0c10, NAND_D9,
GPIO0_C2 = 0x0c20, NAND_D10,
GPIO0_C3 = 0x0c30, NAND_D11,
GPIO0_C4 = 0x0c40, NAND_D12,
GPIO0_C5 = 0x0c50, NAND_D13,
GPIO0_C6 = 0x0c60, NAND_D14,
GPIO0_C7 = 0x0c70, NAND_D15,
/* GPIO0_D */
GPIO0_D0 = 0x0d00, NAND_DQS, EMMC_CLKOUT,
GPIO0_D1 = 0x0d10, NAND_CS1,
GPIO0_D2 = 0x0d20, NAND_CS2, EMMC_CMD,
GPIO0_D3 = 0x0d30, NAND_CS3, EMMC_RSTNOUT,
GPIO0_D4 = 0x0d40, SPI1_RXD,
GPIO0_D5 = 0x0d50, SPI1_TXD,
GPIO0_D6 = 0x0d60, SPI1_CLK,
GPIO0_D7 = 0x0d70, SPI1_CS0,
/* GPIO1_A */
GPIO1_A0 = 0x1a00, UART0_SIN,
GPIO1_A1 = 0x1a10, UART0_SOUT,
GPIO1_A2 = 0x1a20, UART0_CTSN,
GPIO1_A3 = 0x1a30, UART0_RTSN,
GPIO1_A4 = 0x1a40, UART1_SIN, SPI0_RXD,
GPIO1_A5 = 0x1a50, UART1_SOUT, SPI0_TXD,
GPIO1_A6 = 0x1a60, UART1_CTSN, SPI0_CLK,
GPIO1_A7 = 0x1a70, UART1_RTSN, SPI0_CS0,
/* GPIO1_B */
GPIO1_B0 = 0x1b00, UART2_SIN, JTAG_TDI,
GPIO1_B1 = 0x1b10, UART2_SOUT, JTAG_TDO,
GPIO1_B2 = 0x1b20, UART3_SIN, GPS_MAG,
GPIO1_B3 = 0x1b30, UART3_SOUT, GPS_SIG,
GPIO1_B4 = 0x1b40, UART3_CTSN, GPS_RFCLK,
GPIO1_B5 = 0x1b50, UART3_RTSN,
GPIO1_B6 = 0x1b60, SPDIF_TX, SPI1_CS1,
GPIO1_B7 = 0x1b70, SPI0_CS1,
/* GPIO1_C */
GPIO1_C0 = 0x1c00, I2S0_CLK,
GPIO1_C1 = 0x1c10, I2S0_SCLK,
GPIO1_C2 = 0x1c20, I2S0_LRCLKRX,
GPIO1_C3 = 0x1c30, I2S0_LRCKTX,
GPIO1_C4 = 0x1c40, I2S0_SDI,
GPIO1_C5 = 0x1c50, I2S0_SDO,
/* GPIO1_D */
GPIO1_D0 = 0x1d00, I2C0_SDA,
GPIO1_D1 = 0x1d10, I2C0_SCL,
GPIO1_D2 = 0x1d20, I2C1_SDA,
GPIO1_D3 = 0x1d30, I2C1_SCL,
GPIO1_D4 = 0x1d40, I2C2_SDA,
GPIO1_D5 = 0x1d50, I2C2_SCL,
GPIO1_D6 = 0x1d60, I2C4_SDA,
GPIO1_D7 = 0x1d70, I2C4_SCL,
/* GPIO2_A */
GPIO2_A0 = 0x2a00, LCDC1_D0, SMC_D0, TRACE_D0,
GPIO2_A1 = 0x2a10, LCDC1_D1, SMC_D1, TRACE_D1,
GPIO2_A2 = 0x2a20, LCDC1_D2, SMC_D2, TRACE_D2,
GPIO2_A3 = 0x2a30, LCDC1_D3, SMC_D3, TRACE_D3,
GPIO2_A4 = 0x2a40, LCDC1_D4, SMC_D4, TRACE_D4,
GPIO2_A5 = 0x2a50, LCDC1_D5, SMC_D5, TRACE_D5,
GPIO2_A6 = 0x2a60, LCDC1_D6, SMC_D6, TRACE_D6,
GPIO2_A7 = 0x2a70, LCDC1_D7, SMC_D7, TRACE_D7,
/* GPIO2_B */
GPIO2_B0 = 0x2b00, LCDC1_D8, SMC_D8, TRACE_D8,
GPIO2_B1 = 0x2b10, LCDC1_D9, SMC_D9, TRACE_D9,
GPIO2_B2 = 0x2b20, LCDC1_D10, SMC_D10, TRACE_D10,
GPIO2_B3 = 0x2b30, LCDC1_D11, SMC_D11, TRACE_D11,
GPIO2_B4 = 0x2b40, LCDC1_D12, SMC_D12, TRACE_D12,
GPIO2_B5 = 0x2b50, LCDC1_D13, SMC_D13, TRACE_D13,
GPIO2_B6 = 0x2b60, LCDC1_D14, SMC_D14, TRACE_D14,
GPIO2_B7 = 0x2b70, LCDC1_D15, SMC_D15, TRACE_D15,
/* GPIO2_C */
GPIO2_C0 = 0x2c00, LCDC1_D16, SMC_R0, TRACE_CLK,
GPIO2_C1 = 0x2c10, LCDC1_D17, SMC_R1, TRACE_CTL,
GPIO2_C2 = 0x2c20, LCDC1_D18, SMC_R2,
GPIO2_C3 = 0x2c30, LCDC1_D19, SMC_R3,
GPIO2_C4 = 0x2c40, LCDC1_D20, SMC_R4,
GPIO2_C5 = 0x2c50, LCDC1_D21, SMC_R5,
GPIO2_C6 = 0x2c60, LCDC1_D22, SMC_R6,
GPIO2_C7 = 0x2c70, LCDC1_D23, SMC_R7,
/* GPIO2_D */
GPIO2_D0 = 0x2d00, LCDC1_DCLK, SMC_CS0,
GPIO2_D1 = 0x2d10, LCDC1_DEN, SMC_WEN,
GPIO2_D2 = 0x2d20, LCDC1_HSYNC, SMC_OEN,
GPIO2_D3 = 0x2d30, LCDC1_VSYNC, SMC_ADVN,
GPIO2_D4 = 0x2d40, SMC_BLSN0,
GPIO2_D5 = 0x2d50, SMC_BLSN1,
GPIO2_D6 = 0x2d60, SMC_CS1,
GPIO2_D7 = 0x2d70, TEST_CLOCK_OUT,
/* GPIO3_A */
GPIO3_A0 = 0x3a00, MMC0_RSTNOUT,
GPIO3_A1 = 0x3a10, MMC0_PWREN,
GPIO3_A2 = 0x3a20, MMC0_CLKOUT,
GPIO3_A3 = 0x3a30, MMC0_CMD,
GPIO3_A4 = 0x3a40, MMC0_D0,
GPIO3_A5 = 0x3a50, MMC0_D1,
GPIO3_A6 = 0x3a60, MMC0_D2,
GPIO3_A7 = 0x3a70, MMC0_D3,
/* GPIO3_B */
GPIO3_B0 = 0x3b00, MMC0_DETN,
GPIO3_B1 = 0x3b10, MMC0_WRPRT,
GPIO3_B3 = 0x3b30, CIF0_CLKOUT,
GPIO3_B4 = 0x3b40, CIF0_D0, HSADC_D8,
GPIO3_B5 = 0x3b50, CIF0_D1, HSADC_D9,
GPIO3_B6 = 0x3b60, CIF0_D10, I2C3_SDA,
GPIO3_B7 = 0x3b70, CIF0_D11, I2C3_SCL,
/* GPIO3_C */
GPIO3_C0 = 0x3c00, MMC1_CMD, RMII_TXEN,
GPIO3_C1 = 0x3c10, MMC1_D0, RMII_TXD1,
GPIO3_C2 = 0x3c20, MMC1_D1, RMII_TXD0,
GPIO3_C3 = 0x3c30, MMC1_D2, RMII_RXD0,
GPIO3_C4 = 0x3c40, MMC1_D3, RMII_RXD1,
GPIO3_C5 = 0x3c50, MMC1_CLKOUT, RMII_CLKOUT, RMII_CLKIN,
GPIO3_C6 = 0x3c60, MMC1_DETN, RMII_RXERR,
GPIO3_C7 = 0x3c70, MMC1_WRPRT, RMII_CRS,
/* GPIO3_D */
GPIO3_D0 = 0x3d00, MMC1_PWREN, RMII_MD,
GPIO3_D1 = 0x3d10, MMC1_BKEPWR, RMII_MDCLK,
GPIO3_D2 = 0x3d20, MMC1_INTN,
GPIO3_D3 = 0x3d30, PWM0,
GPIO3_D4 = 0x3d40, PWM1, JTAG_TRSTN,
GPIO3_D5 = 0x3d50, PWM2, JTAG_TCK, OTG_DRV_VBUS,
GPIO3_D6 = 0x3d60, PWM3, JTAG_TMS, HOST_DRV_VBUS,
};
#else
#endif
void __init iomux_init(void);
#endif

2
arch/arm/mach-rk30/include/mach/iomux.h
View File

@@ -2,7 +2,7 @@
#define __MACH_IOMUX_H__
#include <linux/init.h>
#include <mach/iomux-rk30.h>
#if defined(CONFIG_ARCH_RK3066B)
#include <mach/iomux-rk3066b.h>
#elif defined(CONFIG_ARCH_RK30)

74
arch/arm/mach-rk30/iomux.c
View File

@@ -20,6 +20,77 @@
#include <mach/io.h>
#include <mach/iomux.h>
/******************** new iomux ********************/
static unsigned int default_mode[] = {
#if defined(CONFIG_UART0_RK29) || (CONFIG_RK_DEBUG_UART == 0)
UART0_SOUT, UART0_SIN,
#ifdef CONFIG_UART0_CTS_RTS_RK29
UART0_RTSN, UART0_CTSN,
#endif
#endif
#if defined(CONFIG_UART1_RK29) || (CONFIG_RK_DEBUG_UART == 1)
UART1_SIN, UART1_SOUT,
#ifdef CONFIG_UART1_CTS_RTS_RK29
UART1_CTSN, UART1_RTSN,
#endif
#endif
#if defined(CONFIG_UART2_RK29) || (CONFIG_RK_DEBUG_UART == 2)
UART2_SIN, UART2_SOUT,
#endif
#if defined(CONFIG_UART3_RK29) || (CONFIG_RK_DEBUG_UART == 3)
UART3_SIN, UART3_SOUT,
#endif
#ifdef CONFIG_SPIM0_RK29
SPI0_CLK, SPI0_TXD, SPI0_RXD, SPI0_CSN0,
#endif
#ifdef CONFIG_SPIM1_RK29
SPI1_CLK, SPI1_TXD, SPI1_RXD, SPI1_CSN0,
#endif
#ifdef CONFIG_I2C0_RK30
I2C0_SCL, I2C0_SDA,
#endif
#ifdef CONFIG_I2C1_RK30
I2C1_SCL, I2C1_SDA,
#endif
#ifdef CONFIG_I2C2_RK30
I2C2_SDA, I2C2_SCL,
#endif
#ifdef CONFIG_I2C3_RK30
I2C3_SDA, I2C3_SCL,
#endif
#ifdef CONFIG_I2C4_RK30
I2C4_SDA, I2C4_SCL,
#endif
#ifdef CONFIG_RK30_VMAC
RMII_CLKOUT, RMII_TXEN, RMII_TXD1, RMII_TXD0, RMII_RXERR,
RMII_CRS, RMII_RXD1, RMII_RXD0, RMII_MD, RMII_MDCLK,
#endif
};
void __init iomux_init(void)
{
int i, len;
len = ARRAY_SIZE(default_mode);
for(i = 0; i < len; i++)
iomux_set(default_mode[i]);
return;
}
/***************************************************/
//#define IOMUX_DBG
#if defined(CONFIG_ARCH_RK3066B)
@@ -259,6 +330,9 @@ int __init rk30_iomux_init(void)
{
int i;
printk("%s\n",__func__);
iomux_init();
for(i=0;i<ARRAY_SIZE(rk30_muxs);i++)
{
if(rk30_muxs[i].flags != DEFAULT)

1
arch/arm/plat-rk/Makefile
View File

@@ -10,6 +10,7 @@ obj-$(CONFIG_RK_EARLY_PRINTK) += early_printk.o ../kernel/debug.o
obj-y += mem_reserve.o
obj-y += config.o
obj-y += sram.o
obj-y += iomux.o
CFLAGS_sram.o += -mthumb
obj-$(CONFIG_DDR_TEST) += memtester.o ddr_test.o
obj-$(CONFIG_DDR_FREQ) += ddr_freq.o

11
arch/arm/plat-rk/include/plat/iomux.h Normal file
View File

@@ -0,0 +1,11 @@
#ifndef __PLAT_IOMUX_H
#define __PLAT_IOMUX_H
#define INVALID_MODE 0xffffffff
int gpio_to_mode(int gpio);
int mode_to_gpio(unsigned int mode);
void iomux_set_gpio_mode(int gpio);
void iomux_set(unsigned int mode);
#endif

116
arch/arm/plat-rk/iomux.c Normal file
View File

@@ -0,0 +1,116 @@
#include <linux/init.h>
#include <linux/module.h>
#include <mach/iomux.h>
#include <mach/gpio.h>
#include <asm/io.h>
#if 0
#define DBG(x...) INFO(KERN_INFO x)
#else
#define DBG(x...)
#endif
#define INFO(x...) printk(KERN_INFO x)
struct iomux_mode{
unsigned int mode:4,
off:4,
goff:4,
bank:4,
reserve:16;
};
struct union_mode{
union{
struct iomux_mode mux;
unsigned int mode;
};
};
static inline int mode_is_valid(unsigned int mode)
{
struct union_mode m;
m.mode = mode;
if(mode == INVALID_MODE || m.mux.bank >= GPIO_BANKS)
return 0;
else
return 1;
}
int mode_to_gpio(unsigned int mode)
{
struct union_mode m;
if(!mode_is_valid(mode)){
INFO("<%s> mode(0x%x) is invalid\n", __func__, mode);
return INVALID_GPIO;
}
m.mode = mode;
return PIN_BASE + m.mux.bank * 32 + (m.mux.goff - 0x0A) * 8 + m.mux.off;
}
int gpio_to_mode(int gpio)
{
unsigned int off;
struct union_mode m;
if(!gpio_is_valid(gpio)){
INFO("<%s> gpio(%d), is invalid\n", __func__, gpio);
return INVALID_MODE;
}
off = gpio - PIN_BASE;
m.mux.bank = off/32;
m.mux.goff = (off%32)/8 + 0x0A;
m.mux.off = off%256;
if(!mode_is_valid(m.mode)){
INFO("<%s> gpio(gpio%d_%x%d) is invalid\n", __func__, m.mux.bank, m.mux.goff, m.mux.off);
return INVALID_MODE;
}
return m.mode;
}
#ifdef GRF_IOMUX_BASE
void iomux_set(unsigned int mode)
{
unsigned int v, addr, mask;
struct union_mode m;
m.mode = mode;
if(!mode_is_valid(mode)){
INFO("<%s> mode(0x%x) is invalid\n", __func__, mode);
return;
}
mask = (m.mux.mode < 2)?1:3;
v = (m.mux.mode << (m.mux.off * 2)) + (mask << (m.mux.off * 2 + 16));
addr = (unsigned int)GRF_IOMUX_BASE + 16 * m.mux.bank + 4 * (m.mux.goff - 0x0A);
DBG("<%s> mode(0x%04x), reg_addr(0x%08x), set_value(0x%08x)\n", __func__, mode, addr, v);
writel_relaxed(v, (void *)addr);
}
#else
void iomux_set(unsigned int mode)
{
INFO("%s is not support\n", __func__);
return;
}
#endif
EXPORT_SYMBOL(iomux_set);
void iomux_set_gpio_mode(int gpio)
{
unsigned int mode;
mode = gpio_to_mode(gpio);
if(mode_is_valid(mode))
iomux_set(mode);
}
EXPORT_SYMBOL(iomux_set_gpio_mode);

5
drivers/gpio/gpio-rk30.c
View File

@@ -308,9 +308,8 @@ static int rk30_gpiolib_request(struct gpio_chip *chip, unsigned offset)
struct rk30_gpio_bank *bank = to_rk30_gpio_bank(chip);
int gpio = offset + PIN_BASE + bank->id * 32;
#ifdef CONFIG_ARCH_RK2928
gpio_set_iomux(gpio);
#endif
iomux_set_gpio_mode(gpio);
return 0;
}