From 88ec34820f793bc1026aac2c35e41a23f71a2957 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 28 May 2018 16:56:50 +0800 Subject: [PATCH] clk: rockchip: fix up the frac clk get rate error support fractional divider with only one level parent clock Change-Id: I6593f908edf4454ef03255080bf9ac1d72c6f64e Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index c9052c4f8606..15419bbb0ccb 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -166,11 +166,16 @@ static void rockchip_fractional_approximation(struct clk_hw *hw, if (((rate * 20 > p_rate) && (p_rate % rate != 0)) || (fd->max_prate && fd->max_prate < p_rate)) { p_parent = clk_hw_get_parent(clk_hw_get_parent(hw)); - p_parent_rate = clk_hw_get_rate(p_parent); - *parent_rate = p_parent_rate; - if (fd->max_prate && p_parent_rate > fd->max_prate) { - div = DIV_ROUND_UP(p_parent_rate, fd->max_prate); - *parent_rate = p_parent_rate / div; + if (!p_parent) { + *parent_rate = p_rate; + } else { + p_parent_rate = clk_hw_get_rate(p_parent); + *parent_rate = p_parent_rate; + if (fd->max_prate && p_parent_rate > fd->max_prate) { + div = DIV_ROUND_UP(p_parent_rate, + fd->max_prate); + *parent_rate = p_parent_rate / div; + } } if (*parent_rate < rate * 20) {