From 8974a80274950eaf6367f2488717e35e99057faf Mon Sep 17 00:00:00 2001 From: Mark Yao Date: Wed, 1 Sep 2021 08:56:17 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3399: add dclk pll sources Change-Id: I0e29d67d5e3738b18a7407a049d216f8dcebb8e8 Signed-off-by: Mark Yao Signed-off-by: Jianqun Xu --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index c17195d9366b..0dc4b082ba38 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -172,6 +172,8 @@ display_subsystem: display-subsystem { compatible = "rockchip,display-subsystem"; ports = <&vopl_out>, <&vopb_out>; + clocks = <&cru PLL_VPLL>, <&cru PLL_CPLL>; + clock-names = "hdmi-tmds-pll", "default-vop-pll"; }; pmu_a53 { @@ -1803,8 +1805,8 @@ compatible = "rockchip,rk3399-vop-lit"; reg = <0x0 0xff8f0000 0x0 0x3efc>; interrupts = ; - clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>, <&cru DCLK_VOP1_DIV>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop", "dclk_source"; iommus = <&vopl_mmu>; power-domains = <&power RK3399_PD_VOPL>; resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; @@ -1869,8 +1871,8 @@ compatible = "rockchip,rk3399-vop-big"; reg = <0x0 0xff900000 0x0 0x3efc>; interrupts = ; - clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>, <&cru DCLK_VOP0_DIV>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop", "dclk_source"; iommus = <&vopb_mmu>; power-domains = <&power RK3399_PD_VOPB>; resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;