From 89b73666cb95684c695e179308e72f62dfcaab2e Mon Sep 17 00:00:00 2001 From: ckkim Date: Mon, 28 Feb 2022 16:52:41 +0900 Subject: [PATCH] ODROID-COMMON:HDMI HPLL clk accuracy Improvements (800x600p60hz) Signed-off-by: ckkim Change-Id: I46a743df83a05943b09a02ea5a7b5606ba404869 --- .../media/vout/hdmitx/hdmi_common/hdmi_parameters.c | 10 +++++----- .../amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_common/hdmi_parameters.c b/drivers/amlogic/media/vout/hdmitx/hdmi_common/hdmi_parameters.c index d951cb8d8bc6..b92c0b4b5a45 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_common/hdmi_parameters.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_common/hdmi_parameters.c @@ -1876,15 +1876,15 @@ static struct hdmi_format_para fmt_para_vesa_800x600p60_4x3 = { .progress_mode = 1, .scrambler_en = 0, .tmds_clk_div40 = 0, - .tmds_clk = 40000, + .tmds_clk = 39895, .timing = { #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON) - .pixel_freq = 40000, + .pixel_freq = 39895, #else .pixel_freq = 66666, #endif - .h_freq = 37879, - .v_freq = 60317, + .h_freq = 37780, + .v_freq = 60000, .vsync = 60, .vsync_polarity = 1, .hsync_polarity = 1, @@ -1913,7 +1913,7 @@ static struct hdmi_format_para fmt_para_vesa_800x600p60_4x3 = { .sync_duration_num = 60, .sync_duration_den = 1, #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON) - .video_clk = 40000000, + .video_clk = 39895000, #else .video_clk = 66666000, #endif diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c index d858c5eb96a4..0690da7eee98 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c @@ -861,7 +861,7 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = { {{HDMIV_800x600p60hz, HDMI_VIC_END}, #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON) - 3243240, 4, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1}, + 3191600, 4, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1}, #else 3200000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, #endif