From 89bdfb869629112385e75b5e595f4752396d2d94 Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Sat, 8 Jul 2023 00:21:47 +0800 Subject: [PATCH] ASoC: rockchip: sai: Handle clk enable in prepare stage Currently, the BCLK/FSYNC enable is addressed in hw_params stage, because the real clk is measured by samplerate. so, it is quite a good solution. But, on the system PM situation, it is failed to recovery BCLK/LRCK after resume. the root cause is that never do 'hw_params' after resume. which is similar to XRUN issue. So, let's move it to prepare stage which any path must do before trigger-start. Signed-off-by: Sugar Zhang Change-Id: I9025a98259a4e9bd9f09ec3d23584f753552031d --- sound/soc/rockchip/rockchip_sai.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/sound/soc/rockchip/rockchip_sai.c b/sound/soc/rockchip/rockchip_sai.c index b62e5ed19509..8c43150dd151 100644 --- a/sound/soc/rockchip/rockchip_sai.c +++ b/sound/soc/rockchip/rockchip_sai.c @@ -506,6 +506,17 @@ static int rockchip_sai_hw_params(struct snd_pcm_substream *substream, regmap_update_bits(sai->regmap, SAI_CKR, SAI_CKR_MDIV_MASK, SAI_CKR_MDIV(div_bclk)); + } + + return 0; +} + +static int rockchip_sai_prepare(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai); + + if (sai->is_master_mode) { /* * Should wait for one BCLK ready after DIV and then ungate * output clk to achieve the clean clk. @@ -628,6 +639,7 @@ static const struct snd_soc_dai_ops rockchip_sai_dai_ops = { .hw_params = rockchip_sai_hw_params, .set_sysclk = rockchip_sai_set_sysclk, .set_fmt = rockchip_sai_set_fmt, + .prepare = rockchip_sai_prepare, .trigger = rockchip_sai_trigger, .set_tdm_slot = rockchip_sai_set_tdm_slot, };