From 89f86b710111c2b623a5397b1ab2feaeec9c5976 Mon Sep 17 00:00:00 2001
From: Huibin Hong <huibin.hong@rock-chips.com>
Date: Thu, 21 Nov 2019 15:32:49 +0800
Subject: [PATCH] ARM: dts: rockchip: add en 2t mode for rk3128

Disable it default, because we found it is unstable when using
some ddr chip.

Change-Id: Iffd98a0f5ab9c9256ec9a1450ce105a5b7f6127b
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
---
 arch/arm/boot/dts/rk3128-dram-default-timing.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/rk3128-dram-default-timing.dtsi b/arch/arm/boot/dts/rk3128-dram-default-timing.dtsi
index 62e0d99589ef..6ba7b9b5b429 100644
--- a/arch/arm/boot/dts/rk3128-dram-default-timing.dtsi
+++ b/arch/arm/boot/dts/rk3128-dram-default-timing.dtsi
@@ -68,5 +68,6 @@
 		phy_lpddr2_clk_drv = <PHY_RON_44ohm>;
 		phy_lpddr2_cmd_drv = <PHY_RON_44ohm>;
 		phy_lpddr2_dqs_drv = <PHY_RON_44ohm>;
+		ddr_2t = <0>;
 	};
 };