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clk: rockchip: add clock controller for the RK3399

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Add the clock tree definition for the new RK3399 SoC.

Change-Id: I1d8755eb7c89bdc56b79644a96a7d3fd8e7fbc4b
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
This commit is contained in:
Xing Zheng
2016-02-29 16:55:07 +08:00
committed by Gerrit Code Review
parent 945ed51212
commit 89f93129bd
3 changed files with 1566 additions and 12 deletions
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1
drivers/clk/rockchip/Makefile
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@@ -15,3 +15,4 @@ obj-y += clk-rk3188.o
obj-y += clk-rk3288.o
obj-y += clk-rk3366.o
obj-y += clk-rk3368.o
obj-y += clk-rk3399.o

1543
drivers/clk/rockchip/clk-rk3399.c Normal file
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File diff suppressed because it is too large Load Diff

34
drivers/clk/rockchip/clk.h
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@@ -84,6 +84,28 @@ struct clk;
#define RK3368_EMMC_CON0 0x418
#define RK3368_EMMC_CON1 0x41c
#define RK3399_PLL_CON(x) RK2928_PLL_CON(x)
#define RK3399_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
#define RK3399_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
#define RK3399_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
#define RK3399_GLB_SRST_FST 0x500
#define RK3399_GLB_SRST_SND 0x504
#define RK3399_GLB_CNT_TH 0x508
#define RK3399_MISC_CON 0x50c
#define RK3399_RST_CON 0x510
#define RK3399_RST_ST 0x514
#define RK3399_SDMMC_CON0 0x580
#define RK3399_SDMMC_CON1 0x584
#define RK3399_SDIO_CON0 0x588
#define RK3399_SDIO_CON1 0x58c
#define RK3399_PMU_PLL_CON(x) RK2928_PLL_CON(x)
#define RK3399_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x80)
#define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
#define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
#define RK3399_PMU_RSTNHOLD_CON(x) ((x) * 0x4 + 0x120)
#define RK3399_PMU_GATEDIS_CON(x) ((x) * 0x4 + 0x130)
enum rockchip_pll_type {
pll_rk3036,
pll_rk3066,
@@ -121,18 +143,6 @@ enum rockchip_pll_type {
.nb = _nb, \
}
#define RK3399_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
_postdiv2, _dsmpd, _frac) \
{ \
.rate = _rate##U, \
.fbdiv = _fbdiv, \
.postdiv1 = _postdiv1, \
.refdiv = _refdiv, \
.postdiv2 = _postdiv2, \
.dsmpd = _dsmpd, \
.frac = _frac, \
}
/**
* struct rockchip_clk_provider - information about clock provider
* @reg_base: virtual address for the register base.