From 8a060a5c1359afdfe2c8c0b5b2c83f2065397094 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Wed, 12 May 2021 17:38:23 +0800 Subject: [PATCH] drm/rockchip: Add vop2 support Signed-off-by: Andy Yan Change-Id: I4c42d655f75903066888b6aea92e926192b000c2 --- drivers/gpu/drm/rockchip/Makefile | 3 +- drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 25 + drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 113 +++- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 550 ++++++++++++++++++- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 178 +++--- drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 10 +- drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 416 ++++++++++++++ 7 files changed, 1199 insertions(+), 96 deletions(-) diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile index 17a9e7eb2130..603d143c1401 100644 --- a/drivers/gpu/drm/rockchip/Makefile +++ b/drivers/gpu/drm/rockchip/Makefile @@ -4,7 +4,8 @@ # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \ - rockchip_drm_gem.o rockchip_drm_vop.o rockchip_vop_reg.o + rockchip_drm_gem.o rockchip_drm_vop.o rockchip_vop_reg.o \ + rockchip_drm_vop2.o rockchip_vop2_reg.o rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += rockchip_drm_fbdev.o rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c index 0f3eb392fe39..b32d625a790d 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c @@ -37,6 +37,31 @@ static bool is_support_iommu = true; static struct drm_driver rockchip_drm_driver; +int rockchip_register_crtc_funcs(struct drm_crtc *crtc, + const struct rockchip_crtc_funcs *crtc_funcs) +{ + int pipe = drm_crtc_index(crtc); + struct rockchip_drm_private *priv = crtc->dev->dev_private; + + if (pipe >= ROCKCHIP_MAX_CRTC) + return -EINVAL; + + priv->crtc_funcs[pipe] = crtc_funcs; + + return 0; +} + +void rockchip_unregister_crtc_funcs(struct drm_crtc *crtc) +{ + int pipe = drm_crtc_index(crtc); + struct rockchip_drm_private *priv = crtc->dev->dev_private; + + if (pipe >= ROCKCHIP_MAX_CRTC) + return; + + priv->crtc_funcs[pipe] = NULL; +} + /* * Attach a (component) device to the shared drm dma mapping from master drm * device. This is used by the VOPs to map GEM buffers to a common DMA diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h index 92cc7fe61ac7..9466abd8d5f7 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h @@ -12,13 +12,15 @@ #include #include #include - +#include #include #include #define ROCKCHIP_MAX_FB_BUFFER 3 #define ROCKCHIP_MAX_CONNECTOR 2 -#define ROCKCHIP_MAX_CRTC 2 +#define ROCKCHIP_MAX_CRTC 4 +#define ROCKCHIP_MAX_LAYER 16 + struct drm_device; struct drm_connector; @@ -38,6 +40,26 @@ struct iommu_domain; #define VOP_OUTPUT_IF_HDMI0 BIT(11) #define VOP_OUTPUT_IF_HDMI1 BIT(12) +struct rockchip_sdr2hdr_state { + int sdr2hdr_func; + + bool bt1886eotf_pre_conv_en; + bool rgb2rgb_pre_conv_en; + bool rgb2rgb_pre_conv_mode; + bool st2084oetf_pre_conv_en; + + bool bt1886eotf_post_conv_en; + bool rgb2rgb_post_conv_en; + bool rgb2rgb_post_conv_mode; + bool st2084oetf_post_conv_en; +}; + +struct rockchip_hdr_state { + bool pre_overlay; + bool hdr2sdr_en; + struct rockchip_sdr2hdr_state sdr2hdr_state; +}; + struct rockchip_crtc_state { struct drm_crtc_state base; int output_type; @@ -45,10 +67,79 @@ struct rockchip_crtc_state { int output_bpc; int output_flags; bool enable_afbc; + + struct drm_tv_connector_state *tv_state; + int left_margin; + int right_margin; + int top_margin; + int bottom_margin; + int vdisplay; + int afbdc_win_format; + int afbdc_win_width; + int afbdc_win_height; + int afbdc_win_ptr; + int afbdc_win_id; + int afbdc_en; + int afbdc_win_vir_width; + int afbdc_win_xoffset; + int afbdc_win_yoffset; + int dsp_layer_sel; + u32 output_if; + u32 bus_format; + u32 bus_flags; + int yuv_overlay; + int post_r2y_en; + int post_y2r_en; + int post_csc_mode; + int bcsh_en; + int color_space; + int eotf; + u8 mode_update; + struct rockchip_hdr_state hdr; }; + #define to_rockchip_crtc_state(s) \ container_of(s, struct rockchip_crtc_state, base) +struct rockchip_logo { + dma_addr_t dma_addr; + void *kvaddr; + phys_addr_t start; + phys_addr_t size; + int count; +}; + +struct loader_cubic_lut { + bool enable; + u32 offset; +}; + +/* + * Rockchip drm private crtc funcs. + * @loader_protect: protect loader logo crtc's power + * @enable_vblank: enable crtc vblank irq. + * @disable_vblank: disable crtc vblank irq. + * @bandwidth: report present crtc bandwidth consume. + */ +struct rockchip_crtc_funcs { + int (*loader_protect)(struct drm_crtc *crtc, bool on); + int (*enable_vblank)(struct drm_crtc *crtc); + void (*disable_vblank)(struct drm_crtc *crtc); + size_t (*bandwidth)(struct drm_crtc *crtc, + struct drm_crtc_state *crtc_state, + unsigned int *plane_num_total); + void (*cancel_pending_vblank)(struct drm_crtc *crtc, + struct drm_file *file_priv); + int (*debugfs_init)(struct drm_minor *minor, struct drm_crtc *crtc); + int (*debugfs_dump)(struct drm_crtc *crtc, struct seq_file *s); + void (*regs_dump)(struct drm_crtc *crtc, struct seq_file *s); + enum drm_mode_status (*mode_valid)(struct drm_crtc *crtc, + const struct drm_display_mode *mode, + int output_type); + void (*crtc_close)(struct drm_crtc *crtc); + void (*crtc_send_mcu_cmd)(struct drm_crtc *crtc, u32 type, u32 value); +}; + /* * Rockchip drm private structure. * @@ -64,6 +155,21 @@ struct rockchip_drm_private { struct drm_mm mm; struct list_head psr_list; struct mutex psr_list_lock; + + struct drm_property *eotf_prop; + struct drm_property *color_space_prop; + struct drm_property *global_alpha_prop; + struct drm_property *blend_mode_prop; + struct drm_property *alpha_scale_prop; + struct drm_property *async_commit_prop; + struct drm_property *share_id_prop; + struct drm_property *connector_id_prop; + + const struct rockchip_crtc_funcs *crtc_funcs[ROCKCHIP_MAX_CRTC]; + + dma_addr_t cubic_lut_dma_addr; + void *cubic_lut_kvaddr; + struct loader_cubic_lut cubic_lut[ROCKCHIP_MAX_CRTC]; }; int rockchip_drm_dma_attach_device(struct drm_device *drm_dev, @@ -71,6 +177,9 @@ int rockchip_drm_dma_attach_device(struct drm_device *drm_dev, void rockchip_drm_dma_detach_device(struct drm_device *drm_dev, struct device *dev); int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout); +int rockchip_register_crtc_funcs(struct drm_crtc *crtc, + const struct rockchip_crtc_funcs *crtc_funcs); +void rockchip_unregister_crtc_funcs(struct drm_crtc *crtc); int rockchip_drm_endpoint_is_subdriver(struct device_node *ep); extern struct platform_driver cdn_dp_driver; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 1929af368427..ad721fccc6aa 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -8,6 +8,7 @@ #define _ROCKCHIP_DRM_VOP_H #include +#include /* * major: IP major version, used for IP structure @@ -17,8 +18,26 @@ #define VOP_MAJOR(version) ((version) >> 8) #define VOP_MINOR(version) ((version) & 0xff) +#define VOP2_SOC_VARIANT 4 + #define NUM_YUV2YUV_COEFFICIENTS 12 +#define VOP_FEATURE_OUTPUT_10BIT BIT(0) +#define VOP_FEATURE_AFBDC BIT(1) +#define VOP_FEATURE_ALPHA_SCALE BIT(2) + +#define WIN_FEATURE_HDR2SDR BIT(0) +#define WIN_FEATURE_SDR2HDR BIT(1) +#define WIN_FEATURE_PRE_OVERLAY BIT(2) +#define WIN_FEATURE_AFBDC BIT(3) +#define WIN_FEATURE_CLUSTER_MAIN BIT(4) +#define WIN_FEATURE_CLUSTER_SUB BIT(5) + +#define DSP_BG_SWAP 0x1 +#define DSP_RB_SWAP 0x2 +#define DSP_RG_SWAP 0x4 +#define DSP_DELTA_SWAP 0x8 + /* AFBC supports a number of configurable modes. Relevant to us is block size * (16x16 or 32x8), storage modifiers (SPARSE, SPLIT), and the YUV-like * colourspace transform (YTR). 16x16 SPARSE mode is always used. SPLIT mode @@ -44,6 +63,77 @@ enum vop_data_format { VOP_FMT_YUV444SP, }; +enum _vop_sdr2hdr_func { + SDR2HDR_FOR_BT2020, + SDR2HDR_FOR_HDR, + SDR2HDR_FOR_HLG_HDR, +}; + +enum _vop_rgb2rgb_conv_mode { + BT709_TO_BT2020, + BT2020_TO_BT709, +}; + +enum vop_csc_format { + CSC_BT601L, + CSC_BT709L, + CSC_BT601F, + CSC_BT2020, +}; + +enum bcsh_out_mode { + BCSH_OUT_MODE_BLACK, + BCSH_OUT_MODE_BLUE, + BCSH_OUT_MODE_COLOR_BAR, + BCSH_OUT_MODE_NORMAL_VIDEO, +}; + +/* + * the delay number of a window in different mode. + */ +enum vop2_win_dly_mode { + VOP2_DLY_MODE_DEFAULT, /**< default mode */ + VOP2_DLY_MODE_HISO_S, /** HDR in SDR out mode, as a SDR window */ + VOP2_DLY_MODE_HIHO_H, /** HDR in HDR out mode, as a HDR window */ + VOP2_DLY_MODE_MAX, +}; + +struct vop_rect { + int width; + int height; +}; + +struct vop_hdr_table { + const uint32_t hdr2sdr_eetf_oetf_y0_offset; + const uint32_t hdr2sdr_eetf_oetf_y1_offset; + const uint32_t *hdr2sdr_eetf_yn; + const uint32_t *hdr2sdr_bt1886oetf_yn; + const uint32_t hdr2sdr_sat_y0_offset; + const uint32_t hdr2sdr_sat_y1_offset; + const uint32_t *hdr2sdr_sat_yn; + + const uint32_t hdr2sdr_src_range_min; + const uint32_t hdr2sdr_src_range_max; + const uint32_t hdr2sdr_normfaceetf; + const uint32_t hdr2sdr_dst_range_min; + const uint32_t hdr2sdr_dst_range_max; + const uint32_t hdr2sdr_normfacgamma; + + const uint32_t sdr2hdr_eotf_oetf_y0_offset; + const uint32_t sdr2hdr_eotf_oetf_y1_offset; + const uint32_t *sdr2hdr_bt1886eotf_yn_for_hlg_hdr; + const uint32_t *sdr2hdr_bt1886eotf_yn_for_bt2020; + const uint32_t *sdr2hdr_bt1886eotf_yn_for_hdr; + const uint32_t *sdr2hdr_st2084oetf_yn_for_hlg_hdr; + const uint32_t *sdr2hdr_st2084oetf_yn_for_bt2020; + const uint32_t *sdr2hdr_st2084oetf_yn_for_hdr; + const uint32_t sdr2hdr_oetf_dx_dxpow1_offset; + const uint32_t *sdr2hdr_st2084oetf_dxn_pow2; + const uint32_t *sdr2hdr_st2084oetf_dxn; + const uint32_t sdr2hdr_oetf_xn1_offset; + const uint32_t *sdr2hdr_st2084oetf_xn; +}; + struct vop_reg { uint32_t mask; uint16_t offset; @@ -57,8 +147,23 @@ struct vop_afbc { struct vop_reg win_sel; struct vop_reg format; struct vop_reg hreg_block_split; + struct vop_reg rb_swap; + struct vop_reg uv_swap; + struct vop_reg auto_gating_en; + struct vop_reg rotate; + struct vop_reg block_split_en; + struct vop_reg pic_vir_width; + struct vop_reg tile_num; + struct vop_reg pic_offset; struct vop_reg pic_size; + struct vop_reg dsp_offset; + struct vop_reg transform_offset; struct vop_reg hdr_ptr; + struct vop_reg half_block_en; + struct vop_reg xmirror; + struct vop_reg ymirror; + struct vop_reg rotate_270; + struct vop_reg rotate_90; struct vop_reg rstn; }; @@ -198,6 +303,12 @@ struct vop_win_data { enum drm_plane_type type; }; +struct vop_grf_ctrl { + struct vop_reg grf_dclk_inv; + struct vop_reg grf_bt1120_clk_inv; + struct vop_reg grf_bt656_clk_inv; +}; + struct vop_data { uint32_t version; const struct vop_intr *intr; @@ -216,14 +327,397 @@ struct vop_data { u64 feature; }; +struct vop2_cluster_regs { + struct vop_reg enable; + struct vop_reg afbc_enable; + struct vop_reg lb_mode; +}; + +struct vop2_scl_regs { + struct vop_reg scale_yrgb_x; + struct vop_reg scale_yrgb_y; + struct vop_reg scale_cbcr_x; + struct vop_reg scale_cbcr_y; + struct vop_reg yrgb_hor_scl_mode; + struct vop_reg yrgb_hscl_filter_mode; + struct vop_reg yrgb_ver_scl_mode; + struct vop_reg yrgb_vscl_filter_mode; + struct vop_reg cbcr_ver_scl_mode; + struct vop_reg cbcr_hscl_filter_mode; + struct vop_reg cbcr_hor_scl_mode; + struct vop_reg cbcr_vscl_filter_mode; + struct vop_reg vsd_cbcr_gt2; + struct vop_reg vsd_cbcr_gt4; + struct vop_reg vsd_yrgb_gt2; + struct vop_reg vsd_yrgb_gt4; + struct vop_reg bic_coe_sel; +}; + +struct vop2_win_regs { + const struct vop2_scl_regs *scl; + const struct vop2_cluster_regs *cluster; + const struct vop_afbc *afbc; + + struct vop_reg gate; + struct vop_reg enable; + struct vop_reg format; + struct vop_reg csc_mode; + struct vop_reg xmirror; + struct vop_reg ymirror; + struct vop_reg rb_swap; + struct vop_reg uv_swap; + struct vop_reg act_info; + struct vop_reg dsp_info; + struct vop_reg dsp_st; + struct vop_reg yrgb_mst; + struct vop_reg uv_mst; + struct vop_reg yrgb_vir; + struct vop_reg uv_vir; + struct vop_reg yuv_clip; + struct vop_reg lb_mode; + struct vop_reg y2r_en; + struct vop_reg r2y_en; + struct vop_reg channel; + struct vop_reg dst_alpha_ctl; + struct vop_reg src_alpha_ctl; + struct vop_reg alpha_mode; + struct vop_reg alpha_en; + struct vop_reg global_alpha_val; + struct vop_reg color_key; + struct vop_reg color_key_en; +}; + +struct vop2_video_port_regs { + struct vop_reg cfg_done; + struct vop_reg overlay_mode; + struct vop_reg dsp_background; + struct vop_reg port_mux; + struct vop_reg out_mode; + struct vop_reg standby; + struct vop_reg dsp_interlace; + struct vop_reg dsp_filed_pol; + struct vop_reg dsp_data_swap; + struct vop_reg post_dsp_out_r2y; + struct vop_reg pre_scan_htiming; + struct vop_reg htotal_pw; + struct vop_reg hact_st_end; + struct vop_reg vtotal_pw; + struct vop_reg vact_st_end; + struct vop_reg vact_st_end_f1; + struct vop_reg vs_st_end_f1; + struct vop_reg hpost_st_end; + struct vop_reg vpost_st_end; + struct vop_reg vpost_st_end_f1; + struct vop_reg post_scl_factor; + struct vop_reg post_scl_ctrl; + struct vop_reg dither_down_sel; + struct vop_reg dither_down_mode; + struct vop_reg dither_down_en; + struct vop_reg pre_dither_down_en; + struct vop_reg dither_up_en; + struct vop_reg bg_dly; + + struct vop_reg core_dclk_div; + struct vop_reg p2i_en; + struct vop_reg mipi_dual_en; + struct vop_reg mipi_dual_channel_swap; + struct vop_reg dsp_lut_en; + + struct vop_reg dclk_div2; + struct vop_reg dclk_div2_phase_lock; + + struct vop_reg hdr10_en; + struct vop_reg hdr_lut_update_en; + struct vop_reg hdr_lut_mode; + struct vop_reg hdr_lut_mst; + struct vop_reg sdr2hdr_eotf_en; + struct vop_reg sdr2hdr_r2r_en; + struct vop_reg sdr2hdr_r2r_mode; + struct vop_reg sdr2hdr_oetf_en; + struct vop_reg sdr2hdr_bypass_en; + struct vop_reg sdr2hdr_auto_gating_en; + struct vop_reg sdr2hdr_path_en; + struct vop_reg hdr2sdr_en; + struct vop_reg hdr2sdr_bypass_en; + struct vop_reg hdr2sdr_auto_gating_en; + struct vop_reg hdr2sdr_src_min; + struct vop_reg hdr2sdr_src_max; + struct vop_reg hdr2sdr_normfaceetf; + struct vop_reg hdr2sdr_dst_min; + struct vop_reg hdr2sdr_dst_max; + struct vop_reg hdr2sdr_normfacgamma; + uint32_t hdr2sdr_eetf_oetf_y0_offset; + uint32_t hdr2sdr_sat_y0_offset; + uint32_t sdr2hdr_eotf_oetf_y0_offset; + uint32_t sdr2hdr_oetf_dx_pow1_offset; + uint32_t sdr2hdr_oetf_xn1_offset; + struct vop_reg hdr_src_color_ctrl; + struct vop_reg hdr_dst_color_ctrl; + struct vop_reg hdr_src_alpha_ctrl; + struct vop_reg hdr_dst_alpha_ctrl; + + /* BCSH */ + struct vop_reg bcsh_brightness; + struct vop_reg bcsh_contrast; + struct vop_reg bcsh_sat_con; + struct vop_reg bcsh_sin_hue; + struct vop_reg bcsh_cos_hue; + struct vop_reg bcsh_r2y_csc_mode; + struct vop_reg bcsh_r2y_en; + struct vop_reg bcsh_y2r_csc_mode; + struct vop_reg bcsh_y2r_en; + struct vop_reg bcsh_out_mode; + struct vop_reg bcsh_en; + + /* 3d lut */ + struct vop_reg cubic_lut_en; + struct vop_reg cubic_lut_update_en; + struct vop_reg cubic_lut_mst; +}; + +struct vop2_wb_regs { + struct vop_reg enable; + struct vop_reg format; + struct vop_reg dither_en; + struct vop_reg r2y_en; + struct vop_reg yrgb_mst; + struct vop_reg uv_mst; + struct vop_reg vp_id; + struct vop_reg fifo_throd; + struct vop_reg scale_x_factor; + struct vop_reg scale_x_en; + struct vop_reg scale_y_en; + struct vop_reg axi_yrgb_id; + struct vop_reg axi_uv_id; +}; + +struct vop2_win_data { + const char *name; + uint8_t phys_id; + + uint32_t base; + enum drm_plane_type type; + + uint32_t nformats; + const uint32_t *formats; + const uint64_t *format_modifiers; + const unsigned int supported_rotations; + + const struct vop2_win_regs *regs; + const struct vop2_win_regs **area; + unsigned int area_size; + + /* + * vertical/horizontal scale up/down filter mode + */ + const u8 hsu_filter_mode; + const u8 hsd_filter_mode; + const u8 vsu_filter_mode; + const u8 vsd_filter_mode; + /** + * @layer_sel_id: defined by register OVERLAY_LAYER_SEL of VOP2 + */ + int layer_sel_id; + uint64_t feature; + + unsigned int max_upscale_factor; + unsigned int max_downscale_factor; + const uint8_t dly[VOP2_DLY_MODE_MAX]; +}; + +struct vop2_wb_data { + uint32_t nformats; + const uint32_t *formats; + struct vop_rect max_output; + const struct vop2_wb_regs *regs; +}; + +struct vop2_video_port_data { + char id; + uint32_t feature; + uint64_t soc_id[VOP2_SOC_VARIANT]; + uint16_t gamma_lut_len; + uint16_t cubic_lut_len; + struct vop_rect max_output; + const u8 pre_scan_max_dly[4]; + const struct vop_intr *intr; + const struct vop_hdr_table *hdr_table; + const struct vop2_video_port_regs *regs; +}; + +struct vop2_layer_regs { + struct vop_reg layer_sel; +}; + +/** + * struct vop2_layer_data - The logic graphic layer in vop2 + * + * The zorder: + * LAYERn + * LAYERn-1 + * . + * . + * . + * LAYER5 + * LAYER4 + * LAYER3 + * LAYER2 + * LAYER1 + * LAYER0 + * + * Each layer can select a unused window as input than feed to + * mixer for overlay. + * + * The pipeline in vop2: + * + * win-->layer-->mixer-->vp-->connector(RGB/LVDS/HDMI/MIPI) + * + */ +struct vop2_layer_data { + char id; + const struct vop2_layer_regs *regs; +}; + +struct vop2_ctrl { + struct vop_reg cfg_done_en; + struct vop_reg wb_cfg_done; + struct vop_reg auto_gating_en; + struct vop_reg ovl_cfg_done_port; + struct vop_reg ovl_port_mux_cfg_done_imd; + struct vop_reg ovl_port_mux_cfg; + struct vop_reg if_ctrl_cfg_done_imd; + struct vop_reg version; + struct vop_reg standby; + struct vop_reg dma_stop; + struct vop_reg lut_dma_en; + struct vop_reg axi_outstanding_max_num; + struct vop_reg axi_max_outstanding_en; + struct vop_reg hdmi_dclk_out_en; + struct vop_reg rgb_en; + struct vop_reg hdmi0_en; + struct vop_reg hdmi1_en; + struct vop_reg dp0_en; + struct vop_reg dp1_en; + struct vop_reg edp0_en; + struct vop_reg edp1_en; + struct vop_reg mipi0_en; + struct vop_reg mipi1_en; + struct vop_reg lvds0_en; + struct vop_reg lvds1_en; + struct vop_reg bt656_en; + struct vop_reg bt1120_en; + struct vop_reg dclk_pol; + struct vop_reg pin_pol; + struct vop_reg rgb_dclk_pol; + struct vop_reg rgb_pin_pol; + struct vop_reg lvds_dclk_pol; + struct vop_reg lvds_pin_pol; + struct vop_reg hdmi_dclk_pol; + struct vop_reg hdmi_pin_pol; + struct vop_reg edp_dclk_pol; + struct vop_reg edp_pin_pol; + struct vop_reg mipi_dclk_pol; + struct vop_reg mipi_pin_pol; + struct vop_reg dp_dclk_pol; + struct vop_reg dp_pin_pol; + + struct vop_reg win_vp_id[8]; + struct vop_reg win_dly[8]; + + /* connector mux */ + struct vop_reg rgb_mux; + struct vop_reg hdmi0_mux; + struct vop_reg hdmi1_mux; + struct vop_reg dp0_mux; + struct vop_reg dp1_mux; + struct vop_reg edp0_mux; + struct vop_reg edp1_mux; + struct vop_reg mipi0_mux; + struct vop_reg mipi1_mux; + struct vop_reg lvds0_mux; + struct vop_reg lvds1_mux; + + struct vop_reg lvds_dual_en; + struct vop_reg lvds_dual_mode; + struct vop_reg lvds_dual_channel_swap; + + struct vop_reg cluster0_src_color_ctrl; + struct vop_reg cluster0_dst_color_ctrl; + struct vop_reg cluster0_src_alpha_ctrl; + struct vop_reg cluster0_dst_alpha_ctrl; + struct vop_reg src_color_ctrl; + struct vop_reg dst_color_ctrl; + struct vop_reg src_alpha_ctrl; + struct vop_reg dst_alpha_ctrl; + + struct vop_reg bt1120_yc_swap; + struct vop_reg bt656_yc_swap; + struct vop_reg gamma_port_sel; + + struct vop_reg otp_en; + struct vop_reg reg_done_frm; + struct vop_reg cfg_done; +}; + +/** + * VOP2 data structe + * + * @version: VOP IP version + * @win_size: hardware win number + */ +struct vop2_data { + uint32_t version; + uint32_t feature; + uint8_t nr_vps; + uint8_t nr_mixers; + uint8_t nr_layers; + uint8_t nr_axi_intr; + const struct vop_intr *axi_intr; + const struct vop2_ctrl *ctrl; + const struct vop2_win_data *win; + const struct vop2_video_port_data *vp; + const struct vop2_wb_data *wb; + const struct vop2_layer_data *layer; + const struct vop_csc_table *csc_table; + const struct vop_hdr_table *hdr_table; + const struct vop_grf_ctrl *grf_ctrl; + struct vop_rect max_input; + struct vop_rect max_output; + + unsigned int win_size; +}; + /* interrupt define */ #define DSP_HOLD_VALID_INTR (1 << 0) #define FS_INTR (1 << 1) #define LINE_FLAG_INTR (1 << 2) #define BUS_ERROR_INTR (1 << 3) +#define FS_NEW_INTR BIT(4) +#define ADDR_SAME_INTR BIT(5) +#define LINE_FLAG1_INTR BIT(6) +#define WIN0_EMPTY_INTR BIT(7) +#define WIN1_EMPTY_INTR BIT(8) +#define WIN2_EMPTY_INTR BIT(9) +#define WIN3_EMPTY_INTR BIT(10) +#define HWC_EMPTY_INTR BIT(11) +#define POST_BUF_EMPTY_INTR BIT(12) +#define PWM_GEN_INTR BIT(13) +#define DMA_FINISH_INTR BIT(14) +#define FS_FIELD_INTR BIT(15) +#define FE_INTR BIT(16) +#define WB_UV_FIFO_FULL_INTR BIT(17) +#define WB_YRGB_FIFO_FULL_INTR BIT(18) +#define WB_COMPLETE_INTR BIT(19) #define INTR_MASK (DSP_HOLD_VALID_INTR | FS_INTR | \ - LINE_FLAG_INTR | BUS_ERROR_INTR) + LINE_FLAG_INTR | BUS_ERROR_INTR | \ + FS_NEW_INTR | LINE_FLAG1_INTR | \ + WIN0_EMPTY_INTR | WIN1_EMPTY_INTR | \ + WIN2_EMPTY_INTR | WIN3_EMPTY_INTR | \ + HWC_EMPTY_INTR | \ + POST_BUF_EMPTY_INTR | \ + DMA_FINISH_INTR | FS_FIELD_INTR | \ + FE_INTR) #define DSP_HOLD_VALID_INTR_EN(x) ((x) << 4) #define FS_INTR_EN(x) ((x) << 5) @@ -259,14 +753,24 @@ struct vop_data { * display output interface supported by rockchip lcdc */ #define ROCKCHIP_OUT_MODE_P888 0 +#define ROCKCHIP_OUT_MODE_BT1120 0 #define ROCKCHIP_OUT_MODE_P666 1 #define ROCKCHIP_OUT_MODE_P565 2 +#define ROCKCHIP_OUT_MODE_BT656 5 +#define ROCKCHIP_OUT_MODE_S888 8 +#define ROCKCHIP_OUT_MODE_S888_DUMMY 12 +#define ROCKCHIP_OUT_MODE_YUV420 14 /* for use special outface */ -#define ROCKCHIP_OUT_MODE_AAAA 15 +#define ROCKCHIP_OUT_MODE_AAAA 15 + /* output flags */ #define ROCKCHIP_OUTPUT_DSI_DUAL BIT(0) +#define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0) +#define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1) +#define ROCKCHIP_OUTPUT_DATA_SWAP BIT(2) + enum alpha_mode { ALPHA_STRAIGHT, ALPHA_INVERSE, @@ -296,6 +800,24 @@ enum factor_mode { ALPHA_SRC_GLOBAL, }; +enum src_factor_mode { + SRC_FAC_ALPHA_ZERO, + SRC_FAC_ALPHA_ONE, + SRC_FAC_ALPHA_DST, + SRC_FAC_ALPHA_DST_INVERSE, + SRC_FAC_ALPHA_SRC, + SRC_FAC_ALPHA_SRC_GLOBAL, +}; + +enum dst_factor_mode { + DST_FAC_ALPHA_ZERO, + DST_FAC_ALPHA_ONE, + DST_FAC_ALPHA_SRC, + DST_FAC_ALPHA_SRC_INVERSE, + DST_FAC_ALPHA_DST, + DST_FAC_ALPHA_DST_GLOBAL, +}; + enum scale_mode { SCALE_NONE = 0x0, SCALE_UP = 0x1, @@ -321,6 +843,18 @@ enum scale_down_mode { SCALE_DOWN_AVG = 0x1 }; +enum vop2_scale_up_mode { + VOP2_SCALE_UP_NRST_NBOR, + VOP2_SCALE_UP_BIL, + VOP2_SCALE_UP_BIC, +}; + +enum vop2_scale_down_mode { + VOP2_SCALE_DOWN_NRST_NBOR, + VOP2_SCALE_DOWN_BIL, + VOP2_SCALE_DOWN_AVG, +}; + enum dither_down_mode { RGB888_TO_RGB565 = 0x0, RGB888_TO_RGB666 = 0x1 @@ -337,6 +871,7 @@ enum vop_pol { DEN_NEGATIVE = 2 }; + #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) #define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12 #define SCL_MAX_VSKIPLINES 4 @@ -411,5 +946,16 @@ static inline int scl_vop_cal_lb_mode(int width, bool is_yuv) return lb_mode; } +static inline int us_to_vertical_line(struct drm_display_mode *mode, int us) +{ + return us * mode->clock / mode->htotal / 1000; +} + +static inline int interpolate(int x1, int y1, int x2, int y2, int x) +{ + return y1 + (y2 - y1) * (x - x1) / (x2 - x1); +} + extern const struct component_ops vop_component_ops; +extern const struct component_ops vop2_component_ops; #endif /* _ROCKCHIP_DRM_VOP_H */ diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 1b510f0ebd8e..f5da6b438926 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -4,12 +4,15 @@ * Author: Andy Yan */ #include -#include #include +#include #include #include +#include #include +#include #include +#include #include #ifdef CONFIG_DRM_ANALOGIX_DP #include @@ -39,12 +42,12 @@ #include #include +#include "../drm_crtc_internal.h" #include "../drm_internal.h" #include "rockchip_drm_drv.h" #include "rockchip_drm_gem.h" #include "rockchip_drm_fb.h" -#include "rockchip_drm_psr.h" #include "rockchip_drm_vop.h" #include "rockchip_vop_reg.h" @@ -244,7 +247,6 @@ struct vop2_plane_state { int global_alpha; int blend_mode; int color_key; - void *yrgb_kvaddr; unsigned long offset; int pdaf_data_type; bool async_commit; @@ -555,8 +557,6 @@ static const struct drm_bus_format_enum_list drm_bus_format_enum_list[] = { { MEDIA_BUS_FMT_UYYVYY8_0_5X24, "UYYVYY8_0_5X24" }, { MEDIA_BUS_FMT_YUV10_1X30, "YUV10_1X30" }, { MEDIA_BUS_FMT_UYYVYY10_0_5X30, "UYYVYY10_0_5X30" }, - { MEDIA_BUS_FMT_SRGB888_3X8, "SRGB888_3X8" }, - { MEDIA_BUS_FMT_SRGB888_DUMMY_4X8, "SRGB888_DUMMY_4X8" }, { MEDIA_BUS_FMT_RGB888_1X24, "RGB888_1X24" }, { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, "RGB888_1X7X4_SPWG" }, { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, "RGB888_1X7X4_JEIDA" }, @@ -920,16 +920,10 @@ static enum vop2_data_format vop2_convert_format(uint32_t format) return VOP2_FMT_RGB565; case DRM_FORMAT_NV12: return VOP2_FMT_YUV420SP; - case DRM_FORMAT_NV12_10: - return VOP2_FMT_YUV420SP_10; case DRM_FORMAT_NV16: return VOP2_FMT_YUV422SP; - case DRM_FORMAT_NV16_10: - return VOP2_FMT_YUV422SP_10; case DRM_FORMAT_NV24: return VOP2_FMT_YUV444SP; - case DRM_FORMAT_NV24_10: - return VOP2_FMT_YUV444SP_10; case DRM_FORMAT_YUYV: return VOP2_FMT_YUYV422; default: @@ -954,12 +948,8 @@ static enum vop2_afbc_format vop2_convert_afbc_format(uint32_t format) return VOP2_AFBC_FMT_RGB565; case DRM_FORMAT_NV12: return VOP2_AFBC_FMT_YUV420; - case DRM_FORMAT_NV12_10: - return VOP2_AFBC_FMT_YUV420_10BIT; case DRM_FORMAT_NV16: return VOP2_AFBC_FMT_YUV422; - case DRM_FORMAT_NV16_10: - return VOP2_AFBC_FMT_YUV422_10BIT; /* either of the below should not be reachable */ default: @@ -1012,7 +1002,6 @@ static bool vop2_afbc_rb_swap(uint32_t format) { switch (format) { case DRM_FORMAT_NV24: - case DRM_FORMAT_NV24_10: return true; default: return false; @@ -1024,8 +1013,6 @@ static bool vop2_afbc_uv_swap(uint32_t format) switch (format) { case DRM_FORMAT_NV12: case DRM_FORMAT_NV16: - case DRM_FORMAT_NV12_10: - case DRM_FORMAT_NV16_10: return true; default: return false; @@ -1038,9 +1025,6 @@ static bool vop2_win_uv_swap(uint32_t format) case DRM_FORMAT_NV12: case DRM_FORMAT_NV16: case DRM_FORMAT_NV24: - case DRM_FORMAT_NV12_10: - case DRM_FORMAT_NV16_10: - case DRM_FORMAT_NV24_10: return true; default: return false; @@ -1088,11 +1072,8 @@ static bool is_yuv_support(uint32_t format) { switch (format) { case DRM_FORMAT_NV12: - case DRM_FORMAT_NV12_10: case DRM_FORMAT_NV16: - case DRM_FORMAT_NV16_10: case DRM_FORMAT_NV24: - case DRM_FORMAT_NV24_10: case DRM_FORMAT_YUYV: return true; default: @@ -1181,7 +1162,7 @@ static uint32_t vop2_afbc_transform_offset(struct vop2_plane_state *vpstate) { struct drm_rect *src = &vpstate->src; struct drm_framebuffer *fb = vpstate->base.fb; - uint32_t bpp = fb->format->bpp[0]; + uint32_t bpp = fb->format->cpp[0] << 3; uint32_t vir_width = (fb->pitches[0] << 3) / bpp; uint32_t width = drm_rect_width(src) >> 16; uint32_t height = drm_rect_height(src) >> 16; @@ -1374,9 +1355,9 @@ static void vop2_setup_scale(struct vop2 *vop2, const struct vop2_win *win, { const struct vop2_data *vop2_data = vop2->data; const struct vop2_win_data *win_data = &vop2_data->win[win->win_id]; - const struct drm_format_info *info; - int hsub = drm_format_horz_chroma_subsampling(pixel_format); - int vsub = drm_format_vert_chroma_subsampling(pixel_format); + const struct drm_format_info *info = drm_format_info(pixel_format); + uint8_t hsub = info->hsub; + uint8_t vsub = info->vsub; uint16_t cbcr_src_w = src_w / hsub; uint16_t cbcr_src_h = src_h / vsub; uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; @@ -1386,8 +1367,6 @@ static void vop2_setup_scale(struct vop2 *vop2, const struct vop2_win *win, uint8_t gt4 = 0; uint32_t val; - info = drm_format_info(pixel_format); - if (src_h >= (4 * dst_h)) gt4 = 1; else if (src_h >= (2 * dst_h)) @@ -1834,6 +1813,10 @@ static int vop2_wb_encoder_atomic_check(struct drm_encoder *encoder, struct drm_crtc *crtc = cstate->crtc; struct vop2_video_port *vp = to_vop2_video_port(crtc); struct drm_framebuffer *fb; + struct drm_gem_object *obj, *uv_obj; + struct rockchip_gem_object *rk_obj, *rk_uv_obj; + + if (!conn_state->writeback_job || !conn_state->writeback_job->fb) return 0; @@ -1864,10 +1847,15 @@ static int vop2_wb_encoder_atomic_check(struct drm_encoder *encoder, } wb_state->vp_id = vp->id; - wb_state->yrgb_addr = rockchip_fb_get_dma_addr(fb, 0); + obj = fb->obj[0]; + rk_obj = to_rockchip_obj(obj); + wb_state->yrgb_addr = rk_obj->dma_addr + fb->offsets[0]; + if (fb->format->is_yuv) { - wb_state->uv_addr = rockchip_fb_get_dma_addr(fb, 1); - wb_state->uv_addr += fb->offsets[1]; + uv_obj = fb->obj[1]; + rk_uv_obj = to_rockchip_obj(uv_obj); + + wb_state->uv_addr = rk_uv_obj->dma_addr + fb->offsets[1]; } return 0; @@ -1958,7 +1946,7 @@ static void vop2_wb_commit(struct drm_crtc *crtc) DRM_DEV_DEBUG(vop2->dev, "Enable wb %ux%u fmt: %u pitches: %d\n", fb->width, fb->height, wb_state->format, fb->pitches[0]); - drm_writeback_queue_job(wb_conn, conn_state->writeback_job); + drm_writeback_queue_job(wb_conn, conn_state); conn_state->writeback_job = NULL; fifo_throd = fb->pitches[0] >> 4; @@ -2090,6 +2078,7 @@ static int vop2_crtc_atomic_gamma_set(struct drm_crtc *crtc, return 0; } +#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT) static int vop2_crtc_atomic_cubic_lut_set(struct drm_crtc *crtc, struct drm_crtc_state *old_state) { @@ -2108,7 +2097,7 @@ static int vop2_crtc_atomic_cubic_lut_set(struct drm_crtc *crtc, if (!vp->cubic_lut_gem_obj) { size_t size = (vp->cubic_lut_len + 1) / 2 * 16; - vp->cubic_lut_gem_obj = rockchip_gem_create_object(crtc->dev, size, true, 0); + vp->cubic_lut_gem_obj = rockchip_gem_create_object(crtc->dev, size, true); if (IS_ERR(vp->cubic_lut_gem_obj)) return -ENOMEM; } @@ -2144,6 +2133,42 @@ static int vop2_crtc_atomic_cubic_lut_set(struct drm_crtc *crtc, return 0; } +static void drm_crtc_enable_cubic_lut(struct drm_crtc *crtc, unsigned int cubic_lut_size) +{ + struct drm_device *dev = crtc->dev; + struct drm_mode_config *config = &dev->mode_config; + + if (cubic_lut_size) { + drm_object_attach_property(&crtc->base, + config->cubic_lut_property, 0); + drm_object_attach_property(&crtc->base, + config->cubic_lut_size_property, + cubic_lut_size); + } +} + +static void vop2_cubic_lut_init(struct vop2 *vop2) +{ + const struct vop2_data *vop2_data = vop2->data; + const struct vop2_video_port_data *vp_data; + struct vop2_video_port *vp; + struct drm_crtc *crtc; + int i; + + for (i = 0; i < vop2_data->nr_vps; i++) { + vp = &vop2->vps[i]; + crtc = &vp->crtc; + vp_data = &vop2_data->vp[vp->id]; + vp->cubic_lut_len = vp_data->cubic_lut_len; + + if (vp->cubic_lut_len) + drm_crtc_enable_cubic_lut(crtc, vp->cubic_lut_len); + } +} +#else +static void vop2_cubic_lut_init(struct vop2 *vop2) { } +#endif + static int vop2_core_clks_prepare_enable(struct vop2 *vop2) { int ret; @@ -2462,11 +2487,12 @@ static int vop2_plane_atomic_check(struct drm_plane *plane, struct drm_plane_sta const struct vop2_data *vop2_data; struct drm_rect *dest = &vpstate->dest; struct drm_rect *src = &vpstate->src; + struct drm_gem_object *obj, *uv_obj; + struct rockchip_gem_object *rk_obj, *rk_uv_obj; int min_scale = win->regs->scl ? FRAC_16_16(1, 8) : DRM_PLANE_HELPER_NO_SCALING; int max_scale = win->regs->scl ? FRAC_16_16(8, 1) : DRM_PLANE_HELPER_NO_SCALING; unsigned long offset; dma_addr_t dma_addr; - void *kvaddr; int ret; crtc = crtc ? crtc : plane->state->crtc; @@ -2550,7 +2576,7 @@ static int vop2_plane_atomic_check(struct drm_plane *plane, struct drm_plane_sta return -EINVAL; } - offset = (src->x1 >> 16) * fb->format->bpp[0] / 8; + offset = (src->x1 >> 16) * fb->format->cpp[0]; vpstate->offset = offset + fb->offsets[0]; /* @@ -2563,20 +2589,21 @@ static int vop2_plane_atomic_check(struct drm_plane *plane, struct drm_plane_sta else offset += (src->y1 >> 16) * fb->pitches[0]; - dma_addr = rockchip_fb_get_dma_addr(fb, 0); - kvaddr = rockchip_fb_get_kvaddr(fb, 0); + obj = fb->obj[0]; + rk_obj = to_rockchip_obj(obj); - vpstate->yrgb_mst = dma_addr + offset + fb->offsets[0]; - vpstate->yrgb_kvaddr = kvaddr + offset + fb->offsets[0]; + vpstate->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0]; if (fb->format->is_yuv) { - int hsub = drm_format_horz_chroma_subsampling(fb->format->format); - int vsub = drm_format_vert_chroma_subsampling(fb->format->format); + int hsub = fb->format->hsub; + int vsub = fb->format->vsub; - offset = (src->x1 >> 16) * fb->format->bpp[1] / hsub / 8; + offset = (src->x1 >> 16) * fb->format->cpp[1] / hsub; offset += (src->y1 >> 16) * fb->pitches[1] / vsub; - dma_addr = rockchip_fb_get_dma_addr(fb, 1); - dma_addr += offset + fb->offsets[1]; + uv_obj = fb->obj[1]; + rk_uv_obj = to_rockchip_obj(uv_obj); + + dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; vpstate->uv_mst = dma_addr; } @@ -2672,7 +2699,7 @@ static void vop2_plane_atomic_update(struct drm_plane *plane, struct drm_plane_s struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; struct vop2 *vop2 = win->vop2; struct drm_framebuffer *fb = pstate->fb; - uint32_t bpp = fb->format->bpp[0]; + uint32_t bpp = fb->format->cpp[0] << 3; uint32_t actual_w, actual_h, dsp_w, dsp_h; uint32_t dsp_stx, dsp_sty; uint32_t act_info, dsp_info, dsp_st; @@ -3270,6 +3297,10 @@ static int vop2_plane_info_dump(struct seq_file *s, struct drm_plane *plane) struct drm_rect *src, *dest; struct drm_framebuffer *fb = pstate->fb; struct drm_format_name_buf format_name; + struct drm_gem_object *obj; + struct rockchip_gem_object *rk_obj; + dma_addr_t fb_addr; + int i; DEBUG_PRINT(" %s: %s\n", win->name, pstate->crtc ? "ACTIVE" : "DISABLED"); @@ -3300,8 +3331,10 @@ static int vop2_plane_info_dump(struct seq_file *s, struct drm_plane *plane) DEBUG_PRINT("\tdst: pos[%d, %d] rect[%d x %d]\n", dest->x1, dest->y1, drm_rect_width(dest), drm_rect_height(dest)); - for (i = 0; i < drm_format_num_planes(fb->format->format); i++) { - dma_addr_t fb_addr = rockchip_fb_get_dma_addr(fb, i); + for (i = 0; i < fb->format->num_planes; i++) { + obj = fb->obj[0]; + rk_obj = to_rockchip_obj(obj); + fb_addr = rk_obj->dma_addr + fb->offsets[0]; DEBUG_PRINT("\tbuf[%d]: addr: %pad pitch: %d offset: %d\n", i, &fb_addr, fb->pitches[i], fb->offsets[i]); @@ -3487,19 +3520,11 @@ static int vop2_crtc_debugfs_init(struct drm_minor *minor, struct drm_crtc *crtc for (i = 0; i < ARRAY_SIZE(vop2_debugfs_files); i++) vop2->debugfs_files[i].data = vop2; - ret = drm_debugfs_create_files(vop2->debugfs_files, - ARRAY_SIZE(vop2_debugfs_files), - vop2->debugfs, - minor); - if (ret) { - dev_err(vop2->dev, "could not install rockchip_debugfs_list\n"); - goto free; - } - + drm_debugfs_create_files(vop2->debugfs_files, + ARRAY_SIZE(vop2_debugfs_files), + vop2->debugfs, + minor); return 0; -free: - kfree(vop2->debugfs_files); - vop2->debugfs_files = NULL; remove: debugfs_remove(vop2->debugfs); vop2->debugfs = NULL; @@ -3556,7 +3581,7 @@ static size_t vop2_plane_line_bandwidth(struct drm_plane_state *pstate) struct drm_framebuffer *fb = pstate->fb; struct drm_rect *dst = &vpstate->dest; struct drm_rect *src = &vpstate->src; - int bpp = fb->format->bpp[0]; + int bpp = fb->format->cpp[0] << 3; int src_width = drm_rect_width(src) >> 16; int src_height = drm_rect_height(src) >> 16; int dst_width = drm_rect_width(dst); @@ -3746,8 +3771,6 @@ static void vop2_dither_setup(struct drm_crtc *crtc) VOP_MODULE_SET(vop2, vp, dither_down_en, 0); VOP_MODULE_SET(vop2, vp, pre_dither_down_en, 0); break; - case MEDIA_BUS_FMT_SRGB888_3X8: - case MEDIA_BUS_FMT_SRGB888_DUMMY_4X8: case MEDIA_BUS_FMT_RGB888_1X24: case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: @@ -3881,7 +3904,7 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state vop2_lock(vop2); DRM_DEV_INFO(vop2->dev, "Update mode to %dx%d%s%d, type: %d for vp%d\n", hdisplay, vdisplay, interlaced ? "i" : "p", - adjusted_mode->vrefresh, vcstate->output_type, vp->id); + drm_mode_vrefresh(adjusted_mode), vcstate->output_type, vp->id); vop2_initial(crtc); vcstate->vdisplay = vdisplay; vcstate->mode_update = vop2_crtc_mode_update(crtc); @@ -4137,12 +4160,12 @@ static void vop2_setup_hdr10(struct vop2_video_port *vp, uint8_t win_phys_id) /* * HDR video plane input */ - if (vpstate->eotf == SMPTE_ST2084) + if (vpstate->eotf == HDMI_EOTF_SMPTE_ST2084) hdr_en = 1; vp->hdr_en = hdr_en; vp->hdr_in = hdr_en; - vp->hdr_out = (vcstate->eotf == SMPTE_ST2084) ? true : false; + vp->hdr_out = (vcstate->eotf == HDMI_EOTF_SMPTE_ST2084) ? true : false; /* * only laryer0 support hdr2sdr @@ -4861,12 +4884,13 @@ static void vop2_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state vp->gamma_lut = crtc->state->gamma_lut->data; vop2_crtc_atomic_gamma_set(crtc, crtc->state); } - +#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT) if (crtc->state->cubic_lut || vp->cubic_lut) { if (crtc->state->cubic_lut) vp->cubic_lut = crtc->state->cubic_lut->data; vop2_crtc_atomic_cubic_lut_set(crtc, crtc->state); } +#endif } else { VOP_MODULE_SET(vop2, vp, cubic_lut_update_en, 0); } @@ -5474,24 +5498,6 @@ static int vop2_gamma_init(struct vop2 *vop2) return 0; } -static void vop2_cubic_lut_init(struct vop2 *vop2) -{ - const struct vop2_data *vop2_data = vop2->data; - const struct vop2_video_port_data *vp_data; - struct vop2_video_port *vp; - struct drm_crtc *crtc; - int i; - - for (i = 0; i < vop2_data->nr_vps; i++) { - vp = &vop2->vps[i]; - crtc = &vp->crtc; - vp_data = &vop2_data->vp[vp->id]; - vp->cubic_lut_len = vp_data->cubic_lut_len; - - if (vp->cubic_lut_len) - drm_crtc_enable_cubic_lut(crtc, vp->cubic_lut_len); - } -} static int vop2_create_crtc(struct vop2 *vop2) { diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c index bb68b3597a6d..cd1abb41f7ac 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c @@ -4,10 +4,13 @@ * Author: Andy Yan */ -#include #include #include +#include +#include +#include +#include #include "rockchip_drm_vop.h" #include "rockchip_vop_reg.h" @@ -37,9 +40,6 @@ static const uint32_t formats_win_full_10bit[] = { DRM_FORMAT_NV12, DRM_FORMAT_NV16, DRM_FORMAT_NV24, - DRM_FORMAT_NV12_10, - DRM_FORMAT_NV16_10, - DRM_FORMAT_NV24_10, }; static const uint32_t formats_win_lite[] = { @@ -955,7 +955,7 @@ static const struct vop2_win_regs rk3568_esmart_win_data = { .csc_mode = VOP_REG(RK3568_ESMART0_CTRL0, 0x3, 2), .ymirror = VOP_REG(RK3568_ESMART0_CTRL1, 0x1, 31), .color_key = VOP_REG(RK3568_ESMART0_COLOR_KEY_CTRL, 0x3fffffff, 0), - .color_key_en = VOP_REG(RK3366_LIT_WIN0_COLOR_KEY, 0x1, 31), + .color_key_en = VOP_REG(RK3568_ESMART0_COLOR_KEY_CTRL, 0x1, 31), }; /* diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h index 6e9fa5815d4d..8923c8b1577e 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h @@ -1028,4 +1028,420 @@ #define RK3066_DSP_LUT_ADDR 0x800 /* rk3066 register definition end */ +#define RK3568_GRF_VO_CON1 0x0364 +/* System registers definition */ +#define RK3568_REG_CFG_DONE 0x000 +#define RK3568_VOP2_WB_CFG_DONE BIT(14) +#define RK3568_VOP2_GLB_CFG_DONE_EN BIT(15) +#define RK3568_VERSION_INFO 0x004 +#define RK3568_SYS_AUTO_GATING_CTRL 0x008 +#define RK3568_SYS_AXI_LUT_CTRL 0x024 +#define RK3568_DSP_IF_EN 0x028 +#define RK3568_DSP_IF_CTRL 0x02c +#define RK3568_DSP_IF_POL 0x030 +#define RK3568_WB_CTRL 0x40 +#define RK3568_WB_XSCAL_FACTOR 0x44 +#define RK3568_WB_YRGB_MST 0x48 +#define RK3568_WB_CBR_MST 0x4C +#define RK3568_OTP_WIN_EN 0x050 +#define RK3568_LUT_PORT_SEL 0x058 +#define RK3568_SYS_STATUS0 0x060 +#define RK3568_VP0_LINE_FLAG 0x70 +#define RK3568_VP1_LINE_FLAG 0x74 +#define RK3568_VP2_LINE_FLAG 0x78 +#define RK3568_SYS0_INT_EN 0x80 +#define RK3568_SYS0_INT_CLR 0x84 +#define RK3568_SYS0_INT_STATUS 0x88 +#define RK3568_SYS1_INT_EN 0x90 +#define RK3568_SYS1_INT_CLR 0x94 +#define RK3568_SYS1_INT_STATUS 0x98 +#define RK3568_VP0_INT_EN 0xA0 +#define RK3568_VP0_INT_CLR 0xA4 +#define RK3568_VP0_INT_STATUS 0xA8 +#define RK3568_VP0_INT_RAW_STATUS 0xAC +#define RK3568_VP1_INT_EN 0xB0 +#define RK3568_VP1_INT_CLR 0xB4 +#define RK3568_VP1_INT_STATUS 0xB8 +#define RK3568_VP1_INT_RAW_STATUS 0xBC +#define RK3568_VP2_INT_EN 0xC0 +#define RK3568_VP2_INT_CLR 0xC4 +#define RK3568_VP2_INT_STATUS 0xC8 +#define RK3568_VP2_INT_RAW_STATUS 0xCC + +/* Video Port registers definition */ +#define RK3568_VP0_DSP_CTRL 0xC00 +#define RK3568_VP0_MIPI_CTRL 0xC04 +#define RK3568_VP0_COLOR_BAR_CTRL 0xC08 +#define RK3568_VP0_3D_LUT_CTRL 0xC10 +#define RK3568_VP0_3D_LUT_MST 0xC20 +#define RK3568_VP0_DSP_BG 0xC2C +#define RK3568_VP0_PRE_SCAN_HTIMING 0xC30 +#define RK3568_VP0_POST_DSP_HACT_INFO 0xC34 +#define RK3568_VP0_POST_DSP_VACT_INFO 0xC38 +#define RK3568_VP0_POST_SCL_FACTOR_YRGB 0xC3C +#define RK3568_VP0_POST_SCL_CTRL 0xC40 +#define RK3568_VP0_POST_DSP_VACT_INFO_F1 0xC44 +#define RK3568_VP0_DSP_HTOTAL_HS_END 0xC48 +#define RK3568_VP0_DSP_HACT_ST_END 0xC4C +#define RK3568_VP0_DSP_VTOTAL_VS_END 0xC50 +#define RK3568_VP0_DSP_VACT_ST_END 0xC54 +#define RK3568_VP0_DSP_VS_ST_END_F1 0xC58 +#define RK3568_VP0_DSP_VACT_ST_END_F1 0xC5C +#define RK3568_VP0_BCSH_CTRL 0xC60 +#define RK3568_VP0_BCSH_BCS 0xC64 +#define RK3568_VP0_BCSH_H 0xC68 +#define RK3568_VP0_BCSH_COLOR_BAR 0xC6C + +#define RK3568_VP1_DSP_CTRL 0xD00 +#define RK3568_VP1_MIPI_CTRL 0xD04 +#define RK3568_VP1_COLOR_BAR_CTRL 0xD08 +#define RK3568_VP1_DSP_BG 0xD2C +#define RK3568_VP1_PRE_SCAN_HTIMING 0xD30 +#define RK3568_VP1_POST_DSP_HACT_INFO 0xD34 +#define RK3568_VP1_POST_DSP_VACT_INFO 0xD38 +#define RK3568_VP1_POST_SCL_FACTOR_YRGB 0xD3C +#define RK3568_VP1_POST_SCL_CTRL 0xD40 +#define RK3568_VP1_DSP_HACT_INFO 0xD34 +#define RK3568_VP1_DSP_VACT_INFO 0xD38 +#define RK3568_VP1_POST_DSP_VACT_INFO_F1 0xD44 +#define RK3568_VP1_DSP_HTOTAL_HS_END 0xD48 +#define RK3568_VP1_DSP_HACT_ST_END 0xD4C +#define RK3568_VP1_DSP_VTOTAL_VS_END 0xD50 +#define RK3568_VP1_DSP_VACT_ST_END 0xD54 +#define RK3568_VP1_DSP_VS_ST_END_F1 0xD58 +#define RK3568_VP1_DSP_VACT_ST_END_F1 0xD5C +#define RK3568_VP1_BCSH_CTRL 0xD60 +#define RK3568_VP1_BCSH_BCS 0xD64 +#define RK3568_VP1_BCSH_H 0xD68 +#define RK3568_VP1_BCSH_COLOR_BAR 0xD6C + +#define RK3568_VP2_DSP_CTRL 0xE00 +#define RK3568_VP2_MIPI_CTRL 0xE04 +#define RK3568_VP2_COLOR_BAR_CTRL 0xE08 +#define RK3568_VP2_DSP_BG 0xE2C +#define RK3568_VP2_PRE_SCAN_HTIMING 0xE30 +#define RK3568_VP2_POST_DSP_HACT_INFO 0xE34 +#define RK3568_VP2_POST_DSP_VACT_INFO 0xE38 +#define RK3568_VP2_POST_SCL_FACTOR_YRGB 0xE3C +#define RK3568_VP2_POST_SCL_CTRL 0xE40 +#define RK3568_VP2_DSP_HACT_INFO 0xE34 +#define RK3568_VP2_DSP_VACT_INFO 0xE38 +#define RK3568_VP2_POST_DSP_VACT_INFO_F1 0xE44 +#define RK3568_VP2_DSP_HTOTAL_HS_END 0xE48 +#define RK3568_VP2_DSP_HACT_ST_END 0xE4C +#define RK3568_VP2_DSP_VTOTAL_VS_END 0xE50 +#define RK3568_VP2_DSP_VACT_ST_END 0xE54 +#define RK3568_VP2_DSP_VS_ST_END_F1 0xE58 +#define RK3568_VP2_DSP_VACT_ST_END_F1 0xE5C +#define RK3568_VP2_BCSH_CTRL 0xE60 +#define RK3568_VP2_BCSH_BCS 0xE64 +#define RK3568_VP2_BCSH_H 0xE68 +#define RK3568_VP2_BCSH_COLOR_BAR 0xE6C + +/* Overlay registers definition */ +#define RK3568_OVL_CTRL 0x600 +#define RK3568_OVL_LAYER_SEL 0x604 +#define RK3568_OVL_PORT_SEL 0x608 +#define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL 0x610 +#define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614 +#define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618 +#define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C +#define RK3568_MIX0_SRC_COLOR_CTRL 0x650 +#define RK3568_MIX0_DST_COLOR_CTRL 0x654 +#define RK3568_MIX0_SRC_ALPHA_CTRL 0x658 +#define RK3568_MIX0_DST_ALPHA_CTRL 0x65C +#define RK3568_HDR0_SRC_COLOR_CTRL 0x6C0 +#define RK3568_HDR0_DST_COLOR_CTRL 0x6C4 +#define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8 +#define RK3568_HDR0_DST_ALPHA_CTRL 0x6CC +#define RK3568_VP0_BG_MIX_CTRL 0x6E0 +#define RK3568_VP1_BG_MIX_CTRL 0x6E4 +#define RK3568_VP2_BG_MIX_CTRL 0x6E8 +#define RK3568_CLUSTER_DLY_NUM 0x6F0 +#define RK3568_SMART_DLY_NUM 0x6F8 + +/* Cluster0 register definition */ +#define RK3568_CLUSTER0_WIN0_CTRL0 0x1000 +#define RK3568_CLUSTER0_WIN0_CTRL1 0x1004 +#define RK3568_CLUSTER0_WIN0_YRGB_MST 0x1010 +#define RK3568_CLUSTER0_WIN0_CBR_MST 0x1014 +#define RK3568_CLUSTER0_WIN0_VIR 0x1018 +#define RK3568_CLUSTER0_WIN0_ACT_INFO 0x1020 +#define RK3568_CLUSTER0_WIN0_DSP_INFO 0x1024 +#define RK3568_CLUSTER0_WIN0_DSP_ST 0x1028 +#define RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB 0x1030 +#define RK3568_CLUSTER0_WIN0_AFBCD_TRANSFORM_OFFSET 0x103C +#define RK3568_CLUSTER0_WIN0_AFBCD_OUTPUT_CTRL 0x1050 +#define RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE 0x1054 +#define RK3568_CLUSTER0_WIN0_AFBCD_HDR_PTR 0x1058 +#define RK3568_CLUSTER0_WIN0_AFBCD_VIR_WIDTH 0x105C +#define RK3568_CLUSTER0_WIN0_AFBCD_PIC_SIZE 0x1060 +#define RK3568_CLUSTER0_WIN0_AFBCD_PIC_OFFSET 0x1064 +#define RK3568_CLUSTER0_WIN0_AFBCD_DSP_OFFSET 0x1068 +#define RK3568_CLUSTER0_WIN0_AFBCD_CTRL 0x106C + +#define RK3568_CLUSTER0_WIN1_CTRL0 0x1080 +#define RK3568_CLUSTER0_WIN1_CTRL1 0x1084 +#define RK3568_CLUSTER0_WIN1_YRGB_MST 0x1090 +#define RK3568_CLUSTER0_WIN1_CBR_MST 0x1094 +#define RK3568_CLUSTER0_WIN1_VIR 0x1098 +#define RK3568_CLUSTER0_WIN1_ACT_INFO 0x10A0 +#define RK3568_CLUSTER0_WIN1_DSP_INFO 0x10A4 +#define RK3568_CLUSTER0_WIN1_DSP_ST 0x10A8 +#define RK3568_CLUSTER0_WIN1_SCL_FACTOR_YRGB 0x10B0 +#define RK3568_CLUSTER0_WIN1_AFBCD_OUTPUT_CTRL 0x10D0 +#define RK3568_CLUSTER0_WIN1_AFBCD_ROTATE_MODE 0x10D4 +#define RK3568_CLUSTER0_WIN1_AFBCD_HDR_PTR 0x10D8 +#define RK3568_CLUSTER0_WIN1_AFBCD_VIR_WIDTH 0x10DC +#define RK3568_CLUSTER0_WIN1_AFBCD_PIC_SIZE 0x10E0 +#define RK3568_CLUSTER0_WIN1_AFBCD_PIC_OFFSET 0x10E4 +#define RK3568_CLUSTER0_WIN1_AFBCD_DSP_OFFSET 0x10E8 +#define RK3568_CLUSTER0_WIN1_AFBCD_CTRL 0x10EC + +#define RK3568_CLUSTER0_CTRL 0x1100 + +#define RK3568_CLUSTER1_WIN0_CTRL0 0x1200 +#define RK3568_CLUSTER1_WIN0_CTRL1 0x1204 +#define RK3568_CLUSTER1_WIN0_YRGB_MST 0x1210 +#define RK3568_CLUSTER1_WIN0_CBR_MST 0x1214 +#define RK3568_CLUSTER1_WIN0_VIR 0x1218 +#define RK3568_CLUSTER1_WIN0_ACT_INFO 0x1220 +#define RK3568_CLUSTER1_WIN0_DSP_INFO 0x1224 +#define RK3568_CLUSTER1_WIN0_DSP_ST 0x1228 +#define RK3568_CLUSTER1_WIN0_SCL_FACTOR_YRGB 0x1230 +#define RK3568_CLUSTER1_WIN0_AFBCD_TRANSFORM_OFFSET 0x123C +#define RK3568_CLUSTER1_WIN0_AFBCD_OUTPUT_CTRL 0x1250 +#define RK3568_CLUSTER1_WIN0_AFBCD_ROTATE_MODE 0x1254 +#define RK3568_CLUSTER1_WIN0_AFBCD_HDR_PTR 0x1258 +#define RK3568_CLUSTER1_WIN0_AFBCD_VIR_WIDTH 0x125C +#define RK3568_CLUSTER1_WIN0_AFBCD_PIC_SIZE 0x1260 +#define RK3568_CLUSTER1_WIN0_AFBCD_PIC_OFFSET 0x1264 +#define RK3568_CLUSTER1_WIN0_AFBCD_DSP_OFFSET 0x1268 +#define RK3568_CLUSTER1_WIN0_AFBCD_CTRL 0x126C + +#define RK3568_CLUSTER1_WIN1_CTRL0 0x1280 +#define RK3568_CLUSTER1_WIN1_CTRL1 0x1284 +#define RK3568_CLUSTER1_WIN1_YRGB_MST 0x1290 +#define RK3568_CLUSTER1_WIN1_CBR_MST 0x1294 +#define RK3568_CLUSTER1_WIN1_VIR 0x1298 +#define RK3568_CLUSTER1_WIN1_ACT_INFO 0x12A0 +#define RK3568_CLUSTER1_WIN1_DSP_INFO 0x12A4 +#define RK3568_CLUSTER1_WIN1_DSP_ST 0x12A8 +#define RK3568_CLUSTER1_WIN1_SCL_FACTOR_YRGB 0x12B0 +#define RK3568_CLUSTER1_WIN1_AFBCD_OUTPUT_CTRL 0x12D0 +#define RK3568_CLUSTER1_WIN1_AFBCD_ROTATE_MODE 0x12D4 +#define RK3568_CLUSTER1_WIN1_AFBCD_HDR_PTR 0x12D8 +#define RK3568_CLUSTER1_WIN1_AFBCD_VIR_WIDTH 0x12DC +#define RK3568_CLUSTER1_WIN1_AFBCD_PIC_SIZE 0x12E0 +#define RK3568_CLUSTER1_WIN1_AFBCD_PIC_OFFSET 0x12E4 +#define RK3568_CLUSTER1_WIN1_AFBCD_DSP_OFFSET 0x12E8 +#define RK3568_CLUSTER1_WIN1_AFBCD_CTRL 0x12EC + +#define RK3568_CLUSTER1_CTRL 0x1300 + +/* Esmart register definition */ +#define RK3568_ESMART0_CTRL0 0x1800 +#define RK3568_ESMART0_CTRL1 0x1804 +#define RK3568_ESMART0_REGION0_CTRL 0x1810 +#define RK3568_ESMART0_REGION0_YRGB_MST 0x1814 +#define RK3568_ESMART0_REGION0_CBR_MST 0x1818 +#define RK3568_ESMART0_REGION0_VIR 0x181C +#define RK3568_ESMART0_REGION0_ACT_INFO 0x1820 +#define RK3568_ESMART0_REGION0_DSP_INFO 0x1824 +#define RK3568_ESMART0_REGION0_DSP_ST 0x1828 +#define RK3568_ESMART0_REGION0_SCL_CTRL 0x1830 +#define RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB 0x1834 +#define RK3568_ESMART0_REGION0_SCL_FACTOR_CBR 0x1838 +#define RK3568_ESMART0_REGION0_SCL_OFFSET 0x183C +#define RK3568_ESMART0_REGION1_CTRL 0x1840 +#define RK3568_ESMART0_REGION1_YRGB_MST 0x1844 +#define RK3568_ESMART0_REGION1_CBR_MST 0x1848 +#define RK3568_ESMART0_REGION1_VIR 0x184C +#define RK3568_ESMART0_REGION1_ACT_INFO 0x1850 +#define RK3568_ESMART0_REGION1_DSP_INFO 0x1854 +#define RK3568_ESMART0_REGION1_DSP_ST 0x1858 +#define RK3568_ESMART0_REGION1_SCL_CTRL 0x1860 +#define RK3568_ESMART0_REGION1_SCL_FACTOR_YRGB 0x1864 +#define RK3568_ESMART0_REGION1_SCL_FACTOR_CBR 0x1868 +#define RK3568_ESMART0_REGION1_SCL_OFFSET 0x186C +#define RK3568_ESMART0_REGION2_CTRL 0x1870 +#define RK3568_ESMART0_REGION2_YRGB_MST 0x1874 +#define RK3568_ESMART0_REGION2_CBR_MST 0x1878 +#define RK3568_ESMART0_REGION2_VIR 0x187C +#define RK3568_ESMART0_REGION2_ACT_INFO 0x1880 +#define RK3568_ESMART0_REGION2_DSP_INFO 0x1884 +#define RK3568_ESMART0_REGION2_DSP_ST 0x1888 +#define RK3568_ESMART0_REGION2_SCL_CTRL 0x1890 +#define RK3568_ESMART0_REGION2_SCL_FACTOR_YRGB 0x1894 +#define RK3568_ESMART0_REGION2_SCL_FACTOR_CBR 0x1898 +#define RK3568_ESMART0_REGION2_SCL_OFFSET 0x189C +#define RK3568_ESMART0_REGION3_CTRL 0x18A0 +#define RK3568_ESMART0_REGION3_YRGB_MST 0x18A4 +#define RK3568_ESMART0_REGION3_CBR_MST 0x18A8 +#define RK3568_ESMART0_REGION3_VIR 0x18AC +#define RK3568_ESMART0_REGION3_ACT_INFO 0x18B0 +#define RK3568_ESMART0_REGION3_DSP_INFO 0x18B4 +#define RK3568_ESMART0_REGION3_DSP_ST 0x18B8 +#define RK3568_ESMART0_REGION3_SCL_CTRL 0x18C0 +#define RK3568_ESMART0_REGION3_SCL_FACTOR_YRGB 0x18C4 +#define RK3568_ESMART0_REGION3_SCL_FACTOR_CBR 0x18C8 +#define RK3568_ESMART0_REGION3_SCL_OFFSET 0x18CC +#define RK3568_ESMART0_COLOR_KEY_CTRL 0x18D0 + +#define RK3568_ESMART1_CTRL0 0x1A00 +#define RK3568_ESMART1_CTRL1 0x1A04 +#define RK3568_ESMART1_REGION0_CTRL 0x1A10 +#define RK3568_ESMART1_REGION0_YRGB_MST 0x1A14 +#define RK3568_ESMART1_REGION0_CBR_MST 0x1A18 +#define RK3568_ESMART1_REGION0_VIR 0x1A1C +#define RK3568_ESMART1_REGION0_ACT_INFO 0x1A20 +#define RK3568_ESMART1_REGION0_DSP_INFO 0x1A24 +#define RK3568_ESMART1_REGION0_DSP_ST 0x1A28 +#define RK3568_ESMART1_REGION0_SCL_CTRL 0x1A30 +#define RK3568_ESMART1_REGION0_SCL_FACTOR_YRGB 0x1A34 +#define RK3568_ESMART1_REGION0_SCL_FACTOR_CBR 0x1A38 +#define RK3568_ESMART1_REGION0_SCL_OFFSET 0x1A3C +#define RK3568_ESMART1_REGION1_CTRL 0x1A40 +#define RK3568_ESMART1_REGION1_YRGB_MST 0x1A44 +#define RK3568_ESMART1_REGION1_CBR_MST 0x1A48 +#define RK3568_ESMART1_REGION1_VIR 0x1A4C +#define RK3568_ESMART1_REGION1_ACT_INFO 0x1A50 +#define RK3568_ESMART1_REGION1_DSP_INFO 0x1A54 +#define RK3568_ESMART1_REGION1_DSP_ST 0x1A58 +#define RK3568_ESMART1_REGION1_SCL_CTRL 0x1A60 +#define RK3568_ESMART1_REGION1_SCL_FACTOR_YRGB 0x1A64 +#define RK3568_ESMART1_REGION1_SCL_FACTOR_CBR 0x1A68 +#define RK3568_ESMART1_REGION1_SCL_OFFSET 0x1A6C +#define RK3568_ESMART1_REGION2_CTRL 0x1A70 +#define RK3568_ESMART1_REGION2_YRGB_MST 0x1A74 +#define RK3568_ESMART1_REGION2_CBR_MST 0x1A78 +#define RK3568_ESMART1_REGION2_VIR 0x1A7C +#define RK3568_ESMART1_REGION2_ACT_INFO 0x1A80 +#define RK3568_ESMART1_REGION2_DSP_INFO 0x1A84 +#define RK3568_ESMART1_REGION2_DSP_ST 0x1A88 +#define RK3568_ESMART1_REGION2_SCL_CTRL 0x1A90 +#define RK3568_ESMART1_REGION2_SCL_FACTOR_YRGB 0x1A94 +#define RK3568_ESMART1_REGION2_SCL_FACTOR_CBR 0x1A98 +#define RK3568_ESMART1_REGION2_SCL_OFFSET 0x1A9C +#define RK3568_ESMART1_REGION3_CTRL 0x1AA0 +#define RK3568_ESMART1_REGION3_YRGB_MST 0x1AA4 +#define RK3568_ESMART1_REGION3_CBR_MST 0x1AA8 +#define RK3568_ESMART1_REGION3_VIR 0x1AAC +#define RK3568_ESMART1_REGION3_ACT_INFO 0x1AB0 +#define RK3568_ESMART1_REGION3_DSP_INFO 0x1AB4 +#define RK3568_ESMART1_REGION3_DSP_ST 0x1AB8 +#define RK3568_ESMART1_REGION3_SCL_CTRL 0x1AC0 +#define RK3568_ESMART1_REGION3_SCL_FACTOR_YRGB 0x1AC4 +#define RK3568_ESMART1_REGION3_SCL_FACTOR_CBR 0x1AC8 +#define RK3568_ESMART1_REGION3_SCL_OFFSET 0x1ACC + +#define RK3568_SMART0_CTRL0 0x1C00 +#define RK3568_SMART0_CTRL1 0x1C04 +#define RK3568_SMART0_REGION0_CTRL 0x1C10 +#define RK3568_SMART0_REGION0_YRGB_MST 0x1C14 +#define RK3568_SMART0_REGION0_CBR_MST 0x1C18 +#define RK3568_SMART0_REGION0_VIR 0x1C1C +#define RK3568_SMART0_REGION0_ACT_INFO 0x1C20 +#define RK3568_SMART0_REGION0_DSP_INFO 0x1C24 +#define RK3568_SMART0_REGION0_DSP_ST 0x1C28 +#define RK3568_SMART0_REGION0_SCL_CTRL 0x1C30 +#define RK3568_SMART0_REGION0_SCL_FACTOR_YRGB 0x1C34 +#define RK3568_SMART0_REGION0_SCL_FACTOR_CBR 0x1C38 +#define RK3568_SMART0_REGION0_SCL_OFFSET 0x1C3C +#define RK3568_SMART0_REGION1_CTRL 0x1C40 +#define RK3568_SMART0_REGION1_YRGB_MST 0x1C44 +#define RK3568_SMART0_REGION1_CBR_MST 0x1C48 +#define RK3568_SMART0_REGION1_VIR 0x1C4C +#define RK3568_SMART0_REGION1_ACT_INFO 0x1C50 +#define RK3568_SMART0_REGION1_DSP_INFO 0x1C54 +#define RK3568_SMART0_REGION1_DSP_ST 0x1C58 +#define RK3568_SMART0_REGION1_SCL_CTRL 0x1C60 +#define RK3568_SMART0_REGION1_SCL_FACTOR_YRGB 0x1C64 +#define RK3568_SMART0_REGION1_SCL_FACTOR_CBR 0x1C68 +#define RK3568_SMART0_REGION1_SCL_OFFSET 0x1C6C +#define RK3568_SMART0_REGION2_CTRL 0x1C70 +#define RK3568_SMART0_REGION2_YRGB_MST 0x1C74 +#define RK3568_SMART0_REGION2_CBR_MST 0x1C78 +#define RK3568_SMART0_REGION2_VIR 0x1C7C +#define RK3568_SMART0_REGION2_ACT_INFO 0x1C80 +#define RK3568_SMART0_REGION2_DSP_INFO 0x1C84 +#define RK3568_SMART0_REGION2_DSP_ST 0x1C88 +#define RK3568_SMART0_REGION2_SCL_CTRL 0x1C90 +#define RK3568_SMART0_REGION2_SCL_FACTOR_YRGB 0x1C94 +#define RK3568_SMART0_REGION2_SCL_FACTOR_CBR 0x1C98 +#define RK3568_SMART0_REGION2_SCL_OFFSET 0x1C9C +#define RK3568_SMART0_REGION3_CTRL 0x1CA0 +#define RK3568_SMART0_REGION3_YRGB_MST 0x1CA4 +#define RK3568_SMART0_REGION3_CBR_MST 0x1CA8 +#define RK3568_SMART0_REGION3_VIR 0x1CAC +#define RK3568_SMART0_REGION3_ACT_INFO 0x1CB0 +#define RK3568_SMART0_REGION3_DSP_INFO 0x1CB4 +#define RK3568_SMART0_REGION3_DSP_ST 0x1CB8 +#define RK3568_SMART0_REGION3_SCL_CTRL 0x1CC0 +#define RK3568_SMART0_REGION3_SCL_FACTOR_YRGB 0x1CC4 +#define RK3568_SMART0_REGION3_SCL_FACTOR_CBR 0x1CC8 +#define RK3568_SMART0_REGION3_SCL_OFFSET 0x1CCC + +#define RK3568_SMART1_CTRL0 0x1E00 +#define RK3568_SMART1_CTRL1 0x1E04 +#define RK3568_SMART1_REGION0_CTRL 0x1E10 +#define RK3568_SMART1_REGION0_YRGB_MST 0x1E14 +#define RK3568_SMART1_REGION0_CBR_MST 0x1E18 +#define RK3568_SMART1_REGION0_VIR 0x1E1C +#define RK3568_SMART1_REGION0_ACT_INFO 0x1E20 +#define RK3568_SMART1_REGION0_DSP_INFO 0x1E24 +#define RK3568_SMART1_REGION0_DSP_ST 0x1E28 +#define RK3568_SMART1_REGION0_SCL_CTRL 0x1E30 +#define RK3568_SMART1_REGION0_SCL_FACTOR_YRGB 0x1E34 +#define RK3568_SMART1_REGION0_SCL_FACTOR_CBR 0x1E38 +#define RK3568_SMART1_REGION0_SCL_OFFSET 0x1E3C +#define RK3568_SMART1_REGION1_CTRL 0x1E40 +#define RK3568_SMART1_REGION1_YRGB_MST 0x1E44 +#define RK3568_SMART1_REGION1_CBR_MST 0x1E48 +#define RK3568_SMART1_REGION1_VIR 0x1E4C +#define RK3568_SMART1_REGION1_ACT_INFO 0x1E50 +#define RK3568_SMART1_REGION1_DSP_INFO 0x1E54 +#define RK3568_SMART1_REGION1_DSP_ST 0x1E58 +#define RK3568_SMART1_REGION1_SCL_CTRL 0x1E60 +#define RK3568_SMART1_REGION1_SCL_FACTOR_YRGB 0x1E64 +#define RK3568_SMART1_REGION1_SCL_FACTOR_CBR 0x1E68 +#define RK3568_SMART1_REGION1_SCL_OFFSET 0x1E6C +#define RK3568_SMART1_REGION2_CTRL 0x1E70 +#define RK3568_SMART1_REGION2_YRGB_MST 0x1E74 +#define RK3568_SMART1_REGION2_CBR_MST 0x1E78 +#define RK3568_SMART1_REGION2_VIR 0x1E7C +#define RK3568_SMART1_REGION2_ACT_INFO 0x1E80 +#define RK3568_SMART1_REGION2_DSP_INFO 0x1E84 +#define RK3568_SMART1_REGION2_DSP_ST 0x1E88 +#define RK3568_SMART1_REGION2_SCL_CTRL 0x1E90 +#define RK3568_SMART1_REGION2_SCL_FACTOR_YRGB 0x1E94 +#define RK3568_SMART1_REGION2_SCL_FACTOR_CBR 0x1E98 +#define RK3568_SMART1_REGION2_SCL_OFFSET 0x1E9C +#define RK3568_SMART1_REGION3_CTRL 0x1EA0 +#define RK3568_SMART1_REGION3_YRGB_MST 0x1EA4 +#define RK3568_SMART1_REGION3_CBR_MST 0x1EA8 +#define RK3568_SMART1_REGION3_VIR 0x1EAC +#define RK3568_SMART1_REGION3_ACT_INFO 0x1EB0 +#define RK3568_SMART1_REGION3_DSP_INFO 0x1EB4 +#define RK3568_SMART1_REGION3_DSP_ST 0x1EB8 +#define RK3568_SMART1_REGION3_SCL_CTRL 0x1EC0 +#define RK3568_SMART1_REGION3_SCL_FACTOR_YRGB 0x1EC4 +#define RK3568_SMART1_REGION3_SCL_FACTOR_CBR 0x1EC8 +#define RK3568_SMART1_REGION3_SCL_OFFSET 0x1ECC + +/* HDR register definition */ +#define RK3568_HDR_LUT_CTRL 0x2000 +#define RK3568_HDR_LUT_MST 0x2004 +#define RK3568_SDR2HDR_CTRL 0x2010 +#define RK3568_HDR2SDR_CTRL 0x2020 +#define RK3568_HDR2SDR_SRC_RANGE 0x2024 +#define RK3568_HDR2SDR_NORMFACEETF 0x2028 +#define RK3568_HDR2SDR_DST_RANGE 0x202C +#define RK3568_HDR2SDR_NORMFACCGAMMA 0x2030 +#define RK3568_HDR_EETF_OETF_Y0 0x203C +#define RK3568_HDR_SAT_Y0 0x20C0 +#define RK3568_HDR_EOTF_OETF_Y0 0x20F0 +#define RK3568_HDR_OETF_DX_POW1 0x2200 +#define RK3568_HDR_OETF_XN1 0x2300 + #endif /* _ROCKCHIP_VOP_REG_H */