From 8a6091f2926aeb35567f2cccd6c1332dc9fab0e1 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Fri, 5 Nov 2021 09:02:23 +0800 Subject: [PATCH] mmc: dw_mmc-rockchip: Restore slot's clock if it's updated slot's clock is cached before calling ->set_ios for sub-driver. If the clock is updated by sub-driver, it's better to restore the cached slot's clock. Or we can see a unexpected clock as the driver didn't know the slot's clock is updated and still use the old clock to calculate divider. So we may see a lower clock. It theory, it's won't be a problem because any rate lower than 400k should be fine, and we even didn't start issuing any command during the lower clock. But still it's right to update slot's clock to reflect the correct clock and may fix some potential unknown problems. Signed-off-by: Shawn Lin Change-Id: I06581320547bb06c306da57e141d06f9206ea585 --- drivers/mmc/host/dw_mmc-rockchip.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c index aec06b9284a8..b0673f876317 100644 --- a/drivers/mmc/host/dw_mmc-rockchip.c +++ b/drivers/mmc/host/dw_mmc-rockchip.c @@ -50,8 +50,10 @@ static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios) * Note: div can only be 0 or 1, but div must be set to 1 for eMMC * DDR52 8-bit mode. */ - if (ios->clock < priv->f_min) + if (ios->clock < priv->f_min) { ios->clock = priv->f_min; + host->slot->clock = ios->clock; + } if (ios->bus_width == MMC_BUS_WIDTH_8 && ios->timing == MMC_TIMING_MMC_DDR52)