From 8a89e948a225b44434134aa7528f8d13ea278314 Mon Sep 17 00:00:00 2001 From: Xing Zheng Date: Thu, 9 Jan 2025 17:21:10 +0800 Subject: [PATCH] ARM: dts: rockchip: rk3506g-demo-display-control: fix noise dues to mclk and coeffs without matched The requirements of rk3506 codec are mainly divided into three sampling rate groups: 48/44.1/32kHz. And, the rk3506 codec has internal frequency division, the driver limits these three mclk inputs: #define MCLK_REFERENCE_8000 32768000 #define MCLK_REFERENCE_11025 45158400 #define MCLK_REFERENCE_12000 49152000 Therefore, it is necessary to add the "rockchip,mclk-no-set" property to the SAI4 to avoid switching the mclk frequency in the function of rockchip_sai_set_sysclk() after the codec configures mclk, causing the codec filter to work abnormally. Change-Id: Ic6cd0688287eb4c92c3b27bba4f60c46610c9006 Signed-off-by: Xing Zheng --- arch/arm/boot/dts/rk3506g-demo-display-control.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/rk3506g-demo-display-control.dts b/arch/arm/boot/dts/rk3506g-demo-display-control.dts index ec9438ffc3f8..1688896903ce 100644 --- a/arch/arm/boot/dts/rk3506g-demo-display-control.dts +++ b/arch/arm/boot/dts/rk3506g-demo-display-control.dts @@ -591,6 +591,7 @@ &sai1 { status = "okay"; + rockchip,mclk-no-set; pinctrl-names = "default"; pinctrl-0 = <&rm_io9_sai1_sclk &rm_io10_sai1_lrck @@ -600,6 +601,7 @@ &sai4 { status = "okay"; + rockchip,mclk-no-set; }; &saradc {