mirror of
https://github.com/hardkernel/linux.git
synced 2026-06-09 12:17:12 +09:00
oprofile/x86: fix msr access to reserved counters
commit cfc9c0b450 upstream.
During switching virtual counters there is access to perfctr msrs. If
the counter is not available this fails due to an invalid
address. This patch fixes this.
Signed-off-by: Robert Richter <robert.richter@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
committed by
Greg Kroah-Hartman
parent
daed371625
commit
8a9bd933fb
@@ -85,7 +85,7 @@ static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
|
||||
/* enable active counters */
|
||||
for (i = 0; i < NUM_COUNTERS; ++i) {
|
||||
int virt = op_x86_phys_to_virt(i);
|
||||
if (!counter_config[virt].enabled)
|
||||
if (!reset_value[virt])
|
||||
continue;
|
||||
rdmsrl(msrs->controls[i].addr, val);
|
||||
val &= model->reserved;
|
||||
@@ -121,7 +121,8 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
|
||||
|
||||
/* setup reset_value */
|
||||
for (i = 0; i < NUM_VIRT_COUNTERS; ++i) {
|
||||
if (counter_config[i].enabled)
|
||||
if (counter_config[i].enabled
|
||||
&& msrs->counters[op_x86_virt_to_phys(i)].addr)
|
||||
reset_value[i] = counter_config[i].count;
|
||||
else
|
||||
reset_value[i] = 0;
|
||||
@@ -146,9 +147,7 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
|
||||
/* enable active counters */
|
||||
for (i = 0; i < NUM_COUNTERS; ++i) {
|
||||
int virt = op_x86_phys_to_virt(i);
|
||||
if (!counter_config[virt].enabled)
|
||||
continue;
|
||||
if (!msrs->counters[i].addr)
|
||||
if (!reset_value[virt])
|
||||
continue;
|
||||
|
||||
/* setup counter registers */
|
||||
|
||||
Reference in New Issue
Block a user