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crypto: rockchip: crypto v2: compatible with rng modules

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Crypto V2 regs should divided into two parts when rng is belonging
to crypto module.

Change-Id: Ib976851b845ff8cdccc607a677266bb61f54ae18
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
This commit is contained in:
Lin Jinhan
2021-02-23 15:01:52 +08:00
committed by Tao Huang
parent 1dc8aff822
commit 8ac6165349
5 changed files with 43 additions and 31 deletions
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9
drivers/crypto/rockchip/rk_crypto_core.c
View File

@@ -34,6 +34,7 @@
.hw_init = rk_hw_crypto_v1_init,\
.hw_deinit = rk_hw_crypto_v1_deinit,\
.hw_info_size = sizeof(struct rk_hw_crypto_v1_info),\
.default_pka_offset = 0,\
}
#define RK_CRYPTO_V2_SOC_DATA_INIT(names, soft_aes_192) {\
@@ -47,6 +48,7 @@
.hw_init = rk_hw_crypto_v2_init,\
.hw_deinit = rk_hw_crypto_v2_deinit,\
.hw_info_size = sizeof(struct rk_hw_crypto_v2_info),\
.default_pka_offset = 0x0480,\
}
static int rk_crypto_enable_clk(struct rk_crypto_info *dev)
@@ -524,6 +526,7 @@ static int rk_crypto_probe(struct platform_device *pdev)
spin_lock_init(&crypto_info->lock);
/* get crypto base */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
crypto_info->reg = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(crypto_info->reg)) {
@@ -531,6 +534,12 @@ static int rk_crypto_probe(struct platform_device *pdev)
goto err_crypto;
}
/* get pka base, if pka reg not set, pka reg = crypto + pka offset */
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
crypto_info->pka_reg = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(crypto_info->pka_reg))
crypto_info->pka_reg = crypto_info->reg + crypto_info->soc_data->default_pka_offset;
crypto_info->clks_num = devm_clk_bulk_get_all(&pdev->dev, &crypto_info->clk_bulks);
if (crypto_info->clks_num < 0) {
dev_err(&pdev->dev, "failed to get clks property\n");

3
drivers/crypto/rockchip/rk_crypto_core.h
View File

@@ -33,7 +33,7 @@ struct rk_crypto_soc_data {
int rsts_num;
unsigned int hw_info_size;
bool use_soft_aes192;
int default_pka_offset;
int (*hw_init)(struct device *dev, void *hw_info);
void (*hw_deinit)(struct device *dev, void *hw_info);
};
@@ -42,6 +42,7 @@ struct rk_crypto_info {
struct device *dev;
struct reset_control *rst;
void __iomem *reg;
void __iomem *pka_reg;
int irq;
struct crypto_queue queue;
struct tasklet_struct queue_task;

2
drivers/crypto/rockchip/rk_crypto_v2_akcipher.c
View File

@@ -266,7 +266,7 @@ static int rk_rsa_init_tfm(struct crypto_akcipher *tfm)
ctx->dev = info;
rk_pka_set_crypto_base(ctx->dev->reg);
rk_pka_set_crypto_base(ctx->dev->pka_reg);
return 0;
}

14
drivers/crypto/rockchip/rk_crypto_v2_pka.c
View File

@@ -75,8 +75,8 @@ enum pka_opcode {
#define PKA_CLK_ENABLE()
#define PKA_CLK_DISABLE()
#define PKA_READ(offset) readl_relaxed((crypto_base) + (offset))
#define PKA_WRITE(val, offset) writel_relaxed((val), (crypto_base) + (offset))
#define PKA_READ(offset) readl_relaxed((pka_base) + (offset))
#define PKA_WRITE(val, offset) writel_relaxed((val), (pka_base) + (offset))
#define PKA_BIGNUM_WORDS(x) (rk_bn_get_size(x) / sizeof(u32))
@@ -89,7 +89,7 @@ enum pka_opcode {
cpu_relax(); \
} while (0)
#define PKA_GET_SRAM_ADDR(addr) ((void *)(crypto_base + CRYPTO_SRAM_BASE + (addr)))
#define PKA_GET_SRAM_ADDR(addr) ((void *)(pka_base + CRYPTO_SRAM_BASE + (addr)))
/*************************************************************************
* Macros for calling PKA operations (names according to operation issue *
@@ -148,7 +148,7 @@ enum pka_opcode {
#define RK_PKA_TERMINATE() pka_exec_op(PKA_OPCODE_TERMINATE, 0, 0, 0, 0, 0, 0, 0, 0)
/********************* Private Variable Definition ***************************/
static void __iomem *crypto_base;
static void __iomem *pka_base;
static void pka_word_memcpy(u32 *dst, u32 *src, u32 size)
{
@@ -170,7 +170,7 @@ static int pka_wait_pipe_rdy(void)
{
u32 reg_val = 0;
return readl_poll_timeout(crypto_base + CRYPTO_PKA_PIPE_RDY, reg_val,
return readl_poll_timeout(pka_base + CRYPTO_PKA_PIPE_RDY, reg_val,
reg_val, PKA_POLL_PERIOD_US, PKA_POLL_TIMEOUT_US);
}
@@ -178,7 +178,7 @@ static int pka_wait_done(void)
{
u32 reg_val = 0;
return readl_poll_timeout(crypto_base + CRYPTO_PKA_DONE, reg_val,
return readl_poll_timeout(pka_base + CRYPTO_PKA_DONE, reg_val,
reg_val, PKA_POLL_PERIOD_US, PKA_POLL_TIMEOUT_US);
}
@@ -597,7 +597,7 @@ static u32 pka_calc_and_init_np(struct rk_bignum *bn, u8 r_t0, u8 r_t1, u8 r_t2)
void rk_pka_set_crypto_base(void __iomem *base)
{
crypto_base = base;
pka_base = base;
}
/**

46
drivers/crypto/rockchip/rk_crypto_v2_reg.h
View File

@@ -241,26 +241,28 @@
#define CRYPTO_HASH_VALID 0x03e4
#define CRYPTO_HASH_IS_VALID BIT(0)
#define CRYPTO_RAM_CTL 0x0480
#define CRYPTO_PKA_BASE_OFFSET 0x0480
#define CRYPTO_RAM_CTL (0x0480 - CRYPTO_PKA_BASE_OFFSET)
#define CRYPTO_RAM_PKA_RDY BIT(0)
#define CRYPTO_RAM_ST 0x0484
#define CRYPTO_RAM_ST (0x0484 - CRYPTO_PKA_BASE_OFFSET)
#define CRYPTO_CLK_RAM_RDY BIT(0)
#define CRYPTO_CLK_RAM_RDY_MASK BIT(0)
#define CRYPTO_DEBUG_CTL 0x04a0
#define CRYPTO_DEBUG_CTL (0x04a0 - CRYPTO_PKA_BASE_OFFSET)
#define CRYPTO_DEBUG_MODE BIT(0)
#define CRYPTO_DEBUG_ST 0x04a4
#define CRYPTO_DEBUG_ST (0x04a4 - CRYPTO_PKA_BASE_OFFSET)
#define CRYPTO_PKA_DEBUG_CLK_EN BIT(0)
#define CRYPTO_DEBUG_MONITOR 0x04a8
#define CRYPTO_DEBUG_MONITOR (0x04a8 - CRYPTO_PKA_BASE_OFFSET)
/* MAP0 ~ MAP31 */
#define CRYPTO_MEMORY_MAP0 0x00800
#define CRYPTO_MEMORY_MAP0 (0x00800 - CRYPTO_PKA_BASE_OFFSET)
#define CRYPTO_MAP_REG_NUM 32
#define CRYPTO_OPCODE 0x00880
#define CRYPTO_OPCODE (0x00880 - CRYPTO_PKA_BASE_OFFSET)
#define CRYPTO_OPCODE_TAG_SHIFT 0
#define CRYPTO_OPCODE_R_SHIFT 6
#define CRYPTO_OPCODE_R_DIS_SHIFT 11
@@ -271,7 +273,7 @@
#define CRYPTO_OPCODE_LEN_SHIFT 24
#define CRYPTO_OPCODE_CODE_SHIFT 27
#define CRYPTO_N_NP_T0_T1_ADDR 0x00884
#define CRYPTO_N_NP_T0_T1_ADDR (0x00884 - CRYPTO_PKA_BASE_OFFSET)
#define CRYPTO_N_VIRTUAL_ADDR_SHIFT 0
#define CRYPTO_N_VIRTUAL_ADDR_MASK 0x0000001f
#define CRYPTO_NP_VIRTUAL_ADDR_SHIFT 5
@@ -281,7 +283,7 @@
#define CRYPTO_T1_VIRTUAL_ADDR_SHIFT 15
#define CRYPTO_T1_VIRTUAL_ADDR_MASK 0x000f8000
#define CRYPTO_PKA_STATUS 0x00888
#define CRYPTO_PKA_STATUS (0x00888 - CRYPTO_PKA_BASE_OFFSET)
#define CRYPTO_PKA_PIPE_IS_RDY BIT(0)
#define CRYPTO_PKA_BUSY BIT(1)
#define CRYPTO_PKA_ALU_OUT_ZERO BIT(2)
@@ -296,23 +298,23 @@
#define CRYPTO_PKA_TAG_STATUS_SHIFT 14
#define CRYPTO_PKA_TAG_STATUS_MASK 0x0003c000
#define CRYPTO_PKA_SW_RESET 0x0088C
#define CRYPTO_PKA_SW_RESET (0x0088C - CRYPTO_PKA_BASE_OFFSET)
/* PKA_L0 ~ PKA_L7 */
#define CRYPTO_PKA_L0 0x00890
#define CRYPTO_PKA_L0 (0x00890 - CRYPTO_PKA_BASE_OFFSET)
#define CRYPTO_LEN_REG_NUM 8
#define CRYPTO_PKA_PIPE_RDY 0x008B0
#define CRYPTO_PKA_DONE 0x008B4
#define CRYPTO_PKA_MON_SELECT 0x008B8
#define CRYPTO_PKA_DEBUG_REG_EN 0x008BC
#define CRYPTO_DEBUG_CNT_ADDR 0x008C0
#define CRYPTO_DEBUG_EXT_ADDR 0x008C4
#define CRYPTO_PKA_DEBUG_HALT 0x008C8
#define CRYPTO_PKA_MON_READ 0x008D0
#define CRYPTO_PKA_INT_ENA 0x008D4
#define CRYPTO_PKA_INT_ST 0x008D8
#define CRYPTO_SRAM_BASE 0x01000
#define CRYPTO_PKA_PIPE_RDY (0x008B0 - CRYPTO_PKA_BASE_OFFSET)
#define CRYPTO_PKA_DONE (0x008B4 - CRYPTO_PKA_BASE_OFFSET)
#define CRYPTO_PKA_MON_SELECT (0x008B8 - CRYPTO_PKA_BASE_OFFSET)
#define CRYPTO_PKA_DEBUG_REG_EN (0x008BC - CRYPTO_PKA_BASE_OFFSET)
#define CRYPTO_DEBUG_CNT_ADDR (0x008C0 - CRYPTO_PKA_BASE_OFFSET)
#define CRYPTO_DEBUG_EXT_ADDR (0x008C4 - CRYPTO_PKA_BASE_OFFSET)
#define CRYPTO_PKA_DEBUG_HALT (0x008C8 - CRYPTO_PKA_BASE_OFFSET)
#define CRYPTO_PKA_MON_READ (0x008D0 - CRYPTO_PKA_BASE_OFFSET)
#define CRYPTO_PKA_INT_ENA (0x008D4 - CRYPTO_PKA_BASE_OFFSET)
#define CRYPTO_PKA_INT_ST (0x008D8 - CRYPTO_PKA_BASE_OFFSET)
#define CRYPTO_SRAM_BASE (0x01000 - CRYPTO_PKA_BASE_OFFSET)
#define CRYPTO_SRAM_SIZE 0x01000
enum endian_mode {