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drm/rockchip: support rk3328 vop
Change-Id: Ic8c1073a22b62fc9a1b2e758429298538727c20e Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
This commit is contained in:
Mark Yao
@@ -550,6 +550,83 @@ static const struct vop_data rk322x_vop = {
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.win_size = ARRAY_SIZE(rk3368_vop_win_data),
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};
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static const struct vop_ctrl rk3328_ctrl_data = {
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.standby = VOP_REG(RK3328_SYS_CTRL, 0x1, 22),
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.auto_gate_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 23),
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.htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
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.hact_st_end = VOP_REG(RK3328_DSP_HACT_ST_END, 0x1fff1fff, 0),
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.vtotal_pw = VOP_REG(RK3328_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
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.vact_st_end = VOP_REG(RK3328_DSP_VACT_ST_END, 0x1fff1fff, 0),
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.vact_st_end_f1 = VOP_REG(RK3328_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
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.vs_st_end_f1 = VOP_REG(RK3328_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
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.hpost_st_end = VOP_REG(RK3328_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
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.vpost_st_end = VOP_REG(RK3328_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
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.vpost_st_end_f1 = VOP_REG(RK3328_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
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.dsp_interlace = VOP_REG(RK3328_DSP_CTRL0, 0x1, 10),
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.dsp_layer_sel = VOP_REG(RK3328_DSP_CTRL1, 0xff, 8),
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.post_lb_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 18),
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.global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11),
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.overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16),
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.core_dclk_div = VOP_REG(RK3328_DSP_CTRL0, 0x1, 4),
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.p2i_en = VOP_REG(RK3328_DSP_CTRL0, 0x1, 5),
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.rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12),
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.hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13),
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.edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14),
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.mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15),
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.rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 16),
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.hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 20),
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.edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 24),
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.mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 28),
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.dither_down = VOP_REG(RK3328_DSP_CTRL1, 0xf, 1),
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.dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6),
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.dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12),
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.dsp_ccir656_avg = VOP_REG(RK3328_DSP_CTRL0, 0x1, 20),
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.dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18),
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.dsp_lut_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 0),
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.out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0),
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.xmirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 22),
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.ymirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 23),
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.dsp_background = VOP_REG(RK3328_DSP_BG, 0xffffffff, 0),
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.cfg_done = VOP_REG(RK3328_REG_CFG_DONE, 0x1, 0),
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};
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static const struct vop_intr rk3328_vop_intr = {
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.intrs = rk3368_vop_intrs,
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.nintrs = ARRAY_SIZE(rk3368_vop_intrs),
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.line_flag_num[0] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 0),
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.line_flag_num[1] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 16),
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.status = VOP_REG_MASK(RK3328_INTR_STATUS0, 0xffff, 0),
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.enable = VOP_REG_MASK(RK3328_INTR_EN0, 0xffff, 0),
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.clear = VOP_REG_MASK(RK3328_INTR_CLEAR0, 0xffff, 0),
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};
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static const struct vop_win_data rk3328_vop_win_data[] = {
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{ .base = 0xd0, .phy = &rk3288_win01_data,
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.type = DRM_PLANE_TYPE_PRIMARY },
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{ .base = 0x1d0, .phy = &rk3288_win01_data,
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.type = DRM_PLANE_TYPE_OVERLAY },
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{ .base = 0x2d0, .phy = &rk3288_win01_data,
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.type = DRM_PLANE_TYPE_OVERLAY },
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{ .base = 0x3d0, .phy = &rk3288_win01_data,
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.type = DRM_PLANE_TYPE_CURSOR },
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};
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static const struct vop_data rk3328_vop = {
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.version = VOP_VERSION(3, 8),
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.feature = VOP_FEATURE_OUTPUT_10BIT,
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.max_input = {4096, 8192},
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.max_output = {4096, 2160},
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.intr = &rk3328_vop_intr,
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.ctrl = &rk3328_ctrl_data,
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.win = rk3328_vop_win_data,
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.win_size = ARRAY_SIZE(rk3328_vop_win_data),
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};
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static const struct vop_scl_regs rk3066_win_scl = {
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.scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
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.scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
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@@ -651,6 +728,8 @@ static const struct of_device_id vop_driver_dt_match[] = {
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.data = &rk3399_vop_lit },
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{ .compatible = "rockchip,rk322x-vop",
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.data = &rk322x_vop },
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{ .compatible = "rockchip,rk3328-vop",
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.data = &rk3328_vop },
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{},
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};
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MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
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@@ -664,6 +664,175 @@
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#define RK3399_GAMMA_LUT_ADDR 0x2000
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/* rk3399 register definition end */
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/* rk3328 register definition end */
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#define RK3328_REG_CFG_DONE 0x00000000
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#define RK3328_VERSION_INFO 0x00000004
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#define RK3328_SYS_CTRL 0x00000008
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#define RK3328_SYS_CTRL1 0x0000000c
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#define RK3328_DSP_CTRL0 0x00000010
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#define RK3328_DSP_CTRL1 0x00000014
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#define RK3328_DSP_BG 0x00000018
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#define RK3328_AUTO_GATING_EN 0x0000003c
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#define RK3328_LINE_FLAG 0x00000040
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#define RK3328_VOP_STATUS 0x00000044
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#define RK3328_BLANKING_VALUE 0x00000048
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#define RK3328_WIN0_DSP_BG 0x00000050
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#define RK3328_WIN1_DSP_BG 0x00000054
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#define RK3328_DBG_PERF_LATENCY_CTRL0 0x000000c0
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#define RK3328_DBG_PERF_RD_MAX_LATENCY_NUM0 0x000000c4
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#define RK3328_DBG_PERF_RD_LATENCY_THR_NUM0 0x000000c8
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#define RK3328_DBG_PERF_RD_LATENCY_SAMP_NUM0 0x000000cc
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#define RK3328_INTR_EN0 0x000000e0
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#define RK3328_INTR_CLEAR0 0x000000e4
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#define RK3328_INTR_STATUS0 0x000000e8
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#define RK3328_INTR_RAW_STATUS0 0x000000ec
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#define RK3328_INTR_EN1 0x000000f0
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#define RK3328_INTR_CLEAR1 0x000000f4
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#define RK3328_INTR_STATUS1 0x000000f8
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#define RK3328_INTR_RAW_STATUS1 0x000000fc
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#define RK3328_WIN0_CTRL0 0x00000100
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#define RK3328_WIN0_CTRL1 0x00000104
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#define RK3328_WIN0_COLOR_KEY 0x00000108
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#define RK3328_WIN0_VIR 0x0000010c
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#define RK3328_WIN0_YRGB_MST 0x00000110
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#define RK3328_WIN0_CBR_MST 0x00000114
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#define RK3328_WIN0_ACT_INFO 0x00000118
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#define RK3328_WIN0_DSP_INFO 0x0000011c
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#define RK3328_WIN0_DSP_ST 0x00000120
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#define RK3328_WIN0_SCL_FACTOR_YRGB 0x00000124
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#define RK3328_WIN0_SCL_FACTOR_CBR 0x00000128
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#define RK3328_WIN0_SCL_OFFSET 0x0000012c
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#define RK3328_WIN0_SRC_ALPHA_CTRL 0x00000130
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#define RK3328_WIN0_DST_ALPHA_CTRL 0x00000134
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#define RK3328_WIN0_FADING_CTRL 0x00000138
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#define RK3328_WIN0_CTRL2 0x0000013c
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#define RK3328_DBG_WIN0_REG0 0x000001f0
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#define RK3328_DBG_WIN0_REG1 0x000001f4
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#define RK3328_DBG_WIN0_REG2 0x000001f8
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#define RK3328_DBG_WIN0_RESERVED 0x000001fc
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#define RK3328_WIN1_CTRL0 0x00000200
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#define RK3328_WIN1_CTRL1 0x00000204
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#define RK3328_WIN1_COLOR_KEY 0x00000208
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#define RK3328_WIN1_VIR 0x0000020c
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#define RK3328_WIN1_YRGB_MST 0x00000210
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#define RK3328_WIN1_CBR_MST 0x00000214
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#define RK3328_WIN1_ACT_INFO 0x00000218
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#define RK3328_WIN1_DSP_INFO 0x0000021c
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#define RK3328_WIN1_DSP_ST 0x00000220
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#define RK3328_WIN1_SCL_FACTOR_YRGB 0x00000224
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#define RK3328_WIN1_SCL_FACTOR_CBR 0x00000228
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#define RK3328_WIN1_SCL_OFFSET 0x0000022c
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#define RK3328_WIN1_SRC_ALPHA_CTRL 0x00000230
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#define RK3328_WIN1_DST_ALPHA_CTRL 0x00000234
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#define RK3328_WIN1_FADING_CTRL 0x00000238
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#define RK3328_WIN1_CTRL2 0x0000023c
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#define RK3328_DBG_WIN1_REG0 0x000002f0
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#define RK3328_DBG_WIN1_REG1 0x000002f4
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#define RK3328_DBG_WIN1_REG2 0x000002f8
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#define RK3328_DBG_WIN1_RESERVED 0x000002fc
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#define RK3328_WIN2_CTRL0 0x00000300
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#define RK3328_WIN2_CTRL1 0x00000304
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#define RK3328_WIN2_COLOR_KEY 0x00000308
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#define RK3328_WIN2_VIR 0x0000030c
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#define RK3328_WIN2_YRGB_MST 0x00000310
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#define RK3328_WIN2_CBR_MST 0x00000314
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#define RK3328_WIN2_ACT_INFO 0x00000318
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#define RK3328_WIN2_DSP_INFO 0x0000031c
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#define RK3328_WIN2_DSP_ST 0x00000320
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#define RK3328_WIN2_SCL_FACTOR_YRGB 0x00000324
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#define RK3328_WIN2_SCL_FACTOR_CBR 0x00000328
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#define RK3328_WIN2_SCL_OFFSET 0x0000032c
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#define RK3328_WIN2_SRC_ALPHA_CTRL 0x00000330
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#define RK3328_WIN2_DST_ALPHA_CTRL 0x00000334
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#define RK3328_WIN2_FADING_CTRL 0x00000338
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#define RK3328_WIN2_CTRL2 0x0000033c
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#define RK3328_DBG_WIN2_REG0 0x000003f0
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#define RK3328_DBG_WIN2_REG1 0x000003f4
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#define RK3328_DBG_WIN2_REG2 0x000003f8
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#define RK3328_DBG_WIN2_RESERVED 0x000003fc
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#define RK3328_WIN3_CTRL0 0x00000400
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#define RK3328_WIN3_CTRL1 0x00000404
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#define RK3328_WIN3_COLOR_KEY 0x00000408
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#define RK3328_WIN3_VIR 0x0000040c
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#define RK3328_WIN3_YRGB_MST 0x00000410
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#define RK3328_WIN3_CBR_MST 0x00000414
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#define RK3328_WIN3_ACT_INFO 0x00000418
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#define RK3328_WIN3_DSP_INFO 0x0000041c
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#define RK3328_WIN3_DSP_ST 0x00000420
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#define RK3328_WIN3_SCL_FACTOR_YRGB 0x00000424
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#define RK3328_WIN3_SCL_FACTOR_CBR 0x00000428
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#define RK3328_WIN3_SCL_OFFSET 0x0000042c
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#define RK3328_WIN3_SRC_ALPHA_CTRL 0x00000430
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#define RK3328_WIN3_DST_ALPHA_CTRL 0x00000434
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#define RK3328_WIN3_FADING_CTRL 0x00000438
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#define RK3328_WIN3_CTRL2 0x0000043c
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#define RK3328_DBG_WIN3_REG0 0x000004f0
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#define RK3328_DBG_WIN3_REG1 0x000004f4
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#define RK3328_DBG_WIN3_REG2 0x000004f8
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#define RK3328_DBG_WIN3_RESERVED 0x000004fc
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#define RK3328_HWC_CTRL0 0x00000500
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#define RK3328_HWC_CTRL1 0x00000504
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#define RK3328_HWC_MST 0x00000508
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#define RK3328_HWC_DSP_ST 0x0000050c
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#define RK3328_HWC_SRC_ALPHA_CTRL 0x00000510
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#define RK3328_HWC_DST_ALPHA_CTRL 0x00000514
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#define RK3328_HWC_FADING_CTRL 0x00000518
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#define RK3328_HWC_RESERVED1 0x0000051c
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#define RK3328_POST_DSP_HACT_INFO 0x00000600
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#define RK3328_POST_DSP_VACT_INFO 0x00000604
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#define RK3328_POST_SCL_FACTOR_YRGB 0x00000608
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#define RK3328_POST_RESERVED 0x0000060c
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#define RK3328_POST_SCL_CTRL 0x00000610
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#define RK3328_POST_DSP_VACT_INFO_F1 0x00000614
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#define RK3328_DSP_HTOTAL_HS_END 0x00000618
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#define RK3328_DSP_HACT_ST_END 0x0000061c
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#define RK3328_DSP_VTOTAL_VS_END 0x00000620
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#define RK3328_DSP_VACT_ST_END 0x00000624
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#define RK3328_DSP_VS_ST_END_F1 0x00000628
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#define RK3328_DSP_VACT_ST_END_F1 0x0000062c
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#define RK3328_BCSH_COLOR_BAR 0x00000640
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#define RK3328_BCSH_BCS 0x00000644
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#define RK3328_BCSH_H 0x00000648
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#define RK3328_BCSH_CTRL 0x0000064c
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#define RK3328_FRC_LOWER01_0 0x00000678
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#define RK3328_FRC_LOWER01_1 0x0000067c
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#define RK3328_FRC_LOWER10_0 0x00000680
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#define RK3328_FRC_LOWER10_1 0x00000684
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#define RK3328_FRC_LOWER11_0 0x00000688
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#define RK3328_FRC_LOWER11_1 0x0000068c
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#define RK3328_DBG_POST_REG0 0x000006e8
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#define RK3328_DBG_POST_RESERVED 0x000006ec
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#define RK3328_DBG_DATAO 0x000006f0
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#define RK3328_DBG_DATAO_2 0x000006f4
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/* sdr to hdr */
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#define RK3328_SDR2HDR_CTRL 0x00000700
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#define RK3328_EOTF_OETF_Y0 0x00000704
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#define RK3328_RESERVED0001 0x00000708
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#define RK3328_RESERVED0002 0x0000070c
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#define RK3328_EOTF_OETF_Y1 0x00000710
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#define RK3328_EOTF_OETF_Y64 0x0000080c
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#define RK3328_OETF_DX_DXPOW1 0x00000810
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#define RK3328_OETF_DX_DXPOW64 0x0000090c
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#define RK3328_OETF_XN1 0x00000910
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#define RK3328_OETF_XN63 0x00000a08
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/* hdr to sdr */
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#define RK3328_HDR2SDR_CTRL 0x00000a10
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#define RK3328_HDR2SDR_SRC_RANGE 0x00000a14
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#define RK3328_HDR2SDR_NORMFACEETF 0x00000a18
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#define RK3328_RESERVED0003 0x00000a1c
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#define RK3328_HDR2SDR_DST_RANGE 0x00000a20
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#define RK3328_HDR2SDR_NORMFACCGAMMA 0x00000a24
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#define RK3328_EETF_OETF_Y0 0x00000a28
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#define RK3328_SAT_Y0 0x00000a2c
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#define RK3328_EETF_OETF_Y1 0x00000a30
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#define RK3328_SAT_Y1 0x00000ab0
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#define RK3328_SAT_Y8 0x00000acc
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#define RK3328_HWC_LUT_ADDR 0x00000c00
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/* rk3036 register definition */
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#define RK3036_SYS_CTRL 0x00
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#define RK3036_DSP_CTRL0 0x04
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