From 8b7704805eaffc9bdfbd8afd54cd23ecbc7899d5 Mon Sep 17 00:00:00 2001 From: Chuangcheng Peng Date: Mon, 15 Apr 2019 13:57:18 +0800 Subject: [PATCH] dvb: tm2 support hiu1 [1/2] PD#SWPL-6806 Problem: tm2 support hiu1 in bringup Solution: tm2 support hiu1 in bringup Verify: veify at AB301 Change-Id: If158788a29b6e96395cb2f546276f516c1cb7a0b Signed-off-by: Chuangcheng Peng --- .../stream_input/parser/hw_demux/aml_dmx.c | 13 ++++++++++--- .../stream_input/parser/hw_demux/aml_dvb.c | 8 ++++---- .../stream_input/parser/hw_demux/c_stb_define.h | 7 ++++--- 3 files changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dmx.c b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dmx.c index 724bc0c35b15..3b2b9a7106f3 100644 --- a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dmx.c +++ b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dmx.c @@ -1715,7 +1715,9 @@ static void stb_enable(struct aml_dvb *dvb) WRITE_MPEG_REG(TS_HIU1_CONFIG, (demux_skipbyte << FILE_M2TS_SKIP_BYTES_HIU1) | (hiu << TS_HIU_ENABLE_HIU1) | - (fec_clk << FEC_CLK_DIV_HIU1)); + (fec_clk << FEC_CLK_DIV_HIU1) | + (0xBB << TS_PACKAGE_LENGTH_SUB_1_HIU1) | + (0x47 << FEC_SYNC_BYTE_HIU1)); } else { /* invert ts out clk end */ WRITE_MPEG_REG(TS_FILE_CONFIG, @@ -3140,9 +3142,15 @@ static int dmx_enable(struct aml_dmx *dmx) (7<id, TS_HIU_CTL, + if (fec_sel != 8) { + DMX_WRITE_REG(dmx->id, TS_HIU_CTL, // (0 << LAST_BURST_THRESHOLD) | (hi_bsf << USE_HI_BSF_INTERFACE)); + } else { + DMX_WRITE_REG(dmx->id, TS_HIU_CTL, + (1 << PDTS_WR_SEL) | + (hi_bsf << USE_HI_BSF_INTERFACE)); + } if (fec_sel == -1) { dmx_cascade_set(dmx->id,dmx->source); @@ -3189,7 +3197,6 @@ static int dmx_enable(struct aml_dmx *dmx) (dmx->id != dmx->source-AM_TS_SRC_DMX0)) dmx_cascade_set(dmx->id,dmx->source); } - return 0; } diff --git a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dvb.c b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dvb.c index 800c77e9d483..1e5bcdf93e02 100644 --- a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dvb.c +++ b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dvb.c @@ -890,10 +890,10 @@ static ssize_t stb_store_source(struct class *class, src = DMX_SOURCE_FRONT2; else if (!strncmp("ts3", buf, 3)) src = DMX_SOURCE_FRONT3; - else if (!strncmp("hiu", buf, 3)) - src = DMX_SOURCE_DVR0; else if (!strncmp("hiu1", buf, 4)) src = DMX_SOURCE_DVR1; + else if (!strncmp("hiu", buf, 3)) + src = DMX_SOURCE_DVR0; else if (!strncmp("dmx0", buf, 4)) src = DMX_SOURCE_FRONT0 + 100; else if (!strncmp("dmx1", buf, 4)) @@ -1150,10 +1150,10 @@ static ssize_t demux##i##_store_source(struct class *class, \ src = DMX_SOURCE_FRONT1;\ } else if (!strncmp("ts2", buf, 3)) {\ src = DMX_SOURCE_FRONT2;\ + } else if (!strncmp("hiu1", buf, 4)) {\ + src = DMX_SOURCE_DVR1;\ } else if (!strncmp("hiu", buf, 3)) {\ src = DMX_SOURCE_DVR0;\ - } else if (!strncmp("hiu1", buf, 3)) {\ - src = DMX_SOURCE_DVR1;\ } else if (!strncmp("dmx0", buf, 4)) {\ src = DMX_SOURCE_FRONT0_OFFSET;\ } else if (!strncmp("dmx1", buf, 4)) {\ diff --git a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/c_stb_define.h b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/c_stb_define.h index 5f7f4e3e83f3..6b815b67bbd7 100644 --- a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/c_stb_define.h +++ b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/c_stb_define.h @@ -758,8 +758,8 @@ #define BYPASS_ENDIAN 3 #define SECTION_ENDIAN 0 -/* Bit 15:8 -- last_burst_threshold*/ -/* Bit 7 -- use hi_bsf interface*/ +/* Bit 10:9 -- PDTS_wr_sel: 0 select video_PDTS_wr_ptr; 1 select video_PDTS_wr_ptr_parser_B; */ +/* Bit 7:8 -- use hi_bsf interface*/ /* Bit 6:2 - fec_clk_div*/ /* Bit 1 ts_source_sel */ /* Bit 0 - Hiu TS generate enable */ @@ -770,7 +770,8 @@ /*#define TS_HIU_CTL_3 * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x25) // 0x16c5*/ /*----------- bit define -----------*/ -#define LAST_BURST_THRESHOLD 8 +//#define LAST_BURST_THRESHOLD 8 +#define PDTS_WR_SEL 9 #define USE_HI_BSF_INTERFACE 7 /* bit 15:0 -- base address for section buffer start