From 8b88e58c448dd13b022167ac4e074a4c0036a6da Mon Sep 17 00:00:00 2001
From: Xuhui Lin <xuhui.lin@rock-chips.com>
Date: Mon, 10 Feb 2025 18:46:03 +0800
Subject: [PATCH] arm64: dts: rockchip: rv1126b: Add spi nodes

Change-Id: Ia29b4a322f51664e5db478471e46db3c908d22bc
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rv1126b.dtsi | 32 +++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rv1126b.dtsi b/arch/arm64/boot/dts/rockchip/rv1126b.dtsi
index 861bb6f49b9f..fa5cea4d6a13 100644
--- a/arch/arm64/boot/dts/rockchip/rv1126b.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rv1126b.dtsi
@@ -41,6 +41,8 @@
 		rkcif_mipi_lvds2= &rkcif_mipi_lvds2;
 		rkcif_mipi_lvds3= &rkcif_mipi_lvds3;
 		serial0 = &uart0;
+		spi0 = &spi0;
+		spi1 = &spi1;
 	};
 
 	clocks {
@@ -942,6 +944,36 @@
 		status = "disabled";
 	};
 
+	spi0: spi@211e0000 {
+		compatible = "rockchip,rv1126b-spi", "rockchip,rk3066-spi";
+		reg = <0x211e0000 0x1000>;
+		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
+		clock-names = "spiclk", "apb_pclk";
+		dmas = <&dmac 40>, <&dmac 41>;
+		dma-names = "rx", "tx";
+		pinctrl-names = "default";
+		pinctrl-0 = <&spi0m0_clk_pins &spi0m0_csn0_pins &spi0m0_csn1_pins>;
+		status = "disabled";
+	};
+
+	spi1: spi@211f0000 {
+		compatible = "rockchip,rv1126b-spi", "rockchip,rk3066-spi";
+		reg = <0x211f0000 0x1000>;
+		interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
+		clock-names = "spiclk", "apb_pclk";
+		dmas = <&dmac 42>, <&dmac 43>;
+		dma-names = "rx", "tx";
+		pinctrl-names = "default";
+		pinctrl-0 = <&spi1m0_clk_pins &spi1m0_csn0_pins &spi1m0_csn1_pins>;
+		status = "disabled";
+	};
+
 	gic: interrupt-controller@21201000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;