From 8ba551e60d041353bd9db3c2185451455950e87b Mon Sep 17 00:00:00 2001 From: Shunqing Chen Date: Wed, 7 Apr 2021 09:10:10 +0800 Subject: [PATCH] drm: rockchip: rk628: post_process: recalculate dst clock Signed-off-by: Shunqing Chen Change-Id: I93388ba499f0d74c5f5c549decc83f3225ae1b82 --- drivers/gpu/drm/rockchip/rk628/rk628_post_process.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rk628/rk628_post_process.c b/drivers/gpu/drm/rockchip/rk628/rk628_post_process.c index d0f9e494244b..80fd257a6471 100644 --- a/drivers/gpu/drm/rockchip/rk628/rk628_post_process.c +++ b/drivers/gpu/drm/rockchip/rk628/rk628_post_process.c @@ -209,8 +209,9 @@ static void rk628_post_process_scaler_init(struct rk628_post_process *pp, static void rk628_post_process_bridge_pre_enable(struct drm_bridge *bridge) { struct rk628_post_process *pp = bridge_to_pp(bridge); - const struct drm_display_mode *src = &pp->src_mode; - const struct drm_display_mode *dst = &pp->dst_mode; + struct drm_display_mode *src = &pp->src_mode; + struct drm_display_mode *dst = &pp->dst_mode; + u64 dst_rate, src_rate; reset_control_assert(pp->rstc_decoder); udelay(10); @@ -224,6 +225,12 @@ static void rk628_post_process_bridge_pre_enable(struct drm_bridge *bridge) reset_control_deassert(pp->rstc_clk_rx); udelay(10); + src_rate = src->clock * 1000; + dst_rate = src_rate * dst->vdisplay * dst->htotal; + do_div(dst_rate, src->vdisplay * src->htotal); + do_div(dst_rate, 1000); + dst->clock = dst_rate; + clk_set_rate(pp->sclk_vop, dst->clock * 1000); clk_prepare_enable(pp->sclk_vop); reset_control_assert(pp->rstc_vop);