diff --git a/drivers/media/platform/rockchip/isp/Kconfig b/drivers/media/platform/rockchip/isp/Kconfig index 98a530a171f1..4f0518a33e9e 100644 --- a/drivers/media/platform/rockchip/isp/Kconfig +++ b/drivers/media/platform/rockchip/isp/Kconfig @@ -30,6 +30,10 @@ config VIDEO_ROCKCHIP_ISP_VERSION_V30 bool "isp30 for rk3588" default y if CPU_RK3588 +config VIDEO_ROCKCHIP_ISP_VERSION_V32 + bool "isp32 for rv1106" + default y if CPU_RV1106 + config VIDEO_ROCKCHIP_THUNDER_BOOT_ISP bool "Rockchip Image Signal Processing Thunderboot helper" depends on ROCKCHIP_THUNDER_BOOT diff --git a/drivers/media/platform/rockchip/isp/Makefile b/drivers/media/platform/rockchip/isp/Makefile index 52cac629003f..425d81d7489c 100644 --- a/drivers/media/platform/rockchip/isp/Makefile +++ b/drivers/media/platform/rockchip/isp/Makefile @@ -39,4 +39,9 @@ video_rkisp-$(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V30) += \ bridge.o \ bridge_v30.o +video_rkisp-$(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V32) += \ + capture_v32.o \ + isp_params_v32.o \ + isp_stats_v32.o + video_rkisp-$(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) += rkisp_tb_helper.o diff --git a/drivers/media/platform/rockchip/isp/capture.c b/drivers/media/platform/rockchip/isp/capture.c index 2b35580568da..0639b928e0d9 100644 --- a/drivers/media/platform/rockchip/isp/capture.c +++ b/drivers/media/platform/rockchip/isp/capture.c @@ -900,6 +900,7 @@ static int rkisp_set_fmt(struct rkisp_stream *stream, bool try) { const struct capture_fmt *fmt; + struct rkisp_vdev_node *node = &stream->vnode; const struct stream_config *config = stream->config; struct rkisp_device *dev = stream->ispdev; u32 planes, imagsize = 0; @@ -927,7 +928,8 @@ static int rkisp_set_fmt(struct rkisp_stream *stream, fmt = find_fmt(stream, pixm->pixelformat); if (!fmt) { v4l2_err(&dev->v4l2_dev, - "nonsupport pixelformat:%c%c%c%c\n", + "%s nonsupport pixelformat:%c%c%c%c\n", + node->vdev.name, pixm->pixelformat, pixm->pixelformat >> 8, pixm->pixelformat >> 16, @@ -949,7 +951,8 @@ static int rkisp_set_fmt(struct rkisp_stream *stream, pixm->width != dev->isp_sdev.out_crop.width && pixm->height != dev->isp_sdev.out_crop.height) { v4l2_warn(&dev->v4l2_dev, - "fullpath %dx%d no equal to isp output %dx%d\n", + "%s %dx%d no equal to isp output %dx%d\n", + node->vdev.name, pixm->width, pixm->height, dev->isp_sdev.out_crop.width, dev->isp_sdev.out_crop.height); @@ -959,12 +962,31 @@ static int rkisp_set_fmt(struct rkisp_stream *stream, pixm->width != stream->dcrop.width && pixm->height != stream->dcrop.height) { v4l2_warn(&dev->v4l2_dev, - "fbcpatch no scale %dx%d should equal to crop %dx%d\n", + "%s no scale %dx%d should equal to crop %dx%d\n", + node->vdev.name, pixm->width, pixm->height, stream->dcrop.width, stream->dcrop.height); pixm->width = stream->dcrop.width; pixm->height = stream->dcrop.height; } + } else if (stream->id == RKISP_STREAM_MPDS || stream->id == RKISP_STREAM_BPDS) { + struct rkisp_stream *t = &dev->cap_dev.stream[stream->conn_id]; + + if (pixm->pixelformat != t->out_fmt.pixelformat || + pixm->width != t->out_fmt.width / 4 || + pixm->height != t->out_fmt.height / 4) { + v4l2_warn(&dev->v4l2_dev, + "%s from %s, force to %dx%d %c%c%c%c\n", + node->vdev.name, t->vnode.vdev.name, + t->out_fmt.width / 4, t->out_fmt.height / 4, + t->out_fmt.pixelformat, + t->out_fmt.pixelformat >> 8, + t->out_fmt.pixelformat >> 16, + t->out_fmt.pixelformat >> 24); + pixm->pixelformat = t->out_fmt.pixelformat; + pixm->width = t->out_fmt.width / 4; + pixm->height = t->out_fmt.height / 4; + } } pixm->num_planes = fmt->mplanes; @@ -985,6 +1007,9 @@ static int rkisp_set_fmt(struct rkisp_stream *stream, ALIGN(pixm->width, 16) : pixm->width; h = (fmt->fmt_type == FMT_FBC) ? ALIGN(pixm->height, 16) : pixm->height; + /* mainpath for warp default */ + if (dev->cap_dev.wrap_line && stream->id == RKISP_STREAM_MP) + h = dev->cap_dev.wrap_line; width = i ? w / xsubs : w; height = i ? h / ysubs : h; @@ -1009,7 +1034,7 @@ static int rkisp_set_fmt(struct rkisp_stream *stream, /* 128bit AXI, 16byte align for bytesperline */ if ((dev->isp_ver == ISP_V20 && stream->id == RKISP_STREAM_SP) || - dev->isp_ver == ISP_V30) + dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) plane_fmt->bytesperline = ALIGN(plane_fmt->bytesperline, 16); plane_fmt->sizeimage = plane_fmt->bytesperline * height; @@ -1048,8 +1073,8 @@ static int rkisp_set_fmt(struct rkisp_stream *stream, } v4l2_dbg(1, rkisp_debug, &stream->ispdev->v4l2_dev, - "%s: stream: %d req(%d, %d) out(%d, %d)\n", __func__, - stream->id, pixm->width, pixm->height, + "%s: %s req(%d, %d) out(%d, %d)\n", __func__, + node->vdev.name, pixm->width, pixm->height, stream->out_fmt.width, stream->out_fmt.height); } @@ -1181,7 +1206,10 @@ static int rkisp_get_cmsk(struct rkisp_stream *stream, struct rkisp_cmsk_cfg *cf unsigned long lock_flags = 0; u32 i, win_en, mode; - if (dev->isp_ver != ISP_V30 || stream->id == RKISP_STREAM_FBC) { + if ((dev->isp_ver != ISP_V30 && dev->isp_ver != ISP_V32) || + stream->id == RKISP_STREAM_FBC || + stream->id == RKISP_STREAM_MPDS || + stream->id == RKISP_STREAM_BPDS) { v4l2_err(&dev->v4l2_dev, "%s not support\n", __func__); return -EINVAL; } @@ -1226,7 +1254,10 @@ static int rkisp_set_cmsk(struct rkisp_stream *stream, struct rkisp_cmsk_cfg *cf u32 height = dev->isp_sdev.out_crop.height; bool warn = false; - if (dev->isp_ver != ISP_V30 || stream->id == RKISP_STREAM_FBC) { + if ((dev->isp_ver != ISP_V30 && dev->isp_ver != ISP_V32) || + stream->id == RKISP_STREAM_FBC || + stream->id == RKISP_STREAM_MPDS || + stream->id == RKISP_STREAM_BPDS) { v4l2_err(&dev->v4l2_dev, "%s not support\n", __func__); return -EINVAL; } @@ -1510,7 +1541,9 @@ static struct v4l2_rect *rkisp_update_crop(struct rkisp_stream *stream, stream->id == RKISP_STREAM_DMATX0 || stream->id == RKISP_STREAM_DMATX1 || stream->id == RKISP_STREAM_DMATX2 || - stream->id == RKISP_STREAM_DMATX3) { + stream->id == RKISP_STREAM_DMATX3 || + stream->id == RKISP_STREAM_MPDS || + stream->id == RKISP_STREAM_BPDS) { sel->left = 0; sel->top = 0; sel->width = in->width; @@ -1678,7 +1711,7 @@ unreg: int rkisp_register_stream_vdevs(struct rkisp_device *dev) { struct rkisp_capture_device *cap_dev = &dev->cap_dev; - struct stream_config *mp_cfg = &rkisp_mp_stream_config; + struct stream_config *st_cfg = &rkisp_mp_stream_config; int ret = 0; memset(cap_dev, 0, sizeof(*cap_dev)); @@ -1687,25 +1720,32 @@ int rkisp_register_stream_vdevs(struct rkisp_device *dev) if (dev->isp_ver <= ISP_V13) { if (dev->isp_ver == ISP_V12) { - mp_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V12; - mp_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V12; + st_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V12; + st_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V12; } else if (dev->isp_ver == ISP_V13) { - mp_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V13; - mp_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V13; + st_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V13; + st_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V13; } ret = rkisp_register_stream_v1x(dev); } else if (dev->isp_ver == ISP_V20) { ret = rkisp_register_stream_v20(dev); } else if (dev->isp_ver == ISP_V21) { - mp_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V21; - mp_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V21; + st_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V21; + st_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V21; ret = rkisp_register_stream_v21(dev); } else if (dev->isp_ver == ISP_V30) { - mp_cfg->max_rsz_width = dev->hw_dev->is_unite ? + st_cfg->max_rsz_width = dev->hw_dev->is_unite ? CIF_ISP_INPUT_W_MAX_V30_UNITE : CIF_ISP_INPUT_W_MAX_V30; - mp_cfg->max_rsz_height = dev->hw_dev->is_unite ? + st_cfg->max_rsz_height = dev->hw_dev->is_unite ? CIF_ISP_INPUT_H_MAX_V30_UNITE : CIF_ISP_INPUT_H_MAX_V30; ret = rkisp_register_stream_v30(dev); + } else if (dev->isp_ver == ISP_V32) { + st_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V32; + st_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V32; + st_cfg = &rkisp_sp_stream_config; + st_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V32; + st_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V32; + ret = rkisp_register_stream_v32(dev); } return ret; } @@ -1720,6 +1760,8 @@ void rkisp_unregister_stream_vdevs(struct rkisp_device *dev) rkisp_unregister_stream_v21(dev); else if (dev->isp_ver == ISP_V30) rkisp_unregister_stream_v30(dev); + else if (dev->isp_ver == ISP_V32) + rkisp_unregister_stream_v32(dev); } void rkisp_mi_isr(u32 mis_val, struct rkisp_device *dev) @@ -1732,4 +1774,6 @@ void rkisp_mi_isr(u32 mis_val, struct rkisp_device *dev) rkisp_mi_v21_isr(mis_val, dev); else if (dev->isp_ver == ISP_V30) rkisp_mi_v30_isr(mis_val, dev); + else if (dev->isp_ver == ISP_V32) + rkisp_mi_v32_isr(mis_val, dev); } diff --git a/drivers/media/platform/rockchip/isp/capture.h b/drivers/media/platform/rockchip/isp/capture.h index 5a9251a9c973..418fbaabbe32 100644 --- a/drivers/media/platform/rockchip/isp/capture.h +++ b/drivers/media/platform/rockchip/isp/capture.h @@ -44,7 +44,9 @@ #define SP_VDEV_NAME DRIVER_NAME "_selfpath" #define MP_VDEV_NAME DRIVER_NAME "_mainpath" #define FBC_VDEV_NAME DRIVER_NAME "_fbcpath" -#define BP_VDEV_NAME DRIVER_NAME "_fullpath" +#define BP_VDEV_NAME DRIVER_NAME "_bypasspath" +#define MPDS_VDEV_NAME DRIVER_NAME "_mainpath_4x4sampling" +#define BPDS_VDEV_NAME DRIVER_NAME "_bypasspath_4x4sampling" #define VIR_VDEV_NAME DRIVER_NAME "_iqtool" #define DMATX0_VDEV_NAME DRIVER_NAME "_rawwr0" @@ -70,6 +72,8 @@ enum { RKISP_STREAM_DMATX3, RKISP_STREAM_FBC, RKISP_STREAM_BP, + RKISP_STREAM_MPDS, + RKISP_STREAM_BPDS, RKISP_STREAM_VIR, RKISP_MAX_STREAM, }; @@ -187,6 +191,7 @@ struct stream_config { u32 cr_offs_cnt_init; u32 y_base_ad_shd; u32 length; + u32 ctrl; } mi; struct { u32 ctrl; @@ -241,6 +246,7 @@ struct rkisp_stream { struct list_head buf_queue; struct rkisp_buffer *curr_buf; struct rkisp_buffer *next_buf; + struct rkisp_dummy_buffer dummy_buf; struct mutex apilock; bool streaming; bool stopping; @@ -275,6 +281,7 @@ struct rkisp_capture_device { struct rkisp_vir_cpy vir_cpy; atomic_t refcnt; u32 wait_line; + u32 wrap_line; bool is_done_early; }; diff --git a/drivers/media/platform/rockchip/isp/capture_v30.c b/drivers/media/platform/rockchip/isp/capture_v30.c index d012bc6aca5f..9782fe060d3e 100644 --- a/drivers/media/platform/rockchip/isp/capture_v30.c +++ b/drivers/media/platform/rockchip/isp/capture_v30.c @@ -67,7 +67,7 @@ static const struct capture_fmt bp_fmts[] = { } }; -struct stream_config rkisp_fbc_stream_config = { +static struct stream_config rkisp_fbc_stream_config = { .fmts = fbc_fmts, .fmt_size = ARRAY_SIZE(fbc_fmts), .frame_end_id = ISP3X_MI_MPFBC_FRAME, @@ -86,7 +86,7 @@ struct stream_config rkisp_fbc_stream_config = { }, }; -struct stream_config rkisp_bp_stream_config = { +static struct stream_config rkisp_bp_stream_config = { .fmts = bp_fmts, .fmt_size = ARRAY_SIZE(bp_fmts), .frame_end_id = ISP3X_MI_BP_FRAME, @@ -109,6 +109,13 @@ struct stream_config rkisp_bp_stream_config = { }, }; +static inline bool is_bp_stream_stopped(void __iomem *base) +{ + u32 ret = readl(base + ISP3X_MI_BP_WR_CTRL); + + return !(ret & ISP3X_BP_ENABLE); +} + static bool is_fbc_stream_stopped(void __iomem *base) { u32 ret = readl(base + ISP3X_MPFBC_CTRL); diff --git a/drivers/media/platform/rockchip/isp/capture_v32.c b/drivers/media/platform/rockchip/isp/capture_v32.c new file mode 100644 index 000000000000..bec6d6a89c50 --- /dev/null +++ b/drivers/media/platform/rockchip/isp/capture_v32.c @@ -0,0 +1,1414 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (c) 2021 Rockchip Electronics Co., Ltd. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "dev.h" +#include "regs.h" + +/* + * |--mainpath----[wrap]--------->enc(or ddr) + * | |->mainpath_4x4sampling--->ddr + *output->|->bypasspath----------------->ddr + * | |->bypasspath_4x4sampling->ddr + * |->selfpath------------------->ddr + */ + +#define CIF_ISP_REQ_BUFS_MIN 0 + +static int mi_frame_end(struct rkisp_stream *stream); + +static const struct capture_fmt bp_fmts[] = { + { + .fourcc = V4L2_PIX_FMT_UYVY, + .fmt_type = FMT_YUV, + .bpp = { 16 }, + .cplanes = 1, + .mplanes = 1, + .write_format = ISP3X_BP_FORMAT_INT, + .output_format = ISP3X_BP_OUTPUT_YUV422, + }, { + .fourcc = V4L2_PIX_FMT_NV16, + .fmt_type = FMT_YUV, + .bpp = { 8, 16 }, + .cplanes = 2, + .mplanes = 1, + .write_format = ISP3X_BP_FORMAT_SPLA, + .output_format = ISP3X_BP_OUTPUT_YUV422, + }, { + .fourcc = V4L2_PIX_FMT_NV12, + .fmt_type = FMT_YUV, + .bpp = { 8, 16 }, + .cplanes = 2, + .mplanes = 1, + .write_format = ISP3X_BP_FORMAT_SPLA, + .output_format = ISP3X_BP_OUTPUT_YUV420, + }, { + .fourcc = V4L2_PIX_FMT_NV12M, + .fmt_type = FMT_YUV, + .bpp = { 8, 16 }, + .cplanes = 2, + .mplanes = 2, + .write_format = ISP3X_BP_FORMAT_SPLA, + .output_format = ISP3X_BP_OUTPUT_YUV420, + } +}; + +static struct stream_config rkisp_bp_stream_config = { + .fmts = bp_fmts, + .fmt_size = ARRAY_SIZE(bp_fmts), + .max_rsz_width = CIF_ISP_INPUT_W_MAX_V32, + .max_rsz_height = CIF_ISP_INPUT_H_MAX_V32, + .min_rsz_width = CIF_ISP_INPUT_W_MIN, + .min_rsz_height = CIF_ISP_INPUT_H_MIN, + .frame_end_id = ISP3X_MI_BP_FRAME, + .rsz = { + .ctrl = ISP32_BP_RESIZE_CTRL, + .scale_hy = ISP32_BP_RESIZE_SCALE_HY, + .scale_hcr = ISP32_BP_RESIZE_SCALE_HCR, + .scale_hcb = ISP32_BP_RESIZE_SCALE_HCB, + .scale_vy = ISP32_BP_RESIZE_SCALE_VY, + .scale_vc = ISP32_BP_RESIZE_SCALE_VC, + .scale_lut = ISP32_BP_RESIZE_SCALE_LUT, + .scale_lut_addr = ISP32_BP_RESIZE_SCALE_LUT_ADDR, + .scale_hy_shd = ISP32_BP_RESIZE_SCALE_HY_SHD, + .scale_hcr_shd = ISP32_BP_RESIZE_SCALE_HCR_SHD, + .scale_hcb_shd = ISP32_BP_RESIZE_SCALE_HCB_SHD, + .scale_vy_shd = ISP32_BP_RESIZE_SCALE_VY_SHD, + .scale_vc_shd = ISP32_BP_RESIZE_SCALE_VC_SHD, + .phase_hy = ISP32_BP_RESIZE_PHASE_HY_SHD, + .phase_hc = ISP32_BP_RESIZE_PHASE_HC_SHD, + .phase_vy = ISP32_BP_RESIZE_PHASE_VY_SHD, + .phase_vc = ISP32_BP_RESIZE_PHASE_VC_SHD, + .ctrl_shd = ISP32_BP_RESIZE_CTRL_SHD, + .phase_hy_shd = ISP32_BP_RESIZE_PHASE_HY_SHD, + .phase_hc_shd = ISP32_BP_RESIZE_PHASE_HC_SHD, + .phase_vy_shd = ISP32_BP_RESIZE_PHASE_VY_SHD, + .phase_vc_shd = ISP32_BP_RESIZE_PHASE_VC_SHD, + }, + .dual_crop = { + .ctrl = ISP3X_DUAL_CROP_CTRL, + .yuvmode_mask = ISP3X_DUAL_CROP_FBC_MODE, + .h_offset = ISP3X_DUAL_CROP_FBC_H_OFFS, + .v_offset = ISP3X_DUAL_CROP_FBC_V_OFFS, + .h_size = ISP3X_DUAL_CROP_FBC_H_SIZE, + .v_size = ISP3X_DUAL_CROP_FBC_V_SIZE, + }, + .mi = { + .y_size_init = ISP3X_MI_BP_WR_Y_SIZE, + .cb_size_init = ISP3X_MI_BP_WR_CB_SIZE, + .y_base_ad_init = ISP3X_MI_BP_WR_Y_BASE, + .cb_base_ad_init = ISP3X_MI_BP_WR_CB_BASE, + .y_offs_cnt_init = ISP3X_MI_BP_WR_Y_OFFS_CNT, + .cb_offs_cnt_init = ISP3X_MI_BP_WR_CB_OFFS_CNT, + .y_base_ad_shd = ISP3X_MI_BP_WR_Y_BASE_SHD, + }, +}; + +static struct stream_config rkisp_bpds_stream_config = { + .fmts = bp_fmts, + .fmt_size = ARRAY_SIZE(bp_fmts), + .frame_end_id = ISP32_MI_BPDS_FRAME, + .mi = { + .ctrl = ISP32_MI_BPDS_WR_CTRL, + .length = ISP32_MI_BPDS_WR_Y_LLENGTH, + .y_size_init = ISP32_MI_BPDS_WR_Y_SIZE, + .cb_size_init = ISP32_MI_BPDS_WR_CB_SIZE, + .y_base_ad_init = ISP32_MI_BPDS_WR_Y_BASE, + .cb_base_ad_init = ISP32_MI_BPDS_WR_CB_BASE, + .y_offs_cnt_init = ISP32_MI_BPDS_WR_Y_OFFS_CNT, + .cb_offs_cnt_init = ISP32_MI_BPDS_WR_CB_OFFS_CNT, + .y_base_ad_shd = ISP32_MI_BPDS_WR_Y_BASE_SHD, + }, +}; + +static struct stream_config rkisp_mpds_stream_config = { + .fmts = bp_fmts, + .fmt_size = ARRAY_SIZE(bp_fmts), + .frame_end_id = ISP32_MI_MPDS_FRAME, + .mi = { + .ctrl = ISP32_MI_MPDS_WR_CTRL, + .length = ISP32_MI_MPDS_WR_Y_LLENGTH, + .y_size_init = ISP32_MI_MPDS_WR_Y_SIZE, + .cb_size_init = ISP32_MI_MPDS_WR_CB_SIZE, + .y_base_ad_init = ISP32_MI_MPDS_WR_Y_BASE, + .cb_base_ad_init = ISP32_MI_MPDS_WR_CB_BASE, + .y_offs_cnt_init = ISP32_MI_MPDS_WR_Y_OFFS_CNT, + .cb_offs_cnt_init = ISP32_MI_MPDS_WR_CB_OFFS_CNT, + .y_base_ad_shd = ISP32_MI_MPDS_WR_Y_BASE_SHD, + }, +}; + +static bool is_bp_stream_stopped(void __iomem *base) +{ + u32 ret = readl(base + ISP32_MI_WR_CTRL2_SHD); + + return !(ret & ISP32_BP_EN_OUT_SHD); +} + +static bool is_bpds_stream_stopped(void __iomem *base) +{ + u32 ret = readl(base + ISP32_MI_WR_CTRL2_SHD); + + return is_bp_stream_stopped(base) || !(ret & ISP32_BPDS_EN_OUT_SHD); +} + +static bool is_mpds_stream_stopped(void __iomem *base) +{ + u32 ret = readl(base + ISP32_MI_WR_CTRL2_SHD); + + return mp_is_stream_stopped(base) || !(ret & ISP32_MPDS_EN_OUT_SHD); +} + +static int get_stream_irq_mask(struct rkisp_stream *stream) +{ + int ret; + + switch (stream->id) { + case RKISP_STREAM_SP: + ret = ISP_FRAME_SP; + break; + case RKISP_STREAM_BP: + ret = ISP_FRAME_BP; + break; + case RKISP_STREAM_MP: + ret = ISP_FRAME_MP; + break; + default: + ret = 0; + } + + return ret; +} + +/* configure dual-crop unit */ +static int rkisp_stream_config_dcrop(struct rkisp_stream *stream, bool async) +{ + struct rkisp_device *dev = stream->ispdev; + struct v4l2_rect *dcrop = &stream->dcrop; + struct v4l2_rect *input_win; + + /* dual-crop unit get data from isp */ + input_win = rkisp_get_isp_sd_win(&dev->isp_sdev); + + if (dcrop->width == input_win->width && + dcrop->height == input_win->height && + dcrop->left == 0 && dcrop->top == 0) { + rkisp_disable_dcrop(stream, async); + v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev, + "stream %d crop disabled\n", stream->id); + return 0; + } + + v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev, + "stream %d crop: %dx%d -> %dx%d\n", stream->id, + input_win->width, input_win->height, + dcrop->width, dcrop->height); + + rkisp_config_dcrop(stream, dcrop, async); + + return 0; +} + +/* configure scale unit */ +static int rkisp_stream_config_rsz(struct rkisp_stream *stream, bool async) +{ + struct rkisp_device *dev = stream->ispdev; + struct v4l2_pix_format_mplane output_fmt = stream->out_fmt; + struct ispsd_out_fmt *input_isp_fmt = + rkisp_get_ispsd_out_fmt(&dev->isp_sdev); + struct v4l2_rect in_y, in_c, out_y, out_c; + + if (input_isp_fmt->fmt_type == FMT_BAYER) + goto disable; + + /* set input and output sizes for scale calculation + * input/output yuv422 + */ + in_y.width = stream->dcrop.width; + in_y.height = stream->dcrop.height; + in_c.width = in_y.width / 2; + in_c.height = in_y.height; + + out_y.width = output_fmt.width; + out_y.height = output_fmt.height; + out_c.width = out_y.width / 2; + out_c.height = out_y.height; + if (in_c.width == out_c.width && in_c.height == out_c.height) + goto disable; + + /* set RSZ input and output */ + v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev, + "stream %d rsz/scale: %dx%d -> %dx%d\n", + stream->id, stream->dcrop.width, stream->dcrop.height, + output_fmt.width, output_fmt.height); + v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev, + "chroma scaling %dx%d -> %dx%d\n", + in_c.width, in_c.height, out_c.width, out_c.height); + + /* calculate and set scale */ + rkisp_config_rsz(stream, &in_y, &in_c, &out_y, &out_c, async); + + return 0; + +disable: + rkisp_disable_rsz(stream, async); + + return 0; +} + +/***************************** stream operations*******************************/ + +/* + * memory base addresses should be with respect + * to the burst alignment restriction for AXI. + */ +static u32 calc_burst_len(struct rkisp_stream *stream) +{ + struct rkisp_device *dev = stream->ispdev; + u32 y_size = stream->out_fmt.plane_fmt[0].bytesperline * + stream->out_fmt.height; + u32 cb_size = stream->out_fmt.plane_fmt[1].sizeimage; + u32 cr_size = stream->out_fmt.plane_fmt[2].sizeimage; + u32 cb_offs, cr_offs; + u32 bus = 16, burst; + int i; + + /* y/c base addr: burstN * bus alignment */ + cb_offs = y_size; + cr_offs = cr_size ? (cb_size + cb_offs) : 0; + + if (!(cb_offs % (bus * 16)) && !(cr_offs % (bus * 16))) + burst = CIF_MI_CTRL_BURST_LEN_LUM_16 | + CIF_MI_CTRL_BURST_LEN_CHROM_16; + else if (!(cb_offs % (bus * 8)) && !(cr_offs % (bus * 8))) + burst = CIF_MI_CTRL_BURST_LEN_LUM_8 | + CIF_MI_CTRL_BURST_LEN_CHROM_8; + else + burst = CIF_MI_CTRL_BURST_LEN_LUM_4 | + CIF_MI_CTRL_BURST_LEN_CHROM_4; + + if (cb_offs % (bus * 4) || cr_offs % (bus * 4)) + v4l2_warn(&dev->v4l2_dev, + "%dx%d fmt:0x%x not support, should be %d aligned\n", + stream->out_fmt.width, + stream->out_fmt.height, + stream->out_fmt.pixelformat, + (cr_offs == 0) ? bus * 4 : bus * 16); + + stream->burst = burst; + for (i = 0; i <= RKISP_STREAM_SP; i++) + if (burst > dev->cap_dev.stream[i].burst) + burst = dev->cap_dev.stream[i].burst; + + if (stream->interlaced) { + if (!stream->out_fmt.width % (bus * 16)) + stream->burst = CIF_MI_CTRL_BURST_LEN_LUM_16 | + CIF_MI_CTRL_BURST_LEN_CHROM_16; + else if (!stream->out_fmt.width % (bus * 8)) + stream->burst = CIF_MI_CTRL_BURST_LEN_LUM_8 | + CIF_MI_CTRL_BURST_LEN_CHROM_8; + else + stream->burst = CIF_MI_CTRL_BURST_LEN_LUM_4 | + CIF_MI_CTRL_BURST_LEN_CHROM_4; + if (stream->out_fmt.width % (bus * 4)) + v4l2_warn(&dev->v4l2_dev, + "interlaced: width should be %d aligned\n", + bus * 4); + burst = min(stream->burst, burst); + stream->burst = burst; + } + + return burst; +} + +/* + * configure memory interface for mainpath + * This should only be called when stream-on + */ +static int mp_config_mi(struct rkisp_stream *stream) +{ + struct rkisp_device *dev = stream->ispdev; + struct v4l2_pix_format_mplane *out_fmt = &stream->out_fmt; + u32 val, mask, height = out_fmt->height; + + /* + * NOTE: plane_fmt[0].sizeimage is total size of all planes for single + * memory plane formats, so calculate the size explicitly. + */ + if (dev->cap_dev.wrap_line) { + height = dev->cap_dev.wrap_line; + rkisp_clear_bits(dev, 0x1814, BIT(0), false); + } + val = out_fmt->plane_fmt[0].bytesperline * height; + rkisp_write(dev, stream->config->mi.y_size_init, val, false); + + val = out_fmt->plane_fmt[1].sizeimage; + rkisp_write(dev, stream->config->mi.cb_size_init, val, false); + + val = out_fmt->plane_fmt[2].sizeimage; + rkisp_write(dev, stream->config->mi.cr_size_init, val, false); + + val = ALIGN(out_fmt->plane_fmt[0].bytesperline, 16); + rkisp_write(dev, ISP3X_MI_MP_WR_Y_LLENGTH, val, false); + + val = stream->out_isp_fmt.uv_swap ? ISP3X_MI_XTD_FORMAT_MP_UV_SWAP : 0; + mask = ISP3X_MI_XTD_FORMAT_MP_UV_SWAP; + rkisp_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false); + + mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_MP_YUV_MODE; + val = rkisp_read_reg_cache(dev, ISP3X_MPFBC_CTRL) & ~mask; + if (stream->out_fmt.pixelformat == V4L2_PIX_FMT_NV21 || + stream->out_fmt.pixelformat == V4L2_PIX_FMT_NV12 || + stream->out_fmt.pixelformat == V4L2_PIX_FMT_NV21M || + stream->out_fmt.pixelformat == V4L2_PIX_FMT_NV12M || + stream->out_fmt.pixelformat == V4L2_PIX_FMT_YUV420) + val |= ISP3X_SEPERATE_YUV_CFG; + else + val |= ISP3X_SEPERATE_YUV_CFG | ISP3X_MP_YUV_MODE; + rkisp_write(dev, ISP3X_MPFBC_CTRL, val, false); + + val = calc_burst_len(stream) | CIF_MI_CTRL_INIT_BASE_EN | + CIF_MI_CTRL_INIT_OFFSET_EN | CIF_MI_MP_AUTOUPDATE_ENABLE | + stream->out_isp_fmt.write_format; + mask = GENMASK(19, 16) | MI_CTRL_MP_FMT_MASK; + rkisp_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false); + + mi_frame_end_int_enable(stream); + /* set up first buffer */ + mi_frame_end(stream); + return 0; +} + +static int mbus_code_sp_in_fmt(u32 in_mbus_code, u32 out_fourcc, u32 *format) +{ + switch (in_mbus_code) { + case MEDIA_BUS_FMT_YUYV8_2X8: + *format = MI_CTRL_SP_INPUT_YUV422; + break; + default: + return -EINVAL; + } + + /* + * Only SP can support output format of YCbCr4:0:0, + * and the input format of SP must be YCbCr4:0:0 + * when outputting YCbCr4:0:0. + * The output format of isp is YCbCr4:2:2, + * so the CbCr data is discarded here. + */ + if (out_fourcc == V4L2_PIX_FMT_GREY) + *format = MI_CTRL_SP_INPUT_YUV400; + + return 0; +} + +/* + * configure memory interface for selfpath + * This should only be called when stream-on + */ +static int sp_config_mi(struct rkisp_stream *stream) +{ + struct rkisp_device *dev = stream->ispdev; + struct v4l2_pix_format_mplane *out_fmt = &stream->out_fmt; + struct ispsd_out_fmt *input_isp_fmt = + rkisp_get_ispsd_out_fmt(&dev->isp_sdev); + u32 sp_in_fmt, val, mask; + + if (mbus_code_sp_in_fmt(input_isp_fmt->mbus_code, + out_fmt->pixelformat, &sp_in_fmt)) { + v4l2_err(&dev->v4l2_dev, "Can't find the input format\n"); + return -EINVAL; + } + + /* + * NOTE: plane_fmt[0].sizeimage is total size of all planes for single + * memory plane formats, so calculate the size explicitly. + */ + val = out_fmt->plane_fmt[0].bytesperline * out_fmt->height; + rkisp_write(dev, stream->config->mi.y_size_init, val, false); + + val = out_fmt->plane_fmt[1].sizeimage; + rkisp_write(dev, stream->config->mi.cb_size_init, val, false); + + val = out_fmt->plane_fmt[2].sizeimage; + rkisp_write(dev, stream->config->mi.cr_size_init, val, false); + + val = ALIGN(out_fmt->plane_fmt[0].bytesperline, 16); + rkisp_write(dev, ISP3X_MI_SP_WR_Y_LLENGTH, val, false); + + val = stream->out_isp_fmt.uv_swap ? ISP3X_MI_XTD_FORMAT_SP_UV_SWAP : 0; + mask = ISP3X_MI_XTD_FORMAT_SP_UV_SWAP; + rkisp_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false); + + mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_SP_YUV_MODE; + val = rkisp_read_reg_cache(dev, ISP3X_MPFBC_CTRL) & ~mask; + if (stream->out_fmt.pixelformat == V4L2_PIX_FMT_NV21 || + stream->out_fmt.pixelformat == V4L2_PIX_FMT_NV12 || + stream->out_fmt.pixelformat == V4L2_PIX_FMT_NV21M || + stream->out_fmt.pixelformat == V4L2_PIX_FMT_NV12M || + stream->out_fmt.pixelformat == V4L2_PIX_FMT_YUV420) + val |= ISP3X_SEPERATE_YUV_CFG; + else + val |= ISP3X_SEPERATE_YUV_CFG | ISP3X_SP_YUV_MODE; + rkisp_write(dev, ISP3X_MPFBC_CTRL, val, false); + + val = calc_burst_len(stream) | CIF_MI_CTRL_INIT_BASE_EN | + CIF_MI_CTRL_INIT_OFFSET_EN | stream->out_isp_fmt.write_format | + sp_in_fmt | stream->out_isp_fmt.output_format | + CIF_MI_SP_AUTOUPDATE_ENABLE; + mask = GENMASK(19, 16) | MI_CTRL_SP_FMT_MASK; + rkisp_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false); + + mi_frame_end_int_enable(stream); + /* set up first buffer */ + mi_frame_end(stream); + return 0; +} + +static int bp_config_mi(struct rkisp_stream *stream) +{ + struct v4l2_pix_format_mplane *out_fmt = &stream->out_fmt; + struct rkisp_device *dev = stream->ispdev; + u32 val, mask; + + /* + * NOTE: plane_fmt[0].sizeimage is total size of all planes for single + * memory plane formats, so calculate the size explicitly. + */ + val = out_fmt->plane_fmt[0].bytesperline * out_fmt->height; + rkisp_write(dev, stream->config->mi.y_size_init, val, false); + + val = out_fmt->plane_fmt[1].sizeimage; + rkisp_write(dev, stream->config->mi.cb_size_init, val, false); + + val = ALIGN(out_fmt->plane_fmt[0].bytesperline, 16); + rkisp_write(dev, ISP3X_MI_BP_WR_Y_LLENGTH, val, false); + + mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_BP_YUV_MODE; + val = rkisp_read_reg_cache(dev, ISP3X_MPFBC_CTRL) & ~mask; + + if (out_fmt->pixelformat == V4L2_PIX_FMT_NV12 || + out_fmt->pixelformat == V4L2_PIX_FMT_NV12M) + val |= ISP3X_SEPERATE_YUV_CFG; + else + val |= ISP3X_SEPERATE_YUV_CFG | ISP3X_BP_YUV_MODE; + rkisp_write(dev, ISP3X_MPFBC_CTRL, val, false); + val = CIF_MI_CTRL_INIT_BASE_EN | CIF_MI_CTRL_INIT_OFFSET_EN; + rkisp_set_bits(dev, ISP3X_MI_WR_CTRL, 0, val, false); + mi_frame_end_int_enable(stream); + /* set up first buffer */ + mi_frame_end(stream); + return 0; +} + +static int ds_config_mi(struct rkisp_stream *stream) +{ + struct v4l2_pix_format_mplane *out_fmt = &stream->out_fmt; + struct rkisp_device *dev = stream->ispdev; + u32 val; + + val = out_fmt->plane_fmt[0].bytesperline * out_fmt->height; + rkisp_write(dev, stream->config->mi.y_size_init, val, false); + + val = out_fmt->plane_fmt[1].sizeimage; + rkisp_write(dev, stream->config->mi.cb_size_init, val, false); + + val = ALIGN(out_fmt->plane_fmt[0].bytesperline, 16); + rkisp_write(dev, stream->config->mi.length, val, false); + + val = CIF_MI_CTRL_INIT_BASE_EN | CIF_MI_CTRL_INIT_OFFSET_EN; + rkisp_set_bits(dev, ISP3X_MI_WR_CTRL, 0, val, false); + + mi_frame_end_int_enable(stream); + + mi_frame_end(stream); + return 0; +} + +static void mp_enable_mi(struct rkisp_stream *stream) +{ + struct rkisp_device *dev = stream->ispdev; + struct rkisp_stream *t = &dev->cap_dev.stream[stream->conn_id]; + struct capture_fmt *isp_fmt = &stream->out_isp_fmt; + u32 mask = CIF_MI_CTRL_MP_ENABLE | CIF_MI_CTRL_RAW_ENABLE; + u32 val = CIF_MI_CTRL_MP_ENABLE; + + if (isp_fmt->fmt_type == FMT_BAYER) + val = CIF_MI_CTRL_RAW_ENABLE; + rkisp_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val, false); + + /* enable bpds path output */ + if (t->streaming) + t->ops->enable_mi(t); +} + +static void sp_enable_mi(struct rkisp_stream *stream) +{ + rkisp_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, + 0, CIF_MI_CTRL_SP_ENABLE, false); +} + +static void bp_enable_mi(struct rkisp_stream *stream) +{ + struct rkisp_device *dev = stream->ispdev; + struct rkisp_stream *t = &dev->cap_dev.stream[stream->conn_id]; + + u32 val = stream->out_isp_fmt.write_format | + stream->out_isp_fmt.output_format | + ISP3X_BP_ENABLE | ISP3X_BP_AUTO_UPD; + + rkisp_write(stream->ispdev, ISP3X_MI_BP_WR_CTRL, val, false); + + /* enable bpds path output */ + if (t->streaming) + t->ops->enable_mi(t); +} + +static void ds_enable_mi(struct rkisp_stream *stream) +{ + u32 val = stream->out_isp_fmt.write_format | + stream->out_isp_fmt.output_format | + ISP32_DS_ENABLE | ISP32_DS_AUTO_UPD; + + rkisp_write(stream->ispdev, stream->config->mi.ctrl, val, false); +} + +static void mp_disable_mi(struct rkisp_stream *stream) +{ + struct rkisp_device *dev = stream->ispdev; + struct rkisp_stream *t = &dev->cap_dev.stream[stream->conn_id]; + u32 mask = CIF_MI_CTRL_MP_ENABLE | CIF_MI_CTRL_RAW_ENABLE; + + rkisp_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, false); + + /* disable mpds path output */ + if (t->streaming) + t->ops->disable_mi(t); +} + +static void sp_disable_mi(struct rkisp_stream *stream) +{ + rkisp_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, CIF_MI_CTRL_SP_ENABLE, false); +} + +static void bp_disable_mi(struct rkisp_stream *stream) +{ + struct rkisp_device *dev = stream->ispdev; + struct rkisp_stream *t = &dev->cap_dev.stream[stream->conn_id]; + + rkisp_clear_bits(stream->ispdev, ISP3X_MI_BP_WR_CTRL, ISP3X_BP_ENABLE, false); + + /* disable bpds path output */ + if (t->streaming) + t->ops->disable_mi(t); +} + +static void ds_disable_mi(struct rkisp_stream *stream) +{ + rkisp_clear_bits(stream->ispdev, stream->config->mi.ctrl, ISP32_DS_ENABLE, false); +} + +static void update_mi(struct rkisp_stream *stream) +{ + struct rkisp_device *dev = stream->ispdev; + struct rkisp_dummy_buffer *dummy_buf = &stream->dummy_buf; + u32 val, reg; + bool is_cr_cfg = false; + + if (stream->id == RKISP_STREAM_MP || stream->id == RKISP_STREAM_SP) + is_cr_cfg = true; + + if (stream->next_buf) { + reg = stream->config->mi.y_base_ad_init; + val = stream->next_buf->buff_addr[RKISP_PLANE_Y]; + rkisp_write(dev, reg, val, false); + + reg = stream->config->mi.cb_base_ad_init; + val = stream->next_buf->buff_addr[RKISP_PLANE_CB]; + rkisp_write(dev, reg, val, false); + + if (is_cr_cfg) { + reg = stream->config->mi.cr_base_ad_init; + val = stream->next_buf->buff_addr[RKISP_PLANE_CR]; + rkisp_write(dev, reg, val, false); + } + + /* single buf force updated at readback for multidevice */ + if (!dev->hw_dev->is_single) { + unsigned long lock_flags = 0; + + stream->curr_buf = stream->next_buf; + stream->next_buf = NULL; + spin_lock_irqsave(&stream->vbq_lock, lock_flags); + if (!list_empty(&stream->buf_queue)) { + stream->next_buf = list_first_entry(&stream->buf_queue, + struct rkisp_buffer, queue); + list_del(&stream->next_buf->queue); + } + spin_unlock_irqrestore(&stream->vbq_lock, lock_flags); + } + } else if (dummy_buf->mem_priv) { + val = dummy_buf->dma_addr; + reg = stream->config->mi.y_base_ad_init; + rkisp_write(dev, reg, val, false); + val += stream->out_fmt.plane_fmt[0].bytesperline * dev->cap_dev.wrap_line; + reg = stream->config->mi.cb_base_ad_init; + rkisp_write(dev, reg, val, false); + if (is_cr_cfg) { + reg = stream->config->mi.cr_base_ad_init; + rkisp_write(dev, reg, val, false); + } + } + + reg = stream->config->mi.y_offs_cnt_init; + rkisp_write(dev, reg, 0, false); + reg = stream->config->mi.cb_offs_cnt_init; + rkisp_write(dev, reg, 0, false); + if (is_cr_cfg) { + reg = stream->config->mi.cr_offs_cnt_init; + rkisp_write(dev, reg, 0, false); + } + v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev, + "%s stream:%d Y:0x%x CB:0x%x | Y_SHD:0x%x\n", + __func__, stream->id, + rkisp_read(dev, stream->config->mi.y_base_ad_init, false), + rkisp_read(dev, stream->config->mi.cb_base_ad_init, false), + rkisp_read(dev, stream->config->mi.y_base_ad_shd, true)); +} + +static struct streams_ops rkisp_mp_streams_ops = { + .config_mi = mp_config_mi, + .enable_mi = mp_enable_mi, + .disable_mi = mp_disable_mi, + .set_data_path = stream_data_path, + .is_stream_stopped = mp_is_stream_stopped, + .update_mi = update_mi, + .frame_end = mi_frame_end, +}; + +static struct streams_ops rkisp_sp_streams_ops = { + .config_mi = sp_config_mi, + .enable_mi = sp_enable_mi, + .disable_mi = sp_disable_mi, + .set_data_path = stream_data_path, + .is_stream_stopped = sp_is_stream_stopped, + .update_mi = update_mi, + .frame_end = mi_frame_end, +}; + +static struct streams_ops rkisp_bp_streams_ops = { + .config_mi = bp_config_mi, + .enable_mi = bp_enable_mi, + .disable_mi = bp_disable_mi, + .is_stream_stopped = is_bp_stream_stopped, + .update_mi = update_mi, + .frame_end = mi_frame_end, +}; + +static struct streams_ops rkisp_bpds_streams_ops = { + .config_mi = ds_config_mi, + .enable_mi = ds_enable_mi, + .disable_mi = ds_disable_mi, + .is_stream_stopped = is_bpds_stream_stopped, + .update_mi = update_mi, + .frame_end = mi_frame_end, +}; + +static struct streams_ops rkisp_mpds_streams_ops = { + .config_mi = ds_config_mi, + .enable_mi = ds_enable_mi, + .disable_mi = ds_disable_mi, + .is_stream_stopped = is_mpds_stream_stopped, + .update_mi = update_mi, + .frame_end = mi_frame_end, +}; +/* + * This function is called when a frame end come. The next frame + * is processing and we should set up buffer for next-next frame, + * otherwise it will overflow. + */ +static int mi_frame_end(struct rkisp_stream *stream) +{ + struct rkisp_device *dev = stream->ispdev; + struct capture_fmt *isp_fmt = &stream->out_isp_fmt; + unsigned long lock_flags = 0; + u64 ns = 0; + u32 i, seq; + + rkisp_dmarx_get_frame(dev, &seq, NULL, &ns, true); + + /* hold one buf for hw dma write */ + if (stream->curr_buf && stream->next_buf) { + struct vb2_buffer *vb2_buf = &stream->curr_buf->vb.vb2_buf; + + for (i = 0; i < isp_fmt->mplanes; i++) { + u32 payload_size = stream->out_fmt.plane_fmt[i].sizeimage; + + vb2_set_plane_payload(vb2_buf, i, payload_size); + } + + stream->curr_buf->vb.sequence = seq; + if (!ns) + ns = ktime_get_ns(); + vb2_buf->timestamp = ns; + + ns = ktime_get_ns(); + stream->dbg.interval = ns - stream->dbg.timestamp; + stream->dbg.timestamp = ns; + stream->dbg.id = seq; + stream->dbg.delay = ns - dev->isp_sdev.frm_timestamp; + + vb2_buffer_done(vb2_buf, VB2_BUF_STATE_DONE); + stream->curr_buf = NULL; + } else { + if (!stream->next_buf && stream->curr_buf) { + v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev, + "stream:%d can't get buf, drop %d frame\n", + stream->id, seq); + stream->dbg.frameloss++; + } + if (!dev->hw_dev->is_single) + stream->next_buf = stream->curr_buf; + } + + /* + * base/shd with same buf for multi device update after update_mi + * base/shd with dual buf for single device + */ + if (stream->next_buf && dev->hw_dev->is_single) { + stream->curr_buf = stream->next_buf; + stream->next_buf = NULL; + } + spin_lock_irqsave(&stream->vbq_lock, lock_flags); + if (!stream->next_buf && !list_empty(&stream->buf_queue)) { + stream->next_buf = list_first_entry(&stream->buf_queue, + struct rkisp_buffer, queue); + list_del(&stream->next_buf->queue); + } + spin_unlock_irqrestore(&stream->vbq_lock, lock_flags); + + stream->ops->update_mi(stream); + + return 0; +} + +/***************************** vb2 operations*******************************/ + +/* + * Set flags and wait, it should stop in interrupt. + * If it didn't, stop it by force. + */ +static void rkisp_stream_stop(struct rkisp_stream *stream) +{ + struct rkisp_device *dev = stream->ispdev; + struct v4l2_device *v4l2_dev = &dev->v4l2_dev; + int ret = 0; + + stream->stopping = true; + if (dev->hw_dev->is_single) + stream->ops->disable_mi(stream); + if (dev->isp_state & ISP_START && + !stream->ops->is_stream_stopped(dev->base_addr)) { + ret = wait_event_timeout(stream->done, + !stream->streaming, + msecs_to_jiffies(500)); + if (!ret) + v4l2_warn(v4l2_dev, "%s id:%d timeout\n", + __func__, stream->id); + } + + stream->stopping = false; + stream->streaming = false; + stream->ops->disable_mi(stream); + if (stream->id == RKISP_STREAM_MP || + stream->id == RKISP_STREAM_SP || + stream->id == RKISP_STREAM_BP) { + rkisp_disable_dcrop(stream, true); + rkisp_disable_rsz(stream, true); + } + ret = get_stream_irq_mask(stream); + dev->irq_ends_mask &= ~ret; + + stream->burst = + CIF_MI_CTRL_BURST_LEN_LUM_16 | + CIF_MI_CTRL_BURST_LEN_CHROM_16; + stream->interlaced = false; +} + +/* + * Most of registers inside rockchip isp1 have shadow register since + * they must be not changed during processing a frame. + * Usually, each sub-module updates its shadow register after + * processing the last pixel of a frame. + */ +static int rkisp_start(struct rkisp_stream *stream) +{ + struct rkisp_device *dev = stream->ispdev; + bool is_update = atomic_read(&dev->cap_dev.refcnt) > 1 ? false : true; + int ret; + + if (stream->ops->set_data_path) + stream->ops->set_data_path(stream); + ret = stream->ops->config_mi(stream); + if (ret) + return ret; + + stream->ops->enable_mi(stream); + if (is_update) + dev->irq_ends_mask |= get_stream_irq_mask(stream); + stream->streaming = true; + + return 0; +} + +static int rkisp_queue_setup(struct vb2_queue *queue, + unsigned int *num_buffers, + unsigned int *num_planes, + unsigned int sizes[], + struct device *alloc_ctxs[]) +{ + struct rkisp_stream *stream = queue->drv_priv; + struct rkisp_device *dev = stream->ispdev; + const struct v4l2_pix_format_mplane *pixm = NULL; + const struct capture_fmt *isp_fmt = NULL; + u32 i; + + pixm = &stream->out_fmt; + isp_fmt = &stream->out_isp_fmt; + *num_planes = isp_fmt->mplanes; + + for (i = 0; i < isp_fmt->mplanes; i++) { + const struct v4l2_plane_pix_format *plane_fmt; + u32 height = pixm->height; + + if (dev->cap_dev.wrap_line && stream->id == RKISP_STREAM_MP) + height = dev->cap_dev.wrap_line; + plane_fmt = &pixm->plane_fmt[i]; + /* height to align with 16 when allocating memory + * so that Rockchip encoder can use DMA buffer directly + */ + sizes[i] = (isp_fmt->fmt_type == FMT_YUV) ? + plane_fmt->sizeimage / height * + ALIGN(height, 16) : + plane_fmt->sizeimage; + } + + rkisp_chk_tb_over(dev); + v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev, "%s %s count %d, size %d\n", + stream->vnode.vdev.name, v4l2_type_names[queue->type], *num_buffers, sizes[0]); + + return 0; +} + +/* + * The vb2_buffer are stored in rkisp_buffer, in order to unify + * mplane buffer and none-mplane buffer. + */ +static void rkisp_buf_queue(struct vb2_buffer *vb) +{ + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct rkisp_buffer *ispbuf = to_rkisp_buffer(vbuf); + struct vb2_queue *queue = vb->vb2_queue; + struct rkisp_stream *stream = queue->drv_priv; + struct rkisp_device *dev = stream->ispdev; + struct v4l2_pix_format_mplane *pixm = &stream->out_fmt; + struct capture_fmt *isp_fmt = &stream->out_isp_fmt; + unsigned long lock_flags = 0; + struct sg_table *sgt; + u32 height, offset; + int i; + + memset(ispbuf->buff_addr, 0, sizeof(ispbuf->buff_addr)); + for (i = 0; i < isp_fmt->mplanes; i++) { + vb2_plane_vaddr(vb, i); + + if (stream->ispdev->hw_dev->is_dma_sg_ops) { + sgt = vb2_dma_sg_plane_desc(vb, i); + ispbuf->buff_addr[i] = sg_dma_address(sgt->sgl); + } else { + ispbuf->buff_addr[i] = vb2_dma_contig_plane_dma_addr(vb, i); + } + } + /* + * NOTE: plane_fmt[0].sizeimage is total size of all planes for single + * memory plane formats, so calculate the size explicitly. + */ + if (isp_fmt->mplanes == 1) { + for (i = 0; i < isp_fmt->cplanes - 1; i++) { + height = pixm->height; + if (dev->cap_dev.wrap_line && stream->id == RKISP_STREAM_MP) + height = dev->cap_dev.wrap_line; + offset = (i == 0) ? + pixm->plane_fmt[i].bytesperline * height : + pixm->plane_fmt[i].sizeimage; + ispbuf->buff_addr[i + 1] = + ispbuf->buff_addr[i] + offset; + } + } + + v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev, + "stream:%d queue buf:0x%x\n", + stream->id, ispbuf->buff_addr[0]); + + spin_lock_irqsave(&stream->vbq_lock, lock_flags); + list_add_tail(&ispbuf->queue, &stream->buf_queue); + spin_unlock_irqrestore(&stream->vbq_lock, lock_flags); +} + +static int rkisp_create_dummy_buf(struct rkisp_stream *stream) +{ + struct rkisp_device *dev = stream->ispdev; + struct rkisp_dummy_buffer *buf = &stream->dummy_buf; + + /* mainpath for warp default */ + if (!dev->cap_dev.wrap_line || stream->id != RKISP_STREAM_MP) + return 0; + + buf->size = stream->out_fmt.plane_fmt[0].sizeimage; + buf->is_need_dbuf = true; + return rkisp_alloc_buffer(stream->ispdev, buf); +} + +static void rkisp_destroy_dummy_buf(struct rkisp_stream *stream) +{ + struct rkisp_device *dev = stream->ispdev; + + if (!dev->cap_dev.wrap_line || stream->id != RKISP_STREAM_MP) + return; + rkisp_free_buffer(stream->ispdev, &stream->dummy_buf); +} + +static void destroy_buf_queue(struct rkisp_stream *stream, + enum vb2_buffer_state state) +{ + unsigned long lock_flags = 0; + struct rkisp_buffer *buf; + + spin_lock_irqsave(&stream->vbq_lock, lock_flags); + if (stream->curr_buf) { + list_add_tail(&stream->curr_buf->queue, &stream->buf_queue); + if (stream->curr_buf == stream->next_buf) + stream->next_buf = NULL; + stream->curr_buf = NULL; + } + if (stream->next_buf) { + list_add_tail(&stream->next_buf->queue, &stream->buf_queue); + stream->next_buf = NULL; + } + while (!list_empty(&stream->buf_queue)) { + buf = list_first_entry(&stream->buf_queue, + struct rkisp_buffer, queue); + list_del(&buf->queue); + vb2_buffer_done(&buf->vb.vb2_buf, state); + } + spin_unlock_irqrestore(&stream->vbq_lock, lock_flags); +} + +static void rkisp_stop_streaming(struct vb2_queue *queue) +{ + struct rkisp_stream *stream = queue->drv_priv; + struct rkisp_vdev_node *node = &stream->vnode; + struct rkisp_device *dev = stream->ispdev; + struct v4l2_device *v4l2_dev = &dev->v4l2_dev; + int ret; + + mutex_lock(&dev->hw_dev->dev_lock); + + v4l2_dbg(1, rkisp_debug, v4l2_dev, "%s %s %d\n", + __func__, node->vdev.name, stream->id); + + if (!stream->streaming) + goto end; + + rkisp_stream_stop(stream); + if (!dev->cap_dev.wrap_line || atomic_read(&dev->cap_dev.refcnt) == 1) { + /* call to the other devices */ + media_pipeline_stop(&node->vdev.entity); + ret = dev->pipe.set_stream(&dev->pipe, false); + if (ret < 0) + v4l2_err(v4l2_dev, "pipeline stream-off failed:%d\n", ret); + } + + /* release buffers */ + destroy_buf_queue(stream, VB2_BUF_STATE_ERROR); + + ret = dev->pipe.close(&dev->pipe); + if (ret < 0) + v4l2_err(v4l2_dev, "pipeline close failed error:%d\n", ret); + rkisp_destroy_dummy_buf(stream); + atomic_dec(&dev->cap_dev.refcnt); + +end: + mutex_unlock(&dev->hw_dev->dev_lock); +} + +static int rkisp_stream_start(struct rkisp_stream *stream) +{ + struct rkisp_device *dev = stream->ispdev; + struct v4l2_device *v4l2_dev = &dev->v4l2_dev; + bool async = false; + int ret; + + if (stream->id == RKISP_STREAM_MPDS || stream->id == RKISP_STREAM_BPDS) + goto end; + + async = (stream->id == RKISP_STREAM_MP) ? + dev->cap_dev.stream[RKISP_STREAM_SP].streaming : + dev->cap_dev.stream[RKISP_STREAM_MP].streaming; + + /* + * can't be async now, otherwise the latter started stream fails to + * produce mi interrupt. + */ + ret = rkisp_stream_config_dcrop(stream, false); + if (ret < 0) { + v4l2_err(v4l2_dev, "config dcrop failed with error %d\n", ret); + return ret; + } + + ret = rkisp_stream_config_rsz(stream, async); + if (ret < 0) { + v4l2_err(v4l2_dev, "config rsz failed with error %d\n", ret); + return ret; + } + +end: + return rkisp_start(stream); +} + +static int +rkisp_start_streaming(struct vb2_queue *queue, unsigned int count) +{ + struct rkisp_stream *stream = queue->drv_priv; + struct rkisp_vdev_node *node = &stream->vnode; + struct rkisp_device *dev = stream->ispdev; + struct v4l2_device *v4l2_dev = &dev->v4l2_dev; + int ret = -EINVAL; + bool is_pipe = true; + + if (dev->cap_dev.wrap_line && stream->id != RKISP_STREAM_MP) + is_pipe = false; + + mutex_lock(&dev->hw_dev->dev_lock); + + v4l2_dbg(1, rkisp_debug, v4l2_dev, "%s %s id:%d\n", + __func__, node->vdev.name, stream->id); + + if (WARN_ON(stream->streaming)) { + mutex_unlock(&dev->hw_dev->dev_lock); + return -EBUSY; + } + + memset(&stream->dbg, 0, sizeof(stream->dbg)); + atomic_inc(&dev->cap_dev.refcnt); + if (!dev->isp_inp || !stream->linked) { + v4l2_err(v4l2_dev, "check %s link or isp input\n", node->vdev.name); + goto buffer_done; + } + + if (stream->id == RKISP_STREAM_MPDS || stream->id == RKISP_STREAM_BPDS) { + struct rkisp_stream *t = &dev->cap_dev.stream[stream->conn_id]; + + if (!t->streaming) { + v4l2_err(v4l2_dev, "%s from %s no start\n", + node->vdev.name, t->vnode.vdev.name); + goto buffer_done; + } + } + + if (atomic_read(&dev->cap_dev.refcnt) == 1 && + (dev->isp_inp & INP_CIF)) { + /* update sensor info when first streaming */ + ret = rkisp_update_sensor_info(dev); + if (ret < 0) { + v4l2_err(v4l2_dev, "update sensor info failed %d\n", ret); + goto buffer_done; + } + } + + ret = rkisp_create_dummy_buf(stream); + if (ret < 0) + goto buffer_done; + + if (count == 0 && !stream->dummy_buf.mem_priv) { + v4l2_err(v4l2_dev, "no buf for %s\n", node->vdev.name); + ret = -EINVAL; + goto buffer_done; + } + + /* enable clocks/power-domains */ + ret = dev->pipe.open(&dev->pipe, &node->vdev.entity, true); + if (ret < 0) { + v4l2_err(v4l2_dev, "open isp pipeline failed %d\n", ret); + goto destroy_dummy_buf; + } + + /* configure stream hardware to start */ + ret = rkisp_stream_start(stream); + if (ret < 0) { + v4l2_err(v4l2_dev, "start %s failed\n", node->vdev.name); + goto close_pipe; + } + + if (is_pipe) { + /* start sub-devices */ + ret = dev->pipe.set_stream(&dev->pipe, true); + if (ret < 0) + goto stop_stream; + + ret = media_pipeline_start(&node->vdev.entity, &dev->pipe.pipe); + if (ret < 0) { + v4l2_err(v4l2_dev, "start pipeline failed %d\n", ret); + goto pipe_stream_off; + } + } + + mutex_unlock(&dev->hw_dev->dev_lock); + return 0; + +pipe_stream_off: + dev->pipe.set_stream(&dev->pipe, false); +stop_stream: + rkisp_stream_stop(stream); +close_pipe: + dev->pipe.close(&dev->pipe); +destroy_dummy_buf: + rkisp_destroy_dummy_buf(stream); +buffer_done: + destroy_buf_queue(stream, VB2_BUF_STATE_QUEUED); + atomic_dec(&dev->cap_dev.refcnt); + stream->streaming = false; + mutex_unlock(&dev->hw_dev->dev_lock); + return ret; +} + +static const struct vb2_ops rkisp_vb2_ops = { + .queue_setup = rkisp_queue_setup, + .buf_queue = rkisp_buf_queue, + .wait_prepare = vb2_ops_wait_prepare, + .wait_finish = vb2_ops_wait_finish, + .stop_streaming = rkisp_stop_streaming, + .start_streaming = rkisp_start_streaming, +}; + +static int rkisp_init_vb2_queue(struct vb2_queue *q, + struct rkisp_stream *stream, + enum v4l2_buf_type buf_type) +{ + q->type = buf_type; + q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; + q->drv_priv = stream; + q->ops = &rkisp_vb2_ops; + q->mem_ops = stream->ispdev->hw_dev->mem_ops; + q->buf_struct_size = sizeof(struct rkisp_buffer); + q->min_buffers_needed = CIF_ISP_REQ_BUFS_MIN; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->lock = &stream->apilock; + q->dev = stream->ispdev->hw_dev->dev; + q->allow_cache_hints = 1; + q->bidirectional = 1; + if (stream->ispdev->hw_dev->is_dma_contig) + q->dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS; + q->gfp_flags = GFP_DMA32; + return vb2_queue_init(q); +} + +static int rkisp_stream_init(struct rkisp_device *dev, u32 id) +{ + struct rkisp_capture_device *cap_dev = &dev->cap_dev; + struct rkisp_stream *stream; + struct video_device *vdev; + struct rkisp_vdev_node *node; + int ret = 0; + + stream = &cap_dev->stream[id]; + stream->id = id; + stream->ispdev = dev; + vdev = &stream->vnode.vdev; + + INIT_LIST_HEAD(&stream->buf_queue); + init_waitqueue_head(&stream->done); + spin_lock_init(&stream->vbq_lock); + stream->linked = true; + + switch (id) { + case RKISP_STREAM_SP: + strscpy(vdev->name, SP_VDEV_NAME, sizeof(vdev->name)); + stream->ops = &rkisp_sp_streams_ops; + stream->config = &rkisp_sp_stream_config; + break; + case RKISP_STREAM_BP: + strscpy(vdev->name, BP_VDEV_NAME, sizeof(vdev->name)); + stream->ops = &rkisp_bp_streams_ops; + stream->config = &rkisp_bp_stream_config; + stream->conn_id = RKISP_STREAM_BPDS; + break; + case RKISP_STREAM_BPDS: + strscpy(vdev->name, BPDS_VDEV_NAME, sizeof(vdev->name)); + stream->ops = &rkisp_bpds_streams_ops; + stream->config = &rkisp_bpds_stream_config; + stream->conn_id = RKISP_STREAM_BP; + break; + case RKISP_STREAM_MPDS: + strscpy(vdev->name, MPDS_VDEV_NAME, sizeof(vdev->name)); + stream->ops = &rkisp_mpds_streams_ops; + stream->config = &rkisp_mpds_stream_config; + stream->conn_id = RKISP_STREAM_MP; + break; + default: + strscpy(vdev->name, MP_VDEV_NAME, sizeof(vdev->name)); + stream->ops = &rkisp_mp_streams_ops; + stream->config = &rkisp_mp_stream_config; + stream->conn_id = RKISP_STREAM_MPDS; + } + + node = vdev_to_node(vdev); + rkisp_init_vb2_queue(&node->buf_queue, stream, + V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); + ret = rkisp_register_stream_vdev(stream); + if (ret < 0) + return ret; + + stream->streaming = false; + stream->interlaced = false; + stream->burst = + CIF_MI_CTRL_BURST_LEN_LUM_16 | + CIF_MI_CTRL_BURST_LEN_CHROM_16; + atomic_set(&stream->sequence, 0); + return 0; +} + +int rkisp_register_stream_v32(struct rkisp_device *dev) +{ + struct rkisp_capture_device *cap_dev = &dev->cap_dev; + int ret; + + ret = rkisp_stream_init(dev, RKISP_STREAM_MP); + if (ret < 0) + goto err; + ret = rkisp_stream_init(dev, RKISP_STREAM_SP); + if (ret < 0) + goto err_free_mp; + ret = rkisp_stream_init(dev, RKISP_STREAM_BP); + if (ret < 0) + goto err_free_sp; + ret = rkisp_stream_init(dev, RKISP_STREAM_MPDS); + if (ret < 0) + goto err_free_bp; + ret = rkisp_stream_init(dev, RKISP_STREAM_BPDS); + if (ret < 0) + goto err_free_mpds; + return 0; +err_free_mpds: + rkisp_unregister_stream_vdev(&cap_dev->stream[RKISP_STREAM_MPDS]); +err_free_bp: + rkisp_unregister_stream_vdev(&cap_dev->stream[RKISP_STREAM_BP]); +err_free_sp: + rkisp_unregister_stream_vdev(&cap_dev->stream[RKISP_STREAM_SP]); +err_free_mp: + rkisp_unregister_stream_vdev(&cap_dev->stream[RKISP_STREAM_MP]); +err: + return ret; +} + +void rkisp_unregister_stream_v32(struct rkisp_device *dev) +{ + struct rkisp_capture_device *cap_dev = &dev->cap_dev; + struct rkisp_stream *stream; + + stream = &cap_dev->stream[RKISP_STREAM_MP]; + rkisp_unregister_stream_vdev(stream); + stream = &cap_dev->stream[RKISP_STREAM_SP]; + rkisp_unregister_stream_vdev(stream); + stream = &cap_dev->stream[RKISP_STREAM_BP]; + rkisp_unregister_stream_vdev(stream); + stream = &cap_dev->stream[RKISP_STREAM_MPDS]; + rkisp_unregister_stream_vdev(stream); + stream = &cap_dev->stream[RKISP_STREAM_BPDS]; + rkisp_unregister_stream_vdev(stream); +} + +/**************** Interrupter Handler ****************/ + +void rkisp_mi_v32_isr(u32 mis_val, struct rkisp_device *dev) +{ + struct rkisp_stream *stream; + unsigned int i; + + v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev, + "mi isr:0x%x\n", mis_val); + + for (i = 0; i < RKISP_MAX_STREAM; ++i) { + stream = &dev->cap_dev.stream[i]; + + if (!(mis_val & CIF_MI_FRAME(stream))) + continue; + + mi_frame_end_int_clear(stream); + + if (stream->stopping) { + /* + * Make sure stream is actually stopped, whose state + * can be read from the shadow register, before + * wake_up() thread which would immediately free all + * frame buffers. disable_mi() takes effect at the next + * frame end that sync the configurations to shadow + * regs. + */ + if (!dev->hw_dev->is_single) { + stream->stopping = false; + stream->streaming = false; + stream->ops->disable_mi(stream); + wake_up(&stream->done); + } else if (stream->ops->is_stream_stopped(dev->base_addr)) { + stream->stopping = false; + stream->streaming = false; + wake_up(&stream->done); + } + } else { + /* TODO frame end event to mpp */ + mi_frame_end(stream); + } + } + + if (mis_val & ISP3X_MI_MP_FRAME) { + stream = &dev->cap_dev.stream[RKISP_STREAM_MP]; + if (!stream->streaming) + dev->irq_ends_mask &= ~ISP_FRAME_MP; + else + dev->irq_ends_mask |= ISP_FRAME_MP; + rkisp_check_idle(dev, ISP_FRAME_MP); + } + if (mis_val & ISP3X_MI_SP_FRAME) { + stream = &dev->cap_dev.stream[RKISP_STREAM_SP]; + if (!stream->streaming) + dev->irq_ends_mask &= ~ISP_FRAME_SP; + else + dev->irq_ends_mask |= ISP_FRAME_SP; + rkisp_check_idle(dev, ISP_FRAME_SP); + } + if (mis_val & ISP3X_MI_BP_FRAME) { + stream = &dev->cap_dev.stream[RKISP_STREAM_BP]; + if (!stream->streaming) + dev->irq_ends_mask &= ~ISP_FRAME_BP; + else + dev->irq_ends_mask |= ISP_FRAME_BP; + rkisp_check_idle(dev, ISP_FRAME_BP); + } +} + +void rkisp_mipi_v32_isr(unsigned int phy, unsigned int packet, + unsigned int overflow, unsigned int state, + struct rkisp_device *dev) +{ + if (state & GENMASK(19, 17)) + v4l2_warn(&dev->v4l2_dev, "RD_SIZE_ERR:0x%08x\n", state); +} diff --git a/drivers/media/platform/rockchip/isp/capture_v3x.h b/drivers/media/platform/rockchip/isp/capture_v3x.h index cb3d59391e87..62e15905a664 100644 --- a/drivers/media/platform/rockchip/isp/capture_v3x.h +++ b/drivers/media/platform/rockchip/isp/capture_v3x.h @@ -20,4 +20,16 @@ static inline void rkisp_mi_v30_isr(u32 mis_val, struct rkisp_device *dev) {} static inline void rkisp_mipi_v30_isr(u32 phy, u32 packet, u32 overflow, u32 state, struct rkisp_device *dev) {} #endif +#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V32) +int rkisp_register_stream_v32(struct rkisp_device *dev); +void rkisp_unregister_stream_v32(struct rkisp_device *dev); +void rkisp_mi_v32_isr(u32 mis_val, struct rkisp_device *dev); +void rkisp_mipi_v32_isr(u32 phy, u32 packet, u32 overflow, u32 state, struct rkisp_device *dev); +#else +static inline int rkisp_register_stream_v32(struct rkisp_device *dev) { return -EINVAL; } +static inline void rkisp_unregister_stream_v32(struct rkisp_device *dev) {} +static inline void rkisp_mi_v32_isr(u32 mis_val, struct rkisp_device *dev) {} +static inline void rkisp_mipi_v32_isr(u32 phy, u32 packet, u32 overflow, u32 state, struct rkisp_device *dev) {} +#endif + #endif diff --git a/drivers/media/platform/rockchip/isp/common.h b/drivers/media/platform/rockchip/isp/common.h index 6ff84a21b216..37285089f464 100644 --- a/drivers/media/platform/rockchip/isp/common.h +++ b/drivers/media/platform/rockchip/isp/common.h @@ -71,6 +71,7 @@ enum rkisp_isp_ver { ISP_V20 = 0x40, ISP_V21 = 0x50, ISP_V30 = 0x60, + ISP_V32 = 0x70, }; enum rkisp_sd_type { @@ -110,11 +111,9 @@ enum rkisp_fmt_raw_pat_type { struct rkisp_buffer { struct vb2_v4l2_buffer vb; struct list_head queue; + void *vaddr[VIDEO_MAX_PLANES]; + u32 buff_addr[VIDEO_MAX_PLANES]; int dev_id; - union { - u32 buff_addr[VIDEO_MAX_PLANES]; - void *vaddr[VIDEO_MAX_PLANES]; - }; }; struct rkisp_dummy_buffer { diff --git a/drivers/media/platform/rockchip/isp/csi.c b/drivers/media/platform/rockchip/isp/csi.c index e6cf292b8350..3b55fcfc3272 100644 --- a/drivers/media/platform/rockchip/isp/csi.c +++ b/drivers/media/platform/rockchip/isp/csi.c @@ -470,7 +470,8 @@ int rkisp_csi_config_patch(struct rkisp_device *dev) v4l2_subdev_call(mipi_sensor, core, ioctl, RKISP_VICAP_CMD_MODE, &mode); /* vicap direct to isp */ - if (dev->isp_ver == ISP_V30 && !mode.is_rdbk) { + if ((dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) && + !mode.is_rdbk) { switch (dev->hdr.op_mode) { case HDR_RDBK_FRAME3: dev->hdr.op_mode = HDR_LINEX3_DDR; @@ -538,7 +539,7 @@ int rkisp_csi_config_patch(struct rkisp_device *dev) rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, SW_MPIP_DROP_FRM_DIS, true, dev->hw_dev->is_unite); - if (dev->isp_ver == ISP_V30) + if (dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, ISP3X_SW_ACK_FRM_PRO_DIS, true, dev->hw_dev->is_unite); @@ -608,7 +609,7 @@ int rkisp_register_csi_subdev(struct rkisp_device *dev, csi_dev->pads[CSI_SRC_CH2].flags = MEDIA_PAD_FL_SOURCE; csi_dev->pads[CSI_SRC_CH3].flags = MEDIA_PAD_FL_SOURCE; csi_dev->pads[CSI_SRC_CH4].flags = MEDIA_PAD_FL_SOURCE; - } else if (dev->isp_ver == ISP_V30) { + } else if (dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) { return 0; } diff --git a/drivers/media/platform/rockchip/isp/dev.c b/drivers/media/platform/rockchip/isp/dev.c index ff8a15cd479c..631e08e94451 100644 --- a/drivers/media/platform/rockchip/isp/dev.c +++ b/drivers/media/platform/rockchip/isp/dev.c @@ -265,7 +265,8 @@ static int rkisp_pipeline_close(struct rkisp_pipeline *p) atomic_dec(&p->power_cnt); - if (dev->isp_ver == ISP_V30 && !atomic_read(&p->power_cnt)) + if (!atomic_read(&p->power_cnt) && + (dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32)) rkisp_rx_buf_pool_free(dev); return 0; @@ -470,6 +471,23 @@ static int _set_pipeline_default_fmt(struct rkisp_device *dev) width, height, V4L2_PIX_FMT_NV12); #endif } + + if (dev->isp_ver == ISP_V32) { + struct v4l2_pix_format_mplane pixm = { + .width = width, + .height = height, + .pixelformat = rkisp_mbus_pixelcode_to_v4l2(code), + }; + + rkisp_dmarx_set_fmt(&dev->dmarx_dev.stream[RKISP_STREAM_RAWRD0], pixm); + rkisp_dmarx_set_fmt(&dev->dmarx_dev.stream[RKISP_STREAM_RAWRD2], pixm); + rkisp_set_stream_def_fmt(dev, RKISP_STREAM_BP, + width, height, V4L2_PIX_FMT_NV12); + rkisp_set_stream_def_fmt(dev, RKISP_STREAM_MPDS, + width / 4, height / 4, V4L2_PIX_FMT_NV12); + rkisp_set_stream_def_fmt(dev, RKISP_STREAM_BPDS, + width / 4, height / 4, V4L2_PIX_FMT_NV12); + } return 0; } diff --git a/drivers/media/platform/rockchip/isp/dev.h b/drivers/media/platform/rockchip/isp/dev.h index bb93dbed7314..6763ab4a70d6 100644 --- a/drivers/media/platform/rockchip/isp/dev.h +++ b/drivers/media/platform/rockchip/isp/dev.h @@ -60,8 +60,8 @@ #define GRP_ID_ISP_BRIDGE BIT(6) #define GRP_ID_CSI BIT(7) -#define RKISP_MAX_SENSOR 2 -#define RKISP_MAX_PIPELINE 4 +#define RKISP_MAX_SENSOR 4 +#define RKISP_MAX_PIPELINE 8 #define RKISP_MEDIA_BUS_FMT_MASK 0xF000 #define RKISP_MEDIA_BUS_FMT_BAYER 0x3000 @@ -181,7 +181,6 @@ struct rkisp_device { struct v4l2_ctrl_handler ctrl_handler; struct media_device media_dev; struct v4l2_async_notifier notifier; - struct v4l2_subdev *subdevs[RKISP_SD_MAX]; struct rkisp_sensor_info *active_sensor; struct rkisp_sensor_info sensors[RKISP_MAX_SENSOR]; int num_sensors; diff --git a/drivers/media/platform/rockchip/isp/dmarx.c b/drivers/media/platform/rockchip/isp/dmarx.c index b50d2adbd36f..f1747a9b17c3 100644 --- a/drivers/media/platform/rockchip/isp/dmarx.c +++ b/drivers/media/platform/rockchip/isp/dmarx.c @@ -619,7 +619,8 @@ static void dmarx_stop_streaming(struct vb2_queue *queue) if (stream->id == RKISP_STREAM_RAWRD2 && (stream->ispdev->isp_ver == ISP_V20 || stream->ispdev->isp_ver == ISP_V21 || - stream->ispdev->isp_ver == ISP_V30)) + stream->ispdev->isp_ver == ISP_V30 || + stream->ispdev->isp_ver == ISP_V32)) kfifo_reset(&stream->ispdev->rdbk_kfifo); } @@ -732,7 +733,8 @@ static int rkisp_set_fmt(struct rkisp_stream *stream, if ((stream->ispdev->isp_ver == ISP_V20 || stream->ispdev->isp_ver == ISP_V21 || - stream->ispdev->isp_ver == ISP_V30) && + stream->ispdev->isp_ver == ISP_V30 || + stream->ispdev->isp_ver == ISP_V32) && fmt->fmt_type == FMT_BAYER && !stream->memory && stream->id != RKISP_STREAM_DMARX) @@ -1132,7 +1134,8 @@ int rkisp_register_dmarx_vdev(struct rkisp_device *dev) #endif if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 || - dev->isp_ver == ISP_V30) { + dev->isp_ver == ISP_V30 || + dev->isp_ver == ISP_V32) { ret = dmarx_init(dev, RKISP_STREAM_RAWRD0); if (ret < 0) goto err_free_dmarx; @@ -1171,7 +1174,8 @@ void rkisp_unregister_dmarx_vdev(struct rkisp_device *dev) if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 || - dev->isp_ver == ISP_V30) { + dev->isp_ver == ISP_V30 || + dev->isp_ver == ISP_V32) { stream = &dmarx_dev->stream[RKISP_STREAM_RAWRD0]; rkisp_unregister_dmarx_video(stream); diff --git a/drivers/media/platform/rockchip/isp/hw.c b/drivers/media/platform/rockchip/isp/hw.c index 6f507142e866..fe38492ea222 100644 --- a/drivers/media/platform/rockchip/isp/hw.c +++ b/drivers/media/platform/rockchip/isp/hw.c @@ -87,6 +87,23 @@ static void default_sw_reg_flag(struct rkisp_device *dev) ISP3X_RAWHIST_BIG1_BASE, ISP3X_RAWHIST_BIG2_BASE, ISP3X_RAWHIST_BIG3_BASE, ISP3X_RAWAF_CTRL, ISP3X_RAWAWB_CTRL, }; + u32 v32_reg[] = { + ISP3X_VI_ISP_PATH, ISP3X_IMG_EFF_CTRL, ISP3X_CMSK_CTRL0, + ISP3X_CCM_CTRL, ISP3X_CPROC_CTRL, ISP3X_DUAL_CROP_CTRL, + ISP3X_GAMMA_OUT_CTRL, ISP3X_SELF_RESIZE_CTRL, ISP3X_MAIN_RESIZE_CTRL, + ISP32_BP_RESIZE_BASE, ISP3X_MI_BP_WR_CTRL, ISP32_MI_MPDS_WR_CTRL, + ISP32_MI_BPDS_WR_CTRL, ISP32_MI_WR_WRAP_CTRL, + ISP3X_LSC_CTRL, ISP3X_DEBAYER_CONTROL, ISP3X_CAC_CTRL, + ISP3X_YNR_GLOBAL_CTRL, ISP3X_CNR_CTRL, ISP3X_SHARP_EN, + ISP3X_BAY3D_CTRL, ISP3X_GIC_CONTROL, ISP3X_BLS_CTRL, + ISP3X_DPCC0_MODE, ISP3X_DPCC1_MODE, ISP3X_DPCC2_MODE, + ISP3X_HDRMGE_CTRL, ISP3X_DRC_CTRL0, ISP3X_BAYNR_CTRL, + ISP3X_LDCH_STS, ISP3X_DHAZ_CTRL, ISP3X_3DLUT_CTRL, + ISP3X_GAIN_CTRL, ISP3X_RAWAE_LITE_CTRL, ISP3X_RAWAE_BIG1_BASE, + ISP3X_RAWAE_BIG2_BASE, ISP3X_RAWAE_BIG3_BASE, ISP3X_RAWHIST_LITE_CTRL, + ISP3X_RAWHIST_BIG1_BASE, ISP3X_RAWHIST_BIG2_BASE, ISP3X_RAWHIST_BIG3_BASE, + ISP3X_RAWAF_CTRL, ISP3X_RAWAWB_CTRL, + }; u32 i, *flag, *reg, size; switch (dev->isp_ver) { @@ -102,6 +119,10 @@ static void default_sw_reg_flag(struct rkisp_device *dev) reg = v30_reg; size = ARRAY_SIZE(v30_reg); break; + case ISP_V32: + reg = v32_reg; + size = ARRAY_SIZE(v32_reg); + break; default: return; } @@ -138,7 +159,8 @@ static irqreturn_t mipi_irq_hdl(int irq, void *ctx) rkisp_mipi_v13_isr(err1, err2, err3, isp); } else if (hw_dev->isp_ver == ISP_V20 || hw_dev->isp_ver == ISP_V21 || - hw_dev->isp_ver == ISP_V30) { + hw_dev->isp_ver == ISP_V30 || + hw_dev->isp_ver == ISP_V32) { u32 phy, packet, overflow, state; state = readl(base + CSI2RX_ERR_STAT); @@ -150,8 +172,10 @@ static irqreturn_t mipi_irq_hdl(int irq, void *ctx) rkisp_mipi_v20_isr(phy, packet, overflow, state, isp); else if (hw_dev->isp_ver == ISP_V21) rkisp_mipi_v21_isr(phy, packet, overflow, state, isp); - else + else if (hw_dev->isp_ver == ISP_V30) rkisp_mipi_v30_isr(phy, packet, overflow, state, isp); + else + rkisp_mipi_v32_isr(phy, packet, overflow, state, isp); } } else { u32 mis_val = readl(base + CIF_MIPI_MIS); @@ -203,7 +227,8 @@ static irqreturn_t isp_irq_hdl(int irq, void *ctx) mis_val = readl(base + CIF_ISP_MIS); if (hw_dev->isp_ver == ISP_V20 || hw_dev->isp_ver == ISP_V21 || - hw_dev->isp_ver == ISP_V30) + hw_dev->isp_ver == ISP_V30 || + hw_dev->isp_ver == ISP_V32) mis_3a = readl(base + ISP_ISP3A_MIS); if (mis_val || mis_3a) rkisp_isp_isr(mis_val, mis_3a, isp); @@ -221,7 +246,8 @@ static irqreturn_t irq_handler(int irq, void *ctx) mis_val = readl(hw_dev->base_addr + CIF_ISP_MIS); if (hw_dev->isp_ver == ISP_V20 || hw_dev->isp_ver == ISP_V21 || - hw_dev->isp_ver == ISP_V30) + hw_dev->isp_ver == ISP_V30 || + hw_dev->isp_ver == ISP_V32) mis_3a = readl(hw_dev->base_addr + ISP_ISP3A_MIS); if (mis_val || mis_3a) rkisp_isp_isr(mis_val, mis_3a, isp); @@ -363,6 +389,13 @@ static const char * const rk3588_isp_unite_clks[] = { "clk_isp_core_vicap1", }; +static const char * const rv1106_isp_clks[] = { + "clk_isp_core", + "aclk_isp", + "hclk_isp", + "clk_isp_core_vicap", +}; + static const char * const rv1126_isp_clks[] = { "clk_isp", "aclk_isp", @@ -429,6 +462,19 @@ static const struct isp_clk_info rk3588_isp_clk_rate[] = { } }; +static const struct isp_clk_info rv1106_isp_clk_rate[] = { + { + .clk_rate = 200, + .refer_data = 1920, //width + }, { + .clk_rate = 300, + .refer_data = 2688, + }, { + .clk_rate = 400, + .refer_data = 3072, + } +}; + static const struct isp_clk_info rv1126_isp_clk_rate[] = { { .clk_rate = 20, @@ -484,12 +530,29 @@ static struct isp_irqs_data rk3588_isp_irqs[] = { {"mipi_irq", mipi_irq_hdl} }; +static struct isp_irqs_data rv1106_isp_irqs[] = { + {"isp_irq", isp_irq_hdl}, + {"mi_irq", mi_irq_hdl}, + {"mipi_irq", mipi_irq_hdl} +}; + static struct isp_irqs_data rv1126_isp_irqs[] = { {"isp_irq", isp_irq_hdl}, {"mi_irq", mi_irq_hdl}, {"mipi_irq", mipi_irq_hdl} }; +static const struct isp_match_data rv1106_isp_match_data = { + .clks = rv1106_isp_clks, + .num_clks = ARRAY_SIZE(rv1106_isp_clks), + .isp_ver = ISP_V32, + .clk_rate_tbl = rv1106_isp_clk_rate, + .num_clk_rate_tbl = ARRAY_SIZE(rv1106_isp_clk_rate), + .irqs = rv1106_isp_irqs, + .num_irqs = ARRAY_SIZE(rv1106_isp_irqs), + .unite = false, +}; + static const struct isp_match_data rv1126_isp_match_data = { .clks = rv1126_isp_clks, .num_clks = ARRAY_SIZE(rv1126_isp_clks), @@ -614,6 +677,9 @@ static const struct of_device_id rkisp_hw_of_match[] = { }, { .compatible = "rockchip,rk3588-rkisp-unite", .data = &rk3588_isp_unite_match_data, + }, { + .compatible = "rockchip,rv1106-rkisp", + .data = &rv1106_isp_match_data, }, { .compatible = "rockchip,rv1126-rkisp", .data = &rv1126_isp_match_data, @@ -684,6 +750,8 @@ static void isp_config_clk(struct rkisp_hw_dev *dev, int on) if ((dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V30) && on) val |= ICCL_MPFBC_CLK; + if (dev->isp_ver == ISP_V32 && on) + val |= ISP32_BRSZ_CLK_ENABLE; writel(val, dev->base_addr + CIF_ICCL); if (dev->is_unite) @@ -697,9 +765,8 @@ static void isp_config_clk(struct rkisp_hw_dev *dev, int on) CIF_CLK_CTRL_CP | CIF_CLK_CTRL_IE; writel(val, dev->base_addr + CIF_VI_ISP_CLK_CTRL_V12); - } else if (dev->isp_ver == ISP_V20 || - dev->isp_ver == ISP_V21 || - dev->isp_ver == ISP_V30) { + } else if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 || + dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) { val = !on ? 0 : CLK_CTRL_MI_LDC | CLK_CTRL_MI_MP | CLK_CTRL_MI_JPEG | CLK_CTRL_MI_DP | @@ -708,7 +775,8 @@ static void isp_config_clk(struct rkisp_hw_dev *dev, int on) CLK_CTRL_MI_READ | CLK_CTRL_MI_RAWRD | CLK_CTRL_ISP_RAW; - if ((dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V30) && on) + if ((dev->isp_ver == ISP_V20 || + dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) && on) val |= CLK_CTRL_ISP_3A; writel(val, dev->base_addr + CTRL_VI_ISP_CLK_CTRL); if (dev->is_unite) @@ -758,6 +826,12 @@ static int enable_sys_clk(struct rkisp_hw_dev *dev) writel(0, dev->base_addr + CIF_ISP_CSI0_MASK1); writel(0, dev->base_addr + CIF_ISP_CSI0_MASK2); writel(0, dev->base_addr + CIF_ISP_CSI0_MASK3); + } else if (dev->isp_ver == ISP_V32) { + /* disable down samplling default */ + writel(ISP32_DS_DS_DIS, dev->base_addr + ISP32_MI_MPDS_WR_CTRL); + writel(ISP32_DS_DS_DIS, dev->base_addr + ISP32_MI_BPDS_WR_CTRL); + + writel(0, dev->base_addr + ISP32_BLS_ISP_OB_PREDGAIN); } return 0; diff --git a/drivers/media/platform/rockchip/isp/isp_params.c b/drivers/media/platform/rockchip/isp/isp_params.c index e470e3085428..f6463dadace4 100644 --- a/drivers/media/platform/rockchip/isp/isp_params.c +++ b/drivers/media/platform/rockchip/isp/isp_params.c @@ -13,6 +13,7 @@ #include "isp_params_v2x.h" #include "isp_params_v21.h" #include "isp_params_v3x.h" +#include "isp_params_v32.h" #define PARAMS_NAME DRIVER_NAME "-input-params" #define RKISP_ISP_PARAMS_REQ_BUFS_MIN 2 @@ -297,8 +298,10 @@ static int rkisp_init_params_vdev(struct rkisp_isp_params_vdev *params_vdev) ret = rkisp_init_params_vdev_v21(params_vdev); else if (params_vdev->dev->isp_ver == ISP_V20) ret = rkisp_init_params_vdev_v2x(params_vdev); - else + else if (params_vdev->dev->isp_ver == ISP_V30) ret = rkisp_init_params_vdev_v3x(params_vdev); + else + ret = rkisp_init_params_vdev_v32(params_vdev); params_vdev->vdev_fmt.fmt.meta.dataformat = V4L2_META_FMT_RK_ISP1_PARAMS; @@ -316,8 +319,10 @@ static void rkisp_uninit_params_vdev(struct rkisp_isp_params_vdev *params_vdev) rkisp_uninit_params_vdev_v21(params_vdev); else if (params_vdev->dev->isp_ver == ISP_V20) rkisp_uninit_params_vdev_v2x(params_vdev); - else + else if (params_vdev->dev->isp_ver == ISP_V30) rkisp_uninit_params_vdev_v3x(params_vdev); + else + rkisp_uninit_params_vdev_v32(params_vdev); } void rkisp_params_cfg(struct rkisp_isp_params_vdev *params_vdev, u32 frame_id) diff --git a/drivers/media/platform/rockchip/isp/isp_params.h b/drivers/media/platform/rockchip/isp/isp_params.h index fb4e3a2d7569..8297a1992d74 100644 --- a/drivers/media/platform/rockchip/isp/isp_params.h +++ b/drivers/media/platform/rockchip/isp/isp_params.h @@ -7,6 +7,7 @@ #include #include #include +#include #include #include "common.h" @@ -59,6 +60,7 @@ struct rkisp_isp_params_vdev { struct isp2x_isp_params_cfg *isp2x_params; struct isp21_isp_params_cfg *isp21_params; struct isp3x_isp_params_cfg *isp3x_params; + struct isp32_isp_params_cfg *isp32_params; }; struct v4l2_format vdev_fmt; bool streamon; diff --git a/drivers/media/platform/rockchip/isp/isp_params_v32.c b/drivers/media/platform/rockchip/isp/isp_params_v32.c new file mode 100644 index 000000000000..fe8cd47f82f6 --- /dev/null +++ b/drivers/media/platform/rockchip/isp/isp_params_v32.c @@ -0,0 +1,4466 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (c) 2021 Rockchip Electronics Co., Ltd. */ + +#include +#include +#include +#include /* for ISP params */ +#include "dev.h" +#include "regs.h" +#include "isp_params_v32.h" + +#define ISP32_MODULE_EN BIT(0) +#define ISP32_SELF_FORCE_UPD BIT(31) +#define ISP32_REG_WR_MASK BIT(31) //disable write protect + +#define ISP32_NOBIG_OVERFLOW_SIZE (1536 * 896) +#define ISP32_AUTO_BIGMODE_WIDTH 1536 +#define ISP32_VIR2_NOBIG_OVERFLOW_SIZE (960 * 540) +#define ISP32_VIR2_AUTO_BIGMODE_WIDTH 960 +#define ISP32_VIR4_NOBIG_OVERFLOW_SIZE (640 * 400) +#define ISP32_VIR4_AUTO_BIGMODE_WIDTH 1280 + +#define ISP32_VIR2_MAX_WIDTH 1920 +#define ISP32_VIR2_MAX_SIZE (1920 * 1080) +#define ISP32_VIR4_MAX_WIDTH 1280 +#define ISP32_VIR4_MAX_SIZE (1280 * 800) + +static inline void +isp3_param_write_direct(struct rkisp_isp_params_vdev *params_vdev, + u32 value, u32 addr) +{ + rkisp_write(params_vdev->dev, addr, value, true); +} + +static inline void +isp3_param_write(struct rkisp_isp_params_vdev *params_vdev, + u32 value, u32 addr) +{ + rkisp_write(params_vdev->dev, addr, value, false); +} + +static inline u32 +isp3_param_read_direct(struct rkisp_isp_params_vdev *params_vdev, u32 addr) +{ + return rkisp_read(params_vdev->dev, addr, true); +} + +static inline u32 +isp3_param_read(struct rkisp_isp_params_vdev *params_vdev, u32 addr) +{ + return rkisp_read(params_vdev->dev, addr, false); +} + +static inline u32 +isp3_param_read_cache(struct rkisp_isp_params_vdev *params_vdev, u32 addr) +{ + return rkisp_read_reg_cache(params_vdev->dev, addr); +} + +static inline void +isp3_param_set_bits(struct rkisp_isp_params_vdev *params_vdev, + u32 reg, u32 bit_mask) +{ + rkisp_set_bits(params_vdev->dev, reg, 0, bit_mask, false); +} + +static inline void +isp3_param_clear_bits(struct rkisp_isp_params_vdev *params_vdev, + u32 reg, u32 bit_mask) +{ + rkisp_clear_bits(params_vdev->dev, reg, bit_mask, false); +} + +static void +isp_dpcc_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp2x_dpcc_cfg *arg) +{ + u32 value; + int i; + + value = isp3_param_read(params_vdev, ISP3X_DPCC0_MODE); + value &= ISP_DPCC_EN; + + value |= !!arg->stage1_enable << 2 | + !!arg->grayscale_mode << 1; + isp3_param_write(params_vdev, value, ISP3X_DPCC0_MODE); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_MODE); + + value = (arg->sw_rk_out_sel & 0x03) << 5 | + !!arg->sw_dpcc_output_sel << 4 | + !!arg->stage1_rb_3x3 << 3 | + !!arg->stage1_g_3x3 << 2 | + !!arg->stage1_incl_rb_center << 1 | + !!arg->stage1_incl_green_center; + isp3_param_write(params_vdev, value, ISP3X_DPCC0_OUTPUT_MODE); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_OUTPUT_MODE); + + value = !!arg->stage1_use_fix_set << 3 | + !!arg->stage1_use_set_3 << 2 | + !!arg->stage1_use_set_2 << 1 | + !!arg->stage1_use_set_1; + isp3_param_write(params_vdev, value, ISP3X_DPCC0_SET_USE); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_SET_USE); + + value = !!arg->sw_rk_red_blue1_en << 13 | + !!arg->rg_red_blue1_enable << 12 | + !!arg->rnd_red_blue1_enable << 11 | + !!arg->ro_red_blue1_enable << 10 | + !!arg->lc_red_blue1_enable << 9 | + !!arg->pg_red_blue1_enable << 8 | + !!arg->sw_rk_green1_en << 5 | + !!arg->rg_green1_enable << 4 | + !!arg->rnd_green1_enable << 3 | + !!arg->ro_green1_enable << 2 | + !!arg->lc_green1_enable << 1 | + !!arg->pg_green1_enable; + isp3_param_write(params_vdev, value, ISP3X_DPCC0_METHODS_SET_1); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_METHODS_SET_1); + + value = !!arg->sw_rk_red_blue2_en << 13 | + !!arg->rg_red_blue2_enable << 12 | + !!arg->rnd_red_blue2_enable << 11 | + !!arg->ro_red_blue2_enable << 10 | + !!arg->lc_red_blue2_enable << 9 | + !!arg->pg_red_blue2_enable << 8 | + !!arg->sw_rk_green2_en << 5 | + !!arg->rg_green2_enable << 4 | + !!arg->rnd_green2_enable << 3 | + !!arg->ro_green2_enable << 2 | + !!arg->lc_green2_enable << 1 | + !!arg->pg_green2_enable; + isp3_param_write(params_vdev, value, ISP3X_DPCC0_METHODS_SET_2); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_METHODS_SET_2); + + value = !!arg->sw_rk_red_blue3_en << 13 | + !!arg->rg_red_blue3_enable << 12 | + !!arg->rnd_red_blue3_enable << 11 | + !!arg->ro_red_blue3_enable << 10 | + !!arg->lc_red_blue3_enable << 9 | + !!arg->pg_red_blue3_enable << 8 | + !!arg->sw_rk_green3_en << 5 | + !!arg->rg_green3_enable << 4 | + !!arg->rnd_green3_enable << 3 | + !!arg->ro_green3_enable << 2 | + !!arg->lc_green3_enable << 1 | + !!arg->pg_green3_enable; + isp3_param_write(params_vdev, value, ISP3X_DPCC0_METHODS_SET_3); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_METHODS_SET_3); + + value = ISP_PACK_4BYTE(arg->line_thr_1_g, arg->line_thr_1_rb, + arg->sw_mindis1_g, arg->sw_mindis1_rb); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_THRESH_1); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_THRESH_1); + + value = ISP_PACK_4BYTE(arg->line_mad_fac_1_g, arg->line_mad_fac_1_rb, + arg->sw_dis_scale_max1, arg->sw_dis_scale_min1); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_MAD_FAC_1); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_MAD_FAC_1); + + value = ISP_PACK_4BYTE(arg->pg_fac_1_g, arg->pg_fac_1_rb, 0, 0); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_PG_FAC_1); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_PG_FAC_1); + + value = ISP_PACK_4BYTE(arg->rnd_thr_1_g, arg->rnd_thr_1_rb, 0, 0); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_RND_THRESH_1); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_RND_THRESH_1); + + value = ISP_PACK_4BYTE(arg->rg_fac_1_g, arg->rg_fac_1_rb, 0, 0); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_RG_FAC_1); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_RG_FAC_1); + + value = ISP_PACK_4BYTE(arg->line_thr_2_g, arg->line_thr_2_rb, + arg->sw_mindis2_g, arg->sw_mindis2_rb); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_THRESH_2); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_THRESH_2); + + value = ISP_PACK_4BYTE(arg->line_mad_fac_2_g, arg->line_mad_fac_2_rb, + arg->sw_dis_scale_max2, arg->sw_dis_scale_min2); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_MAD_FAC_2); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_MAD_FAC_2); + + value = ISP_PACK_4BYTE(arg->pg_fac_2_g, arg->pg_fac_2_rb, 0, 0); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_PG_FAC_2); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_PG_FAC_2); + + value = ISP_PACK_4BYTE(arg->rnd_thr_2_g, arg->rnd_thr_2_rb, 0, 0); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_RND_THRESH_2); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_RND_THRESH_2); + + value = ISP_PACK_4BYTE(arg->rg_fac_2_g, arg->rg_fac_2_rb, 0, 0); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_RG_FAC_2); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_RG_FAC_2); + + value = ISP_PACK_4BYTE(arg->line_thr_3_g, arg->line_thr_3_rb, + arg->sw_mindis3_g, arg->sw_mindis3_rb); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_THRESH_3); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_THRESH_3); + + value = ISP_PACK_4BYTE(arg->line_mad_fac_3_g, arg->line_mad_fac_3_rb, + arg->sw_dis_scale_max3, arg->sw_dis_scale_min3); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_MAD_FAC_3); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_MAD_FAC_3); + + value = ISP_PACK_4BYTE(arg->pg_fac_3_g, arg->pg_fac_3_rb, 0, 0); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_PG_FAC_3); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_PG_FAC_3); + + value = ISP_PACK_4BYTE(arg->rnd_thr_3_g, arg->rnd_thr_3_rb, 0, 0); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_RND_THRESH_3); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_RND_THRESH_3); + + value = ISP_PACK_4BYTE(arg->rg_fac_3_g, arg->rg_fac_3_rb, 0, 0); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_RG_FAC_3); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_RG_FAC_3); + + value = (arg->ro_lim_3_rb & 0x03) << 10 | + (arg->ro_lim_3_g & 0x03) << 8 | + (arg->ro_lim_2_rb & 0x03) << 6 | + (arg->ro_lim_2_g & 0x03) << 4 | + (arg->ro_lim_1_rb & 0x03) << 2 | + (arg->ro_lim_1_g & 0x03); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_RO_LIMITS); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_RO_LIMITS); + + value = (arg->rnd_offs_3_rb & 0x03) << 10 | + (arg->rnd_offs_3_g & 0x03) << 8 | + (arg->rnd_offs_2_rb & 0x03) << 6 | + (arg->rnd_offs_2_g & 0x03) << 4 | + (arg->rnd_offs_1_rb & 0x03) << 2 | + (arg->rnd_offs_1_g & 0x03); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_RND_OFFS); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_RND_OFFS); + + value = !!arg->bpt_rb_3x3 << 11 | + !!arg->bpt_g_3x3 << 10 | + !!arg->bpt_incl_rb_center << 9 | + !!arg->bpt_incl_green_center << 8 | + !!arg->bpt_use_fix_set << 7 | + !!arg->bpt_use_set_3 << 6 | + !!arg->bpt_use_set_2 << 5 | + !!arg->bpt_use_set_1 << 4 | + !!arg->bpt_cor_en << 1 | + !!arg->bpt_det_en; + isp3_param_write(params_vdev, value, ISP3X_DPCC0_BPT_CTRL); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_BPT_CTRL); + + isp3_param_write(params_vdev, arg->bp_number, ISP3X_DPCC0_BPT_NUMBER); + isp3_param_write(params_vdev, arg->bp_number, ISP3X_DPCC1_BPT_NUMBER); + isp3_param_write(params_vdev, arg->bp_table_addr, ISP3X_DPCC0_BPT_ADDR); + isp3_param_write(params_vdev, arg->bp_table_addr, ISP3X_DPCC1_BPT_ADDR); + + value = ISP_PACK_2SHORT(arg->bpt_h_addr, arg->bpt_v_addr); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_BPT_DATA); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_BPT_DATA); + + isp3_param_write(params_vdev, arg->bp_cnt, ISP3X_DPCC0_BP_CNT); + isp3_param_write(params_vdev, arg->bp_cnt, ISP3X_DPCC1_BP_CNT); + + isp3_param_write(params_vdev, arg->sw_pdaf_en, ISP3X_DPCC0_PDAF_EN); + isp3_param_write(params_vdev, arg->sw_pdaf_en, ISP3X_DPCC1_PDAF_EN); + + value = 0; + for (i = 0; i < ISP32_DPCC_PDAF_POINT_NUM; i++) + value |= !!arg->pdaf_point_en[i] << i; + isp3_param_write(params_vdev, value, ISP3X_DPCC0_PDAF_POINT_EN); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_PDAF_POINT_EN); + + value = ISP_PACK_2SHORT(arg->pdaf_offsetx, arg->pdaf_offsety); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_PDAF_OFFSET); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_PDAF_OFFSET); + + value = ISP_PACK_2SHORT(arg->pdaf_wrapx, arg->pdaf_wrapy); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_PDAF_WRAP); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_PDAF_WRAP); + + value = ISP_PACK_2SHORT(arg->pdaf_wrapx_num, arg->pdaf_wrapy_num); + isp3_param_write(params_vdev, value, ISP_DPCC0_PDAF_SCOPE); + isp3_param_write(params_vdev, value, ISP_DPCC1_PDAF_SCOPE); + + for (i = 0; i < ISP32_DPCC_PDAF_POINT_NUM / 2; i++) { + value = ISP_PACK_4BYTE(arg->point[2 * i].x, arg->point[2 * i].y, + arg->point[2 * i + 1].x, arg->point[2 * i + 1].y); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_PDAF_POINT_0 + 4 * i); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_PDAF_POINT_0 + 4 * i); + } + + isp3_param_write(params_vdev, arg->pdaf_forward_med, ISP3X_DPCC0_PDAF_FORWARD_MED); + isp3_param_write(params_vdev, arg->pdaf_forward_med, ISP3X_DPCC1_PDAF_FORWARD_MED); +} + +static void +isp_dpcc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + u32 value; + + value = isp3_param_read(params_vdev, ISP3X_DPCC0_MODE); + value &= ~ISP_DPCC_EN; + + if (en) + value |= ISP_DPCC_EN; + isp3_param_write(params_vdev, value, ISP3X_DPCC0_MODE); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_MODE); +} + +static void +isp_bls_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_bls_cfg *arg) +{ + const struct isp2x_bls_fixed_val *pval; + u32 new_control, value; + + new_control = isp3_param_read(params_vdev, ISP3X_BLS_CTRL); + new_control &= ISP_BLS_ENA; + + pval = &arg->bls1_val; + if (arg->bls1_en) { + new_control |= ISP_BLS_BLS1_EN; + + switch (params_vdev->raw_type) { + case RAW_BGGR: + isp3_param_write(params_vdev, pval->r, ISP3X_BLS1_D_FIXED); + isp3_param_write(params_vdev, pval->gr, ISP3X_BLS1_C_FIXED); + isp3_param_write(params_vdev, pval->gb, ISP3X_BLS1_B_FIXED); + isp3_param_write(params_vdev, pval->b, ISP3X_BLS1_A_FIXED); + break; + case RAW_GBRG: + isp3_param_write(params_vdev, pval->r, ISP3X_BLS1_C_FIXED); + isp3_param_write(params_vdev, pval->gr, ISP3X_BLS1_D_FIXED); + isp3_param_write(params_vdev, pval->gb, ISP3X_BLS1_A_FIXED); + isp3_param_write(params_vdev, pval->b, ISP3X_BLS1_B_FIXED); + break; + case RAW_GRBG: + isp3_param_write(params_vdev, pval->r, ISP3X_BLS1_B_FIXED); + isp3_param_write(params_vdev, pval->gr, ISP3X_BLS1_A_FIXED); + isp3_param_write(params_vdev, pval->gb, ISP3X_BLS1_D_FIXED); + isp3_param_write(params_vdev, pval->b, ISP3X_BLS1_C_FIXED); + break; + case RAW_RGGB: + default: + isp3_param_write(params_vdev, pval->r, ISP3X_BLS1_A_FIXED); + isp3_param_write(params_vdev, pval->gr, ISP3X_BLS1_B_FIXED); + isp3_param_write(params_vdev, pval->gb, ISP3X_BLS1_C_FIXED); + isp3_param_write(params_vdev, pval->b, ISP3X_BLS1_D_FIXED); + break; + } + } + + pval = &arg->bls2_val; + if (arg->bls2_en) { + new_control |= ISP32_BLS_BLS2_EN; + + switch (params_vdev->raw_type) { + case RAW_BGGR: + isp3_param_write(params_vdev, pval->r, ISP32_BLS2_D_FIXED); + isp3_param_write(params_vdev, pval->gr, ISP32_BLS2_C_FIXED); + isp3_param_write(params_vdev, pval->gb, ISP32_BLS2_B_FIXED); + isp3_param_write(params_vdev, pval->b, ISP32_BLS2_A_FIXED); + break; + case RAW_GBRG: + isp3_param_write(params_vdev, pval->r, ISP32_BLS2_C_FIXED); + isp3_param_write(params_vdev, pval->gr, ISP32_BLS2_D_FIXED); + isp3_param_write(params_vdev, pval->gb, ISP32_BLS2_A_FIXED); + isp3_param_write(params_vdev, pval->b, ISP32_BLS2_B_FIXED); + break; + case RAW_GRBG: + isp3_param_write(params_vdev, pval->r, ISP32_BLS2_B_FIXED); + isp3_param_write(params_vdev, pval->gr, ISP32_BLS2_A_FIXED); + isp3_param_write(params_vdev, pval->gb, ISP32_BLS2_D_FIXED); + isp3_param_write(params_vdev, pval->b, ISP32_BLS2_C_FIXED); + break; + case RAW_RGGB: + default: + isp3_param_write(params_vdev, pval->r, ISP32_BLS2_A_FIXED); + isp3_param_write(params_vdev, pval->gr, ISP32_BLS2_B_FIXED); + isp3_param_write(params_vdev, pval->gb, ISP32_BLS2_C_FIXED); + isp3_param_write(params_vdev, pval->b, ISP32_BLS2_D_FIXED); + break; + } + } + + /* fixed subtraction values */ + pval = &arg->fixed_val; + if (!arg->enable_auto) { + switch (params_vdev->raw_type) { + case RAW_BGGR: + isp3_param_write(params_vdev, pval->r, ISP3X_BLS_D_FIXED); + isp3_param_write(params_vdev, pval->gr, ISP3X_BLS_C_FIXED); + isp3_param_write(params_vdev, pval->gb, ISP3X_BLS_B_FIXED); + isp3_param_write(params_vdev, pval->b, ISP3X_BLS_A_FIXED); + break; + case RAW_GBRG: + isp3_param_write(params_vdev, pval->r, ISP3X_BLS_C_FIXED); + isp3_param_write(params_vdev, pval->gr, ISP3X_BLS_D_FIXED); + isp3_param_write(params_vdev, pval->gb, ISP3X_BLS_A_FIXED); + isp3_param_write(params_vdev, pval->b, ISP3X_BLS_B_FIXED); + break; + case RAW_GRBG: + isp3_param_write(params_vdev, pval->r, ISP3X_BLS_B_FIXED); + isp3_param_write(params_vdev, pval->gr, ISP3X_BLS_A_FIXED); + isp3_param_write(params_vdev, pval->gb, ISP3X_BLS_D_FIXED); + isp3_param_write(params_vdev, pval->b, ISP3X_BLS_C_FIXED); + break; + case RAW_RGGB: + default: + isp3_param_write(params_vdev, pval->r, ISP3X_BLS_A_FIXED); + isp3_param_write(params_vdev, pval->gr, ISP3X_BLS_B_FIXED); + isp3_param_write(params_vdev, pval->gb, ISP3X_BLS_C_FIXED); + isp3_param_write(params_vdev, pval->b, ISP3X_BLS_D_FIXED); + break; + } + } else { + if (arg->en_windows & BIT(1)) { + isp3_param_write(params_vdev, arg->bls_window2.h_offs, ISP3X_BLS_H2_START); + value = arg->bls_window2.h_offs + arg->bls_window2.h_size; + isp3_param_write(params_vdev, value, ISP3X_BLS_H2_STOP); + isp3_param_write(params_vdev, arg->bls_window2.v_offs, ISP3X_BLS_V2_START); + value = arg->bls_window2.v_offs + arg->bls_window2.v_size; + isp3_param_write(params_vdev, value, ISP3X_BLS_V2_STOP); + new_control |= ISP_BLS_WINDOW_2; + } + + if (arg->en_windows & BIT(0)) { + isp3_param_write(params_vdev, arg->bls_window1.h_offs, ISP3X_BLS_H1_START); + value = arg->bls_window1.h_offs + arg->bls_window1.h_size; + isp3_param_write(params_vdev, value, ISP3X_BLS_H1_STOP); + isp3_param_write(params_vdev, arg->bls_window1.v_offs, ISP3X_BLS_V1_START); + value = arg->bls_window1.v_offs + arg->bls_window1.v_size; + isp3_param_write(params_vdev, value, ISP3X_BLS_V1_STOP); + new_control |= ISP_BLS_WINDOW_1; + } + + isp3_param_write(params_vdev, arg->bls_samples, ISP3X_BLS_SAMPLES); + + new_control |= ISP_BLS_MODE_MEASURED; + } + isp3_param_write(params_vdev, new_control, ISP3X_BLS_CTRL); + + isp3_param_write(params_vdev, arg->isp_ob_offset, ISP32_BLS_ISP_OB_OFFSET); + isp3_param_write(params_vdev, arg->isp_ob_predgain, ISP32_BLS_ISP_OB_PREDGAIN); + isp3_param_write(params_vdev, arg->isp_ob_max, ISP32_BLS_ISP_OB_MAX); +} + +static void +isp_bls_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + u32 new_control; + + new_control = isp3_param_read(params_vdev, ISP3X_BLS_CTRL); + if (en) + new_control |= ISP_BLS_ENA; + else + new_control &= ~ISP_BLS_ENA; + isp3_param_write(params_vdev, new_control, ISP3X_BLS_CTRL); +} + +static void +isp_sdg_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp2x_sdg_cfg *arg) +{ + int i; + + isp3_param_write(params_vdev, arg->xa_pnts.gamma_dx0, ISP3X_ISP_GAMMA_DX_LO); + isp3_param_write(params_vdev, arg->xa_pnts.gamma_dx1, ISP3X_ISP_GAMMA_DX_HI); + + for (i = 0; i < ISP32_DEGAMMA_CURVE_SIZE; i++) { + isp3_param_write(params_vdev, arg->curve_r.gamma_y[i], + ISP3X_ISP_GAMMA_R_Y_0 + i * 4); + isp3_param_write(params_vdev, arg->curve_g.gamma_y[i], + ISP3X_ISP_GAMMA_G_Y_0 + i * 4); + isp3_param_write(params_vdev, arg->curve_b.gamma_y[i], + ISP3X_ISP_GAMMA_B_Y_0 + i * 4); + } +} + +static void +isp_sdg_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + if (en) + isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL0, + CIF_ISP_CTRL_ISP_GAMMA_IN_ENA); + else + isp3_param_clear_bits(params_vdev, ISP3X_ISP_CTRL0, + CIF_ISP_CTRL_ISP_GAMMA_IN_ENA); +} + +static void +isp_lsc_matrix_cfg_sram(struct rkisp_isp_params_vdev *params_vdev, + const struct isp3x_lsc_cfg *pconfig, + bool is_check) +{ + struct rkisp_device *dev = params_vdev->dev; + u32 sram_addr, data, table; + int i, j; + + if (is_check && + !(isp3_param_read(params_vdev, ISP3X_LSC_CTRL) & ISP_LSC_EN)) + return; + + table = isp3_param_read_direct(params_vdev, ISP3X_LSC_STATUS); + table &= ISP3X_LSC_ACTIVE_TABLE; + /* default table 0 for multi device */ + if (!dev->hw_dev->is_single) + table = ISP3X_LSC_ACTIVE_TABLE; + + /* CIF_ISP_LSC_TABLE_ADDRESS_153 = ( 17 * 18 ) >> 1 */ + sram_addr = table ? ISP3X_LSC_TABLE_ADDRESS_0 : CIF_ISP_LSC_TABLE_ADDRESS_153; + isp3_param_write_direct(params_vdev, sram_addr, ISP3X_LSC_R_TABLE_ADDR); + isp3_param_write_direct(params_vdev, sram_addr, ISP3X_LSC_GR_TABLE_ADDR); + isp3_param_write_direct(params_vdev, sram_addr, ISP3X_LSC_GB_TABLE_ADDR); + isp3_param_write_direct(params_vdev, sram_addr, ISP3X_LSC_B_TABLE_ADDR); + + /* program data tables (table size is 9 * 17 = 153) */ + for (i = 0; i < CIF_ISP_LSC_SECTORS_MAX * CIF_ISP_LSC_SECTORS_MAX; + i += CIF_ISP_LSC_SECTORS_MAX) { + /* + * 17 sectors with 2 values in one DWORD = 9 + * DWORDs (2nd value of last DWORD unused) + */ + for (j = 0; j < CIF_ISP_LSC_SECTORS_MAX - 1; j += 2) { + data = ISP_ISP_LSC_TABLE_DATA(pconfig->r_data_tbl[i + j], + pconfig->r_data_tbl[i + j + 1]); + isp3_param_write_direct(params_vdev, data, ISP3X_LSC_R_TABLE_DATA); + + data = ISP_ISP_LSC_TABLE_DATA(pconfig->gr_data_tbl[i + j], + pconfig->gr_data_tbl[i + j + 1]); + isp3_param_write_direct(params_vdev, data, ISP3X_LSC_GR_TABLE_DATA); + + data = ISP_ISP_LSC_TABLE_DATA(pconfig->gb_data_tbl[i + j], + pconfig->gb_data_tbl[i + j + 1]); + isp3_param_write_direct(params_vdev, data, ISP3X_LSC_GB_TABLE_DATA); + + data = ISP_ISP_LSC_TABLE_DATA(pconfig->b_data_tbl[i + j], + pconfig->b_data_tbl[i + j + 1]); + isp3_param_write_direct(params_vdev, data, ISP3X_LSC_B_TABLE_DATA); + } + + data = ISP_ISP_LSC_TABLE_DATA(pconfig->r_data_tbl[i + j], 0); + isp3_param_write_direct(params_vdev, data, ISP3X_LSC_R_TABLE_DATA); + + data = ISP_ISP_LSC_TABLE_DATA(pconfig->gr_data_tbl[i + j], 0); + isp3_param_write_direct(params_vdev, data, ISP3X_LSC_GR_TABLE_DATA); + + data = ISP_ISP_LSC_TABLE_DATA(pconfig->gb_data_tbl[i + j], 0); + isp3_param_write_direct(params_vdev, data, ISP3X_LSC_GB_TABLE_DATA); + + data = ISP_ISP_LSC_TABLE_DATA(pconfig->b_data_tbl[i + j], 0); + isp3_param_write_direct(params_vdev, data, ISP3X_LSC_B_TABLE_DATA); + } + isp3_param_write_direct(params_vdev, !table, ISP3X_LSC_TABLE_SEL); +} + +static void +isp_lsc_cfg_sram_task(unsigned long data) +{ + struct rkisp_isp_params_vdev *params_vdev = + (struct rkisp_isp_params_vdev *)data; + struct isp32_isp_params_cfg *params = params_vdev->isp32_params; + + isp_lsc_matrix_cfg_sram(params_vdev, ¶ms->others.lsc_cfg, true); +} + +static void +isp_lsc_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp3x_lsc_cfg *arg) +{ + struct rkisp_isp_params_val_v32 *priv_val = + (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; + struct isp32_isp_params_cfg *params_rec = params_vdev->isp32_params; + struct rkisp_device *dev = params_vdev->dev; + u32 data, lsc_ctrl; + int i; + + /* To config must be off , store the current status firstly */ + lsc_ctrl = isp3_param_read(params_vdev, ISP3X_LSC_CTRL); + isp3_param_clear_bits(params_vdev, ISP3X_LSC_CTRL, ISP_LSC_EN | BIT(2)); + params_rec->others.lsc_cfg = *arg; + if (dev->hw_dev->is_single) { + if (lsc_ctrl & ISP_LSC_EN) + tasklet_schedule(&priv_val->lsc_tasklet); + else + isp_lsc_matrix_cfg_sram(params_vdev, arg, false); + } + + for (i = 0; i < ISP32_LSC_SIZE_TBL_SIZE / 4; i++) { + /* program x size tables */ + data = CIF_ISP_LSC_SECT_SIZE(arg->x_size_tbl[i * 2], arg->x_size_tbl[i * 2 + 1]); + isp3_param_write(params_vdev, data, ISP3X_LSC_XSIZE_01 + i * 4); + data = CIF_ISP_LSC_SECT_SIZE(arg->x_size_tbl[i * 2 + 8], arg->x_size_tbl[i * 2 + 9]); + isp3_param_write(params_vdev, data, ISP3X_LSC_XSIZE_89 + i * 4); + + /* program x grad tables */ + data = CIF_ISP_LSC_SECT_SIZE(arg->x_grad_tbl[i * 2], arg->x_grad_tbl[i * 2 + 1]); + isp3_param_write(params_vdev, data, ISP3X_LSC_XGRAD_01 + i * 4); + data = CIF_ISP_LSC_SECT_SIZE(arg->x_grad_tbl[i * 2 + 8], arg->x_grad_tbl[i * 2 + 9]); + isp3_param_write(params_vdev, data, ISP3X_LSC_XGRAD_89 + i * 4); + + /* program y size tables */ + data = CIF_ISP_LSC_SECT_SIZE(arg->y_size_tbl[i * 2], arg->y_size_tbl[i * 2 + 1]); + isp3_param_write(params_vdev, data, ISP3X_LSC_YSIZE_01 + i * 4); + data = CIF_ISP_LSC_SECT_SIZE(arg->y_size_tbl[i * 2 + 8], arg->y_size_tbl[i * 2 + 9]); + isp3_param_write(params_vdev, data, ISP3X_LSC_YSIZE_89 + i * 4); + + /* program y grad tables */ + data = CIF_ISP_LSC_SECT_SIZE(arg->y_grad_tbl[i * 2], arg->y_grad_tbl[i * 2 + 1]); + isp3_param_write(params_vdev, data, ISP3X_LSC_YGRAD_01 + i * 4); + data = CIF_ISP_LSC_SECT_SIZE(arg->y_grad_tbl[i * 2 + 8], arg->y_grad_tbl[i * 2 + 9]); + isp3_param_write(params_vdev, data, ISP3X_LSC_YGRAD_89 + i * 4); + } + + if (arg->sector_16x16) + lsc_ctrl |= BIT(2); + isp3_param_set_bits(params_vdev, ISP3X_LSC_CTRL, lsc_ctrl); +} + +static void +isp_lsc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + u32 val = ISP_LSC_EN; + + if (en) { + isp3_param_set_bits(params_vdev, ISP3X_LSC_CTRL, val); + } else { + isp3_param_clear_bits(params_vdev, ISP3X_LSC_CTRL, ISP_LSC_EN); + isp3_param_clear_bits(params_vdev, ISP3X_GAIN_CTRL, BIT(8)); + } +} + +static void +isp_debayer_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_debayer_cfg *arg) +{ + u32 value; + + value = isp3_param_read(params_vdev, ISP3X_DEBAYER_CONTROL); + value &= ISP_DEBAYER_EN; + + value |= !!arg->filter_c_en << 8 | + !!arg->filter_g_en << 4; + isp3_param_write(params_vdev, value, ISP3X_DEBAYER_CONTROL); + + value = (arg->max_ratio & 0x3F) << 24 | arg->select_thed << 16 | + (arg->thed1 & 0x0F) << 12 | (arg->thed0 & 0x0F) << 8 | + (arg->dist_scale & 0x0F) << 4 | !!arg->clip_en; + isp3_param_write(params_vdev, value, ISP3X_DEBAYER_G_INTERP); + + value = (arg->filter1_coe4 & 0x1F) << 24 | (arg->filter1_coe3 & 0x1F) << 16 | + (arg->filter1_coe2 & 0x1F) << 8 | (arg->filter1_coe1 & 0x1F); + isp3_param_write(params_vdev, value, ISP3X_DEBAYER_G_INTERP_FILTER1); + + value = (arg->filter2_coe4 & 0x1F) << 24 | (arg->filter2_coe3 & 0x1F) << 16 | + (arg->filter2_coe2 & 0x1F) << 8 | (arg->filter2_coe1 & 0x1F); + isp3_param_write(params_vdev, value, ISP3X_DEBAYER_G_INTERP_FILTER2); + + value = arg->hf_offset << 16 | (arg->gain_offset & 0xFFF); + isp3_param_write(params_vdev, value, ISP32_DEBAYER_G_INTERP_OFFSET); + + value = (arg->offset & 0x7FF); + isp3_param_write(params_vdev, value, ISP32_DEBAYER_G_FILTER_OFFSET); + + value = arg->guid_gaus_coe2 << 16 | + arg->guid_gaus_coe1 << 8 | arg->guid_gaus_coe0; + isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_GUIDE_GAUS); + + value = arg->ce_gaus_coe2 << 16 | + arg->ce_gaus_coe1 << 8 | arg->ce_gaus_coe0; + isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_CE_GAUS); + + value = arg->alpha_gaus_coe2 << 16 | + arg->alpha_gaus_coe1 << 8 | arg->alpha_gaus_coe0; + isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_ALPHA_GAUS); + + value = (arg->loggd_offset & 0xfff) << 16 | (arg->loghf_offset & 0x1fff); + isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_LOG_OFFSET); + + value = (arg->alpha_scale & 0xfffff) << 12 | (arg->alpha_offset & 0xfff); + isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_ALPHA); + + value = (arg->edge_scale & 0xfffff) << 12 | (arg->edge_offset & 0xfff); + isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_EDGE); + + value = (arg->wgtslope & 0xfff) << 16 | + (arg->exp_shift & 0x3f) << 8 | arg->ce_sgm; + isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_IIR_0); + + value = (arg->wet_ghost & 0x3f) << 8 | (arg->wet_clip & 0x7f); + isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_IIR_1); + + value = (arg->bf_curwgt & 0x7f) << 24 | + (arg->bf_clip & 0x7f) << 16 | arg->bf_sgm; + isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_BF); +} + +static void +isp_debayer_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + if (en) + isp3_param_set_bits(params_vdev, + ISP3X_DEBAYER_CONTROL, ISP32_MODULE_EN); + else + isp3_param_clear_bits(params_vdev, + ISP3X_DEBAYER_CONTROL, ISP32_MODULE_EN); +} + +static void +isp_awbgain_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_awb_gain_cfg *arg) +{ + struct rkisp_device *dev = params_vdev->dev; + + if (!arg->gain0_red || !arg->gain0_blue || + !arg->gain1_red || !arg->gain1_blue || + !arg->gain2_red || !arg->gain2_blue || + !arg->gain0_green_r || !arg->gain0_green_b || + !arg->gain1_green_r || !arg->gain1_green_b || + !arg->gain2_green_r || !arg->gain2_green_b) { + dev_err(dev->dev, "awb gain is zero!\n"); + return; + } + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->gain0_green_b, arg->gain0_green_r), + ISP3X_ISP_AWB_GAIN0_G); + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->gain0_blue, arg->gain0_red), + ISP3X_ISP_AWB_GAIN0_RB); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->gain1_green_b, arg->gain1_green_r), + ISP3X_ISP_AWB_GAIN1_G); + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->gain1_blue, arg->gain1_red), + ISP3X_ISP_AWB_GAIN1_RB); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->gain2_green_b, arg->gain2_green_r), + ISP3X_ISP_AWB_GAIN2_G); + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->gain2_blue, arg->gain2_red), + ISP3X_ISP_AWB_GAIN2_RB); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->awb1_gain_gb, arg->awb1_gain_gr), + ISP32_ISP_AWB1_GAIN_G); + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->awb1_gain_b, arg->awb1_gain_r), + ISP32_ISP_AWB1_GAIN_RB); +} + +static void +isp_awbgain_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + if (en) + isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL0, + CIF_ISP_CTRL_ISP_AWB_ENA); + else + isp3_param_clear_bits(params_vdev, ISP3X_ISP_CTRL0, + CIF_ISP_CTRL_ISP_AWB_ENA); +} + +static void +isp_ccm_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_ccm_cfg *arg) +{ + u32 value; + u32 i; + + value = isp3_param_read(params_vdev, ISP3X_CCM_CTRL); + value &= ISP_CCM_EN; + + value |= !!arg->asym_adj_en << 3 | + !!arg->enh_adj_en << 2 | + !!arg->highy_adjust_dis << 1; + isp3_param_write(params_vdev, value, ISP3X_CCM_CTRL); + + value = ISP_PACK_2SHORT(arg->coeff0_r, arg->coeff1_r); + isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF0_R); + + value = ISP_PACK_2SHORT(arg->coeff2_r, arg->offset_r); + isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF1_R); + + value = ISP_PACK_2SHORT(arg->coeff0_g, arg->coeff1_g); + isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF0_G); + + value = ISP_PACK_2SHORT(arg->coeff2_g, arg->offset_g); + isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF1_G); + + value = ISP_PACK_2SHORT(arg->coeff0_b, arg->coeff1_b); + isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF0_B); + + value = ISP_PACK_2SHORT(arg->coeff2_b, arg->offset_b); + isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF1_B); + + value = ISP_PACK_2SHORT(arg->coeff0_y, arg->coeff1_y); + isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF0_Y); + + value = ISP_PACK_2SHORT(arg->coeff2_y, 0); + isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF1_Y); + + for (i = 0; i < ISP32_CCM_CURVE_NUM / 2; i++) { + value = ISP_PACK_2SHORT(arg->alp_y[2 * i], arg->alp_y[2 * i + 1]); + isp3_param_write(params_vdev, value, ISP3X_CCM_ALP_Y0 + 4 * i); + } + + value = (arg->right_bit & 0xf) << 4 | (arg->bound_bit & 0xf); + isp3_param_write(params_vdev, value, ISP3X_CCM_BOUND_BIT); + + value = (arg->color_coef1_g2y & 0x7ff) << 16 | + (arg->color_coef0_r2y & 0x7ff); + isp3_param_write(params_vdev, value, ISP32_CCM_ENHANCE0); + + value = (arg->color_enh_rat_max & 0x3fff) << 16 | + (arg->color_coef2_b2y & 0x7ff); + isp3_param_write(params_vdev, value, ISP32_CCM_ENHANCE1); +} + +static void +isp_ccm_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + if (en) + isp3_param_set_bits(params_vdev, ISP3X_CCM_CTRL, ISP_CCM_EN); + else + isp3_param_clear_bits(params_vdev, ISP3X_CCM_CTRL, ISP_CCM_EN); +} + +static void +isp_goc_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp3x_gammaout_cfg *arg) +{ + int i; + u32 value; + + value = isp3_param_read(params_vdev, ISP3X_GAMMA_OUT_CTRL); + value &= ISP3X_GAMMA_OUT_EN; + value |= !!arg->equ_segm << 1 | !!arg->finalx4_dense_en << 2; + isp3_param_write(params_vdev, value, ISP3X_GAMMA_OUT_CTRL); + + isp3_param_write(params_vdev, arg->offset, ISP3X_GAMMA_OUT_OFFSET); + for (i = 0; i < ISP32_GAMMA_OUT_MAX_SAMPLES / 2; i++) { + value = ISP_PACK_2SHORT(arg->gamma_y[2 * i], + arg->gamma_y[2 * i + 1]); + isp3_param_write(params_vdev, value, ISP3X_GAMMA_OUT_Y0 + i * 4); + } + isp3_param_write(params_vdev, arg->gamma_y[2 * i], ISP3X_GAMMA_OUT_Y0 + i * 4); +} + +static void +isp_goc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + if (en) + isp3_param_set_bits(params_vdev, ISP3X_GAMMA_OUT_CTRL, ISP3X_GAMMA_OUT_EN); + else + isp3_param_clear_bits(params_vdev, ISP3X_GAMMA_OUT_CTRL, ISP3X_GAMMA_OUT_EN); +} + +static void +isp_cproc_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp2x_cproc_cfg *arg) +{ + struct isp32_isp_params_cfg *params = params_vdev->isp32_params; + struct isp32_isp_other_cfg *cur_other_cfg = ¶ms->others; + struct isp2x_ie_cfg *cur_ie_config = &cur_other_cfg->ie_cfg; + u32 effect = cur_ie_config->effect; + u32 quantization = params_vdev->quantization; + + isp3_param_write(params_vdev, arg->contrast, ISP3X_CPROC_CONTRAST); + isp3_param_write(params_vdev, arg->hue, ISP3X_CPROC_HUE); + isp3_param_write(params_vdev, arg->sat, ISP3X_CPROC_SATURATION); + isp3_param_write(params_vdev, arg->brightness, ISP3X_CPROC_BRIGHTNESS); + + if (quantization != V4L2_QUANTIZATION_FULL_RANGE || + effect != V4L2_COLORFX_NONE) { + isp3_param_clear_bits(params_vdev, ISP3X_CPROC_CTRL, + CIF_C_PROC_YOUT_FULL | + CIF_C_PROC_YIN_FULL | + CIF_C_PROC_COUT_FULL); + } else { + isp3_param_set_bits(params_vdev, ISP3X_CPROC_CTRL, + CIF_C_PROC_YOUT_FULL | + CIF_C_PROC_YIN_FULL | + CIF_C_PROC_COUT_FULL); + } +} + +static void +isp_cproc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + if (en) + isp3_param_set_bits(params_vdev, ISP3X_CPROC_CTRL, + CIF_C_PROC_CTR_ENABLE); + else + isp3_param_clear_bits(params_vdev, ISP3X_CPROC_CTRL, + CIF_C_PROC_CTR_ENABLE); +} + +static void +isp_ie_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp2x_ie_cfg *arg) +{ + u32 eff_ctrl; + + eff_ctrl = isp3_param_read(params_vdev, ISP3X_IMG_EFF_CTRL); + eff_ctrl &= ~CIF_IMG_EFF_CTRL_MODE_MASK; + + if (params_vdev->quantization == V4L2_QUANTIZATION_FULL_RANGE) + eff_ctrl |= CIF_IMG_EFF_CTRL_YCBCR_FULL; + + switch (arg->effect) { + case V4L2_COLORFX_SEPIA: + eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_SEPIA; + break; + case V4L2_COLORFX_SET_CBCR: + isp3_param_write(params_vdev, arg->eff_tint, ISP3X_IMG_EFF_TINT); + eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_SEPIA; + break; + /* + * Color selection is similar to water color(AQUA): + * grayscale + selected color w threshold + */ + case V4L2_COLORFX_AQUA: + eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_COLOR_SEL; + isp3_param_write(params_vdev, arg->color_sel, + ISP3X_IMG_EFF_COLOR_SEL); + break; + case V4L2_COLORFX_EMBOSS: + eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_EMBOSS; + isp3_param_write(params_vdev, arg->eff_mat_1, + CIF_IMG_EFF_MAT_1); + isp3_param_write(params_vdev, arg->eff_mat_2, + CIF_IMG_EFF_MAT_2); + isp3_param_write(params_vdev, arg->eff_mat_3, + CIF_IMG_EFF_MAT_3); + break; + case V4L2_COLORFX_SKETCH: + eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_SKETCH; + isp3_param_write(params_vdev, arg->eff_mat_3, + CIF_IMG_EFF_MAT_3); + isp3_param_write(params_vdev, arg->eff_mat_4, + CIF_IMG_EFF_MAT_4); + isp3_param_write(params_vdev, arg->eff_mat_5, + CIF_IMG_EFF_MAT_5); + break; + case V4L2_COLORFX_BW: + eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_BLACKWHITE; + break; + case V4L2_COLORFX_NEGATIVE: + eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_NEGATIVE; + break; + default: + break; + } + + isp3_param_write(params_vdev, eff_ctrl, ISP3X_IMG_EFF_CTRL); +} + +static void +isp_ie_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + if (en) { + isp3_param_set_bits(params_vdev, ISP3X_IMG_EFF_CTRL, + CIF_IMG_EFF_CTRL_CFG_UPD | + CIF_IMG_EFF_CTRL_ENABLE); + } else { + isp3_param_clear_bits(params_vdev, ISP3X_IMG_EFF_CTRL, + CIF_IMG_EFF_CTRL_ENABLE); + } +} + +static void +isp_rawaebig_config_foraf(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_rawaf_meas_cfg *arg) +{ + u32 block_hsize, block_vsize; + u32 addr, value; + u32 wnd_num_idx = 2; + const u32 ae_wnd_num[] = { + 1, 5, 15, 15 + }; + + addr = ISP3X_RAWAE_BIG1_BASE; + value = isp3_param_read(params_vdev, addr + ISP3X_RAWAE_BIG_CTRL); + value &= ISP3X_RAWAE_BIG_EN; + + value |= ISP3X_RAWAE_BIG_WND0_NUM(wnd_num_idx); + isp3_param_write(params_vdev, value, addr + ISP3X_RAWAE_BIG_CTRL); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->win[0].h_offs, arg->win[0].v_offs), + addr + ISP3X_RAWAE_BIG_OFFSET); + + block_hsize = arg->win[0].h_size / ae_wnd_num[wnd_num_idx]; + block_vsize = arg->win[0].v_size / ae_wnd_num[wnd_num_idx]; + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(block_hsize, block_vsize), + addr + ISP3X_RAWAE_BIG_BLK_SIZE); +} + +static void +isp_rawaf_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_rawaf_meas_cfg *arg) +{ + u32 i, var, ctrl; + u16 h_size, v_size; + u16 h_offs, v_offs; + u8 gaus_en, viir_en, v1_fir_sel; + size_t num_of_win = min_t(size_t, ARRAY_SIZE(arg->win), + arg->num_afm_win); + + for (i = 0; i < num_of_win; i++) { + h_size = arg->win[i].h_size; + v_size = arg->win[i].v_size; + h_offs = arg->win[i].h_offs < 2 ? 2 : arg->win[i].h_offs; + v_offs = arg->win[i].v_offs < 1 ? 1 : arg->win[i].v_offs; + + if (i == 0) { + h_size = h_size / 15 * 15; + v_size = v_size / 15 * 15; + } + + /* + * (horizontal left row), value must be greater or equal 2 + * (vertical top line), value must be greater or equal 1 + */ + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(v_offs, h_offs), + ISP3X_RAWAF_OFFSET_WINA + i * 8); + + /* + * value must be smaller than [width of picture -2] + * value must be lower than (number of lines -2) + */ + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(v_size, h_size), + ISP3X_RAWAF_SIZE_WINA + i * 8); + } + + var = 0; + for (i = 0; i < ISP32_RAWAF_LINE_NUM; i++) { + if (arg->line_en[i]) + var |= ISP3X_RAWAF_INTLINE0_EN << i; + var |= ISP3X_RAWAF_INELINE0(arg->line_num[i]) << 4 * i; + } + isp3_param_write(params_vdev, var, ISP3X_RAWAF_INT_LINE); + + var = isp3_param_read(params_vdev, ISP3X_RAWAF_THRES); + var &= ~0xFFFF; + var |= arg->afm_thres; + isp3_param_write(params_vdev, var, ISP3X_RAWAF_THRES); + + var = (arg->lum_var_shift[1] & 0x7) << 20 | (arg->lum_var_shift[0] & 0x7) << 16 | + (arg->afm_var_shift[1] & 0x7) << 4 | (arg->afm_var_shift[0] & 0x7); + isp3_param_write(params_vdev, var, ISP3X_RAWAF_VAR_SHIFT); + + for (i = 0; i < ISP32_RAWAF_GAMMA_NUM / 2; i++) { + var = ISP_PACK_2SHORT(arg->gamma_y[2 * i], arg->gamma_y[2 * i + 1]); + isp3_param_write(params_vdev, var, ISP3X_RAWAF_GAMMA_Y0 + i * 4); + } + var = ISP_PACK_2SHORT(arg->gamma_y[16], 0); + isp3_param_write(params_vdev, var, ISP3X_RAWAF_GAMMA_Y8); + + var = (arg->v2iir_var_shift & 0x7) << 12 | (arg->v1iir_var_shift & 0x7) << 8 | + (arg->h2iir_var_shift & 0x7) << 4 | (arg->h1iir_var_shift & 0x7); + isp3_param_write(params_vdev, var, ISP3X_RAWAF_HVIIR_VAR_SHIFT); + + var = ISP_PACK_2SHORT(arg->h_fv_thresh, arg->v_fv_thresh); + isp3_param_write(params_vdev, var, ISP3X_RAWAF_HIIR_THRESH); + + for (i = 0; i < ISP32_RAWAF_VFIR_COE_NUM; i++) { + var = ISP_PACK_2SHORT(arg->v1fir_coe[i], arg->v2fir_coe[i]); + isp3_param_write(params_vdev, var, ISP32_RAWAF_V_FIR_COE0 + i * 4); + } + + for (i = 0; i < ISP32_RAWAF_GAUS_COE_NUM / 4; i++) { + var = ISP_PACK_4BYTE(arg->gaus_coe[i * 4], arg->gaus_coe[i * 4 + 1], + arg->gaus_coe[i * 4 + 2], arg->gaus_coe[i * 4 + 3]); + isp3_param_write(params_vdev, var, ISP32_RAWAF_GAUS_COE03 + i * 4); + } + var = ISP_PACK_4BYTE(arg->gaus_coe[ISP32_RAWAF_GAUS_COE_NUM - 1], 0, 0, 0); + isp3_param_write(params_vdev, var, ISP32_RAWAF_GAUS_COE8); + + isp3_param_write(params_vdev, arg->highlit_thresh, ISP3X_RAWAF_HIGHLIT_THRESH); + + viir_en = arg->viir_en; + gaus_en = arg->gaus_en; + v1_fir_sel = arg->v1_fir_sel; + if (viir_en == 0) + v1_fir_sel = 0; + + ctrl = isp3_param_read(params_vdev, ISP3X_RAWAF_CTRL); + ctrl &= ISP3X_RAWAF_EN; + if (arg->hiir_en) { + ctrl |= ISP3X_RAWAF_HIIR_EN; + for (i = 0; i < ISP32_RAWAF_HIIR_COE_NUM / 2; i++) { + var = ISP_PACK_2SHORT(arg->h1iir1_coe[i * 2], arg->h1iir1_coe[i * 2 + 1]); + isp3_param_write(params_vdev, var, ISP3X_RAWAF_H1_IIR1_COE01 + i * 4); + var = ISP_PACK_2SHORT(arg->h1iir2_coe[i * 2], arg->h1iir2_coe[i * 2 + 1]); + isp3_param_write(params_vdev, var, ISP3X_RAWAF_H1_IIR2_COE01 + i * 4); + var = ISP_PACK_2SHORT(arg->h2iir1_coe[i * 2], arg->h2iir1_coe[i * 2 + 1]); + isp3_param_write(params_vdev, var, ISP3X_RAWAF_H2_IIR1_COE01 + i * 4); + var = ISP_PACK_2SHORT(arg->h2iir2_coe[i * 2], arg->h2iir2_coe[i * 2 + 1]); + isp3_param_write(params_vdev, var, ISP3X_RAWAF_H2_IIR2_COE01 + i * 4); + } + } + if (viir_en) { + ctrl |= ISP3X_RAWAF_VIIR_EN; + for (i = 0; i < ISP32_RAWAF_VIIR_COE_NUM; i++) { + var = ISP_PACK_2SHORT(arg->v1iir_coe[i], arg->v2iir_coe[i]); + isp3_param_write(params_vdev, var, ISP3X_RAWAF_V_IIR_COE0 + i * 4); + } + } + if (arg->ldg_en) { + ctrl |= ISP3X_RAWAF_LDG_EN; + for (i = 0; i < ISP32_RAWAF_CURVE_NUM; i++) { + isp3_param_write(params_vdev, + arg->curve_h[i].ldg_lumth | + arg->curve_h[i].ldg_gain << 8 | + arg->curve_h[i].ldg_gslp << 16, + ISP3X_RAWAF_H_CURVEL + i * 16); + isp3_param_write(params_vdev, + arg->curve_v[i].ldg_lumth | + arg->curve_v[i].ldg_gain << 8 | + arg->curve_v[i].ldg_gslp << 16, + ISP3X_RAWAF_V_CURVEL + i * 16); + } + } + + ctrl |= !!arg->ae_config_use << 20 | !!arg->from_ynr << 19 | + !!arg->from_awb << 18 | (arg->v_dnscl_mode & 0x3) << 16 | + !!arg->sobel_sel << 15 | !!arg->vldg_sel << 14 | + !!arg->y_mode << 13 | !!arg->ae_mode << 12 | + !!arg->v2_fv_mode << 11 | !!arg->v1_fv_mode << 10 | + !!arg->h2_fv_mode << 9 | !!arg->h1_fv_mode << 8 | + !!arg->accu_8bit_mode << 6 | !!v1_fir_sel << 3 | + !!gaus_en << 2 | !!arg->gamma_en << 1; + isp3_param_write(params_vdev, ctrl, ISP3X_RAWAF_CTRL); + + ctrl = isp3_param_read(params_vdev, ISP3X_VI_ISP_PATH); + ctrl &= ~(ISP3X_RAWAF_SEL(3)); + ctrl |= ISP3X_RAWAF_SEL(arg->rawaf_sel); + isp3_param_write(params_vdev, ctrl, ISP3X_VI_ISP_PATH); + + params_vdev->afaemode_en = arg->ae_mode; + if (params_vdev->afaemode_en) + isp_rawaebig_config_foraf(params_vdev, arg); +} + +static void +isp_rawaebig_enable_foraf(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + u32 exp_ctrl; + u32 addr = ISP3X_RAWAE_BIG1_BASE; + + exp_ctrl = isp3_param_read(params_vdev, addr + ISP3X_RAWAE_BIG_CTRL); + exp_ctrl &= ~ISP32_REG_WR_MASK; + if (en) + exp_ctrl |= ISP32_MODULE_EN; + else + exp_ctrl &= ~ISP32_MODULE_EN; + + isp3_param_write(params_vdev, exp_ctrl, addr + ISP3X_RAWAE_BIG_CTRL); +} + +static void +isp_rawaf_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + u32 afm_ctrl = isp3_param_read(params_vdev, ISP3X_RAWAF_CTRL); + + afm_ctrl &= ~ISP32_REG_WR_MASK; + if (en) + afm_ctrl |= ISP3X_RAWAF_EN; + else + afm_ctrl &= ~ISP3X_RAWAF_EN; + + isp3_param_write(params_vdev, afm_ctrl, ISP3X_RAWAF_CTRL); + if (params_vdev->afaemode_en) { + isp_rawaebig_enable_foraf(params_vdev, en); + if (!en) + params_vdev->afaemode_en = false; + } +} + +static void +isp_rawaelite_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp2x_rawaelite_meas_cfg *arg) +{ + struct rkisp_device *ispdev = params_vdev->dev; + struct v4l2_rect *out_crop = &ispdev->isp_sdev.out_crop; + u32 width = out_crop->width; + u32 block_hsize, block_vsize, value; + u32 wnd_num_idx = 0; + const u32 ae_wnd_num[] = {1, 5}; + + value = isp3_param_read(params_vdev, ISP3X_RAWAE_LITE_CTRL); + value &= ~(ISP3X_RAWAE_LITE_WNDNUM); + if (arg->wnd_num) { + value |= ISP3X_RAWAE_LITE_WNDNUM; + wnd_num_idx = 1; + } + value &= ~ISP32_REG_WR_MASK; + isp3_param_write(params_vdev, value, ISP3X_RAWAE_LITE_CTRL); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->win.h_offs, arg->win.v_offs), + ISP3X_RAWAE_LITE_OFFSET); + + block_hsize = arg->win.h_size / ae_wnd_num[wnd_num_idx]; + value = block_hsize * ae_wnd_num[wnd_num_idx] + arg->win.h_offs; + if (ispdev->hw_dev->is_unite) + width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL; + if (value + 1 > width) + block_hsize -= 1; + block_vsize = arg->win.v_size / ae_wnd_num[wnd_num_idx]; + value = block_vsize * ae_wnd_num[wnd_num_idx] + arg->win.v_offs; + if (value + 2 > out_crop->height) + block_vsize -= 1; + if (block_vsize % 2) + block_vsize -= 1; + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(block_hsize, block_vsize), + ISP3X_RAWAE_LITE_BLK_SIZ); + + value = isp3_param_read(params_vdev, ISP3X_VI_ISP_PATH); + value &= ~(ISP3X_RAWAE012_SEL(3)); + value |= ISP3X_RAWAE012_SEL(arg->rawae_sel); + isp3_param_write(params_vdev, value, ISP3X_VI_ISP_PATH); +} + +static void +isp_rawaelite_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + u32 exp_ctrl; + + exp_ctrl = isp3_param_read(params_vdev, ISP3X_RAWAE_LITE_CTRL); + exp_ctrl &= ~ISP32_REG_WR_MASK; + if (en) + exp_ctrl |= ISP3X_RAWAE_LITE_EN; + else + exp_ctrl &= ~ISP3X_RAWAE_LITE_EN; + + isp3_param_write(params_vdev, exp_ctrl, ISP3X_RAWAE_LITE_CTRL); +} + +static void +isp_rawaebig_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp2x_rawaebig_meas_cfg *arg, + u32 blk_no) +{ + struct rkisp_device *ispdev = params_vdev->dev; + struct v4l2_rect *out_crop = &ispdev->isp_sdev.out_crop; + u32 width = out_crop->width; + u32 block_hsize, block_vsize; + u32 addr, i, value, h_size, v_size; + u32 wnd_num_idx = 0; + const u32 ae_wnd_num[] = { + 1, 5, 15, 15 + }; + + switch (blk_no) { + case 1: + addr = ISP3X_RAWAE_BIG2_BASE; + break; + case 2: + addr = ISP3X_RAWAE_BIG3_BASE; + break; + case 0: + default: + addr = ISP3X_RAWAE_BIG1_BASE; + break; + } + + /* avoid to override the old enable value */ + value = isp3_param_read(params_vdev, addr + ISP3X_RAWAE_BIG_CTRL); + value &= ISP3X_RAWAE_BIG_EN; + + wnd_num_idx = arg->wnd_num; + value |= ISP3X_RAWAE_BIG_WND0_NUM(wnd_num_idx); + + if (arg->subwin_en[0]) + value |= ISP3X_RAWAE_BIG_WND1_EN; + if (arg->subwin_en[1]) + value |= ISP3X_RAWAE_BIG_WND2_EN; + if (arg->subwin_en[2]) + value |= ISP3X_RAWAE_BIG_WND3_EN; + if (arg->subwin_en[3]) + value |= ISP3X_RAWAE_BIG_WND4_EN; + + isp3_param_write(params_vdev, value, addr + ISP3X_RAWAE_BIG_CTRL); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->win.h_offs, arg->win.v_offs), + addr + ISP3X_RAWAE_BIG_OFFSET); + + block_hsize = arg->win.h_size / ae_wnd_num[wnd_num_idx]; + value = block_hsize * ae_wnd_num[wnd_num_idx] + arg->win.h_offs; + if (ispdev->hw_dev->is_unite) + width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL; + if (value + 1 > width) + block_hsize -= 1; + block_vsize = arg->win.v_size / ae_wnd_num[wnd_num_idx]; + value = block_vsize * ae_wnd_num[wnd_num_idx] + arg->win.v_offs; + if (value + 2 > out_crop->height) + block_vsize -= 1; + if (block_vsize % 2) + block_vsize -= 1; + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(block_hsize, block_vsize), + addr + ISP3X_RAWAE_BIG_BLK_SIZE); + + for (i = 0; i < ISP32_RAWAEBIG_SUBWIN_NUM; i++) { + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->subwin[i].h_offs, arg->subwin[i].v_offs), + addr + ISP3X_RAWAE_BIG_WND1_OFFSET + 8 * i); + + v_size = arg->subwin[i].v_size + arg->subwin[i].v_offs; + h_size = arg->subwin[i].h_size + arg->subwin[i].h_offs; + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(h_size, v_size), + addr + ISP3X_RAWAE_BIG_WND1_SIZE + 8 * i); + } + + if (blk_no == 0) { + value = isp3_param_read(params_vdev, ISP3X_VI_ISP_PATH); + value &= ~(ISP3X_RAWAE3_SEL(3)); + value |= ISP3X_RAWAE3_SEL(arg->rawae_sel); + isp3_param_write(params_vdev, value, ISP3X_VI_ISP_PATH); + } else { + value = isp3_param_read(params_vdev, ISP3X_VI_ISP_PATH); + value &= ~(ISP3X_RAWAE012_SEL(3)); + value |= ISP3X_RAWAE012_SEL(arg->rawae_sel); + isp3_param_write(params_vdev, value, ISP3X_VI_ISP_PATH); + } +} + +static void +isp_rawaebig_enable(struct rkisp_isp_params_vdev *params_vdev, + bool en, u32 blk_no) +{ + u32 exp_ctrl; + u32 addr; + + switch (blk_no) { + case 1: + addr = ISP3X_RAWAE_BIG2_BASE; + break; + case 2: + addr = ISP3X_RAWAE_BIG3_BASE; + break; + case 0: + default: + addr = ISP3X_RAWAE_BIG1_BASE; + break; + } + + exp_ctrl = isp3_param_read(params_vdev, addr + ISP3X_RAWAE_BIG_CTRL); + exp_ctrl &= ~ISP32_REG_WR_MASK; + if (en) + exp_ctrl |= ISP32_MODULE_EN; + else + exp_ctrl &= ~ISP32_MODULE_EN; + + isp3_param_write(params_vdev, exp_ctrl, addr + ISP3X_RAWAE_BIG_CTRL); +} + +static void +isp_rawae1_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp2x_rawaebig_meas_cfg *arg) +{ + isp_rawaebig_config(params_vdev, arg, 1); +} + +static void +isp_rawae1_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + isp_rawaebig_enable(params_vdev, en, 1); +} + +static void +isp_rawae2_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp2x_rawaebig_meas_cfg *arg) +{ + isp_rawaebig_config(params_vdev, arg, 2); +} + +static void +isp_rawae2_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + isp_rawaebig_enable(params_vdev, en, 2); +} + +static void +isp_rawae3_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp2x_rawaebig_meas_cfg *arg) +{ + isp_rawaebig_config(params_vdev, arg, 0); +} + +static void +isp_rawae3_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + isp_rawaebig_enable(params_vdev, en, 0); +} + +static void +isp_rawawb_cfg_sram(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_rawawb_meas_cfg *arg, bool is_check) +{ + u32 i, val = ISP32_MODULE_EN; + + if (is_check && + !(isp3_param_read(params_vdev, ISP3X_RAWAWB_CTRL) & val)) + return; + + for (i = 0; i < ISP32_RAWAWB_WEIGHT_NUM / 5; i++) { + isp3_param_write(params_vdev, + (arg->wp_blk_wei_w[5 * i] & 0x3f) | + (arg->wp_blk_wei_w[5 * i + 1] & 0x3f) << 6 | + (arg->wp_blk_wei_w[5 * i + 2] & 0x3f) << 12 | + (arg->wp_blk_wei_w[5 * i + 3] & 0x3f) << 18 | + (arg->wp_blk_wei_w[5 * i + 4] & 0x3f) << 24, + ISP3X_RAWAWB_WRAM_DATA_BASE); + } +} + +static void +isp_rawawb_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_rawawb_meas_cfg *arg) +{ + struct isp32_isp_params_cfg *params_rec = params_vdev->isp32_params; + struct isp32_rawawb_meas_cfg *arg_rec = ¶ms_rec->meas.rawawb; + u32 value; + + value = arg->in_overexposure_threshold << 16 | + !!arg->blk_with_luma_wei_en << 8 | + (arg->blk_measure_illu_idx & 0x7) << 4 | + !!arg->blk_rtdw_measure_en << 3 | + !!arg->blk_measure_xytype << 2 | + !!arg->blk_measure_mode << 1 | + !!arg->blk_measure_enable; + isp3_param_write(params_vdev, value, ISP3X_RAWAWB_BLK_CTRL); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->h_offs, arg->v_offs), + ISP3X_RAWAWB_WIN_OFFS); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->h_size, arg->v_size), + ISP3X_RAWAWB_WIN_SIZE); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->r_max, arg->g_max), + ISP3X_RAWAWB_LIMIT_RG_MAX); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->b_max, arg->y_max), + ISP3X_RAWAWB_LIMIT_BY_MAX); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->r_min, arg->g_min), + ISP3X_RAWAWB_LIMIT_RG_MIN); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->b_min, arg->y_min), + ISP3X_RAWAWB_LIMIT_BY_MIN); + + value = !!arg->wp_hist_xytype << 4 | + !!arg->wp_blk_wei_en1 << 3 | + !!arg->wp_blk_wei_en0 << 2 | + !!arg->wp_luma_wei_en1 << 1 | + !!arg->wp_luma_wei_en0; + isp3_param_write(params_vdev, value, ISP3X_RAWAWB_WEIGHT_CURVE_CTRL); + + isp3_param_write(params_vdev, + ISP_PACK_4BYTE(arg->wp_luma_weicurve_y0, + arg->wp_luma_weicurve_y1, + arg->wp_luma_weicurve_y2, + arg->wp_luma_weicurve_y3), + ISP3X_RAWAWB_YWEIGHT_CURVE_XCOOR03); + + isp3_param_write(params_vdev, + ISP_PACK_4BYTE(arg->wp_luma_weicurve_y4, + arg->wp_luma_weicurve_y5, + arg->wp_luma_weicurve_y6, + arg->wp_luma_weicurve_y7), + ISP3X_RAWAWB_YWEIGHT_CURVE_XCOOR47); + + isp3_param_write(params_vdev, + arg->wp_luma_weicurve_y8, + ISP3X_RAWAWB_YWEIGHT_CURVE_XCOOR8); + + isp3_param_write(params_vdev, + ISP_PACK_4BYTE(arg->wp_luma_weicurve_w0, + arg->wp_luma_weicurve_w1, + arg->wp_luma_weicurve_w2, + arg->wp_luma_weicurve_w3), + ISP3X_RAWAWB_YWEIGHT_CURVE_YCOOR03); + + isp3_param_write(params_vdev, + ISP_PACK_4BYTE(arg->wp_luma_weicurve_w4, + arg->wp_luma_weicurve_w5, + arg->wp_luma_weicurve_w6, + arg->wp_luma_weicurve_w7), + ISP3X_RAWAWB_YWEIGHT_CURVE_YCOOR47); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->wp_luma_weicurve_w8, + arg->pre_wbgain_inv_r), + ISP3X_RAWAWB_YWEIGHT_CURVE_YCOOR8); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->pre_wbgain_inv_g, + arg->pre_wbgain_inv_b), + ISP3X_RAWAWB_PRE_WBGAIN_INV); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->vertex0_u_0, arg->vertex0_v_0), + ISP3X_RAWAWB_UV_DETC_VERTEX0_0); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->vertex1_u_0, arg->vertex1_v_0), + ISP3X_RAWAWB_UV_DETC_VERTEX1_0); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->vertex2_u_0, arg->vertex2_v_0), + ISP3X_RAWAWB_UV_DETC_VERTEX2_0); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->vertex3_u_0, arg->vertex3_v_0), + ISP3X_RAWAWB_UV_DETC_VERTEX3_0); + + isp3_param_write(params_vdev, arg->islope01_0, + ISP3X_RAWAWB_UV_DETC_ISLOPE01_0); + + isp3_param_write(params_vdev, arg->islope12_0, + ISP3X_RAWAWB_UV_DETC_ISLOPE12_0); + + isp3_param_write(params_vdev, arg->islope23_0, + ISP3X_RAWAWB_UV_DETC_ISLOPE23_0); + + isp3_param_write(params_vdev, arg->islope30_0, + ISP3X_RAWAWB_UV_DETC_ISLOPE30_0); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->vertex0_u_1, + arg->vertex0_v_1), + ISP3X_RAWAWB_UV_DETC_VERTEX0_1); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->vertex1_u_1, + arg->vertex1_v_1), + ISP3X_RAWAWB_UV_DETC_VERTEX1_1); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->vertex2_u_1, + arg->vertex2_v_1), + ISP3X_RAWAWB_UV_DETC_VERTEX2_1); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->vertex3_u_1, + arg->vertex3_v_1), + ISP3X_RAWAWB_UV_DETC_VERTEX3_1); + + isp3_param_write(params_vdev, arg->islope01_1, + ISP3X_RAWAWB_UV_DETC_ISLOPE01_1); + + isp3_param_write(params_vdev, arg->islope12_1, + ISP3X_RAWAWB_UV_DETC_ISLOPE12_1); + + isp3_param_write(params_vdev, arg->islope23_1, + ISP3X_RAWAWB_UV_DETC_ISLOPE23_1); + + isp3_param_write(params_vdev, arg->islope30_1, + ISP3X_RAWAWB_UV_DETC_ISLOPE30_1); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->vertex0_u_2, + arg->vertex0_v_2), + ISP3X_RAWAWB_UV_DETC_VERTEX0_2); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->vertex1_u_2, + arg->vertex1_v_2), + ISP3X_RAWAWB_UV_DETC_VERTEX1_2); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->vertex2_u_2, + arg->vertex2_v_2), + ISP3X_RAWAWB_UV_DETC_VERTEX2_2); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->vertex3_u_2, + arg->vertex3_v_2), + ISP3X_RAWAWB_UV_DETC_VERTEX3_2); + + isp3_param_write(params_vdev, arg->islope01_2, + ISP3X_RAWAWB_UV_DETC_ISLOPE01_2); + + isp3_param_write(params_vdev, arg->islope12_2, + ISP3X_RAWAWB_UV_DETC_ISLOPE12_2); + + isp3_param_write(params_vdev, arg->islope23_2, + ISP3X_RAWAWB_UV_DETC_ISLOPE23_2); + + isp3_param_write(params_vdev, arg->islope30_2, + ISP3X_RAWAWB_UV_DETC_ISLOPE30_2); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->vertex0_u_3, + arg->vertex0_v_3), + ISP3X_RAWAWB_UV_DETC_VERTEX0_3); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->vertex1_u_3, + arg->vertex1_v_3), + ISP3X_RAWAWB_UV_DETC_VERTEX1_3); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->vertex2_u_3, + arg->vertex2_v_3), + ISP3X_RAWAWB_UV_DETC_VERTEX2_3); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->vertex3_u_3, + arg->vertex3_v_3), + ISP3X_RAWAWB_UV_DETC_VERTEX3_3); + + isp3_param_write(params_vdev, arg->islope01_3, + ISP3X_RAWAWB_UV_DETC_ISLOPE01_3); + + isp3_param_write(params_vdev, arg->islope12_3, + ISP3X_RAWAWB_UV_DETC_ISLOPE12_3); + + isp3_param_write(params_vdev, arg->islope23_3, + ISP3X_RAWAWB_UV_DETC_ISLOPE23_3); + + isp3_param_write(params_vdev, arg->islope30_3, + ISP3X_RAWAWB_UV_DETC_ISLOPE30_3); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->rgb2ryuvmat0_y, + arg->rgb2ryuvmat1_y), + ISP3X_RAWAWB_YUV_RGB2ROTY_0); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->rgb2ryuvmat2_y, + arg->rgb2ryuvofs_y), + ISP3X_RAWAWB_YUV_RGB2ROTY_1); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->rgb2ryuvmat0_u, + arg->rgb2ryuvmat1_u), + ISP3X_RAWAWB_YUV_RGB2ROTU_0); + + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->rgb2ryuvmat2_u, + arg->rgb2ryuvofs_u), + ISP3X_RAWAWB_YUV_RGB2ROTU_1); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->rgb2ryuvmat0_v, + arg->rgb2ryuvmat1_v), + ISP3X_RAWAWB_YUV_RGB2ROTV_0); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->rgb2ryuvmat2_v, + arg->rgb2ryuvofs_v), + ISP3X_RAWAWB_YUV_RGB2ROTV_1); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->coor_x1_ls0_y, + arg->vec_x21_ls0_y), + ISP3X_RAWAWB_YUV_X_COOR_Y_0); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->coor_x1_ls0_u, + arg->vec_x21_ls0_u), + ISP3X_RAWAWB_YUV_X_COOR_U_0); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->coor_x1_ls0_v, + arg->vec_x21_ls0_v), + ISP3X_RAWAWB_YUV_X_COOR_V_0); + + isp3_param_write(params_vdev, + ISP_PACK_4BYTE(arg->dis_x1x2_ls0, 0, + arg->rotu0_ls0, arg->rotu1_ls0), + ISP3X_RAWAWB_YUV_X1X2_DIS_0); + + isp3_param_write(params_vdev, + ISP_PACK_4BYTE(arg->rotu2_ls0, arg->rotu3_ls0, + arg->rotu4_ls0, arg->rotu5_ls0), + ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_0); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->th0_ls0, arg->th1_ls0), + ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_0); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->th2_ls0, arg->th3_ls0), + ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_0); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->th4_ls0, arg->th5_ls0), + ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_0); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->coor_x1_ls1_y, + arg->vec_x21_ls1_y), + ISP3X_RAWAWB_YUV_X_COOR_Y_1); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->coor_x1_ls1_u, + arg->vec_x21_ls1_u), + ISP3X_RAWAWB_YUV_X_COOR_U_1); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->coor_x1_ls1_v, + arg->vec_x21_ls1_v), + ISP3X_RAWAWB_YUV_X_COOR_V_1); + + isp3_param_write(params_vdev, + ISP_PACK_4BYTE(arg->dis_x1x2_ls1, 0, + arg->rotu0_ls1, arg->rotu1_ls1), + ISP3X_RAWAWB_YUV_X1X2_DIS_1); + + isp3_param_write(params_vdev, + ISP_PACK_4BYTE(arg->rotu2_ls1, arg->rotu3_ls1, + arg->rotu4_ls1, arg->rotu5_ls1), + ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_1); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->th0_ls1, arg->th1_ls1), + ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_1); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->th2_ls1, arg->th3_ls1), + ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_1); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->th4_ls1, arg->th5_ls1), + ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_1); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->coor_x1_ls2_y, arg->vec_x21_ls2_y), + ISP3X_RAWAWB_YUV_X_COOR_Y_2); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->coor_x1_ls2_u, arg->vec_x21_ls2_u), + ISP3X_RAWAWB_YUV_X_COOR_U_2); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->coor_x1_ls2_v, arg->vec_x21_ls2_v), + ISP3X_RAWAWB_YUV_X_COOR_V_2); + + isp3_param_write(params_vdev, + ISP_PACK_4BYTE(arg->dis_x1x2_ls2, 0, + arg->rotu0_ls2, arg->rotu1_ls2), + ISP3X_RAWAWB_YUV_X1X2_DIS_2); + + isp3_param_write(params_vdev, + ISP_PACK_4BYTE(arg->rotu2_ls2, arg->rotu3_ls2, + arg->rotu4_ls2, arg->rotu5_ls2), + ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_2); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->th0_ls2, arg->th1_ls2), + ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_2); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->th2_ls2, arg->th3_ls2), + ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_2); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->th4_ls2, arg->th5_ls2), + ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_2); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->coor_x1_ls3_y, + arg->vec_x21_ls3_y), + ISP3X_RAWAWB_YUV_X_COOR_Y_3); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->coor_x1_ls3_u, + arg->vec_x21_ls3_u), + ISP3X_RAWAWB_YUV_X_COOR_U_3); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->coor_x1_ls3_v, + arg->vec_x21_ls3_v), + ISP3X_RAWAWB_YUV_X_COOR_V_3); + + isp3_param_write(params_vdev, + ISP_PACK_4BYTE(arg->dis_x1x2_ls3, 0, + arg->rotu0_ls3, arg->rotu1_ls3), + ISP3X_RAWAWB_YUV_X1X2_DIS_3); + + isp3_param_write(params_vdev, + ISP_PACK_4BYTE(arg->rotu2_ls3, arg->rotu3_ls3, + arg->rotu4_ls3, arg->rotu5_ls3), + ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_3); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->th0_ls3, arg->th1_ls3), + ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_3); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->th2_ls3, arg->th3_ls3), + ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_3); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->th4_ls3, arg->th5_ls3), + ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_3); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->wt0, arg->wt1), + ISP3X_RAWAWB_RGB2XY_WT01); + + isp3_param_write(params_vdev, arg->wt2, + ISP3X_RAWAWB_RGB2XY_WT2); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->mat0_x, arg->mat0_y), + ISP3X_RAWAWB_RGB2XY_MAT0_XY); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->mat1_x, arg->mat1_y), + ISP3X_RAWAWB_RGB2XY_MAT1_XY); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->mat2_x, arg->mat2_y), + ISP3X_RAWAWB_RGB2XY_MAT2_XY); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->nor_x0_0, arg->nor_x1_0), + ISP3X_RAWAWB_XY_DETC_NOR_X_0); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->nor_y0_0, arg->nor_y1_0), + ISP3X_RAWAWB_XY_DETC_NOR_Y_0); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->big_x0_0, arg->big_x1_0), + ISP3X_RAWAWB_XY_DETC_BIG_X_0); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->big_y0_0, arg->big_y1_0), + ISP3X_RAWAWB_XY_DETC_BIG_Y_0); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->nor_x0_1, arg->nor_x1_1), + ISP3X_RAWAWB_XY_DETC_NOR_X_1); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->nor_y0_1, arg->nor_y1_1), + ISP3X_RAWAWB_XY_DETC_NOR_Y_1); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->big_x0_1, arg->big_x1_1), + ISP3X_RAWAWB_XY_DETC_BIG_X_1); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->big_y0_1, arg->big_y1_1), + ISP3X_RAWAWB_XY_DETC_BIG_Y_1); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->nor_x0_2, arg->nor_x1_2), + ISP3X_RAWAWB_XY_DETC_NOR_X_2); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->nor_y0_2, arg->nor_y1_2), + ISP3X_RAWAWB_XY_DETC_NOR_Y_2); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->big_x0_2, arg->big_x1_2), + ISP3X_RAWAWB_XY_DETC_BIG_X_2); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->big_y0_2, arg->big_y1_2), + ISP3X_RAWAWB_XY_DETC_BIG_Y_2); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->nor_x0_3, arg->nor_x1_3), + ISP3X_RAWAWB_XY_DETC_NOR_X_3); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->nor_y0_3, arg->nor_y1_3), + ISP3X_RAWAWB_XY_DETC_NOR_Y_3); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->big_x0_3, arg->big_x1_3), + ISP3X_RAWAWB_XY_DETC_BIG_X_3); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->big_y0_3, arg->big_y1_3), + ISP3X_RAWAWB_XY_DETC_BIG_Y_3); + + value = (arg->exc_wp_region0_excen & 0x3) | + !!arg->exc_wp_region0_measen << 2 | + !!arg->exc_wp_region0_domain << 3 | + (arg->exc_wp_region1_excen & 0x3) << 4 | + !!arg->exc_wp_region1_measen << 6 | + !!arg->exc_wp_region1_domain << 7 | + (arg->exc_wp_region2_excen & 0x3) << 8 | + !!arg->exc_wp_region2_measen << 10 | + !!arg->exc_wp_region2_domain << 11 | + (arg->exc_wp_region3_excen & 0x3) << 12 | + !!arg->exc_wp_region3_measen << 14 | + !!arg->exc_wp_region3_domain << 15 | + (arg->exc_wp_region4_excen & 0x3) << 16 | + !!arg->exc_wp_region4_domain << 19 | + (arg->exc_wp_region5_excen & 0x3) << 20 | + !!arg->exc_wp_region5_domain << 23 | + (arg->exc_wp_region6_excen & 0x3) << 24 | + !!arg->exc_wp_region6_domain << 27 | + !!arg->multiwindow_en << 31; + isp3_param_write(params_vdev, value, ISP3X_RAWAWB_MULTIWINDOW_EXC_CTRL); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->multiwindow0_h_offs, + arg->multiwindow0_v_offs), + ISP3X_RAWAWB_MULTIWINDOW0_OFFS); + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->multiwindow0_h_size, + arg->multiwindow0_v_size), + ISP3X_RAWAWB_MULTIWINDOW0_SIZE); + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->multiwindow1_h_offs, + arg->multiwindow1_v_offs), + ISP3X_RAWAWB_MULTIWINDOW1_OFFS); + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->multiwindow1_h_size, + arg->multiwindow1_v_size), + ISP3X_RAWAWB_MULTIWINDOW1_SIZE); + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->multiwindow2_h_offs, + arg->multiwindow2_v_offs), + ISP3X_RAWAWB_MULTIWINDOW2_OFFS); + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->multiwindow2_h_size, + arg->multiwindow2_v_size), + ISP3X_RAWAWB_MULTIWINDOW2_SIZE); + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->multiwindow3_h_offs, + arg->multiwindow3_v_offs), + ISP3X_RAWAWB_MULTIWINDOW3_OFFS); + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->multiwindow3_h_size, + arg->multiwindow3_v_size), + ISP3X_RAWAWB_MULTIWINDOW3_SIZE); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->exc_wp_region0_xu0, + arg->exc_wp_region0_xu1), + ISP3X_RAWAWB_EXC_WP_REGION0_XU); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->exc_wp_region0_yv0, + arg->exc_wp_region0_yv1), + ISP3X_RAWAWB_EXC_WP_REGION0_YV); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->exc_wp_region1_xu0, + arg->exc_wp_region1_xu1), + ISP3X_RAWAWB_EXC_WP_REGION1_XU); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->exc_wp_region1_yv0, + arg->exc_wp_region1_yv1), + ISP3X_RAWAWB_EXC_WP_REGION1_YV); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->exc_wp_region2_xu0, + arg->exc_wp_region2_xu1), + ISP3X_RAWAWB_EXC_WP_REGION2_XU); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->exc_wp_region2_yv0, + arg->exc_wp_region2_yv1), + ISP3X_RAWAWB_EXC_WP_REGION2_YV); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->exc_wp_region3_xu0, + arg->exc_wp_region3_xu1), + ISP3X_RAWAWB_EXC_WP_REGION3_XU); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->exc_wp_region3_yv0, + arg->exc_wp_region3_yv1), + ISP3X_RAWAWB_EXC_WP_REGION3_YV); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->exc_wp_region4_xu0, + arg->exc_wp_region4_xu1), + ISP3X_RAWAWB_EXC_WP_REGION4_XU); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->exc_wp_region4_yv0, + arg->exc_wp_region4_yv1), + ISP3X_RAWAWB_EXC_WP_REGION4_YV); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->exc_wp_region5_xu0, + arg->exc_wp_region5_xu1), + ISP3X_RAWAWB_EXC_WP_REGION5_XU); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->exc_wp_region5_yv0, + arg->exc_wp_region5_yv1), + ISP3X_RAWAWB_EXC_WP_REGION5_YV); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->exc_wp_region6_xu0, + arg->exc_wp_region6_xu1), + ISP3X_RAWAWB_EXC_WP_REGION6_XU); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->exc_wp_region6_yv0, + arg->exc_wp_region6_yv1), + ISP3X_RAWAWB_EXC_WP_REGION6_YV); + + isp3_param_write(params_vdev, + ISP_PACK_4BYTE(arg->exc_wp_region0_weight, + arg->exc_wp_region1_weight, + arg->exc_wp_region2_weight, + arg->exc_wp_region3_weight), + ISP32_RAWAWB_EXC_WP_WEIGHT0_3); + + isp3_param_write(params_vdev, + ISP_PACK_4BYTE(arg->exc_wp_region4_weight, + arg->exc_wp_region5_weight, + arg->exc_wp_region6_weight, 0), + ISP32_RAWAWB_EXC_WP_WEIGHT4_6); + + if (params_vdev->dev->hw_dev->is_single) + isp_rawawb_cfg_sram(params_vdev, arg, false); + else + memcpy(arg_rec->wp_blk_wei_w, arg->wp_blk_wei_w, + ISP32_RAWAWB_WEIGHT_NUM); + + /* avoid to override the old enable value */ + value = isp3_param_read(params_vdev, ISP3X_RAWAWB_CTRL); + value &= ISP32_MODULE_EN; + value |= !!arg->low12bit_val << 28 | + //!!arg->ddr_path_sel << 27 | + !!arg->yuv3d_en1 << 26 | + !!arg->xy_en1 << 25 | + !!arg->uv_en1 << 24 | + //!!(arg->ddr_path_en << 23 | + (arg->light_num & 0x7) << 20 | + !!arg->rawlsc_bypass_en << 19 | + !!arg->wind_size << 18 | + !!arg->in_overexposure_check_en << 17 | + !!arg->in_rshift_to_12bit_en << 16 | + (arg->yuv3d_ls_idx3 & 0x7) << 13 | + (arg->yuv3d_ls_idx2 & 0x7) << 10 | + (arg->yuv3d_ls_idx1 & 0x7) << 7 | + (arg->yuv3d_ls_idx0 & 0x7) << 4 | + !!arg->yuv3d_en0 << 3 | + !!arg->xy_en0 << 2 | + !!arg->uv_en0 << 1; + isp3_param_write(params_vdev, value, ISP3X_RAWAWB_CTRL); + + value = isp3_param_read(params_vdev, ISP3X_VI_ISP_PATH); + value &= ~(ISP32_DRC2AWB_SEL | ISP32_BNR2AWB_SEL | ISP3X_RAWAWB_SEL(3)); + value |= ISP3X_RAWAWB_SEL(arg->rawawb_sel) | + (arg->bnr2awb_sel & 0x1) << 26 | (arg->drc2awb_sel & 0x1) << 27; + isp3_param_write(params_vdev, value, ISP3X_VI_ISP_PATH); +} + +static void +isp_rawawb_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + u32 awb_ctrl; + + awb_ctrl = isp3_param_read(params_vdev, ISP3X_RAWAWB_CTRL); + awb_ctrl &= ~ISP32_REG_WR_MASK; + if (en) + awb_ctrl |= ISP32_MODULE_EN; + else + awb_ctrl &= ~ISP32_MODULE_EN; + + isp3_param_write(params_vdev, awb_ctrl, ISP3X_RAWAWB_CTRL); +} + +static void +isp_rawhstlite_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp2x_rawhistlite_cfg *arg) +{ + u32 i; + u32 value; + u32 hist_ctrl; + u32 block_hsize, block_vsize; + + /* avoid to override the old enable value */ + hist_ctrl = isp3_param_read(params_vdev, ISP3X_RAWHIST_LITE_CTRL); + hist_ctrl &= ISP3X_RAWHIST_EN; + hist_ctrl = hist_ctrl | + ISP3X_RAWHIST_MODE(arg->mode) | + ISP3X_RAWHIST_DATASEL(arg->data_sel) | + ISP3X_RAWHIST_WATERLINE(arg->waterline) | + ISP3X_RAWHIST_STEPSIZE(arg->stepsize); + isp3_param_write(params_vdev, hist_ctrl, ISP3X_RAWHIST_LITE_CTRL); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->win.h_offs, arg->win.v_offs), + ISP3X_RAWHIST_LITE_OFFS); + + block_hsize = arg->win.h_size / ISP32_RAWHISTLITE_ROW_NUM - 1; + block_vsize = arg->win.v_size / ISP32_RAWHISTLITE_COLUMN_NUM - 1; + block_hsize &= 0xFFFE; + block_vsize &= 0xFFFE; + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(block_hsize, block_vsize), + ISP3X_RAWHIST_LITE_SIZE); + + isp3_param_write(params_vdev, + ISP_PACK_4BYTE(arg->rcc, arg->gcc, arg->bcc, arg->off), + ISP3X_RAWHIST_LITE_RAW2Y_CC); + + for (i = 0; i < (ISP32_RAWHISTLITE_WEIGHT_REG_SIZE / 4); i++) { + value = ISP_PACK_4BYTE(arg->weight[4 * i + 0], + arg->weight[4 * i + 1], + arg->weight[4 * i + 2], + arg->weight[4 * i + 3]); + isp3_param_write(params_vdev, value, + ISP3X_RAWHIST_LITE_WEIGHT + 4 * i); + } + + value = ISP_PACK_4BYTE(arg->weight[4 * i + 0], 0, 0, 0); + isp3_param_write(params_vdev, value, + ISP3X_RAWHIST_LITE_WEIGHT + 4 * i); +} + +static void +isp_rawhstlite_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + u32 hist_ctrl; + + hist_ctrl = isp3_param_read(params_vdev, ISP3X_RAWHIST_LITE_CTRL); + hist_ctrl &= ~(ISP32_MODULE_EN | ISP32_REG_WR_MASK); + + if (en) + hist_ctrl |= ISP32_MODULE_EN; + + isp3_param_write(params_vdev, hist_ctrl, ISP3X_RAWHIST_LITE_CTRL); +} + +static void +isp_rawhstbig_cfg_sram(struct rkisp_isp_params_vdev *params_vdev, + const struct isp2x_rawhistbig_cfg *arg, + u32 blk_no, bool is_check) +{ + u32 i, j, wnd_num_idx, value; + u8 weight15x15[ISP32_RAWHISTBIG_WEIGHT_REG_SIZE]; + const u32 hist_wnd_num[] = {5, 5, 15, 15}; + u32 addr; + + switch (blk_no) { + case 1: + addr = ISP3X_RAWHIST_BIG2_BASE; + break; + case 2: + addr = ISP3X_RAWHIST_BIG3_BASE; + break; + case 0: + default: + addr = ISP3X_RAWHIST_BIG1_BASE; + break; + } + + value = ISP3X_RAWHIST_EN; + if (is_check && + !(isp3_param_read(params_vdev, addr + ISP3X_RAWHIST_BIG_CTRL) & value)) + return; + + wnd_num_idx = arg->wnd_num; + memset(weight15x15, 0, sizeof(weight15x15)); + for (i = 0; i < hist_wnd_num[wnd_num_idx]; i++) { + for (j = 0; j < hist_wnd_num[wnd_num_idx]; j++) { + weight15x15[i * ISP32_RAWHISTBIG_ROW_NUM + j] = + arg->weight[i * hist_wnd_num[wnd_num_idx] + j]; + } + } + + for (i = 0; i < (ISP32_RAWHISTBIG_WEIGHT_REG_SIZE / 5); i++) { + value = (weight15x15[5 * i + 0] & 0x3f) | + (weight15x15[5 * i + 1] & 0x3f) << 6 | + (weight15x15[5 * i + 2] & 0x3f) << 12 | + (weight15x15[5 * i + 3] & 0x3f) << 18 | + (weight15x15[5 * i + 4] & 0x3f) << 24; + isp3_param_write_direct(params_vdev, value, + addr + ISP3X_RAWHIST_BIG_WEIGHT_BASE); + } +} + +static void +isp_rawhstbig_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp2x_rawhistbig_cfg *arg, u32 blk_no) +{ + struct isp32_isp_params_cfg *params_rec = params_vdev->isp32_params; + struct rkisp_device *dev = params_vdev->dev; + struct isp2x_rawhistbig_cfg *arg_rec; + u32 hist_ctrl, block_hsize, block_vsize, wnd_num_idx; + const u32 hist_wnd_num[] = {5, 5, 15, 15}; + u32 addr; + + switch (blk_no) { + case 1: + addr = ISP3X_RAWHIST_BIG2_BASE; + arg_rec = ¶ms_rec->meas.rawhist1; + break; + case 2: + addr = ISP3X_RAWHIST_BIG3_BASE; + arg_rec = ¶ms_rec->meas.rawhist2; + break; + case 0: + default: + addr = ISP3X_RAWHIST_BIG1_BASE; + arg_rec = ¶ms_rec->meas.rawhist3; + break; + } + + wnd_num_idx = arg->wnd_num; + /* avoid to override the old enable value */ + hist_ctrl = isp3_param_read(params_vdev, addr + ISP3X_RAWHIST_BIG_CTRL); + hist_ctrl &= ISP3X_RAWHIST_EN; + hist_ctrl = hist_ctrl | + ISP3X_RAWHIST_MODE(arg->mode) | + ISP3X_RAWHIST_DATASEL(arg->data_sel) | + ISP3X_RAWHIST_WATERLINE(arg->waterline) | + ISP3X_RAWHIST_WND_NUM(arg->wnd_num) | + ISP3X_RAWHIST_STEPSIZE(arg->stepsize); + isp3_param_write(params_vdev, hist_ctrl, addr + ISP3X_RAWHIST_BIG_CTRL); + + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(arg->win.h_offs, arg->win.v_offs), + addr + ISP3X_RAWHIST_BIG_OFFS); + + block_hsize = arg->win.h_size / hist_wnd_num[wnd_num_idx] - 1; + block_vsize = arg->win.v_size / hist_wnd_num[wnd_num_idx] - 1; + block_hsize &= 0xFFFE; + block_vsize &= 0xFFFE; + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(block_hsize, block_vsize), + addr + ISP3X_RAWHIST_BIG_SIZE); + + isp3_param_write(params_vdev, + ISP_PACK_4BYTE(arg->rcc, arg->gcc, arg->bcc, arg->off), + addr + ISP3X_RAWHIST_BIG_RAW2Y_CC); + + if (dev->hw_dev->is_single) + isp_rawhstbig_cfg_sram(params_vdev, arg, blk_no, false); + else + *arg_rec = *arg; +} + +static void +isp_rawhstbig_enable(struct rkisp_isp_params_vdev *params_vdev, + bool en, u32 blk_no) +{ + u32 hist_ctrl; + u32 addr; + + switch (blk_no) { + case 1: + addr = ISP3X_RAWHIST_BIG2_BASE; + break; + case 2: + addr = ISP3X_RAWHIST_BIG3_BASE; + break; + case 0: + default: + addr = ISP3X_RAWHIST_BIG1_BASE; + break; + } + + hist_ctrl = isp3_param_read(params_vdev, addr + ISP3X_RAWHIST_BIG_CTRL); + hist_ctrl &= ~(ISP3X_RAWHIST_EN | ISP32_REG_WR_MASK); + if (en) + hist_ctrl |= ISP3X_RAWHIST_EN; + + isp3_param_write(params_vdev, hist_ctrl, addr + ISP3X_RAWHIST_BIG_CTRL); +} + +static void +isp_rawhst1_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp2x_rawhistbig_cfg *arg) +{ + isp_rawhstbig_config(params_vdev, arg, 1); +} + +static void +isp_rawhst1_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + isp_rawhstbig_enable(params_vdev, en, 1); +} + +static void +isp_rawhst2_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp2x_rawhistbig_cfg *arg) +{ + isp_rawhstbig_config(params_vdev, arg, 2); +} + +static void +isp_rawhst2_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + isp_rawhstbig_enable(params_vdev, en, 2); +} + +static void +isp_rawhst3_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp2x_rawhistbig_cfg *arg) +{ + isp_rawhstbig_config(params_vdev, arg, 0); +} + +static void +isp_rawhst3_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + isp_rawhstbig_enable(params_vdev, en, 0); +} + +static void +isp_hdrmge_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_hdrmge_cfg *arg, + enum rkisp_params_type type) +{ + u32 value; + int i; + + if (type == RKISP_PARAMS_SHD || type == RKISP_PARAMS_ALL) { + value = ISP_PACK_2SHORT(arg->gain0, arg->gain0_inv); + isp3_param_write(params_vdev, value, ISP3X_HDRMGE_GAIN0); + + value = ISP_PACK_2SHORT(arg->gain1, arg->gain1_inv); + isp3_param_write(params_vdev, value, ISP3X_HDRMGE_GAIN1); + + value = arg->gain2; + isp3_param_write(params_vdev, value, ISP3X_HDRMGE_GAIN2); + + value = isp3_param_read_cache(params_vdev, ISP3X_HDRMGE_CTRL); + if (arg->s_base) + value |= BIT(1); + else + value &= ~BIT(1); + if (arg->each_raw_en) + value |= BIT(6); + else + value &= ~BIT(6); + isp3_param_write(params_vdev, value, ISP3X_HDRMGE_CTRL); + } + + if (type == RKISP_PARAMS_IMD || type == RKISP_PARAMS_ALL) { + value = ISP_PACK_4BYTE(arg->ms_dif_0p8, arg->ms_diff_0p15, + arg->lm_dif_0p9, arg->lm_dif_0p15); + isp3_param_write(params_vdev, value, ISP3X_HDRMGE_LIGHTZ); + value = (arg->ms_scl & 0x7ff) | + (arg->ms_thd0 & 0x3ff) << 12 | + (arg->ms_thd1 & 0x3ff) << 22; + isp3_param_write(params_vdev, value, ISP3X_HDRMGE_MS_DIFF); + value = (arg->lm_scl & 0x7ff) | + (arg->lm_thd0 & 0x3ff) << 12 | + (arg->lm_thd1 & 0x3ff) << 22; + isp3_param_write(params_vdev, value, ISP3X_HDRMGE_LM_DIFF); + + for (i = 0; i < ISP32_HDRMGE_L_CURVE_NUM; i++) { + value = ISP_PACK_2SHORT(arg->curve.curve_0[i], arg->curve.curve_1[i]); + isp3_param_write(params_vdev, value, ISP3X_HDRMGE_DIFF_Y0 + 4 * i); + } + + for (i = 0; i < ISP32_HDRMGE_E_CURVE_NUM; i++) { + value = (arg->l_raw1[i] & 0x3ff) << 20 | + (arg->l_raw0[i] & 0x3ff) << 10 | + (arg->e_y[i] & 0x3ff); + isp3_param_write(params_vdev, value, ISP3X_HDRMGE_OVER_Y0 + 4 * i); + } + + value = ISP_PACK_2SHORT(arg->each_raw_gain0, arg->each_raw_gain1); + isp3_param_write(params_vdev, value, ISP32_HDRMGE_EACH_GAIN); + } +} + +static void +isp_hdrmge_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ +} + +static void +isp_hdrdrc_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_drc_cfg *arg, + enum rkisp_params_type type) +{ + u32 i, value; + + if (type == RKISP_PARAMS_IMD) + return; + + value = (arg->offset_pow2 & 0x0F) << 28 | + (arg->compres_scl & 0x1FFF) << 14 | + (arg->position & 0x03FFF); + isp3_param_write(params_vdev, value, ISP3X_DRC_CTRL1); + + value = arg->delta_scalein << 24 | + (arg->hpdetail_ratio & 0xFFF) << 12 | + (arg->lpdetail_ratio & 0xFFF); + isp3_param_write(params_vdev, value, ISP3X_DRC_LPRATIO); + + value = ISP_PACK_4BYTE(arg->bilat_wt_off, 0, arg->weipre_frame, arg->weicur_pix); + isp3_param_write(params_vdev, value, ISP3X_DRC_EXPLRATIO); + + value = (arg->force_sgm_inv0 & 0xFFFF) << 16 | + arg->motion_scl << 8 | arg->edge_scl; + isp3_param_write(params_vdev, value, ISP3X_DRC_SIGMA); + + value = ISP_PACK_2SHORT(arg->space_sgm_inv0, arg->space_sgm_inv1); + isp3_param_write(params_vdev, value, ISP3X_DRC_SPACESGM); + + value = ISP_PACK_2SHORT(arg->range_sgm_inv0, arg->range_sgm_inv1); + isp3_param_write(params_vdev, value, ISP3X_DRC_RANESGM); + + value = (arg->weig_bilat & 0x1f) | (arg->weig_maxl & 0x1f) << 8 | + (arg->bilat_soft_thd & 0x3fff) << 16; + if (arg->enable_soft_thd) + value |= BIT(31); + isp3_param_write(params_vdev, value, ISP3X_DRC_BILAT); + + for (i = 0; i < ISP32_DRC_Y_NUM / 2; i++) { + value = ISP_PACK_2SHORT(arg->gain_y[2 * i], + arg->gain_y[2 * i + 1]); + isp3_param_write(params_vdev, value, ISP3X_DRC_GAIN_Y0 + 4 * i); + } + value = ISP_PACK_2SHORT(arg->gain_y[2 * i], 0); + isp3_param_write(params_vdev, value, ISP3X_DRC_GAIN_Y0 + 4 * i); + + for (i = 0; i < ISP32_DRC_Y_NUM / 2; i++) { + value = ISP_PACK_2SHORT(arg->compres_y[2 * i], + arg->compres_y[2 * i + 1]); + isp3_param_write(params_vdev, value, ISP3X_DRC_COMPRES_Y0 + 4 * i); + } + value = ISP_PACK_2SHORT(arg->compres_y[2 * i], 0); + isp3_param_write(params_vdev, value, ISP3X_DRC_COMPRES_Y0 + 4 * i); + + for (i = 0; i < ISP32_DRC_Y_NUM / 2; i++) { + value = ISP_PACK_2SHORT(arg->scale_y[2 * i], + arg->scale_y[2 * i + 1]); + isp3_param_write(params_vdev, value, ISP3X_DRC_SCALE_Y0 + 4 * i); + } + value = ISP_PACK_2SHORT(arg->scale_y[2 * i], 0); + isp3_param_write(params_vdev, value, ISP3X_DRC_SCALE_Y0 + 4 * i); + + value = ISP_PACK_2SHORT(arg->min_ogain, arg->iir_weight); + isp3_param_write(params_vdev, value, ISP3X_DRC_IIRWG_GAIN); + + value = arg->gas_t & 0xfff; + isp3_param_write(params_vdev, value, ISP32_DRC_LUM3X2_CTRL); + + value = ISP_PACK_4BYTE(arg->gas_l0, arg->gas_l1, arg->gas_l2, arg->gas_l3); + isp3_param_write(params_vdev, value, ISP32_DRC_LUM3X2_GAS); +} + +static void +isp_hdrdrc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + u32 value; + bool real_en; + + value = isp3_param_read(params_vdev, ISP3X_DRC_CTRL0); + real_en = !!(value & ISP32_MODULE_EN); + if ((en && real_en) || (!en && !real_en)) + return; + + if (en) { + value |= ISP32_MODULE_EN; + isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL1, + ISP3X_ADRC_FST_FRAME); + } else { + value = 0; + isp3_param_clear_bits(params_vdev, ISP3X_GAIN_CTRL, BIT(12)); + } + isp3_param_write(params_vdev, value, ISP3X_DRC_CTRL0); +} + +static void +isp_gic_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp21_gic_cfg *arg) +{ + u32 value; + s32 i; + + value = (arg->regmingradthrdark2 & 0x03FF) << 20 | + (arg->regmingradthrdark1 & 0x03FF) << 10 | + (arg->regminbusythre & 0x03FF); + isp3_param_write(params_vdev, value, ISP3X_GIC_DIFF_PARA1); + + value = (arg->regdarkthre & 0x07FF) << 21 | + (arg->regmaxcorvboth & 0x03FF) << 11 | + (arg->regdarktthrehi & 0x07FF); + isp3_param_write(params_vdev, value, ISP3X_GIC_DIFF_PARA2); + + value = (arg->regkgrad2dark & 0x0F) << 28 | + (arg->regkgrad1dark & 0x0F) << 24 | + (arg->regstrengthglobal_fix & 0xFF) << 16 | + (arg->regdarkthrestep & 0x0F) << 12 | + (arg->regkgrad2 & 0x0F) << 8 | + (arg->regkgrad1 & 0x0F) << 4 | + (arg->reggbthre & 0x0F); + isp3_param_write(params_vdev, value, ISP3X_GIC_DIFF_PARA3); + + value = (arg->regmaxcorv & 0x03FF) << 20 | + (arg->regmingradthr2 & 0x03FF) << 10 | + (arg->regmingradthr1 & 0x03FF); + isp3_param_write(params_vdev, value, ISP3X_GIC_DIFF_PARA4); + + value = (arg->gr_ratio & 0x03) << 28 | + (arg->noise_scale & 0x7F) << 12 | + (arg->noise_base & 0xFFF); + isp3_param_write(params_vdev, value, ISP3X_GIC_NOISE_PARA1); + + isp3_param_write(params_vdev, arg->diff_clip, ISP3X_GIC_NOISE_PARA2); + + for (i = 0; i < ISP32_GIC_SIGMA_Y_NUM / 2; i++) { + value = ISP_PACK_2SHORT(arg->sigma_y[2 * i], arg->sigma_y[2 * i + 1]); + isp3_param_write(params_vdev, value, ISP3X_GIC_SIGMA_VALUE0 + 4 * i); + } + value = ISP_PACK_2SHORT(arg->sigma_y[2 * i], 0); + isp3_param_write(params_vdev, value, ISP3X_GIC_SIGMA_VALUE0 + 4 * i); +} + +static void +isp_gic_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + u32 value = 0; + + if (en) + value |= ISP32_MODULE_EN; + isp3_param_write(params_vdev, value, ISP3X_GIC_CONTROL); +} + +static void +isp_dhaz_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_dhaz_cfg *arg) +{ + u32 i, value, ctrl; + + ctrl = isp3_param_read(params_vdev, ISP3X_DHAZ_CTRL); + ctrl &= ISP3X_DHAZ_ENMUX; + + ctrl |= !!arg->enh_luma_en << 28 | !!arg->color_deviate_en << 27 | + !!arg->round_en << 26 | !!arg->soft_wr_en << 25 | + !!arg->enhance_en << 20 | !!arg->air_lc_en << 16 | + !!arg->hpara_en << 12 | !!arg->hist_en << 8 | + !!arg->dc_en << 4; + /* merge dual unite isp params at frame end */ + if (arg->soft_wr_en) { + for (i = 0; i < ISP32_DHAZ_HIST_WR_NUM / 3; i++) { + value = (arg->hist_wr[i * 3] & 0x3ff) | + (arg->hist_wr[i * 3 + 1] & 0x3ff) << 10 | + (arg->hist_wr[i * 3 + 2] & 0x3ff) << 20; + isp3_param_write(params_vdev, value, ISP3X_DHAZ_HIST_WR0 + i * 4); + } + value = arg->hist_wr[i * 3] & 0x3ff; + isp3_param_write(params_vdev, value, ISP3X_DHAZ_HIST_WR0 + i * 4); + } + isp3_param_write(params_vdev, ctrl, ISP3X_DHAZ_CTRL); + + value = ISP_PACK_4BYTE(arg->dc_min_th, arg->dc_max_th, + arg->yhist_th, arg->yblk_th); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP0); + + value = ISP_PACK_4BYTE(arg->bright_min, arg->bright_max, + arg->wt_max, 0); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP1); + + value = ISP_PACK_4BYTE(arg->air_min, arg->air_max, + arg->dark_th, arg->tmax_base); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP2); + + value = ISP_PACK_2SHORT(arg->tmax_off, arg->tmax_max); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP_TMAX); + + value = (arg->hist_min & 0xFFFF) << 16 | + (arg->hist_th_off & 0xFF) << 8 | + (arg->hist_k & 0x1F); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP_HIST0); + + value = ISP_PACK_2SHORT(arg->hist_scale, arg->hist_gratio); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP_HIST1); + + value = ISP_PACK_2SHORT(arg->enhance_chroma, arg->enhance_value); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_ENHANCE); + + value = (arg->iir_wt_sigma & 0x07FF) << 16 | + (arg->iir_sigma & 0xFF) << 8 | + (arg->stab_fnum & 0x1F); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_IIR0); + + value = (arg->iir_pre_wet & 0x0F) << 24 | + (arg->iir_tmax_sigma & 0x7FF) << 8 | + (arg->iir_air_sigma & 0xFF); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_IIR1); + + value = (arg->cfg_wt & 0x01FF) << 16 | + (arg->cfg_air & 0xFF) << 8 | + (arg->cfg_alpha & 0xFF); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_SOFT_CFG0); + + value = ISP_PACK_2SHORT(arg->cfg_tmax, arg->cfg_gratio); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_SOFT_CFG1); + + value = (arg->range_sima & 0x01FF) << 16 | + (arg->space_sigma_pre & 0xFF) << 8 | + (arg->space_sigma_cur & 0xFF); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_BF_SIGMA); + + value = ISP_PACK_2SHORT(arg->bf_weight, arg->dc_weitcur); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_BF_WET); + + for (i = 0; i < ISP32_DHAZ_ENH_CURVE_NUM / 2; i++) { + value = ISP_PACK_2SHORT(arg->enh_curve[2 * i], arg->enh_curve[2 * i + 1]); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_ENH_CURVE0 + 4 * i); + } + value = ISP_PACK_2SHORT(arg->enh_curve[2 * i], 0); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_ENH_CURVE0 + 4 * i); + + value = ISP_PACK_4BYTE(arg->gaus_h0, arg->gaus_h1, arg->gaus_h2, 0); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAUS); + + for (i = 0; i < ISP32_DHAZ_SIGMA_IDX_NUM / 4; i++) { + value = ISP_PACK_4BYTE(arg->sigma_idx[i * 4], arg->sigma_idx[i * 4 + 1], + arg->sigma_idx[i * 4 + 2], arg->sigma_idx[i * 4 + 3]); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAIN_IDX0 + i * 4); + } + value = ISP_PACK_4BYTE(arg->sigma_idx[i * 4], arg->sigma_idx[i * 4 + 1], + arg->sigma_idx[i * 4 + 2], 0); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAIN_IDX0 + i * 4); + + for (i = 0; i < ISP32_DHAZ_SIGMA_LUT_NUM / 2; i++) { + value = ISP_PACK_2SHORT(arg->sigma_lut[i * 2], arg->sigma_lut[i * 2 + 1]); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAIN_LUT0 + i * 4); + } + value = ISP_PACK_2SHORT(arg->sigma_lut[i * 2], 0); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAIN_LUT0 + i * 4); + + for (i = 0; i < ISP32_DHAZ_ENH_LUMA_NUM / 3; i++) { + value = (arg->enh_luma[i * 3 + 2] & 0x3ff) << 20 | + (arg->enh_luma[i * 3 + 1] & 0x3ff) << 10 | + (arg->enh_luma[i * 3] & 0x3ff); + isp3_param_write(params_vdev, value, ISP32_DHAZ_ENH_LUMA0 + i * 4); + } + value = (arg->enh_luma[i * 3 + 1] & 0x3ff) << 10 | + (arg->enh_luma[i * 3] & 0x3ff); + isp3_param_write(params_vdev, value, ISP32_DHAZ_ENH_LUMA0 + i * 4); +} + +static void +isp_dhaz_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + u32 value; + bool real_en; + + value = isp3_param_read(params_vdev, ISP3X_DHAZ_CTRL); + real_en = !!(value & ISP3X_DHAZ_ENMUX); + if ((en && real_en) || (!en && !real_en)) + return; + + if (en) { + value |= ISP32_SELF_FORCE_UPD | ISP3X_DHAZ_ENMUX; + isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL1, + ISP3X_DHAZ_FST_FRAME); + } else { + value &= ~ISP3X_DHAZ_ENMUX; + isp3_param_clear_bits(params_vdev, ISP3X_GAIN_CTRL, BIT(16)); + } + isp3_param_write(params_vdev, value, ISP3X_DHAZ_CTRL); +} + +static void +isp_3dlut_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp2x_3dlut_cfg *arg) +{ + struct rkisp_isp_params_val_v32 *priv_val; + u32 value, buf_idx, i; + u32 *data; + + priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; + buf_idx = (priv_val->buf_3dlut_idx++) % ISP32_3DLUT_BUF_NUM; + + data = (u32 *)priv_val->buf_3dlut[buf_idx].vaddr; + for (i = 0; i < arg->actual_size; i++) + data[i] = (arg->lut_b[i] & 0x3FF) | + (arg->lut_g[i] & 0xFFF) << 10 | + (arg->lut_r[i] & 0x3FF) << 22; + rkisp_prepare_buffer(params_vdev->dev, &priv_val->buf_3dlut[buf_idx]); + value = priv_val->buf_3dlut[buf_idx].dma_addr; + isp3_param_write(params_vdev, value, ISP3X_MI_LUT_3D_RD_BASE); + isp3_param_write(params_vdev, arg->actual_size, ISP3X_MI_LUT_3D_RD_WSIZE); + + value = isp3_param_read(params_vdev, ISP3X_3DLUT_CTRL); + value &= ISP3X_3DLUT_EN; + + if (value) + isp3_param_set_bits(params_vdev, ISP3X_3DLUT_UPDATE, 0x01); + + isp3_param_write(params_vdev, value, ISP3X_3DLUT_CTRL); +} + +static void +isp_3dlut_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + u32 value; + bool en_state; + + value = isp3_param_read(params_vdev, ISP3X_3DLUT_CTRL); + en_state = (value & ISP3X_3DLUT_EN) ? true : false; + + if (en == en_state) + return; + + if (en) { + isp3_param_set_bits(params_vdev, ISP3X_3DLUT_CTRL, 0x01); + isp3_param_set_bits(params_vdev, ISP3X_3DLUT_UPDATE, 0x01); + } else { + isp3_param_clear_bits(params_vdev, ISP3X_3DLUT_CTRL, 0x01); + isp3_param_clear_bits(params_vdev, ISP3X_3DLUT_UPDATE, 0x01); + isp3_param_clear_bits(params_vdev, ISP3X_GAIN_CTRL, BIT(20)); + } +} + +static void +isp_ldch_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_ldch_cfg *arg) +{ + struct rkisp_device *dev = params_vdev->dev; + struct rkisp_isp_params_val_v32 *priv_val; + struct isp2x_mesh_head *head; + int buf_idx, i; + u32 value; + + value = isp3_param_read(params_vdev, ISP3X_LDCH_STS); + value &= ISP32_MODULE_EN; + value |= !!arg->map13p3_en << 7 | + !!arg->force_map_en << 6 | + !!arg->bic_mode_en << 4 | + !!arg->sample_avr_en << 3 | + !!arg->zero_interp_en << 2 | + !!arg->frm_end_dis << 1; + isp3_param_write(params_vdev, value, ISP3X_LDCH_STS); + if (arg->bic_mode_en) { + for (i = 0; i < ISP32_LDCH_BIC_NUM / 4; i++) { + value = ISP_PACK_4BYTE(arg->bicubic[i * 4], arg->bicubic[i * 4 + 1], + arg->bicubic[i * 4 + 2], arg->bicubic[i * 4 + 3]); + isp3_param_write(params_vdev, value, ISP32_LDCH_BIC_TABLE0 + i * 4); + } + } + + priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; + for (i = 0; i < ISP32_MESH_BUF_NUM; i++) { + if (arg->buf_fd == priv_val->buf_ldch[i].dma_fd) + break; + } + if (i == ISP32_MESH_BUF_NUM) { + dev_err(dev->dev, "cannot find ldch buf fd(%d)\n", arg->buf_fd); + return; + } + + if (!priv_val->buf_ldch[i].vaddr) { + dev_err(dev->dev, "no ldch buffer allocated\n"); + return; + } + + buf_idx = priv_val->buf_ldch_idx; + head = (struct isp2x_mesh_head *)priv_val->buf_ldch[buf_idx].vaddr; + head->stat = MESH_BUF_INIT; + + buf_idx = i; + head = (struct isp2x_mesh_head *)priv_val->buf_ldch[buf_idx].vaddr; + head->stat = MESH_BUF_CHIPINUSE; + priv_val->buf_ldch_idx = buf_idx; + rkisp_prepare_buffer(dev, &priv_val->buf_ldch[buf_idx]); + value = priv_val->buf_ldch[buf_idx].dma_addr + head->data_oft; + isp3_param_write(params_vdev, value, ISP3X_MI_LUT_LDCH_RD_BASE); + isp3_param_write(params_vdev, arg->hsize, ISP3X_MI_LUT_LDCH_RD_H_WSIZE); + isp3_param_write(params_vdev, arg->vsize, ISP3X_MI_LUT_LDCH_RD_V_SIZE); +} + +static void +isp_ldch_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + struct rkisp_device *dev = params_vdev->dev; + struct rkisp_isp_params_val_v32 *priv_val; + u32 buf_idx; + + priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; + if (en) { + buf_idx = priv_val->buf_ldch_idx; + if (!priv_val->buf_ldch[buf_idx].vaddr) { + dev_err(dev->dev, "no ldch buffer allocated\n"); + return; + } + isp3_param_set_bits(params_vdev, ISP3X_LDCH_STS, 0x01); + } else { + isp3_param_clear_bits(params_vdev, ISP3X_LDCH_STS, 0x01); + } +} + +static void +isp_ynr_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_ynr_cfg *arg) +{ + u32 i, value; + + value = isp3_param_read(params_vdev, ISP3X_YNR_GLOBAL_CTRL); + value &= ISP32_MODULE_EN; + + value |= !!arg->rnr_en << 26 | + !!arg->thumb_mix_cur_en << 24 | + (arg->global_gain_alpha & 0xF) << 20 | + (arg->global_gain & 0x3FF) << 8 | + (arg->flt1x1_bypass_sel & 0x3) << 6 | + !!arg->nlm11x11_bypass << 5 | + !!arg->flt1x1_bypass << 4 | + !!arg->lgft3x3_bypass << 3 | + !!arg->lbft5x5_bypass << 2 | + !!arg->bft3x3_bypass << 1; + isp3_param_write(params_vdev, value, ISP3X_YNR_GLOBAL_CTRL); + + value = ISP_PACK_2SHORT(arg->rnr_max_r, arg->local_gainscale); + isp3_param_write(params_vdev, value, ISP3X_YNR_RNR_MAX_R); + + value = ISP_PACK_2SHORT(arg->rnr_center_coorh, arg->rnr_center_coorv); + isp3_param_write(params_vdev, value, ISP3X_YNR_RNR_CENTER_COOR); + + value = ISP_PACK_2SHORT(arg->loclagain_adj_thresh, arg->localgain_adj); + isp3_param_write(params_vdev, value, ISP3X_YNR_LOCAL_GAIN_CTRL); + + value = ISP_PACK_2SHORT(arg->low_bf_inv0, arg->low_bf_inv1); + isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL0); + + value = ISP_PACK_2SHORT(arg->low_thred_adj, arg->low_peak_supress); + isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL1); + + value = ISP_PACK_2SHORT(arg->low_edge_adj_thresh, arg->low_dist_adj); + isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL2); + + value = (arg->low_bi_weight & 0xFF) << 24 | + (arg->low_weight & 0xFF) << 16 | + (arg->low_center_weight & 0xFFFF); + isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL3); + + value = ISP_PACK_2SHORT(arg->lbf_weight_thres, arg->frame_full_size); + isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL4); + + value = (arg->low_gauss1_coeff2 & 0xFFFF) << 16 | + (arg->low_gauss1_coeff1 & 0xFF) << 8 | + (arg->low_gauss1_coeff0 & 0xFF); + isp3_param_write(params_vdev, value, ISP3X_YNR_GAUSS1_COEFF); + + value = (arg->low_gauss2_coeff2 & 0xFFFF) << 16 | + (arg->low_gauss2_coeff1 & 0xFF) << 8 | + (arg->low_gauss2_coeff0 & 0xFF); + isp3_param_write(params_vdev, value, ISP3X_YNR_GAUSS2_COEFF); + + for (i = 0; i < ISP32_YNR_XY_NUM / 2; i++) { + value = ISP_PACK_2SHORT(arg->luma_points_x[2 * i], + arg->luma_points_x[2 * i + 1]); + isp3_param_write(params_vdev, value, ISP3X_YNR_SGM_DX_0_1 + 4 * i); + } + value = ISP_PACK_2SHORT(arg->luma_points_x[2 * i], 0); + isp3_param_write(params_vdev, value, ISP3X_YNR_SGM_DX_0_1 + 4 * i); + + for (i = 0; i < ISP32_YNR_XY_NUM / 2; i++) { + value = ISP_PACK_2SHORT(arg->lsgm_y[2 * i], + arg->lsgm_y[2 * i + 1]); + isp3_param_write(params_vdev, value, ISP3X_YNR_LSGM_Y_0_1 + 4 * i); + } + value = ISP_PACK_2SHORT(arg->lsgm_y[2 * i], 0); + isp3_param_write(params_vdev, value, ISP3X_YNR_LSGM_Y_0_1 + 4 * i); + + for (i = 0; i < ISP32_YNR_XY_NUM / 4; i++) { + value = ISP_PACK_4BYTE(arg->rnr_strength3[4 * i], + arg->rnr_strength3[4 * i + 1], + arg->rnr_strength3[4 * i + 2], + arg->rnr_strength3[4 * i + 3]); + isp3_param_write(params_vdev, value, ISP3X_YNR_RNR_STRENGTH03 + 4 * i); + } + value = ISP_PACK_4BYTE(arg->rnr_strength3[4 * i], 0, 0, 0); + isp3_param_write(params_vdev, value, ISP3X_YNR_RNR_STRENGTH03 + 4 * i); + + value = (arg->nlm_hi_bf_scale & 0x3ff) << 16 | + (arg->nlm_hi_gain_alpha & 0x1f) << 11 | + (arg->nlm_min_sigma & 0x7ff); + isp3_param_write(params_vdev, value, ISP32_YNR_NLM_SIGMA_GAIN); + + value = (arg->nlm_coe[5] & 0xf) << 20 | (arg->nlm_coe[4] & 0xf) << 16 | + (arg->nlm_coe[3] & 0xf) << 12 | (arg->nlm_coe[2] & 0xf) << 8 | + (arg->nlm_coe[1] & 0xf) << 4 | (arg->nlm_coe[0] & 0xf); + isp3_param_write(params_vdev, value, ISP32_YNR_NLM_COE); + + value = (arg->nlm_center_weight & 0x3ffff) << 10 | (arg->nlm_weight_offset & 0x3ff); + isp3_param_write(params_vdev, value, ISP32_YNR_NLM_WEIGHT); + + value = arg->nlm_nr_weight & 0x7ff; + isp3_param_write(params_vdev, value, ISP32_YNR_NLM_NR_WEIGHT); +} + +static void +isp_ynr_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + u32 ynr_ctrl; + bool real_en; + + ynr_ctrl = isp3_param_read_cache(params_vdev, ISP3X_YNR_GLOBAL_CTRL); + real_en = !!(ynr_ctrl & ISP32_MODULE_EN); + if ((en && real_en) || (!en && !real_en)) + return; + + if (en) { + ynr_ctrl |= ISP32_MODULE_EN; + isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL1, + ISP3X_YNR_FST_FRAME); + } else { + ynr_ctrl &= ~ISP32_MODULE_EN; + } + + isp3_param_write(params_vdev, ynr_ctrl, ISP3X_YNR_GLOBAL_CTRL); +} + +static void +isp_cnr_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_cnr_cfg *arg) +{ + u32 i, value, ctrl, gain_ctrl; + + gain_ctrl = isp3_param_read(params_vdev, ISP3X_GAIN_CTRL); + ctrl = isp3_param_read(params_vdev, ISP3X_CNR_CTRL); + ctrl &= ISP32_MODULE_EN; + + ctrl |= !!arg->bf3x3_wgt0_sel << 8 | + (arg->thumb_mode & 0x3) << 4 | + !!arg->yuv422_mode << 2 | + !!arg->exgain_bypass << 1; + value = (arg->global_gain & 0x3ff) | + (arg->global_gain_alpha & 0xf) << 12 | + arg->gain_iso << 16; + /* gain disable, using global gain for cnr */ + if (ctrl & ISP32_MODULE_EN && !(gain_ctrl & ISP32_MODULE_EN)) { + ctrl |= BIT(1); + value &= ~ISP3X_CNR_GLOBAL_GAIN_ALPHA_MAX; + value |= BIT(15); + } + isp3_param_write(params_vdev, ctrl, ISP3X_CNR_CTRL); + isp3_param_write(params_vdev, value, ISP3X_CNR_EXGAIN); + + value = ISP_PACK_2SHORT(arg->thumb_sigma_c, arg->thumb_sigma_y); + isp3_param_write(params_vdev, value, ISP32_CNR_THUMB1); + + value = arg->thumb_bf_ratio & 0x7ff; + isp3_param_write(params_vdev, value, ISP32_CNR_THUMB_BF_RATIO); + + value = ISP_PACK_4BYTE(arg->lbf1x7_weit_d0, arg->lbf1x7_weit_d1, + arg->lbf1x7_weit_d2, arg->lbf1x7_weit_d3); + isp3_param_write(params_vdev, value, ISP32_CNR_LBF_WEITD); + + value = (arg->wgt_slope & 0x3ff) << 20 | (arg->exp_shift & 0x3f) << 12 | + arg->iir_strength << 4 | (arg->iir_uvgain & 0xf); + isp3_param_write(params_vdev, value, ISP32_CNR_IIR_PARA1); + + value = ISP_PACK_4BYTE(arg->chroma_ghost, arg->iir_uv_clip, 0, 0); + isp3_param_write(params_vdev, value, ISP32_CNR_IIR_PARA2); + + value = ISP_PACK_4BYTE(arg->gaus_coe[0], arg->gaus_coe[1], + arg->gaus_coe[2], arg->gaus_coe[3]); + isp3_param_write(params_vdev, value, ISP32_CNR_GAUS_COE1); + + value = ISP_PACK_4BYTE(arg->gaus_coe[4], arg->gaus_coe[5], 0, 0); + isp3_param_write(params_vdev, value, ISP32_CNR_GAUS_COE2); + + value = (arg->global_alpha & 0x7ff) << 20 | arg->bf_wgt_clip << 12 | + (arg->gaus_ratio & 0x7ff); + isp3_param_write(params_vdev, value, ISP32_CNR_GAUS_RATIO); + + value = arg->bf_ratio << 24 | (arg->sigma_r & 0x3fff) << 8 | + (arg->uv_gain & 0x7f); + isp3_param_write(params_vdev, value, ISP32_CNR_BF_PARA1); + + value = (arg->adj_ratio & 0x7fff) << 16 | (arg->adj_offset & 0x1ff); + isp3_param_write(params_vdev, value, ISP32_CNR_BF_PARA2); + + for (i = 0; i < ISP32_CNR_SIGMA_Y_NUM / 4; i++) { + value = ISP_PACK_4BYTE(arg->sigma_y[i * 4], arg->sigma_y[i * 4 + 1], + arg->sigma_y[i * 4 + 2], arg->sigma_y[i * 4 + 3]); + isp3_param_write(params_vdev, value, ISP32_CNR_SIGMA0 + i * 4); + } + value = arg->sigma_y[i * 4]; + isp3_param_write(params_vdev, value, ISP32_CNR_SIGMA0 + i * 4); + + value = (arg->iir_gain_alpha & 0xf) << 8 | arg->iir_global_gain; + isp3_param_write(params_vdev, value, ISP32_CNR_IIR_GLOBAL_GAIN); +} + +static void +isp_cnr_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + u32 cnr_ctrl; + bool real_en; + + cnr_ctrl = isp3_param_read_cache(params_vdev, ISP3X_CNR_CTRL); + real_en = !!(cnr_ctrl & ISP32_MODULE_EN); + if ((en && real_en) || (!en && !real_en)) + return; + + if (en) { + cnr_ctrl |= ISP32_MODULE_EN; + isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL1, + ISP3X_CNR_FST_FRAME); + } else { + cnr_ctrl &= ~ISP32_MODULE_EN; + } + + isp3_param_write(params_vdev, cnr_ctrl, ISP3X_CNR_CTRL); +} + +static void +isp_sharp_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_sharp_cfg *arg) +{ + u32 i, value; + + value = isp3_param_read(params_vdev, ISP3X_SHARP_EN); + value &= ISP32_MODULE_EN; + + value |= !!arg->bypass << 1 | + !!arg->center_mode << 2 | + !!arg->exgain_bypass << 3 | + !!arg->radius_ds_mode << 4 | + !!arg->noiseclip_mode << 5; + isp3_param_write(params_vdev, value, ISP3X_SHARP_EN); + + value = ISP_PACK_4BYTE(arg->pbf_ratio, arg->gaus_ratio, + arg->bf_ratio, arg->sharp_ratio); + isp3_param_write(params_vdev, value, ISP3X_SHARP_RATIO); + + value = (arg->luma_dx[6] & 0x0F) << 24 | + (arg->luma_dx[5] & 0x0F) << 20 | + (arg->luma_dx[4] & 0x0F) << 16 | + (arg->luma_dx[3] & 0x0F) << 12 | + (arg->luma_dx[2] & 0x0F) << 8 | + (arg->luma_dx[1] & 0x0F) << 4 | + (arg->luma_dx[0] & 0x0F); + isp3_param_write(params_vdev, value, ISP3X_SHARP_LUMA_DX); + + value = (arg->pbf_sigma_inv[2] & 0x3FF) << 20 | + (arg->pbf_sigma_inv[1] & 0x3FF) << 10 | + (arg->pbf_sigma_inv[0] & 0x3FF); + isp3_param_write(params_vdev, value, ISP3X_SHARP_PBF_SIGMA_INV_0); + + value = (arg->pbf_sigma_inv[5] & 0x3FF) << 20 | + (arg->pbf_sigma_inv[4] & 0x3FF) << 10 | + (arg->pbf_sigma_inv[3] & 0x3FF); + isp3_param_write(params_vdev, value, ISP3X_SHARP_PBF_SIGMA_INV_1); + + value = (arg->pbf_sigma_inv[7] & 0x3FF) << 10 | + (arg->pbf_sigma_inv[6] & 0x3FF); + isp3_param_write(params_vdev, value, ISP3X_SHARP_PBF_SIGMA_INV_2); + + value = (arg->bf_sigma_inv[2] & 0x3FF) << 20 | + (arg->bf_sigma_inv[1] & 0x3FF) << 10 | + (arg->bf_sigma_inv[0] & 0x3FF); + isp3_param_write(params_vdev, value, ISP3X_SHARP_BF_SIGMA_INV_0); + + value = (arg->bf_sigma_inv[5] & 0x3FF) << 20 | + (arg->bf_sigma_inv[4] & 0x3FF) << 10 | + (arg->bf_sigma_inv[3] & 0x3FF); + isp3_param_write(params_vdev, value, ISP3X_SHARP_BF_SIGMA_INV_1); + + value = (arg->bf_sigma_inv[7] & 0x3FF) << 10 | + (arg->bf_sigma_inv[6] & 0x3FF); + isp3_param_write(params_vdev, value, ISP3X_SHARP_BF_SIGMA_INV_2); + + value = (arg->bf_sigma_shift & 0x0F) << 4 | + (arg->pbf_sigma_shift & 0x0F); + isp3_param_write(params_vdev, value, ISP3X_SHARP_SIGMA_SHIFT); + + value = (arg->clip_hf[2] & 0x3FF) << 20 | + (arg->clip_hf[1] & 0x3FF) << 10 | + (arg->clip_hf[0] & 0x3FF); + isp3_param_write(params_vdev, value, ISP3X_SHARP_CLIP_HF_0); + + value = (arg->clip_hf[5] & 0x3FF) << 20 | + (arg->clip_hf[4] & 0x3FF) << 10 | + (arg->clip_hf[3] & 0x3FF); + isp3_param_write(params_vdev, value, ISP3X_SHARP_CLIP_HF_1); + + value = (arg->clip_hf[7] & 0x3FF) << 10 | + (arg->clip_hf[6] & 0x3FF); + isp3_param_write(params_vdev, value, ISP3X_SHARP_CLIP_HF_2); + + value = ISP_PACK_4BYTE(arg->pbf_coef0, arg->pbf_coef1, arg->pbf_coef2, 0); + isp3_param_write(params_vdev, value, ISP3X_SHARP_PBF_COEF); + + value = ISP_PACK_4BYTE(arg->bf_coef0, arg->bf_coef1, arg->bf_coef2, 0); + isp3_param_write(params_vdev, value, ISP3X_SHARP_BF_COEF); + + value = ISP_PACK_4BYTE(arg->gaus_coef[0], arg->gaus_coef[1], arg->gaus_coef[2], 0); + isp3_param_write(params_vdev, value, ISP3X_SHARP_GAUS_COEF0); + + value = ISP_PACK_4BYTE(arg->gaus_coef[3], arg->gaus_coef[4], arg->gaus_coef[5], 0); + isp3_param_write(params_vdev, value, ISP3X_SHARP_GAUS_COEF1); + + value = arg->local_gainscale << 24 | (arg->global_gain_alpha & 0xf) << 16 | + (arg->global_gain & 0x3ff); + isp3_param_write(params_vdev, value, ISP32_SHARP_GAIN); + + for (i = 0; i < ISP32_SHARP_GAIN_ADJ_NUM / 2; i++) { + value = ISP_PACK_2SHORT(arg->gain_adj[i * 2], arg->gain_adj[i * 2 + 1]); + isp3_param_write(params_vdev, value, ISP32_SHARP_GAIN_ADJUST0 + i * 4); + } + + value = ISP_PACK_2SHORT(arg->center_wid, arg->center_het); + isp3_param_write(params_vdev, value, ISP32_SHARP_CENTER); + + for (i = 0; i < ISP32_SHARP_STRENGTH_NUM / 4; i++) { + value = ISP_PACK_4BYTE(arg->strength[i * 4], arg->strength[i * 4 + 1], + arg->strength[i * 4 + 2], arg->strength[i * 4 + 3]); + isp3_param_write(params_vdev, value, ISP32_SHARP_GAIN_DIS_STRENGTH0 + i * 4); + } + value = ISP_PACK_4BYTE(arg->strength[i * 4], arg->strength[i * 4 + 1], 0, 0); + isp3_param_write(params_vdev, value, ISP32_SHARP_GAIN_DIS_STRENGTH0 + i * 4); + + value = (arg->noise_strength & 0x3fff) << 16 | (arg->enhance_bit & 0xf) << 12 | + (arg->noise_sigma & 0x3ff); + isp3_param_write(params_vdev, value, ISP32_SHARP_TEXTURE); +} + +static void +isp_sharp_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + u32 value; + + value = isp3_param_read_cache(params_vdev, ISP3X_SHARP_EN); + value &= ~ISP32_MODULE_EN; + + if (en) + value |= ISP32_MODULE_EN; + + isp3_param_write(params_vdev, value, ISP3X_SHARP_EN); +} + +static void +isp_baynr_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_baynr_cfg *arg) +{ + u32 i, value; + + value = isp3_param_read(params_vdev, ISP3X_BAYNR_CTRL); + value &= ISP32_MODULE_EN; + + value |= !!arg->bay3d_gain_en << 16 | + (arg->lg2_mode & 0x3) << 12 | + !!arg->gauss_en << 8 | + !!arg->log_bypass << 4; + isp3_param_write(params_vdev, value, ISP3X_BAYNR_CTRL); + + value = ISP_PACK_2SHORT(arg->dgain0, arg->dgain1); + isp3_param_write(params_vdev, value, ISP3X_BAYNR_DGAIN0); + + isp3_param_write(params_vdev, arg->dgain2, ISP3X_BAYNR_DGAIN1); + isp3_param_write(params_vdev, arg->pix_diff, ISP3X_BAYNR_PIXDIFF); + + value = ISP_PACK_2SHORT(arg->softthld, arg->diff_thld); + isp3_param_write(params_vdev, value, ISP3X_BAYNR_THLD); + + value = ISP_PACK_2SHORT(arg->reg_w1, arg->bltflt_streng); + isp3_param_write(params_vdev, value, ISP3X_BAYNR_W1_STRENG); + + for (i = 0; i < ISP32_BAYNR_XY_NUM / 2; i++) { + value = ISP_PACK_2SHORT(arg->sigma_x[2 * i], arg->sigma_x[2 * i + 1]); + isp3_param_write(params_vdev, value, ISP3X_BAYNR_SIGMAX01 + 4 * i); + } + + for (i = 0; i < ISP32_BAYNR_XY_NUM / 2; i++) { + value = ISP_PACK_2SHORT(arg->sigma_y[2 * i], arg->sigma_y[2 * i + 1]); + isp3_param_write(params_vdev, value, ISP3X_BAYNR_SIGMAY01 + 4 * i); + } + + value = (arg->weit_d2 & 0x3FF) << 20 | + (arg->weit_d1 & 0x3FF) << 10 | + (arg->weit_d0 & 0x3FF); + isp3_param_write(params_vdev, value, ISP3X_BAYNR_WRIT_D); + + value = ISP_PACK_2SHORT(arg->lg2_off, arg->lg2_lgoff); + isp3_param_write(params_vdev, value, ISP3X_BAYNR_LG_OFF); + + value = arg->dat_max & 0xfffff; + isp3_param_write(params_vdev, value, ISP3X_BAYNR_DAT_MAX); + + value = ISP_PACK_2SHORT(arg->rgain_off, arg->bgain_off); + isp3_param_write(params_vdev, value, ISP32_BAYNR_SIGOFF); + + for (i = 0; i < ISP32_BAYNR_GAIN_NUM / 4; i++) { + value = ISP_PACK_4BYTE(arg->gain_x[i * 4], arg->gain_x[i * 4 + 1], + arg->gain_x[i * 4 + 2], arg->gain_x[i * 4 + 3]); + isp3_param_write(params_vdev, value, ISP32_BAYNR_GAINX03 + i * 4); + } + + for (i = 0; i < ISP32_BAYNR_GAIN_NUM / 2; i++) { + value = ISP_PACK_2SHORT(arg->gain_y[i * 2], arg->gain_y[i * 2 + 1]); + isp3_param_write(params_vdev, value, ISP32_BAYNR_GAINY01 + i * 4); + } +} + +static void +isp_baynr_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + u32 value; + + value = isp3_param_read_cache(params_vdev, ISP3X_BAYNR_CTRL); + value &= ~ISP32_MODULE_EN; + + if (en) + value |= ISP32_MODULE_EN; + + isp3_param_write(params_vdev, value, ISP3X_BAYNR_CTRL); +} + +static void +isp_bay3d_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_bay3d_cfg *arg) +{ + struct rkisp_isp_params_val_v32 *priv_val; + u32 i, value; + + priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; + value = isp3_param_read(params_vdev, ISP3X_BAY3D_CTRL); + value &= ISP32_MODULE_EN; + + value |= !!arg->bwsaving_en << 13 | + !!arg->loswitch_protect << 12 | + !!arg->glbpk_en << 11 | + !!arg->logaus3_bypass_en << 10 | + !!arg->logaus5_bypass_en << 9 | + !!arg->lomed_bypass_en << 8 | + !!arg->hichnsplit_en << 7 | + !!arg->hiabs_possel << 6 | + !!arg->higaus_bypass_en << 5 | + !!arg->himed_bypass_en << 4 | + !!arg->lobypass_en << 3 | + !!arg->hibypass_en << 2 | + !!arg->bypass_en << 1; + isp3_param_write(params_vdev, value, ISP3X_BAY3D_CTRL); + + value = !!arg->wgtmix_opt_en << 12 | + !!arg->higaus5x5_en << 11 | + !!arg->higaus3_mode << 9 | + !!arg->curds_high_en << 8 | + !!arg->iirwr_rnd_en << 7 | + !!arg->pksig_ind_sel << 6 | + !!arg->hisig_ind_sel << 5 | + !!arg->lo4x4_en << 4 | + !!arg->lo4x8_en << 3 | + !!arg->bwopt_gain_dis << 2 | + !!arg->hichncor_en << 1 | + !!arg->hiwgt_opt_en; + if (priv_val->is_lo8x8) + value &= ~(BIT(3) | BIT(4)); + else if (!(value & (BIT(3) | BIT(4)))) + value |= BIT(3); + isp3_param_write(params_vdev, value, ISP32_BAY3D_CTRL1); + + value = ISP_PACK_2SHORT(arg->softwgt, arg->hidif_th); + isp3_param_write(params_vdev, value, ISP3X_BAY3D_KALRATIO); + + isp3_param_write(params_vdev, arg->glbpk2, ISP3X_BAY3D_GLBPK2); + + value = ISP_PACK_2SHORT(arg->wgtlmt, arg->wgtratio); + isp3_param_write(params_vdev, value, ISP3X_BAY3D_WGTLMT); + + for (i = 0; i < ISP32_BAY3D_XY_NUM / 2; i++) { + value = ISP_PACK_2SHORT(arg->sig0_x[2 * i], + arg->sig0_x[2 * i + 1]); + isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG0_X0 + 4 * i); + + value = ISP_PACK_2SHORT(arg->sig1_x[2 * i], + arg->sig1_x[2 * i + 1]); + isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG1_X0 + 4 * i); + } + + for (i = 0; i < ISP32_BAY3D_XY_NUM / 2; i++) { + value = ISP_PACK_2SHORT(arg->sig0_y[2 * i], + arg->sig0_y[2 * i + 1]); + isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG0_Y0 + 4 * i); + + value = ISP_PACK_2SHORT(arg->sig1_y[2 * i], + arg->sig1_y[2 * i + 1]); + isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG1_Y0 + 4 * i); + + value = ISP_PACK_2SHORT(arg->sig2_y[2 * i], + arg->sig2_y[2 * i + 1]); + isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG2_Y0 + 4 * i); + } + + value = ISP_PACK_2SHORT(arg->hisigrat0, arg->hisigrat1); + isp3_param_write(params_vdev, value, ISP32_BAY3D_HISIGRAT); + + value = ISP_PACK_2SHORT(arg->hisigoff0, arg->hisigoff1); + isp3_param_write(params_vdev, value, ISP32_BAY3D_HISIGOFF); + + value = ISP_PACK_2SHORT(arg->losigoff, arg->losigrat); + isp3_param_write(params_vdev, value, ISP32_BAY3D_LOSIG); + + value = ISP_PACK_2SHORT(arg->rgain_off, arg->bgain_off); + isp3_param_write(params_vdev, value, ISP32_BAY3D_SIGPK); + + value = ISP_PACK_4BYTE(arg->siggaus0, arg->siggaus1, + arg->siggaus2, arg->siggaus3); + isp3_param_write(params_vdev, value, ISP32_BAY3D_SIGGAUS); +} + +static void +isp_bay3d_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + struct rkisp_device *ispdev = params_vdev->dev; + struct rkisp_isp_params_val_v32 *priv_val; + u32 value, bay3d_ctrl; + + priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; + bay3d_ctrl = isp3_param_read_cache(params_vdev, ISP3X_BAY3D_CTRL); + if ((en && (bay3d_ctrl & ISP32_MODULE_EN)) || + (!en && !(bay3d_ctrl & ISP32_MODULE_EN))) + return; + + if (en) { + if (!priv_val->buf_3dnr_iir.mem_priv) { + dev_err(ispdev->dev, "no bay3d buffer available\n"); + return; + } + + value = isp3_param_read_cache(params_vdev, ISP32_BAY3D_CTRL1); + if (priv_val->is_lo8x8) { + if (value & (BIT(3) | BIT(4))) { + value &= ~(BIT(3) | BIT(4)); + isp3_param_write(params_vdev, value, ISP32_BAY3D_CTRL1); + } + } else if (!(value & (BIT(3) | BIT(4)))) { + value |= BIT(3); + isp3_param_write(params_vdev, value, ISP32_BAY3D_CTRL1); + } + bay3d_ctrl |= ISP32_MODULE_EN; + isp3_param_write(params_vdev, bay3d_ctrl, ISP3X_BAY3D_CTRL); + + value = ISP3X_BAY3D_IIR_WR_AUTO_UPD | ISP3X_BAY3D_CUR_WR_AUTO_UPD | + ISP3X_BAY3D_DS_WR_AUTO_UPD | ISP3X_BAY3D_IIRSELF_UPD | + ISP3X_BAY3D_CURSELF_UPD | ISP3X_BAY3D_DSSELF_UPD | + ISP3X_BAY3D_RDSELF_UPD; + isp3_param_set_bits(params_vdev, MI_WR_CTRL2, value); + + isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL1, ISP3X_RAW3D_FST_FRAME); + } else { + bay3d_ctrl &= ~ISP32_MODULE_EN; + isp3_param_write(params_vdev, bay3d_ctrl, ISP3X_BAY3D_CTRL); + isp3_param_clear_bits(params_vdev, ISP3X_GAIN_CTRL, BIT(4)); + } +} + +static void +isp_gain_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp3x_gain_cfg *arg) +{ + u32 val; + + val = arg->g0 & 0x3ffff; + isp3_param_write(params_vdev, val, ISP3X_GAIN_G0); + val = ISP_PACK_2SHORT(arg->g1, arg->g2); + isp3_param_write(params_vdev, val, ISP3X_GAIN_G1_G2); +} + +static void +isp_gain_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + struct rkisp_isp_params_val_v32 *priv_val = + (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; + u32 val = isp3_param_read_cache(params_vdev, ISP3X_LDCH_STS); + + /* gain will affect ldch, no support for ldch and gain enable */ + if (val & ISP32_MODULE_EN && en) + return; + + val = 0; + if (en) { + val |= priv_val->lut3d_en << 20 | + priv_val->dhaz_en << 16 | + priv_val->drc_en << 12 | + priv_val->lsc_en << 8 | + priv_val->bay3d_en << 4; + if (isp3_param_read(params_vdev, ISP3X_HDRMGE_CTRL) & BIT(0)) + val |= BIT(1); + if (val) + val |= ISP32_MODULE_EN; + } + isp3_param_write(params_vdev, val, ISP3X_GAIN_CTRL); +} + +static void +isp_cac_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_cac_cfg *arg) +{ + struct rkisp_device *dev = params_vdev->dev; + struct rkisp_isp_params_val_v32 *priv_val; + struct isp2x_mesh_head *head; + u32 i, val, ctrl; + + priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; + + ctrl = isp3_param_read(params_vdev, ISP3X_CAC_CTRL); + ctrl &= ISP3X_CAC_EN; + ctrl |= !!arg->bypass_en << 1 | !!arg->center_en << 3 | + (arg->clip_g_mode & 0x3) << 5 | !!arg->edge_detect_en << 7 | + !!arg->neg_clip0_en << 9; + + val = (arg->psf_sft_bit & 0xff) | + (arg->cfg_num & 0x7ff) << 8; + isp3_param_write(params_vdev, val, ISP3X_CAC_PSF_PARA); + + val = ISP_PACK_2SHORT(arg->center_width, arg->center_height); + isp3_param_write(params_vdev, val, ISP3X_CAC_STRENGTH_CENTER); + + for (i = 0; i < ISP32_CAC_STRENGTH_NUM / 2; i++) { + val = ISP_PACK_2SHORT(arg->strength[2 * i], arg->strength[2 * i + 1]); + isp3_param_write(params_vdev, val, ISP3X_CAC_STRENGTH0 + i * 4); + } + + val = (arg->flat_thed_r & 0x1f) << 8 | (arg->flat_thed_b & 0x1f); + isp3_param_write(params_vdev, val, ISP32_CAC_FLAT_THED); + + val = ISP_PACK_2SHORT(arg->offset_b, arg->offset_r); + isp3_param_write(params_vdev, val, ISP32_CAC_OFFSET); + + val = arg->expo_thed_b & 0x1fffff; + isp3_param_write(params_vdev, val, ISP32_CAC_EXPO_THED_B); + + val = arg->expo_thed_b & 0x1fffff; + isp3_param_write(params_vdev, val, ISP32_CAC_EXPO_THED_R); + + val = arg->expo_adj_b & 0xfffff; + isp3_param_write(params_vdev, val, ISP32_CAC_EXPO_ADJ_B); + + val = arg->expo_adj_r & 0xfffff; + isp3_param_write(params_vdev, val, ISP32_CAC_EXPO_ADJ_R); + + /* two buf, buf0 for no bigmode, buf1 for bigmode */ + i = 0; + if (priv_val->is_bigmode) + i = 1; + head = (struct isp2x_mesh_head *)priv_val->buf_cac[i].vaddr; + rkisp_prepare_buffer(dev, &priv_val->buf_cac[i]); + val = priv_val->buf_cac[i].dma_addr + head->data_oft; + isp3_param_write(params_vdev, val, ISP3X_MI_LUT_CAC_RD_BASE); + isp3_param_write(params_vdev, arg->hsize, ISP3X_MI_LUT_CAC_RD_H_WSIZE); + isp3_param_write(params_vdev, arg->vsize, ISP3X_MI_LUT_CAC_RD_V_SIZE); + if (ctrl & ISP3X_CAC_EN) + ctrl |= ISP3X_CAC_LUT_EN; + isp3_param_write(params_vdev, ctrl, ISP3X_CAC_CTRL); +} + +static void +isp_cac_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +{ + u32 val; + + val = isp3_param_read(params_vdev, ISP3X_CAC_CTRL); + val &= ~ISP3X_CAC_EN; + if (en) + val |= ISP3X_CAC_EN | ISP3X_CAC_LUT_EN; + isp3_param_write(params_vdev, val, ISP3X_CAC_CTRL); +} + +static void +isp_csm_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp21_csm_cfg *arg) +{ + u32 i, val, eff_ctrl, cproc_ctrl; + + for (i = 0; i < ISP32_CSM_COEFF_NUM; i++) { + if (i == 0) + val = (arg->csm_y_offset & 0x3f) << 24 | + (arg->csm_c_offset & 0xff) << 16 | + (arg->csm_coeff[i] & 0x1ff); + else + val = arg->csm_coeff[i] & 0x1ff; + isp3_param_write(params_vdev, val, ISP3X_ISP_CC_COEFF_0 + i * 4); + } + + val = CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA | CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA; + if (arg->csm_full_range) { + params_vdev->quantization = V4L2_QUANTIZATION_FULL_RANGE; + isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL0, val); + } else { + params_vdev->quantization = V4L2_QUANTIZATION_LIM_RANGE; + isp3_param_clear_bits(params_vdev, ISP3X_ISP_CTRL0, val); + } + + eff_ctrl = isp3_param_read(params_vdev, ISP3X_IMG_EFF_CTRL); + if (eff_ctrl & CIF_IMG_EFF_CTRL_ENABLE) { + if (arg->csm_full_range) + eff_ctrl |= CIF_IMG_EFF_CTRL_YCBCR_FULL; + else + eff_ctrl &= ~CIF_IMG_EFF_CTRL_YCBCR_FULL; + isp3_param_write(params_vdev, eff_ctrl, ISP3X_IMG_EFF_CTRL); + } + + cproc_ctrl = isp3_param_read(params_vdev, ISP3X_CPROC_CTRL); + if (cproc_ctrl & CIF_C_PROC_CTR_ENABLE) { + val = CIF_C_PROC_YOUT_FULL | CIF_C_PROC_YIN_FULL | CIF_C_PROC_COUT_FULL; + if (eff_ctrl & CIF_IMG_EFF_CTRL_ENABLE || !arg->csm_full_range) + cproc_ctrl &= ~val; + else + cproc_ctrl |= val; + isp3_param_write(params_vdev, cproc_ctrl, ISP3X_CPROC_CTRL); + } +} + +struct rkisp_isp_params_ops_v32 isp_params_ops_v32 = { + .dpcc_config = isp_dpcc_config, + .dpcc_enable = isp_dpcc_enable, + .bls_config = isp_bls_config, + .bls_enable = isp_bls_enable, + .sdg_config = isp_sdg_config, + .sdg_enable = isp_sdg_enable, + .lsc_config = isp_lsc_config, + .lsc_enable = isp_lsc_enable, + .awbgain_config = isp_awbgain_config, + .awbgain_enable = isp_awbgain_enable, + .debayer_config = isp_debayer_config, + .debayer_enable = isp_debayer_enable, + .ccm_config = isp_ccm_config, + .ccm_enable = isp_ccm_enable, + .goc_config = isp_goc_config, + .goc_enable = isp_goc_enable, + .csm_config = isp_csm_config, + .cproc_config = isp_cproc_config, + .cproc_enable = isp_cproc_enable, + .ie_config = isp_ie_config, + .ie_enable = isp_ie_enable, + .rawaf_config = isp_rawaf_config, + .rawaf_enable = isp_rawaf_enable, + .rawae0_config = isp_rawaelite_config, + .rawae0_enable = isp_rawaelite_enable, + .rawae1_config = isp_rawae1_config, + .rawae1_enable = isp_rawae1_enable, + .rawae2_config = isp_rawae2_config, + .rawae2_enable = isp_rawae2_enable, + .rawae3_config = isp_rawae3_config, + .rawae3_enable = isp_rawae3_enable, + .rawawb_config = isp_rawawb_config, + .rawawb_enable = isp_rawawb_enable, + .rawhst0_config = isp_rawhstlite_config, + .rawhst0_enable = isp_rawhstlite_enable, + .rawhst1_config = isp_rawhst1_config, + .rawhst1_enable = isp_rawhst1_enable, + .rawhst2_config = isp_rawhst2_config, + .rawhst2_enable = isp_rawhst2_enable, + .rawhst3_config = isp_rawhst3_config, + .rawhst3_enable = isp_rawhst3_enable, + .hdrmge_config = isp_hdrmge_config, + .hdrmge_enable = isp_hdrmge_enable, + .hdrdrc_config = isp_hdrdrc_config, + .hdrdrc_enable = isp_hdrdrc_enable, + .gic_config = isp_gic_config, + .gic_enable = isp_gic_enable, + .dhaz_config = isp_dhaz_config, + .dhaz_enable = isp_dhaz_enable, + .isp3dlut_config = isp_3dlut_config, + .isp3dlut_enable = isp_3dlut_enable, + .ldch_config = isp_ldch_config, + .ldch_enable = isp_ldch_enable, + .ynr_config = isp_ynr_config, + .ynr_enable = isp_ynr_enable, + .cnr_config = isp_cnr_config, + .cnr_enable = isp_cnr_enable, + .sharp_config = isp_sharp_config, + .sharp_enable = isp_sharp_enable, + .baynr_config = isp_baynr_config, + .baynr_enable = isp_baynr_enable, + .bay3d_config = isp_bay3d_config, + .bay3d_enable = isp_bay3d_enable, + .gain_config = isp_gain_config, + .gain_enable = isp_gain_enable, + .cac_config = isp_cac_config, + .cac_enable = isp_cac_enable, +}; + +static __maybe_unused +void __isp_isr_other_config(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_isp_params_cfg *new_params, + enum rkisp_params_type type) +{ + struct rkisp_isp_params_ops_v32 *ops = + (struct rkisp_isp_params_ops_v32 *)params_vdev->priv_ops; + u64 module_cfg_update = new_params->module_cfg_update; + + if (type == RKISP_PARAMS_SHD) { + if ((module_cfg_update & ISP32_MODULE_HDRMGE)) + ops->hdrmge_config(params_vdev, &new_params->others.hdrmge_cfg, type); + + if ((module_cfg_update & ISP32_MODULE_DRC)) + ops->hdrdrc_config(params_vdev, &new_params->others.drc_cfg, type); + return; + } + + v4l2_dbg(4, rkisp_debug, ¶ms_vdev->dev->v4l2_dev, + "%s seq:%d module_cfg_update:0x%llx\n", + __func__, new_params->frame_id, module_cfg_update); + + if (module_cfg_update & ISP32_MODULE_LSC) + ops->lsc_config(params_vdev, &new_params->others.lsc_cfg); + + if (module_cfg_update & ISP32_MODULE_DPCC) + ops->dpcc_config(params_vdev, &new_params->others.dpcc_cfg); + + if (module_cfg_update & ISP32_MODULE_BLS) + ops->bls_config(params_vdev, &new_params->others.bls_cfg); + + if (module_cfg_update & ISP32_MODULE_SDG) + ops->sdg_config(params_vdev, &new_params->others.sdg_cfg); + + if (module_cfg_update & ISP32_MODULE_AWB_GAIN) + ops->awbgain_config(params_vdev, &new_params->others.awb_gain_cfg); + + if (module_cfg_update & ISP32_MODULE_DEBAYER) + ops->debayer_config(params_vdev, &new_params->others.debayer_cfg); + + if (module_cfg_update & ISP32_MODULE_CCM) + ops->ccm_config(params_vdev, &new_params->others.ccm_cfg); + + if (module_cfg_update & ISP32_MODULE_GOC) + ops->goc_config(params_vdev, &new_params->others.gammaout_cfg); + + if (module_cfg_update & ISP32_MODULE_CSM) + ops->csm_config(params_vdev, &new_params->others.csm_cfg); + + if (module_cfg_update & ISP32_MODULE_CPROC) + ops->cproc_config(params_vdev, &new_params->others.cproc_cfg); + + if (module_cfg_update & ISP32_MODULE_IE) + ops->ie_config(params_vdev, &new_params->others.ie_cfg); + + if (module_cfg_update & ISP32_MODULE_HDRMGE) + ops->hdrmge_config(params_vdev, &new_params->others.hdrmge_cfg, type); + + if (module_cfg_update & ISP32_MODULE_DRC) + ops->hdrdrc_config(params_vdev, &new_params->others.drc_cfg, type); + + if (module_cfg_update & ISP32_MODULE_GIC) + ops->gic_config(params_vdev, &new_params->others.gic_cfg); + + if (module_cfg_update & ISP32_MODULE_DHAZ) + ops->dhaz_config(params_vdev, &new_params->others.dhaz_cfg); + + if (module_cfg_update & ISP32_MODULE_3DLUT) + ops->isp3dlut_config(params_vdev, &new_params->others.isp3dlut_cfg); + + if (module_cfg_update & ISP32_MODULE_LDCH) + ops->ldch_config(params_vdev, &new_params->others.ldch_cfg); + + if (module_cfg_update & ISP32_MODULE_YNR) + ops->ynr_config(params_vdev, &new_params->others.ynr_cfg); + + if (module_cfg_update & ISP32_MODULE_CNR) + ops->cnr_config(params_vdev, &new_params->others.cnr_cfg); + + if (module_cfg_update & ISP32_MODULE_SHARP) + ops->sharp_config(params_vdev, &new_params->others.sharp_cfg); + + if (module_cfg_update & ISP32_MODULE_BAYNR) + ops->baynr_config(params_vdev, &new_params->others.baynr_cfg); + + if (module_cfg_update & ISP32_MODULE_BAY3D) + ops->bay3d_config(params_vdev, &new_params->others.bay3d_cfg); + + if (module_cfg_update & ISP32_MODULE_CAC) + ops->cac_config(params_vdev, &new_params->others.cac_cfg); + + if (module_cfg_update & ISP32_MODULE_GAIN) + ops->gain_config(params_vdev, &new_params->others.gain_cfg); +} + +static __maybe_unused +void __isp_isr_other_en(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_isp_params_cfg *new_params, + enum rkisp_params_type type) +{ + struct rkisp_isp_params_ops_v32 *ops = + (struct rkisp_isp_params_ops_v32 *)params_vdev->priv_ops; + struct rkisp_isp_params_val_v32 *priv_val = + (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; + u64 module_en_update = new_params->module_en_update; + u64 module_ens = new_params->module_ens; + u32 gain_ctrl, cnr_ctrl, val; + + if (type == RKISP_PARAMS_SHD) + return; + + v4l2_dbg(4, rkisp_debug, ¶ms_vdev->dev->v4l2_dev, + "%s seq:%d module_en_update:0x%llx module_ens:0x%llx\n", + __func__, new_params->frame_id, module_en_update, module_ens); + + if (module_en_update & ISP32_MODULE_DPCC) + ops->dpcc_enable(params_vdev, !!(module_ens & ISP32_MODULE_DPCC)); + + if (module_en_update & ISP32_MODULE_BLS) + ops->bls_enable(params_vdev, !!(module_ens & ISP32_MODULE_BLS)); + + if (module_en_update & ISP32_MODULE_SDG) + ops->sdg_enable(params_vdev, !!(module_ens & ISP32_MODULE_SDG)); + + if (module_en_update & ISP32_MODULE_LSC) { + ops->lsc_enable(params_vdev, !!(module_ens & ISP32_MODULE_LSC)); + priv_val->lsc_en = !!(module_ens & ISP32_MODULE_LSC); + } + + if (module_en_update & ISP32_MODULE_AWB_GAIN) + ops->awbgain_enable(params_vdev, !!(module_ens & ISP32_MODULE_AWB_GAIN)); + + if (module_en_update & ISP32_MODULE_DEBAYER) + ops->debayer_enable(params_vdev, !!(module_ens & ISP32_MODULE_DEBAYER)); + + if (module_en_update & ISP32_MODULE_CCM) + ops->ccm_enable(params_vdev, !!(module_ens & ISP32_MODULE_CCM)); + + if (module_en_update & ISP32_MODULE_GOC) + ops->goc_enable(params_vdev, !!(module_ens & ISP32_MODULE_GOC)); + + if (module_en_update & ISP32_MODULE_CPROC) + ops->cproc_enable(params_vdev, !!(module_ens & ISP32_MODULE_CPROC)); + + if (module_en_update & ISP32_MODULE_IE) + ops->ie_enable(params_vdev, !!(module_ens & ISP32_MODULE_IE)); + + if (module_en_update & ISP32_MODULE_HDRMGE) { + ops->hdrmge_enable(params_vdev, !!(module_ens & ISP32_MODULE_HDRMGE)); + priv_val->mge_en = !!(module_ens & ISP32_MODULE_HDRMGE); + } + + if (module_en_update & ISP32_MODULE_DRC) { + ops->hdrdrc_enable(params_vdev, !!(module_ens & ISP32_MODULE_DRC)); + priv_val->drc_en = !!(module_ens & ISP32_MODULE_DRC); + } + + if (module_en_update & ISP32_MODULE_GIC) + ops->gic_enable(params_vdev, !!(module_ens & ISP32_MODULE_GIC)); + + if (module_en_update & ISP32_MODULE_DHAZ) { + ops->dhaz_enable(params_vdev, !!(module_ens & ISP32_MODULE_DHAZ)); + priv_val->dhaz_en = !!(module_ens & ISP32_MODULE_DHAZ); + } + + if (module_en_update & ISP32_MODULE_3DLUT) { + ops->isp3dlut_enable(params_vdev, !!(module_ens & ISP32_MODULE_3DLUT)); + priv_val->lut3d_en = !!(module_ens & ISP32_MODULE_3DLUT); + } + + if (module_en_update & ISP32_MODULE_LDCH) + ops->ldch_enable(params_vdev, !!(module_ens & ISP32_MODULE_LDCH)); + + if (module_en_update & ISP32_MODULE_YNR) + ops->ynr_enable(params_vdev, !!(module_ens & ISP32_MODULE_YNR)); + + if (module_en_update & ISP32_MODULE_CNR) + ops->cnr_enable(params_vdev, !!(module_ens & ISP32_MODULE_CNR)); + + if (module_en_update & ISP32_MODULE_SHARP) + ops->sharp_enable(params_vdev, !!(module_ens & ISP32_MODULE_SHARP)); + + if (module_en_update & ISP32_MODULE_BAYNR) + ops->baynr_enable(params_vdev, !!(module_ens & ISP32_MODULE_BAYNR)); + + if (module_en_update & ISP32_MODULE_BAY3D) { + ops->bay3d_enable(params_vdev, !!(module_ens & ISP32_MODULE_BAY3D)); + priv_val->bay3d_en = !!(module_ens & ISP32_MODULE_BAY3D); + } + + if (module_en_update & ISP32_MODULE_CAC) + ops->cac_enable(params_vdev, !!(module_ens & ISP32_MODULE_CAC)); + + if (module_en_update & ISP32_MODULE_GAIN) + ops->gain_enable(params_vdev, !!(module_ens & ISP32_MODULE_GAIN)); + + /* gain disable, using global gain for cnr */ + gain_ctrl = isp3_param_read_cache(params_vdev, ISP3X_GAIN_CTRL); + cnr_ctrl = isp3_param_read_cache(params_vdev, ISP3X_CNR_CTRL); + if (!(gain_ctrl & ISP32_MODULE_EN) && cnr_ctrl & ISP32_MODULE_EN) { + cnr_ctrl |= BIT(1); + isp3_param_write(params_vdev, cnr_ctrl, ISP3X_CNR_CTRL); + val = isp3_param_read(params_vdev, ISP3X_CNR_EXGAIN) & 0x3ff; + isp3_param_write(params_vdev, val | 0x8000, ISP3X_CNR_EXGAIN); + } +} + +static __maybe_unused +void __isp_isr_meas_config(struct rkisp_isp_params_vdev *params_vdev, + struct isp32_isp_params_cfg *new_params, + enum rkisp_params_type type) +{ + struct rkisp_isp_params_ops_v32 *ops = + (struct rkisp_isp_params_ops_v32 *)params_vdev->priv_ops; + u64 module_cfg_update = new_params->module_cfg_update; + + if (type == RKISP_PARAMS_SHD) + return; + + v4l2_dbg(4, rkisp_debug, ¶ms_vdev->dev->v4l2_dev, + "%s seq:%d module_cfg_update:0x%llx\n", + __func__, new_params->frame_id, module_cfg_update); + + if ((module_cfg_update & ISP32_MODULE_RAWAF)) + ops->rawaf_config(params_vdev, &new_params->meas.rawaf); + + if ((module_cfg_update & ISP32_MODULE_RAWAE0)) + ops->rawae0_config(params_vdev, &new_params->meas.rawae0); + + if ((module_cfg_update & ISP32_MODULE_RAWAE1)) + ops->rawae1_config(params_vdev, &new_params->meas.rawae1); + + if ((module_cfg_update & ISP32_MODULE_RAWAE2)) + ops->rawae2_config(params_vdev, &new_params->meas.rawae2); + + if ((module_cfg_update & ISP32_MODULE_RAWAE3) && !params_vdev->afaemode_en) + ops->rawae3_config(params_vdev, &new_params->meas.rawae3); + + if ((module_cfg_update & ISP32_MODULE_RAWHIST0)) + ops->rawhst0_config(params_vdev, &new_params->meas.rawhist0); + + if ((module_cfg_update & ISP32_MODULE_RAWHIST1)) + ops->rawhst1_config(params_vdev, &new_params->meas.rawhist1); + + if ((module_cfg_update & ISP32_MODULE_RAWHIST2)) + ops->rawhst2_config(params_vdev, &new_params->meas.rawhist2); + + if ((module_cfg_update & ISP32_MODULE_RAWHIST3)) + ops->rawhst3_config(params_vdev, &new_params->meas.rawhist3); + + if ((module_cfg_update & ISP32_MODULE_RAWAWB)) + ops->rawawb_config(params_vdev, &new_params->meas.rawawb); +} + +static __maybe_unused +void __isp_isr_meas_en(struct rkisp_isp_params_vdev *params_vdev, + struct isp32_isp_params_cfg *new_params, + enum rkisp_params_type type) +{ + struct rkisp_isp_params_ops_v32 *ops = + (struct rkisp_isp_params_ops_v32 *)params_vdev->priv_ops; + u64 module_en_update = new_params->module_en_update; + u64 module_ens = new_params->module_ens; + + if (type == RKISP_PARAMS_SHD) + return; + + v4l2_dbg(4, rkisp_debug, ¶ms_vdev->dev->v4l2_dev, + "%s seq:%d module_en_update:0x%llx module_ens:0x%llx\n", + __func__, new_params->frame_id, module_en_update, module_ens); + + if (module_en_update & ISP32_MODULE_RAWAF) + ops->rawaf_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWAF)); + + if (module_en_update & ISP32_MODULE_RAWAE0) + ops->rawae0_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWAE0)); + + if (module_en_update & ISP32_MODULE_RAWAE1) + ops->rawae1_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWAE1)); + + if (module_en_update & ISP32_MODULE_RAWAE2) + ops->rawae2_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWAE2)); + + if ((module_en_update & ISP32_MODULE_RAWAE3) && !params_vdev->afaemode_en) + ops->rawae3_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWAE3)); + + if (module_en_update & ISP32_MODULE_RAWHIST0) + ops->rawhst0_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWHIST0)); + + if (module_en_update & ISP32_MODULE_RAWHIST1) + ops->rawhst1_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWHIST1)); + + if (module_en_update & ISP32_MODULE_RAWHIST2) + ops->rawhst2_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWHIST2)); + + if (module_en_update & ISP32_MODULE_RAWHIST3) + ops->rawhst3_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWHIST3)); + + if (module_en_update & ISP32_MODULE_RAWAWB) + ops->rawawb_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWAWB)); +} + +static __maybe_unused +void __isp_config_hdrshd(struct rkisp_isp_params_vdev *params_vdev) +{ + struct rkisp_isp_params_ops_v32 *ops = + (struct rkisp_isp_params_ops_v32 *)params_vdev->priv_ops; + struct rkisp_isp_params_val_v32 *priv_val = + (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; + + ops->hdrmge_config(params_vdev, &priv_val->last_hdrmge, RKISP_PARAMS_SHD); + ops->hdrdrc_config(params_vdev, &priv_val->last_hdrdrc, RKISP_PARAMS_SHD); +} + +static +void rkisp_params_cfgsram_v32(struct rkisp_isp_params_vdev *params_vdev) +{ + struct isp32_isp_params_cfg *params = params_vdev->isp32_params; + + isp_lsc_matrix_cfg_sram(params_vdev, ¶ms->others.lsc_cfg, true); + isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist1, 1, true); + isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist2, 2, true); + isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist3, 0, true); + isp_rawawb_cfg_sram(params_vdev, ¶ms->meas.rawawb, true); +} + +static int +rkisp_alloc_internal_buf(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_isp_params_cfg *new_params) +{ + struct rkisp_device *dev = params_vdev->dev; + struct rkisp_isp_subdev *isp_sdev = &dev->isp_sdev; + struct rkisp_isp_params_val_v32 *priv_val; + u64 module_en_update, module_ens; + int ret, i; + + priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; + module_en_update = new_params->module_en_update; + module_ens = new_params->module_ens; + + priv_val->buf_3dlut_idx = 0; + for (i = 0; i < ISP32_3DLUT_BUF_NUM; i++) { + priv_val->buf_3dlut[i].is_need_vaddr = true; + priv_val->buf_3dlut[i].size = ISP32_3DLUT_BUF_SIZE; + ret = rkisp_alloc_buffer(dev, &priv_val->buf_3dlut[i]); + if (ret) { + dev_err(dev->dev, "alloc 3dlut buf fail:%d\n", ret); + goto err_3dlut; + } + } + + if ((module_en_update & ISP32_MODULE_BAY3D) && + (module_ens & ISP32_MODULE_BAY3D)) { + bool is_hdr = !(dev->rd_mode == HDR_NORMAL || dev->rd_mode == HDR_RDBK_FRAME1); + bool is_bwsaving = !!new_params->others.bay3d_cfg.bwsaving_en; + bool is_glbpk = !!new_params->others.bay3d_cfg.glbpk_en; + bool is_predgain = !!new_params->others.bls_cfg.isp_ob_predgain; + u32 w = ALIGN(isp_sdev->in_crop.width, 16); + u32 h = ALIGN(isp_sdev->in_crop.height, 16); + u32 val, wrap_line, wsize = w * 2; + + priv_val->is_lo8x8 = (!new_params->others.bay3d_cfg.lo4x8_en && + !new_params->others.bay3d_cfg.lo4x4_en && + w <= 1440); + if (is_bwsaving) + wsize = wsize * 3 / 4; + if (!is_glbpk) + wsize += w / 8; + val = ALIGN(wsize * h, 16); + priv_val->buf_3dnr_iir.size = val; + ret = rkisp_alloc_buffer(dev, &priv_val->buf_3dnr_iir); + if (ret) { + dev_err(dev->dev, "alloc bay3d iir buf fail:%d\n", ret); + goto err_3dnr; + } + isp3_param_write(params_vdev, val, ISP3X_MI_BAY3D_IIR_WR_SIZE); + val = priv_val->buf_3dnr_iir.dma_addr; + isp3_param_write(params_vdev, val, ISP3X_MI_BAY3D_IIR_WR_BASE); + isp3_param_write(params_vdev, val, ISP3X_MI_BAY3D_IIR_RD_BASE); + + wrap_line = priv_val->is_lo8x8 ? 76 : 36; + wsize = w * 2; + if (is_bwsaving) + wsize = wsize * 3 / 4; + if (is_hdr || is_predgain) + wsize += w / 8; + wsize = ALIGN(wsize * 2, 16); + val = ALIGN(wsize * wrap_line / 2, 16); + priv_val->buf_3dnr_cur.size = val; + ret = rkisp_alloc_buffer(dev, &priv_val->buf_3dnr_cur); + if (ret) { + rkisp_free_buffer(dev, &priv_val->buf_3dnr_iir); + dev_err(dev->dev, "alloc bay3d cur buf fail:%d\n", ret); + goto err_3dnr; + } + isp3_param_write(params_vdev, val, ISP3X_MI_BAY3D_CUR_WR_SIZE); + isp3_param_write(params_vdev, val, ISP32_MI_BAY3D_CUR_RD_SIZE); + isp3_param_write(params_vdev, wsize, ISP3X_MI_BAY3D_CUR_WR_LENGTH); + isp3_param_write(params_vdev, wsize, ISP3X_MI_BAY3D_CUR_RD_LENGTH); + val = priv_val->buf_3dnr_cur.dma_addr; + isp3_param_write(params_vdev, val, ISP3X_MI_BAY3D_CUR_WR_BASE); + isp3_param_write(params_vdev, val, ISP3X_MI_BAY3D_CUR_RD_BASE); + val = wrap_line << 16 | 28; + isp3_param_write(params_vdev, val, ISP3X_BAY3D_MI_ST); + + val = ALIGN(w * h / 8, 16); + priv_val->buf_3dnr_ds.size = val; + ret = rkisp_alloc_buffer(dev, &priv_val->buf_3dnr_ds); + if (ret) { + rkisp_free_buffer(dev, &priv_val->buf_3dnr_iir); + rkisp_free_buffer(dev, &priv_val->buf_3dnr_cur); + dev_err(dev->dev, "alloc bay3d ds buf fail:%d\n", ret); + goto err_3dnr; + } + isp3_param_write(params_vdev, val, ISP3X_MI_BAY3D_DS_WR_SIZE); + val = priv_val->buf_3dnr_ds.dma_addr; + isp3_param_write(params_vdev, val, ISP3X_MI_BAY3D_DS_WR_BASE); + isp3_param_write(params_vdev, val, ISP3X_MI_BAY3D_DS_RD_BASE); + + } + return 0; +err_3dnr: + i = ISP32_3DLUT_BUF_NUM; +err_3dlut: + for (i -= 1; i >= 0; i--) + rkisp_free_buffer(dev, &priv_val->buf_3dlut[i]); + return ret; +} + +/* Not called when the camera active, thus not isr protection. */ +static void +rkisp_params_first_cfg_v32(struct rkisp_isp_params_vdev *params_vdev) +{ + struct device *dev = params_vdev->dev->dev; + struct rkisp_isp_params_val_v32 *priv_val = + (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; + struct rkisp_hw_dev *hw = params_vdev->dev->hw_dev; + struct v4l2_rect *out_crop = ¶ms_vdev->dev->isp_sdev.out_crop; + u32 width = hw->max_in.w ? hw->max_in.w : out_crop->width; + u32 height = hw->max_in.h ? hw->max_in.h : out_crop->height; + u32 size = width * height; + u32 bigmode_max_w, bigmode_max_size; + + tasklet_enable(&priv_val->lsc_tasklet); + + if (hw->dev_link_num > 2) { + bigmode_max_w = ISP32_VIR4_AUTO_BIGMODE_WIDTH; + bigmode_max_size = ISP32_VIR4_NOBIG_OVERFLOW_SIZE; + if (width > ISP32_VIR4_MAX_WIDTH || size > ISP32_VIR4_MAX_SIZE) + dev_err(dev, "%dx%d > max:2560x1536 for %d virtual isp\n", + width, height, hw->dev_link_num); + } else if (hw->dev_link_num > 1) { + bigmode_max_w = ISP32_VIR2_AUTO_BIGMODE_WIDTH; + bigmode_max_size = ISP32_VIR2_NOBIG_OVERFLOW_SIZE; + if (width > ISP32_VIR2_MAX_WIDTH || size > ISP32_VIR2_MAX_SIZE) + dev_err(dev, "%dx%d > max:3840x2160 for %d virtual isp\n", + width, height, hw->dev_link_num); + } else { + bigmode_max_w = ISP32_AUTO_BIGMODE_WIDTH; + bigmode_max_size = ISP32_NOBIG_OVERFLOW_SIZE; + } + rkisp_alloc_internal_buf(params_vdev, params_vdev->isp32_params); + spin_lock(¶ms_vdev->config_lock); + /* override the default things */ + if (!params_vdev->isp32_params->module_cfg_update && + !params_vdev->isp32_params->module_en_update) + dev_warn(dev, "can not get first iq setting in stream on\n"); + + priv_val->bay3d_en = 0; + priv_val->dhaz_en = 0; + priv_val->drc_en = 0; + priv_val->lsc_en = 0; + priv_val->mge_en = 0; + priv_val->lut3d_en = 0; + priv_val->is_bigmode = 0; + if (width > bigmode_max_w || size > bigmode_max_size) { + priv_val->is_bigmode = true; + rkisp_set_bits(params_vdev->dev, ISP3X_ISP_CTRL1, 0, + ISP3X_BIGMODE_MANUAL | ISP3X_BIGMODE_FORCE_EN, false); + } + __isp_isr_meas_config(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL); + __isp_isr_other_config(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL); + __isp_isr_other_en(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL); + __isp_isr_meas_en(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL); + + priv_val->cur_hdrmge = params_vdev->isp32_params->others.hdrmge_cfg; + priv_val->cur_hdrdrc = params_vdev->isp32_params->others.drc_cfg; + priv_val->last_hdrmge = priv_val->cur_hdrmge; + priv_val->last_hdrdrc = priv_val->cur_hdrdrc; + spin_unlock(¶ms_vdev->config_lock); +} + +static void rkisp_save_first_param_v32(struct rkisp_isp_params_vdev *params_vdev, void *param) +{ + memcpy(params_vdev->isp32_params, param, params_vdev->vdev_fmt.fmt.meta.buffersize); +} + +static void rkisp_clear_first_param_v32(struct rkisp_isp_params_vdev *params_vdev) +{ + memset(params_vdev->isp32_params, 0, sizeof(struct isp32_isp_params_cfg)); +} + +static void rkisp_deinit_mesh_buf(struct rkisp_isp_params_vdev *params_vdev, + u64 module_id) +{ + struct rkisp_isp_params_val_v32 *priv_val; + struct rkisp_dummy_buffer *buf; + int i; + + priv_val = params_vdev->priv_val; + if (!priv_val) + return; + + switch (module_id) { + case ISP32_MODULE_CAC: + buf = priv_val->buf_cac; + break; + case ISP32_MODULE_LDCH: + default: + buf = priv_val->buf_ldch; + break; + } + + for (i = 0; i < ISP32_MESH_BUF_NUM; i++) + rkisp_free_buffer(params_vdev->dev, buf + i); +} + +static int rkisp_init_mesh_buf(struct rkisp_isp_params_vdev *params_vdev, + struct rkisp_meshbuf_size *meshsize) +{ + struct rkisp_device *ispdev = params_vdev->dev; + struct device *dev = ispdev->dev; + struct rkisp_isp_params_val_v32 *priv_val; + struct isp2x_mesh_head *mesh_head; + struct rkisp_dummy_buffer *buf; + u32 mesh_w = meshsize->meas_width; + u32 mesh_h = meshsize->meas_height; + u32 mesh_size, buf_size; + int i, ret; + + priv_val = params_vdev->priv_val; + if (!priv_val) { + dev_err(dev, "priv_val is NULL\n"); + return -EINVAL; + } + + switch (meshsize->module_id) { + case ISP32_MODULE_CAC: + priv_val->buf_cac_idx = 0; + buf = priv_val->buf_cac; + mesh_w = (mesh_w + 62) / 64 * 9; + mesh_h = (mesh_h + 62) / 64 * 2; + mesh_size = mesh_w * 4 * mesh_h; + break; + case ISP32_MODULE_LDCH: + default: + priv_val->buf_ldch_idx = 0; + buf = priv_val->buf_ldch; + mesh_w = ((mesh_w + 15) / 16 + 2) / 2; + mesh_h = (mesh_h + 7) / 8 + 1; + mesh_size = mesh_w * 4 * mesh_h; + break; + } + + buf_size = PAGE_ALIGN(mesh_size + ALIGN(sizeof(struct isp2x_mesh_head), 16)); + for (i = 0; i < ISP32_MESH_BUF_NUM; i++) { + buf->is_need_vaddr = true; + buf->is_need_dbuf = true; + buf->is_need_dmafd = true; + buf->size = buf_size; + ret = rkisp_alloc_buffer(params_vdev->dev, buf); + if (ret) { + dev_err(dev, "%s failed\n", __func__); + goto err; + } + + mesh_head = (struct isp2x_mesh_head *)buf->vaddr; + mesh_head->stat = MESH_BUF_INIT; + mesh_head->data_oft = ALIGN(sizeof(struct isp2x_mesh_head), 16); + buf++; + } + + return 0; +err: + rkisp_deinit_mesh_buf(params_vdev, meshsize->module_id); + return -ENOMEM; +} + +static void +rkisp_get_param_size_v32(struct rkisp_isp_params_vdev *params_vdev, + unsigned int sizes[]) +{ + sizes[0] = sizeof(struct isp32_isp_params_cfg); +} + +static void +rkisp_params_get_meshbuf_inf_v32(struct rkisp_isp_params_vdev *params_vdev, + void *meshbuf_inf) +{ + struct rkisp_isp_params_val_v32 *priv_val; + struct rkisp_meshbuf_info *meshbuf = meshbuf_inf; + struct rkisp_dummy_buffer *buf; + int i; + + priv_val = params_vdev->priv_val; + switch (meshbuf->module_id) { + case ISP32_MODULE_CAC: + priv_val->buf_cac_idx = 0; + buf = priv_val->buf_cac; + break; + case ISP32_MODULE_LDCH: + default: + priv_val->buf_ldch_idx = 0; + buf = priv_val->buf_ldch; + break; + } + + for (i = 0; i < ISP32_MESH_BUF_NUM; i++) { + if (!buf->mem_priv) { + meshbuf->buf_fd[i] = -1; + meshbuf->buf_size[i] = 0; + } else { + meshbuf->buf_fd[i] = buf->dma_fd; + meshbuf->buf_size[i] = buf->size; + } + buf++; + } +} + +static void +rkisp_params_set_meshbuf_size_v32(struct rkisp_isp_params_vdev *params_vdev, + void *size) +{ + struct rkisp_meshbuf_size *meshsize = size; + + rkisp_deinit_mesh_buf(params_vdev, meshsize->module_id); + rkisp_init_mesh_buf(params_vdev, meshsize); +} + +static void +rkisp_params_stream_stop_v32(struct rkisp_isp_params_vdev *params_vdev) +{ + struct rkisp_device *ispdev = params_vdev->dev; + struct rkisp_isp_params_val_v32 *priv_val; + int i; + + priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; + tasklet_disable(&priv_val->lsc_tasklet); + rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_iir); + rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_cur); + rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_ds); + for (i = 0; i < ISP32_3DLUT_BUF_NUM; i++) + rkisp_free_buffer(ispdev, &priv_val->buf_3dlut[i]); + for (i = 0; i < RKISP_STATS_DDR_BUF_NUM; i++) + rkisp_free_buffer(ispdev, &ispdev->stats_vdev.stats_buf[i]); +} + +static void +rkisp_params_fop_release_v32(struct rkisp_isp_params_vdev *params_vdev) +{ + rkisp_deinit_mesh_buf(params_vdev, ISP32_MODULE_LDCH); + rkisp_deinit_mesh_buf(params_vdev, ISP32_MODULE_CAC); +} + +/* Not called when the camera active, thus not isr protection. */ +static void +rkisp_params_disable_isp_v32(struct rkisp_isp_params_vdev *params_vdev) +{ + params_vdev->isp32_params->module_ens = 0; + params_vdev->isp32_params->module_en_update = 0x7ffffffffff; + + __isp_isr_other_en(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL); + __isp_isr_meas_en(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL); +} + +static void +module_data_abandon(struct rkisp_isp_params_vdev *params_vdev, + struct isp32_isp_params_cfg *params) +{ + struct rkisp_isp_params_val_v32 *priv_val; + struct isp2x_mesh_head *mesh_head; + int i; + + priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; + if (params->module_cfg_update & ISP32_MODULE_LDCH) { + const struct isp32_ldch_cfg *arg = ¶ms->others.ldch_cfg; + + for (i = 0; i < ISP32_MESH_BUF_NUM; i++) { + if (arg->buf_fd == priv_val->buf_ldch[i].dma_fd && + priv_val->buf_ldch[i].vaddr) { + mesh_head = (struct isp2x_mesh_head *)priv_val->buf_ldch[i].vaddr; + mesh_head->stat = MESH_BUF_CHIPINUSE; + break; + } + } + } + + if (params->module_cfg_update & ISP32_MODULE_CAC) { + const struct isp32_cac_cfg *arg = ¶ms->others.cac_cfg; + + for (i = 0; i < ISP32_MESH_BUF_NUM; i++) { + if (arg->buf_fd == priv_val->buf_cac[i].dma_fd && + priv_val->buf_cac[i].vaddr) { + mesh_head = (struct isp2x_mesh_head *)priv_val->buf_cac[i].vaddr; + mesh_head->stat = MESH_BUF_CHIPINUSE; + break; + } + } + } +} + +static void +rkisp_params_cfg_v32(struct rkisp_isp_params_vdev *params_vdev, + u32 frame_id, enum rkisp_params_type type) +{ + struct isp32_isp_params_cfg *new_params = NULL; + struct rkisp_buffer *cur_buf = params_vdev->cur_buf; + struct rkisp_device *dev = params_vdev->dev; + struct rkisp_hw_dev *hw_dev = dev->hw_dev; + + spin_lock(¶ms_vdev->config_lock); + if (!params_vdev->streamon) + goto unlock; + + /* get buffer by frame_id */ + while (!list_empty(¶ms_vdev->params) && !cur_buf) { + cur_buf = list_first_entry(¶ms_vdev->params, + struct rkisp_buffer, queue); + + new_params = (struct isp32_isp_params_cfg *)(cur_buf->vaddr[0]); + if (new_params->frame_id < frame_id) { + list_del(&cur_buf->queue); + if (list_empty(¶ms_vdev->params)) + break; + else if (new_params->module_en_update) { + /* update en immediately */ + __isp_isr_other_en(params_vdev, new_params, type); + __isp_isr_meas_en(params_vdev, new_params, type); + } + if (new_params->module_cfg_update & + (ISP32_MODULE_LDCH | ISP32_MODULE_CAC)) { + module_data_abandon(params_vdev, new_params); + } + vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); + cur_buf = NULL; + continue; + } else if (new_params->frame_id == frame_id) { + list_del(&cur_buf->queue); + } else { + cur_buf = NULL; + } + break; + } + + if (!cur_buf) + goto unlock; + + new_params = (struct isp32_isp_params_cfg *)(cur_buf->vaddr[0]); + __isp_isr_meas_config(params_vdev, new_params, type); + __isp_isr_other_config(params_vdev, new_params, type); + __isp_isr_other_en(params_vdev, new_params, type); + __isp_isr_meas_en(params_vdev, new_params, type); + if (!hw_dev->is_single && type != RKISP_PARAMS_SHD) + __isp_config_hdrshd(params_vdev); + + if (type != RKISP_PARAMS_IMD) { + struct rkisp_isp_params_val_v32 *priv_val = + (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; + + priv_val->last_hdrmge = priv_val->cur_hdrmge; + priv_val->last_hdrdrc = priv_val->cur_hdrdrc; + priv_val->cur_hdrmge = new_params->others.hdrmge_cfg; + priv_val->cur_hdrdrc = new_params->others.drc_cfg; + vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); + cur_buf = NULL; + } + +unlock: + params_vdev->cur_buf = cur_buf; + spin_unlock(¶ms_vdev->config_lock); +} + +static void +rkisp_params_clear_fstflg(struct rkisp_isp_params_vdev *params_vdev) +{ + u32 value = isp3_param_read(params_vdev, ISP3X_ISP_CTRL1); + + value &= (ISP3X_YNR_FST_FRAME | ISP3X_ADRC_FST_FRAME | + ISP3X_DHAZ_FST_FRAME | ISP3X_CNR_FST_FRAME | + ISP3X_RAW3D_FST_FRAME); + if (value) + isp3_param_clear_bits(params_vdev, ISP3X_ISP_CTRL1, value); +} + +static void +rkisp_params_isr_v32(struct rkisp_isp_params_vdev *params_vdev, + u32 isp_mis) +{ + struct rkisp_device *dev = params_vdev->dev; + u32 cur_frame_id; + + rkisp_dmarx_get_frame(dev, &cur_frame_id, NULL, NULL, true); + if (isp_mis & CIF_ISP_V_START) { + if (params_vdev->rdbk_times) + params_vdev->rdbk_times--; + if (!params_vdev->cur_buf) + return; + + if (IS_HDR_RDBK(dev->rd_mode) && !params_vdev->rdbk_times) { + rkisp_params_cfg_v32(params_vdev, cur_frame_id, RKISP_PARAMS_SHD); + return; + } + } + + if (isp_mis & CIF_ISP_FRAME) + rkisp_params_clear_fstflg(params_vdev); + + if ((isp_mis & CIF_ISP_FRAME) && !IS_HDR_RDBK(dev->rd_mode)) + rkisp_params_cfg_v32(params_vdev, cur_frame_id + 1, RKISP_PARAMS_ALL); +} + +static struct rkisp_isp_params_ops rkisp_isp_params_ops_tbl = { + .save_first_param = rkisp_save_first_param_v32, + .clear_first_param = rkisp_clear_first_param_v32, + .get_param_size = rkisp_get_param_size_v32, + .first_cfg = rkisp_params_first_cfg_v32, + .disable_isp = rkisp_params_disable_isp_v32, + .isr_hdl = rkisp_params_isr_v32, + .param_cfg = rkisp_params_cfg_v32, + .param_cfgsram = rkisp_params_cfgsram_v32, + .get_meshbuf_inf = rkisp_params_get_meshbuf_inf_v32, + .set_meshbuf_size = rkisp_params_set_meshbuf_size_v32, + .stream_stop = rkisp_params_stream_stop_v32, + .fop_release = rkisp_params_fop_release_v32, +}; + +int rkisp_init_params_vdev_v32(struct rkisp_isp_params_vdev *params_vdev) +{ + struct rkisp_isp_params_val_v32 *priv_val; + int size; + + priv_val = kzalloc(sizeof(*priv_val), GFP_KERNEL); + if (!priv_val) + return -ENOMEM; + + size = sizeof(struct isp32_isp_params_cfg); + params_vdev->isp32_params = vmalloc(size); + if (!params_vdev->isp32_params) { + kfree(priv_val); + return -ENOMEM; + } + + params_vdev->priv_val = (void *)priv_val; + params_vdev->ops = &rkisp_isp_params_ops_tbl; + params_vdev->priv_ops = &isp_params_ops_v32; + rkisp_clear_first_param_v32(params_vdev); + tasklet_init(&priv_val->lsc_tasklet, + isp_lsc_cfg_sram_task, + (unsigned long)params_vdev); + tasklet_disable(&priv_val->lsc_tasklet); + return 0; +} + +void rkisp_uninit_params_vdev_v32(struct rkisp_isp_params_vdev *params_vdev) +{ + struct rkisp_isp_params_val_v32 *priv_val = params_vdev->priv_val; + + if (params_vdev->isp32_params) + vfree(params_vdev->isp32_params); + if (priv_val) { + tasklet_kill(&priv_val->lsc_tasklet); + kfree(priv_val); + params_vdev->priv_val = NULL; + } +} diff --git a/drivers/media/platform/rockchip/isp/isp_params_v32.h b/drivers/media/platform/rockchip/isp/isp_params_v32.h new file mode 100644 index 000000000000..d534b3fd0218 --- /dev/null +++ b/drivers/media/platform/rockchip/isp/isp_params_v32.h @@ -0,0 +1,204 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2022 Rockchip Electronics Co., Ltd. */ + +#ifndef _RKISP_ISP_PARAM_V32_H +#define _RKISP_ISP_PARAM_V32_H + +#include +#include +#include "common.h" +#include "isp_params.h" + +#define ISP32_3DLUT_BUF_NUM 2 +#define ISP32_3DLUT_BUF_SIZE (9 * 9 * 9 * 4) + +#define ISP32_RAWHISTBIG_ROW_NUM 15 +#define ISP32_RAWHISTBIG_COLUMN_NUM 15 +#define ISP32_RAWHISTBIG_WEIGHT_REG_SIZE \ + (ISP32_RAWHISTBIG_ROW_NUM * ISP32_RAWHISTBIG_COLUMN_NUM) + +#define ISP32_RAWHISTLITE_ROW_NUM 5 +#define ISP32_RAWHISTLITE_COLUMN_NUM 5 +#define ISP32_RAWHISTLITE_WEIGHT_REG_SIZE \ + (ISP32_RAWHISTLITE_ROW_NUM * ISP32_RAWHISTLITE_COLUMN_NUM) + +struct rkisp_isp_params_vdev; +struct rkisp_isp_params_ops_v32 { + void (*dpcc_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp2x_dpcc_cfg *arg); + void (*dpcc_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*bls_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_bls_cfg *arg); + void (*bls_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*sdg_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp2x_sdg_cfg *arg); + void (*sdg_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*lsc_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp3x_lsc_cfg *arg); + void (*lsc_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*awbgain_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_awb_gain_cfg *arg); + void (*awbgain_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*debayer_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_debayer_cfg *arg); + void (*debayer_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*ccm_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_ccm_cfg *arg); + void (*ccm_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*goc_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp3x_gammaout_cfg *arg); + void (*goc_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*cproc_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp2x_cproc_cfg *arg); + void (*cproc_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*ie_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp2x_ie_cfg *arg); + void (*ie_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*rawaf_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_rawaf_meas_cfg *arg); + void (*rawaf_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*rawae0_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp2x_rawaelite_meas_cfg *arg); + void (*rawae0_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*rawae1_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp2x_rawaebig_meas_cfg *arg); + void (*rawae1_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*rawae2_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp2x_rawaebig_meas_cfg *arg); + void (*rawae2_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*rawae3_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp2x_rawaebig_meas_cfg *arg); + void (*rawae3_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*rawawb_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_rawawb_meas_cfg *arg); + void (*rawawb_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*rawhst0_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp2x_rawhistlite_cfg *arg); + void (*rawhst0_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*rawhst1_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp2x_rawhistbig_cfg *arg); + void (*rawhst1_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*rawhst2_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp2x_rawhistbig_cfg *arg); + void (*rawhst2_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*rawhst3_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp2x_rawhistbig_cfg *arg); + void (*rawhst3_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*hdrdrc_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_drc_cfg *arg, + enum rkisp_params_type type); + void (*hdrdrc_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*hdrmge_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_hdrmge_cfg *arg, + enum rkisp_params_type type); + void (*hdrmge_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*gic_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp21_gic_cfg *arg); + void (*gic_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*dhaz_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_dhaz_cfg *arg); + void (*dhaz_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*isp3dlut_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp2x_3dlut_cfg *arg); + void (*isp3dlut_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*ldch_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_ldch_cfg *arg); + void (*ldch_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*ynr_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_ynr_cfg *arg); + void (*ynr_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*cnr_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_cnr_cfg *arg); + void (*cnr_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*sharp_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_sharp_cfg *arg); + void (*sharp_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*baynr_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_baynr_cfg *arg); + void (*baynr_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*bay3d_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_bay3d_cfg *arg); + void (*bay3d_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*gain_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp3x_gain_cfg *arg); + void (*gain_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*cac_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_cac_cfg *arg); + void (*cac_enable)(struct rkisp_isp_params_vdev *params_vdev, + bool en); + void (*csm_config)(struct rkisp_isp_params_vdev *params_vdev, + const struct isp21_csm_cfg *arg); +}; + +struct rkisp_isp_params_val_v32 { + struct tasklet_struct lsc_tasklet; + + struct rkisp_dummy_buffer buf_3dlut[ISP32_3DLUT_BUF_NUM]; + u32 buf_3dlut_idx; + + struct rkisp_dummy_buffer buf_ldch[ISP3X_MESH_BUF_NUM]; + u32 buf_ldch_idx; + + struct rkisp_dummy_buffer buf_cac[ISP3X_MESH_BUF_NUM]; + u32 buf_cac_idx; + + struct rkisp_dummy_buffer buf_3dnr_iir; + struct rkisp_dummy_buffer buf_3dnr_cur; + struct rkisp_dummy_buffer buf_3dnr_ds; + + struct isp32_hdrmge_cfg last_hdrmge; + struct isp32_drc_cfg last_hdrdrc; + struct isp32_hdrmge_cfg cur_hdrmge; + struct isp32_drc_cfg cur_hdrdrc; + + bool dhaz_en; + bool drc_en; + bool lsc_en; + bool mge_en; + bool lut3d_en; + bool bay3d_en; + bool is_bigmode; + bool is_lo8x8; +}; + +#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V32) +int rkisp_init_params_vdev_v32(struct rkisp_isp_params_vdev *params_vdev); +void rkisp_uninit_params_vdev_v32(struct rkisp_isp_params_vdev *params_vdev); +#else +static inline int rkisp_init_params_vdev_v32(struct rkisp_isp_params_vdev *params_vdev) { return -EINVAL; } +static inline void rkisp_uninit_params_vdev_v32(struct rkisp_isp_params_vdev *params_vdev) {} +#endif + +#endif /* _RKISP_ISP_PARAM_V32_H */ diff --git a/drivers/media/platform/rockchip/isp/isp_stats.c b/drivers/media/platform/rockchip/isp/isp_stats.c index 981b74915255..b2cbcc19ef2a 100644 --- a/drivers/media/platform/rockchip/isp/isp_stats.c +++ b/drivers/media/platform/rockchip/isp/isp_stats.c @@ -12,6 +12,7 @@ #include "isp_stats_v2x.h" #include "isp_stats_v21.h" #include "isp_stats_v3x.h" +#include "isp_stats_v32.h" #define STATS_NAME DRIVER_NAME "-statistics" #define RKISP_ISP_STATS_REQ_BUFS_MIN 2 @@ -140,10 +141,14 @@ static void rkisp_stats_vb2_buf_queue(struct vb2_buffer *vb) struct rkisp_buffer *stats_buf = to_rkisp_buffer(vbuf); struct vb2_queue *vq = vb->vb2_queue; struct rkisp_isp_stats_vdev *stats_dev = vq->drv_priv; + u32 size = stats_dev->vdev_fmt.fmt.meta.buffersize; unsigned long flags; stats_buf->vaddr[0] = vb2_plane_vaddr(vb, 0); - + if (stats_dev->dev->isp_ver == ISP_V32) + stats_buf->buff_addr[0] = vb2_dma_contig_plane_dma_addr(vb, 0); + if (stats_buf->vaddr[0]) + memset(stats_buf->vaddr[0], 0, size); spin_lock_irqsave(&stats_dev->rd_lock, flags); list_add_tail(&stats_buf->queue, &stats_dev->stat); spin_unlock_irqrestore(&stats_dev->rd_lock, flags); @@ -172,8 +177,16 @@ static void rkisp_stats_vb2_stop_streaming(struct vb2_queue *vq) list_del(&buf->queue); vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); } - if (stats_vdev->cur_buf) + if (stats_vdev->cur_buf) { vb2_buffer_done(&stats_vdev->cur_buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); + if (stats_vdev->cur_buf == stats_vdev->nxt_buf) + stats_vdev->nxt_buf = NULL; + stats_vdev->cur_buf = NULL; + } + if (stats_vdev->nxt_buf) { + vb2_buffer_done(&stats_vdev->nxt_buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); + stats_vdev->nxt_buf = NULL; + } spin_unlock_irqrestore(&stats_vdev->rd_lock, flags); } @@ -208,7 +221,10 @@ static int rkisp_stats_init_vb2_queue(struct vb2_queue *q, q->io_modes = VB2_MMAP | VB2_USERPTR; q->drv_priv = stats_vdev; q->ops = &rkisp_stats_vb2_ops; - q->mem_ops = &vb2_vmalloc_memops; + if (stats_vdev->dev->isp_ver == ISP_V32) + q->mem_ops = &vb2_dma_contig_memops; + else + q->mem_ops = &vb2_vmalloc_memops; q->buf_struct_size = sizeof(struct rkisp_buffer); q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; q->lock = &stats_vdev->dev->iqlock; @@ -247,8 +263,10 @@ static void rkisp_init_stats_vdev(struct rkisp_isp_stats_vdev *stats_vdev) rkisp_init_stats_vdev_v21(stats_vdev); else if (stats_vdev->dev->isp_ver == ISP_V20) rkisp_init_stats_vdev_v2x(stats_vdev); - else + else if (stats_vdev->dev->isp_ver == ISP_V30) rkisp_init_stats_vdev_v3x(stats_vdev); + else + rkisp_init_stats_vdev_v32(stats_vdev); } static void rkisp_uninit_stats_vdev(struct rkisp_isp_stats_vdev *stats_vdev) @@ -259,8 +277,10 @@ static void rkisp_uninit_stats_vdev(struct rkisp_isp_stats_vdev *stats_vdev) rkisp_uninit_stats_vdev_v21(stats_vdev); else if (stats_vdev->dev->isp_ver == ISP_V20) rkisp_uninit_stats_vdev_v2x(stats_vdev); - else + else if (stats_vdev->dev->isp_ver == ISP_V30) rkisp_uninit_stats_vdev_v3x(stats_vdev); + else + rkisp_uninit_stats_vdev_v32(stats_vdev); } void rkisp_stats_rdbk_enable(struct rkisp_isp_stats_vdev *stats_vdev, bool en) @@ -276,6 +296,14 @@ void rkisp_stats_first_ddr_config(struct rkisp_isp_stats_vdev *stats_vdev) rkisp_stats_first_ddr_config_v21(stats_vdev); else if (stats_vdev->dev->isp_ver == ISP_V30) rkisp_stats_first_ddr_config_v3x(stats_vdev); + else if (stats_vdev->dev->isp_ver == ISP_V32) + rkisp_stats_first_ddr_config_v32(stats_vdev); +} + +void rkisp_stats_next_ddr_config(struct rkisp_isp_stats_vdev *stats_vdev) +{ + if (stats_vdev->dev->isp_ver == ISP_V32) + rkisp_stats_next_ddr_config_v32(stats_vdev); } void rkisp_stats_isr(struct rkisp_isp_stats_vdev *stats_vdev, diff --git a/drivers/media/platform/rockchip/isp/isp_stats.h b/drivers/media/platform/rockchip/isp/isp_stats.h index 249ed2535585..d3b1e33eb66c 100644 --- a/drivers/media/platform/rockchip/isp/isp_stats.h +++ b/drivers/media/platform/rockchip/isp/isp_stats.h @@ -71,11 +71,13 @@ struct rkisp_isp_stats_vdev { struct rkisp_dummy_buffer tmp_statsbuf; struct rkisp_buffer *cur_buf; + struct rkisp_buffer *nxt_buf; }; void rkisp_stats_rdbk_enable(struct rkisp_isp_stats_vdev *stats_vdev, bool en); void rkisp_stats_first_ddr_config(struct rkisp_isp_stats_vdev *stats_vdev); +void rkisp_stats_next_ddr_config(struct rkisp_isp_stats_vdev *stats_vdev); void rkisp_stats_isr(struct rkisp_isp_stats_vdev *stats_vdev, u32 isp_ris, u32 isp3a_ris); diff --git a/drivers/media/platform/rockchip/isp/isp_stats_v32.c b/drivers/media/platform/rockchip/isp/isp_stats_v32.c new file mode 100644 index 000000000000..c589642be6b2 --- /dev/null +++ b/drivers/media/platform/rockchip/isp/isp_stats_v32.c @@ -0,0 +1,656 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (c) 2022 Rockchip Electronics Co., Ltd. */ + +#include +#include +#include +#include +#include +#include /* for ISP statistics */ +#include "dev.h" +#include "regs.h" +#include "common.h" +#include "isp_stats.h" +#include "isp_stats_v32.h" + +#define ISP32_3A_MEAS_DONE BIT(31) + +static void isp3_module_done(struct rkisp_isp_stats_vdev *stats_vdev, + u32 reg, u32 value) +{ + void __iomem *base = stats_vdev->dev->hw_dev->base_addr; + + writel(value, base + reg); +} + +static u32 isp3_stats_read(struct rkisp_isp_stats_vdev *stats_vdev, u32 addr) +{ + return rkisp_read(stats_vdev->dev, addr, true); +} + +static void isp3_stats_write(struct rkisp_isp_stats_vdev *stats_vdev, + u32 addr, u32 value) +{ + rkisp_write(stats_vdev->dev, addr, value, true); +} + +static int +rkisp_stats_get_bls_stats(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp32_isp_stat_buffer *pbuf) +{ + struct ispsd_in_fmt in_fmt = stats_vdev->dev->isp_sdev.in_fmt; + enum rkisp_fmt_raw_pat_type raw_type = in_fmt.bayer_pat; + struct isp2x_bls_stat *bls; + u32 value; + + if (!pbuf) + return 0; + + bls = &pbuf->params.bls; + value = isp3_stats_read(stats_vdev, ISP3X_BLS_CTRL); + if (value & (ISP_BLS_ENA | ISP_BLS_MODE_MEASURED)) { + pbuf->meas_type |= ISP32_STAT_BLS; + + switch (raw_type) { + case RAW_BGGR: + bls->meas_r = isp3_stats_read(stats_vdev, ISP3X_BLS_D_MEASURED); + bls->meas_gr = isp3_stats_read(stats_vdev, ISP3X_BLS_C_MEASURED); + bls->meas_gb = isp3_stats_read(stats_vdev, ISP3X_BLS_B_MEASURED); + bls->meas_b = isp3_stats_read(stats_vdev, ISP3X_BLS_A_MEASURED); + break; + case RAW_GBRG: + bls->meas_r = isp3_stats_read(stats_vdev, ISP3X_BLS_C_MEASURED); + bls->meas_gr = isp3_stats_read(stats_vdev, ISP3X_BLS_D_MEASURED); + bls->meas_gb = isp3_stats_read(stats_vdev, ISP3X_BLS_A_MEASURED); + bls->meas_b = isp3_stats_read(stats_vdev, ISP3X_BLS_B_MEASURED); + break; + case RAW_GRBG: + bls->meas_r = isp3_stats_read(stats_vdev, ISP3X_BLS_B_MEASURED); + bls->meas_gr = isp3_stats_read(stats_vdev, ISP3X_BLS_A_MEASURED); + bls->meas_gb = isp3_stats_read(stats_vdev, ISP3X_BLS_D_MEASURED); + bls->meas_b = isp3_stats_read(stats_vdev, ISP3X_BLS_C_MEASURED); + break; + case RAW_RGGB: + bls->meas_r = isp3_stats_read(stats_vdev, ISP3X_BLS_A_MEASURED); + bls->meas_gr = isp3_stats_read(stats_vdev, ISP3X_BLS_B_MEASURED); + bls->meas_gb = isp3_stats_read(stats_vdev, ISP3X_BLS_C_MEASURED); + bls->meas_b = isp3_stats_read(stats_vdev, ISP3X_BLS_D_MEASURED); + break; + default: + break; + } + } + return 0; +} + +static int +rkisp_stats_get_dhaz_stats(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp32_isp_stat_buffer *pbuf) +{ + struct isp3x_dhaz_stat *dhaz; + u32 value, i; + + if (!pbuf) + return 0; + + dhaz = &pbuf->params.dhaz; + value = isp3_stats_read(stats_vdev, ISP3X_DHAZ_CTRL); + if (value & ISP_DHAZ_ENMUX) { + pbuf->meas_type |= ISP32_STAT_DHAZ; + + value = isp3_stats_read(stats_vdev, ISP3X_DHAZ_SUMH_RD); + dhaz->dhaz_pic_sumh = value; + + value = isp3_stats_read(stats_vdev, ISP3X_DHAZ_ADP_RD0); + dhaz->dhaz_adp_air_base = value >> 16; + dhaz->dhaz_adp_wt = value & 0xFFFF; + + value = isp3_stats_read(stats_vdev, ISP3X_DHAZ_ADP_RD1); + dhaz->dhaz_adp_gratio = value >> 16; + dhaz->dhaz_adp_tmax = value & 0xFFFF; + + for (i = 0; i < ISP3X_DHAZ_HIST_IIR_NUM / 2; i++) { + value = isp3_stats_read(stats_vdev, ISP3X_DHAZ_HIST_REG0 + 4 * i); + dhaz->h_rgb_iir[2 * i] = value & 0xFFFF; + dhaz->h_rgb_iir[2 * i + 1] = value >> 16; + } + } + return 0; +} + +static int +rkisp_stats_get_rawawb_meas_ddr(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp32_isp_stat_buffer *pbuf) +{ + u32 ctrl = isp3_stats_read(stats_vdev, ISP3X_RAWAWB_CTRL); + + if (!(ctrl & ISP32_3A_MEAS_DONE)) { + v4l2_dbg(1, rkisp_debug, &stats_vdev->dev->v4l2_dev, + "%s fail, ctrl:0x%x\n", __func__, ctrl); + return -ENODATA; + } + + if (!pbuf) + goto out; + + pbuf->meas_type |= ISP32_STAT_RAWAWB; +out: + isp3_module_done(stats_vdev, ISP3X_RAWAWB_CTRL, ctrl); + return 0; +} + +static int +rkisp_stats_get_rawaf_meas_ddr(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp32_isp_stat_buffer *pbuf) +{ + struct isp32_rawaf_stat *af; + u32 ctrl; + + ctrl = isp3_stats_read(stats_vdev, ISP3X_RAWAF_CTRL); + if (!(ctrl & ISP32_3A_MEAS_DONE)) { + v4l2_dbg(1, rkisp_debug, &stats_vdev->dev->v4l2_dev, + "%s fail, ctrl:0x%x\n", __func__, ctrl); + return -ENODATA; + } + + if (!pbuf) + goto out; + + af = &pbuf->params.rawaf; + pbuf->meas_type |= ISP32_STAT_RAWAF; + + af->afm_sum_b = isp3_stats_read(stats_vdev, ISP3X_RAWAF_SUM_B); + af->afm_lum_b = isp3_stats_read(stats_vdev, ISP3X_RAWAF_LUM_B); + af->int_state = isp3_stats_read(stats_vdev, ISP3X_RAWAF_INT_STATE); + af->highlit_cnt_winb = isp3_stats_read(stats_vdev, ISP3X_RAWAF_HIGHLIT_CNT_WINB); + +out: + isp3_module_done(stats_vdev, ISP3X_RAWAF_CTRL, ctrl); + return 0; +} + +static int +rkisp_stats_get_rawaebig_meas_ddr(struct rkisp_isp_stats_vdev *stats_vdev, + struct isp32_rawaebig_stat1 *ae, u32 blk_no) +{ + u32 i, base, addr, ctrl; + + switch (blk_no) { + case 1: + base = RAWAE_BIG2_BASE; + break; + case 2: + base = RAWAE_BIG3_BASE; + break; + default: + base = RAWAE_BIG1_BASE; + break; + } + + ctrl = isp3_stats_read(stats_vdev, base + ISP3X_RAWAE_BIG_CTRL); + if (!(ctrl & ISP32_3A_MEAS_DONE)) { + v4l2_dbg(1, rkisp_debug, &stats_vdev->dev->v4l2_dev, + "%s fail, addr:0x%x ctrl:0x%x\n", + __func__, base, ctrl); + return -ENODATA; + } + + if (!ae) + goto out; + + for (i = 0; i < ISP32_RAWAEBIG_SUBWIN_NUM; i++) { + addr = base + ISP3X_RAWAE_BIG_WND1_SUMR + i * 4; + ae->sumr[i] = isp3_stats_read(stats_vdev, addr); + addr = base + ISP3X_RAWAE_BIG_WND1_SUMG + i * 4; + ae->sumg[i] = isp3_stats_read(stats_vdev, addr); + addr = base + ISP3X_RAWAE_BIG_WND1_SUMB + i * 4; + ae->sumb[i] = isp3_stats_read(stats_vdev, addr); + } + +out: + isp3_module_done(stats_vdev, base + ISP3X_RAWAE_BIG_CTRL, ctrl); + return 0; +} + +static int +rkisp_stats_get_rawhstbig_meas_ddr(struct rkisp_isp_stats_vdev *stats_vdev, + struct isp2x_rawhistbig_stat *hst, u32 blk_no) +{ + u32 addr, ctrl; + + switch (blk_no) { + case 1: + addr = ISP3X_RAWHIST_BIG2_BASE; + break; + case 2: + addr = ISP3X_RAWHIST_BIG3_BASE; + break; + case 0: + default: + addr = ISP3X_RAWHIST_BIG1_BASE; + break; + } + + ctrl = isp3_stats_read(stats_vdev, addr + ISP3X_RAWHIST_BIG_CTRL); + if (!(ctrl & ISP32_3A_MEAS_DONE)) { + v4l2_dbg(1, rkisp_debug, &stats_vdev->dev->v4l2_dev, + "%s fail, addr:0x%x ctrl:0x%x\n", + __func__, addr, ctrl); + return -ENODATA; + } + + if (!hst) + goto out; + +out: + isp3_module_done(stats_vdev, addr + ISP3X_RAWHIST_BIG_CTRL, ctrl); + return 0; +} + +static int +rkisp_stats_get_rawae1_meas_ddr(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp32_isp_stat_buffer *pbuf) +{ + int ret = 0; + + if (!pbuf) { + rkisp_stats_get_rawaebig_meas_ddr(stats_vdev, NULL, 1); + } else { + ret = rkisp_stats_get_rawaebig_meas_ddr(stats_vdev, + &pbuf->params.rawae1_1, 1); + if (!ret) + pbuf->meas_type |= ISP32_STAT_RAWAE1; + } + + return ret; +} + +static int +rkisp_stats_get_rawhst1_meas_ddr(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp32_isp_stat_buffer *pbuf) +{ + int ret = 0; + + if (!pbuf) { + rkisp_stats_get_rawhstbig_meas_ddr(stats_vdev, NULL, 1); + } else { + ret = rkisp_stats_get_rawhstbig_meas_ddr(stats_vdev, + &pbuf->params.rawhist1, 1); + if (!ret) + pbuf->meas_type |= ISP32_STAT_RAWHST1; + } + + return ret; +} + +static int +rkisp_stats_get_rawae2_meas_ddr(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp32_isp_stat_buffer *pbuf) +{ + int ret = 0; + + if (!pbuf) { + rkisp_stats_get_rawaebig_meas_ddr(stats_vdev, NULL, 2); + } else { + ret = rkisp_stats_get_rawaebig_meas_ddr(stats_vdev, + &pbuf->params.rawae2_1, 2); + if (!ret) + pbuf->meas_type |= ISP32_STAT_RAWAE2; + } + + return ret; +} + +static int +rkisp_stats_get_rawhst2_meas_ddr(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp32_isp_stat_buffer *pbuf) +{ + int ret = 0; + + if (!pbuf) { + rkisp_stats_get_rawhstbig_meas_ddr(stats_vdev, NULL, 2); + } else { + ret = rkisp_stats_get_rawhstbig_meas_ddr(stats_vdev, + &pbuf->params.rawhist2, 2); + if (!ret) + pbuf->meas_type |= ISP32_STAT_RAWHST2; + } + + return ret; +} + +static int +rkisp_stats_get_rawae3_meas_ddr(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp32_isp_stat_buffer *pbuf) +{ + int ret = 0; + + if (!pbuf) { + rkisp_stats_get_rawaebig_meas_ddr(stats_vdev, NULL, 0); + } else { + ret = rkisp_stats_get_rawaebig_meas_ddr(stats_vdev, + &pbuf->params.rawae3_1, 0); + if (!ret) + pbuf->meas_type |= ISP32_STAT_RAWAE3; + } + + return ret; +} + +static int +rkisp_stats_get_rawhst3_meas_ddr(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp32_isp_stat_buffer *pbuf) +{ + int ret = 0; + + if (!pbuf) { + rkisp_stats_get_rawhstbig_meas_ddr(stats_vdev, NULL, 0); + } else { + ret = rkisp_stats_get_rawhstbig_meas_ddr(stats_vdev, + &pbuf->params.rawhist3, 0); + if (!ret) + pbuf->meas_type |= ISP32_STAT_RAWHST3; + } + + return ret; +} + +static int +rkisp_stats_get_rawaelite_meas_ddr(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp32_isp_stat_buffer *pbuf) +{ + u32 ctrl; + + ctrl = isp3_stats_read(stats_vdev, ISP3X_RAWAE_LITE_CTRL); + if ((ctrl & ISP32_3A_MEAS_DONE) == 0) { + v4l2_dbg(1, rkisp_debug, &stats_vdev->dev->v4l2_dev, + "%s fail, ctrl:0x%x\n", __func__, ctrl); + return -ENODATA; + } + + if (!pbuf) + goto out; + + pbuf->meas_type |= ISP32_STAT_RAWAE0; + +out: + isp3_module_done(stats_vdev, ISP3X_RAWAE_LITE_CTRL, ctrl); + return 0; +} + +static int +rkisp_stats_get_rawhstlite_meas_ddr(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp32_isp_stat_buffer *pbuf) +{ + u32 ctrl; + + ctrl = isp3_stats_read(stats_vdev, ISP3X_RAWHIST_LITE_CTRL); + if ((ctrl & ISP32_3A_MEAS_DONE) == 0) { + v4l2_dbg(1, rkisp_debug, &stats_vdev->dev->v4l2_dev, + "%s fail, ctrl:0x%x\n", __func__, ctrl); + return -ENODATA; + } + + if (!pbuf) + goto out; + + pbuf->meas_type |= ISP32_STAT_RAWHST0; + +out: + isp3_module_done(stats_vdev, ISP3X_RAWHIST_LITE_CTRL, ctrl); + return 0; +} + +static struct rkisp_stats_ops_v32 __maybe_unused stats_ddr_ops_v32 = { + .get_rawawb_meas = rkisp_stats_get_rawawb_meas_ddr, + .get_rawaf_meas = rkisp_stats_get_rawaf_meas_ddr, + .get_rawae0_meas = rkisp_stats_get_rawaelite_meas_ddr, + .get_rawhst0_meas = rkisp_stats_get_rawhstlite_meas_ddr, + .get_rawae1_meas = rkisp_stats_get_rawae1_meas_ddr, + .get_rawhst1_meas = rkisp_stats_get_rawhst1_meas_ddr, + .get_rawae2_meas = rkisp_stats_get_rawae2_meas_ddr, + .get_rawhst2_meas = rkisp_stats_get_rawhst2_meas_ddr, + .get_rawae3_meas = rkisp_stats_get_rawae3_meas_ddr, + .get_rawhst3_meas = rkisp_stats_get_rawhst3_meas_ddr, + .get_bls_stats = rkisp_stats_get_bls_stats, + .get_dhaz_stats = rkisp_stats_get_dhaz_stats, +}; + +static void +rkisp_stats_update_buf(struct rkisp_isp_stats_vdev *stats_vdev) +{ + struct rkisp_device *dev = stats_vdev->dev; + struct rkisp_buffer *buf; + unsigned long flags; + + spin_lock_irqsave(&stats_vdev->rd_lock, flags); + if (!stats_vdev->nxt_buf && !list_empty(&stats_vdev->stat)) { + buf = list_first_entry(&stats_vdev->stat, + struct rkisp_buffer, queue); + list_del(&buf->queue); + stats_vdev->nxt_buf = buf; + } + spin_unlock_irqrestore(&stats_vdev->rd_lock, flags); + + if (stats_vdev->nxt_buf) { + rkisp_set_bits(dev, ISP3X_SWS_CFG, 0, ISP3X_3A_DDR_WRITE_EN, false); + rkisp_write(dev, ISP3X_MI_3A_WR_BASE, stats_vdev->nxt_buf->buff_addr[0], false); + v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev, + "%s BASE:0x%x SHD:0x%x\n", + __func__, stats_vdev->nxt_buf->buff_addr[0], + isp3_stats_read(stats_vdev, ISP3X_MI_3A_WR_BASE)); + if (!dev->hw_dev->is_single) { + stats_vdev->cur_buf = stats_vdev->nxt_buf; + stats_vdev->nxt_buf = NULL; + } + } else { + rkisp_clear_bits(dev, ISP3X_SWS_CFG, ISP3X_3A_DDR_WRITE_EN, false); + } +} + +static void +rkisp_stats_send_meas_v32(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp_isp_readout_work *meas_work) +{ + unsigned int cur_frame_id = -1; + struct rkisp_buffer *cur_buf = stats_vdev->cur_buf; + struct rkisp32_isp_stat_buffer *cur_stat_buf = NULL; + struct rkisp_stats_ops_v32 *ops = + (struct rkisp_stats_ops_v32 *)stats_vdev->priv_ops; + u32 size = sizeof(struct rkisp32_isp_stat_buffer); + int ret = 0; + + /* config buf for next frame */ + stats_vdev->cur_buf = NULL; + if (stats_vdev->nxt_buf) { + stats_vdev->cur_buf = stats_vdev->nxt_buf; + stats_vdev->nxt_buf = NULL; + } + rkisp_stats_update_buf(stats_vdev); + + cur_frame_id = meas_work->frame_id; + + if (cur_buf) { + cur_stat_buf = + (struct rkisp32_isp_stat_buffer *)(cur_buf->vaddr[0]); + cur_stat_buf->frame_id = cur_frame_id; + } + + if (meas_work->isp_ris & ISP3X_AFM_SUM_OF) + v4l2_warn(stats_vdev->vnode.vdev.v4l2_dev, + "ISP3X_AFM_SUM_OF\n"); + + if (meas_work->isp_ris & ISP3X_AFM_LUM_OF) + v4l2_warn(stats_vdev->vnode.vdev.v4l2_dev, + "ISP3X_AFM_LUM_OF\n"); + + if (meas_work->isp3a_ris & ISP3X_3A_RAWAF_SUM) + v4l2_warn(stats_vdev->vnode.vdev.v4l2_dev, + "ISP3X_3A_RAWAF_SUM\n"); + + if (meas_work->isp3a_ris & ISP3X_3A_RAWAWB) + ret |= ops->get_rawawb_meas(stats_vdev, cur_stat_buf); + + if (meas_work->isp3a_ris & ISP3X_3A_RAWAF) + ret |= ops->get_rawaf_meas(stats_vdev, cur_stat_buf); + + if (meas_work->isp3a_ris & ISP3X_3A_RAWAE_BIG) + ret |= ops->get_rawae3_meas(stats_vdev, cur_stat_buf); + + if (meas_work->isp3a_ris & ISP3X_3A_RAWHIST_BIG) + ret |= ops->get_rawhst3_meas(stats_vdev, cur_stat_buf); + + if (meas_work->isp3a_ris & ISP3X_3A_RAWAE_CH0) + ret |= ops->get_rawae0_meas(stats_vdev, cur_stat_buf); + + if (meas_work->isp3a_ris & ISP3X_3A_RAWAE_CH1) + ret |= ops->get_rawae1_meas(stats_vdev, cur_stat_buf); + + if (meas_work->isp3a_ris & ISP3X_3A_RAWAE_CH2) + ret |= ops->get_rawae2_meas(stats_vdev, cur_stat_buf); + + if (meas_work->isp3a_ris & ISP3X_3A_RAWHIST_CH0) + ret |= ops->get_rawhst0_meas(stats_vdev, cur_stat_buf); + + if (meas_work->isp3a_ris & ISP3X_3A_RAWHIST_CH1) + ret |= ops->get_rawhst1_meas(stats_vdev, cur_stat_buf); + + if (meas_work->isp3a_ris & ISP3X_3A_RAWHIST_CH2) + ret |= ops->get_rawhst2_meas(stats_vdev, cur_stat_buf); + + if (meas_work->isp_ris & ISP3X_FRAME) { + ret |= ops->get_bls_stats(stats_vdev, cur_stat_buf); + ret |= ops->get_dhaz_stats(stats_vdev, cur_stat_buf); + } + + if (cur_buf) { + if (ret || !cur_stat_buf->meas_type) { + unsigned long flags; + + spin_lock_irqsave(&stats_vdev->rd_lock, flags); + list_add_tail(&cur_buf->queue, &stats_vdev->stat); + spin_unlock_irqrestore(&stats_vdev->rd_lock, flags); + } else { + vb2_set_plane_payload(&cur_buf->vb.vb2_buf, 0, size); + cur_buf->vb.sequence = cur_frame_id; + cur_buf->vb.vb2_buf.timestamp = meas_work->timestamp; + vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); + } + } +} + +static void +rkisp_stats_isr_v32(struct rkisp_isp_stats_vdev *stats_vdev, + u32 isp_ris, u32 isp3a_ris) +{ + struct rkisp_isp_readout_work work; + u32 iq_isr_mask = ISP3X_SIAWB_DONE | ISP3X_SIAF_FIN | + ISP3X_EXP_END | ISP3X_SIHST_RDY | ISP3X_AFM_SUM_OF | ISP3X_AFM_LUM_OF; + u32 cur_frame_id, isp_mis_tmp = 0; + u32 temp_isp_ris, temp_isp3a_ris; + + rkisp_dmarx_get_frame(stats_vdev->dev, &cur_frame_id, NULL, NULL, true); + + spin_lock(&stats_vdev->irq_lock); + + temp_isp_ris = isp3_stats_read(stats_vdev, ISP3X_ISP_RIS); + temp_isp3a_ris = isp3_stats_read(stats_vdev, ISP3X_ISP_3A_RIS); + + isp_mis_tmp = isp_ris & iq_isr_mask; + if (isp_mis_tmp) { + isp3_stats_write(stats_vdev, ISP3X_ISP_ICR, isp_mis_tmp); + + isp_mis_tmp &= isp3_stats_read(stats_vdev, ISP3X_ISP_MIS); + if (isp_mis_tmp) + v4l2_err(stats_vdev->vnode.vdev.v4l2_dev, + "isp icr 3A info err: 0x%x 0x%x\n", + isp_mis_tmp, isp_ris); + } + + isp_mis_tmp = temp_isp3a_ris; + if (isp_mis_tmp) { + isp3_stats_write(stats_vdev, ISP3X_ISP_3A_ICR, isp_mis_tmp); + + isp_mis_tmp &= isp3_stats_read(stats_vdev, ISP3X_ISP_3A_MIS); + if (isp_mis_tmp) + v4l2_err(stats_vdev->vnode.vdev.v4l2_dev, + "isp3A icr 3A info err: 0x%x 0x%x\n", + isp_mis_tmp, isp3a_ris); + } + + if (!stats_vdev->streamon) + goto unlock; + + if (isp_ris & ISP3X_FRAME) { + work.readout = RKISP_ISP_READOUT_MEAS; + work.frame_id = cur_frame_id; + work.isp_ris = temp_isp_ris | isp_ris; + work.isp3a_ris = temp_isp3a_ris; + work.timestamp = ktime_get_ns(); + rkisp_stats_send_meas_v32(stats_vdev, &work); + } + +unlock: + spin_unlock(&stats_vdev->irq_lock); +} + +static void +rkisp_stats_rdbk_enable_v32(struct rkisp_isp_stats_vdev *stats_vdev, bool en) +{ + if (!en) { + stats_vdev->isp_rdbk = 0; + stats_vdev->isp3a_rdbk = 0; + } + + stats_vdev->rdbk_mode = en; +} + +static struct rkisp_isp_stats_ops rkisp_isp_stats_ops_tbl = { + .isr_hdl = rkisp_stats_isr_v32, + .send_meas = rkisp_stats_send_meas_v32, + .rdbk_enable = rkisp_stats_rdbk_enable_v32, +}; + +void rkisp_stats_first_ddr_config_v32(struct rkisp_isp_stats_vdev *stats_vdev) +{ + struct rkisp_device *dev = stats_vdev->dev; + u32 size = stats_vdev->vdev_fmt.fmt.meta.buffersize; + + if (!stats_vdev->streamon) + return; + + rkisp_stats_update_buf(stats_vdev); + rkisp_write(dev, ISP3X_MI_DBR_WR_SIZE, size, false); + if (stats_vdev->nxt_buf) { + stats_vdev->cur_buf = stats_vdev->nxt_buf; + stats_vdev->nxt_buf = NULL; + } +} + +void rkisp_stats_next_ddr_config_v32(struct rkisp_isp_stats_vdev *stats_vdev) +{ + struct rkisp_hw_dev *hw = stats_vdev->dev->hw_dev; + + if (!stats_vdev->streamon) + return; + /* pingpong buf */ + if (hw->is_single) + rkisp_stats_update_buf(stats_vdev); +} + +void rkisp_init_stats_vdev_v32(struct rkisp_isp_stats_vdev *stats_vdev) +{ + stats_vdev->vdev_fmt.fmt.meta.dataformat = + V4L2_META_FMT_RK_ISP1_STAT_3A; + stats_vdev->vdev_fmt.fmt.meta.buffersize = + sizeof(struct rkisp32_isp_stat_buffer); + + stats_vdev->ops = &rkisp_isp_stats_ops_tbl; + stats_vdev->priv_ops = &stats_ddr_ops_v32; + stats_vdev->rd_stats_from_ddr = true; +} + +void rkisp_uninit_stats_vdev_v32(struct rkisp_isp_stats_vdev *stats_vdev) +{ + +} diff --git a/drivers/media/platform/rockchip/isp/isp_stats_v32.h b/drivers/media/platform/rockchip/isp/isp_stats_v32.h new file mode 100644 index 000000000000..9c17f38172b9 --- /dev/null +++ b/drivers/media/platform/rockchip/isp/isp_stats_v32.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2022 Rockchip Electronics Co., Ltd. */ + +#ifndef _RKISP_ISP_STATS_V32_H +#define _RKISP_ISP_STATS_V32_H + +#include +#include +#include +#include "common.h" + +#define ISP32_RD_STATS_BUF_SIZE 0x10000 + +struct rkisp_isp_stats_vdev; +struct rkisp_stats_ops_v32 { + int (*get_rawawb_meas)(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp32_isp_stat_buffer *pbuf); + int (*get_rawaf_meas)(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp32_isp_stat_buffer *pbuf); + int (*get_rawae0_meas)(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp32_isp_stat_buffer *pbuf); + int (*get_rawhst0_meas)(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp32_isp_stat_buffer *pbuf); + int (*get_rawae1_meas)(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp32_isp_stat_buffer *pbuf); + int (*get_rawhst1_meas)(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp32_isp_stat_buffer *pbuf); + int (*get_rawae2_meas)(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp32_isp_stat_buffer *pbuf); + int (*get_rawhst2_meas)(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp32_isp_stat_buffer *pbuf); + int (*get_rawae3_meas)(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp32_isp_stat_buffer *pbuf); + int (*get_rawhst3_meas)(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp32_isp_stat_buffer *pbuf); + int (*get_bls_stats)(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp32_isp_stat_buffer *pbuf); + int (*get_dhaz_stats)(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp32_isp_stat_buffer *pbuf); +}; + +#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V32) +void rkisp_stats_first_ddr_config_v32(struct rkisp_isp_stats_vdev *stats_vdev); +void rkisp_stats_next_ddr_config_v32(struct rkisp_isp_stats_vdev *stats_vdev); +void rkisp_init_stats_vdev_v32(struct rkisp_isp_stats_vdev *stats_vdev); +void rkisp_uninit_stats_vdev_v32(struct rkisp_isp_stats_vdev *stats_vdev); +#else +static inline void rkisp_stats_first_ddr_config_v32(struct rkisp_isp_stats_vdev *stats_vdev) {} +static inline void rkisp_stats_next_ddr_config_v32(struct rkisp_isp_stats_vdev *stats_vdev) {} +static inline void rkisp_init_stats_vdev_v32(struct rkisp_isp_stats_vdev *stats_vdev) {} +static inline void rkisp_uninit_stats_vdev_v32(struct rkisp_isp_stats_vdev *stats_vdev) {} +#endif + +#endif /* _RKISP_ISP_STATS_V32_H */ diff --git a/drivers/media/platform/rockchip/isp/procfs.c b/drivers/media/platform/rockchip/isp/procfs.c index 4594789ac355..aa34e3c8e0c5 100644 --- a/drivers/media/platform/rockchip/isp/procfs.c +++ b/drivers/media/platform/rockchip/isp/procfs.c @@ -762,6 +762,9 @@ static int isp_show(struct seq_file *p, void *v) else isp30_show(dev, p); break; + case ISP_V32: + isp30_show(dev, p); + break; default: break; } diff --git a/drivers/media/platform/rockchip/isp/regs_v3x.h b/drivers/media/platform/rockchip/isp/regs_v3x.h index b8db3e46f439..f2c88e825008 100644 --- a/drivers/media/platform/rockchip/isp/regs_v3x.h +++ b/drivers/media/platform/rockchip/isp/regs_v3x.h @@ -39,6 +39,10 @@ #define ISP3X_CMSK_YUV5 (ISP3X_CMSK_BASE + 0x00034) #define ISP3X_CMSK_YUV6 (ISP3X_CMSK_BASE + 0x00038) #define ISP3X_CMSK_YUV7 (ISP3X_CMSK_BASE + 0x0003c) +#define ISP32_CMSK_YUV8 (ISP3X_CMSK_BASE + 0x00040) +#define ISP32_CMSK_YUV9 (ISP3X_CMSK_BASE + 0x00044) +#define ISP32_CMSK_YUV10 (ISP3X_CMSK_BASE + 0x00048) +#define ISP32_CMSK_YUV11 (ISP3X_CMSK_BASE + 0x0004c) #define ISP3X_CMSK_OFFS0 (ISP3X_CMSK_BASE + 0x00050) #define ISP3X_CMSK_SIZE0 (ISP3X_CMSK_BASE + 0x00054) #define ISP3X_CMSK_OFFS1 (ISP3X_CMSK_BASE + 0x00058) @@ -55,6 +59,14 @@ #define ISP3X_CMSK_SIZE6 (ISP3X_CMSK_BASE + 0x00084) #define ISP3X_CMSK_OFFS7 (ISP3X_CMSK_BASE + 0x00088) #define ISP3X_CMSK_SIZE7 (ISP3X_CMSK_BASE + 0x0008c) +#define ISP32_CMSK_OFFS8 (ISP3X_CMSK_BASE + 0x00090) +#define ISP32_CMSK_SIZE8 (ISP3X_CMSK_BASE + 0x00094) +#define ISP32_CMSK_OFFS9 (ISP3X_CMSK_BASE + 0x00098) +#define ISP32_CMSK_SIZE9 (ISP3X_CMSK_BASE + 0x0009c) +#define ISP32_CMSK_OFFS10 (ISP3X_CMSK_BASE + 0x000a0) +#define ISP32_CMSK_SIZE10 (ISP3X_CMSK_BASE + 0x000a4) +#define ISP32_CMSK_OFFS11 (ISP3X_CMSK_BASE + 0x000a8) +#define ISP32_CMSK_SIZE11 (ISP3X_CMSK_BASE + 0x000ac) #define ISP3X_SUPER_IMP_BASE 0x00000300 #define ISP3X_SUPER_IMP_CTRL (ISP3X_SUPER_IMP_BASE + 0x00000) @@ -125,6 +137,8 @@ #define ISP3X_ISP_GAMMA_B_Y_14 (ISP3X_ISP_BASE + 0x000e4) #define ISP3X_ISP_GAMMA_B_Y_15 (ISP3X_ISP_BASE + 0x000e8) #define ISP3X_ISP_GAMMA_B_Y_16 (ISP3X_ISP_BASE + 0x000ec) +#define ISP32_ISP_AWB1_GAIN_G (ISP3X_ISP_BASE + 0x00130) +#define ISP32_ISP_AWB1_GAIN_RB (ISP3X_ISP_BASE + 0x00134) #define ISP3X_ISP_AWB_GAIN0_G (ISP3X_ISP_BASE + 0x00138) #define ISP3X_ISP_AWB_GAIN0_RB (ISP3X_ISP_BASE + 0x0013c) #define ISP3X_ISP_AWB_GAIN1_G (ISP3X_ISP_BASE + 0x00140) @@ -134,6 +148,8 @@ #define ISP3X_ISP_HURRY_CTRL (ISP3X_ISP_BASE + 0x00158) #define ISP3X_ISP_AWQOS_CTRL (ISP3X_ISP_BASE + 0x0015C) #define ISP3X_ISP_ARQOS_CTRL (ISP3X_ISP_BASE + 0x00160) +#define ISP32_ISP_IRQ_CFG0 (ISP3X_ISP_BASE + 0x00164) +#define ISP32_ISP_IRQ_CFG1 (ISP3X_ISP_BASE + 0x00168) #define ISP3X_ISP_CC_COEFF_0 (ISP3X_ISP_BASE + 0x00170) #define ISP3X_ISP_CC_COEFF_1 (ISP3X_ISP_BASE + 0x00174) #define ISP3X_ISP_CC_COEFF_2 (ISP3X_ISP_BASE + 0x00178) @@ -167,6 +183,9 @@ #define ISP3X_ISP_DEBUG1 (ISP3X_ISP_BASE + 0x00248) #define ISP3X_ISP_DEBUG2 (ISP3X_ISP_BASE + 0x0024C) #define ISP3X_ISP_DEBUG3 (ISP3X_ISP_BASE + 0x00250) +#define ISP32_ISP_DEBUG4 (ISP3X_ISP_BASE + 0x00254) +#define ISP32_YNR_LUMA_RCTRL (ISP3X_ISP_BASE + 0x00290) +#define ISP32_YNR_LUMA_RDATA (ISP3X_ISP_BASE + 0x00294) #define ISP3X_FLASH_BASE 0x00000660 #define ISP3X_FLASH_CMD (ISP3X_FLASH_BASE + 0x00000) @@ -202,6 +221,8 @@ #define ISP3X_CCM_ALP_Y7 (ISP3X_CCM_BASE + 0x00040) #define ISP3X_CCM_ALP_Y8 (ISP3X_CCM_BASE + 0x00044) #define ISP3X_CCM_BOUND_BIT (ISP3X_CCM_BASE + 0x00048) +#define ISP32_CCM_ENHANCE0 (ISP3X_CCM_BASE + 0x0004c) +#define ISP32_CCM_ENHANCE1 (ISP3X_CCM_BASE + 0x00050) #define ISP3X_CPROC_BASE 0x00000800 #define ISP3X_CPROC_CTRL (ISP3X_CPROC_BASE + 0x00000) @@ -299,6 +320,30 @@ #define ISP3X_MAIN_RESIZE_HC_OFFS_MI_SHD (ISP3X_MAIN_RESIZE_BASE + 0x00074) #define ISP3X_MAIN_RESIZE_IN_CROP_OFFSET (ISP3X_MAIN_RESIZE_BASE + 0x00078) +#define ISP32_BP_RESIZE_BASE 0x00000E00 +#define ISP32_BP_RESIZE_CTRL (ISP32_BP_RESIZE_BASE + 0x00000) +#define ISP32_BP_RESIZE_SCALE_HY (ISP32_BP_RESIZE_BASE + 0x00004) +#define ISP32_BP_RESIZE_SCALE_HCB (ISP32_BP_RESIZE_BASE + 0x00008) +#define ISP32_BP_RESIZE_SCALE_HCR (ISP32_BP_RESIZE_BASE + 0x0000c) +#define ISP32_BP_RESIZE_SCALE_VY (ISP32_BP_RESIZE_BASE + 0x00010) +#define ISP32_BP_RESIZE_SCALE_VC (ISP32_BP_RESIZE_BASE + 0x00014) +#define ISP32_BP_RESIZE_PHASE_HY (ISP32_BP_RESIZE_BASE + 0x00018) +#define ISP32_BP_RESIZE_PHASE_HC (ISP32_BP_RESIZE_BASE + 0x0001c) +#define ISP32_BP_RESIZE_PHASE_VY (ISP32_BP_RESIZE_BASE + 0x00020) +#define ISP32_BP_RESIZE_PHASE_VC (ISP32_BP_RESIZE_BASE + 0x00024) +#define ISP32_BP_RESIZE_SCALE_LUT_ADDR (ISP32_BP_RESIZE_BASE + 0x00028) +#define ISP32_BP_RESIZE_SCALE_LUT (ISP32_BP_RESIZE_BASE + 0x0002c) +#define ISP32_BP_RESIZE_CTRL_SHD (ISP32_BP_RESIZE_BASE + 0x00030) +#define ISP32_BP_RESIZE_SCALE_HY_SHD (ISP32_BP_RESIZE_BASE + 0x00034) +#define ISP32_BP_RESIZE_SCALE_HCB_SHD (ISP32_BP_RESIZE_BASE + 0x00038) +#define ISP32_BP_RESIZE_SCALE_HCR_SHD (ISP32_BP_RESIZE_BASE + 0x0003c) +#define ISP32_BP_RESIZE_SCALE_VY_SHD (ISP32_BP_RESIZE_BASE + 0x00040) +#define ISP32_BP_RESIZE_SCALE_VC_SHD (ISP32_BP_RESIZE_BASE + 0x00044) +#define ISP32_BP_RESIZE_PHASE_HY_SHD (ISP32_BP_RESIZE_BASE + 0x00048) +#define ISP32_BP_RESIZE_PHASE_HC_SHD (ISP32_BP_RESIZE_BASE + 0x0004c) +#define ISP32_BP_RESIZE_PHASE_VY_SHD (ISP32_BP_RESIZE_BASE + 0x00050) +#define ISP32_BP_RESIZE_PHASE_VC_SHD (ISP32_BP_RESIZE_BASE + 0x00054) + #define ISP3X_SELF_RESIZE_BASE 0x00001000 #define ISP3X_SELF_RESIZE_CTRL (ISP3X_SELF_RESIZE_BASE + 0x00000) #define ISP3X_SELF_RESIZE_SCALE_HY (ISP3X_SELF_RESIZE_BASE + 0x00004) @@ -407,6 +452,7 @@ #define ISP3X_MI_MP_WR_Y_PIC_WIDTH (ISP3X_MI_BASE + 0x001EC) #define ISP3X_MI_MP_WR_Y_PIC_HEIGHT (ISP3X_MI_BASE + 0x001F0) #define ISP3X_MI_MP_WR_Y_PIC_SIZE (ISP3X_MI_BASE + 0x001F4) +#define ISP32_MI_MP_WR_CTRL (ISP3X_MI_BASE + 0x001F8) #define ISP3X_MI_BP_WR_CTRL (ISP3X_MI_BASE + 0x00200) #define ISP3X_MI_BP_WR_Y_BASE (ISP3X_MI_BASE + 0x00204) #define ISP3X_MI_BP_WR_Y_SIZE (ISP3X_MI_BASE + 0x00208) @@ -428,19 +474,73 @@ #define ISP3X_MI_BP_WR_CB_OFFS_CNT_SHD (ISP3X_MI_BASE + 0x00248) #define ISP3X_MI_BP_WR_Y_BASE2 (ISP3X_MI_BASE + 0x0024C) #define ISP3X_MI_BP_WR_CB_BASE2 (ISP3X_MI_BASE + 0x00250) +#define ISP32_MI_MP_WR_Y_END_ADDR (ISP3X_MI_BASE + 0x00260) +#define ISP32_MI_MP_WR_CB_END_ADDR (ISP3X_MI_BASE + 0x00264) +#define ISP32_MI_SP_WR_Y_END_ADDR (ISP3X_MI_BASE + 0x00268) +#define ISP32_MI_SP_WR_CB_END_ADDR (ISP3X_MI_BASE + 0x0026c) +#define ISP32_MI_BP_WR_Y_END_ADDR (ISP3X_MI_BASE + 0x00270) +#define ISP32_MI_BP_WR_CB_END_ADDR (ISP3X_MI_BASE + 0x00274) +#define ISP32_MI_MPDS_WR_Y_END_ADDR (ISP3X_MI_BASE + 0x00278) +#define ISP32_MI_MPDS_WR_CB_END_ADDR (ISP3X_MI_BASE + 0x0027c) +#define ISP32_MI_BPDS_WR_Y_END_ADDR (ISP3X_MI_BASE + 0x00280) +#define ISP32_MI_BPDS_WR_CB_END_ADDR (ISP3X_MI_BASE + 0x00284) +#define ISP32_MI_MPDS_WR_CTRL (ISP3X_MI_BASE + 0x002a0) +#define ISP32_MI_MPDS_WR_Y_BASE (ISP3X_MI_BASE + 0x002a4) +#define ISP32_MI_MPDS_WR_Y_SIZE (ISP3X_MI_BASE + 0x002a8) +#define ISP32_MI_MPDS_WR_Y_OFFS_CNT (ISP3X_MI_BASE + 0x002ac) +#define ISP32_MI_MPDS_WR_Y_OFFS_CNT_START (ISP3X_MI_BASE + 0x002b0) +#define ISP32_MI_MPDS_WR_Y_LLENGTH (ISP3X_MI_BASE + 0x002b4) +#define ISP32_MI_MPDS_WR_Y_PIC_WIDTH (ISP3X_MI_BASE + 0x002b8) +#define ISP32_MI_MPDS_WR_Y_PIC_HEIGHT (ISP3X_MI_BASE + 0x002bc) +#define ISP32_MI_MPDS_WR_Y_PIC_SIZE (ISP3X_MI_BASE + 0x002c0) +#define ISP32_MI_MPDS_WR_CB_BASE (ISP3X_MI_BASE + 0x002c4) +#define ISP32_MI_MPDS_WR_CB_SIZE (ISP3X_MI_BASE + 0x002c8) +#define ISP32_MI_MPDS_WR_CB_OFFS_CNT (ISP3X_MI_BASE + 0x002cc) +#define ISP32_MI_MPDS_WR_CB_OFFS_CNT_START (ISP3X_MI_BASE + 0x002d0) +#define ISP32_MI_MPDS_WR_Y_BASE_SHD (ISP3X_MI_BASE + 0x002d4) +#define ISP32_MI_MPDS_WR_Y_SIZE_SHD (ISP3X_MI_BASE + 0x002d8) +#define ISP32_MI_MPDS_WR_Y_OFFS_CNT_SHD (ISP3X_MI_BASE + 0x002dc) +#define ISP32_MI_MPDS_WR_CB_BASE_SHD (ISP3X_MI_BASE + 0x002e0) +#define ISP32_MI_MPDS_WR_CB_SIZE_SHD (ISP3X_MI_BASE + 0x002e4) +#define ISP32_MI_MPDS_WR_CB_OFFS_CNT_SHD (ISP3X_MI_BASE + 0x002e8) +#define ISP32_MI_BPDS_WR_CTRL (ISP3X_MI_BASE + 0x002f0) +#define ISP32_MI_BPDS_WR_Y_BASE (ISP3X_MI_BASE + 0x002f4) +#define ISP32_MI_BPDS_WR_Y_SIZE (ISP3X_MI_BASE + 0x002f8) +#define ISP32_MI_BPDS_WR_Y_OFFS_CNT (ISP3X_MI_BASE + 0x002fc) +#define ISP32_MI_BPDS_WR_Y_OFFS_CNT_START (ISP3X_MI_BASE + 0x00300) +#define ISP32_MI_BPDS_WR_Y_LLENGTH (ISP3X_MI_BASE + 0x00304) +#define ISP32_MI_BPDS_WR_Y_PIC_WIDTH (ISP3X_MI_BASE + 0x00308) +#define ISP32_MI_BPDS_WR_Y_PIC_HEIGHT (ISP3X_MI_BASE + 0x0030c) +#define ISP32_MI_BPDS_WR_Y_PIC_SIZE (ISP3X_MI_BASE + 0x00310) +#define ISP32_MI_BPDS_WR_CB_BASE (ISP3X_MI_BASE + 0x00314) +#define ISP32_MI_BPDS_WR_CB_SIZE (ISP3X_MI_BASE + 0x00318) +#define ISP32_MI_BPDS_WR_CB_OFFS_CNT (ISP3X_MI_BASE + 0x0031c) +#define ISP32_MI_BPDS_WR_CB_OFFS_CNT_START (ISP3X_MI_BASE + 0x00320) +#define ISP32_MI_BPDS_WR_Y_BASE_SHD (ISP3X_MI_BASE + 0x00324) +#define ISP32_MI_BPDS_WR_Y_SIZE_SHD (ISP3X_MI_BASE + 0x00328) +#define ISP32_MI_BPDS_WR_Y_OFFS_CNT_SHD (ISP3X_MI_BASE + 0x0032c) +#define ISP32_MI_BPDS_WR_CB_BASE_SHD (ISP3X_MI_BASE + 0x00330) +#define ISP32_MI_BPDS_WR_CB_SIZE_SHD (ISP3X_MI_BASE + 0x00334) +#define ISP32_MI_BPDS_WR_CB_OFFS_CNT_SHD (ISP3X_MI_BASE + 0x00338) #define ISP3X_MI_WR_CTRL2 (ISP3X_MI_BASE + 0x00400) #define ISP3X_MI_WR_ID2 (ISP3X_MI_BASE + 0x00404) #define ISP3X_MI_RD_CTRL2 (ISP3X_MI_BASE + 0x00408) #define ISP3X_MI_RD_ID (ISP3X_MI_BASE + 0x0040c) +#define ISP32_MI_WR_CTRL2_SHD (ISP3X_MI_BASE + 0x00410) +#define ISP32_MI_WR_WRAP_CTRL (ISP3X_MI_BASE + 0x00414) +#define ISP32_MI_WR_VFLIP_CTRL (ISP3X_MI_BASE + 0x00418) #define ISP3X_MI_RAW0_RD_BASE (ISP3X_MI_BASE + 0x00470) #define ISP3X_MI_RAW0_RD_LENGTH (ISP3X_MI_BASE + 0x00474) #define ISP3X_MI_RAW0_RD_BASE_SHD (ISP3X_MI_BASE + 0x00478) +#define ISP32_MI_RAW0_RD_SIZE (ISP3X_MI_BASE + 0x0047c) #define ISP3X_MI_RAW1_RD_BASE (ISP3X_MI_BASE + 0x00480) #define ISP3X_MI_RAW1_RD_LENGTH (ISP3X_MI_BASE + 0x00484) #define ISP3X_MI_RAW1_RD_BASE_SHD (ISP3X_MI_BASE + 0x00488) +#define ISP32_MI_RAW1_RD_SIZE (ISP3X_MI_BASE + 0x0048c) #define ISP3X_MI_RAWS_RD_BASE (ISP3X_MI_BASE + 0x00490) #define ISP3X_MI_RAWS_RD_LENGTH (ISP3X_MI_BASE + 0x00494) #define ISP3X_MI_RAWS_RD_BASE_SHD (ISP3X_MI_BASE + 0x00498) +#define ISP32_MI_RAWS_RD_SIZE (ISP3X_MI_BASE + 0x0049c) #define ISP3X_MI_LUT_CAC_RD_BASE (ISP3X_MI_BASE + 0x00530) #define ISP3X_MI_LUT_CAC_RD_H_WSIZE (ISP3X_MI_BASE + 0x00534) #define ISP3X_MI_LUT_CAC_RD_V_SIZE (ISP3X_MI_BASE + 0x00538) @@ -478,6 +578,7 @@ #define ISP3X_MI_BAY3D_CUR_RD_BASE (ISP3X_MI_BASE + 0x005D0) #define ISP3X_MI_BAY3D_CUR_RD_LENGTH (ISP3X_MI_BASE + 0x005D4) #define ISP3X_MI_BAY3D_CUR_RD_BASE_SHD (ISP3X_MI_BASE + 0x005D8) +#define ISP32_MI_BAY3D_CUR_RD_SIZE (ISP3X_MI_BASE + 0x005DC) #define ISP3X_MI_BAY3D_DS_WR_BASE (ISP3X_MI_BASE + 0x005E0) #define ISP3X_MI_BAY3D_DS_WR_SIZE (ISP3X_MI_BASE + 0x005E4) #define ISP3X_MI_BAY3D_DS_WR_LENGTH (ISP3X_MI_BASE + 0x005E8) @@ -503,6 +604,7 @@ #define ISP3X_CSI2RX_CTRL0 (ISP3X_CSI2RX_BASE + 0x00000) #define ISP3X_CSI2RX_CTRL1 (ISP3X_CSI2RX_BASE + 0x00004) #define ISP3X_CSI2RX_CTRL2 (ISP3X_CSI2RX_BASE + 0x00008) +#define ISP32_CSI2RX_CTRL3 (ISP3X_CSI2RX_BASE + 0x0000c) #define ISP3X_CSI2RX_CSI2_RESETN (ISP3X_CSI2RX_BASE + 0x00010) #define ISP3X_CSI2RX_PHY_STATE_RO (ISP3X_CSI2RX_BASE + 0x00014) #define ISP3X_CSI2RX_DATA_IDS_1 (ISP3X_CSI2RX_BASE + 0x00018) @@ -574,6 +676,17 @@ #define ISP3X_DEBAYER_G_INTERP_FILTER2 (ISP3X_DEBAYER_BASE + 0x0000c) #define ISP3X_DEBAYER_OFFSET (ISP3X_DEBAYER_BASE + 0x00010) #define ISP3X_DEBAYER_C_FILTER (ISP3X_DEBAYER_BASE + 0x00014) +#define ISP32_DEBAYER_G_INTERP_OFFSET (ISP3X_DEBAYER_BASE + 0x00010) +#define ISP32_DEBAYER_G_FILTER_OFFSET (ISP3X_DEBAYER_BASE + 0x00014) +#define ISP32_DEBAYER_C_FILTER_GUIDE_GAUS (ISP3X_DEBAYER_BASE + 0x00018) +#define ISP32_DEBAYER_C_FILTER_CE_GAUS (ISP3X_DEBAYER_BASE + 0x0001c) +#define ISP32_DEBAYER_C_FILTER_ALPHA_GAUS (ISP3X_DEBAYER_BASE + 0x00020) +#define ISP32_DEBAYER_C_FILTER_LOG_OFFSET (ISP3X_DEBAYER_BASE + 0x00024) +#define ISP32_DEBAYER_C_FILTER_ALPHA (ISP3X_DEBAYER_BASE + 0x00028) +#define ISP32_DEBAYER_C_FILTER_EDGE (ISP3X_DEBAYER_BASE + 0x0002c) +#define ISP32_DEBAYER_C_FILTER_IIR_0 (ISP3X_DEBAYER_BASE + 0x00030) +#define ISP32_DEBAYER_C_FILTER_IIR_1 (ISP3X_DEBAYER_BASE + 0x00034) +#define ISP32_DEBAYER_C_FILTER_BF (ISP3X_DEBAYER_BASE + 0x00038) #define ISP3X_CAC_BASE 0x00002600 #define ISP3X_CAC_CTRL (ISP3X_CAC_BASE + 0x00000) @@ -590,6 +703,8 @@ #define ISP3X_CAC_STRENGTH8 (ISP3X_CAC_BASE + 0x0002C) #define ISP3X_CAC_STRENGTH9 (ISP3X_CAC_BASE + 0x00030) #define ISP3X_CAC_STRENGTH10 (ISP3X_CAC_BASE + 0x00034) +#define ISP32_CAC_FLAT_THED (ISP3X_CAC_BASE + 0x00038) +#define ISP32_CAC_OFFSET (ISP3X_CAC_BASE + 0x0003c) #define ISP3X_CAC_PSF_CFG0 (ISP3X_CAC_BASE + 0x00040) #define ISP3X_CAC_PSF_CFG1 (ISP3X_CAC_BASE + 0x00044) #define ISP3X_CAC_PSF_CFG2 (ISP3X_CAC_BASE + 0x00048) @@ -607,6 +722,11 @@ #define ISP3X_CAC_PSF_CFG14 (ISP3X_CAC_BASE + 0x00078) #define ISP3X_CAC_PSF_CFG15 (ISP3X_CAC_BASE + 0x0007C) #define ISP3X_CAC_RO_CNT (ISP3X_CAC_BASE + 0x00080) +#define ISP32_CAC_EXPO_THED_B (ISP3X_CAC_BASE + 0x00080) +#define ISP32_CAC_EXPO_THED_R (ISP3X_CAC_BASE + 0x00084) +#define ISP32_CAC_EXPO_ADJ_B (ISP3X_CAC_BASE + 0x00088) +#define ISP32_CAC_EXPO_ADJ_R (ISP3X_CAC_BASE + 0x0008c) +#define ISP32_CAC_RO_CNT (ISP3X_CAC_BASE + 0x000fc) #define ISP3X_YNR_BASE 0x00002700 #define ISP3X_YNR_GLOBAL_CTRL (ISP3X_YNR_BASE + 0x00000) @@ -657,23 +777,42 @@ #define ISP3X_YNR_RNR_STRENGTH8B (ISP3X_YNR_BASE + 0x000d8) #define ISP3X_YNR_RNR_STRENGTHCF (ISP3X_YNR_BASE + 0x000dc) #define ISP3X_YNR_RNR_STRENGTH16 (ISP3X_YNR_BASE + 0x000e0) +#define ISP32_YNR_NLM_SIGMA_GAIN (ISP3X_YNR_BASE + 0x000f0) +#define ISP32_YNR_NLM_COE (ISP3X_YNR_BASE + 0x000f4) +#define ISP32_YNR_NLM_WEIGHT (ISP3X_YNR_BASE + 0x000f8) +#define ISP32_YNR_NLM_NR_WEIGHT (ISP3X_YNR_BASE + 0x000fc) #define ISP3X_CNR_BASE 0x00002800 #define ISP3X_CNR_CTRL (ISP3X_CNR_BASE + 0x00000) #define ISP3X_CNR_EXGAIN (ISP3X_CNR_BASE + 0x00004) #define ISP3X_CNR_GAIN_PARA (ISP3X_CNR_BASE + 0x00008) +#define ISP32_CNR_THUMB1 (ISP3X_CNR_BASE + 0x00008) #define ISP3X_CNR_GAIN_UV_PARA (ISP3X_CNR_BASE + 0x0000c) +#define ISP32_CNR_THUMB_BF_RATIO (ISP3X_CNR_BASE + 0x0000c) #define ISP3X_CNR_LMED3 (ISP3X_CNR_BASE + 0x00010) +#define ISP32_CNR_LBF_WEITD (ISP3X_CNR_BASE + 0x00010) #define ISP3X_CNR_LBF5_GAIN (ISP3X_CNR_BASE + 0x00014) +#define ISP32_CNR_IIR_PARA1 (ISP3X_CNR_BASE + 0x00014) #define ISP3X_CNR_LBF5_WEITD0_3 (ISP3X_CNR_BASE + 0x00018) +#define ISP32_CNR_IIR_PARA2 (ISP3X_CNR_BASE + 0x00018) #define ISP3X_CNR_LBF5_WEITD4 (ISP3X_CNR_BASE + 0x0001c) +#define ISP32_CNR_GAUS_COE1 (ISP3X_CNR_BASE + 0x0001c) #define ISP3X_CNR_HMED3 (ISP3X_CNR_BASE + 0x00020) +#define ISP32_CNR_GAUS_COE2 (ISP3X_CNR_BASE + 0x00020) #define ISP3X_CNR_HBF5 (ISP3X_CNR_BASE + 0x00024) +#define ISP32_CNR_GAUS_RATIO (ISP3X_CNR_BASE + 0x00024) #define ISP3X_CNR_LBF3 (ISP3X_CNR_BASE + 0x00028) +#define ISP32_CNR_BF_PARA1 (ISP3X_CNR_BASE + 0x00028) +#define ISP32_CNR_BF_PARA2 (ISP3X_CNR_BASE + 0x0002C) #define ISP3X_CNR_SIGMA0 (ISP3X_CNR_BASE + 0x0002C) #define ISP3X_CNR_SIGMA1 (ISP3X_CNR_BASE + 0x00030) #define ISP3X_CNR_SIGMA2 (ISP3X_CNR_BASE + 0x00034) #define ISP3X_CNR_SIGMA3 (ISP3X_CNR_BASE + 0x00038) +#define ISP32_CNR_SIGMA0 (ISP3X_CNR_BASE + 0x00030) +#define ISP32_CNR_SIGMA1 (ISP3X_CNR_BASE + 0x00034) +#define ISP32_CNR_SIGMA2 (ISP3X_CNR_BASE + 0x00038) +#define ISP32_CNR_SIGMA3 (ISP3X_CNR_BASE + 0x0003c) +#define ISP32_CNR_IIR_GLOBAL_GAIN (ISP3X_CNR_BASE + 0x00040) #define ISP3X_SHARP_BASE 0x00002900 #define ISP3X_SHARP_EN (ISP3X_SHARP_BASE + 0x00000) @@ -696,11 +835,28 @@ #define ISP3X_SHARP_BF_COEF (ISP3X_SHARP_BASE + 0x00044) #define ISP3X_SHARP_GAUS_COEF0 (ISP3X_SHARP_BASE + 0x00048) #define ISP3X_SHARP_GAUS_COEF1 (ISP3X_SHARP_BASE + 0x0004C) +#define ISP32_SHARP_GAIN (ISP3X_SHARP_BASE + 0x00050) +#define ISP32_SHARP_GAIN_ADJUST0 (ISP3X_SHARP_BASE + 0x00054) +#define ISP32_SHARP_GAIN_ADJUST1 (ISP3X_SHARP_BASE + 0x00058) +#define ISP32_SHARP_GAIN_ADJUST2 (ISP3X_SHARP_BASE + 0x0005c) +#define ISP32_SHARP_GAIN_ADJUST3 (ISP3X_SHARP_BASE + 0x00060) +#define ISP32_SHARP_GAIN_ADJUST4 (ISP3X_SHARP_BASE + 0x00064) +#define ISP32_SHARP_GAIN_ADJUST5 (ISP3X_SHARP_BASE + 0x00068) +#define ISP32_SHARP_GAIN_ADJUST6 (ISP3X_SHARP_BASE + 0x0006c) +#define ISP32_SHARP_CENTER (ISP3X_SHARP_BASE + 0x00070) +#define ISP32_SHARP_GAIN_DIS_STRENGTH0 (ISP3X_SHARP_BASE + 0x00074) +#define ISP32_SHARP_GAIN_DIS_STRENGTH1 (ISP3X_SHARP_BASE + 0x00078) +#define ISP32_SHARP_GAIN_DIS_STRENGTH2 (ISP3X_SHARP_BASE + 0x0007c) +#define ISP32_SHARP_GAIN_DIS_STRENGTH3 (ISP3X_SHARP_BASE + 0x00080) +#define ISP32_SHARP_GAIN_DIS_STRENGTH4 (ISP3X_SHARP_BASE + 0x00084) +#define ISP32_SHARP_GAIN_DIS_STRENGTH5 (ISP3X_SHARP_BASE + 0x00088) +#define ISP32_SHARP_TEXTURE (ISP3X_SHARP_BASE + 0x0008c) #define ISP3X_BAY3D_BASE 0x00002C00 #define ISP3X_BAY3D_CTRL (ISP3X_BAY3D_BASE + 0x00000) #define ISP3X_BAY3D_KALRATIO (ISP3X_BAY3D_BASE + 0x00004) #define ISP3X_BAY3D_GLBPK2 (ISP3X_BAY3D_BASE + 0x00008) +#define ISP32_BAY3D_CTRL1 (ISP3X_BAY3D_BASE + 0x0000c) #define ISP3X_BAY3D_WGTLMT (ISP3X_BAY3D_BASE + 0x00010) #define ISP3X_BAY3D_SIG0_X0 (ISP3X_BAY3D_BASE + 0x00014) #define ISP3X_BAY3D_SIG0_X1 (ISP3X_BAY3D_BASE + 0x00018) @@ -753,6 +909,13 @@ #define ISP3X_BAY3D_RO_FIFO_DS (ISP3X_BAY3D_BASE + 0x000D8) #define ISP3X_BAY3D_RO_FIFO_STATE (ISP3X_BAY3D_BASE + 0x000DC) #define ISP3X_BAY3D_IN_IRQ_LINECNT (ISP3X_BAY3D_BASE + 0x000E0) +#define ISP32_BAY3D_HISIGRAT (ISP3X_BAY3D_BASE + 0x000E4) +#define ISP32_BAY3D_HISIGOFF (ISP3X_BAY3D_BASE + 0x000E8) +#define ISP32_BAY3D_LOSIG (ISP3X_BAY3D_BASE + 0x000EC) +#define ISP32_BAY3D_SIGPK (ISP3X_BAY3D_BASE + 0x000F0) +#define ISP32_BAY3D_SIGGAUS (ISP3X_BAY3D_BASE + 0x000F4) +#define ISP32_BAY3D_WRMI (ISP3X_BAY3D_BASE + 0x000F8) +#define ISP32_BAY3D_RDMI (ISP3X_BAY3D_BASE + 0x000FC) #define ISP3X_GIC_BASE 0x00002F00 #define ISP3X_GIC_CONTROL (ISP3X_GIC_BASE + 0x00000) @@ -795,6 +958,13 @@ #define ISP3X_BLS1_B_FIXED (ISP3X_BLS_BASE + 0x0004c) #define ISP3X_BLS1_C_FIXED (ISP3X_BLS_BASE + 0x00050) #define ISP3X_BLS1_D_FIXED (ISP3X_BLS_BASE + 0x00054) +#define ISP32_BLS2_A_FIXED (ISP3X_BLS_BASE + 0x00058) +#define ISP32_BLS2_B_FIXED (ISP3X_BLS_BASE + 0x0005c) +#define ISP32_BLS2_C_FIXED (ISP3X_BLS_BASE + 0x00060) +#define ISP32_BLS2_D_FIXED (ISP3X_BLS_BASE + 0x00064) +#define ISP32_BLS_ISP_OB_OFFSET (ISP3X_BLS_BASE + 0x00068) +#define ISP32_BLS_ISP_OB_PREDGAIN (ISP3X_BLS_BASE + 0x0006c) +#define ISP32_BLS_ISP_OB_MAX (ISP3X_BLS_BASE + 0x00070) #define ISP3X_DPCC0_BASE 0x00003400 #define ISP3X_DPCC1_BASE 0x00003500 @@ -970,6 +1140,7 @@ #define ISP3X_HDRMGE_OVER_Y14 (ISP3X_HDRMGE_BASE + 0x000a8) #define ISP3X_HDRMGE_OVER_Y15 (ISP3X_HDRMGE_BASE + 0x000ac) #define ISP3X_HDRMGE_OVER_Y16 (ISP3X_HDRMGE_BASE + 0x000b0) +#define ISP32_HDRMGE_EACH_GAIN (ISP3X_HDRMGE_BASE + 0x000b4) #define ISP3X_DRC_BASE 0x00003900 #define ISP3X_DRC_CTRL0 (ISP3X_DRC_BASE + 0x00000) @@ -1008,6 +1179,8 @@ #define ISP3X_DRC_SCALE_Y7 (ISP3X_DRC_BASE + 0x00084) #define ISP3X_DRC_SCALE_Y8 (ISP3X_DRC_BASE + 0x00088) #define ISP3X_DRC_IIRWG_GAIN (ISP3X_DRC_BASE + 0x0008c) +#define ISP32_DRC_LUM3X2_CTRL (ISP3X_DRC_BASE + 0x00090) +#define ISP32_DRC_LUM3X2_GAS (ISP3X_DRC_BASE + 0x00094) #define ISP3X_BAYNR_BASE 0x00003A00 #define ISP3X_BAYNR_CTRL (ISP3X_BAYNR_BASE + 0x00000) @@ -1035,9 +1208,31 @@ #define ISP3X_BAYNR_WRIT_D (ISP3X_BAYNR_BASE + 0x00058) #define ISP3X_BAYNR_LG_OFF (ISP3X_BAYNR_BASE + 0x0005c) #define ISP3X_BAYNR_DAT_MAX (ISP3X_BAYNR_BASE + 0x00060) +#define ISP32_BAYNR_SIGOFF (ISP3X_BAYNR_BASE + 0x00064) +#define ISP32_BAYNR_GAINX03 (ISP3X_BAYNR_BASE + 0x00068) +#define ISP32_BAYNR_GAINX47 (ISP3X_BAYNR_BASE + 0x0006c) +#define ISP32_BAYNR_GAINX811 (ISP3X_BAYNR_BASE + 0x00070) +#define ISP32_BAYNR_GAINX1215 (ISP3X_BAYNR_BASE + 0x00074) +#define ISP32_BAYNR_GAINY01 (ISP3X_BAYNR_BASE + 0x00078) +#define ISP32_BAYNR_GAINX23 (ISP3X_BAYNR_BASE + 0x0007c) +#define ISP32_BAYNR_GAINX45 (ISP3X_BAYNR_BASE + 0x00080) +#define ISP32_BAYNR_GAINX67 (ISP3X_BAYNR_BASE + 0x00084) +#define ISP32_BAYNR_GAINX89 (ISP3X_BAYNR_BASE + 0x00088) +#define ISP32_BAYNR_GAINX1011 (ISP3X_BAYNR_BASE + 0x0008c) +#define ISP32_BAYNR_GAINX1213 (ISP3X_BAYNR_BASE + 0x00090) +#define ISP32_BAYNR_GAINX1415 (ISP3X_BAYNR_BASE + 0x00094) #define ISP3X_LDCH_BASE 0x00003B00 #define ISP3X_LDCH_STS (ISP3X_LDCH_BASE + 0x00000) +#define ISP32_LDCH_BIC_TABLE0 (ISP3X_LDCH_BASE + 0x00004) +#define ISP32_LDCH_BIC_TABLE1 (ISP3X_LDCH_BASE + 0x00008) +#define ISP32_LDCH_BIC_TABLE2 (ISP3X_LDCH_BASE + 0x0000c) +#define ISP32_LDCH_BIC_TABLE3 (ISP3X_LDCH_BASE + 0x00010) +#define ISP32_LDCH_BIC_TABLE4 (ISP3X_LDCH_BASE + 0x00014) +#define ISP32_LDCH_BIC_TABLE5 (ISP3X_LDCH_BASE + 0x00018) +#define ISP32_LDCH_BIC_TABLE6 (ISP3X_LDCH_BASE + 0x0001c) +#define ISP32_LDCH_BIC_TABLE7 (ISP3X_LDCH_BASE + 0x00020) +#define ISP32_LDCH_BIC_TABLE8 (ISP3X_LDCH_BASE + 0x00024) #define ISP3X_DHAZ_BASE 0x00003C00 #define ISP3X_DHAZ_CTRL (ISP3X_DHAZ_BASE + 0x00000) @@ -1137,6 +1332,12 @@ #define ISP3X_DHAZ_HIST_REG29 (ISP3X_DHAZ_BASE + 0x00184) #define ISP3X_DHAZ_HIST_REG30 (ISP3X_DHAZ_BASE + 0x00188) #define ISP3X_DHAZ_HIST_REG31 (ISP3X_DHAZ_BASE + 0x0018C) +#define ISP32_DHAZ_ENH_LUMA0 (ISP3X_DHAZ_BASE + 0x00190) +#define ISP32_DHAZ_ENH_LUMA1 (ISP3X_DHAZ_BASE + 0x00194) +#define ISP32_DHAZ_ENH_LUMA2 (ISP3X_DHAZ_BASE + 0x00198) +#define ISP32_DHAZ_ENH_LUMA3 (ISP3X_DHAZ_BASE + 0x0019c) +#define ISP32_DHAZ_ENH_LUMA4 (ISP3X_DHAZ_BASE + 0x001a0) +#define ISP32_DHAZ_ENH_LUMA5 (ISP3X_DHAZ_BASE + 0x001a4) #define ISP3X_3DLUT_BASE 0x00003E00 #define ISP3X_3DLUT_CTRL (ISP3X_3DLUT_BASE + 0x00000) @@ -1266,276 +1467,290 @@ #define ISP3X_RAWAF_V_FIR_COE0 (ISP3X_RAWAF_BASE + 0x000C4) #define ISP3X_RAWAF_V_FIR_COE1 (ISP3X_RAWAF_BASE + 0x000C8) #define ISP3X_RAWAF_V_FIR_COE2 (ISP3X_RAWAF_BASE + 0x000CC) +#define ISP32_RAWAF_V_FIR_COE0 (ISP3X_RAWAF_BASE + 0x000b0) +#define ISP32_RAWAF_V_FIR_COE1 (ISP3X_RAWAF_BASE + 0x000b4) +#define ISP32_RAWAF_V_FIR_COE2 (ISP3X_RAWAF_BASE + 0x000b8) +#define ISP32_RAWAF_GAUS_COE03 (ISP3X_RAWAF_BASE + 0x000c0) +#define ISP32_RAWAF_GAUS_COE47 (ISP3X_RAWAF_BASE + 0x000c4) +#define ISP32_RAWAF_GAUS_COE8 (ISP3X_RAWAF_BASE + 0x000c8) #define ISP3X_RAWAF_HIGHLIT_THRESH (ISP3X_RAWAF_BASE + 0x000D0) #define ISP3X_RAWAF_HIGHLIT_CNT_WINB (ISP3X_RAWAF_BASE + 0x000D8) #define ISP3X_RAWAF_RAM_DATA (ISP3X_RAWAF_BASE + 0x000E0) -#define ISP3X_RAWAWB_BASE 0x00005000 -#define ISP3X_RAWAWB_CTRL (ISP3X_RAWAWB_BASE + 0x0000) -#define ISP3X_RAWAWB_BLK_CTRL (ISP3X_RAWAWB_BASE + 0x0004) -#define ISP3X_RAWAWB_WIN_OFFS (ISP3X_RAWAWB_BASE + 0x0008) -#define ISP3X_RAWAWB_WIN_SIZE (ISP3X_RAWAWB_BASE + 0x000c) -#define ISP3X_RAWAWB_LIMIT_RG_MAX (ISP3X_RAWAWB_BASE + 0x0010) -#define ISP3X_RAWAWB_LIMIT_BY_MAX (ISP3X_RAWAWB_BASE + 0x0014) -#define ISP3X_RAWAWB_LIMIT_RG_MIN (ISP3X_RAWAWB_BASE + 0x0018) -#define ISP3X_RAWAWB_LIMIT_BY_MIN (ISP3X_RAWAWB_BASE + 0x001c) -#define ISP3X_RAWAWB_WEIGHT_CURVE_CTRL (ISP3X_RAWAWB_BASE + 0x0020) -#define ISP3X_RAWAWB_YWEIGHT_CURVE_XCOOR03 (ISP3X_RAWAWB_BASE + 0x0024) -#define ISP3X_RAWAWB_YWEIGHT_CURVE_XCOOR47 (ISP3X_RAWAWB_BASE + 0x0028) -#define ISP3X_RAWAWB_YWEIGHT_CURVE_XCOOR8 (ISP3X_RAWAWB_BASE + 0x002c) -#define ISP3X_RAWAWB_YWEIGHT_CURVE_YCOOR03 (ISP3X_RAWAWB_BASE + 0x0030) -#define ISP3X_RAWAWB_YWEIGHT_CURVE_YCOOR47 (ISP3X_RAWAWB_BASE + 0x0034) -#define ISP3X_RAWAWB_YWEIGHT_CURVE_YCOOR8 (ISP3X_RAWAWB_BASE + 0x0038) -#define ISP3X_RAWAWB_PRE_WBGAIN_INV (ISP3X_RAWAWB_BASE + 0x003c) -#define ISP3X_RAWAWB_UV_DETC_VERTEX0_0 (ISP3X_RAWAWB_BASE + 0x0040) -#define ISP3X_RAWAWB_UV_DETC_VERTEX1_0 (ISP3X_RAWAWB_BASE + 0x0044) -#define ISP3X_RAWAWB_UV_DETC_VERTEX2_0 (ISP3X_RAWAWB_BASE + 0x0048) -#define ISP3X_RAWAWB_UV_DETC_VERTEX3_0 (ISP3X_RAWAWB_BASE + 0x004c) -#define ISP3X_RAWAWB_UV_DETC_ISLOPE01_0 (ISP3X_RAWAWB_BASE + 0x0050) -#define ISP3X_RAWAWB_UV_DETC_ISLOPE12_0 (ISP3X_RAWAWB_BASE + 0x0054) -#define ISP3X_RAWAWB_UV_DETC_ISLOPE23_0 (ISP3X_RAWAWB_BASE + 0x0058) -#define ISP3X_RAWAWB_UV_DETC_ISLOPE30_0 (ISP3X_RAWAWB_BASE + 0x005c) -#define ISP3X_RAWAWB_UV_DETC_VERTEX0_1 (ISP3X_RAWAWB_BASE + 0x0060) -#define ISP3X_RAWAWB_UV_DETC_VERTEX1_1 (ISP3X_RAWAWB_BASE + 0x0064) -#define ISP3X_RAWAWB_UV_DETC_VERTEX2_1 (ISP3X_RAWAWB_BASE + 0x0068) -#define ISP3X_RAWAWB_UV_DETC_VERTEX3_1 (ISP3X_RAWAWB_BASE + 0x006c) -#define ISP3X_RAWAWB_UV_DETC_ISLOPE01_1 (ISP3X_RAWAWB_BASE + 0x0070) -#define ISP3X_RAWAWB_UV_DETC_ISLOPE12_1 (ISP3X_RAWAWB_BASE + 0x0074) -#define ISP3X_RAWAWB_UV_DETC_ISLOPE23_1 (ISP3X_RAWAWB_BASE + 0x0078) -#define ISP3X_RAWAWB_UV_DETC_ISLOPE30_1 (ISP3X_RAWAWB_BASE + 0x007c) -#define ISP3X_RAWAWB_UV_DETC_VERTEX0_2 (ISP3X_RAWAWB_BASE + 0x0080) -#define ISP3X_RAWAWB_UV_DETC_VERTEX1_2 (ISP3X_RAWAWB_BASE + 0x0084) -#define ISP3X_RAWAWB_UV_DETC_VERTEX2_2 (ISP3X_RAWAWB_BASE + 0x0088) -#define ISP3X_RAWAWB_UV_DETC_VERTEX3_2 (ISP3X_RAWAWB_BASE + 0x008c) -#define ISP3X_RAWAWB_UV_DETC_ISLOPE01_2 (ISP3X_RAWAWB_BASE + 0x0090) -#define ISP3X_RAWAWB_UV_DETC_ISLOPE12_2 (ISP3X_RAWAWB_BASE + 0x0094) -#define ISP3X_RAWAWB_UV_DETC_ISLOPE23_2 (ISP3X_RAWAWB_BASE + 0x0098) -#define ISP3X_RAWAWB_UV_DETC_ISLOPE30_2 (ISP3X_RAWAWB_BASE + 0x009c) -#define ISP3X_RAWAWB_UV_DETC_VERTEX0_3 (ISP3X_RAWAWB_BASE + 0x00a0) -#define ISP3X_RAWAWB_UV_DETC_VERTEX1_3 (ISP3X_RAWAWB_BASE + 0x00a4) -#define ISP3X_RAWAWB_UV_DETC_VERTEX2_3 (ISP3X_RAWAWB_BASE + 0x00a8) -#define ISP3X_RAWAWB_UV_DETC_VERTEX3_3 (ISP3X_RAWAWB_BASE + 0x00ac) -#define ISP3X_RAWAWB_UV_DETC_ISLOPE01_3 (ISP3X_RAWAWB_BASE + 0x00b0) -#define ISP3X_RAWAWB_UV_DETC_ISLOPE12_3 (ISP3X_RAWAWB_BASE + 0x00b4) -#define ISP3X_RAWAWB_UV_DETC_ISLOPE23_3 (ISP3X_RAWAWB_BASE + 0x00b8) -#define ISP3X_RAWAWB_UV_DETC_ISLOPE30_3 (ISP3X_RAWAWB_BASE + 0x00bc) -#define ISP3X_RAWAWB_UV_DETC_VERTEX0_4 (ISP3X_RAWAWB_BASE + 0x00c0) -#define ISP3X_RAWAWB_UV_DETC_VERTEX1_4 (ISP3X_RAWAWB_BASE + 0x00c4) -#define ISP3X_RAWAWB_UV_DETC_VERTEX2_4 (ISP3X_RAWAWB_BASE + 0x00c8) -#define ISP3X_RAWAWB_UV_DETC_VERTEX3_4 (ISP3X_RAWAWB_BASE + 0x00cc) -#define ISP3X_RAWAWB_UV_DETC_ISLOPE01_4 (ISP3X_RAWAWB_BASE + 0x00d0) -#define ISP3X_RAWAWB_UV_DETC_ISLOPE12_4 (ISP3X_RAWAWB_BASE + 0x00d4) -#define ISP3X_RAWAWB_UV_DETC_ISLOPE23_4 (ISP3X_RAWAWB_BASE + 0x00d8) -#define ISP3X_RAWAWB_UV_DETC_ISLOPE30_4 (ISP3X_RAWAWB_BASE + 0x00dc) -#define ISP3X_RAWAWB_UV_DETC_VERTEX0_5 (ISP3X_RAWAWB_BASE + 0x00e0) -#define ISP3X_RAWAWB_UV_DETC_VERTEX1_5 (ISP3X_RAWAWB_BASE + 0x00e4) -#define ISP3X_RAWAWB_UV_DETC_VERTEX2_5 (ISP3X_RAWAWB_BASE + 0x00e8) -#define ISP3X_RAWAWB_UV_DETC_VERTEX3_5 (ISP3X_RAWAWB_BASE + 0x00ec) -#define ISP3X_RAWAWB_UV_DETC_ISLOPE01_5 (ISP3X_RAWAWB_BASE + 0x00f0) -#define ISP3X_RAWAWB_UV_DETC_ISLOPE10_5 (ISP3X_RAWAWB_BASE + 0x00f4) -#define ISP3X_RAWAWB_UV_DETC_ISLOPE23_5 (ISP3X_RAWAWB_BASE + 0x00f8) -#define ISP3X_RAWAWB_UV_DETC_ISLOPE30_5 (ISP3X_RAWAWB_BASE + 0x00fc) -#define ISP3X_RAWAWB_UV_DETC_VERTEX0_6 (ISP3X_RAWAWB_BASE + 0x0100) -#define ISP3X_RAWAWB_UV_DETC_VERTEX1_6 (ISP3X_RAWAWB_BASE + 0x0104) -#define ISP3X_RAWAWB_UV_DETC_VERTEX2_6 (ISP3X_RAWAWB_BASE + 0x0108) -#define ISP3X_RAWAWB_UV_DETC_VERTEX3_6 (ISP3X_RAWAWB_BASE + 0x010c) -#define ISP3X_RAWAWB_UV_DETC_ISLOPE01_6 (ISP3X_RAWAWB_BASE + 0x0110) -#define ISP3X_RAWAWB_UV_DETC_ISLOPE10_6 (ISP3X_RAWAWB_BASE + 0x0114) -#define ISP3X_RAWAWB_UV_DETC_ISLOPE23_6 (ISP3X_RAWAWB_BASE + 0x0118) -#define ISP3X_RAWAWB_UV_DETC_ISLOPE30_6 (ISP3X_RAWAWB_BASE + 0x011c) -#define ISP3X_RAWAWB_YUV_RGB2ROTY_0 (ISP3X_RAWAWB_BASE + 0x0120) -#define ISP3X_RAWAWB_YUV_RGB2ROTY_1 (ISP3X_RAWAWB_BASE + 0x0124) -#define ISP3X_RAWAWB_YUV_RGB2ROTU_0 (ISP3X_RAWAWB_BASE + 0x0128) -#define ISP3X_RAWAWB_YUV_RGB2ROTU_1 (ISP3X_RAWAWB_BASE + 0x012c) -#define ISP3X_RAWAWB_YUV_RGB2ROTV_0 (ISP3X_RAWAWB_BASE + 0x0130) -#define ISP3X_RAWAWB_YUV_RGB2ROTV_1 (ISP3X_RAWAWB_BASE + 0x0134) -#define ISP3X_RAWAWB_YUV_X_COOR_Y_0 (ISP3X_RAWAWB_BASE + 0x0140) -#define ISP3X_RAWAWB_YUV_X_COOR_U_0 (ISP3X_RAWAWB_BASE + 0x0144) -#define ISP3X_RAWAWB_YUV_X_COOR_V_0 (ISP3X_RAWAWB_BASE + 0x0148) -#define ISP3X_RAWAWB_YUV_X1X2_DIS_0 (ISP3X_RAWAWB_BASE + 0x014c) -#define ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_0 (ISP3X_RAWAWB_BASE + 0x0150) -#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_0 (ISP3X_RAWAWB_BASE + 0x0154) -#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_0 (ISP3X_RAWAWB_BASE + 0x0158) -#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_0 (ISP3X_RAWAWB_BASE + 0x015c) -#define ISP3X_RAWAWB_YUV_X_COOR_Y_1 (ISP3X_RAWAWB_BASE + 0x0160) -#define ISP3X_RAWAWB_YUV_X_COOR_U_1 (ISP3X_RAWAWB_BASE + 0x0164) -#define ISP3X_RAWAWB_YUV_X_COOR_V_1 (ISP3X_RAWAWB_BASE + 0x0168) -#define ISP3X_RAWAWB_YUV_X1X2_DIS_1 (ISP3X_RAWAWB_BASE + 0x016c) -#define ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_1 (ISP3X_RAWAWB_BASE + 0x0170) -#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_1 (ISP3X_RAWAWB_BASE + 0x0174) -#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_1 (ISP3X_RAWAWB_BASE + 0x0178) -#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_1 (ISP3X_RAWAWB_BASE + 0x017c) -#define ISP3X_RAWAWB_YUV_X_COOR_Y_2 (ISP3X_RAWAWB_BASE + 0x0180) -#define ISP3X_RAWAWB_YUV_X_COOR_U_2 (ISP3X_RAWAWB_BASE + 0x0184) -#define ISP3X_RAWAWB_YUV_X_COOR_V_2 (ISP3X_RAWAWB_BASE + 0x0188) -#define ISP3X_RAWAWB_YUV_X1X2_DIS_2 (ISP3X_RAWAWB_BASE + 0x018c) -#define ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_2 (ISP3X_RAWAWB_BASE + 0x0190) -#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_2 (ISP3X_RAWAWB_BASE + 0x0194) -#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_2 (ISP3X_RAWAWB_BASE + 0x0198) -#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_2 (ISP3X_RAWAWB_BASE + 0x019c) -#define ISP3X_RAWAWB_YUV_X_COOR_Y_3 (ISP3X_RAWAWB_BASE + 0x01a0) -#define ISP3X_RAWAWB_YUV_X_COOR_U_3 (ISP3X_RAWAWB_BASE + 0x01a4) -#define ISP3X_RAWAWB_YUV_X_COOR_V_3 (ISP3X_RAWAWB_BASE + 0x01a8) -#define ISP3X_RAWAWB_YUV_X1X2_DIS_3 (ISP3X_RAWAWB_BASE + 0x01ac) -#define ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_3 (ISP3X_RAWAWB_BASE + 0x01b0) -#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_3 (ISP3X_RAWAWB_BASE + 0x01b4) -#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_3 (ISP3X_RAWAWB_BASE + 0x01b8) -#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_3 (ISP3X_RAWAWB_BASE + 0x01bc) -#define ISP3X_RAWAWB_RGB2XY_WT01 (ISP3X_RAWAWB_BASE + 0x01fc) -#define ISP3X_RAWAWB_RGB2XY_WT2 (ISP3X_RAWAWB_BASE + 0x0200) -#define ISP3X_RAWAWB_RGB2XY_MAT0_XY (ISP3X_RAWAWB_BASE + 0x0204) -#define ISP3X_RAWAWB_RGB2XY_MAT1_XY (ISP3X_RAWAWB_BASE + 0x0208) -#define ISP3X_RAWAWB_RGB2XY_MAT2_XY (ISP3X_RAWAWB_BASE + 0x020c) -#define ISP3X_RAWAWB_XY_DETC_NOR_X_0 (ISP3X_RAWAWB_BASE + 0x0210) -#define ISP3X_RAWAWB_XY_DETC_NOR_Y_0 (ISP3X_RAWAWB_BASE + 0x0214) -#define ISP3X_RAWAWB_XY_DETC_BIG_X_0 (ISP3X_RAWAWB_BASE + 0x0218) -#define ISP3X_RAWAWB_XY_DETC_BIG_Y_0 (ISP3X_RAWAWB_BASE + 0x021c) -#define ISP3X_RAWAWB_XY_DETC_NOR_X_1 (ISP3X_RAWAWB_BASE + 0x0228) -#define ISP3X_RAWAWB_XY_DETC_NOR_Y_1 (ISP3X_RAWAWB_BASE + 0x022c) -#define ISP3X_RAWAWB_XY_DETC_BIG_X_1 (ISP3X_RAWAWB_BASE + 0x0230) -#define ISP3X_RAWAWB_XY_DETC_BIG_Y_1 (ISP3X_RAWAWB_BASE + 0x0234) -#define ISP3X_RAWAWB_XY_DETC_NOR_X_2 (ISP3X_RAWAWB_BASE + 0x0240) -#define ISP3X_RAWAWB_XY_DETC_NOR_Y_2 (ISP3X_RAWAWB_BASE + 0x0244) -#define ISP3X_RAWAWB_XY_DETC_BIG_X_2 (ISP3X_RAWAWB_BASE + 0x0248) -#define ISP3X_RAWAWB_XY_DETC_BIG_Y_2 (ISP3X_RAWAWB_BASE + 0x024c) -#define ISP3X_RAWAWB_XY_DETC_NOR_X_3 (ISP3X_RAWAWB_BASE + 0x0258) -#define ISP3X_RAWAWB_XY_DETC_NOR_Y_3 (ISP3X_RAWAWB_BASE + 0x025c) -#define ISP3X_RAWAWB_XY_DETC_BIG_X_3 (ISP3X_RAWAWB_BASE + 0x0260) -#define ISP3X_RAWAWB_XY_DETC_BIG_Y_3 (ISP3X_RAWAWB_BASE + 0x0264) -#define ISP3X_RAWAWB_XY_DETC_NOR_X_4 (ISP3X_RAWAWB_BASE + 0x0270) -#define ISP3X_RAWAWB_XY_DETC_NOR_Y_4 (ISP3X_RAWAWB_BASE + 0x0274) -#define ISP3X_RAWAWB_XY_DETC_BIG_X_4 (ISP3X_RAWAWB_BASE + 0x0278) -#define ISP3X_RAWAWB_XY_DETC_BIG_Y_4 (ISP3X_RAWAWB_BASE + 0x027c) -#define ISP3X_RAWAWB_XY_DETC_NOR_X_5 (ISP3X_RAWAWB_BASE + 0x0288) -#define ISP3X_RAWAWB_XY_DETC_NOR_Y_5 (ISP3X_RAWAWB_BASE + 0x028c) -#define ISP3X_RAWAWB_XY_DETC_BIG_X_5 (ISP3X_RAWAWB_BASE + 0x0290) -#define ISP3X_RAWAWB_XY_DETC_BIG_Y_5 (ISP3X_RAWAWB_BASE + 0x0294) -#define ISP3X_RAWAWB_XY_DETC_NOR_X_6 (ISP3X_RAWAWB_BASE + 0x02a0) -#define ISP3X_RAWAWB_XY_DETC_NOR_Y_6 (ISP3X_RAWAWB_BASE + 0x02a4) -#define ISP3X_RAWAWB_XY_DETC_BIG_X_6 (ISP3X_RAWAWB_BASE + 0x02a8) -#define ISP3X_RAWAWB_XY_DETC_BIG_Y_6 (ISP3X_RAWAWB_BASE + 0x02ac) -#define ISP3X_RAWAWB_MULTIWINDOW_EXC_CTRL (ISP3X_RAWAWB_BASE + 0x02b8) -#define ISP3X_RAWAWB_MULTIWINDOW0_OFFS (ISP3X_RAWAWB_BASE + 0x02bc) -#define ISP3X_RAWAWB_MULTIWINDOW0_SIZE (ISP3X_RAWAWB_BASE + 0x02c0) -#define ISP3X_RAWAWB_MULTIWINDOW1_OFFS (ISP3X_RAWAWB_BASE + 0x02c4) -#define ISP3X_RAWAWB_MULTIWINDOW1_SIZE (ISP3X_RAWAWB_BASE + 0x02c8) -#define ISP3X_RAWAWB_MULTIWINDOW2_OFFS (ISP3X_RAWAWB_BASE + 0x02cc) -#define ISP3X_RAWAWB_MULTIWINDOW2_SIZE (ISP3X_RAWAWB_BASE + 0x02d0) -#define ISP3X_RAWAWB_MULTIWINDOW3_OFFS (ISP3X_RAWAWB_BASE + 0x02d4) -#define ISP3X_RAWAWB_MULTIWINDOW3_SIZE (ISP3X_RAWAWB_BASE + 0x02d8) -#define ISP3X_RAWAWB_EXC_WP_REGION0_XU (ISP3X_RAWAWB_BASE + 0x02fc) -#define ISP3X_RAWAWB_EXC_WP_REGION0_YV (ISP3X_RAWAWB_BASE + 0x0300) -#define ISP3X_RAWAWB_EXC_WP_REGION1_XU (ISP3X_RAWAWB_BASE + 0x0304) -#define ISP3X_RAWAWB_EXC_WP_REGION1_YV (ISP3X_RAWAWB_BASE + 0x0308) -#define ISP3X_RAWAWB_EXC_WP_REGION2_XU (ISP3X_RAWAWB_BASE + 0x030c) -#define ISP3X_RAWAWB_EXC_WP_REGION2_YV (ISP3X_RAWAWB_BASE + 0x0310) -#define ISP3X_RAWAWB_EXC_WP_REGION3_XU (ISP3X_RAWAWB_BASE + 0x0314) -#define ISP3X_RAWAWB_EXC_WP_REGION3_YV (ISP3X_RAWAWB_BASE + 0x0318) -#define ISP3X_RAWAWB_EXC_WP_REGION4_XU (ISP3X_RAWAWB_BASE + 0x031c) -#define ISP3X_RAWAWB_EXC_WP_REGION4_YV (ISP3X_RAWAWB_BASE + 0x0320) -#define ISP3X_RAWAWB_EXC_WP_REGION5_XU (ISP3X_RAWAWB_BASE + 0x0324) -#define ISP3X_RAWAWB_EXC_WP_REGION5_YV (ISP3X_RAWAWB_BASE + 0x0328) -#define ISP3X_RAWAWB_EXC_WP_REGION6_XU (ISP3X_RAWAWB_BASE + 0x032c) -#define ISP3X_RAWAWB_EXC_WP_REGION6_YV (ISP3X_RAWAWB_BASE + 0x0330) -#define ISP3X_RAWAWB_SUM_RGAIN_NOR_0 (ISP3X_RAWAWB_BASE + 0x0340) -#define ISP3X_RAWAWB_SUM_BGAIN_NOR_0 (ISP3X_RAWAWB_BASE + 0x0348) -#define ISP3X_RAWAWB_WP_NUM_NOR_0 (ISP3X_RAWAWB_BASE + 0x034c) -#define ISP3X_RAWAWB_SUM_RGAIN_BIG_0 (ISP3X_RAWAWB_BASE + 0x0350) -#define ISP3X_RAWAWB_SUM_BGAIN_BIG_0 (ISP3X_RAWAWB_BASE + 0x0358) -#define ISP3X_RAWAWB_WP_NUM_BIG_0 (ISP3X_RAWAWB_BASE + 0x035c) -#define ISP3X_RAWAWB_SUM_RGAIN_NOR_1 (ISP3X_RAWAWB_BASE + 0x0370) -#define ISP3X_RAWAWB_SUM_BGAIN_NOR_1 (ISP3X_RAWAWB_BASE + 0x0378) -#define ISP3X_RAWAWB_WP_NUM_NOR_1 (ISP3X_RAWAWB_BASE + 0x037c) -#define ISP3X_RAWAWB_SUM_RGAIN_BIG_1 (ISP3X_RAWAWB_BASE + 0x0380) -#define ISP3X_RAWAWB_SUM_BGAIN_BIG_1 (ISP3X_RAWAWB_BASE + 0x0388) -#define ISP3X_RAWAWB_WP_NUM_BIG_1 (ISP3X_RAWAWB_BASE + 0x038c) -#define ISP3X_RAWAWB_SUM_RGAIN_NOR_2 (ISP3X_RAWAWB_BASE + 0x03a0) -#define ISP3X_RAWAWB_SUM_BGAIN_NOR_2 (ISP3X_RAWAWB_BASE + 0x03a8) -#define ISP3X_RAWAWB_WP_NUM_NOR_2 (ISP3X_RAWAWB_BASE + 0x03ac) -#define ISP3X_RAWAWB_SUM_RGAIN_BIG_2 (ISP3X_RAWAWB_BASE + 0x03b0) -#define ISP3X_RAWAWB_SUM_BGAIN_BIG_2 (ISP3X_RAWAWB_BASE + 0x03b8) -#define ISP3X_RAWAWB_WP_NUM_BIG_2 (ISP3X_RAWAWB_BASE + 0x03bc) -#define ISP3X_RAWAWB_SUM_RGAIN_NOR_3 (ISP3X_RAWAWB_BASE + 0x03d0) -#define ISP3X_RAWAWB_SUM_BGAIN_NOR_3 (ISP3X_RAWAWB_BASE + 0x03d8) -#define ISP3X_RAWAWB_WP_NUM_NOR_3 (ISP3X_RAWAWB_BASE + 0x03dc) -#define ISP3X_RAWAWB_SUM_RGAIN_BIG_3 (ISP3X_RAWAWB_BASE + 0x03e0) -#define ISP3X_RAWAWB_SUM_BGAIN_BIG_3 (ISP3X_RAWAWB_BASE + 0x03e8) -#define ISP3X_RAWAWB_WP_NUM_BIG_3 (ISP3X_RAWAWB_BASE + 0x03ec) -#define ISP3X_RAWAWB_SUM_RGAIN_NOR_4 (ISP3X_RAWAWB_BASE + 0x0400) -#define ISP3X_RAWAWB_SUM_BGAIN_NOR_4 (ISP3X_RAWAWB_BASE + 0x0408) -#define ISP3X_RAWAWB_WP_NUM_NOR_4 (ISP3X_RAWAWB_BASE + 0x040c) -#define ISP3X_RAWAWB_SUM_RGAIN_BIG_4 (ISP3X_RAWAWB_BASE + 0x0410) -#define ISP3X_RAWAWB_SUM_BGAIN_BIG_4 (ISP3X_RAWAWB_BASE + 0x0418) -#define ISP3X_RAWAWB_WP_NUM_BIG_4 (ISP3X_RAWAWB_BASE + 0x041c) -#define ISP3X_RAWAWB_SUM_RGAIN_NOR_5 (ISP3X_RAWAWB_BASE + 0x0430) -#define ISP3X_RAWAWB_SUM_BGAIN_NOR_5 (ISP3X_RAWAWB_BASE + 0x0438) -#define ISP3X_RAWAWB_WP_NUM_NOR_5 (ISP3X_RAWAWB_BASE + 0x043c) -#define ISP3X_RAWAWB_SUM_RGAIN_BIG_5 (ISP3X_RAWAWB_BASE + 0x0440) -#define ISP3X_RAWAWB_SUM_BGAIN_BIG_5 (ISP3X_RAWAWB_BASE + 0x0448) -#define ISP3X_RAWAWB_WP_NUM_BIG_5 (ISP3X_RAWAWB_BASE + 0x044c) -#define ISP3X_RAWAWB_SUM_RGAIN_NOR_6 (ISP3X_RAWAWB_BASE + 0x0460) -#define ISP3X_RAWAWB_SUM_BGAIN_NOR_6 (ISP3X_RAWAWB_BASE + 0x0468) -#define ISP3X_RAWAWB_WP_NUM_NOR_6 (ISP3X_RAWAWB_BASE + 0x046c) -#define ISP3X_RAWAWB_SUM_RGAIN_BIG_6 (ISP3X_RAWAWB_BASE + 0x0470) -#define ISP3X_RAWAWB_SUM_BGAIN_BIG_6 (ISP3X_RAWAWB_BASE + 0x0478) -#define ISP3X_RAWAWB_WP_NUM_BIG_6 (ISP3X_RAWAWB_BASE + 0x047c) -#define ISP3X_RAWAWB_SUM_R_NOR_MULTIWINDOW0 (ISP3X_RAWAWB_BASE + 0x0490) -#define ISP3X_RAWAWB_SUM_B_NOR_MULTIWINDOW0 (ISP3X_RAWAWB_BASE + 0x0498) -#define ISP3X_RAWAWB_WP_NM_NOR_MULTIWINDOW0 (ISP3X_RAWAWB_BASE + 0x049c) -#define ISP3X_RAWAWB_SUM_R_BIG_MULTIWINDOW0 (ISP3X_RAWAWB_BASE + 0x04a0) -#define ISP3X_RAWAWB_SUM_B_BIG_MULTIWINDOW0 (ISP3X_RAWAWB_BASE + 0x04a8) -#define ISP3X_RAWAWB_WP_NM_BIG_MULTIWINDOW0 (ISP3X_RAWAWB_BASE + 0x04ac) -#define ISP3X_RAWAWB_SUM_R_NOR_MULTIWINDOW1 (ISP3X_RAWAWB_BASE + 0x04c0) -#define ISP3X_RAWAWB_SUM_B_NOR_MULTIWINDOW1 (ISP3X_RAWAWB_BASE + 0x04c8) -#define ISP3X_RAWAWB_WP_NM_NOR_MULTIWINDOW1 (ISP3X_RAWAWB_BASE + 0x04cc) -#define ISP3X_RAWAWB_SUM_R_BIG_MULTIWINDOW1 (ISP3X_RAWAWB_BASE + 0x04d0) -#define ISP3X_RAWAWB_SUM_B_BIG_MULTIWINDOW1 (ISP3X_RAWAWB_BASE + 0x04d8) -#define ISP3X_RAWAWB_WP_NM_BIG_MULTIWINDOW1 (ISP3X_RAWAWB_BASE + 0x04dc) -#define ISP3X_RAWAWB_SUM_R_NOR_MULTIWINDOW2 (ISP3X_RAWAWB_BASE + 0x04f0) -#define ISP3X_RAWAWB_SUM_B_NOR_MULTIWINDOW2 (ISP3X_RAWAWB_BASE + 0x04f8) -#define ISP3X_RAWAWB_WP_NM_NOR_MULTIWINDOW2 (ISP3X_RAWAWB_BASE + 0x04fc) -#define ISP3X_RAWAWB_SUM_R_BIG_MULTIWINDOW2 (ISP3X_RAWAWB_BASE + 0x0500) -#define ISP3X_RAWAWB_SUM_B_BIG_MULTIWINDOW2 (ISP3X_RAWAWB_BASE + 0x0508) -#define ISP3X_RAWAWB_WP_NM_BIG_MULTIWINDOW2 (ISP3X_RAWAWB_BASE + 0x050c) -#define ISP3X_RAWAWB_SUM_R_NOR_MULTIWINDOW3 (ISP3X_RAWAWB_BASE + 0x0520) -#define ISP3X_RAWAWB_SUM_B_NOR_MULTIWINDOW3 (ISP3X_RAWAWB_BASE + 0x0528) -#define ISP3X_RAWAWB_WP_NM_NOR_MULTIWINDOW3 (ISP3X_RAWAWB_BASE + 0x052c) -#define ISP3X_RAWAWB_SUM_R_BIG_MULTIWINDOW3 (ISP3X_RAWAWB_BASE + 0x0530) -#define ISP3X_RAWAWB_SUM_B_BIG_MULTIWINDOW3 (ISP3X_RAWAWB_BASE + 0x0538) -#define ISP3X_RAWAWB_WP_NM_BIG_MULTIWINDOW3 (ISP3X_RAWAWB_BASE + 0x053c) -#define ISP3X_RAWAWB_SUM_R_EXC0 (ISP3X_RAWAWB_BASE + 0x05e0) -#define ISP3X_RAWAWB_SUM_B_EXC0 (ISP3X_RAWAWB_BASE + 0x05e8) -#define ISP3X_RAWAWB_WP_NM_EXC0 (ISP3X_RAWAWB_BASE + 0x05ec) -#define ISP3X_RAWAWB_SUM_R_EXC1 (ISP3X_RAWAWB_BASE + 0x05f0) -#define ISP3X_RAWAWB_SUM_B_EXC1 (ISP3X_RAWAWB_BASE + 0x05f8) -#define ISP3X_RAWAWB_WP_NM_EXC1 (ISP3X_RAWAWB_BASE + 0x05fc) -#define ISP3X_RAWAWB_SUM_R_EXC2 (ISP3X_RAWAWB_BASE + 0x0600) -#define ISP3X_RAWAWB_SUM_B_EXC2 (ISP3X_RAWAWB_BASE + 0x0608) -#define ISP3X_RAWAWB_WP_NM_EXC2 (ISP3X_RAWAWB_BASE + 0x060c) -#define ISP3X_RAWAWB_SUM_R_EXC3 (ISP3X_RAWAWB_BASE + 0x0610) -#define ISP3X_RAWAWB_SUM_B_EXC3 (ISP3X_RAWAWB_BASE + 0x0618) -#define ISP3X_RAWAWB_WP_NM_EXC3 (ISP3X_RAWAWB_BASE + 0x061c) -#define ISP3X_RAWAWB_Y_HIST01 (ISP3X_RAWAWB_BASE + 0x0620) -#define ISP3X_RAWAWB_Y_HIST23 (ISP3X_RAWAWB_BASE + 0x0624) -#define ISP3X_RAWAWB_Y_HIST45 (ISP3X_RAWAWB_BASE + 0x0628) -#define ISP3X_RAWAWB_Y_HIST67 (ISP3X_RAWAWB_BASE + 0x062c) -#define ISP3X_RAWAWB_WPNUM2_0 (ISP3X_RAWAWB_BASE + 0x0630) -#define ISP3X_RAWAWB_WPNUM2_1 (ISP3X_RAWAWB_BASE + 0x0634) -#define ISP3X_RAWAWB_WPNUM2_2 (ISP3X_RAWAWB_BASE + 0x0638) -#define ISP3X_RAWAWB_WPNUM2_3 (ISP3X_RAWAWB_BASE + 0x063c) -#define ISP3X_RAWAWB_WPNUM2_4 (ISP3X_RAWAWB_BASE + 0x0640) -#define ISP3X_RAWAWB_WPNUM2_5 (ISP3X_RAWAWB_BASE + 0x0644) -#define ISP3X_RAWAWB_WPNUM2_6 (ISP3X_RAWAWB_BASE + 0x0648) -#define ISP3X_RAWAWB_RAM_CTRL (ISP3X_RAWAWB_BASE + 0x0650) -#define ISP3X_RAWAWB_WRAM_CTRL (ISP3X_RAWAWB_BASE + 0x0654) -#define ISP3X_RAWAWB_WRAM_DATA_BASE (ISP3X_RAWAWB_BASE + 0x0660) -#define ISP3X_RAWAWB_RAM_DATA_BASE (ISP3X_RAWAWB_BASE + 0x0700) +#define ISP3X_RAWAWB_BASE 0x00005000 +#define ISP3X_RAWAWB_CTRL (ISP3X_RAWAWB_BASE + 0x0000) +#define ISP3X_RAWAWB_BLK_CTRL (ISP3X_RAWAWB_BASE + 0x0004) +#define ISP3X_RAWAWB_WIN_OFFS (ISP3X_RAWAWB_BASE + 0x0008) +#define ISP3X_RAWAWB_WIN_SIZE (ISP3X_RAWAWB_BASE + 0x000c) +#define ISP3X_RAWAWB_LIMIT_RG_MAX (ISP3X_RAWAWB_BASE + 0x0010) +#define ISP3X_RAWAWB_LIMIT_BY_MAX (ISP3X_RAWAWB_BASE + 0x0014) +#define ISP3X_RAWAWB_LIMIT_RG_MIN (ISP3X_RAWAWB_BASE + 0x0018) +#define ISP3X_RAWAWB_LIMIT_BY_MIN (ISP3X_RAWAWB_BASE + 0x001c) +#define ISP3X_RAWAWB_WEIGHT_CURVE_CTRL (ISP3X_RAWAWB_BASE + 0x0020) +#define ISP3X_RAWAWB_YWEIGHT_CURVE_XCOOR03 (ISP3X_RAWAWB_BASE + 0x0024) +#define ISP3X_RAWAWB_YWEIGHT_CURVE_XCOOR47 (ISP3X_RAWAWB_BASE + 0x0028) +#define ISP3X_RAWAWB_YWEIGHT_CURVE_XCOOR8 (ISP3X_RAWAWB_BASE + 0x002c) +#define ISP3X_RAWAWB_YWEIGHT_CURVE_YCOOR03 (ISP3X_RAWAWB_BASE + 0x0030) +#define ISP3X_RAWAWB_YWEIGHT_CURVE_YCOOR47 (ISP3X_RAWAWB_BASE + 0x0034) +#define ISP3X_RAWAWB_YWEIGHT_CURVE_YCOOR8 (ISP3X_RAWAWB_BASE + 0x0038) +#define ISP3X_RAWAWB_PRE_WBGAIN_INV (ISP3X_RAWAWB_BASE + 0x003c) +#define ISP3X_RAWAWB_UV_DETC_VERTEX0_0 (ISP3X_RAWAWB_BASE + 0x0040) +#define ISP3X_RAWAWB_UV_DETC_VERTEX1_0 (ISP3X_RAWAWB_BASE + 0x0044) +#define ISP3X_RAWAWB_UV_DETC_VERTEX2_0 (ISP3X_RAWAWB_BASE + 0x0048) +#define ISP3X_RAWAWB_UV_DETC_VERTEX3_0 (ISP3X_RAWAWB_BASE + 0x004c) +#define ISP3X_RAWAWB_UV_DETC_ISLOPE01_0 (ISP3X_RAWAWB_BASE + 0x0050) +#define ISP3X_RAWAWB_UV_DETC_ISLOPE12_0 (ISP3X_RAWAWB_BASE + 0x0054) +#define ISP3X_RAWAWB_UV_DETC_ISLOPE23_0 (ISP3X_RAWAWB_BASE + 0x0058) +#define ISP3X_RAWAWB_UV_DETC_ISLOPE30_0 (ISP3X_RAWAWB_BASE + 0x005c) +#define ISP3X_RAWAWB_UV_DETC_VERTEX0_1 (ISP3X_RAWAWB_BASE + 0x0060) +#define ISP3X_RAWAWB_UV_DETC_VERTEX1_1 (ISP3X_RAWAWB_BASE + 0x0064) +#define ISP3X_RAWAWB_UV_DETC_VERTEX2_1 (ISP3X_RAWAWB_BASE + 0x0068) +#define ISP3X_RAWAWB_UV_DETC_VERTEX3_1 (ISP3X_RAWAWB_BASE + 0x006c) +#define ISP3X_RAWAWB_UV_DETC_ISLOPE01_1 (ISP3X_RAWAWB_BASE + 0x0070) +#define ISP3X_RAWAWB_UV_DETC_ISLOPE12_1 (ISP3X_RAWAWB_BASE + 0x0074) +#define ISP3X_RAWAWB_UV_DETC_ISLOPE23_1 (ISP3X_RAWAWB_BASE + 0x0078) +#define ISP3X_RAWAWB_UV_DETC_ISLOPE30_1 (ISP3X_RAWAWB_BASE + 0x007c) +#define ISP3X_RAWAWB_UV_DETC_VERTEX0_2 (ISP3X_RAWAWB_BASE + 0x0080) +#define ISP3X_RAWAWB_UV_DETC_VERTEX1_2 (ISP3X_RAWAWB_BASE + 0x0084) +#define ISP3X_RAWAWB_UV_DETC_VERTEX2_2 (ISP3X_RAWAWB_BASE + 0x0088) +#define ISP3X_RAWAWB_UV_DETC_VERTEX3_2 (ISP3X_RAWAWB_BASE + 0x008c) +#define ISP3X_RAWAWB_UV_DETC_ISLOPE01_2 (ISP3X_RAWAWB_BASE + 0x0090) +#define ISP3X_RAWAWB_UV_DETC_ISLOPE12_2 (ISP3X_RAWAWB_BASE + 0x0094) +#define ISP3X_RAWAWB_UV_DETC_ISLOPE23_2 (ISP3X_RAWAWB_BASE + 0x0098) +#define ISP3X_RAWAWB_UV_DETC_ISLOPE30_2 (ISP3X_RAWAWB_BASE + 0x009c) +#define ISP3X_RAWAWB_UV_DETC_VERTEX0_3 (ISP3X_RAWAWB_BASE + 0x00a0) +#define ISP3X_RAWAWB_UV_DETC_VERTEX1_3 (ISP3X_RAWAWB_BASE + 0x00a4) +#define ISP3X_RAWAWB_UV_DETC_VERTEX2_3 (ISP3X_RAWAWB_BASE + 0x00a8) +#define ISP3X_RAWAWB_UV_DETC_VERTEX3_3 (ISP3X_RAWAWB_BASE + 0x00ac) +#define ISP3X_RAWAWB_UV_DETC_ISLOPE01_3 (ISP3X_RAWAWB_BASE + 0x00b0) +#define ISP3X_RAWAWB_UV_DETC_ISLOPE12_3 (ISP3X_RAWAWB_BASE + 0x00b4) +#define ISP3X_RAWAWB_UV_DETC_ISLOPE23_3 (ISP3X_RAWAWB_BASE + 0x00b8) +#define ISP3X_RAWAWB_UV_DETC_ISLOPE30_3 (ISP3X_RAWAWB_BASE + 0x00bc) +#define ISP3X_RAWAWB_UV_DETC_VERTEX0_4 (ISP3X_RAWAWB_BASE + 0x00c0) +#define ISP3X_RAWAWB_UV_DETC_VERTEX1_4 (ISP3X_RAWAWB_BASE + 0x00c4) +#define ISP3X_RAWAWB_UV_DETC_VERTEX2_4 (ISP3X_RAWAWB_BASE + 0x00c8) +#define ISP3X_RAWAWB_UV_DETC_VERTEX3_4 (ISP3X_RAWAWB_BASE + 0x00cc) +#define ISP3X_RAWAWB_UV_DETC_ISLOPE01_4 (ISP3X_RAWAWB_BASE + 0x00d0) +#define ISP3X_RAWAWB_UV_DETC_ISLOPE12_4 (ISP3X_RAWAWB_BASE + 0x00d4) +#define ISP3X_RAWAWB_UV_DETC_ISLOPE23_4 (ISP3X_RAWAWB_BASE + 0x00d8) +#define ISP3X_RAWAWB_UV_DETC_ISLOPE30_4 (ISP3X_RAWAWB_BASE + 0x00dc) +#define ISP3X_RAWAWB_UV_DETC_VERTEX0_5 (ISP3X_RAWAWB_BASE + 0x00e0) +#define ISP3X_RAWAWB_UV_DETC_VERTEX1_5 (ISP3X_RAWAWB_BASE + 0x00e4) +#define ISP3X_RAWAWB_UV_DETC_VERTEX2_5 (ISP3X_RAWAWB_BASE + 0x00e8) +#define ISP3X_RAWAWB_UV_DETC_VERTEX3_5 (ISP3X_RAWAWB_BASE + 0x00ec) +#define ISP3X_RAWAWB_UV_DETC_ISLOPE01_5 (ISP3X_RAWAWB_BASE + 0x00f0) +#define ISP3X_RAWAWB_UV_DETC_ISLOPE10_5 (ISP3X_RAWAWB_BASE + 0x00f4) +#define ISP3X_RAWAWB_UV_DETC_ISLOPE23_5 (ISP3X_RAWAWB_BASE + 0x00f8) +#define ISP3X_RAWAWB_UV_DETC_ISLOPE30_5 (ISP3X_RAWAWB_BASE + 0x00fc) +#define ISP3X_RAWAWB_UV_DETC_VERTEX0_6 (ISP3X_RAWAWB_BASE + 0x0100) +#define ISP3X_RAWAWB_UV_DETC_VERTEX1_6 (ISP3X_RAWAWB_BASE + 0x0104) +#define ISP3X_RAWAWB_UV_DETC_VERTEX2_6 (ISP3X_RAWAWB_BASE + 0x0108) +#define ISP3X_RAWAWB_UV_DETC_VERTEX3_6 (ISP3X_RAWAWB_BASE + 0x010c) +#define ISP3X_RAWAWB_UV_DETC_ISLOPE01_6 (ISP3X_RAWAWB_BASE + 0x0110) +#define ISP3X_RAWAWB_UV_DETC_ISLOPE10_6 (ISP3X_RAWAWB_BASE + 0x0114) +#define ISP3X_RAWAWB_UV_DETC_ISLOPE23_6 (ISP3X_RAWAWB_BASE + 0x0118) +#define ISP3X_RAWAWB_UV_DETC_ISLOPE30_6 (ISP3X_RAWAWB_BASE + 0x011c) +#define ISP3X_RAWAWB_YUV_RGB2ROTY_0 (ISP3X_RAWAWB_BASE + 0x0120) +#define ISP3X_RAWAWB_YUV_RGB2ROTY_1 (ISP3X_RAWAWB_BASE + 0x0124) +#define ISP3X_RAWAWB_YUV_RGB2ROTU_0 (ISP3X_RAWAWB_BASE + 0x0128) +#define ISP3X_RAWAWB_YUV_RGB2ROTU_1 (ISP3X_RAWAWB_BASE + 0x012c) +#define ISP3X_RAWAWB_YUV_RGB2ROTV_0 (ISP3X_RAWAWB_BASE + 0x0130) +#define ISP3X_RAWAWB_YUV_RGB2ROTV_1 (ISP3X_RAWAWB_BASE + 0x0134) +#define ISP3X_RAWAWB_YUV_X_COOR_Y_0 (ISP3X_RAWAWB_BASE + 0x0140) +#define ISP3X_RAWAWB_YUV_X_COOR_U_0 (ISP3X_RAWAWB_BASE + 0x0144) +#define ISP3X_RAWAWB_YUV_X_COOR_V_0 (ISP3X_RAWAWB_BASE + 0x0148) +#define ISP3X_RAWAWB_YUV_X1X2_DIS_0 (ISP3X_RAWAWB_BASE + 0x014c) +#define ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_0 (ISP3X_RAWAWB_BASE + 0x0150) +#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_0 (ISP3X_RAWAWB_BASE + 0x0154) +#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_0 (ISP3X_RAWAWB_BASE + 0x0158) +#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_0 (ISP3X_RAWAWB_BASE + 0x015c) +#define ISP3X_RAWAWB_YUV_X_COOR_Y_1 (ISP3X_RAWAWB_BASE + 0x0160) +#define ISP3X_RAWAWB_YUV_X_COOR_U_1 (ISP3X_RAWAWB_BASE + 0x0164) +#define ISP3X_RAWAWB_YUV_X_COOR_V_1 (ISP3X_RAWAWB_BASE + 0x0168) +#define ISP3X_RAWAWB_YUV_X1X2_DIS_1 (ISP3X_RAWAWB_BASE + 0x016c) +#define ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_1 (ISP3X_RAWAWB_BASE + 0x0170) +#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_1 (ISP3X_RAWAWB_BASE + 0x0174) +#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_1 (ISP3X_RAWAWB_BASE + 0x0178) +#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_1 (ISP3X_RAWAWB_BASE + 0x017c) +#define ISP3X_RAWAWB_YUV_X_COOR_Y_2 (ISP3X_RAWAWB_BASE + 0x0180) +#define ISP3X_RAWAWB_YUV_X_COOR_U_2 (ISP3X_RAWAWB_BASE + 0x0184) +#define ISP3X_RAWAWB_YUV_X_COOR_V_2 (ISP3X_RAWAWB_BASE + 0x0188) +#define ISP3X_RAWAWB_YUV_X1X2_DIS_2 (ISP3X_RAWAWB_BASE + 0x018c) +#define ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_2 (ISP3X_RAWAWB_BASE + 0x0190) +#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_2 (ISP3X_RAWAWB_BASE + 0x0194) +#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_2 (ISP3X_RAWAWB_BASE + 0x0198) +#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_2 (ISP3X_RAWAWB_BASE + 0x019c) +#define ISP3X_RAWAWB_YUV_X_COOR_Y_3 (ISP3X_RAWAWB_BASE + 0x01a0) +#define ISP3X_RAWAWB_YUV_X_COOR_U_3 (ISP3X_RAWAWB_BASE + 0x01a4) +#define ISP3X_RAWAWB_YUV_X_COOR_V_3 (ISP3X_RAWAWB_BASE + 0x01a8) +#define ISP3X_RAWAWB_YUV_X1X2_DIS_3 (ISP3X_RAWAWB_BASE + 0x01ac) +#define ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_3 (ISP3X_RAWAWB_BASE + 0x01b0) +#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_3 (ISP3X_RAWAWB_BASE + 0x01b4) +#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_3 (ISP3X_RAWAWB_BASE + 0x01b8) +#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_3 (ISP3X_RAWAWB_BASE + 0x01bc) +#define ISP3X_RAWAWB_RGB2XY_WT01 (ISP3X_RAWAWB_BASE + 0x01fc) +#define ISP3X_RAWAWB_RGB2XY_WT2 (ISP3X_RAWAWB_BASE + 0x0200) +#define ISP3X_RAWAWB_RGB2XY_MAT0_XY (ISP3X_RAWAWB_BASE + 0x0204) +#define ISP3X_RAWAWB_RGB2XY_MAT1_XY (ISP3X_RAWAWB_BASE + 0x0208) +#define ISP3X_RAWAWB_RGB2XY_MAT2_XY (ISP3X_RAWAWB_BASE + 0x020c) +#define ISP3X_RAWAWB_XY_DETC_NOR_X_0 (ISP3X_RAWAWB_BASE + 0x0210) +#define ISP3X_RAWAWB_XY_DETC_NOR_Y_0 (ISP3X_RAWAWB_BASE + 0x0214) +#define ISP3X_RAWAWB_XY_DETC_BIG_X_0 (ISP3X_RAWAWB_BASE + 0x0218) +#define ISP3X_RAWAWB_XY_DETC_BIG_Y_0 (ISP3X_RAWAWB_BASE + 0x021c) +#define ISP3X_RAWAWB_XY_DETC_NOR_X_1 (ISP3X_RAWAWB_BASE + 0x0228) +#define ISP3X_RAWAWB_XY_DETC_NOR_Y_1 (ISP3X_RAWAWB_BASE + 0x022c) +#define ISP3X_RAWAWB_XY_DETC_BIG_X_1 (ISP3X_RAWAWB_BASE + 0x0230) +#define ISP3X_RAWAWB_XY_DETC_BIG_Y_1 (ISP3X_RAWAWB_BASE + 0x0234) +#define ISP3X_RAWAWB_XY_DETC_NOR_X_2 (ISP3X_RAWAWB_BASE + 0x0240) +#define ISP3X_RAWAWB_XY_DETC_NOR_Y_2 (ISP3X_RAWAWB_BASE + 0x0244) +#define ISP3X_RAWAWB_XY_DETC_BIG_X_2 (ISP3X_RAWAWB_BASE + 0x0248) +#define ISP3X_RAWAWB_XY_DETC_BIG_Y_2 (ISP3X_RAWAWB_BASE + 0x024c) +#define ISP3X_RAWAWB_XY_DETC_NOR_X_3 (ISP3X_RAWAWB_BASE + 0x0258) +#define ISP3X_RAWAWB_XY_DETC_NOR_Y_3 (ISP3X_RAWAWB_BASE + 0x025c) +#define ISP3X_RAWAWB_XY_DETC_BIG_X_3 (ISP3X_RAWAWB_BASE + 0x0260) +#define ISP3X_RAWAWB_XY_DETC_BIG_Y_3 (ISP3X_RAWAWB_BASE + 0x0264) +#define ISP3X_RAWAWB_XY_DETC_NOR_X_4 (ISP3X_RAWAWB_BASE + 0x0270) +#define ISP3X_RAWAWB_XY_DETC_NOR_Y_4 (ISP3X_RAWAWB_BASE + 0x0274) +#define ISP3X_RAWAWB_XY_DETC_BIG_X_4 (ISP3X_RAWAWB_BASE + 0x0278) +#define ISP3X_RAWAWB_XY_DETC_BIG_Y_4 (ISP3X_RAWAWB_BASE + 0x027c) +#define ISP3X_RAWAWB_XY_DETC_NOR_X_5 (ISP3X_RAWAWB_BASE + 0x0288) +#define ISP3X_RAWAWB_XY_DETC_NOR_Y_5 (ISP3X_RAWAWB_BASE + 0x028c) +#define ISP3X_RAWAWB_XY_DETC_BIG_X_5 (ISP3X_RAWAWB_BASE + 0x0290) +#define ISP3X_RAWAWB_XY_DETC_BIG_Y_5 (ISP3X_RAWAWB_BASE + 0x0294) +#define ISP3X_RAWAWB_XY_DETC_NOR_X_6 (ISP3X_RAWAWB_BASE + 0x02a0) +#define ISP3X_RAWAWB_XY_DETC_NOR_Y_6 (ISP3X_RAWAWB_BASE + 0x02a4) +#define ISP3X_RAWAWB_XY_DETC_BIG_X_6 (ISP3X_RAWAWB_BASE + 0x02a8) +#define ISP3X_RAWAWB_XY_DETC_BIG_Y_6 (ISP3X_RAWAWB_BASE + 0x02ac) +#define ISP3X_RAWAWB_MULTIWINDOW_EXC_CTRL (ISP3X_RAWAWB_BASE + 0x02b8) +#define ISP3X_RAWAWB_MULTIWINDOW0_OFFS (ISP3X_RAWAWB_BASE + 0x02bc) +#define ISP3X_RAWAWB_MULTIWINDOW0_SIZE (ISP3X_RAWAWB_BASE + 0x02c0) +#define ISP3X_RAWAWB_MULTIWINDOW1_OFFS (ISP3X_RAWAWB_BASE + 0x02c4) +#define ISP3X_RAWAWB_MULTIWINDOW1_SIZE (ISP3X_RAWAWB_BASE + 0x02c8) +#define ISP3X_RAWAWB_MULTIWINDOW2_OFFS (ISP3X_RAWAWB_BASE + 0x02cc) +#define ISP3X_RAWAWB_MULTIWINDOW2_SIZE (ISP3X_RAWAWB_BASE + 0x02d0) +#define ISP3X_RAWAWB_MULTIWINDOW3_OFFS (ISP3X_RAWAWB_BASE + 0x02d4) +#define ISP3X_RAWAWB_MULTIWINDOW3_SIZE (ISP3X_RAWAWB_BASE + 0x02d8) +#define ISP3X_RAWAWB_EXC_WP_REGION0_XU (ISP3X_RAWAWB_BASE + 0x02fc) +#define ISP3X_RAWAWB_EXC_WP_REGION0_YV (ISP3X_RAWAWB_BASE + 0x0300) +#define ISP3X_RAWAWB_EXC_WP_REGION1_XU (ISP3X_RAWAWB_BASE + 0x0304) +#define ISP3X_RAWAWB_EXC_WP_REGION1_YV (ISP3X_RAWAWB_BASE + 0x0308) +#define ISP3X_RAWAWB_EXC_WP_REGION2_XU (ISP3X_RAWAWB_BASE + 0x030c) +#define ISP3X_RAWAWB_EXC_WP_REGION2_YV (ISP3X_RAWAWB_BASE + 0x0310) +#define ISP3X_RAWAWB_EXC_WP_REGION3_XU (ISP3X_RAWAWB_BASE + 0x0314) +#define ISP3X_RAWAWB_EXC_WP_REGION3_YV (ISP3X_RAWAWB_BASE + 0x0318) +#define ISP3X_RAWAWB_EXC_WP_REGION4_XU (ISP3X_RAWAWB_BASE + 0x031c) +#define ISP3X_RAWAWB_EXC_WP_REGION4_YV (ISP3X_RAWAWB_BASE + 0x0320) +#define ISP3X_RAWAWB_EXC_WP_REGION5_XU (ISP3X_RAWAWB_BASE + 0x0324) +#define ISP3X_RAWAWB_EXC_WP_REGION5_YV (ISP3X_RAWAWB_BASE + 0x0328) +#define ISP3X_RAWAWB_EXC_WP_REGION6_XU (ISP3X_RAWAWB_BASE + 0x032c) +#define ISP3X_RAWAWB_EXC_WP_REGION6_YV (ISP3X_RAWAWB_BASE + 0x0330) +#define ISP32_RAWAWB_EXC_WP_WEIGHT0_3 (ISP3X_RAWAWB_BASE + 0x0334) +#define ISP32_RAWAWB_EXC_WP_WEIGHT4_6 (ISP3X_RAWAWB_BASE + 0x0338) +#define ISP3X_RAWAWB_SUM_RGAIN_NOR_0 (ISP3X_RAWAWB_BASE + 0x0340) +#define ISP3X_RAWAWB_SUM_BGAIN_NOR_0 (ISP3X_RAWAWB_BASE + 0x0348) +#define ISP3X_RAWAWB_WP_NUM_NOR_0 (ISP3X_RAWAWB_BASE + 0x034c) +#define ISP3X_RAWAWB_SUM_RGAIN_BIG_0 (ISP3X_RAWAWB_BASE + 0x0350) +#define ISP3X_RAWAWB_SUM_BGAIN_BIG_0 (ISP3X_RAWAWB_BASE + 0x0358) +#define ISP3X_RAWAWB_WP_NUM_BIG_0 (ISP3X_RAWAWB_BASE + 0x035c) +#define ISP3X_RAWAWB_SUM_RGAIN_NOR_1 (ISP3X_RAWAWB_BASE + 0x0370) +#define ISP3X_RAWAWB_SUM_BGAIN_NOR_1 (ISP3X_RAWAWB_BASE + 0x0378) +#define ISP3X_RAWAWB_WP_NUM_NOR_1 (ISP3X_RAWAWB_BASE + 0x037c) +#define ISP3X_RAWAWB_SUM_RGAIN_BIG_1 (ISP3X_RAWAWB_BASE + 0x0380) +#define ISP3X_RAWAWB_SUM_BGAIN_BIG_1 (ISP3X_RAWAWB_BASE + 0x0388) +#define ISP3X_RAWAWB_WP_NUM_BIG_1 (ISP3X_RAWAWB_BASE + 0x038c) +#define ISP3X_RAWAWB_SUM_RGAIN_NOR_2 (ISP3X_RAWAWB_BASE + 0x03a0) +#define ISP3X_RAWAWB_SUM_BGAIN_NOR_2 (ISP3X_RAWAWB_BASE + 0x03a8) +#define ISP3X_RAWAWB_WP_NUM_NOR_2 (ISP3X_RAWAWB_BASE + 0x03ac) +#define ISP3X_RAWAWB_SUM_RGAIN_BIG_2 (ISP3X_RAWAWB_BASE + 0x03b0) +#define ISP3X_RAWAWB_SUM_BGAIN_BIG_2 (ISP3X_RAWAWB_BASE + 0x03b8) +#define ISP3X_RAWAWB_WP_NUM_BIG_2 (ISP3X_RAWAWB_BASE + 0x03bc) +#define ISP3X_RAWAWB_SUM_RGAIN_NOR_3 (ISP3X_RAWAWB_BASE + 0x03d0) +#define ISP3X_RAWAWB_SUM_BGAIN_NOR_3 (ISP3X_RAWAWB_BASE + 0x03d8) +#define ISP3X_RAWAWB_WP_NUM_NOR_3 (ISP3X_RAWAWB_BASE + 0x03dc) +#define ISP3X_RAWAWB_SUM_RGAIN_BIG_3 (ISP3X_RAWAWB_BASE + 0x03e0) +#define ISP3X_RAWAWB_SUM_BGAIN_BIG_3 (ISP3X_RAWAWB_BASE + 0x03e8) +#define ISP3X_RAWAWB_WP_NUM_BIG_3 (ISP3X_RAWAWB_BASE + 0x03ec) +#define ISP3X_RAWAWB_SUM_RGAIN_NOR_4 (ISP3X_RAWAWB_BASE + 0x0400) +#define ISP3X_RAWAWB_SUM_BGAIN_NOR_4 (ISP3X_RAWAWB_BASE + 0x0408) +#define ISP3X_RAWAWB_WP_NUM_NOR_4 (ISP3X_RAWAWB_BASE + 0x040c) +#define ISP3X_RAWAWB_SUM_RGAIN_BIG_4 (ISP3X_RAWAWB_BASE + 0x0410) +#define ISP3X_RAWAWB_SUM_BGAIN_BIG_4 (ISP3X_RAWAWB_BASE + 0x0418) +#define ISP3X_RAWAWB_WP_NUM_BIG_4 (ISP3X_RAWAWB_BASE + 0x041c) +#define ISP3X_RAWAWB_SUM_RGAIN_NOR_5 (ISP3X_RAWAWB_BASE + 0x0430) +#define ISP3X_RAWAWB_SUM_BGAIN_NOR_5 (ISP3X_RAWAWB_BASE + 0x0438) +#define ISP3X_RAWAWB_WP_NUM_NOR_5 (ISP3X_RAWAWB_BASE + 0x043c) +#define ISP3X_RAWAWB_SUM_RGAIN_BIG_5 (ISP3X_RAWAWB_BASE + 0x0440) +#define ISP3X_RAWAWB_SUM_BGAIN_BIG_5 (ISP3X_RAWAWB_BASE + 0x0448) +#define ISP3X_RAWAWB_WP_NUM_BIG_5 (ISP3X_RAWAWB_BASE + 0x044c) +#define ISP3X_RAWAWB_SUM_RGAIN_NOR_6 (ISP3X_RAWAWB_BASE + 0x0460) +#define ISP3X_RAWAWB_SUM_BGAIN_NOR_6 (ISP3X_RAWAWB_BASE + 0x0468) +#define ISP3X_RAWAWB_WP_NUM_NOR_6 (ISP3X_RAWAWB_BASE + 0x046c) +#define ISP3X_RAWAWB_SUM_RGAIN_BIG_6 (ISP3X_RAWAWB_BASE + 0x0470) +#define ISP3X_RAWAWB_SUM_BGAIN_BIG_6 (ISP3X_RAWAWB_BASE + 0x0478) +#define ISP3X_RAWAWB_WP_NUM_BIG_6 (ISP3X_RAWAWB_BASE + 0x047c) +#define ISP3X_RAWAWB_SUM_R_NOR_MULTIWINDOW0 (ISP3X_RAWAWB_BASE + 0x0490) +#define ISP3X_RAWAWB_SUM_B_NOR_MULTIWINDOW0 (ISP3X_RAWAWB_BASE + 0x0498) +#define ISP3X_RAWAWB_WP_NM_NOR_MULTIWINDOW0 (ISP3X_RAWAWB_BASE + 0x049c) +#define ISP3X_RAWAWB_SUM_R_BIG_MULTIWINDOW0 (ISP3X_RAWAWB_BASE + 0x04a0) +#define ISP3X_RAWAWB_SUM_B_BIG_MULTIWINDOW0 (ISP3X_RAWAWB_BASE + 0x04a8) +#define ISP3X_RAWAWB_WP_NM_BIG_MULTIWINDOW0 (ISP3X_RAWAWB_BASE + 0x04ac) +#define ISP3X_RAWAWB_SUM_R_NOR_MULTIWINDOW1 (ISP3X_RAWAWB_BASE + 0x04c0) +#define ISP3X_RAWAWB_SUM_B_NOR_MULTIWINDOW1 (ISP3X_RAWAWB_BASE + 0x04c8) +#define ISP3X_RAWAWB_WP_NM_NOR_MULTIWINDOW1 (ISP3X_RAWAWB_BASE + 0x04cc) +#define ISP3X_RAWAWB_SUM_R_BIG_MULTIWINDOW1 (ISP3X_RAWAWB_BASE + 0x04d0) +#define ISP3X_RAWAWB_SUM_B_BIG_MULTIWINDOW1 (ISP3X_RAWAWB_BASE + 0x04d8) +#define ISP3X_RAWAWB_WP_NM_BIG_MULTIWINDOW1 (ISP3X_RAWAWB_BASE + 0x04dc) +#define ISP3X_RAWAWB_SUM_R_NOR_MULTIWINDOW2 (ISP3X_RAWAWB_BASE + 0x04f0) +#define ISP3X_RAWAWB_SUM_B_NOR_MULTIWINDOW2 (ISP3X_RAWAWB_BASE + 0x04f8) +#define ISP3X_RAWAWB_WP_NM_NOR_MULTIWINDOW2 (ISP3X_RAWAWB_BASE + 0x04fc) +#define ISP3X_RAWAWB_SUM_R_BIG_MULTIWINDOW2 (ISP3X_RAWAWB_BASE + 0x0500) +#define ISP3X_RAWAWB_SUM_B_BIG_MULTIWINDOW2 (ISP3X_RAWAWB_BASE + 0x0508) +#define ISP3X_RAWAWB_WP_NM_BIG_MULTIWINDOW2 (ISP3X_RAWAWB_BASE + 0x050c) +#define ISP3X_RAWAWB_SUM_R_NOR_MULTIWINDOW3 (ISP3X_RAWAWB_BASE + 0x0520) +#define ISP3X_RAWAWB_SUM_B_NOR_MULTIWINDOW3 (ISP3X_RAWAWB_BASE + 0x0528) +#define ISP3X_RAWAWB_WP_NM_NOR_MULTIWINDOW3 (ISP3X_RAWAWB_BASE + 0x052c) +#define ISP3X_RAWAWB_SUM_R_BIG_MULTIWINDOW3 (ISP3X_RAWAWB_BASE + 0x0530) +#define ISP3X_RAWAWB_SUM_B_BIG_MULTIWINDOW3 (ISP3X_RAWAWB_BASE + 0x0538) +#define ISP3X_RAWAWB_WP_NM_BIG_MULTIWINDOW3 (ISP3X_RAWAWB_BASE + 0x053c) +#define ISP3X_RAWAWB_SUM_R_EXC0 (ISP3X_RAWAWB_BASE + 0x05e0) +#define ISP3X_RAWAWB_SUM_B_EXC0 (ISP3X_RAWAWB_BASE + 0x05e8) +#define ISP3X_RAWAWB_WP_NM_EXC0 (ISP3X_RAWAWB_BASE + 0x05ec) +#define ISP3X_RAWAWB_SUM_R_EXC1 (ISP3X_RAWAWB_BASE + 0x05f0) +#define ISP3X_RAWAWB_SUM_B_EXC1 (ISP3X_RAWAWB_BASE + 0x05f8) +#define ISP3X_RAWAWB_WP_NM_EXC1 (ISP3X_RAWAWB_BASE + 0x05fc) +#define ISP3X_RAWAWB_SUM_R_EXC2 (ISP3X_RAWAWB_BASE + 0x0600) +#define ISP3X_RAWAWB_SUM_B_EXC2 (ISP3X_RAWAWB_BASE + 0x0608) +#define ISP3X_RAWAWB_WP_NM_EXC2 (ISP3X_RAWAWB_BASE + 0x060c) +#define ISP3X_RAWAWB_SUM_R_EXC3 (ISP3X_RAWAWB_BASE + 0x0610) +#define ISP3X_RAWAWB_SUM_B_EXC3 (ISP3X_RAWAWB_BASE + 0x0618) +#define ISP3X_RAWAWB_WP_NM_EXC3 (ISP3X_RAWAWB_BASE + 0x061c) +#define ISP3X_RAWAWB_Y_HIST01 (ISP3X_RAWAWB_BASE + 0x0620) +#define ISP3X_RAWAWB_Y_HIST23 (ISP3X_RAWAWB_BASE + 0x0624) +#define ISP3X_RAWAWB_Y_HIST45 (ISP3X_RAWAWB_BASE + 0x0628) +#define ISP3X_RAWAWB_Y_HIST67 (ISP3X_RAWAWB_BASE + 0x062c) +#define ISP3X_RAWAWB_WPNUM2_0 (ISP3X_RAWAWB_BASE + 0x0630) +#define ISP3X_RAWAWB_WPNUM2_1 (ISP3X_RAWAWB_BASE + 0x0634) +#define ISP3X_RAWAWB_WPNUM2_2 (ISP3X_RAWAWB_BASE + 0x0638) +#define ISP3X_RAWAWB_WPNUM2_3 (ISP3X_RAWAWB_BASE + 0x063c) +#define ISP3X_RAWAWB_WPNUM2_4 (ISP3X_RAWAWB_BASE + 0x0640) +#define ISP3X_RAWAWB_WPNUM2_5 (ISP3X_RAWAWB_BASE + 0x0644) +#define ISP3X_RAWAWB_WPNUM2_6 (ISP3X_RAWAWB_BASE + 0x0648) +#define ISP3X_RAWAWB_RAM_CTRL (ISP3X_RAWAWB_BASE + 0x0650) +#define ISP3X_RAWAWB_WRAM_CTRL (ISP3X_RAWAWB_BASE + 0x0654) +#define ISP3X_RAWAWB_WRAM_DATA_BASE (ISP3X_RAWAWB_BASE + 0x0660) +#define ISP3X_RAWAWB_RAM_DATA_BASE (ISP3X_RAWAWB_BASE + 0x0700) /* VI_ISP_PATH */ #define ISP3X_RAWAE3_SEL(x) (((x) & 3) << 16) #define ISP3X_RAWAF_SEL(x) (((x) & 3) << 18) #define ISP3X_RAWAWB_SEL(x) (((x) & 3) << 20) #define ISP3X_RAWAE012_SEL(x) (((x) & 3) << 22) +#define ISP3X_LSC_CFG_SEL(x) (((x) & 3) << 24) +#define ISP32_BNR2AWB_SEL BIT(26) +#define ISP32_DRC2AWB_SEL BIT(27) + +/* VI_ICCL */ +#define ISP32_BRSZ_CLK_ENABLE BIT(13) /* SWS_CFG */ #define ISP3X_SW_ACK_FRM_PRO_DIS BIT(3) @@ -1554,6 +1769,7 @@ #define ISP3X_SW_CMSK_YUV(x, y, z) (((x) & 0xff) | ((y) & 0xff) << 8 | ((z) & 0xff) << 16) /* ISP CTRL0 */ +#define ISP32_MIR_ENABLE BIT(5) #define ISP3X_SW_CGC_YUV_LIMIT BIT(28) #define ISP3X_SW_CGC_RATIO_EN BIT(29) @@ -1655,6 +1871,8 @@ #define ISP3X_MI_BP_FRAME BIT(25) #define ISP3X_MI_WRAP_BP_Y BIT(26) #define ISP3X_MI_WRAP_BP_CB BIT(27) +#define ISP32_MI_MPDS_FRAME BIT(28) +#define ISP32_MI_BPDS_FRAME BIT(29) #define ISP3X_MI_BUS_ERR BIT(30) #define ISP3X_MI_MPFBC_FRAME BIT(31) @@ -1681,9 +1899,29 @@ #define ISP3X_BAY3D_IIRSELF_UPD BIT(22) #define ISP3X_BAY3D_CURSELF_UPD BIT(23) #define ISP3X_BAY3D_DSSELF_UPD BIT(24) +#define ISP32_MPDSSELF_FORCE_UPD BIT(25) +#define ISP32_BPDSSELF_FORCE_UPD BIT(26) #define ISP3X_DBR_ST_MODE BIT(30) #define ISP3X_DBR_ST BIT(31) +/* MI_WR_CTRL2_SHD */ +#define ISP32_BP_EN_IN_SHD BIT(4) +#define ISP32_DBR_WR_EN_IN_SHD BIT(5) +#define ISP32_GAIN_WR_EN_IN_SHD BIT(6) +#define ISP32_BAY3D_CUR_WR_EN_IN_SHD BIT(8) +#define ISP32_BAY3D_IIR_WR_EN_IN_SHD BIT(9) +#define ISP32_BAY3D_DS_WR_EN_IN_SHD BIT(10) +#define ISP32_MPDS_EN_IN_SHD BIT(12) +#define ISP32_BPDS_EN_IN_SHD BIT(13) +#define ISP32_BP_EN_OUT_SHD BIT(20) +#define ISP32_DBR_WR_EN_OUT_SHD BIT(21) +#define ISP32_GAIN_WR_EN_OUT_SHD BIT(22) +#define ISP32_BAY3D_CUR_WR_EN_OUT_SHD BIT(24) +#define ISP32_BAY3D_IIR_WR_EN_OUT_SHD BIT(25) +#define ISP32_BAY3D_DS_WR_EN_OUT_SHD BIT(26) +#define ISP32_MPDS_EN_OUT_SHD BIT(28) +#define ISP32_BPDS_EN_OUT_SHD BIT(29) + /* BP_WR_CTRL */ #define ISP3X_BP_ENABLE BIT(0) #define ISP3X_BP_AUTO_UPD BIT(1) @@ -1692,6 +1930,48 @@ #define ISP3X_BP_FORMAT_SPLA BIT(4) #define ISP3X_BP_FORMAT_INT BIT(5) #define ISP3X_BP_FORMAT_MASK GENMASK(5, 4) +#define ISP3X_BP_OUTPUT_YUV400 0 +#define ISP3X_BP_OUTPUT_YUV420 BIT(8) +#define ISP3X_BP_OUTPUT_YUV422 BIT(9) +#define ISP3X_BP_OUTPUT_MASK GENMASK(10, 8) + +/* MPDS/BPDS WR_CTRL */ +#define ISP32_DS_ENABLE BIT(0) +#define ISP32_DS_AUTO_UPD BIT(1) +#define ISP32_DS_FORMAT_PLA 0 +#define ISP32_DS_FORMAT_SPLA BIT(4) +#define ISP32_DS_FORMAT_INT BIT(5) +#define ISP32_DS_FORMAT_MASK GENMASK(5, 4) +#define ISP32_DS_OUTPUT_YUV400 0 +#define ISP32_DS_OUTPUT_YUV420 BIT(8) +#define ISP32_DS_OUTPUT_YUV422 BIT(9) +#define ISP32_DS_OUTPUT_MASK GENMASK(10, 8) +#define ISP32_DS_RAM_CLK_DIS BIT(30) +#define ISP32_DS_DS_DIS BIT(31) + +/* WRAP_CTRL */ +#define ISP32_MP_WR_INIT_OFFSET_EN BIT(0) +#define ISP32_SP_WR_INIT_OFFSET_EN BIT(1) +#define ISP32_BP_WR_INIT_OFFSET_EN BIT(2) +#define ISP32_MPDS_WR_INIT_OFFSET_EN BIT(4) +#define ISP32_BPDS_WR_INIT_OFFSET_EN BIT(5) +#define ISP32_MP_DYNAMIC_UPD_ADDR BIT(8) +#define ISP32_SP_DYNAMIC_UPD_ADDR BIT(9) +#define ISP32_BP_DYNAMIC_UPD_ADDR BIT(10) +#define ISP32_MPDS_DYNAMIC_UPD_ADDR BIT(11) +#define ISP32_BPDS_DYNAMIC_UPD_ADDR BIT(12) +#define ISP32_MP_WR_FRMEND_UPD_DIS BIT(24) +#define ISP32_SP_WR_FRMEND_UPD_DIS BIT(25) +#define ISP32_BP_WR_FRMEND_UPD_DIS BIT(26) +#define ISP32_MPDS_WR_FRMEND_UPD_DIS BIT(27) +#define ISP32_BPDS_WR_FRMEND_UPD_DIS BIT(28) + +/* WRAP_CTRL */ +#define ISP32_MP_WR_V_FLIP BIT(0) +#define ISP32_SP_WR_V_FLIP BIT(1) +#define ISP32_BP_WR_V_FLIP BIT(2) +#define ISP32_MPDS_WR_V_FLIP BIT(4) +#define ISP32_BPDS_WR_V_FIIP BIT(5) /* MPFBC */ #define ISP3X_MPFBC_YUV_MASK GENMASK(2, 1) @@ -1725,10 +2005,12 @@ #define ISP3X_CAC_LUT_MODE(x) (((x) & 0x3) << 24) /* CNR */ +#define ISP3X_CNR_GLOBAL_GAIN_ALPHA_MAX GENMASK(15, 12) /* YNR */ /* BLS */ +#define ISP32_BLS_BLS2_EN BIT(5) /* GIC */ @@ -1759,6 +2041,9 @@ /* DPCC */ /* CCM */ +#define ISP3X_CCM_HIGHY_ADJ_DIS BIT(1) +#define ISP32_CCM_ENH_ADJ_EN BIT(2) +#define ISP32_CCM_ASYM_ADJ_EN BIT(3) /* 3DLUT */ #define ISP3X_3DLUT_EN BIT(0) @@ -1812,11 +2097,4 @@ #define ISP3X_RAWAF_INELINE0(x) ((x) & 0xf) #define ISP3X_RAWAF_INTLINE0_EN BIT(27) -static inline bool is_bp_stream_stopped(void __iomem *base) -{ - u32 ret = readl(base + ISP3X_MI_BP_WR_CTRL); - - return !(ret & ISP3X_BP_ENABLE); -} - #endif /* _RKISP_REGS_V3X_H */ diff --git a/drivers/media/platform/rockchip/isp/rkisp.c b/drivers/media/platform/rockchip/isp/rkisp.c index 171769388718..0d07e7cf4e10 100644 --- a/drivers/media/platform/rockchip/isp/rkisp.c +++ b/drivers/media/platform/rockchip/isp/rkisp.c @@ -231,6 +231,14 @@ int rkisp_align_sensor_resolution(struct rkisp_device *dev, CIF_ISP_INPUT_H_MAX_V30_UNITE : CIF_ISP_INPUT_H_MAX_V30; h = clamp_t(u32, src_h, CIF_ISP_INPUT_H_MIN, h); break; + case ISP_V32: + w = clamp_t(u32, src_w, + CIF_ISP_INPUT_W_MIN, + CIF_ISP_INPUT_W_MAX_V32); + h = clamp_t(u32, src_h, + CIF_ISP_INPUT_H_MIN, + CIF_ISP_INPUT_H_MAX_V32); + break; default: w = clamp_t(u32, src_w, CIF_ISP_INPUT_W_MIN, @@ -591,9 +599,12 @@ void rkisp_trigger_read_back(struct rkisp_device *dev, u8 dma2frm, u32 mode, boo val = rkisp_read(dev, ISP3X_MPFBC_CTRL, false); val |= ISP3X_MPFBC_FORCE_UPD; writel(val, hw->base_addr + ISP3X_MPFBC_CTRL); + } else if (dev->isp_ver == ISP_V32) { + writel(CIF_MI_INIT_SOFT_UPD, hw->base_addr + ISP3X_MI_WR_INIT); } /* sensor mode & index */ - if (dev->isp_ver == ISP_V21 || dev->isp_ver == ISP_V30) { + if (dev->isp_ver == ISP_V21 || dev->isp_ver == ISP_V30 || + dev->isp_ver == ISP_V32) { u32 mode = hw->dev_link_num >= 3 ? 2 : hw->dev_link_num - 1; u32 index = dev->dev_id; @@ -621,7 +632,9 @@ void rkisp_trigger_read_back(struct rkisp_device *dev, u8 dma2frm, u32 mode, boo is_upd = true; } - if (dev->isp_ver == ISP_V21 || dev->isp_ver == ISP_V30) + if (dev->isp_ver == ISP_V21 || + dev->isp_ver == ISP_V30 || + dev->isp_ver == ISP_V32) dma2frm = 0; if (dma2frm > 2) dma2frm = 2; @@ -845,7 +858,7 @@ static void rkisp_config_ism(struct rkisp_device *dev) rkisp_unite_write(dev, CIF_ISP_IS_V_SIZE, out_crop->height / mult, false, is_unite); - if (dev->isp_ver == ISP_V30) + if (dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) return; /* IS(Image Stabilization) is always on, working as output crop */ @@ -1006,7 +1019,7 @@ static void rkisp_restart_monitor(struct work_struct *work) !(monitor->state & ISP_MIPI_ERROR))) { for (i = 0; i < hw->dev_num; i++) { isp = hw->isp[i]; - if (isp && !(isp->isp_inp & INP_CSI)) + if (!isp || (isp && !(isp->isp_inp & INP_CSI))) continue; if (!(isp->isp_state & ISP_START)) break; @@ -1326,7 +1339,7 @@ static void rkisp_config_cmsk(struct rkisp_device *dev) unsigned long lock_flags = 0; struct rkisp_cmsk_cfg cfg; - if (dev->isp_ver != ISP_V30) + if (dev->isp_ver != ISP_V30 && dev->isp_ver != ISP_V32) return; spin_lock_irqsave(&dev->cmsk_lock, lock_flags); @@ -1382,9 +1395,8 @@ static int rkisp_config_isp(struct rkisp_device *dev) if (in_fmt->mbus_code == MEDIA_BUS_FMT_Y8_1X8 || in_fmt->mbus_code == MEDIA_BUS_FMT_Y10_1X10 || in_fmt->mbus_code == MEDIA_BUS_FMT_Y12_1X12) { - if (dev->isp_ver == ISP_V20 || - dev->isp_ver == ISP_V21 || - dev->isp_ver == ISP_V30) + if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 || + dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) rkisp_unite_write(dev, ISP_DEBAYER_CONTROL, 0, false, is_unite); else @@ -1392,9 +1404,8 @@ static int rkisp_config_isp(struct rkisp_device *dev) CIF_ISP_DEMOSAIC_BYPASS | CIF_ISP_DEMOSAIC_TH(0xc), false); } else { - if (dev->isp_ver == ISP_V20 || - dev->isp_ver == ISP_V21 || - dev->isp_ver == ISP_V30) + if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 || + dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) rkisp_unite_write(dev, ISP_DEBAYER_CONTROL, SW_DEBAYER_EN | SW_DEBAYER_FILTER_G_EN | @@ -1489,9 +1500,8 @@ static int rkisp_config_isp(struct rkisp_device *dev) /* interrupt mask */ irq_mask |= CIF_ISP_FRAME | CIF_ISP_V_START | CIF_ISP_PIC_SIZE_ERROR | CIF_ISP_FRAME_IN; - if (dev->isp_ver == ISP_V20 || - dev->isp_ver == ISP_V21 || - dev->isp_ver == ISP_V30) + if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 || + dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) irq_mask |= ISP2X_LSC_LUT_ERR; if (is_unite) rkisp_next_write(dev, CIF_ISP_IMSC, irq_mask, true); @@ -1769,9 +1779,8 @@ static int rkisp_isp_stop(struct rkisp_device *dev) readl(base + CIF_ISP_CSI0_ERR1); readl(base + CIF_ISP_CSI0_ERR2); readl(base + CIF_ISP_CSI0_ERR3); - } else if (dev->isp_ver == ISP_V20 || - dev->isp_ver == ISP_V21 || - dev->isp_ver == ISP_V30) { + } else if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 || + dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) { writel(0, base + CSI2RX_MASK_PHY); writel(0, base + CSI2RX_MASK_PACKET); writel(0, base + CSI2RX_MASK_OVERFLOW); @@ -1788,9 +1797,8 @@ static int rkisp_isp_stop(struct rkisp_device *dev) writel(0, base + CIF_ISP_IMSC); writel(~0, base + CIF_ISP_ICR); - if (dev->isp_ver == ISP_V20 || - dev->isp_ver == ISP_V21 || - dev->isp_ver == ISP_V30) { + if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 || + dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) { writel(0, base + ISP_ISP3A_IMSC); writel(~0, base + ISP_ISP3A_ICR); } @@ -1806,9 +1814,8 @@ static int rkisp_isp_stop(struct rkisp_device *dev) udelay(20); } /* stop lsc to avoid lsclut error */ - if (dev->isp_ver == ISP_V20 || - dev->isp_ver == ISP_V21 || - dev->isp_ver == ISP_V30) + if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 || + dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) writel(0, base + ISP_LSC_CTRL); /* stop ISP */ val = readl(base + CIF_ISP_CTRL); @@ -1849,9 +1856,8 @@ static int rkisp_isp_stop(struct rkisp_device *dev) writel(0, base + CIF_ISP_CSI0_MASK1); writel(0, base + CIF_ISP_CSI0_MASK2); writel(0, base + CIF_ISP_CSI0_MASK3); - } else if (dev->isp_ver == ISP_V20 || - dev->isp_ver == ISP_V21 || - dev->isp_ver == ISP_V30) { + } else if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 || + dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) { writel(0, base + CSI2RX_CSI2_RESETN); if (hw->is_unite) rkisp_next_write(dev, CSI2RX_CSI2_RESETN, 0, true); @@ -1864,11 +1870,10 @@ end: dev->hdr.op_mode = 0; rkisp_set_state(&dev->isp_state, ISP_STOP); - if (dev->isp_ver == ISP_V20 || - dev->isp_ver == ISP_V21 || - dev->isp_ver == ISP_V30) + if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 || + dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) kfifo_reset(&dev->rdbk_kfifo); - if (dev->isp_ver == ISP_V30) + if (dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) memset(&dev->cmsk_cfg, 0, sizeof(dev->cmsk_cfg)); if (dev->emd_vc <= CIF_ISP_ADD_DATA_VC_MAX) { for (i = 0; i < RKISP_EMDDATA_FIFO_MAX; i++) @@ -2403,6 +2408,10 @@ static int rkisp_isp_sd_get_selection(struct v4l2_subdev *sd, max_h = dev->hw_dev->is_unite ? CIF_ISP_INPUT_H_MAX_V30_UNITE : CIF_ISP_INPUT_H_MAX_V30; break; + case ISP_V32: + max_w = CIF_ISP_INPUT_W_MAX_V32; + max_h = CIF_ISP_INPUT_H_MAX_V32; + break; default: max_w = CIF_ISP_INPUT_W_MAX; max_h = CIF_ISP_INPUT_H_MAX; @@ -2455,19 +2464,17 @@ static int rkisp_isp_sd_set_selection(struct v4l2_subdev *sd, if (sel->pad == RKISP_ISP_PAD_SINK) { isp_sd->in_crop = *crop; - /* ISP20 don't have out crop */ - if (dev->isp_ver == ISP_V20 || - dev->isp_ver == ISP_V21 || - dev->isp_ver == ISP_V30) { + /* don't have out crop */ + if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 || + dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) { isp_sd->out_crop = *crop; isp_sd->out_crop.left = 0; isp_sd->out_crop.top = 0; dev->br_dev.crop = isp_sd->out_crop; } } else { - if (dev->isp_ver == ISP_V20 || - dev->isp_ver == ISP_V21 || - dev->isp_ver == ISP_V30) + if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 || + dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) *crop = isp_sd->out_crop; isp_sd->out_crop = *crop; } @@ -2546,6 +2553,7 @@ static void rkisp_global_update_mi(struct rkisp_device *dev) stream->ops->frame_end(stream); } } + rkisp_stats_next_ddr_config(&dev->stats_vdev); } static int rkisp_isp_sd_s_stream(struct v4l2_subdev *sd, int on) @@ -2574,9 +2582,9 @@ static int rkisp_isp_sd_s_stream(struct v4l2_subdev *sd, int on) } atomic_set(&isp_dev->isp_sdev.frm_sync_seq, 0); - rkisp_global_update_mi(isp_dev); rkisp_config_cif(isp_dev); rkisp_isp_start(isp_dev); + rkisp_global_update_mi(isp_dev); rkisp_rdbk_trigger_event(isp_dev, T_CMD_QUEUE, NULL); return 0; } @@ -2698,9 +2706,8 @@ static int rkisp_isp_sd_s_power(struct v4l2_subdev *sd, int on) "%s on:%d\n", __func__, on); if (on) { - if (isp_dev->isp_ver == ISP_V20 || - isp_dev->isp_ver == ISP_V21 || - isp_dev->isp_ver == ISP_V30) + if (isp_dev->isp_ver == ISP_V20 || isp_dev->isp_ver == ISP_V21 || + isp_dev->isp_ver == ISP_V30 || isp_dev->isp_ver == ISP_V32) kfifo_reset(&isp_dev->rdbk_kfifo); ret = pm_runtime_get_sync(isp_dev->dev); } else { diff --git a/drivers/media/platform/rockchip/isp/rkisp.h b/drivers/media/platform/rockchip/isp/rkisp.h index bb19692e8a87..97f433c0ac23 100644 --- a/drivers/media/platform/rockchip/isp/rkisp.h +++ b/drivers/media/platform/rockchip/isp/rkisp.h @@ -55,6 +55,8 @@ #define CIF_ISP_INPUT_H_MAX_V30 3504 #define CIF_ISP_INPUT_W_MAX_V30_UNITE 8192 #define CIF_ISP_INPUT_H_MAX_V30_UNITE 6144 +#define CIF_ISP_INPUT_W_MAX_V32 3072 +#define CIF_ISP_INPUT_H_MAX_V32 1728 #define CIF_ISP_INPUT_W_MIN 208 #define CIF_ISP_INPUT_H_MIN 128 #define CIF_ISP_OUTPUT_W_MAX CIF_ISP_INPUT_W_MAX diff --git a/include/uapi/linux/rkisp32-config.h b/include/uapi/linux/rkisp32-config.h new file mode 100644 index 000000000000..9ad883b9b6f2 --- /dev/null +++ b/include/uapi/linux/rkisp32-config.h @@ -0,0 +1,1371 @@ +/* SPDX-License-Identifier: (GPL-2.0+ WITH Linux-syscall-note) OR MIT + * + * Rockchip ISP32 + * Copyright (C) 2022 Rockchip Electronics Co., Ltd. + */ + +#ifndef _UAPI_RKISP32_CONFIG_H +#define _UAPI_RKISP32_CONFIG_H + +#include +#include +#include + +#define ISP32_MODULE_DPCC ISP3X_MODULE_DPCC +#define ISP32_MODULE_BLS ISP3X_MODULE_BLS +#define ISP32_MODULE_SDG ISP3X_MODULE_SDG +#define ISP32_MODULE_LSC ISP3X_MODULE_LSC +#define ISP32_MODULE_AWB_GAIN ISP3X_MODULE_AWB_GAIN +#define ISP32_MODULE_BDM ISP3X_MODULE_BDM +#define ISP32_MODULE_CCM ISP3X_MODULE_CCM +#define ISP32_MODULE_GOC ISP3X_MODULE_GOC +#define ISP32_MODULE_CPROC ISP3X_MODULE_CPROC +#define ISP32_MODULE_IE ISP3X_MODULE_IE +#define ISP32_MODULE_RAWAF ISP3X_MODULE_RAWAF +#define ISP32_MODULE_RAWAE0 ISP3X_MODULE_RAWAE0 +#define ISP32_MODULE_RAWAE1 ISP3X_MODULE_RAWAE1 +#define ISP32_MODULE_RAWAE2 ISP3X_MODULE_RAWAE2 +#define ISP32_MODULE_RAWAE3 ISP3X_MODULE_RAWAE3 +#define ISP32_MODULE_RAWAWB ISP3X_MODULE_RAWAWB +#define ISP32_MODULE_RAWHIST0 ISP3X_MODULE_RAWHIST0 +#define ISP32_MODULE_RAWHIST1 ISP3X_MODULE_RAWHIST1 +#define ISP32_MODULE_RAWHIST2 ISP3X_MODULE_RAWHIST2 +#define ISP32_MODULE_RAWHIST3 ISP3X_MODULE_RAWHIST3 +#define ISP32_MODULE_HDRMGE ISP3X_MODULE_HDRMGE +#define ISP32_MODULE_RAWNR ISP3X_MODULE_RAWNR +#define ISP32_MODULE_GIC ISP3X_MODULE_GIC +#define ISP32_MODULE_DHAZ ISP3X_MODULE_DHAZ +#define ISP32_MODULE_3DLUT ISP3X_MODULE_3DLUT +#define ISP32_MODULE_LDCH ISP3X_MODULE_LDCH +#define ISP32_MODULE_GAIN ISP3X_MODULE_GAIN +#define ISP32_MODULE_DEBAYER ISP3X_MODULE_DEBAYER +#define ISP32_MODULE_BAYNR ISP3X_MODULE_BAYNR +#define ISP32_MODULE_BAY3D ISP3X_MODULE_BAY3D +#define ISP32_MODULE_YNR ISP3X_MODULE_YNR +#define ISP32_MODULE_CNR ISP3X_MODULE_CNR +#define ISP32_MODULE_SHARP ISP3X_MODULE_SHARP +#define ISP32_MODULE_DRC ISP3X_MODULE_DRC +#define ISP32_MODULE_CAC ISP3X_MODULE_CAC +#define ISP32_MODULE_CSM ISP3X_MODULE_CSM + +/* Measurement types */ +#define ISP32_STAT_RAWAWB ISP3X_STAT_RAWAWB +#define ISP32_STAT_RAWAF ISP3X_STAT_RAWAF +#define ISP32_STAT_RAWAE0 ISP3X_STAT_RAWAE0 +#define ISP32_STAT_RAWAE1 ISP3X_STAT_RAWAE1 +#define ISP32_STAT_RAWAE2 ISP3X_STAT_RAWAE2 +#define ISP32_STAT_RAWAE3 ISP3X_STAT_RAWAE3 +#define ISP32_STAT_RAWHST0 ISP3X_STAT_RAWHST0 +#define ISP32_STAT_RAWHST1 ISP3X_STAT_RAWHST1 +#define ISP32_STAT_RAWHST2 ISP3X_STAT_RAWHST2 +#define ISP32_STAT_RAWHST3 ISP3X_STAT_RAWHST3 +#define ISP32_STAT_BLS ISP3X_STAT_BLS +#define ISP32_STAT_DHAZ ISP3X_STAT_DHAZ + +#define ISP32_MESH_BUF_NUM ISP3X_MESH_BUF_NUM + +#define ISP32_LSC_GRAD_TBL_SIZE ISP3X_LSC_GRAD_TBL_SIZE +#define ISP32_LSC_SIZE_TBL_SIZE ISP3X_LSC_SIZE_TBL_SIZE +#define ISP32_LSC_DATA_TBL_SIZE ISP3X_LSC_DATA_TBL_SIZE + +#define ISP32_DEGAMMA_CURVE_SIZE ISP3X_DEGAMMA_CURVE_SIZE + +#define ISP32_GAIN_IDX_NUM ISP3X_GAIN_IDX_NUM +#define ISP32_GAIN_LUT_NUM ISP3X_GAIN_LUT_NUM + +#define ISP32_RAWAWB_EXCL_STAT_NUM ISP3X_RAWAWB_EXCL_STAT_NUM +#define ISP32_RAWAWB_HSTBIN_NUM ISP3X_RAWAWB_HSTBIN_NUM +#define ISP32_RAWAWB_WEIGHT_NUM ISP3X_RAWAWB_WEIGHT_NUM +#define ISP32_RAWAWB_SUM_NUM 4 +#define ISP32_RAWAWB_RAMDATA_NUM ISP3X_RAWAWB_RAMDATA_NUM + +#define ISP32_RAWAEBIG_SUBWIN_NUM ISP3X_RAWAEBIG_SUBWIN_NUM +#define ISP32_RAWAEBIG_MEAN_NUM ISP3X_RAWAEBIG_MEAN_NUM +#define ISP32_RAWAELITE_MEAN_NUM ISP3X_RAWAELITE_MEAN_NUM + +#define ISP32_RAWHISTBIG_SUBWIN_NUM ISP3X_RAWHISTBIG_SUBWIN_NUM +#define ISP32_RAWHISTLITE_SUBWIN_NUM ISP3X_RAWHISTLITE_SUBWIN_NUM +#define ISP32_HIST_BIN_N_MAX ISP3X_HIST_BIN_N_MAX + +#define ISP32_RAWAF_CURVE_NUM ISP3X_RAWAF_CURVE_NUM +#define ISP32_RAWAF_HIIR_COE_NUM ISP3X_RAWAF_HIIR_COE_NUM +#define ISP32_RAWAF_VFIR_COE_NUM ISP3X_RAWAF_VFIR_COE_NUM +#define ISP32_RAWAF_WIN_NUM ISP3X_RAWAF_WIN_NUM +#define ISP32_RAWAF_LINE_NUM ISP3X_RAWAF_LINE_NUM +#define ISP32_RAWAF_GAMMA_NUM ISP3X_RAWAF_GAMMA_NUM +#define ISP32_RAWAF_SUMDATA_NUM ISP3X_RAWAF_SUMDATA_NUM +#define ISP32_RAWAF_VIIR_COE_NUM 3 +#define ISP32_RAWAF_GAUS_COE_NUM 9 + +#define ISP32_DPCC_PDAF_POINT_NUM ISP3X_DPCC_PDAF_POINT_NUM + +#define ISP32_HDRMGE_L_CURVE_NUM ISP3X_HDRMGE_L_CURVE_NUM +#define ISP32_HDRMGE_E_CURVE_NUM ISP3X_HDRMGE_E_CURVE_NUM + +#define ISP32_GIC_SIGMA_Y_NUM ISP3X_GIC_SIGMA_Y_NUM + +#define ISP32_CCM_CURVE_NUM 18 + +#define ISP32_3DLUT_DATA_NUM ISP3X_3DLUT_DATA_NUM + +#define ISP32_LDCH_MESH_XY_NUM ISP3X_LDCH_MESH_XY_NUM +#define ISP32_LDCH_BIC_NUM 36 + +#define ISP32_GAMMA_OUT_MAX_SAMPLES ISP3X_GAMMA_OUT_MAX_SAMPLES + +#define ISP32_DHAZ_SIGMA_IDX_NUM ISP3X_DHAZ_SIGMA_IDX_NUM +#define ISP32_DHAZ_SIGMA_LUT_NUM ISP3X_DHAZ_SIGMA_LUT_NUM +#define ISP32_DHAZ_HIST_WR_NUM ISP3X_DHAZ_HIST_WR_NUM +#define ISP32_DHAZ_ENH_CURVE_NUM ISP3X_DHAZ_ENH_CURVE_NUM +#define ISP32_DHAZ_HIST_IIR_NUM ISP3X_DHAZ_HIST_IIR_NUM +#define ISP32_DHAZ_ENH_LUMA_NUM 17 + +#define ISP32_DRC_Y_NUM ISP3X_DRC_Y_NUM + +#define ISP32_CNR_SIGMA_Y_NUM ISP3X_CNR_SIGMA_Y_NUM +#define ISP32_CNR_GAUS_COE_NUM 6 + +#define ISP32_YNR_XY_NUM ISP21_YNR_XY_NUM +#define ISP32_YNR_NLM_COE_NUM 6 + +#define ISP32_BAYNR_XY_NUM ISP3X_YNR_XY_NUM +#define ISP32_BAYNR_GAIN_NUM 16 + +#define ISP32_BAY3D_XY_NUM ISP3X_BAY3D_XY_NUM + +#define ISP32_SHARP_X_NUM ISP3X_SHARP_X_NUM +#define ISP32_SHARP_Y_NUM ISP3X_SHARP_Y_NUM +#define ISP32_SHARP_GAUS_COEF_NUM ISP3X_SHARP_GAUS_COEF_NUM +#define ISP32_SHARP_GAIN_ADJ_NUM 14 +#define ISP32_SHARP_STRENGTH_NUM 22 + +#define ISP32_CAC_STRENGTH_NUM ISP3X_CAC_STRENGTH_NUM + +#define ISP32_CSM_COEFF_NUM ISP3X_CSM_COEFF_NUM + +struct isp32_ldch_cfg { + u8 frm_end_dis; + u8 zero_interp_en; + u8 sample_avr_en; + u8 bic_mode_en; + u8 force_map_en; + u8 map13p3_en; + + u8 bicubic[ISP32_LDCH_BIC_NUM]; + + u32 hsize; + u32 vsize; + s32 buf_fd; +} __attribute__ ((packed)); + +struct isp32_awb_gain_cfg { + /* AWB1_GAIN_G */ + u16 awb1_gain_gb; + u16 awb1_gain_gr; + /* AWB1_GAIN_RB */ + u16 awb1_gain_b; + u16 awb1_gain_r; + /* AWB0_GAIN0_G */ + u16 gain0_green_b; + u16 gain0_green_r; + /* AWB0_GAIN0_RB*/ + u16 gain0_blue; + u16 gain0_red; + /* AWB0_GAIN1_G */ + u16 gain1_green_b; + u16 gain1_green_r; + /* AWB0_GAIN1_RB*/ + u16 gain1_blue; + u16 gain1_red; + /* AWB0_GAIN2_G */ + u16 gain2_green_b; + u16 gain2_green_r; + /* AWB0_GAIN2_RB*/ + u16 gain2_blue; + u16 gain2_red; +} __attribute__ ((packed)); + +struct isp32_bls_cfg { + u8 enable_auto; + u8 en_windows; + u8 bls1_en; + u8 bls2_en; + + u8 bls_samples; + + struct isp2x_window bls_window1; + struct isp2x_window bls_window2; + struct isp2x_bls_fixed_val fixed_val; + struct isp2x_bls_fixed_val bls1_val; + struct isp2x_bls_fixed_val bls2_val; + + u16 isp_ob_offset; + u16 isp_ob_predgain; + u32 isp_ob_max; +} __attribute__ ((packed)); + +struct isp32_ccm_cfg { + /* CTRL */ + u8 highy_adjust_dis; + u8 enh_adj_en; + u8 asym_adj_en; + /* BOUND_BIT */ + u8 bound_bit; + u8 right_bit; + /* COEFF0_R */ + s16 coeff0_r; + s16 coeff1_r; + /* COEFF1_R */ + s16 coeff2_r; + s16 offset_r; + /* COEFF0_G */ + s16 coeff0_g; + s16 coeff1_g; + /* COEFF1_G */ + s16 coeff2_g; + s16 offset_g; + /* COEFF0_B */ + s16 coeff0_b; + s16 coeff1_b; + /* COEFF1_B */ + s16 coeff2_b; + s16 offset_b; + /* COEFF0_Y */ + u16 coeff0_y; + u16 coeff1_y; + /* COEFF1_Y */ + u16 coeff2_y; + /* ALP_Y */ + u16 alp_y[ISP32_CCM_CURVE_NUM]; + /* ENHANCE0 */ + u16 color_coef0_r2y; + u16 color_coef1_g2y; + /* ENHANCE1 */ + u16 color_coef2_b2y; + u16 color_enh_rat_max; +} __attribute__ ((packed)); + +struct isp32_debayer_cfg { + /* CONTROL */ + u8 filter_g_en; + u8 filter_c_en; + /* G_INTERP */ + u8 clip_en; + u8 dist_scale; + u8 thed0; + u8 thed1; + u8 select_thed; + u8 max_ratio; + /* G_INTERP_FILTER1 */ + s8 filter1_coe1; + s8 filter1_coe2; + s8 filter1_coe3; + s8 filter1_coe4; + /* G_INTERP_FILTER2 */ + s8 filter2_coe1; + s8 filter2_coe2; + s8 filter2_coe3; + s8 filter2_coe4; + /* C_FILTER_GUIDE_GAUS */ + s8 guid_gaus_coe0; + s8 guid_gaus_coe1; + s8 guid_gaus_coe2; + /* C_FILTER_CE_GAUS */ + s8 ce_gaus_coe0; + s8 ce_gaus_coe1; + s8 ce_gaus_coe2; + /* C_FILTER_ALPHA_GAUS */ + s8 alpha_gaus_coe0; + s8 alpha_gaus_coe1; + s8 alpha_gaus_coe2; + /* C_FILTER_IIR_0 */ + u8 ce_sgm; + u8 exp_shift; + /* C_FILTER_IIR_1 */ + u8 wet_clip; + u8 wet_ghost; + /* C_FILTER_BF */ + u8 bf_clip; + u8 bf_curwgt; + u16 bf_sgm; + /* G_INTERP_OFFSET */ + u16 hf_offset; + u16 gain_offset; + /* G_FILTER_OFFSET */ + u16 offset; + /* C_FILTER_LOG_OFFSET */ + u16 loghf_offset; + u16 loggd_offset; + /* C_FILTER_IIR_0 */ + u16 wgtslope; + /* C_FILTER_ALPHA */ + u16 alpha_offset; + /* C_FILTER_EDGE */ + u16 edge_offset; + u32 edge_scale; + /* C_FILTER_ALPHA */ + u32 alpha_scale; +} __attribute__ ((packed)); + +struct isp32_baynr_cfg { + /* BAYNR_CTRL */ + u8 bay3d_gain_en; + u8 lg2_mode; + u8 gauss_en; + u8 log_bypass; + /* BAYNR_DGAIN */ + u16 dgain1; + u16 dgain0; + u16 dgain2; + /* BAYNR_PIXDIFF */ + u16 pix_diff; + /* BAYNR_THLD */ + u16 diff_thld; + u16 softthld; + /* BAYNR_W1_STRENG */ + u16 bltflt_streng; + u16 reg_w1; + /* BAYNR_SIGMA */ + u16 sigma_x[ISP32_BAYNR_XY_NUM]; + u16 sigma_y[ISP32_BAYNR_XY_NUM]; + /* BAYNR_WRIT_D */ + u16 weit_d2; + u16 weit_d1; + u16 weit_d0; + /* BAYNR_LG_OFF */ + u16 lg2_lgoff; + u16 lg2_off; + /* BAYNR_DAT_MAX */ + u32 dat_max; + /* BAYNR_SIGOFF */ + u16 rgain_off; + u16 bgain_off; + /* BAYNR_GAIN */ + u8 gain_x[ISP32_BAYNR_GAIN_NUM]; + u16 gain_y[ISP32_BAYNR_GAIN_NUM]; +} __attribute__ ((packed)); + +struct isp32_bay3d_cfg { + /* BAY3D_CTRL */ + u8 bypass_en; + u8 hibypass_en; + u8 lobypass_en; + u8 himed_bypass_en; + u8 higaus_bypass_en; + u8 hiabs_possel; + u8 hichnsplit_en; + u8 lomed_bypass_en; + u8 logaus5_bypass_en; + u8 logaus3_bypass_en; + u8 glbpk_en; + u8 loswitch_protect; + u8 bwsaving_en; + /* BAY3D_CTRL1 */ + u8 hiwgt_opt_en; + u8 hichncor_en; + u8 bwopt_gain_dis; + u8 lo4x8_en; + u8 lo4x4_en; + u8 hisig_ind_sel; + u8 pksig_ind_sel; + u8 iirwr_rnd_en; + u8 curds_high_en; + u8 higaus3_mode; + u8 higaus5x5_en; + u8 wgtmix_opt_en; + /* BAY3D_SIGGAUS */ + u8 siggaus0; + u8 siggaus1; + u8 siggaus2; + u8 siggaus3; + /* BAY3D_KALRATIO */ + u16 softwgt; + u16 hidif_th; + /* BAY3D_WGTLMT */ + u16 wgtlmt; + u16 wgtratio; + /* BAY3D_SIG */ + u16 sig0_x[ISP32_BAY3D_XY_NUM]; + u16 sig0_y[ISP32_BAY3D_XY_NUM]; + u16 sig1_x[ISP32_BAY3D_XY_NUM]; + u16 sig1_y[ISP32_BAY3D_XY_NUM]; + u16 sig2_x[ISP32_BAY3D_XY_NUM]; + u16 sig2_y[ISP32_BAY3D_XY_NUM]; + /* BAY3D_HISIGRAT */ + u16 hisigrat0; + u16 hisigrat1; + /* BAY3D_HISIGOFF */ + u16 hisigoff0; + u16 hisigoff1; + /* BAY3D_LOSIG */ + u16 losigoff; + u16 losigrat; + /* BAY3D_SIGPK */ + u16 rgain_off; + u16 bgain_off; + /* BAY3D_GLBPK2 */ + u32 glbpk2; +} __attribute__ ((packed)); + +struct isp32_ynr_cfg { + /* YNR_GLOBAL_CTRL */ + u8 rnr_en; + u8 thumb_mix_cur_en; + u8 global_gain_alpha; + u8 flt1x1_bypass_sel; + u8 nlm11x11_bypass; + u8 flt1x1_bypass; + u8 lgft3x3_bypass; + u8 lbft5x5_bypass; + u8 bft3x3_bypass; + /* YNR_RNR_STRENGTH */ + u8 rnr_strength3[ISP32_YNR_XY_NUM]; + /* YNR_NLM_SIGMA_GAIN */ + u8 nlm_hi_gain_alpha; + /* YNR_NLM_COE */ + u8 nlm_coe[ISP32_YNR_NLM_COE_NUM]; + + u16 global_gain; + + /* YNR_RNR_MAX_R */ + u16 rnr_max_r; + u16 local_gainscale; + /* YNR_RNR_CENTER_COOR */ + u16 rnr_center_coorh; + u16 rnr_center_coorv; + /* YNR_LOCAL_GAIN_CTRL */ + u16 loclagain_adj_thresh; + u16 localgain_adj; + /* YNR_LOWNR_CTRL0 */ + u16 low_bf_inv1; + u16 low_bf_inv0; + /* YNR_LOWNR_CTRL1 */ + u16 low_peak_supress; + u16 low_thred_adj; + /* YNR_LOWNR_CTRL2 */ + u16 low_dist_adj; + u16 low_edge_adj_thresh; + /* YNR_LOWNR_CTRL3 */ + u16 low_bi_weight; + u16 low_weight; + u16 low_center_weight; + /* YNR_LOWNR_CTRL4 */ + u16 frame_full_size; + u16 lbf_weight_thres; + /* YNR_GAUSS1_COEFF */ + u16 low_gauss1_coeff2; + u16 low_gauss1_coeff1; + u16 low_gauss1_coeff0; + /* YNR_GAUSS2_COEFF */ + u16 low_gauss2_coeff2; + u16 low_gauss2_coeff1; + u16 low_gauss2_coeff0; + /* YNR_SGM_DX */ + u16 luma_points_x[ISP32_YNR_XY_NUM]; + /* YNR_LSGM_Y */ + u16 lsgm_y[ISP32_YNR_XY_NUM]; + /* YNR_NLM_SIGMA_GAIN */ + u16 nlm_min_sigma; + u16 nlm_hi_bf_scale; + /* YNR_NLM_WEIGHT */ + u16 nlm_nr_weight; + u16 nlm_weight_offset; + /* YNR_NLM_NR_WEIGHT */ + u32 nlm_center_weight; +} __attribute__ ((packed)); + +struct isp32_cnr_cfg { + /* CNR_CTRL */ + u8 exgain_bypass; + u8 yuv422_mode; + u8 thumb_mode; + u8 bf3x3_wgt0_sel; + /* CNR_LBF_WEITD */ + u8 lbf1x7_weit_d0; + u8 lbf1x7_weit_d1; + u8 lbf1x7_weit_d2; + u8 lbf1x7_weit_d3; + /* CNR_IIR_PARA1 */ + u8 iir_uvgain; + u8 iir_strength; + u8 exp_shift; + /* CNR_IIR_PARA2 */ + u8 chroma_ghost; + u8 iir_uv_clip; + /* CNR_GAUS_COE */ + u8 gaus_coe[ISP32_CNR_GAUS_COE_NUM]; + /* CNR_GAUS_RATIO */ + u8 bf_wgt_clip; + /* CNR_BF_PARA1 */ + u8 uv_gain; + u8 bf_ratio; + /* CNR_SIGMA */ + u8 sigma_y[ISP32_CNR_SIGMA_Y_NUM]; + /* CNR_IIR_GLOBAL_GAIN */ + u8 iir_gain_alpha; + u8 iir_global_gain; + /* CNR_EXGAIN */ + u8 gain_iso; + u8 global_gain_alpha; + u16 global_gain; + /* CNR_THUMB1 */ + u16 thumb_sigma_c; + u16 thumb_sigma_y; + /* CNR_THUMB_BF_RATIO */ + u16 thumb_bf_ratio; + /* CNR_IIR_PARA1 */ + u16 wgt_slope; + /* CNR_GAUS_RATIO */ + u16 gaus_ratio; + u16 global_alpha; + /* CNR_BF_PARA1 */ + u16 sigma_r; + /* CNR_BF_PARA2 */ + u16 adj_offset; + u16 adj_ratio; +} __attribute__ ((packed)); + +struct isp32_sharp_cfg { + /* SHARP_EN */ + u8 bypass; + u8 center_mode; + u8 exgain_bypass; + u8 radius_ds_mode; + u8 noiseclip_mode; + /* SHARP_RATIO */ + u8 sharp_ratio; + u8 bf_ratio; + u8 gaus_ratio; + u8 pbf_ratio; + /* SHARP_LUMA_DX */ + u8 luma_dx[ISP32_SHARP_X_NUM]; + /* SHARP_SIGMA_SHIFT */ + u8 bf_sigma_shift; + u8 pbf_sigma_shift; + /* SHARP_PBF_COEF */ + u8 pbf_coef2; + u8 pbf_coef1; + u8 pbf_coef0; + /* SHARP_BF_COEF */ + u8 bf_coef2; + u8 bf_coef1; + u8 bf_coef0; + /* SHARP_GAUS_COEF */ + u8 gaus_coef[ISP32_SHARP_GAUS_COEF_NUM]; + /* SHARP_GAIN */ + u8 global_gain_alpha; + u8 local_gainscale; + /* SHARP_GAIN_DIS_STRENGTH */ + u8 strength[ISP32_SHARP_STRENGTH_NUM]; + /* SHARP_TEXTURE */ + u8 enhance_bit; + /* SHARP_PBF_SIGMA_INV */ + u16 pbf_sigma_inv[ISP32_SHARP_Y_NUM]; + /* SHARP_BF_SIGMA_INV */ + u16 bf_sigma_inv[ISP32_SHARP_Y_NUM]; + /* SHARP_CLIP_HF */ + u16 clip_hf[ISP32_SHARP_Y_NUM]; + /* SHARP_GAIN */ + u16 global_gain; + /* SHARP_GAIN_ADJUST */ + u16 gain_adj[ISP32_SHARP_GAIN_ADJ_NUM]; + /* SHARP_CENTER */ + u16 center_wid; + u16 center_het; + /* SHARP_TEXTURE */ + u16 noise_sigma; + u16 noise_strength; +} __attribute__ ((packed)); + +struct isp32_dhaz_cfg { + /* DHAZ_CTRL */ + u8 enh_luma_en; + u8 color_deviate_en; + u8 round_en; + u8 soft_wr_en; + u8 enhance_en; + u8 air_lc_en; + u8 hpara_en; + u8 hist_en; + u8 dc_en; + /* DHAZ_ADP0 */ + u8 yblk_th; + u8 yhist_th; + u8 dc_max_th; + u8 dc_min_th; + /* DHAZ_ADP2 */ + u8 tmax_base; + u8 dark_th; + u8 air_max; + u8 air_min; + /* DHAZ_GAUS */ + u8 gaus_h2; + u8 gaus_h1; + u8 gaus_h0; + /* DHAZ_GAIN_IDX */ + u8 sigma_idx[ISP32_DHAZ_SIGMA_IDX_NUM]; + /* DHAZ_ADP_HIST1 */ + u8 hist_gratio; + u16 hist_scale; + /* DHAZ_ADP1 */ + u8 bright_max; + u8 bright_min; + u16 wt_max; + /* DHAZ_ADP_TMAX */ + u16 tmax_max; + u16 tmax_off; + /* DHAZ_ADP_HIST0 */ + u8 hist_k; + u8 hist_th_off; + u16 hist_min; + /* DHAZ_ENHANCE */ + u16 enhance_value; + u16 enhance_chroma; + /* DHAZ_IIR0 */ + u16 iir_wt_sigma; + u8 iir_sigma; + u8 stab_fnum; + /* DHAZ_IIR1 */ + u16 iir_tmax_sigma; + u8 iir_air_sigma; + u8 iir_pre_wet; + /* DHAZ_SOFT_CFG0 */ + u16 cfg_wt; + u8 cfg_air; + u8 cfg_alpha; + /* DHAZ_SOFT_CFG1 */ + u16 cfg_gratio; + u16 cfg_tmax; + /* DHAZ_BF_SIGMA */ + u16 range_sima; + u8 space_sigma_pre; + u8 space_sigma_cur; + /* DHAZ_BF_WET */ + u16 dc_weitcur; + u16 bf_weight; + /* DHAZ_ENH_CURVE */ + u16 enh_curve[ISP32_DHAZ_ENH_CURVE_NUM]; + + u16 sigma_lut[ISP32_DHAZ_SIGMA_LUT_NUM]; + + u16 hist_wr[ISP32_DHAZ_HIST_WR_NUM]; + + u16 enh_luma[ISP32_DHAZ_ENH_LUMA_NUM]; +} __attribute__ ((packed)); + +struct isp32_drc_cfg { + u8 bypass_en; + /* DRC_CTRL1 */ + u8 offset_pow2; + u16 compres_scl; + u16 position; + /* DRC_LPRATIO */ + u16 hpdetail_ratio; + u16 lpdetail_ratio; + u8 delta_scalein; + /* DRC_EXPLRATIO */ + u8 weicur_pix; + u8 weipre_frame; + u8 bilat_wt_off; + /* DRC_SIGMA */ + u8 edge_scl; + u8 motion_scl; + u16 force_sgm_inv0; + /* DRC_SPACESGM */ + u16 space_sgm_inv1; + u16 space_sgm_inv0; + /* DRC_RANESGM */ + u16 range_sgm_inv1; + u16 range_sgm_inv0; + /* DRC_BILAT */ + u16 bilat_soft_thd; + u8 weig_maxl; + u8 weig_bilat; + u8 enable_soft_thd; + /* DRC_IIRWG_GAIN */ + u8 iir_weight; + u16 min_ogain; + /* DRC_LUM3X2_CTRL */ + u16 gas_t; + /* DRC_LUM3X2_GAS */ + u8 gas_l0; + u8 gas_l1; + u8 gas_l2; + u8 gas_l3; + + u16 gain_y[ISP32_DRC_Y_NUM]; + u16 compres_y[ISP32_DRC_Y_NUM]; + u16 scale_y[ISP32_DRC_Y_NUM]; +} __attribute__ ((packed)); + +struct isp32_hdrmge_cfg { + u8 s_base; + u8 mode; + u8 dbg_mode; + u8 each_raw_en; + + u8 gain2; + + u8 lm_dif_0p15; + u8 lm_dif_0p9; + u8 ms_diff_0p15; + u8 ms_dif_0p8; + + u16 gain0_inv; + u16 gain0; + u16 gain1_inv; + u16 gain1; + + u16 ms_thd1; + u16 ms_thd0; + u16 ms_scl; + u16 lm_thd1; + u16 lm_thd0; + u16 lm_scl; + struct isp2x_hdrmge_curve curve; + u16 e_y[ISP32_HDRMGE_E_CURVE_NUM]; + u16 l_raw0[ISP32_HDRMGE_E_CURVE_NUM]; + u16 l_raw1[ISP32_HDRMGE_E_CURVE_NUM]; + u16 each_raw_gain0; + u16 each_raw_gain1; +} __attribute__ ((packed)); + +struct isp32_rawawb_meas_cfg { + u8 rawawb_sel; + u8 bnr2awb_sel; + u8 drc2awb_sel; + /* RAWAWB_CTRL */ + u8 uv_en0; + u8 xy_en0; + u8 yuv3d_en0; + u8 yuv3d_ls_idx0; + u8 yuv3d_ls_idx1; + u8 yuv3d_ls_idx2; + u8 yuv3d_ls_idx3; + u8 in_rshift_to_12bit_en; + u8 in_overexposure_check_en; + u8 wind_size; + u8 rawlsc_bypass_en; + u8 light_num; + u8 ddr_path_en; + u8 uv_en1; + u8 xy_en1; + u8 yuv3d_en1; + u8 ddr_path_sel; + u8 low12bit_val; + /* RAWAWB_WEIGHT_CURVE_CTRL */ + u8 wp_luma_wei_en0; + u8 wp_luma_wei_en1; + u8 wp_blk_wei_en0; + u8 wp_blk_wei_en1; + u8 wp_hist_xytype; + /* RAWAWB_MULTIWINDOW_EXC_CTRL */ + u8 exc_wp_region0_excen; + u8 exc_wp_region0_measen; + u8 exc_wp_region0_domain; + u8 exc_wp_region1_excen; + u8 exc_wp_region1_measen; + u8 exc_wp_region1_domain; + u8 exc_wp_region2_excen; + u8 exc_wp_region2_measen; + u8 exc_wp_region2_domain; + u8 exc_wp_region3_excen; + u8 exc_wp_region3_measen; + u8 exc_wp_region3_domain; + u8 exc_wp_region4_excen; + u8 exc_wp_region4_domain; + u8 exc_wp_region5_excen; + u8 exc_wp_region5_domain; + u8 exc_wp_region6_excen; + u8 exc_wp_region6_domain; + u8 multiwindow_en; + /* RAWAWB_YWEIGHT_CURVE_XCOOR03 */ + u8 wp_luma_weicurve_y0; + u8 wp_luma_weicurve_y1; + u8 wp_luma_weicurve_y2; + u8 wp_luma_weicurve_y3; + /* RAWAWB_YWEIGHT_CURVE_XCOOR47 */ + u8 wp_luma_weicurve_y4; + u8 wp_luma_weicurve_y5; + u8 wp_luma_weicurve_y6; + u8 wp_luma_weicurve_y7; + /* RAWAWB_YWEIGHT_CURVE_XCOOR8 */ + u8 wp_luma_weicurve_y8; + /* RAWAWB_YWEIGHT_CURVE_YCOOR03 */ + u8 wp_luma_weicurve_w0; + u8 wp_luma_weicurve_w1; + u8 wp_luma_weicurve_w2; + u8 wp_luma_weicurve_w3; + /* RAWAWB_YWEIGHT_CURVE_YCOOR47 */ + u8 wp_luma_weicurve_w4; + u8 wp_luma_weicurve_w5; + u8 wp_luma_weicurve_w6; + u8 wp_luma_weicurve_w7; + /* RAWAWB_YWEIGHT_CURVE_YCOOR8 */ + u8 wp_luma_weicurve_w8; + /* RAWAWB_YUV_X1X2_DIS_0 */ + u8 dis_x1x2_ls0; + u8 rotu0_ls0; + u8 rotu1_ls0; + /* RAWAWB_YUV_INTERP_CURVE_UCOOR_0 */ + u8 rotu2_ls0; + u8 rotu3_ls0; + u8 rotu4_ls0; + u8 rotu5_ls0; + /* RAWAWB_YUV_X1X2_DIS_1 */ + u8 dis_x1x2_ls1; + u8 rotu0_ls1; + u8 rotu1_ls1; + /* YUV_INTERP_CURVE_UCOOR_1 */ + u8 rotu2_ls1; + u8 rotu3_ls1; + u8 rotu4_ls1; + u8 rotu5_ls1; + /* RAWAWB_YUV_X1X2_DIS_2 */ + u8 dis_x1x2_ls2; + u8 rotu0_ls2; + u8 rotu1_ls2; + /* YUV_INTERP_CURVE_UCOOR_2 */ + u8 rotu2_ls2; + u8 rotu3_ls2; + u8 rotu4_ls2; + u8 rotu5_ls2; + /* RAWAWB_YUV_X1X2_DIS_3 */ + u8 dis_x1x2_ls3; + u8 rotu0_ls3; + u8 rotu1_ls3; + u8 rotu2_ls3; + u8 rotu3_ls3; + u8 rotu4_ls3; + u8 rotu5_ls3; + /* RAWAWB_EXC_WP_WEIGHT */ + u8 exc_wp_region0_weight; + u8 exc_wp_region1_weight; + u8 exc_wp_region2_weight; + u8 exc_wp_region3_weight; + u8 exc_wp_region4_weight; + u8 exc_wp_region5_weight; + u8 exc_wp_region6_weight; + /* RAWAWB_WRAM_DATA */ + u8 wp_blk_wei_w[ISP32_RAWAWB_WEIGHT_NUM]; + /* RAWAWB_BLK_CTRL */ + u8 blk_measure_enable; + u8 blk_measure_mode; + u8 blk_measure_xytype; + u8 blk_rtdw_measure_en; + u8 blk_measure_illu_idx; + u8 blk_with_luma_wei_en; + u16 in_overexposure_threshold; + /* RAWAWB_LIMIT_RG_MAX*/ + u16 r_max; + u16 g_max; + /* RAWAWB_LIMIT_BY_MAX */ + u16 b_max; + u16 y_max; + /* RAWAWB_LIMIT_RG_MIN */ + u16 r_min; + u16 g_min; + /* RAWAWB_LIMIT_BY_MIN */ + u16 b_min; + u16 y_min; + /* RAWAWB_WIN_OFFS */ + u16 h_offs; + u16 v_offs; + /* RAWAWB_WIN_SIZE */ + u16 h_size; + u16 v_size; + /* RAWAWB_YWEIGHT_CURVE_YCOOR8 */ + u16 pre_wbgain_inv_r; + /* RAWAWB_PRE_WBGAIN_INV */ + u16 pre_wbgain_inv_g; + u16 pre_wbgain_inv_b; + /* RAWAWB_UV_DETC_VERTEX */ + u16 vertex0_u_0; + u16 vertex0_v_0; + + u16 vertex1_u_0; + u16 vertex1_v_0; + + u16 vertex2_u_0; + u16 vertex2_v_0; + + u16 vertex3_u_0; + u16 vertex3_v_0; + + u16 vertex0_u_1; + u16 vertex0_v_1; + + u16 vertex1_u_1; + u16 vertex1_v_1; + + u16 vertex2_u_1; + u16 vertex2_v_1; + + u16 vertex3_u_1; + u16 vertex3_v_1; + + u16 vertex0_u_2; + u16 vertex0_v_2; + + u16 vertex1_u_2; + u16 vertex1_v_2; + + u16 vertex2_u_2; + u16 vertex2_v_2; + + u16 vertex3_u_2; + u16 vertex3_v_2; + + u16 vertex0_u_3; + u16 vertex0_v_3; + + u16 vertex1_u_3; + u16 vertex1_v_3; + + u16 vertex2_u_3; + u16 vertex2_v_3; + + u16 vertex3_u_3; + u16 vertex3_v_3; + /* RAWAWB_RGB2XY_WT */ + u16 wt0; + u16 wt1; + u16 wt2; + /* RAWAWB_RGB2XY_MAT */ + u16 mat0_x; + u16 mat0_y; + + u16 mat1_x; + u16 mat1_y; + + u16 mat2_x; + u16 mat2_y; + /* RAWAWB_XY_DETC_NOR */ + u16 nor_x0_0; + u16 nor_x1_0; + u16 nor_y0_0; + u16 nor_y1_0; + + u16 nor_x0_1; + u16 nor_x1_1; + u16 nor_y0_1; + u16 nor_y1_1; + + u16 nor_x0_2; + u16 nor_x1_2; + u16 nor_y0_2; + u16 nor_y1_2; + + u16 nor_x0_3; + u16 nor_x1_3; + u16 nor_y0_3; + u16 nor_y1_3; + /* RAWAWB_XY_DETC_BIG */ + u16 big_x0_0; + u16 big_x1_0; + u16 big_y0_0; + u16 big_y1_0; + + u16 big_x0_1; + u16 big_x1_1; + u16 big_y0_1; + u16 big_y1_1; + + u16 big_x0_2; + u16 big_x1_2; + u16 big_y0_2; + u16 big_y1_2; + + u16 big_x0_3; + u16 big_x1_3; + u16 big_y0_3; + u16 big_y1_3; + /* RAWAWB_MULTIWINDOW */ + u16 multiwindow0_v_offs; + u16 multiwindow0_h_offs; + u16 multiwindow0_v_size; + u16 multiwindow0_h_size; + + u16 multiwindow1_v_offs; + u16 multiwindow1_h_offs; + u16 multiwindow1_v_size; + u16 multiwindow1_h_size; + + u16 multiwindow2_v_offs; + u16 multiwindow2_h_offs; + u16 multiwindow2_v_size; + u16 multiwindow2_h_size; + + u16 multiwindow3_v_offs; + u16 multiwindow3_h_offs; + u16 multiwindow3_v_size; + u16 multiwindow3_h_size; + /* RAWAWB_EXC_WP_REGION */ + u16 exc_wp_region0_xu0; + u16 exc_wp_region0_xu1; + + u16 exc_wp_region0_yv0; + u16 exc_wp_region0_yv1; + + u16 exc_wp_region1_xu0; + u16 exc_wp_region1_xu1; + + u16 exc_wp_region1_yv0; + u16 exc_wp_region1_yv1; + + u16 exc_wp_region2_xu0; + u16 exc_wp_region2_xu1; + + u16 exc_wp_region2_yv0; + u16 exc_wp_region2_yv1; + + u16 exc_wp_region3_xu0; + u16 exc_wp_region3_xu1; + + u16 exc_wp_region3_yv0; + u16 exc_wp_region3_yv1; + + u16 exc_wp_region4_xu0; + u16 exc_wp_region4_xu1; + + u16 exc_wp_region4_yv0; + u16 exc_wp_region4_yv1; + + u16 exc_wp_region5_xu0; + u16 exc_wp_region5_xu1; + + u16 exc_wp_region5_yv0; + u16 exc_wp_region5_yv1; + + u16 exc_wp_region6_xu0; + u16 exc_wp_region6_xu1; + + u16 exc_wp_region6_yv0; + u16 exc_wp_region6_yv1; + /* RAWAWB_YUV_RGB2ROTY */ + u16 rgb2ryuvmat0_y; + u16 rgb2ryuvmat1_y; + u16 rgb2ryuvmat2_y; + u16 rgb2ryuvofs_y; + /* RAWAWB_YUV_RGB2ROTU */ + u16 rgb2ryuvmat0_u; + u16 rgb2ryuvmat1_u; + u16 rgb2ryuvmat2_u; + u16 rgb2ryuvofs_u; + /* RAWAWB_YUV_RGB2ROTV */ + u16 rgb2ryuvmat0_v; + u16 rgb2ryuvmat1_v; + u16 rgb2ryuvmat2_v; + u16 rgb2ryuvofs_v; + /* RAWAWB_YUV_X_COOR */ + u16 coor_x1_ls0_y; + u16 vec_x21_ls0_y; + u16 coor_x1_ls0_u; + u16 vec_x21_ls0_u; + u16 coor_x1_ls0_v; + u16 vec_x21_ls0_v; + + u16 coor_x1_ls1_y; + u16 vec_x21_ls1_y; + u16 coor_x1_ls1_u; + u16 vec_x21_ls1_u; + u16 coor_x1_ls1_v; + u16 vec_x21_ls1_v; + + u16 coor_x1_ls2_y; + u16 vec_x21_ls2_y; + u16 coor_x1_ls2_u; + u16 vec_x21_ls2_v; + u16 coor_x1_ls2_v; + u16 vec_x21_ls2_u; + + u16 coor_x1_ls3_y; + u16 vec_x21_ls3_y; + u16 coor_x1_ls3_u; + u16 vec_x21_ls3_u; + u16 coor_x1_ls3_v; + u16 vec_x21_ls3_v; + /* RAWAWB_YUV_INTERP_CURVE_TH */ + u16 th0_ls0; + u16 th1_ls0; + u16 th2_ls0; + u16 th3_ls0; + u16 th4_ls0; + u16 th5_ls0; + + u16 th0_ls1; + u16 th1_ls1; + u16 th2_ls1; + u16 th3_ls1; + u16 th4_ls1; + u16 th5_ls1; + + u16 th0_ls2; + u16 th1_ls2; + u16 th2_ls2; + u16 th3_ls2; + u16 th4_ls2; + u16 th5_ls2; + + u16 th0_ls3; + u16 th1_ls3; + u16 th2_ls3; + u16 th3_ls3; + u16 th4_ls3; + u16 th5_ls3; + /* RAWAWB_UV_DETC_ISLOPE */ + u32 islope01_0; + u32 islope12_0; + u32 islope23_0; + u32 islope30_0; + u32 islope01_1; + u32 islope12_1; + u32 islope23_1; + u32 islope30_1; + u32 islope01_2; + u32 islope12_2; + u32 islope23_2; + u32 islope30_2; + u32 islope01_3; + u32 islope12_3; + u32 islope23_3; + u32 islope30_3; +} __attribute__ ((packed)); + +struct isp32_rawaf_meas_cfg { + u8 rawaf_sel; + u8 num_afm_win; + /* CTRL */ + u8 gamma_en; + u8 gaus_en; + u8 v1_fir_sel; + u8 hiir_en; + u8 viir_en; + u8 accu_8bit_mode; + u8 ldg_en; + u8 h1_fv_mode; + u8 h2_fv_mode; + u8 v1_fv_mode; + u8 v2_fv_mode; + u8 ae_mode; + u8 y_mode; + u8 vldg_sel; + u8 sobel_sel; + u8 v_dnscl_mode; + u8 from_awb; + u8 from_ynr; + u8 ae_config_use; + /* WINA_B */ + struct isp2x_window win[ISP32_RAWAF_WIN_NUM]; + /* INT_LINE */ + u8 line_num[ISP32_RAWAF_LINE_NUM]; + u8 line_en[ISP32_RAWAF_LINE_NUM]; + /* THRES */ + u16 afm_thres; + /* VAR_SHIFT */ + u8 afm_var_shift[ISP32_RAWAF_WIN_NUM]; + u8 lum_var_shift[ISP32_RAWAF_WIN_NUM]; + /* HVIIR_VAR_SHIFT */ + u8 h1iir_var_shift; + u8 h2iir_var_shift; + u8 v1iir_var_shift; + u8 v2iir_var_shift; + /* GAUS_COE */ + s8 gaus_coe[ISP32_RAWAF_GAUS_COE_NUM]; + + /* GAMMA_Y */ + u16 gamma_y[ISP32_RAWAF_GAMMA_NUM]; + /* HIIR_THRESH */ + u16 h_fv_thresh; + u16 v_fv_thresh; + struct isp3x_rawaf_curve curve_h[ISP32_RAWAF_CURVE_NUM]; + struct isp3x_rawaf_curve curve_v[ISP32_RAWAF_CURVE_NUM]; + s16 h1iir1_coe[ISP32_RAWAF_HIIR_COE_NUM]; + s16 h1iir2_coe[ISP32_RAWAF_HIIR_COE_NUM]; + s16 h2iir1_coe[ISP32_RAWAF_HIIR_COE_NUM]; + s16 h2iir2_coe[ISP32_RAWAF_HIIR_COE_NUM]; + s16 v1iir_coe[ISP32_RAWAF_VIIR_COE_NUM]; + s16 v2iir_coe[ISP32_RAWAF_VIIR_COE_NUM]; + s16 v1fir_coe[ISP32_RAWAF_VFIR_COE_NUM]; + s16 v2fir_coe[ISP32_RAWAF_VFIR_COE_NUM]; + u16 highlit_thresh; +} __attribute__ ((packed)); + +struct isp32_cac_cfg { + u8 bypass_en; + u8 center_en; + u8 clip_g_mode; + u8 edge_detect_en; + u8 neg_clip0_en; + + u8 flat_thed_b; + u8 flat_thed_r; + + u8 psf_sft_bit; + u16 cfg_num; + + u16 center_width; + u16 center_height; + + u16 strength[ISP32_CAC_STRENGTH_NUM]; + + u16 offset_b; + u16 offset_r; + + u32 expo_thed_b; + u32 expo_thed_r; + u32 expo_adj_b; + u32 expo_adj_r; + + u32 hsize; + u32 vsize; + s32 buf_fd; +} __attribute__ ((packed)); + +struct isp32_isp_other_cfg { + struct isp32_bls_cfg bls_cfg; + struct isp2x_dpcc_cfg dpcc_cfg; + struct isp3x_lsc_cfg lsc_cfg; + struct isp32_awb_gain_cfg awb_gain_cfg; + struct isp21_gic_cfg gic_cfg; + struct isp32_debayer_cfg debayer_cfg; + struct isp32_ccm_cfg ccm_cfg; + struct isp3x_gammaout_cfg gammaout_cfg; + struct isp2x_cproc_cfg cproc_cfg; + struct isp2x_ie_cfg ie_cfg; + struct isp2x_sdg_cfg sdg_cfg; + struct isp32_drc_cfg drc_cfg; + struct isp32_hdrmge_cfg hdrmge_cfg; + struct isp32_dhaz_cfg dhaz_cfg; + struct isp2x_3dlut_cfg isp3dlut_cfg; + struct isp32_ldch_cfg ldch_cfg; + struct isp32_baynr_cfg baynr_cfg; + struct isp32_bay3d_cfg bay3d_cfg; + struct isp32_ynr_cfg ynr_cfg; + struct isp32_cnr_cfg cnr_cfg; + struct isp32_sharp_cfg sharp_cfg; + struct isp32_cac_cfg cac_cfg; + struct isp3x_gain_cfg gain_cfg; + struct isp21_csm_cfg csm_cfg; +} __attribute__ ((packed)); + +struct isp32_isp_meas_cfg { + struct isp32_rawaf_meas_cfg rawaf; + struct isp32_rawawb_meas_cfg rawawb; + struct isp2x_rawaelite_meas_cfg rawae0; + struct isp2x_rawaebig_meas_cfg rawae1; + struct isp2x_rawaebig_meas_cfg rawae2; + struct isp2x_rawaebig_meas_cfg rawae3; + struct isp2x_rawhistlite_cfg rawhist0; + struct isp2x_rawhistbig_cfg rawhist1; + struct isp2x_rawhistbig_cfg rawhist2; + struct isp2x_rawhistbig_cfg rawhist3; +} __attribute__ ((packed)); + +struct isp32_rawae_meas_data { + u32 channelg_xy:12; + u32 channelb_xy:10; + u32 channelr_xy:10; +} __attribute__ ((packed)); + +struct isp32_rawaebig_stat0 { + struct isp32_rawae_meas_data data[ISP32_RAWAEBIG_MEAN_NUM]; + u32 reserved[3]; +} __attribute__ ((packed)); + +struct isp32_rawaebig_stat1 { + u32 sumr[ISP32_RAWAEBIG_SUBWIN_NUM]; + u32 sumg[ISP32_RAWAEBIG_SUBWIN_NUM]; + u32 sumb[ISP32_RAWAEBIG_SUBWIN_NUM]; +} __attribute__ ((packed)); + +struct isp32_rawaelite_stat { + struct isp32_rawae_meas_data data[ISP32_RAWAELITE_MEAN_NUM]; + u32 reserved[21]; +} __attribute__ ((packed)); + +struct isp32_rawaf_stat { + struct isp3x_rawaf_ramdata ramdata[ISP32_RAWAF_SUMDATA_NUM]; + u32 int_state; + u32 afm_sum_b; + u32 afm_lum_b; + u32 highlit_cnt_winb; + u32 reserved[21]; +} __attribute__ ((packed)); + +struct isp32_rawawb_ramdata { + u64 b:18; + u64 g:18; + u64 r:18; + u64 wp:10; +} __attribute__ ((packed)); + +struct isp32_rawawb_sum { + u32 rgain_nor; + u32 bgain_nor; + u32 wp_num_nor; + u32 wp_num2; + + u32 rgain_big; + u32 bgain_big; + u32 wp_num_big; + u32 reserved; +} __attribute__ ((packed)); + +struct isp32_rawawb_sum_exc { + u32 rgain_exc; + u32 bgain_exc; + u32 wp_num_exc; + u32 reserved; +} __attribute__ ((packed)); + +struct isp32_rawawb_meas_stat { + struct isp32_rawawb_ramdata ramdata[ISP32_RAWAWB_RAMDATA_NUM]; + u64 reserved; + struct isp32_rawawb_sum sum[ISP32_RAWAWB_SUM_NUM]; + u16 yhist_bin[ISP32_RAWAWB_HSTBIN_NUM]; + struct isp32_rawawb_sum_exc sum_exc[ISP32_RAWAWB_EXCL_STAT_NUM]; +} __attribute__ ((packed)); + +struct isp32_isp_params_cfg { + u64 module_en_update; + u64 module_ens; + u64 module_cfg_update; + + u32 frame_id; + struct isp32_isp_meas_cfg meas; + struct isp32_isp_other_cfg others; +} __attribute__ ((packed)); + +struct isp32_stat { + struct isp32_rawaebig_stat0 rawae3_0; //offset 0 + struct isp32_rawaebig_stat0 rawae1_0; //offset 0x390 + struct isp32_rawaebig_stat0 rawae2_0; //offset 0x720 + struct isp32_rawaelite_stat rawae0; //offset 0xab0 + struct isp32_rawaebig_stat1 rawae3_1; + struct isp32_rawaebig_stat1 rawae1_1; + struct isp32_rawaebig_stat1 rawae2_1; + struct isp2x_bls_stat bls; + struct isp2x_rawhistbig_stat rawhist3; //offset 0xc00 + struct isp2x_rawhistlite_stat rawhist0; //offset 0x1000 + struct isp2x_rawhistbig_stat rawhist1; //offset 0x1400 + struct isp2x_rawhistbig_stat rawhist2; //offset 0x1800 + struct isp32_rawaf_stat rawaf; //offset 0x1c00 + struct isp3x_dhaz_stat dhaz; + struct isp32_rawawb_meas_stat rawawb; //offset 0x2b00 +} __attribute__ ((packed)); + +/** + * struct rkisp32_isp_stat_buffer - Rockchip ISP32 Statistics Meta Data + * + * @meas_type: measurement types (ISP3X_STAT_ definitions) + * @frame_id: frame ID for sync + * @params: statistics data + */ +struct rkisp32_isp_stat_buffer { + struct isp32_stat params; + u32 meas_type; + u32 frame_id; +} __attribute__ ((packed)); + +#endif /* _UAPI_RKISP32_CONFIG_H */