From 8c0bf43f0955c8b86fc0adcfef08933904c56183 Mon Sep 17 00:00:00 2001 From: Ding Wei Date: Thu, 3 Mar 2022 17:04:22 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3588: Add node for avs plus decoder Change-Id: I3d2a4609fedb0ac27bc0b3b18de6908bbc01928d Signed-off-by: Ding Wei --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 673664ea2338..3465eb3be031 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -2610,7 +2610,7 @@ assigned-clocks = <&cru ACLK_VPU>; assigned-clock-rates = <594000000>; resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>; - reset-names = "video_a", "video_h"; + reset-names = "shared_video_a", "shared_video_h"; rockchip,skip-pmu-idle-request; iommus = <&vdpu_mmu>; rockchip,srv = <&mpp_srv>; @@ -2631,6 +2631,22 @@ status = "disabled"; }; + avsd: avsd-plus@fdb51000 { + compatible = "rockchip,avs-plus-decoder"; + reg = <0x0 0xfdb51000 0x0 0x200>; + interrupts = ; + interrupt-names = "irq_avsd"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>; + reset-names = "shared_video_a", "shared_video_h"; + iommus = <&vdpu_mmu>; + power-domains = <&power RK3588_PD_VDPU>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <0>; + status = "disabled"; + }; + rga3_core0: rga@fdb60000 { compatible = "rockchip,rga3_core0"; reg = <0x0 0xfdb60000 0x0 0x1000>;