1,add ddr_change_freq function, and support menuconfig to change DDR frequce

2,DDR3 ODT use 120ohm, to save power
  3,decrease auto power-down idle cnt to 0x40, to save power
  4,resolve ddr_suspend and ddr_resume problem
  5,enable ddr_testmode in pm.c

arch/arm/mach-rk30/common.c

@@ -14,6 +14,7 @@
 #include <mach/fiq.h>
 #include <mach/pmu.h>
 #include <mach/loader.h>
+#include <mach/ddr.h>
 
 static void __init rk30_cpu_axi_init(void)
 {
@@ -127,6 +128,7 @@ void __init rk30_map_io(void)
 	rk29_sram_init();
 	board_clock_init();
 	rk30_l2_cache_init();
+    ddr_init(DDR_TYPE, DDR_FREQ);
 	rk30_iomux_init();
 	rk30_boot_mode_init();
 }

arch/arm/mach-rk30/include/mach/ddr.h

@@ -0,0 +1,152 @@
+/* arch/arm/mach-rk30/include/mach/ddr.h
+ *
+ * Copyright (C) 2011 ROCKCHIP, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_RK30_DDR_H
+#define __ARCH_ARM_MACH_RK30_DDR_H
+
+#include <linux/types.h>
+#include <mach/sram.h>
+
+#ifdef CONFIG_DDR_SDRAM_FREQ
+#define DDR_FREQ          (CONFIG_DDR_SDRAM_FREQ)
+#else
+#define DDR_FREQ 400
+#endif
+
+#define DDR3_800D   (0)     // 5-5-5
+#define DDR3_800E   (1)     // 6-6-6
+#define DDR3_1066E  (2)     // 6-6-6
+#define DDR3_1066F  (3)     // 7-7-7
+#define DDR3_1066G  (4)     // 8-8-8
+#define DDR3_1333F  (5)     // 7-7-7
+#define DDR3_1333G  (6)     // 8-8-8
+#define DDR3_1333H  (7)     // 9-9-9
+#define DDR3_1333J  (8)     // 10-10-10
+#define DDR3_1600G  (9)     // 8-8-8
+#define DDR3_1600H  (10)    // 9-9-9
+#define DDR3_1600J  (11)    // 10-10-10
+#define DDR3_1600K  (12)    // 11-11-11
+#define DDR3_1866J  (13)    // 10-10-10
+#define DDR3_1866K  (14)    // 11-11-11
+#define DDR3_1866L  (15)    // 12-12-12
+#define DDR3_1866M  (16)    // 13-13-13
+#define DDR3_2133K  (17)    // 11-11-11
+#define DDR3_2133L  (18)    // 12-12-12
+#define DDR3_2133M  (19)    // 13-13-13
+#define DDR3_2133N  (20)    // 14-14-14
+#define DDR3_DEFAULT (21)
+#define DDR_DDR2     (22)
+#define DDR_LPDDR    (23)
+#define DDR_LPDDR2   (24)
+
+#ifdef CONFIG_DDR_TYPE_DDR3_800D
+#define DDR_TYPE DDR3_800D
+#endif
+
+#ifdef CONFIG_DDR_TYPE_DDR3_800E
+#define DDR_TYPE DDR3_800E
+#endif
+
+#ifdef CONFIG_DDR_TYPE_DDR3_1066E
+#define DDR_TYPE DDR3_1066E
+#endif
+
+#ifdef CONFIG_DDR_TYPE_DDR3_1066F
+#define DDR_TYPE DDR3_1066F
+#endif
+
+#ifdef CONFIG_DDR_TYPE_DDR3_1066G
+#define DDR_TYPE DDR3_1066G
+#endif
+
+#ifdef CONFIG_DDR_TYPE_DDR3_1333F
+#define DDR_TYPE DDR3_1333F
+#endif
+
+#ifdef CONFIG_DDR_TYPE_DDR3_1333G
+#define DDR_TYPE DDR3_1333G
+#endif
+
+#ifdef CONFIG_DDR_TYPE_DDR3_1333H
+#define DDR_TYPE DDR3_1333H
+#endif
+
+#ifdef CONFIG_DDR_TYPE_DDR3_1333J
+#define DDR_TYPE DDR3_1333J
+#endif
+
+#ifdef CONFIG_DDR_TYPE_DDR3_1600G
+#define DDR_TYPE DDR3_1600G
+#endif
+
+#ifdef CONFIG_DDR_TYPE_DDR3_1600H
+#define DDR_TYPE DDR3_1600H
+#endif
+
+#ifdef CONFIG_DDR_TYPE_DDR3_1600J
+#define DDR_TYPE DDR3_1600J
+#endif
+
+#ifdef CONFIG_DDR_TYPE_DDR3_1866J
+#define DDR_TYPE DDR3_1866J
+#endif
+
+#ifdef CONFIG_DDR_TYPE_DDR3_1866K
+#define DDR_TYPE DDR3_1866K
+#endif
+
+#ifdef CONFIG_DDR_TYPE_DDR3_1866L
+#define DDR_TYPE DDR3_1866L
+#endif
+
+#ifdef CONFIG_DDR_TYPE_DDR3_1866M
+#define DDR_TYPE DDR3_1866M
+#endif
+
+#ifdef CONFIG_DDR_TYPE_DDR3_2133K
+#define DDR_TYPE DDR3_2133K
+#endif
+
+#ifdef CONFIG_DDR_TYPE_DDR3_2133L
+#define DDR_TYPE DDR3_2133L
+#endif
+
+#ifdef CONFIG_DDR_TYPE_DDR3_2133M
+#define DDR_TYPE DDR3_2133M
+#endif
+
+#ifdef CONFIG_DDR_TYPE_DDR3_2133N
+#define DDR_TYPE DDR3_2133N
+#endif
+
+#ifdef CONFIG_DDR_TYPE_DDR3_DEFAULT
+#define DDR_TYPE DDR3_DEFAULT
+#endif
+
+#ifdef CONFIG_DDR_TYPE_DDRII
+#define DDR_TYPE DDR_DDRII
+#endif
+
+#ifdef CONFIG_DDR_TYPE_LPDDR
+#define DDR_TYPE DDR_LPDDR
+#endif
+
+void __sramfunc ddr_suspend(void);
+void __sramfunc ddr_resume(void);
+//void __sramlocalfunc delayus(uint32_t us);
+uint32_t __sramfunc ddr_change_freq(uint32_t nMHz);
+int ddr_init(uint32_t dram_type, uint32_t freq);
+
+#endif

arch/arm/mach-rk30/pm.c

@@ -21,6 +21,7 @@
 #include <mach/gpio.h>
 #include <mach/iomux.h>
 #include <mach/cru.h>
+#include <mach/ddr.h>
 
 #define cru_readl(offset)	readl_relaxed(RK30_CRU_BASE + offset)
 #define cru_writel(v, offset)	do { writel_relaxed(v, RK30_CRU_BASE + offset); dsb(); } while (0)
@@ -73,7 +74,7 @@ void __sramfunc sram_printch(char byte)
 }
 
 #ifdef CONFIG_DDR_TEST
-static int ddr_debug;
+static int ddr_debug=0;
 module_param(ddr_debug, int, 0644);
 
 static int inline calc_crc32(u32 addr, size_t len)
@@ -90,13 +91,14 @@ static void __sramfunc ddr_testmode(void)
 
 	if (ddr_debug == 1) {
 		for (;;) {
-			sram_printascii("change freq\n");
+			sram_printascii("\n change freq:");
 			g_crc1 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
-			nMHz = 333 + random32();
-			nMHz %= 490;
-			if (nMHz < 100)
-				nMHz = 100;
-//			nMHz = ddr_change_freq(nMHz);
+			do
+			{
+			    nMHz = 300 + random32();
+			    nMHz %= 500;
+			}while(nMHz < 300);
+			nMHz = ddr_change_freq(nMHz);
 			sram_printhex(nMHz);
 			sram_printch(' ');
 			sram_printhex(n++);
@@ -117,9 +119,9 @@ static void __sramfunc ddr_testmode(void)
 			sram_printch(' ');
 			g_crc1 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
 			nMHz = (random32()>>13);// 16.7s max
-//			ddr_suspend();
-//			delayus(nMHz);
-//			ddr_resume();
+			ddr_suspend();
+			sram_udelay(nMHz);
+			ddr_resume();
 			sram_printhex(nMHz);
 			sram_printch(' ');
 			sram_printhex(n++);
@@ -217,8 +219,8 @@ static void pm_pll_wait_lock(int pll_idx)
 
 static unsigned long save_sp;
 
-extern void __sramfunc ddr_selfrefresh_enter(void);
-extern void __sramfunc ddr_selfrefresh_exit(void);
+//extern void __sramfunc ddr_selfrefresh_enter(void);
+//extern void __sramfunc ddr_selfrefresh_exit(void);
 
 static noinline void interface_ctr_reg_pread(void)
 {
@@ -321,7 +323,7 @@ static void __sramfunc rk30_sram_suspend(void)
 	int i;
 
 	sram_printch('5');
-	ddr_selfrefresh_enter();
+	ddr_suspend();
 	sram_printch('6');
 
 	for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
@@ -369,7 +371,7 @@ static void __sramfunc rk30_sram_suspend(void)
 	}
 
 	sram_printch('6');
-	ddr_selfrefresh_exit();
+	ddr_resume();
 	sram_printch('5');
 }
 
@@ -389,12 +391,6 @@ static int rk30_pm_enter(suspend_state_t state)
 	u32 cru_mode_con;
 	u32 pmu_pwrdn_st;
 
-#ifdef CONFIG_DDR_TEST
-	// memory tester
-	if (ddr_debug != 2)
-		ddr_testmode();
-#endif
-
 	// dump GPIO INTEN for debug
 	rk30_pm_dump_inten();
 
@@ -407,6 +403,12 @@ static int rk30_pm_enter(suspend_state_t state)
 	pmu_pwrdn_st = pmu_readl(PMU_PWRDN_ST);
 	rk30_pm_set_power_domain(pmu_pwrdn_st, false);
 
+	#ifdef CONFIG_DDR_TEST
+	// memory tester
+	if (ddr_debug != 0)
+		ddr_testmode();
+    #endif
+
 	sram_printch('1');
 	local_fiq_disable();