From 8c42cecbaaafec190efea33cb8fb7fd365cdd902 Mon Sep 17 00:00:00 2001 From: Algea Cao Date: Sun, 18 Feb 2024 10:01:02 +0800 Subject: [PATCH] phy: rockchip-samsung-hdptx-hdmi: Remove phy/pll reset These are ic debug reset, practically unusable. Change-Id: Ibc5817ccf9d17abf35d1ff32c2a047866ef1dd2f Signed-off-by: Algea Cao --- .../phy-rockchip-samsung-hdptx-hdmi.c | 42 +------------------ 1 file changed, 1 insertion(+), 41 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx-hdmi.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx-hdmi.c index 0ff63760be46..defa3a498fbd 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx-hdmi.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx-hdmi.c @@ -719,13 +719,10 @@ struct rockchip_hdptx_phy { struct clk *dclk; unsigned long rate; - struct reset_control *phy_reset; struct reset_control *apb_reset; struct reset_control *cmn_reset; struct reset_control *init_reset; struct reset_control *lane_reset; - struct reset_control *ropll_reset; - struct reset_control *lcpll_reset; bool earc_en; int count; @@ -990,11 +987,7 @@ static void hdptx_phy_disable(struct rockchip_hdptx_phy *hdptx) { u32 val; - /* reset phy and apb, or phy locked flag may keep 1 */ - reset_control_assert(hdptx->phy_reset); - udelay(20); - reset_control_deassert(hdptx->phy_reset); - + /* reset apb, or phy locked flag may keep 1 */ reset_control_assert(hdptx->apb_reset); udelay(20); reset_control_deassert(hdptx->apb_reset); @@ -1203,10 +1196,6 @@ static int hdptx_ropll_cmn_config(struct rockchip_hdptx_phy *hdptx, unsigned lon hdptx_pre_power_up(hdptx); - reset_control_assert(hdptx->ropll_reset); - udelay(20); - reset_control_deassert(hdptx->ropll_reset); - hdptx_grf_write(hdptx, GRF_HDPTX_CON0, LC_REF_CLK_SEL << 16); hdptx_write(hdptx, CMN_REG0008, 0x00); @@ -1480,14 +1469,6 @@ static int hdptx_lcpll_ropll_cmn_config(struct rockchip_hdptx_phy *hdptx, unsign hdptx_pre_power_up(hdptx); - reset_control_assert(hdptx->ropll_reset); - udelay(20); - reset_control_deassert(hdptx->ropll_reset); - - reset_control_assert(hdptx->lcpll_reset); - udelay(20); - reset_control_deassert(hdptx->lcpll_reset); - /* ROPLL input reference clock from LCPLL (cascade mode) */ val = (LC_REF_CLK_SEL << 16) | LC_REF_CLK_SEL; hdptx_grf_write(hdptx, GRF_HDPTX_CON0, val); @@ -2271,13 +2252,6 @@ static int rockchip_hdptx_phy_probe(struct platform_device *pdev) goto err_regsmap; } - hdptx->phy_reset = devm_reset_control_get(dev, "phy"); - if (IS_ERR(hdptx->phy_reset)) { - ret = PTR_ERR(hdptx->phy_reset); - dev_err(dev, "failed to get phy reset: %d\n", ret); - goto err_regsmap; - } - hdptx->apb_reset = devm_reset_control_get(dev, "apb"); if (IS_ERR(hdptx->apb_reset)) { ret = PTR_ERR(hdptx->apb_reset); @@ -2306,20 +2280,6 @@ static int rockchip_hdptx_phy_probe(struct platform_device *pdev) goto err_regsmap; } - hdptx->ropll_reset = devm_reset_control_get(dev, "ropll"); - if (IS_ERR(hdptx->ropll_reset)) { - ret = PTR_ERR(hdptx->ropll_reset); - dev_err(dev, "failed to get ropll reset: %d\n", ret); - goto err_regsmap; - } - - hdptx->lcpll_reset = devm_reset_control_get(dev, "lcpll"); - if (IS_ERR(hdptx->lcpll_reset)) { - ret = PTR_ERR(hdptx->lcpll_reset); - dev_err(dev, "failed to get lcpll reset: %d\n", ret); - goto err_regsmap; - } - hdptx->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); if (IS_ERR(hdptx->grf)) { ret = PTR_ERR(hdptx->grf);