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clk: rockchip: rk3399: Modify dummy clock for VOP dclks

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Because frac div need to more than 20 multiple between the numerator
and denominator, but we need to be fit many HDMI/DP freqs and may
bring serious jitter when the dclk_vopx below the dclk_vopx_frac.

Therefore, we can select dclk_vopx below the dclk_vopx_div directly.

Change-Id: If3d9051211f0b160a507f0942667796f043f4ec2
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
This commit is contained in:
Xing Zheng
2016-04-07 13:39:08 +08:00
committed by Gerrit Code Review
parent 46265c1e20
commit 8d01ea2168
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/rockchip/clk-rk3399.c
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@@ -147,8 +147,8 @@ PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" };
PNAME(mux_pll_src_dmyvpll_cpll_gpll_npll_p) = { "dummy_vpll", "cpll", "gpll", "npll" };
PNAME(mux_pll_src_dmyvpll_cpll_gpll_24m_p) = { "dummy_vpll", "cpll", "gpll", "xin24m" };
PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div", "dclk_vop0_frac" };
PNAME(mux_dclk_vop1_p) = { "dclk_vop1_div", "dclk_vop1_frac" };
PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div", "dummy_dclk_vop0_frac" };
PNAME(mux_dclk_vop1_p) = { "dclk_vop1_div", "dummy_dclk_vop1_frac" };
PNAME(mux_clk_cif_p) = { "clk_cifout_div", "xin24m" };