From 8e32ff5d7ed2d90c0ef7e76e91c0f359e4e6ff0f Mon Sep 17 00:00:00 2001
From: Huang zhibao <hzb@rock-chips.com>
Date: Tue, 22 Feb 2022 15:19:40 +0800
Subject: [PATCH] arm64: dts: rockchip: rk3588-nvr: swap cpu big and little

Signed-off-by: Huang zhibao <hzb@rock-chips.com>
Change-Id: I4e3a57f5a61717dbb7577b5ac8cf0d0352489303
---
 .../boot/dts/rockchip/rk3588-cpu-swap.dtsi    | 87 +++++++++++++++++++
 arch/arm64/boot/dts/rockchip/rk3588-nvr.dtsi  |  1 +
 2 files changed, 88 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-cpu-swap.dtsi

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-cpu-swap.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-cpu-swap.dtsi
new file mode 100644
index 000000000000..a20a443dd774
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588-cpu-swap.dtsi
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ */
+
+/delete-node/ &cpu_l0;
+/delete-node/ &cpu_l1;
+/delete-node/ &cpu_l2;
+/delete-node/ &cpu_l3;
+
+/ {
+	cpus {
+		cpu_l0: cpu@0000 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <530>;
+			clocks = <&scmi_clk SCMI_CLK_CPUL>;
+			operating-points-v2 = <&cluster0_opp_table>;
+			cpu-idle-states = <&CPU_SLEEP>;
+			i-cache-size = <32768>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_cache_l0>;
+			#cooling-cells = <2>;
+			dynamic-power-coefficient = <228>;
+		};
+
+		cpu_l1: cpu@0100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x100>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <530>;
+			clocks = <&scmi_clk SCMI_CLK_CPUL>;
+			operating-points-v2 = <&cluster0_opp_table>;
+			cpu-idle-states = <&CPU_SLEEP>;
+			i-cache-size = <32768>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_cache_l1>;
+		};
+
+		cpu_l2: cpu@0200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x200>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <530>;
+			clocks = <&scmi_clk SCMI_CLK_CPUL>;
+			operating-points-v2 = <&cluster0_opp_table>;
+			cpu-idle-states = <&CPU_SLEEP>;
+			i-cache-size = <32768>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_cache_l2>;
+		};
+
+		cpu_l3: cpu@0300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x300>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <530>;
+			clocks = <&scmi_clk SCMI_CLK_CPUL>;
+			operating-points-v2 = <&cluster0_opp_table>;
+			cpu-idle-states = <&CPU_SLEEP>;
+			i-cache-size = <32768>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_cache_l3>;
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nvr.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nvr.dtsi
index 5e319297d369..3e0136f714ed 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-nvr.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-nvr.dtsi
@@ -11,6 +11,7 @@
 #include <dt-bindings/display/drm_mipi_dsi.h>
 #include <dt-bindings/display/rockchip_vop.h>
 #include <dt-bindings/sensor-dev.h>
+#include "rk3588-cpu-swap.dtsi"
 
 / {
 	adc_keys: adc-keys {