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Merge tag 'clk-imx-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx
Pull i.MX clk driver updates from Abel Vesa: - Remove audio ipg clock from i.MX8MP - Fix naming typo of clock compatible string - Remove deprecated legacy clock binding for SCU clock driver - Use common clk-imx8qxp for both i.MX8QXP and i.MX8QM - Add multiple clocks to clk-imx8qxp driver (enet, hdmi, lcdif, audio, parallel interface) - Add dedicated clock ops for paralel interface - Different fixes for clocks controlled by ATF - Fix different issues related to parallel interface clocks - Add A53/A72 frequency scaling support clk-scu driver - Add special case for DCSS clock on suspend for clk-scu driver - Add parent save/restore on suspend/resume to clk-scu driver - Skip runtime PM enablement for CPU clocks in clk-scu driver - Remove the sys1_pll/sys2_pll clock gates for i.MX8MQ and their bindings * tag 'clk-imx-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux: clk: imx8mq: remove SYS PLL 1/2 clock gates clk: imx: scu: Do not enable runtime PM for CPU clks clk: imx: scu: add parent save and restore clk: imx: scu: Only save DC SS clock using non-cached clock rate clk: imx: scu: Add A72 frequency scaling support clk: imx: scu: Add A53 frequency scaling support clk: imx: scu: bypass pi_pll enable status restore clk: imx: scu: detach pd if can't power up clk: imx: scu: bypass cpu clock save and restore clk: imx: scu: add parallel port clock ops clk: imx: scu: add more scu clocks clk: imx: scu: add enet rgmii gpr clocks clk: imx8qm: add clock valid resource checking clk: imx8qxp: add clock valid checking mechnism clk: imx: scu: add gpr clocks support clk: imx: scu: remove legacy scu clock binding support dt-bindings: arm: imx: scu: drop deprecated legacy clock binding dt-bindings: arm: imx: scu: fix naming typo of clk compatible string clk: imx: Remove the audio ipg clock from imx8mp
This commit is contained in:
Stephen Boyd
@@ -86,13 +86,11 @@ This binding uses the common clock binding[1].
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Required properties:
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- compatible: Should be one of:
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"fsl,imx8qm-clock"
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"fsl,imx8qxp-clock"
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"fsl,imx8qm-clk"
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"fsl,imx8qxp-clk"
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followed by "fsl,scu-clk"
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- #clock-cells: Should be either
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2: Contains the Resource and Clock ID value.
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or
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1: Contains the Clock ID value. (DEPRECATED)
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- #clock-cells: Should be 2.
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Contains the Resource and Clock ID value.
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- clocks: List of clock specifiers, must contain an entry for
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each required entry in clock-names
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- clock-names: Should include entries "xtal_32KHz", "xtal_24MHz"
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@@ -27,7 +27,8 @@ obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o
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obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
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obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o
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clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o
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clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o \
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clk-imx8qxp-rsrc.o clk-imx8qm-rsrc.o
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clk-imx-lpcg-scu-$(CONFIG_CLK_IMX8QXP) += clk-lpcg-scu.o clk-imx8qxp-lpcg.o
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obj-$(CONFIG_CLK_IMX1) += clk-imx1.o
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@@ -556,7 +556,6 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
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hws[IMX8MP_CLK_MIPI_DSI_ESC_RX] = imx8m_clk_hw_composite_bus("mipi_dsi_esc_rx", imx8mp_mipi_dsi_esc_rx_sels, ccm_base + 0x9200);
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hws[IMX8MP_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb_root", ccm_base + 0x9080, 0, 1);
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hws[IMX8MP_CLK_IPG_AUDIO_ROOT] = imx_clk_hw_divider2("ipg_audio_root", "audio_ahb", ccm_base + 0x9180, 0, 1);
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hws[IMX8MP_CLK_DRAM_ALT] = imx8m_clk_hw_composite("dram_alt", imx8mp_dram_alt_sels, ccm_base + 0xa000);
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hws[IMX8MP_CLK_DRAM_APB] = imx8m_clk_hw_composite_critical("dram_apb", imx8mp_dram_apb_sels, ccm_base + 0xa080);
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@@ -358,46 +358,26 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
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hws[IMX8MQ_VIDEO2_PLL_OUT] = imx_clk_hw_sscg_pll("video2_pll_out", video2_pll_out_sels, ARRAY_SIZE(video2_pll_out_sels), 0, 0, 0, base + 0x54, 0);
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/* SYS PLL1 fixed output */
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hws[IMX8MQ_SYS1_PLL_40M_CG] = imx_clk_hw_gate("sys1_pll_40m_cg", "sys1_pll_out", base + 0x30, 9);
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hws[IMX8MQ_SYS1_PLL_80M_CG] = imx_clk_hw_gate("sys1_pll_80m_cg", "sys1_pll_out", base + 0x30, 11);
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hws[IMX8MQ_SYS1_PLL_100M_CG] = imx_clk_hw_gate("sys1_pll_100m_cg", "sys1_pll_out", base + 0x30, 13);
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hws[IMX8MQ_SYS1_PLL_133M_CG] = imx_clk_hw_gate("sys1_pll_133m_cg", "sys1_pll_out", base + 0x30, 15);
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hws[IMX8MQ_SYS1_PLL_160M_CG] = imx_clk_hw_gate("sys1_pll_160m_cg", "sys1_pll_out", base + 0x30, 17);
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hws[IMX8MQ_SYS1_PLL_200M_CG] = imx_clk_hw_gate("sys1_pll_200m_cg", "sys1_pll_out", base + 0x30, 19);
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hws[IMX8MQ_SYS1_PLL_266M_CG] = imx_clk_hw_gate("sys1_pll_266m_cg", "sys1_pll_out", base + 0x30, 21);
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hws[IMX8MQ_SYS1_PLL_400M_CG] = imx_clk_hw_gate("sys1_pll_400m_cg", "sys1_pll_out", base + 0x30, 23);
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hws[IMX8MQ_SYS1_PLL_800M_CG] = imx_clk_hw_gate("sys1_pll_800m_cg", "sys1_pll_out", base + 0x30, 25);
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hws[IMX8MQ_SYS1_PLL_40M] = imx_clk_hw_fixed_factor("sys1_pll_40m", "sys1_pll_40m_cg", 1, 20);
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hws[IMX8MQ_SYS1_PLL_80M] = imx_clk_hw_fixed_factor("sys1_pll_80m", "sys1_pll_80m_cg", 1, 10);
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hws[IMX8MQ_SYS1_PLL_100M] = imx_clk_hw_fixed_factor("sys1_pll_100m", "sys1_pll_100m_cg", 1, 8);
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hws[IMX8MQ_SYS1_PLL_133M] = imx_clk_hw_fixed_factor("sys1_pll_133m", "sys1_pll_133m_cg", 1, 6);
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hws[IMX8MQ_SYS1_PLL_160M] = imx_clk_hw_fixed_factor("sys1_pll_160m", "sys1_pll_160m_cg", 1, 5);
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hws[IMX8MQ_SYS1_PLL_200M] = imx_clk_hw_fixed_factor("sys1_pll_200m", "sys1_pll_200m_cg", 1, 4);
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hws[IMX8MQ_SYS1_PLL_266M] = imx_clk_hw_fixed_factor("sys1_pll_266m", "sys1_pll_266m_cg", 1, 3);
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hws[IMX8MQ_SYS1_PLL_400M] = imx_clk_hw_fixed_factor("sys1_pll_400m", "sys1_pll_400m_cg", 1, 2);
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hws[IMX8MQ_SYS1_PLL_800M] = imx_clk_hw_fixed_factor("sys1_pll_800m", "sys1_pll_800m_cg", 1, 1);
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hws[IMX8MQ_SYS1_PLL_40M] = imx_clk_hw_fixed_factor("sys1_pll_40m", "sys1_pll_out", 1, 20);
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hws[IMX8MQ_SYS1_PLL_80M] = imx_clk_hw_fixed_factor("sys1_pll_80m", "sys1_pll_out", 1, 10);
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hws[IMX8MQ_SYS1_PLL_100M] = imx_clk_hw_fixed_factor("sys1_pll_100m", "sys1_pll_out", 1, 8);
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hws[IMX8MQ_SYS1_PLL_133M] = imx_clk_hw_fixed_factor("sys1_pll_133m", "sys1_pll_out", 1, 6);
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hws[IMX8MQ_SYS1_PLL_160M] = imx_clk_hw_fixed_factor("sys1_pll_160m", "sys1_pll_out", 1, 5);
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hws[IMX8MQ_SYS1_PLL_200M] = imx_clk_hw_fixed_factor("sys1_pll_200m", "sys1_pll_out", 1, 4);
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hws[IMX8MQ_SYS1_PLL_266M] = imx_clk_hw_fixed_factor("sys1_pll_266m", "sys1_pll_out", 1, 3);
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hws[IMX8MQ_SYS1_PLL_400M] = imx_clk_hw_fixed_factor("sys1_pll_400m", "sys1_pll_out", 1, 2);
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hws[IMX8MQ_SYS1_PLL_800M] = imx_clk_hw_fixed_factor("sys1_pll_800m", "sys1_pll_out", 1, 1);
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/* SYS PLL2 fixed output */
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hws[IMX8MQ_SYS2_PLL_50M_CG] = imx_clk_hw_gate("sys2_pll_50m_cg", "sys2_pll_out", base + 0x3c, 9);
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hws[IMX8MQ_SYS2_PLL_100M_CG] = imx_clk_hw_gate("sys2_pll_100m_cg", "sys2_pll_out", base + 0x3c, 11);
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hws[IMX8MQ_SYS2_PLL_125M_CG] = imx_clk_hw_gate("sys2_pll_125m_cg", "sys2_pll_out", base + 0x3c, 13);
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hws[IMX8MQ_SYS2_PLL_166M_CG] = imx_clk_hw_gate("sys2_pll_166m_cg", "sys2_pll_out", base + 0x3c, 15);
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hws[IMX8MQ_SYS2_PLL_200M_CG] = imx_clk_hw_gate("sys2_pll_200m_cg", "sys2_pll_out", base + 0x3c, 17);
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hws[IMX8MQ_SYS2_PLL_250M_CG] = imx_clk_hw_gate("sys2_pll_250m_cg", "sys2_pll_out", base + 0x3c, 19);
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hws[IMX8MQ_SYS2_PLL_333M_CG] = imx_clk_hw_gate("sys2_pll_333m_cg", "sys2_pll_out", base + 0x3c, 21);
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hws[IMX8MQ_SYS2_PLL_500M_CG] = imx_clk_hw_gate("sys2_pll_500m_cg", "sys2_pll_out", base + 0x3c, 23);
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hws[IMX8MQ_SYS2_PLL_1000M_CG] = imx_clk_hw_gate("sys2_pll_1000m_cg", "sys2_pll_out", base + 0x3c, 25);
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hws[IMX8MQ_SYS2_PLL_50M] = imx_clk_hw_fixed_factor("sys2_pll_50m", "sys2_pll_50m_cg", 1, 20);
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hws[IMX8MQ_SYS2_PLL_100M] = imx_clk_hw_fixed_factor("sys2_pll_100m", "sys2_pll_100m_cg", 1, 10);
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hws[IMX8MQ_SYS2_PLL_125M] = imx_clk_hw_fixed_factor("sys2_pll_125m", "sys2_pll_125m_cg", 1, 8);
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hws[IMX8MQ_SYS2_PLL_166M] = imx_clk_hw_fixed_factor("sys2_pll_166m", "sys2_pll_166m_cg", 1, 6);
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hws[IMX8MQ_SYS2_PLL_200M] = imx_clk_hw_fixed_factor("sys2_pll_200m", "sys2_pll_200m_cg", 1, 5);
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hws[IMX8MQ_SYS2_PLL_250M] = imx_clk_hw_fixed_factor("sys2_pll_250m", "sys2_pll_250m_cg", 1, 4);
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hws[IMX8MQ_SYS2_PLL_333M] = imx_clk_hw_fixed_factor("sys2_pll_333m", "sys2_pll_333m_cg", 1, 3);
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hws[IMX8MQ_SYS2_PLL_500M] = imx_clk_hw_fixed_factor("sys2_pll_500m", "sys2_pll_500m_cg", 1, 2);
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hws[IMX8MQ_SYS2_PLL_1000M] = imx_clk_hw_fixed_factor("sys2_pll_1000m", "sys2_pll_1000m_cg", 1, 1);
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hws[IMX8MQ_SYS2_PLL_50M] = imx_clk_hw_fixed_factor("sys2_pll_50m", "sys2_pll_out", 1, 20);
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hws[IMX8MQ_SYS2_PLL_100M] = imx_clk_hw_fixed_factor("sys2_pll_100m", "sys2_pll_out", 1, 10);
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hws[IMX8MQ_SYS2_PLL_125M] = imx_clk_hw_fixed_factor("sys2_pll_125m", "sys2_pll_out", 1, 8);
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hws[IMX8MQ_SYS2_PLL_166M] = imx_clk_hw_fixed_factor("sys2_pll_166m", "sys2_pll_out", 1, 6);
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hws[IMX8MQ_SYS2_PLL_200M] = imx_clk_hw_fixed_factor("sys2_pll_200m", "sys2_pll_out", 1, 5);
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hws[IMX8MQ_SYS2_PLL_250M] = imx_clk_hw_fixed_factor("sys2_pll_250m", "sys2_pll_out", 1, 4);
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hws[IMX8MQ_SYS2_PLL_333M] = imx_clk_hw_fixed_factor("sys2_pll_333m", "sys2_pll_out", 1, 3);
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hws[IMX8MQ_SYS2_PLL_500M] = imx_clk_hw_fixed_factor("sys2_pll_500m", "sys2_pll_out", 1, 2);
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hws[IMX8MQ_SYS2_PLL_1000M] = imx_clk_hw_fixed_factor("sys2_pll_1000m", "sys2_pll_out", 1, 1);
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hws[IMX8MQ_CLK_MON_AUDIO_PLL1_DIV] = imx_clk_hw_divider("audio_pll1_out_monitor", "audio_pll1_bypass", base + 0x78, 0, 3);
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hws[IMX8MQ_CLK_MON_AUDIO_PLL2_DIV] = imx_clk_hw_divider("audio_pll2_out_monitor", "audio_pll2_bypass", base + 0x78, 4, 3);
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116
drivers/clk/imx/clk-imx8qm-rsrc.c
Normal file
116
drivers/clk/imx/clk-imx8qm-rsrc.c
Normal file
@@ -0,0 +1,116 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019-2021 NXP
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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#include <dt-bindings/firmware/imx/rsrc.h>
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#include "clk-scu.h"
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/* Keep sorted in the ascending order */
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static const u32 imx8qm_clk_scu_rsrc_table[] = {
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IMX_SC_R_A53,
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IMX_SC_R_A72,
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IMX_SC_R_DC_0_VIDEO0,
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IMX_SC_R_DC_0_VIDEO1,
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IMX_SC_R_DC_0,
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IMX_SC_R_DC_0_PLL_0,
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IMX_SC_R_DC_0_PLL_1,
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IMX_SC_R_DC_1_VIDEO0,
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IMX_SC_R_DC_1_VIDEO1,
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IMX_SC_R_DC_1,
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IMX_SC_R_DC_1_PLL_0,
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IMX_SC_R_DC_1_PLL_1,
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IMX_SC_R_SPI_0,
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IMX_SC_R_SPI_1,
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IMX_SC_R_SPI_2,
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IMX_SC_R_SPI_3,
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IMX_SC_R_UART_0,
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IMX_SC_R_UART_1,
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IMX_SC_R_UART_2,
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IMX_SC_R_UART_3,
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IMX_SC_R_UART_4,
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IMX_SC_R_EMVSIM_0,
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IMX_SC_R_EMVSIM_1,
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IMX_SC_R_I2C_0,
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IMX_SC_R_I2C_1,
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IMX_SC_R_I2C_2,
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IMX_SC_R_I2C_3,
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IMX_SC_R_I2C_4,
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IMX_SC_R_ADC_0,
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IMX_SC_R_ADC_1,
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IMX_SC_R_FTM_0,
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IMX_SC_R_FTM_1,
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IMX_SC_R_CAN_0,
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IMX_SC_R_GPU_0_PID0,
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IMX_SC_R_GPU_1_PID0,
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IMX_SC_R_PWM_0,
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IMX_SC_R_PWM_1,
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IMX_SC_R_PWM_2,
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IMX_SC_R_PWM_3,
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IMX_SC_R_PWM_4,
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IMX_SC_R_PWM_5,
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IMX_SC_R_PWM_6,
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IMX_SC_R_PWM_7,
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IMX_SC_R_GPT_0,
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IMX_SC_R_GPT_1,
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IMX_SC_R_GPT_2,
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IMX_SC_R_GPT_3,
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IMX_SC_R_GPT_4,
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IMX_SC_R_FSPI_0,
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IMX_SC_R_FSPI_1,
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IMX_SC_R_SDHC_0,
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IMX_SC_R_SDHC_1,
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IMX_SC_R_SDHC_2,
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IMX_SC_R_ENET_0,
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IMX_SC_R_ENET_1,
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IMX_SC_R_MLB_0,
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IMX_SC_R_USB_2,
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IMX_SC_R_NAND,
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IMX_SC_R_LVDS_0,
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IMX_SC_R_LVDS_0_PWM_0,
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IMX_SC_R_LVDS_0_I2C_0,
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IMX_SC_R_LVDS_0_I2C_1,
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IMX_SC_R_LVDS_1,
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IMX_SC_R_LVDS_1_PWM_0,
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IMX_SC_R_LVDS_1_I2C_0,
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IMX_SC_R_LVDS_1_I2C_1,
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IMX_SC_R_M4_0_I2C,
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IMX_SC_R_M4_1_I2C,
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IMX_SC_R_AUDIO_PLL_0,
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IMX_SC_R_VPU_UART,
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IMX_SC_R_VPUCORE,
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IMX_SC_R_MIPI_0,
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IMX_SC_R_MIPI_0_PWM_0,
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IMX_SC_R_MIPI_0_I2C_0,
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IMX_SC_R_MIPI_0_I2C_1,
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IMX_SC_R_MIPI_1,
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IMX_SC_R_MIPI_1_PWM_0,
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IMX_SC_R_MIPI_1_I2C_0,
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IMX_SC_R_MIPI_1_I2C_1,
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IMX_SC_R_CSI_0,
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IMX_SC_R_CSI_0_PWM_0,
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IMX_SC_R_CSI_0_I2C_0,
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IMX_SC_R_CSI_1,
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IMX_SC_R_CSI_1_PWM_0,
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IMX_SC_R_CSI_1_I2C_0,
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IMX_SC_R_HDMI,
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IMX_SC_R_HDMI_I2S,
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IMX_SC_R_HDMI_I2C_0,
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IMX_SC_R_HDMI_PLL_0,
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IMX_SC_R_HDMI_RX,
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IMX_SC_R_HDMI_RX_BYPASS,
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IMX_SC_R_HDMI_RX_I2C_0,
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IMX_SC_R_AUDIO_PLL_1,
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IMX_SC_R_AUDIO_CLK_0,
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IMX_SC_R_AUDIO_CLK_1,
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IMX_SC_R_HDMI_RX_PWM_0,
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IMX_SC_R_HDMI_PLL_1,
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IMX_SC_R_VPU,
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};
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const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm = {
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.rsrc = imx8qm_clk_scu_rsrc_table,
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.num = ARRAY_SIZE(imx8qm_clk_scu_rsrc_table),
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};
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89
drivers/clk/imx/clk-imx8qxp-rsrc.c
Normal file
89
drivers/clk/imx/clk-imx8qxp-rsrc.c
Normal file
@@ -0,0 +1,89 @@
|
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// SPDX-License-Identifier: GPL-2.0+
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/*
|
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* Copyright 2019-2021 NXP
|
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* Dong Aisheng <aisheng.dong@nxp.com>
|
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*/
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#include <dt-bindings/firmware/imx/rsrc.h>
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#include "clk-scu.h"
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/* Keep sorted in the ascending order */
|
||||
static const u32 imx8qxp_clk_scu_rsrc_table[] = {
|
||||
IMX_SC_R_DC_0_VIDEO0,
|
||||
IMX_SC_R_DC_0_VIDEO1,
|
||||
IMX_SC_R_DC_0,
|
||||
IMX_SC_R_DC_0_PLL_0,
|
||||
IMX_SC_R_DC_0_PLL_1,
|
||||
IMX_SC_R_SPI_0,
|
||||
IMX_SC_R_SPI_1,
|
||||
IMX_SC_R_SPI_2,
|
||||
IMX_SC_R_SPI_3,
|
||||
IMX_SC_R_UART_0,
|
||||
IMX_SC_R_UART_1,
|
||||
IMX_SC_R_UART_2,
|
||||
IMX_SC_R_UART_3,
|
||||
IMX_SC_R_I2C_0,
|
||||
IMX_SC_R_I2C_1,
|
||||
IMX_SC_R_I2C_2,
|
||||
IMX_SC_R_I2C_3,
|
||||
IMX_SC_R_ADC_0,
|
||||
IMX_SC_R_FTM_0,
|
||||
IMX_SC_R_FTM_1,
|
||||
IMX_SC_R_CAN_0,
|
||||
IMX_SC_R_GPU_0_PID0,
|
||||
IMX_SC_R_LCD_0,
|
||||
IMX_SC_R_LCD_0_PWM_0,
|
||||
IMX_SC_R_PWM_0,
|
||||
IMX_SC_R_PWM_1,
|
||||
IMX_SC_R_PWM_2,
|
||||
IMX_SC_R_PWM_3,
|
||||
IMX_SC_R_PWM_4,
|
||||
IMX_SC_R_PWM_5,
|
||||
IMX_SC_R_PWM_6,
|
||||
IMX_SC_R_PWM_7,
|
||||
IMX_SC_R_GPT_0,
|
||||
IMX_SC_R_GPT_1,
|
||||
IMX_SC_R_GPT_2,
|
||||
IMX_SC_R_GPT_3,
|
||||
IMX_SC_R_GPT_4,
|
||||
IMX_SC_R_FSPI_0,
|
||||
IMX_SC_R_FSPI_1,
|
||||
IMX_SC_R_SDHC_0,
|
||||
IMX_SC_R_SDHC_1,
|
||||
IMX_SC_R_SDHC_2,
|
||||
IMX_SC_R_ENET_0,
|
||||
IMX_SC_R_ENET_1,
|
||||
IMX_SC_R_MLB_0,
|
||||
IMX_SC_R_USB_2,
|
||||
IMX_SC_R_NAND,
|
||||
IMX_SC_R_LVDS_0,
|
||||
IMX_SC_R_LVDS_1,
|
||||
IMX_SC_R_M4_0_I2C,
|
||||
IMX_SC_R_ELCDIF_PLL,
|
||||
IMX_SC_R_AUDIO_PLL_0,
|
||||
IMX_SC_R_PI_0,
|
||||
IMX_SC_R_PI_0_PLL,
|
||||
IMX_SC_R_MIPI_0,
|
||||
IMX_SC_R_MIPI_0_PWM_0,
|
||||
IMX_SC_R_MIPI_0_I2C_0,
|
||||
IMX_SC_R_MIPI_0_I2C_1,
|
||||
IMX_SC_R_MIPI_1,
|
||||
IMX_SC_R_MIPI_1_PWM_0,
|
||||
IMX_SC_R_MIPI_1_I2C_0,
|
||||
IMX_SC_R_MIPI_1_I2C_1,
|
||||
IMX_SC_R_CSI_0,
|
||||
IMX_SC_R_CSI_0_PWM_0,
|
||||
IMX_SC_R_CSI_0_I2C_0,
|
||||
IMX_SC_R_AUDIO_PLL_1,
|
||||
IMX_SC_R_AUDIO_CLK_0,
|
||||
IMX_SC_R_AUDIO_CLK_1,
|
||||
IMX_SC_R_A35,
|
||||
IMX_SC_R_VPU_DEC_0,
|
||||
IMX_SC_R_VPU_ENC_0,
|
||||
};
|
||||
|
||||
const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qxp = {
|
||||
.rsrc = imx8qxp_clk_scu_rsrc_table,
|
||||
.num = ARRAY_SIZE(imx8qxp_clk_scu_rsrc_table),
|
||||
};
|
||||
@@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
* Copyright 2018-2021 NXP
|
||||
* Dong Aisheng <aisheng.dong@nxp.com>
|
||||
*/
|
||||
|
||||
@@ -9,12 +9,12 @@
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include "clk-scu.h"
|
||||
|
||||
#include <dt-bindings/clock/imx8-clock.h>
|
||||
#include <dt-bindings/firmware/imx/rsrc.h>
|
||||
|
||||
static const char *dc0_sels[] = {
|
||||
@@ -25,159 +25,278 @@ static const char *dc0_sels[] = {
|
||||
"dc0_bypass0_clk",
|
||||
};
|
||||
|
||||
static const char * const dc1_sels[] = {
|
||||
"clk_dummy",
|
||||
"clk_dummy",
|
||||
"dc1_pll0_clk",
|
||||
"dc1_pll1_clk",
|
||||
"dc1_bypass0_clk",
|
||||
};
|
||||
|
||||
static const char * const enet0_rgmii_txc_sels[] = {
|
||||
"enet0_ref_div",
|
||||
"clk_dummy",
|
||||
};
|
||||
|
||||
static const char * const enet1_rgmii_txc_sels[] = {
|
||||
"enet1_ref_div",
|
||||
"clk_dummy",
|
||||
};
|
||||
|
||||
static const char * const hdmi_sels[] = {
|
||||
"clk_dummy",
|
||||
"hdmi_dig_pll_clk",
|
||||
"clk_dummy",
|
||||
"clk_dummy",
|
||||
"hdmi_av_pll_clk",
|
||||
};
|
||||
|
||||
static const char * const hdmi_rx_sels[] = {
|
||||
"clk_dummy",
|
||||
"hdmi_rx_dig_pll_clk",
|
||||
"clk_dummy",
|
||||
"clk_dummy",
|
||||
"hdmi_rx_bypass_clk",
|
||||
};
|
||||
|
||||
static const char * const lcd_pxl_sels[] = {
|
||||
"clk_dummy",
|
||||
"clk_dummy",
|
||||
"clk_dummy",
|
||||
"clk_dummy",
|
||||
"lcd_pxl_bypass_div_clk",
|
||||
};
|
||||
|
||||
static const char * const mipi_sels[] = {
|
||||
"clk_dummy",
|
||||
"clk_dummy",
|
||||
"mipi_pll_div2_clk",
|
||||
"clk_dummy",
|
||||
"clk_dummy",
|
||||
};
|
||||
|
||||
static const char * const lcd_sels[] = {
|
||||
"clk_dummy",
|
||||
"clk_dummy",
|
||||
"clk_dummy",
|
||||
"clk_dummy",
|
||||
"elcdif_pll",
|
||||
};
|
||||
|
||||
static const char * const pi_pll0_sels[] = {
|
||||
"clk_dummy",
|
||||
"pi_dpll_clk",
|
||||
"clk_dummy",
|
||||
"clk_dummy",
|
||||
"clk_dummy",
|
||||
};
|
||||
|
||||
static int imx8qxp_clk_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *ccm_node = pdev->dev.of_node;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct clk_hw **clks;
|
||||
u32 clk_cells;
|
||||
int ret, i;
|
||||
const struct imx_clk_scu_rsrc_table *rsrc_table;
|
||||
int ret;
|
||||
|
||||
ret = imx_clk_scu_init(ccm_node);
|
||||
rsrc_table = of_device_get_match_data(&pdev->dev);
|
||||
ret = imx_clk_scu_init(ccm_node, rsrc_table);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws,
|
||||
IMX_SCU_CLK_END), GFP_KERNEL);
|
||||
if (!clk_data)
|
||||
return -ENOMEM;
|
||||
|
||||
if (of_property_read_u32(ccm_node, "#clock-cells", &clk_cells))
|
||||
return -EINVAL;
|
||||
|
||||
clk_data->num = IMX_SCU_CLK_END;
|
||||
clks = clk_data->hws;
|
||||
|
||||
/* Fixed clocks */
|
||||
clks[IMX_CLK_DUMMY] = clk_hw_register_fixed_rate(NULL, "dummy", NULL, 0, 0);
|
||||
clks[IMX_ADMA_IPG_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "dma_ipg_clk_root", NULL, 0, 120000000);
|
||||
clks[IMX_CONN_AXI_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "conn_axi_clk_root", NULL, 0, 333333333);
|
||||
clks[IMX_CONN_AHB_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "conn_ahb_clk_root", NULL, 0, 166666666);
|
||||
clks[IMX_CONN_IPG_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "conn_ipg_clk_root", NULL, 0, 83333333);
|
||||
clks[IMX_DC_AXI_EXT_CLK] = clk_hw_register_fixed_rate(NULL, "dc_axi_ext_clk_root", NULL, 0, 800000000);
|
||||
clks[IMX_DC_AXI_INT_CLK] = clk_hw_register_fixed_rate(NULL, "dc_axi_int_clk_root", NULL, 0, 400000000);
|
||||
clks[IMX_DC_CFG_CLK] = clk_hw_register_fixed_rate(NULL, "dc_cfg_clk_root", NULL, 0, 100000000);
|
||||
clks[IMX_MIPI_IPG_CLK] = clk_hw_register_fixed_rate(NULL, "mipi_ipg_clk_root", NULL, 0, 120000000);
|
||||
clks[IMX_IMG_AXI_CLK] = clk_hw_register_fixed_rate(NULL, "img_axi_clk_root", NULL, 0, 400000000);
|
||||
clks[IMX_IMG_IPG_CLK] = clk_hw_register_fixed_rate(NULL, "img_ipg_clk_root", NULL, 0, 200000000);
|
||||
clks[IMX_IMG_PXL_CLK] = clk_hw_register_fixed_rate(NULL, "img_pxl_clk_root", NULL, 0, 600000000);
|
||||
clks[IMX_HSIO_AXI_CLK] = clk_hw_register_fixed_rate(NULL, "hsio_axi_clk_root", NULL, 0, 400000000);
|
||||
clks[IMX_HSIO_PER_CLK] = clk_hw_register_fixed_rate(NULL, "hsio_per_clk_root", NULL, 0, 133333333);
|
||||
clks[IMX_LSIO_MEM_CLK] = clk_hw_register_fixed_rate(NULL, "lsio_mem_clk_root", NULL, 0, 200000000);
|
||||
clks[IMX_LSIO_BUS_CLK] = clk_hw_register_fixed_rate(NULL, "lsio_bus_clk_root", NULL, 0, 100000000);
|
||||
|
||||
/* ARM core */
|
||||
clks[IMX_A35_CLK] = imx_clk_scu("a35_clk", IMX_SC_R_A35, IMX_SC_PM_CLK_CPU, clk_cells);
|
||||
imx_clk_scu("a35_clk", IMX_SC_R_A35, IMX_SC_PM_CLK_CPU);
|
||||
imx_clk_scu("a53_clk", IMX_SC_R_A53, IMX_SC_PM_CLK_CPU);
|
||||
imx_clk_scu("a72_clk", IMX_SC_R_A72, IMX_SC_PM_CLK_CPU);
|
||||
|
||||
/* LSIO SS */
|
||||
clks[IMX_LSIO_PWM0_CLK] = imx_clk_scu("pwm0_clk", IMX_SC_R_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_LSIO_PWM1_CLK] = imx_clk_scu("pwm1_clk", IMX_SC_R_PWM_1, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_LSIO_PWM2_CLK] = imx_clk_scu("pwm2_clk", IMX_SC_R_PWM_2, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_LSIO_PWM3_CLK] = imx_clk_scu("pwm3_clk", IMX_SC_R_PWM_3, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_LSIO_PWM4_CLK] = imx_clk_scu("pwm4_clk", IMX_SC_R_PWM_4, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_LSIO_PWM5_CLK] = imx_clk_scu("pwm5_clk", IMX_SC_R_PWM_5, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_LSIO_PWM6_CLK] = imx_clk_scu("pwm6_clk", IMX_SC_R_PWM_6, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_LSIO_PWM7_CLK] = imx_clk_scu("pwm7_clk", IMX_SC_R_PWM_7, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_LSIO_GPT0_CLK] = imx_clk_scu("gpt0_clk", IMX_SC_R_GPT_0, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_LSIO_GPT1_CLK] = imx_clk_scu("gpt1_clk", IMX_SC_R_GPT_1, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_LSIO_GPT2_CLK] = imx_clk_scu("gpt2_clk", IMX_SC_R_GPT_2, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_LSIO_GPT3_CLK] = imx_clk_scu("gpt3_clk", IMX_SC_R_GPT_3, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_LSIO_GPT4_CLK] = imx_clk_scu("gpt4_clk", IMX_SC_R_GPT_4, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_LSIO_FSPI0_CLK] = imx_clk_scu("fspi0_clk", IMX_SC_R_FSPI_0, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_LSIO_FSPI1_CLK] = imx_clk_scu("fspi1_clk", IMX_SC_R_FSPI_1, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
imx_clk_scu("pwm0_clk", IMX_SC_R_PWM_0, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("pwm1_clk", IMX_SC_R_PWM_1, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("pwm2_clk", IMX_SC_R_PWM_2, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("pwm3_clk", IMX_SC_R_PWM_3, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("pwm4_clk", IMX_SC_R_PWM_4, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("pwm5_clk", IMX_SC_R_PWM_5, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("pwm6_clk", IMX_SC_R_PWM_6, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("pwm7_clk", IMX_SC_R_PWM_7, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("gpt0_clk", IMX_SC_R_GPT_0, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("gpt1_clk", IMX_SC_R_GPT_1, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("gpt2_clk", IMX_SC_R_GPT_2, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("gpt3_clk", IMX_SC_R_GPT_3, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("gpt4_clk", IMX_SC_R_GPT_4, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("fspi0_clk", IMX_SC_R_FSPI_0, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("fspi1_clk", IMX_SC_R_FSPI_1, IMX_SC_PM_CLK_PER);
|
||||
|
||||
/* ADMA SS */
|
||||
clks[IMX_ADMA_UART0_CLK] = imx_clk_scu("uart0_clk", IMX_SC_R_UART_0, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_ADMA_UART1_CLK] = imx_clk_scu("uart1_clk", IMX_SC_R_UART_1, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_ADMA_UART2_CLK] = imx_clk_scu("uart2_clk", IMX_SC_R_UART_2, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_ADMA_UART3_CLK] = imx_clk_scu("uart3_clk", IMX_SC_R_UART_3, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_ADMA_SPI0_CLK] = imx_clk_scu("spi0_clk", IMX_SC_R_SPI_0, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_ADMA_SPI1_CLK] = imx_clk_scu("spi1_clk", IMX_SC_R_SPI_1, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_ADMA_SPI2_CLK] = imx_clk_scu("spi2_clk", IMX_SC_R_SPI_2, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_ADMA_SPI3_CLK] = imx_clk_scu("spi3_clk", IMX_SC_R_SPI_3, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_ADMA_CAN0_CLK] = imx_clk_scu("can0_clk", IMX_SC_R_CAN_0, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_ADMA_I2C0_CLK] = imx_clk_scu("i2c0_clk", IMX_SC_R_I2C_0, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_ADMA_I2C1_CLK] = imx_clk_scu("i2c1_clk", IMX_SC_R_I2C_1, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_ADMA_I2C2_CLK] = imx_clk_scu("i2c2_clk", IMX_SC_R_I2C_2, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_ADMA_I2C3_CLK] = imx_clk_scu("i2c3_clk", IMX_SC_R_I2C_3, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_ADMA_FTM0_CLK] = imx_clk_scu("ftm0_clk", IMX_SC_R_FTM_0, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_ADMA_FTM1_CLK] = imx_clk_scu("ftm1_clk", IMX_SC_R_FTM_1, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_ADMA_ADC0_CLK] = imx_clk_scu("adc0_clk", IMX_SC_R_ADC_0, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_ADMA_PWM_CLK] = imx_clk_scu("pwm_clk", IMX_SC_R_LCD_0_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_ADMA_LCD_CLK] = imx_clk_scu("lcd_clk", IMX_SC_R_LCD_0, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
/* DMA SS */
|
||||
imx_clk_scu("uart0_clk", IMX_SC_R_UART_0, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("uart1_clk", IMX_SC_R_UART_1, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("uart2_clk", IMX_SC_R_UART_2, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("uart3_clk", IMX_SC_R_UART_3, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("uart4_clk", IMX_SC_R_UART_4, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("sim0_clk", IMX_SC_R_EMVSIM_0, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("spi0_clk", IMX_SC_R_SPI_0, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("spi1_clk", IMX_SC_R_SPI_1, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("spi2_clk", IMX_SC_R_SPI_2, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("spi3_clk", IMX_SC_R_SPI_3, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("can0_clk", IMX_SC_R_CAN_0, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("can1_clk", IMX_SC_R_CAN_1, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("can2_clk", IMX_SC_R_CAN_2, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("i2c0_clk", IMX_SC_R_I2C_0, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("i2c1_clk", IMX_SC_R_I2C_1, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("i2c2_clk", IMX_SC_R_I2C_2, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("i2c3_clk", IMX_SC_R_I2C_3, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("i2c4_clk", IMX_SC_R_I2C_4, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("ftm0_clk", IMX_SC_R_FTM_0, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("ftm1_clk", IMX_SC_R_FTM_1, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("adc0_clk", IMX_SC_R_ADC_0, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("adc1_clk", IMX_SC_R_ADC_1, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("pwm_clk", IMX_SC_R_LCD_0_PWM_0, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu2("lcd_clk", lcd_sels, ARRAY_SIZE(lcd_sels), IMX_SC_R_LCD_0, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu2("lcd_pxl_clk", lcd_pxl_sels, ARRAY_SIZE(lcd_pxl_sels), IMX_SC_R_LCD_0, IMX_SC_PM_CLK_MISC0);
|
||||
imx_clk_scu("lcd_pxl_bypass_div_clk", IMX_SC_R_LCD_0, IMX_SC_PM_CLK_BYPASS);
|
||||
imx_clk_scu("elcdif_pll", IMX_SC_R_ELCDIF_PLL, IMX_SC_PM_CLK_PLL);
|
||||
|
||||
/* Audio SS */
|
||||
imx_clk_scu("audio_pll0_clk", IMX_SC_R_AUDIO_PLL_0, IMX_SC_PM_CLK_PLL);
|
||||
imx_clk_scu("audio_pll1_clk", IMX_SC_R_AUDIO_PLL_1, IMX_SC_PM_CLK_PLL);
|
||||
imx_clk_scu("audio_pll_div_clk0_clk", IMX_SC_R_AUDIO_PLL_0, IMX_SC_PM_CLK_MISC0);
|
||||
imx_clk_scu("audio_pll_div_clk1_clk", IMX_SC_R_AUDIO_PLL_1, IMX_SC_PM_CLK_MISC0);
|
||||
imx_clk_scu("audio_rec_clk0_clk", IMX_SC_R_AUDIO_PLL_0, IMX_SC_PM_CLK_MISC1);
|
||||
imx_clk_scu("audio_rec_clk1_clk", IMX_SC_R_AUDIO_PLL_1, IMX_SC_PM_CLK_MISC1);
|
||||
|
||||
/* Connectivity */
|
||||
clks[IMX_CONN_SDHC0_CLK] = imx_clk_scu("sdhc0_clk", IMX_SC_R_SDHC_0, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_CONN_SDHC1_CLK] = imx_clk_scu("sdhc1_clk", IMX_SC_R_SDHC_1, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_CONN_SDHC2_CLK] = imx_clk_scu("sdhc2_clk", IMX_SC_R_SDHC_2, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_CONN_ENET0_ROOT_CLK] = imx_clk_scu("enet0_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_CONN_ENET0_BYPASS_CLK] = imx_clk_scu("enet0_bypass_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_BYPASS, clk_cells);
|
||||
clks[IMX_CONN_ENET0_RGMII_CLK] = imx_clk_scu("enet0_rgmii_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0, clk_cells);
|
||||
clks[IMX_CONN_ENET1_ROOT_CLK] = imx_clk_scu("enet1_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_CONN_ENET1_BYPASS_CLK] = imx_clk_scu("enet1_bypass_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_BYPASS, clk_cells);
|
||||
clks[IMX_CONN_ENET1_RGMII_CLK] = imx_clk_scu("enet1_rgmii_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0, clk_cells);
|
||||
clks[IMX_CONN_GPMI_BCH_IO_CLK] = imx_clk_scu("gpmi_io_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_MST_BUS, clk_cells);
|
||||
clks[IMX_CONN_GPMI_BCH_CLK] = imx_clk_scu("gpmi_bch_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_CONN_USB2_ACLK] = imx_clk_scu("usb3_aclk_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_CONN_USB2_BUS_CLK] = imx_clk_scu("usb3_bus_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MST_BUS, clk_cells);
|
||||
clks[IMX_CONN_USB2_LPM_CLK] = imx_clk_scu("usb3_lpm_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MISC, clk_cells);
|
||||
imx_clk_scu("sdhc0_clk", IMX_SC_R_SDHC_0, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("sdhc1_clk", IMX_SC_R_SDHC_1, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("sdhc2_clk", IMX_SC_R_SDHC_2, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("enet0_root_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_divider_gpr_scu("enet0_ref_div", "enet0_root_clk", IMX_SC_R_ENET_0, IMX_SC_C_CLKDIV);
|
||||
imx_clk_mux_gpr_scu("enet0_rgmii_txc_sel", enet0_rgmii_txc_sels, ARRAY_SIZE(enet0_rgmii_txc_sels), IMX_SC_R_ENET_0, IMX_SC_C_TXCLK);
|
||||
imx_clk_scu("enet0_bypass_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_BYPASS);
|
||||
imx_clk_gate_gpr_scu("enet0_ref_50_clk", "clk_dummy", IMX_SC_R_ENET_0, IMX_SC_C_DISABLE_50, true);
|
||||
imx_clk_scu("enet0_rgmii_rx_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0);
|
||||
imx_clk_scu("enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_divider_gpr_scu("enet1_ref_div", "enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_C_CLKDIV);
|
||||
imx_clk_mux_gpr_scu("enet1_rgmii_txc_sel", enet1_rgmii_txc_sels, ARRAY_SIZE(enet1_rgmii_txc_sels), IMX_SC_R_ENET_1, IMX_SC_C_TXCLK);
|
||||
imx_clk_scu("enet1_bypass_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_BYPASS);
|
||||
imx_clk_gate_gpr_scu("enet1_ref_50_clk", "clk_dummy", IMX_SC_R_ENET_1, IMX_SC_C_DISABLE_50, true);
|
||||
imx_clk_scu("enet1_rgmii_rx_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0);
|
||||
imx_clk_scu("gpmi_io_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_MST_BUS);
|
||||
imx_clk_scu("gpmi_bch_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("usb3_aclk_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("usb3_bus_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MST_BUS);
|
||||
imx_clk_scu("usb3_lpm_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MISC);
|
||||
|
||||
/* Display controller SS */
|
||||
clks[IMX_DC0_DISP0_CLK] = imx_clk_scu2("dc0_disp0_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0, clk_cells);
|
||||
clks[IMX_DC0_DISP1_CLK] = imx_clk_scu2("dc0_disp1_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1, clk_cells);
|
||||
clks[IMX_DC0_PLL0_CLK] = imx_clk_scu("dc0_pll0_clk", IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL, clk_cells);
|
||||
clks[IMX_DC0_PLL1_CLK] = imx_clk_scu("dc0_pll1_clk", IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL, clk_cells);
|
||||
clks[IMX_DC0_BYPASS0_CLK] = imx_clk_scu("dc0_bypass0_clk", IMX_SC_R_DC_0_VIDEO0, IMX_SC_PM_CLK_BYPASS, clk_cells);
|
||||
clks[IMX_DC0_BYPASS1_CLK] = imx_clk_scu("dc0_bypass1_clk", IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS, clk_cells);
|
||||
imx_clk_scu2("dc0_disp0_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0);
|
||||
imx_clk_scu2("dc0_disp1_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1);
|
||||
imx_clk_scu("dc0_pll0_clk", IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL);
|
||||
imx_clk_scu("dc0_pll1_clk", IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL);
|
||||
imx_clk_scu("dc0_bypass0_clk", IMX_SC_R_DC_0_VIDEO0, IMX_SC_PM_CLK_BYPASS);
|
||||
imx_clk_scu("dc0_bypass1_clk", IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS);
|
||||
|
||||
imx_clk_scu2("dc1_disp0_clk", dc1_sels, ARRAY_SIZE(dc1_sels), IMX_SC_R_DC_1, IMX_SC_PM_CLK_MISC0);
|
||||
imx_clk_scu2("dc1_disp1_clk", dc1_sels, ARRAY_SIZE(dc1_sels), IMX_SC_R_DC_1, IMX_SC_PM_CLK_MISC1);
|
||||
imx_clk_scu("dc1_pll0_clk", IMX_SC_R_DC_1_PLL_0, IMX_SC_PM_CLK_PLL);
|
||||
imx_clk_scu("dc1_pll1_clk", IMX_SC_R_DC_1_PLL_1, IMX_SC_PM_CLK_PLL);
|
||||
imx_clk_scu("dc1_bypass0_clk", IMX_SC_R_DC_1_VIDEO0, IMX_SC_PM_CLK_BYPASS);
|
||||
imx_clk_scu("dc1_bypass1_clk", IMX_SC_R_DC_1_VIDEO1, IMX_SC_PM_CLK_BYPASS);
|
||||
|
||||
/* MIPI-LVDS SS */
|
||||
clks[IMX_MIPI0_LVDS_PIXEL_CLK] = imx_clk_scu("mipi0_lvds_pixel_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2, clk_cells);
|
||||
clks[IMX_MIPI0_LVDS_BYPASS_CLK] = imx_clk_scu("mipi0_lvds_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS, clk_cells);
|
||||
clks[IMX_MIPI0_LVDS_PHY_CLK] = imx_clk_scu("mipi0_lvds_phy_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3, clk_cells);
|
||||
clks[IMX_MIPI0_I2C0_CLK] = imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells);
|
||||
clks[IMX_MIPI0_I2C1_CLK] = imx_clk_scu("mipi0_i2c1_clk", IMX_SC_R_MIPI_0_I2C_1, IMX_SC_PM_CLK_MISC2, clk_cells);
|
||||
clks[IMX_MIPI0_PWM0_CLK] = imx_clk_scu("mipi0_pwm0_clk", IMX_SC_R_MIPI_0_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_MIPI1_LVDS_PIXEL_CLK] = imx_clk_scu("mipi1_lvds_pixel_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2, clk_cells);
|
||||
clks[IMX_MIPI1_LVDS_BYPASS_CLK] = imx_clk_scu("mipi1_lvds_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS, clk_cells);
|
||||
clks[IMX_MIPI1_LVDS_PHY_CLK] = imx_clk_scu("mipi1_lvds_phy_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3, clk_cells);
|
||||
clks[IMX_MIPI1_I2C0_CLK] = imx_clk_scu("mipi1_i2c0_clk", IMX_SC_R_MIPI_1_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells);
|
||||
clks[IMX_MIPI1_I2C1_CLK] = imx_clk_scu("mipi1_i2c1_clk", IMX_SC_R_MIPI_1_I2C_1, IMX_SC_PM_CLK_MISC2, clk_cells);
|
||||
clks[IMX_MIPI1_PWM0_CLK] = imx_clk_scu("mipi1_pwm0_clk", IMX_SC_R_MIPI_1_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
imx_clk_scu("mipi0_bypass_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_BYPASS);
|
||||
imx_clk_scu("mipi0_pixel_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("mipi0_lvds_pixel_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2);
|
||||
imx_clk_scu("mipi0_lvds_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS);
|
||||
imx_clk_scu("mipi0_lvds_phy_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3);
|
||||
imx_clk_scu2("mipi0_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_MST_BUS);
|
||||
imx_clk_scu2("mipi0_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_SLV_BUS);
|
||||
imx_clk_scu2("mipi0_dsi_phy_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PHY);
|
||||
imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2);
|
||||
imx_clk_scu("mipi0_i2c1_clk", IMX_SC_R_MIPI_0_I2C_1, IMX_SC_PM_CLK_MISC2);
|
||||
imx_clk_scu("mipi0_pwm0_clk", IMX_SC_R_MIPI_0_PWM_0, IMX_SC_PM_CLK_PER);
|
||||
|
||||
imx_clk_scu("mipi1_bypass_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_BYPASS);
|
||||
imx_clk_scu("mipi1_pixel_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("mipi1_lvds_pixel_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2);
|
||||
imx_clk_scu("mipi1_lvds_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS);
|
||||
imx_clk_scu("mipi1_lvds_phy_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3);
|
||||
|
||||
imx_clk_scu2("mipi1_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_MST_BUS);
|
||||
imx_clk_scu2("mipi1_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_SLV_BUS);
|
||||
imx_clk_scu2("mipi1_dsi_phy_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PHY);
|
||||
imx_clk_scu("mipi1_i2c0_clk", IMX_SC_R_MIPI_1_I2C_0, IMX_SC_PM_CLK_MISC2);
|
||||
imx_clk_scu("mipi1_i2c1_clk", IMX_SC_R_MIPI_1_I2C_1, IMX_SC_PM_CLK_MISC2);
|
||||
imx_clk_scu("mipi1_pwm0_clk", IMX_SC_R_MIPI_1_PWM_0, IMX_SC_PM_CLK_PER);
|
||||
|
||||
imx_clk_scu("lvds0_i2c0_clk", IMX_SC_R_LVDS_0_I2C_0, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("lvds0_i2c1_clk", IMX_SC_R_LVDS_0_I2C_1, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("lvds0_pwm0_clk", IMX_SC_R_LVDS_0_PWM_0, IMX_SC_PM_CLK_PER);
|
||||
|
||||
imx_clk_scu("lvds1_i2c0_clk", IMX_SC_R_LVDS_1_I2C_0, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("lvds1_i2c1_clk", IMX_SC_R_LVDS_1_I2C_1, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("lvds1_pwm0_clk", IMX_SC_R_LVDS_1_PWM_0, IMX_SC_PM_CLK_PER);
|
||||
|
||||
/* MIPI CSI SS */
|
||||
clks[IMX_CSI0_CORE_CLK] = imx_clk_scu("mipi_csi0_core_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_CSI0_ESC_CLK] = imx_clk_scu("mipi_csi0_esc_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_MISC, clk_cells);
|
||||
clks[IMX_CSI0_I2C0_CLK] = imx_clk_scu("mipi_csi0_i2c0_clk", IMX_SC_R_CSI_0_I2C_0, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_CSI0_PWM0_CLK] = imx_clk_scu("mipi_csi0_pwm0_clk", IMX_SC_R_CSI_0_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
imx_clk_scu("mipi_csi0_core_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("mipi_csi0_esc_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_MISC);
|
||||
imx_clk_scu("mipi_csi0_i2c0_clk", IMX_SC_R_CSI_0_I2C_0, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("mipi_csi0_pwm0_clk", IMX_SC_R_CSI_0_PWM_0, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("mipi_csi1_core_clk", IMX_SC_R_CSI_1, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("mipi_csi1_esc_clk", IMX_SC_R_CSI_1, IMX_SC_PM_CLK_MISC);
|
||||
imx_clk_scu("mipi_csi1_i2c0_clk", IMX_SC_R_CSI_1_I2C_0, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("mipi_csi1_pwm0_clk", IMX_SC_R_CSI_1_PWM_0, IMX_SC_PM_CLK_PER);
|
||||
|
||||
/* Parallel Interface SS */
|
||||
imx_clk_scu("pi_dpll_clk", IMX_SC_R_PI_0_PLL, IMX_SC_PM_CLK_PLL);
|
||||
imx_clk_scu2("pi_per_div_clk", pi_pll0_sels, ARRAY_SIZE(pi_pll0_sels), IMX_SC_R_PI_0, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("pi_mclk_div_clk", IMX_SC_R_PI_0, IMX_SC_PM_CLK_MISC0);
|
||||
imx_clk_scu("pi_i2c0_div_clk", IMX_SC_R_PI_0_I2C_0, IMX_SC_PM_CLK_PER);
|
||||
|
||||
/* GPU SS */
|
||||
clks[IMX_GPU0_CORE_CLK] = imx_clk_scu("gpu_core0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_GPU0_SHADER_CLK] = imx_clk_scu("gpu_shader0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_MISC, clk_cells);
|
||||
imx_clk_scu("gpu_core0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("gpu_shader0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_MISC);
|
||||
|
||||
for (i = 0; i < clk_data->num; i++) {
|
||||
if (IS_ERR(clks[i]))
|
||||
pr_warn("i.MX clk %u: register failed with %ld\n",
|
||||
i, PTR_ERR(clks[i]));
|
||||
}
|
||||
imx_clk_scu("gpu_core1_clk", IMX_SC_R_GPU_1_PID0, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("gpu_shader1_clk", IMX_SC_R_GPU_1_PID0, IMX_SC_PM_CLK_MISC);
|
||||
|
||||
if (clk_cells == 2) {
|
||||
ret = of_clk_add_hw_provider(ccm_node, imx_scu_of_clk_src_get, imx_scu_clks);
|
||||
if (ret)
|
||||
imx_clk_scu_unregister();
|
||||
} else {
|
||||
/*
|
||||
* legacy binding code path doesn't unregister here because
|
||||
* it will be removed later.
|
||||
*/
|
||||
ret = of_clk_add_hw_provider(ccm_node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
/* CM40 SS */
|
||||
imx_clk_scu("cm40_i2c_div", IMX_SC_R_M4_0_I2C, IMX_SC_PM_CLK_PER);
|
||||
imx_clk_scu("cm40_lpuart_div", IMX_SC_R_M4_0_UART, IMX_SC_PM_CLK_PER);
|
||||
|
||||
/* CM41 SS */
|
||||
imx_clk_scu("cm41_i2c_div", IMX_SC_R_M4_1_I2C, IMX_SC_PM_CLK_PER);
|
||||
|
||||
/* HDMI TX SS */
|
||||
imx_clk_scu("hdmi_dig_pll_clk", IMX_SC_R_HDMI_PLL_0, IMX_SC_PM_CLK_PLL);
|
||||
imx_clk_scu("hdmi_av_pll_clk", IMX_SC_R_HDMI_PLL_1, IMX_SC_PM_CLK_PLL);
|
||||
imx_clk_scu2("hdmi_pixel_mux_clk", hdmi_sels, ARRAY_SIZE(hdmi_sels), IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC0);
|
||||
imx_clk_scu2("hdmi_pixel_link_clk", hdmi_sels, ARRAY_SIZE(hdmi_sels), IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC1);
|
||||
imx_clk_scu("hdmi_ipg_clk", IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC4);
|
||||
imx_clk_scu("hdmi_i2c0_clk", IMX_SC_R_HDMI_I2C_0, IMX_SC_PM_CLK_MISC2);
|
||||
imx_clk_scu("hdmi_hdp_core_clk", IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC2);
|
||||
imx_clk_scu2("hdmi_pxl_clk", hdmi_sels, ARRAY_SIZE(hdmi_sels), IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC3);
|
||||
imx_clk_scu("hdmi_i2s_bypass_clk", IMX_SC_R_HDMI_I2S, IMX_SC_PM_CLK_BYPASS);
|
||||
imx_clk_scu("hdmi_i2s_clk", IMX_SC_R_HDMI_I2S, IMX_SC_PM_CLK_MISC0);
|
||||
|
||||
/* HDMI RX SS */
|
||||
imx_clk_scu("hdmi_rx_i2s_bypass_clk", IMX_SC_R_HDMI_RX_BYPASS, IMX_SC_PM_CLK_MISC0);
|
||||
imx_clk_scu("hdmi_rx_spdif_bypass_clk", IMX_SC_R_HDMI_RX_BYPASS, IMX_SC_PM_CLK_MISC1);
|
||||
imx_clk_scu("hdmi_rx_bypass_clk", IMX_SC_R_HDMI_RX_BYPASS, IMX_SC_PM_CLK_MISC2);
|
||||
imx_clk_scu("hdmi_rx_i2c0_clk", IMX_SC_R_HDMI_RX_I2C_0, IMX_SC_PM_CLK_MISC2);
|
||||
imx_clk_scu("hdmi_rx_pwm_clk", IMX_SC_R_HDMI_RX_PWM_0, IMX_SC_PM_CLK_MISC2);
|
||||
imx_clk_scu("hdmi_rx_spdif_clk", IMX_SC_R_HDMI_RX, IMX_SC_PM_CLK_MISC0);
|
||||
imx_clk_scu2("hdmi_rx_hd_ref_clk", hdmi_rx_sels, ARRAY_SIZE(hdmi_rx_sels), IMX_SC_R_HDMI_RX, IMX_SC_PM_CLK_MISC1);
|
||||
imx_clk_scu2("hdmi_rx_hd_core_clk", hdmi_rx_sels, ARRAY_SIZE(hdmi_rx_sels), IMX_SC_R_HDMI_RX, IMX_SC_PM_CLK_MISC2);
|
||||
imx_clk_scu2("hdmi_rx_pxl_clk", hdmi_rx_sels, ARRAY_SIZE(hdmi_rx_sels), IMX_SC_R_HDMI_RX, IMX_SC_PM_CLK_MISC3);
|
||||
imx_clk_scu("hdmi_rx_i2s_clk", IMX_SC_R_HDMI_RX, IMX_SC_PM_CLK_MISC4);
|
||||
|
||||
ret = of_clk_add_hw_provider(ccm_node, imx_scu_of_clk_src_get, imx_scu_clks);
|
||||
if (ret)
|
||||
imx_clk_scu_unregister();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct of_device_id imx8qxp_match[] = {
|
||||
{ .compatible = "fsl,scu-clk", },
|
||||
{ .compatible = "fsl,imx8qxp-clk", },
|
||||
{ .compatible = "fsl,imx8qxp-clk", &imx_clk_scu_rsrc_imx8qxp, },
|
||||
{ .compatible = "fsl,imx8qm-clk", &imx_clk_scu_rsrc_imx8qm, },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
|
||||
@@ -1,11 +1,12 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
* Copyright 2018-2021 NXP
|
||||
* Dong Aisheng <aisheng.dong@nxp.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/firmware/imx/rsrc.h>
|
||||
#include <linux/arm-smccc.h>
|
||||
#include <linux/bsearch.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/of_platform.h>
|
||||
@@ -22,6 +23,7 @@
|
||||
static struct imx_sc_ipc *ccm_ipc_handle;
|
||||
static struct device_node *pd_np;
|
||||
static struct platform_driver imx_clk_scu_driver;
|
||||
static const struct imx_clk_scu_rsrc_table *rsrc_table;
|
||||
|
||||
struct imx_scu_clk_node {
|
||||
const char *name;
|
||||
@@ -48,10 +50,28 @@ struct clk_scu {
|
||||
u8 clk_type;
|
||||
|
||||
/* for state save&restore */
|
||||
struct clk_hw *parent;
|
||||
u8 parent_index;
|
||||
bool is_enabled;
|
||||
u32 rate;
|
||||
};
|
||||
|
||||
/*
|
||||
* struct clk_gpr_scu - Description of one SCU GPR clock
|
||||
* @hw: the common clk_hw
|
||||
* @rsrc_id: resource ID of this SCU clock
|
||||
* @gpr_id: GPR ID index to control the divider
|
||||
*/
|
||||
struct clk_gpr_scu {
|
||||
struct clk_hw hw;
|
||||
u16 rsrc_id;
|
||||
u8 gpr_id;
|
||||
u8 flags;
|
||||
bool gate_invert;
|
||||
};
|
||||
|
||||
#define to_clk_gpr_scu(_hw) container_of(_hw, struct clk_gpr_scu, hw)
|
||||
|
||||
/*
|
||||
* struct imx_sc_msg_req_set_clock_rate - clock set rate protocol
|
||||
* @hdr: SCU protocol header
|
||||
@@ -151,7 +171,26 @@ static inline struct clk_scu *to_clk_scu(struct clk_hw *hw)
|
||||
return container_of(hw, struct clk_scu, hw);
|
||||
}
|
||||
|
||||
int imx_clk_scu_init(struct device_node *np)
|
||||
static inline int imx_scu_clk_search_cmp(const void *rsrc, const void *rsrc_p)
|
||||
{
|
||||
return *(u32 *)rsrc - *(u32 *)rsrc_p;
|
||||
}
|
||||
|
||||
static bool imx_scu_clk_is_valid(u32 rsrc_id)
|
||||
{
|
||||
void *p;
|
||||
|
||||
if (!rsrc_table)
|
||||
return true;
|
||||
|
||||
p = bsearch(&rsrc_id, rsrc_table->rsrc, rsrc_table->num,
|
||||
sizeof(rsrc_table->rsrc[0]), imx_scu_clk_search_cmp);
|
||||
|
||||
return p != NULL;
|
||||
}
|
||||
|
||||
int imx_clk_scu_init(struct device_node *np,
|
||||
const struct imx_clk_scu_rsrc_table *data)
|
||||
{
|
||||
u32 clk_cells;
|
||||
int ret, i;
|
||||
@@ -170,6 +209,8 @@ int imx_clk_scu_init(struct device_node *np)
|
||||
pd_np = of_find_compatible_node(NULL, NULL, "fsl,scu-pd");
|
||||
if (!pd_np)
|
||||
return -EINVAL;
|
||||
|
||||
rsrc_table = data;
|
||||
}
|
||||
|
||||
return platform_driver_register(&imx_clk_scu_driver);
|
||||
@@ -234,8 +275,10 @@ static int clk_scu_atf_set_cpu_rate(struct clk_hw *hw, unsigned long rate,
|
||||
struct arm_smccc_res res;
|
||||
unsigned long cluster_id;
|
||||
|
||||
if (clk->rsrc_id == IMX_SC_R_A35)
|
||||
if (clk->rsrc_id == IMX_SC_R_A35 || clk->rsrc_id == IMX_SC_R_A53)
|
||||
cluster_id = 0;
|
||||
else if (clk->rsrc_id == IMX_SC_R_A72)
|
||||
cluster_id = 1;
|
||||
else
|
||||
return -EINVAL;
|
||||
|
||||
@@ -296,6 +339,8 @@ static u8 clk_scu_get_parent(struct clk_hw *hw)
|
||||
return 0;
|
||||
}
|
||||
|
||||
clk->parent_index = msg.data.resp.parent;
|
||||
|
||||
return msg.data.resp.parent;
|
||||
}
|
||||
|
||||
@@ -304,6 +349,7 @@ static int clk_scu_set_parent(struct clk_hw *hw, u8 index)
|
||||
struct clk_scu *clk = to_clk_scu(hw);
|
||||
struct imx_sc_msg_set_clock_parent msg;
|
||||
struct imx_sc_rpc_msg *hdr = &msg.hdr;
|
||||
int ret;
|
||||
|
||||
hdr->ver = IMX_SC_RPC_VERSION;
|
||||
hdr->svc = IMX_SC_RPC_SVC_PM;
|
||||
@@ -314,7 +360,16 @@ static int clk_scu_set_parent(struct clk_hw *hw, u8 index)
|
||||
msg.clk = clk->clk_type;
|
||||
msg.parent = index;
|
||||
|
||||
return imx_scu_call_rpc(ccm_ipc_handle, &msg, true);
|
||||
ret = imx_scu_call_rpc(ccm_ipc_handle, &msg, true);
|
||||
if (ret) {
|
||||
pr_err("%s: failed to set clock parent %d\n",
|
||||
clk_hw_get_name(hw), ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
clk->parent_index = index;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sc_pm_clock_enable(struct imx_sc_ipc *ipc, u16 resource,
|
||||
@@ -386,6 +441,12 @@ static const struct clk_ops clk_scu_cpu_ops = {
|
||||
.unprepare = clk_scu_unprepare,
|
||||
};
|
||||
|
||||
static const struct clk_ops clk_scu_pi_ops = {
|
||||
.recalc_rate = clk_scu_recalc_rate,
|
||||
.round_rate = clk_scu_round_rate,
|
||||
.set_rate = clk_scu_set_rate,
|
||||
};
|
||||
|
||||
struct clk_hw *__imx_clk_scu(struct device *dev, const char *name,
|
||||
const char * const *parents, int num_parents,
|
||||
u32 rsrc_id, u8 clk_type)
|
||||
@@ -404,8 +465,10 @@ struct clk_hw *__imx_clk_scu(struct device *dev, const char *name,
|
||||
|
||||
init.name = name;
|
||||
init.ops = &clk_scu_ops;
|
||||
if (rsrc_id == IMX_SC_R_A35)
|
||||
if (rsrc_id == IMX_SC_R_A35 || rsrc_id == IMX_SC_R_A53 || rsrc_id == IMX_SC_R_A72)
|
||||
init.ops = &clk_scu_cpu_ops;
|
||||
else if (rsrc_id == IMX_SC_R_PI_0_PLL)
|
||||
init.ops = &clk_scu_pi_ops;
|
||||
else
|
||||
init.ops = &clk_scu_ops;
|
||||
init.parent_names = parents;
|
||||
@@ -458,15 +521,19 @@ static int imx_clk_scu_probe(struct platform_device *pdev)
|
||||
struct clk_hw *hw;
|
||||
int ret;
|
||||
|
||||
pm_runtime_set_suspended(dev);
|
||||
pm_runtime_set_autosuspend_delay(dev, 50);
|
||||
pm_runtime_use_autosuspend(&pdev->dev);
|
||||
pm_runtime_enable(dev);
|
||||
if (!((clk->rsrc == IMX_SC_R_A35) || (clk->rsrc == IMX_SC_R_A53) ||
|
||||
(clk->rsrc == IMX_SC_R_A72))) {
|
||||
pm_runtime_set_suspended(dev);
|
||||
pm_runtime_set_autosuspend_delay(dev, 50);
|
||||
pm_runtime_use_autosuspend(&pdev->dev);
|
||||
pm_runtime_enable(dev);
|
||||
|
||||
ret = pm_runtime_get_sync(dev);
|
||||
if (ret) {
|
||||
pm_runtime_disable(dev);
|
||||
return ret;
|
||||
ret = pm_runtime_get_sync(dev);
|
||||
if (ret) {
|
||||
pm_genpd_remove_device(dev);
|
||||
pm_runtime_disable(dev);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
hw = __imx_clk_scu(dev, clk->name, clk->parents, clk->num_parents,
|
||||
@@ -479,8 +546,11 @@ static int imx_clk_scu_probe(struct platform_device *pdev)
|
||||
clk->hw = hw;
|
||||
list_add_tail(&clk->node, &imx_scu_clks[clk->rsrc]);
|
||||
|
||||
pm_runtime_mark_last_busy(&pdev->dev);
|
||||
pm_runtime_put_autosuspend(&pdev->dev);
|
||||
if (!((clk->rsrc == IMX_SC_R_A35) || (clk->rsrc == IMX_SC_R_A53) ||
|
||||
(clk->rsrc == IMX_SC_R_A72))) {
|
||||
pm_runtime_mark_last_busy(&pdev->dev);
|
||||
pm_runtime_put_autosuspend(&pdev->dev);
|
||||
}
|
||||
|
||||
dev_dbg(dev, "register SCU clock rsrc:%d type:%d\n", clk->rsrc,
|
||||
clk->clk_type);
|
||||
@@ -491,10 +561,28 @@ static int imx_clk_scu_probe(struct platform_device *pdev)
|
||||
static int __maybe_unused imx_clk_scu_suspend(struct device *dev)
|
||||
{
|
||||
struct clk_scu *clk = dev_get_drvdata(dev);
|
||||
u32 rsrc_id = clk->rsrc_id;
|
||||
|
||||
clk->rate = clk_hw_get_rate(&clk->hw);
|
||||
if ((rsrc_id == IMX_SC_R_A35) || (rsrc_id == IMX_SC_R_A53) ||
|
||||
(rsrc_id == IMX_SC_R_A72))
|
||||
return 0;
|
||||
|
||||
clk->parent = clk_hw_get_parent(&clk->hw);
|
||||
|
||||
/* DC SS needs to handle bypass clock using non-cached clock rate */
|
||||
if (clk->rsrc_id == IMX_SC_R_DC_0_VIDEO0 ||
|
||||
clk->rsrc_id == IMX_SC_R_DC_0_VIDEO1 ||
|
||||
clk->rsrc_id == IMX_SC_R_DC_1_VIDEO0 ||
|
||||
clk->rsrc_id == IMX_SC_R_DC_1_VIDEO1)
|
||||
clk->rate = clk_scu_recalc_rate(&clk->hw, 0);
|
||||
else
|
||||
clk->rate = clk_hw_get_rate(&clk->hw);
|
||||
clk->is_enabled = clk_hw_is_enabled(&clk->hw);
|
||||
|
||||
if (clk->parent)
|
||||
dev_dbg(dev, "save parent %s idx %u\n", clk_hw_get_name(clk->parent),
|
||||
clk->parent_index);
|
||||
|
||||
if (clk->rate)
|
||||
dev_dbg(dev, "save rate %d\n", clk->rate);
|
||||
|
||||
@@ -507,15 +595,27 @@ static int __maybe_unused imx_clk_scu_suspend(struct device *dev)
|
||||
static int __maybe_unused imx_clk_scu_resume(struct device *dev)
|
||||
{
|
||||
struct clk_scu *clk = dev_get_drvdata(dev);
|
||||
u32 rsrc_id = clk->rsrc_id;
|
||||
int ret = 0;
|
||||
|
||||
if ((rsrc_id == IMX_SC_R_A35) || (rsrc_id == IMX_SC_R_A53) ||
|
||||
(rsrc_id == IMX_SC_R_A72))
|
||||
return 0;
|
||||
|
||||
if (clk->parent) {
|
||||
ret = clk_scu_set_parent(&clk->hw, clk->parent_index);
|
||||
dev_dbg(dev, "restore parent %s idx %u %s\n",
|
||||
clk_hw_get_name(clk->parent),
|
||||
clk->parent_index, !ret ? "success" : "failed");
|
||||
}
|
||||
|
||||
if (clk->rate) {
|
||||
ret = clk_scu_set_rate(&clk->hw, clk->rate, 0);
|
||||
dev_dbg(dev, "restore rate %d %s\n", clk->rate,
|
||||
!ret ? "success" : "failed");
|
||||
}
|
||||
|
||||
if (clk->is_enabled) {
|
||||
if (clk->is_enabled && rsrc_id != IMX_SC_R_PI_0_PLL) {
|
||||
ret = clk_scu_prepare(&clk->hw);
|
||||
dev_dbg(dev, "restore enabled state %s\n",
|
||||
!ret ? "success" : "failed");
|
||||
@@ -567,6 +667,9 @@ struct clk_hw *imx_clk_scu_alloc_dev(const char *name,
|
||||
struct platform_device *pdev;
|
||||
int ret;
|
||||
|
||||
if (!imx_scu_clk_is_valid(rsrc_id))
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
pdev = platform_device_alloc(name, PLATFORM_DEVID_NONE);
|
||||
if (!pdev) {
|
||||
pr_err("%s: failed to allocate scu clk dev rsrc %d type %d\n",
|
||||
@@ -605,3 +708,176 @@ void imx_clk_scu_unregister(void)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static unsigned long clk_gpr_div_scu_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
|
||||
unsigned long rate = 0;
|
||||
u32 val;
|
||||
int err;
|
||||
|
||||
err = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
|
||||
clk->gpr_id, &val);
|
||||
|
||||
rate = val ? parent_rate / 2 : parent_rate;
|
||||
|
||||
return err ? 0 : rate;
|
||||
}
|
||||
|
||||
static long clk_gpr_div_scu_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
if (rate < *prate)
|
||||
rate = *prate / 2;
|
||||
else
|
||||
rate = *prate;
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
||||
static int clk_gpr_div_scu_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
|
||||
uint32_t val;
|
||||
int err;
|
||||
|
||||
val = (rate < parent_rate) ? 1 : 0;
|
||||
err = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
|
||||
clk->gpr_id, val);
|
||||
|
||||
return err ? -EINVAL : 0;
|
||||
}
|
||||
|
||||
static const struct clk_ops clk_gpr_div_scu_ops = {
|
||||
.recalc_rate = clk_gpr_div_scu_recalc_rate,
|
||||
.round_rate = clk_gpr_div_scu_round_rate,
|
||||
.set_rate = clk_gpr_div_scu_set_rate,
|
||||
};
|
||||
|
||||
static u8 clk_gpr_mux_scu_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
|
||||
u32 val = 0;
|
||||
|
||||
imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
|
||||
clk->gpr_id, &val);
|
||||
|
||||
return (u8)val;
|
||||
}
|
||||
|
||||
static int clk_gpr_mux_scu_set_parent(struct clk_hw *hw, u8 index)
|
||||
{
|
||||
struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
|
||||
|
||||
return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
|
||||
clk->gpr_id, index);
|
||||
}
|
||||
|
||||
static const struct clk_ops clk_gpr_mux_scu_ops = {
|
||||
.get_parent = clk_gpr_mux_scu_get_parent,
|
||||
.set_parent = clk_gpr_mux_scu_set_parent,
|
||||
};
|
||||
|
||||
static int clk_gpr_gate_scu_prepare(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
|
||||
|
||||
return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
|
||||
clk->gpr_id, !clk->gate_invert);
|
||||
}
|
||||
|
||||
static void clk_gpr_gate_scu_unprepare(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
|
||||
int ret;
|
||||
|
||||
ret = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
|
||||
clk->gpr_id, clk->gate_invert);
|
||||
if (ret)
|
||||
pr_err("%s: clk unprepare failed %d\n", clk_hw_get_name(hw),
|
||||
ret);
|
||||
}
|
||||
|
||||
static int clk_gpr_gate_scu_is_prepared(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
|
||||
int ret;
|
||||
u32 val;
|
||||
|
||||
ret = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
|
||||
clk->gpr_id, &val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return clk->gate_invert ? !val : val;
|
||||
}
|
||||
|
||||
static const struct clk_ops clk_gpr_gate_scu_ops = {
|
||||
.prepare = clk_gpr_gate_scu_prepare,
|
||||
.unprepare = clk_gpr_gate_scu_unprepare,
|
||||
.is_prepared = clk_gpr_gate_scu_is_prepared,
|
||||
};
|
||||
|
||||
struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_name,
|
||||
int num_parents, u32 rsrc_id, u8 gpr_id, u8 flags,
|
||||
bool invert)
|
||||
{
|
||||
struct imx_scu_clk_node *clk_node;
|
||||
struct clk_gpr_scu *clk;
|
||||
struct clk_hw *hw;
|
||||
struct clk_init_data init;
|
||||
int ret;
|
||||
|
||||
if (rsrc_id >= IMX_SC_R_LAST || gpr_id >= IMX_SC_C_LAST)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
clk_node = kzalloc(sizeof(*clk_node), GFP_KERNEL);
|
||||
if (!clk_node)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
if (!imx_scu_clk_is_valid(rsrc_id))
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
clk = kzalloc(sizeof(*clk), GFP_KERNEL);
|
||||
if (!clk) {
|
||||
kfree(clk_node);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
clk->rsrc_id = rsrc_id;
|
||||
clk->gpr_id = gpr_id;
|
||||
clk->flags = flags;
|
||||
clk->gate_invert = invert;
|
||||
|
||||
if (flags & IMX_SCU_GPR_CLK_GATE)
|
||||
init.ops = &clk_gpr_gate_scu_ops;
|
||||
|
||||
if (flags & IMX_SCU_GPR_CLK_DIV)
|
||||
init.ops = &clk_gpr_div_scu_ops;
|
||||
|
||||
if (flags & IMX_SCU_GPR_CLK_MUX)
|
||||
init.ops = &clk_gpr_mux_scu_ops;
|
||||
|
||||
init.flags = 0;
|
||||
init.name = name;
|
||||
init.parent_names = parent_name;
|
||||
init.num_parents = num_parents;
|
||||
|
||||
clk->hw.init = &init;
|
||||
|
||||
hw = &clk->hw;
|
||||
ret = clk_hw_register(NULL, hw);
|
||||
if (ret) {
|
||||
kfree(clk);
|
||||
kfree(clk_node);
|
||||
hw = ERR_PTR(ret);
|
||||
} else {
|
||||
clk_node->hw = hw;
|
||||
clk_node->clk_type = gpr_id;
|
||||
list_add_tail(&clk_node->node, &imx_scu_clks[rsrc_id]);
|
||||
}
|
||||
|
||||
return hw;
|
||||
}
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
* Copyright 2018-2021 NXP
|
||||
* Dong Aisheng <aisheng.dong@nxp.com>
|
||||
*/
|
||||
|
||||
@@ -10,10 +10,22 @@
|
||||
#include <linux/firmware/imx/sci.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#define IMX_SCU_GPR_CLK_GATE BIT(0)
|
||||
#define IMX_SCU_GPR_CLK_DIV BIT(1)
|
||||
#define IMX_SCU_GPR_CLK_MUX BIT(2)
|
||||
|
||||
struct imx_clk_scu_rsrc_table {
|
||||
const u32 *rsrc;
|
||||
u8 num;
|
||||
};
|
||||
|
||||
extern struct list_head imx_scu_clks[];
|
||||
extern const struct dev_pm_ops imx_clk_lpcg_scu_pm_ops;
|
||||
extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qxp;
|
||||
extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm;
|
||||
|
||||
int imx_clk_scu_init(struct device_node *np);
|
||||
int imx_clk_scu_init(struct device_node *np,
|
||||
const struct imx_clk_scu_rsrc_table *data);
|
||||
struct clk_hw *imx_scu_of_clk_src_get(struct of_phandle_args *clkspec,
|
||||
void *data);
|
||||
struct clk_hw *imx_clk_scu_alloc_dev(const char *name,
|
||||
@@ -31,23 +43,20 @@ struct clk_hw *__imx_clk_lpcg_scu(struct device *dev, const char *name,
|
||||
void __iomem *reg, u8 bit_idx, bool hw_gate);
|
||||
void imx_clk_lpcg_scu_unregister(struct clk_hw *hw);
|
||||
|
||||
struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_name,
|
||||
int num_parents, u32 rsrc_id, u8 gpr_id, u8 flags,
|
||||
bool invert);
|
||||
|
||||
static inline struct clk_hw *imx_clk_scu(const char *name, u32 rsrc_id,
|
||||
u8 clk_type, u8 clk_cells)
|
||||
u8 clk_type)
|
||||
{
|
||||
if (clk_cells == 2)
|
||||
return imx_clk_scu_alloc_dev(name, NULL, 0, rsrc_id, clk_type);
|
||||
else
|
||||
return __imx_clk_scu(NULL, name, NULL, 0, rsrc_id, clk_type);
|
||||
return imx_clk_scu_alloc_dev(name, NULL, 0, rsrc_id, clk_type);
|
||||
}
|
||||
|
||||
static inline struct clk_hw *imx_clk_scu2(const char *name, const char * const *parents,
|
||||
int num_parents, u32 rsrc_id, u8 clk_type,
|
||||
u8 clk_cells)
|
||||
int num_parents, u32 rsrc_id, u8 clk_type)
|
||||
{
|
||||
if (clk_cells == 2)
|
||||
return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type);
|
||||
else
|
||||
return __imx_clk_scu(NULL, name, parents, num_parents, rsrc_id, clk_type);
|
||||
return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type);
|
||||
}
|
||||
|
||||
static inline struct clk_hw *imx_clk_lpcg_scu_dev(struct device *dev, const char *name,
|
||||
@@ -65,4 +74,25 @@ static inline struct clk_hw *imx_clk_lpcg_scu(const char *name, const char *pare
|
||||
return __imx_clk_lpcg_scu(NULL, name, parent_name, flags, reg,
|
||||
bit_idx, hw_gate);
|
||||
}
|
||||
|
||||
static inline struct clk_hw *imx_clk_gate_gpr_scu(const char *name, const char *parent_name,
|
||||
u32 rsrc_id, u8 gpr_id, bool invert)
|
||||
{
|
||||
return __imx_clk_gpr_scu(name, &parent_name, 1, rsrc_id, gpr_id,
|
||||
IMX_SCU_GPR_CLK_GATE, invert);
|
||||
}
|
||||
|
||||
static inline struct clk_hw *imx_clk_divider_gpr_scu(const char *name, const char *parent_name,
|
||||
u32 rsrc_id, u8 gpr_id)
|
||||
{
|
||||
return __imx_clk_gpr_scu(name, &parent_name, 1, rsrc_id, gpr_id,
|
||||
IMX_SCU_GPR_CLK_DIV, 0);
|
||||
}
|
||||
|
||||
static inline struct clk_hw *imx_clk_mux_gpr_scu(const char *name, const char * const *parent_names,
|
||||
int num_parents, u32 rsrc_id, u8 gpr_id)
|
||||
{
|
||||
return __imx_clk_gpr_scu(name, parent_names, num_parents, rsrc_id,
|
||||
gpr_id, IMX_SCU_GPR_CLK_MUX, 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -7,134 +7,6 @@
|
||||
#ifndef __DT_BINDINGS_CLOCK_IMX_H
|
||||
#define __DT_BINDINGS_CLOCK_IMX_H
|
||||
|
||||
/* SCU Clocks */
|
||||
|
||||
#define IMX_CLK_DUMMY 0
|
||||
|
||||
/* CPU */
|
||||
#define IMX_A35_CLK 1
|
||||
|
||||
/* LSIO SS */
|
||||
#define IMX_LSIO_MEM_CLK 2
|
||||
#define IMX_LSIO_BUS_CLK 3
|
||||
#define IMX_LSIO_PWM0_CLK 10
|
||||
#define IMX_LSIO_PWM1_CLK 11
|
||||
#define IMX_LSIO_PWM2_CLK 12
|
||||
#define IMX_LSIO_PWM3_CLK 13
|
||||
#define IMX_LSIO_PWM4_CLK 14
|
||||
#define IMX_LSIO_PWM5_CLK 15
|
||||
#define IMX_LSIO_PWM6_CLK 16
|
||||
#define IMX_LSIO_PWM7_CLK 17
|
||||
#define IMX_LSIO_GPT0_CLK 18
|
||||
#define IMX_LSIO_GPT1_CLK 19
|
||||
#define IMX_LSIO_GPT2_CLK 20
|
||||
#define IMX_LSIO_GPT3_CLK 21
|
||||
#define IMX_LSIO_GPT4_CLK 22
|
||||
#define IMX_LSIO_FSPI0_CLK 23
|
||||
#define IMX_LSIO_FSPI1_CLK 24
|
||||
|
||||
/* Connectivity SS */
|
||||
#define IMX_CONN_AXI_CLK_ROOT 30
|
||||
#define IMX_CONN_AHB_CLK_ROOT 31
|
||||
#define IMX_CONN_IPG_CLK_ROOT 32
|
||||
#define IMX_CONN_SDHC0_CLK 40
|
||||
#define IMX_CONN_SDHC1_CLK 41
|
||||
#define IMX_CONN_SDHC2_CLK 42
|
||||
#define IMX_CONN_ENET0_ROOT_CLK 43
|
||||
#define IMX_CONN_ENET0_BYPASS_CLK 44
|
||||
#define IMX_CONN_ENET0_RGMII_CLK 45
|
||||
#define IMX_CONN_ENET1_ROOT_CLK 46
|
||||
#define IMX_CONN_ENET1_BYPASS_CLK 47
|
||||
#define IMX_CONN_ENET1_RGMII_CLK 48
|
||||
#define IMX_CONN_GPMI_BCH_IO_CLK 49
|
||||
#define IMX_CONN_GPMI_BCH_CLK 50
|
||||
#define IMX_CONN_USB2_ACLK 51
|
||||
#define IMX_CONN_USB2_BUS_CLK 52
|
||||
#define IMX_CONN_USB2_LPM_CLK 53
|
||||
|
||||
/* HSIO SS */
|
||||
#define IMX_HSIO_AXI_CLK 60
|
||||
#define IMX_HSIO_PER_CLK 61
|
||||
|
||||
/* Display controller SS */
|
||||
#define IMX_DC_AXI_EXT_CLK 70
|
||||
#define IMX_DC_AXI_INT_CLK 71
|
||||
#define IMX_DC_CFG_CLK 72
|
||||
#define IMX_DC0_PLL0_CLK 80
|
||||
#define IMX_DC0_PLL1_CLK 81
|
||||
#define IMX_DC0_DISP0_CLK 82
|
||||
#define IMX_DC0_DISP1_CLK 83
|
||||
#define IMX_DC0_BYPASS0_CLK 84
|
||||
#define IMX_DC0_BYPASS1_CLK 85
|
||||
|
||||
/* MIPI-LVDS SS */
|
||||
#define IMX_MIPI_IPG_CLK 90
|
||||
#define IMX_MIPI0_PIXEL_CLK 100
|
||||
#define IMX_MIPI0_BYPASS_CLK 101
|
||||
#define IMX_MIPI0_LVDS_PIXEL_CLK 102
|
||||
#define IMX_MIPI0_LVDS_BYPASS_CLK 103
|
||||
#define IMX_MIPI0_LVDS_PHY_CLK 104
|
||||
#define IMX_MIPI0_I2C0_CLK 105
|
||||
#define IMX_MIPI0_I2C1_CLK 106
|
||||
#define IMX_MIPI0_PWM0_CLK 107
|
||||
#define IMX_MIPI1_PIXEL_CLK 108
|
||||
#define IMX_MIPI1_BYPASS_CLK 109
|
||||
#define IMX_MIPI1_LVDS_PIXEL_CLK 110
|
||||
#define IMX_MIPI1_LVDS_BYPASS_CLK 111
|
||||
#define IMX_MIPI1_LVDS_PHY_CLK 112
|
||||
#define IMX_MIPI1_I2C0_CLK 113
|
||||
#define IMX_MIPI1_I2C1_CLK 114
|
||||
#define IMX_MIPI1_PWM0_CLK 115
|
||||
|
||||
/* IMG SS */
|
||||
#define IMX_IMG_AXI_CLK 120
|
||||
#define IMX_IMG_IPG_CLK 121
|
||||
#define IMX_IMG_PXL_CLK 122
|
||||
|
||||
/* MIPI-CSI SS */
|
||||
#define IMX_CSI0_CORE_CLK 130
|
||||
#define IMX_CSI0_ESC_CLK 131
|
||||
#define IMX_CSI0_PWM0_CLK 132
|
||||
#define IMX_CSI0_I2C0_CLK 133
|
||||
|
||||
/* PARALLER CSI SS */
|
||||
#define IMX_PARALLEL_CSI_DPLL_CLK 140
|
||||
#define IMX_PARALLEL_CSI_PIXEL_CLK 141
|
||||
#define IMX_PARALLEL_CSI_MCLK_CLK 142
|
||||
|
||||
/* VPU SS */
|
||||
#define IMX_VPU_ENC_CLK 150
|
||||
#define IMX_VPU_DEC_CLK 151
|
||||
|
||||
/* GPU SS */
|
||||
#define IMX_GPU0_CORE_CLK 160
|
||||
#define IMX_GPU0_SHADER_CLK 161
|
||||
|
||||
/* ADMA SS */
|
||||
#define IMX_ADMA_IPG_CLK_ROOT 165
|
||||
#define IMX_ADMA_UART0_CLK 170
|
||||
#define IMX_ADMA_UART1_CLK 171
|
||||
#define IMX_ADMA_UART2_CLK 172
|
||||
#define IMX_ADMA_UART3_CLK 173
|
||||
#define IMX_ADMA_SPI0_CLK 174
|
||||
#define IMX_ADMA_SPI1_CLK 175
|
||||
#define IMX_ADMA_SPI2_CLK 176
|
||||
#define IMX_ADMA_SPI3_CLK 177
|
||||
#define IMX_ADMA_CAN0_CLK 178
|
||||
#define IMX_ADMA_CAN1_CLK 179
|
||||
#define IMX_ADMA_CAN2_CLK 180
|
||||
#define IMX_ADMA_I2C0_CLK 181
|
||||
#define IMX_ADMA_I2C1_CLK 182
|
||||
#define IMX_ADMA_I2C2_CLK 183
|
||||
#define IMX_ADMA_I2C3_CLK 184
|
||||
#define IMX_ADMA_FTM0_CLK 185
|
||||
#define IMX_ADMA_FTM1_CLK 186
|
||||
#define IMX_ADMA_ADC0_CLK 187
|
||||
#define IMX_ADMA_PWM_CLK 188
|
||||
#define IMX_ADMA_LCD_CLK 189
|
||||
|
||||
#define IMX_SCU_CLK_END 190
|
||||
|
||||
/* LPCG clocks */
|
||||
|
||||
/* LSIO SS LPCG */
|
||||
|
||||
@@ -405,25 +405,6 @@
|
||||
|
||||
#define IMX8MQ_VIDEO2_PLL1_REF_SEL 266
|
||||
|
||||
#define IMX8MQ_SYS1_PLL_40M_CG 267
|
||||
#define IMX8MQ_SYS1_PLL_80M_CG 268
|
||||
#define IMX8MQ_SYS1_PLL_100M_CG 269
|
||||
#define IMX8MQ_SYS1_PLL_133M_CG 270
|
||||
#define IMX8MQ_SYS1_PLL_160M_CG 271
|
||||
#define IMX8MQ_SYS1_PLL_200M_CG 272
|
||||
#define IMX8MQ_SYS1_PLL_266M_CG 273
|
||||
#define IMX8MQ_SYS1_PLL_400M_CG 274
|
||||
#define IMX8MQ_SYS1_PLL_800M_CG 275
|
||||
#define IMX8MQ_SYS2_PLL_50M_CG 276
|
||||
#define IMX8MQ_SYS2_PLL_100M_CG 277
|
||||
#define IMX8MQ_SYS2_PLL_125M_CG 278
|
||||
#define IMX8MQ_SYS2_PLL_166M_CG 279
|
||||
#define IMX8MQ_SYS2_PLL_200M_CG 280
|
||||
#define IMX8MQ_SYS2_PLL_250M_CG 281
|
||||
#define IMX8MQ_SYS2_PLL_333M_CG 282
|
||||
#define IMX8MQ_SYS2_PLL_500M_CG 283
|
||||
#define IMX8MQ_SYS2_PLL_1000M_CG 284
|
||||
|
||||
#define IMX8MQ_CLK_GPU_CORE 285
|
||||
#define IMX8MQ_CLK_GPU_SHADER 286
|
||||
#define IMX8MQ_CLK_M4_CORE 287
|
||||
|
||||
Reference in New Issue
Block a user