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ARM64: dts: rockchip: rk3399 dtsi fix for upstream
Fix rk3399.dtsi for upstream, includes: - remove psci related codes due to no impletement - rmeove pmu node since wrong content - add spi 3/4/5 - fix pmucru Change-Id: I078874c35e66ef8301e40a753a2acbae9f10b852 Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
This commit is contained in:
Jianqun Xu
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Gerrit Code Review
Gerrit Code Review
parent
c2b591a805
commit
8e7b7be080
@@ -40,8 +40,9 @@
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/clock/rk3399-cru.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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/ {
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@@ -57,11 +58,6 @@
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serial3 = &uart3;
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};
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psci {
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compatible = "arm,psci";
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method = "smc";
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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@@ -92,82 +88,49 @@
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};
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};
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idle-states {
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entry-method = "psci";
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cpu_sleep: cpu-sleep-0 {
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compatible = "arm,idle-state";
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};
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};
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cpu_l0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x0>;
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cpu-idle-states = <&cpu_sleep>;
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enable-method = "psci";
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};
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cpu_l1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x1>;
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cpu-idle-states = <&cpu_sleep>;
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enable-method = "psci";
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};
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cpu_l2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x2>;
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cpu-idle-states = <&cpu_sleep>;
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enable-method = "psci";
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};
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cpu_l3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x3>;
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cpu-idle-states = <&cpu_sleep>;
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enable-method = "psci";
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};
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cpu_b0: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a72", "arm,armv8";
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reg = <0x0 0x100>;
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cpu-idle-states = <&cpu_sleep>;
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enable-method = "psci";
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};
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cpu_b1: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a72", "arm,armv8";
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reg = <0x0 0x101>;
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cpu-idle-states = <&cpu_sleep>;
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enable-method = "psci";
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};
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
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interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
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<&cpu_l3>, <&cpu_b0>, <&cpu_b1>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts =
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<GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <24000000>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
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};
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xin24m: xin24m {
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@@ -190,9 +153,7 @@
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<0x0 0xfff00000 0 0x10000>, /* GICC */
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<0x0 0xfff10000 0 0x10000>, /* GICH */
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<0x0 0xfff20000 0 0x10000>; /* GICV */
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interrupts =
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<GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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its: interrupt-controller@fee20000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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@@ -209,8 +170,8 @@
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dmac_bus: dma-controller@ff6d0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x0 0xff6d0000 0x0 0x4000>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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clocks = <&cru ACLK_DMAC0_PERILP>;
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clock-names = "apb_pclk";
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@@ -219,8 +180,8 @@
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dmac_peri: dma-controller@ff6e0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x0 0xff6e0000 0x0 0x4000>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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clocks = <&cru ACLK_DMAC1_PERILP>;
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clock-names = "apb_pclk";
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@@ -271,11 +232,89 @@
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status = "disabled";
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};
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spi0: spi@ff1c0000 {
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compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
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reg = <0x0 0xff110000 0x0 0x1000>;
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clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
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clock-names = "spiclk", "apb_pclk";
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi1: spi@ff1d0000 {
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compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
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reg = <0x0 0xff120000 0x0 0x1000>;
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clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
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clock-names = "spiclk", "apb_pclk";
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi2: spi@ff1e0000 {
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compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
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reg = <0x0 0xff130000 0x0 0x1000>;
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clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
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clock-names = "spiclk", "apb_pclk";
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi4: spi@ff1f0000 {
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compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
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reg = <0x0 0xff120000 0x0 0x1000>;
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clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
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clock-names = "spiclk", "apb_pclk";
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi5: spi@ff200000 {
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compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
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reg = <0x0 0xff130000 0x0 0x1000>;
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clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
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clock-names = "spiclk", "apb_pclk";
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interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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pmugrf: syscon@ff320000 {
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compatible = "rockchip,rk3399-pmugrf", "syscon";
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reg = <0x0 0xff320000 0x0 0x1000>;
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};
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spi3: spi@ff350000 {
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compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
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reg = <0x0 0xff110000 0x0 0x1000>;
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clocks = <&cru SCLK_SPI3_PMU>, <&cru PCLK_SPI3_PMU>;
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clock-names = "spiclk", "apb_pclk";
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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uart4: serial@ff370000 {
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compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
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reg = <0x0 0xff370000 0x0 0x100>;
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@@ -287,9 +326,10 @@
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status = "disabled";
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};
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cru_pmu: pmu-clock-controller@ff750000 {
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compatible = "rockchip,rk3399-pmu-cru";
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pmucru: pmu-clock-controller@ff750000 {
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compatible = "rockchip,rk3399-pmucru";
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reg = <0x0 0xff750000 0x0 0x1000>;
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rockchip,grf = <&pmugrf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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