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drm/rockchip: vop: Add dclk rate count for RV1126B

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RV1126B supports calculating the exact dclk from the known aclk rate.

Change-Id: I92539f34eda514a5f35ce53ece98109dac888d6c
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
This commit is contained in:
Chaoyi Chen
2025-01-22 09:26:52 +08:00
committed by Tao Huang
parent c80bc3d76f
commit 8f17704e58
4 changed files with 30 additions and 0 deletions
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22
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
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@@ -2921,6 +2921,7 @@ static int vop_crtc_debugfs_init(struct drm_minor *minor, struct drm_crtc *crtc)
rockchip_drm_add_dump_buffer(crtc, vop->debugfs); rockchip_drm_add_dump_buffer(crtc, vop->debugfs);
rockchip_drm_debugfs_add_regs_write(crtc, vop->debugfs); rockchip_drm_debugfs_add_regs_write(crtc, vop->debugfs);
rockchip_drm_debugfs_add_color_bar(crtc, vop->debugfs); rockchip_drm_debugfs_add_color_bar(crtc, vop->debugfs);
rockchip_drm_debugfs_add_dclk_rate(crtc, vop->debugfs);
#endif #endif
for (i = 0; i < ARRAY_SIZE(vop_debugfs_files); i++) for (i = 0; i < ARRAY_SIZE(vop_debugfs_files); i++)
vop->debugfs_files[i].data = vop; vop->debugfs_files[i].data = vop;
@@ -3349,6 +3350,26 @@ static int vop_crtc_set_color_bar(struct drm_crtc *crtc, enum rockchip_color_bar
return ret; return ret;
} }
static unsigned long vop_crtc_get_dclk_rate(struct drm_crtc *crtc)
{
struct vop *vop = to_vop(crtc);
unsigned long rate, count;
if (!VOP_CTRL_SUPPORT(vop, calc_dclk_cnt))
return 0;
VOP_CTRL_SET(vop, calc_clk_en, 1);
usleep_range(500, 1000);
count = VOP_CTRL_GET(vop, calc_dclk_cnt);
rate = clk_get_rate(vop->aclk);
/* calc_dclk_cnt is the count number when aclk counts to 10000 */
rate = rate / 10000 * count;
VOP_CTRL_SET(vop, calc_clk_en, 0);
return rate;
}
#endif #endif
static const struct rockchip_crtc_funcs private_crtc_funcs = { static const struct rockchip_crtc_funcs private_crtc_funcs = {
@@ -3366,6 +3387,7 @@ static const struct rockchip_crtc_funcs private_crtc_funcs = {
.te_handler = vop_crtc_te_handler, .te_handler = vop_crtc_te_handler,
#if defined(CONFIG_ROCKCHIP_DRM_DEBUG) #if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
.crtc_set_color_bar = vop_crtc_set_color_bar, .crtc_set_color_bar = vop_crtc_set_color_bar,
.crtc_get_dclk_rate = vop_crtc_get_dclk_rate,
#endif #endif
}; };

4
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
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@@ -476,6 +476,10 @@ struct vop_ctrl {
/* color bar */ /* color bar */
struct vop_reg color_bar_en; struct vop_reg color_bar_en;
struct vop_reg color_bar_mode; struct vop_reg color_bar_mode;
/* clk cnt */
struct vop_reg calc_clk_en;
struct vop_reg calc_dclk_cnt;
}; };
struct vop_intr { struct vop_intr {

3
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
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@@ -1953,6 +1953,9 @@ static const struct vop_ctrl rv1126b_ctrl_data = {
.color_bar_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xff, 28), .color_bar_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xff, 28),
.color_bar_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xff, 31), .color_bar_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xff, 31),
.calc_dclk_cnt = VOP_REG(RV1126B_CLK_CNT, 0x7fff, 0),
.calc_clk_en = VOP_REG(RV1126B_CLK_CNT, 0x1, 15),
.htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
.hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0), .hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0),
.vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), .vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0),

1
drivers/gpu/drm/rockchip/rockchip_vop_reg.h
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@@ -1039,6 +1039,7 @@
#define RV1126_GRF_IOFUNC_CON3 0x1026c #define RV1126_GRF_IOFUNC_CON3 0x1026c
#define RV1126B_CLK_CNT 0x0040
#define RV1126B_GRF_VOP_LCDC_CON 0x30b9c #define RV1126B_GRF_VOP_LCDC_CON 0x30b9c
#define RK3506_GRF_SOC_CON2 0x0008 #define RK3506_GRF_SOC_CON2 0x0008