From 8ff91bcd82d33becdb5022b6e4dff64ee0243e3e Mon Sep 17 00:00:00 2001 From: Liang Chen Date: Wed, 20 Oct 2021 20:15:17 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3588s: add capacity-dmips-mhz for cpu node add capacity-dmips-mhz for each cpu, so that schedule can select the best cpu for a task. Change-Id: I2799f09e5e0f16d0749bb63aaaf42c7e498d89dd Signed-off-by: Liang Chen --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 39743a6bba8a..7a2f6ed77ffa 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -87,6 +87,7 @@ compatible = "arm,cortex-a55"; reg = <0x0>; enable-method = "psci"; + capacity-dmips-mhz = <530>; }; cpu_l1: cpu@100 { @@ -94,6 +95,7 @@ compatible = "arm,cortex-a55"; reg = <0x100>; enable-method = "psci"; + capacity-dmips-mhz = <530>; }; cpu_l2: cpu@200 { @@ -101,6 +103,7 @@ compatible = "arm,cortex-a55"; reg = <0x200>; enable-method = "psci"; + capacity-dmips-mhz = <530>; }; cpu_l3: cpu@300 { @@ -108,6 +111,7 @@ compatible = "arm,cortex-a55"; reg = <0x300>; enable-method = "psci"; + capacity-dmips-mhz = <530>; }; cpu_b0: cpu@400 { @@ -115,6 +119,7 @@ compatible = "arm,cortex-a76"; reg = <0x400>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; }; cpu_b1: cpu@500 { @@ -122,6 +127,7 @@ compatible = "arm,cortex-a76"; reg = <0x500>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; }; cpu_b2: cpu@600 { @@ -129,6 +135,7 @@ compatible = "arm,cortex-a76"; reg = <0x600>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; }; cpu_b3: cpu@700 { @@ -136,6 +143,7 @@ compatible = "arm,cortex-a76"; reg = <0x700>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; }; };