From d0e6f8a073819af4aae92ac6c323ade172587b6f Mon Sep 17 00:00:00 2001 From: Jianwei Zheng Date: Thu, 10 Aug 2023 17:20:39 +0800 Subject: [PATCH] phy: rockchip: naneng-combphy: fix U3 RX long cable test failed for RK3528 1.Set slow slew rate control for PI 2.Set CDR phase path with 2x gain Signed-off-by: Jianwei Zheng Change-Id: I2d0811b0be7b1d4764ecd738d069b06e4da5eaa2 --- drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 2114b37d52ed..3e8e4363e70e 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -483,6 +483,18 @@ static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv) val |= 0x01 << 17; writel(val, priv->mmio + 0x200); + /* Set slow slew rate control for PI */ + val = readl(priv->mmio + 0x204); + val &= ~GENMASK(2, 0); + val |= 0x07; + writel(val, priv->mmio + 0x204); + + /* Set CDR phase path with 2x gain */ + val = readl(priv->mmio + 0x204); + val &= ~GENMASK(5, 5); + val |= 0x01 << 5; + writel(val, priv->mmio + 0x204); + /* Set Rx squelch input filler bandwidth */ val = readl(priv->mmio + 0x20c); val &= ~GENMASK(2, 0);