From 9190b05f4aa805782cc0d0ca404e046370df90fa Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Thu, 24 Sep 2020 16:08:18 +0800 Subject: [PATCH] clk: rockchip: rk3568: export PCLK_EDPPHY_GRF clock id Change-Id: Ic16fbe5ab6831d7797d417bfce75d9a3c3964fe4 Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-rk3568.c | 2 ++ include/dt-bindings/clock/rk3568-cru.h | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index 0f97d9ee8062..c68caaa3e742 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -1463,6 +1463,8 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { RK3568_CLKGATE_CON(34), 12, GFLAGS), GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_top", 0, RK3568_CLKGATE_CON(34), 13, GFLAGS), + GATE(PCLK_EDPPHY_GRF, "pclk_edpphy_grf", "pclk_top", 0, + RK3568_CLKGATE_CON(34), 14, GFLAGS), }; static struct rockchip_clk_branch rk3568_clk_pmu_branches[] __initdata = { diff --git a/include/dt-bindings/clock/rk3568-cru.h b/include/dt-bindings/clock/rk3568-cru.h index 176e12451208..d7d2be75edbf 100644 --- a/include/dt-bindings/clock/rk3568-cru.h +++ b/include/dt-bindings/clock/rk3568-cru.h @@ -460,8 +460,9 @@ #define SCLK_SDMMC2_SAMPLE 399 #define SCLK_EMMC_DRV 400 #define SCLK_EMMC_SAMPLE 401 +#define PCLK_EDPPHY_GRF 402 -#define CLK_NR_CLKS (SCLK_EMMC_SAMPLE + 1) +#define CLK_NR_CLKS (PCLK_EDPPHY_GRF + 1) /* pmu soft-reset indices */ /* pmucru_softrst_con0 */