mirror of
https://github.com/hardkernel/linux.git
synced 2026-06-09 20:32:04 +09:00
rk30: add RGA driver
This commit is contained in:
黄涛
@@ -723,6 +723,28 @@ static struct platform_device device_lcdc = {
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};
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#endif
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#ifdef CONFIG_RGA_RK30
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static struct resource resource_rga[] = {
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[0] = {
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.start = RK30_RGA_PHYS,
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.end = RK30_RGA_PHYS + RK30_RGA_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_RGA,
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.end = IRQ_RGA,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device device_rga = {
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.name = "rga",
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.id = -1,
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.num_resources = ARRAY_SIZE(resource_rga),
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.resource = resource_rga,
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};
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#endif
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#ifdef CONFIG_KEYS_RK29
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extern struct rk29_keys_platform_data rk29_keys_pdata;
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static struct platform_device device_keys = {
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@@ -746,6 +768,9 @@ static int __init rk30_init_devices(void)
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#ifdef CONFIG_KEYS_RK29
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platform_device_register(&device_keys);
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#endif
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#ifdef CONFIG_RGA_RK30
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platform_device_register(&device_rga);
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#endif
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#ifdef CONFIG_LCDC_RK30
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platform_device_register(&device_lcdc);
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#endif
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@@ -126,7 +126,7 @@ obj-$(CONFIG_FB_PNX4008_DUM_RGB) += pnx4008/
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obj-$(CONFIG_FB_IBM_GXT4500) += gxt4500.o
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obj-$(CONFIG_FB_PS3) += ps3fb.o
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obj-$(CONFIG_FB_RK29) += rk29_fb.o
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obj-$(CONFIG_FB_ROCKCHIP) += rockchip/
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obj-y += rockchip/
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obj-$(CONFIG_FB_SM501) += sm501fb.o
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obj-$(CONFIG_FB_UDL) += udlfb.o
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obj-$(CONFIG_FB_XILINX) += xilinxfb.o
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@@ -5,9 +5,12 @@ config FB_ROCKCHIP
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select FB_CFB_COPYAREA
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select FB_CFB_IMAGEBLIT
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---help---
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Framebuffer driver for rochip based Platform
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Framebuffer driver for rockchip based platform
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config LCDC_RK30
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tristate "Frame buffer driver support for rk30 lcdc "
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depends on FB_ROCKCHIP
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help
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Frame buffer driver for rk30 lcdc based boards.
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source "drivers/video/rockchip/rga/Kconfig"
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@@ -1,2 +1,3 @@
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obj-$(CONFIG_FB_ROCKCHIP) += rk_fb.o
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obj-$(CONFIG_LCDC_RK30) += chips/rk30_lcdc.o
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obj-$(CONFIG_RGA_RK30) += rga/
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9
drivers/video/rockchip/rga/Kconfig
Normal file
9
drivers/video/rockchip/rga/Kconfig
Normal file
@@ -0,0 +1,9 @@
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menu "RGA"
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depends on ARCH_RK30
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config RGA_RK30
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tristate "ROCKCHIP RK30 RGA"
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help
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rk30 rga module.
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endmenu
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3
drivers/video/rockchip/rga/Makefile
Normal file
3
drivers/video/rockchip/rga/Makefile
Normal file
@@ -0,0 +1,3 @@
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rga-y := rga_drv.o rga_mmu_info.o rga_reg_info.o RGA_API.o
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obj-$(CONFIG_RGA_RK30) += rga.o
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330
drivers/video/rockchip/rga/RGA_API.c
Normal file
330
drivers/video/rockchip/rga/RGA_API.c
Normal file
@@ -0,0 +1,330 @@
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#include <linux/memory.h>
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#include "RGA_API.h"
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#include "rga.h"
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//#include "rga_angle.h"
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#define IS_YUV_420(format) \
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((format == RK_FORMAT_YCbCr_420_P) | (format == RK_FORMAT_YCbCr_420_SP) | \
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(format == RK_FORMAT_YCrCb_420_P) | (format == RK_FORMAT_YCrCb_420_SP))
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#define IS_YUV_422(format) \
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((format == RK_FORMAT_YCbCr_422_P) | (format == RK_FORMAT_YCbCr_422_SP) | \
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(format == RK_FORMAT_YCrCb_422_P) | (format == RK_FORMAT_YCrCb_422_SP))
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#define IS_YUV(format) \
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((format == RK_FORMAT_YCbCr_420_P) | (format == RK_FORMAT_YCbCr_420_SP) | \
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(format == RK_FORMAT_YCrCb_420_P) | (format == RK_FORMAT_YCrCb_420_SP) | \
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(format == RK_FORMAT_YCbCr_422_P) | (format == RK_FORMAT_YCbCr_422_SP) | \
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(format == RK_FORMAT_YCrCb_422_P) | (format == RK_FORMAT_YCrCb_422_SP))
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extern rga_service_info rga_service;
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void
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matrix_cal(const struct rga_req *msg, TILE_INFO *tile)
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{
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uint32_t x_time, y_time;
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uint64_t sina, cosa;
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int s_act_w, s_act_h, d_act_w, d_act_h;
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s_act_w = msg->src.act_w;
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s_act_h = msg->src.act_h;
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d_act_w = msg->dst.act_w;
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d_act_h = msg->dst.act_h;
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if (s_act_w == 1) s_act_w += 1;
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if (s_act_h == 1) s_act_h += 1;
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if (d_act_h == 1) d_act_h += 1;
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if (d_act_w == 1) d_act_w += 1;
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x_time = ((s_act_w - 1)<<16) / (d_act_w - 1);
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y_time = ((s_act_h - 1)<<16) / (d_act_h - 1);
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sina = msg->sina;
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cosa = msg->cosa;
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switch(msg->rotate_mode)
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{
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/* 16.16 x 16.16 */
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/* matrix[] is 64 bit wide */
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case 1 :
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tile->matrix[0] = cosa*x_time;
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tile->matrix[1] = -sina*y_time;
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tile->matrix[2] = sina*x_time;
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tile->matrix[3] = cosa*y_time;
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break;
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case 2 :
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tile->matrix[0] = -(x_time<<16);
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tile->matrix[1] = 0;
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tile->matrix[2] = 0;
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tile->matrix[3] = (y_time<<16);
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break;
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case 3 :
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tile->matrix[0] = (x_time<<16);
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tile->matrix[1] = 0;
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tile->matrix[2] = 0;
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tile->matrix[3] = -(y_time<<16);
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break;
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default :
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tile->matrix[0] = (uint64_t)1<<32;
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tile->matrix[1] = 0;
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tile->matrix[2] = 0;
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tile->matrix[3] = (uint64_t)1<<32;
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break;
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}
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}
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u32
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RGA_dst_act_addr_temp(const struct rga_req *msg)
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{
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u32 pw;
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u32 x_off, y_off;
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u32 stride;
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u32 p;
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pw = RGA_pixel_width_init(msg->dst.format);
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stride = (msg->dst.vir_w * pw + 3) & (~3);
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x_off = msg->dst.x_offset;
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y_off = msg->dst.y_offset;
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p = (u32)((stride * y_off) + (x_off * pw));
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return p;
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}
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void
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RGA_set_cmd_info(u8 cmd_mode, u32 cmd_addr)
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{
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u32 reg = 0;
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//reg = rRGA_SYS_CTRL;
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reg |= ((cmd_mode & 1) << 1);
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rRGA_SYS_CTRL = reg;
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rRGA_CMD_ADDR = cmd_addr;
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}
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void
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RGA_start(void)
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{
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u32 reg = 0;
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u8 cmd_mode;
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reg = rRGA_SYS_CTRL;
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cmd_mode = (reg >> 2) & 1;
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if (cmd_mode == 0)
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{
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/* passive */
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reg |= (1<<1);
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rRGA_SYS_CTRL = reg;
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}
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else
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{
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/* master */
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reg = rRGA_CMD_CTRL;
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reg |= 1;
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rRGA_CMD_CTRL = reg;
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}
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}
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void
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RGA_soft_reset(void)
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{
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u32 reg = 0;
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reg = rRGA_SYS_CTRL;
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reg |= 1;
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rRGA_SYS_CTRL = reg;
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}
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#if 0
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/*****************************************/
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//hxx add,2011.6.24
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void rga_one_op_st_master(RGA_INFO *p_rga_info)
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{
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rRGA_SYS_CTRL = 0x4;
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rRGA_INT = s_RGA_INT_ALL_CMD_DONE_INT_EN(p_rga_info->int_info.all_cmd_done_int_en)|
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s_RGA_INT_MMU_INT_EN(p_rga_info->int_info.mmu_int_en)|
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s_RGA_INT_ERROR_INT_EN(p_rga_info->int_info.error_int_en);
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rRGA_CMD_ADDR = (u32) p_rga_info->sys_info.p_cmd_mst;
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rRGA_CMD_CTRL = 0x3;
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}
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void rga_set_int_info(MSG *p_msg,RGA_INFO *p_rga_info)
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{
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p_msg->CMD_fin_int_enable = p_rga_info->int_info.cur_cmd_done_int_en;
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}
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void rga_check_int_all_cmd_finish(RGA_INFO *p_rga_info)
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{
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u8 int_flag;
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int_flag = 0;
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while(!int_flag)
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{
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int_flag = rRGA_INT & m_RGA_INT_ALL_CMD_DONE_INT_FLAG;
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}
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rRGA_INT = rRGA_INT | s_RGA_INT_ALL_CMD_DONE_INT_CLEAR(0x1);
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//if(p_rga_info->sys_info.p_cmd_mst != NULL)
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// free(p_rga_info->sys_info.p_cmd_mst);
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}
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#endif
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void rga_start_cmd_AXI(u8 *base, u32 num)
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{
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rRGA_SYS_CTRL = 0x4;
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rRGA_INT = s_RGA_INT_ALL_CMD_DONE_INT_EN(ENABLE)| s_RGA_INT_MMU_INT_EN(ENABLE)| s_RGA_INT_ERROR_INT_EN(ENABLE);
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rRGA_CMD_ADDR = (u32)base;
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rRGA_CMD_CTRL |= (num<<3);
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rRGA_CMD_CTRL |= 0x3;
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}
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void rga_check_cmd_finish(void)
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{
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u8 int_flag;
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u8 error_flag;
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int_flag = 0;
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error_flag = 0;
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while(!int_flag)
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{
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int_flag = rRGA_INT & m_RGA_INT_ALL_CMD_DONE_INT_FLAG;
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error_flag = rRGA_INT & (m_RGA_INT_ERROR_INT_FLAG);
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if(error_flag)
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{
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printk("~~~~~ ERROR INTTUR OCCUR ~~~~~\n");
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}
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error_flag = rRGA_INT & m_RGA_INT_MMU_INT_FLAG;
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if(error_flag)
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{
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printk("~~~~~ MMU ERROR INTTUR OCCUR ~~~~~\n");
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}
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}
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rRGA_INT = rRGA_INT | s_RGA_INT_ALL_CMD_DONE_INT_CLEAR(0x1);
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}
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void rga_start_cmd_AHB(u8 *base)
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{
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u32 *base_p32;
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base_p32 = (u32 *)base;
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*base_p32 = (*base_p32 | (1<<29));
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memcpy((u8 *)(RGA_BASE + 0x100), base, 28*4);
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rRGA_SYS_CTRL = 0x2;
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}
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void rga_check_cmd_AHB_finish(void)
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{
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u8 int_flag;
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int_flag = 0;
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while(!int_flag)
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{
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int_flag = rRGA_INT & m_RGA_INT_NOW_CMD_DONE_INT_FLAG;
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}
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rRGA_INT = rRGA_INT | s_RGA_INT_NOW_CMD_DONE_INT_CLEAR(0x1);
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}
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uint32_t RGA_gen_two_pro(struct rga_req *msg, struct rga_req *msg1)
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{
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struct rga_req *mp;
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u32 w_ratio, h_ratio;
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u32 stride;
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u32 daw, dah;
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u32 pl;
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daw = dah = 0;
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mp = msg1;
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w_ratio = (msg->src.act_w << 16) / msg->dst.act_w;
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h_ratio = (msg->src.act_h << 16) / msg->dst.act_h;
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memcpy(&mp->src, &msg->src, sizeof(rga_img_info_t));
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mp->dst.format = msg->src.format;
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/*pre_scale_w cal*/
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if ((w_ratio >= (2<<16)) && (w_ratio < (4<<16))) {
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daw = (msg->src.act_w + 1) >> 1;
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if((IS_YUV_420(mp->dst.format)) && (daw & 1)) {
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mp->src.act_w = (daw - 1) << 1;
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}
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}
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else if ((w_ratio >= (4<<16)) && (w_ratio < (8<<16))) {
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daw = (msg->src.act_w + 3) >> 2;
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if((IS_YUV_420(mp->dst.format)) && (daw & 1)) {
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mp->src.act_w = (daw - 1) << 2;
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}
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}
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else if ((w_ratio >= (8<<16)) && (w_ratio < (16<<16))) {
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daw = (msg->src.act_w + 7) >> 3;
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if((IS_YUV_420(mp->dst.format)) && (daw & 1)) {
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mp->src.act_w = (daw - 1) << 3;
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}
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}
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pl = (RGA_pixel_width_init(msg->src.format));
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stride = (pl * daw + 3) & (~3);
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mp->dst.act_w = daw;
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mp->dst.vir_w = stride / pl;
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/*pre_scale_h cal*/
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if ((h_ratio >= (2<<16)) && (h_ratio < (4<<16))) {
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dah = (msg->src.act_h + 1) >> 1;
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if((IS_YUV(mp->dst.format)) && (dah & 1)) {
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mp->src.act_h = (dah - 1) << 1;
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}
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}
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else if ((h_ratio >= (4<<16)) && (h_ratio < (8<<16))) {
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dah = (msg->src.act_h + 3) >> 2;
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if((IS_YUV(mp->dst.format)) && (dah & 1)) {
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mp->src.act_h = (dah - 1) << 2;
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}
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}
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else if ((h_ratio >= (8<<16)) && (h_ratio < (16<<16))) {
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dah = (msg->src.act_h + 7) >> 3;
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if((IS_YUV(mp->dst.format)) && (dah & 1)) {
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mp->src.act_h = (dah - 1) << 3;
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}
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}
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mp->dst.act_h = dah;
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mp->dst.vir_h = dah;
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mp->dst.yrgb_addr = (u32)rga_service.pre_scale_buf;
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mp->dst.uv_addr = mp->dst.yrgb_addr + stride * dah;
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mp->dst.v_addr = mp->dst.uv_addr + ((stride * dah) >> 1);
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mp->render_mode = pre_scaling_mode;
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memcpy(&msg->src, &mp->dst, sizeof(rga_img_info_t));
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return 0;
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}
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227
drivers/video/rockchip/rga/RGA_API.h
Normal file
227
drivers/video/rockchip/rga/RGA_API.h
Normal file
@@ -0,0 +1,227 @@
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#ifndef __RGA_API_H__
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#define __RGA_API_H__
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#include "rga_reg_info.h"
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#include "rga.h"
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#define ENABLE 1
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#define DISABLE 0
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#if 0
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int
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RGA_set_src_act_info(
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msg_t *msg,
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unsigned int width, /* act width */
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unsigned int height, /* act height */
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unsigned int x_off, /* x_off */
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unsigned int y_off /* y_off */
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);
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int
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RGA_set_src_vir_info(
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msg_t *msg,
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unsigned int yrgb_addr, /* yrgb_addr */
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unsigned int uv_addr, /* uv_addr */
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unsigned int v_addr, /* v_addr */
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unsigned int vir_w, /* vir width */
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unsigned int vir_h, /* vir height */
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unsigned char format, /* format */
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unsigned char a_swap_en
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);
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int
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RGA_set_dst_act_info(
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msg_t *msg,
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unsigned int width, /* act width */
|
||||
unsigned int height, /* act height */
|
||||
unsigned int x_off, /* x_off */
|
||||
unsigned int y_off /* y_off */
|
||||
);
|
||||
|
||||
int
|
||||
RGA_set_dst_vir_info(
|
||||
msg_t *msg,
|
||||
unsigned int yrgb_addr, /* yrgb_addr */
|
||||
unsigned int uv_addr, /* uv_addr */
|
||||
unsigned int v_addr, /* v_addr */
|
||||
unsigned int vir_w, /* vir width */
|
||||
unsigned int vir_h, /* vir height */
|
||||
RECT clip, /* clip window*/
|
||||
unsigned char format, /* format */
|
||||
unsigned char a_swap_en );
|
||||
|
||||
|
||||
|
||||
int
|
||||
RGA_set_rop_mask_info(
|
||||
msg_t *msg,
|
||||
u32 rop_mask_addr,
|
||||
u32 rop_mask_endian_mode);
|
||||
|
||||
int
|
||||
RGA_set_pat_info(
|
||||
msg_t *msg,
|
||||
u32 width,
|
||||
u32 height,
|
||||
u32 x_off,
|
||||
u32 y_off,
|
||||
u32 pat_format);
|
||||
|
||||
int
|
||||
RGA_set_alpha_en_info(
|
||||
msg_t *msg,
|
||||
unsigned int alpha_cal_mode,
|
||||
unsigned int alpha_mode,
|
||||
unsigned int global_a_value,
|
||||
unsigned int PD_en,
|
||||
unsigned int PD_mode
|
||||
);
|
||||
|
||||
int
|
||||
RGA_set_rop_en_info(
|
||||
msg_t *msg,
|
||||
unsigned int ROP_mode,
|
||||
unsigned int ROP_code,
|
||||
unsigned int color_mode,
|
||||
unsigned int solid_color);
|
||||
|
||||
/*
|
||||
int
|
||||
RGA_set_MMU_info(
|
||||
MSG *msg,
|
||||
unsigned int base_addr,
|
||||
unsigned int src_flush,
|
||||
unsigned int dst_flush,
|
||||
unsigned int cmd_flush,
|
||||
unsigned int page_size
|
||||
);
|
||||
*/
|
||||
|
||||
int
|
||||
RGA_set_MMU_info(
|
||||
msg_t *msg,
|
||||
u8 mmu_en,
|
||||
u8 src_flush,
|
||||
u8 dst_flush,
|
||||
u8 cmd_flush,
|
||||
u32 base_addr,
|
||||
u8 page_size);
|
||||
|
||||
|
||||
int
|
||||
RGA_set_bitblt_mode(
|
||||
msg_t *msg,
|
||||
unsigned char scale_mode, // 0/near 1/bilnear 2/bicubic
|
||||
unsigned char rotate_mode, // 0/copy 1/rotate_scale 2/x_mirror 3/y_mirror
|
||||
unsigned int angle, // rotate angle (0~359)
|
||||
unsigned int dither_en, // dither en flag
|
||||
unsigned int AA_en, // AA flag
|
||||
unsigned int yuv2rgb_mode
|
||||
);
|
||||
|
||||
|
||||
int
|
||||
RGA_set_color_palette_mode(
|
||||
msg_t *msg,
|
||||
u8 palette_mode, /* 1bpp/2bpp/4bpp/8bpp */
|
||||
u8 endian_mode, /* src endian mode sel */
|
||||
u32 bpp1_0_color, /* BPP1 = 0 */
|
||||
u32 bpp1_1_color /* BPP1 = 1 */
|
||||
);
|
||||
|
||||
|
||||
|
||||
int
|
||||
RGA_set_color_fill_mode(
|
||||
msg_t *msg,
|
||||
CF_GR_COLOR gr_color, /* gradient color part*/
|
||||
u8 gr_satur_mode, /* saturation mode */
|
||||
u8 cf_mode, /* patten fill or solid fill */
|
||||
u32 color, /* solid color */
|
||||
u16 pat_width, /* pat_width */
|
||||
u16 pat_height, /* pat_height */
|
||||
u8 pat_x_off, /* patten x offset */
|
||||
u8 pat_y_off, /* patten y offset */
|
||||
u8 aa_en /* alpha en */
|
||||
);
|
||||
|
||||
|
||||
int
|
||||
RGA_set_line_point_drawing_mode(
|
||||
msg_t *msg,
|
||||
POINT sp, /* start point */
|
||||
POINT ep, /* end point */
|
||||
unsigned int color, /* line point drawing color */
|
||||
unsigned int line_width, /* line width */
|
||||
unsigned char AA_en, /* AA en */
|
||||
unsigned char last_point_en /* last point en */
|
||||
);
|
||||
|
||||
|
||||
|
||||
int
|
||||
RGA_set_blur_sharp_filter_mode(
|
||||
msg_t *msg,
|
||||
unsigned char filter_mode, /* blur/sharpness */
|
||||
unsigned char filter_type, /* filter intensity */
|
||||
unsigned char dither_en /* dither_en flag */
|
||||
);
|
||||
|
||||
int
|
||||
RGA_set_pre_scaling_mode(
|
||||
msg_t *msg,
|
||||
unsigned char dither_en
|
||||
);
|
||||
|
||||
|
||||
int
|
||||
RGA_update_palette_table_mode(
|
||||
msg_t *msg,
|
||||
unsigned int LUT_addr, /* LUT table addr */
|
||||
unsigned int palette_mode /* 1bpp/2bpp/4bpp/8bpp */
|
||||
);
|
||||
|
||||
|
||||
int
|
||||
RGA_set_update_patten_buff_mode(
|
||||
msg_t *msg,
|
||||
unsigned int pat_addr, /* patten addr */
|
||||
unsigned int w, /* patten width */
|
||||
unsigned int h, /* patten height */
|
||||
unsigned int format /* patten format */
|
||||
);
|
||||
/*
|
||||
int
|
||||
RGA_set_MMU_info(
|
||||
MSG *msg,
|
||||
unsigned int base_addr,
|
||||
unsigned int src_flush,
|
||||
unsigned int dst_flush,
|
||||
unsigned int cmd_flush,
|
||||
unsigned int page_size
|
||||
);
|
||||
*/
|
||||
|
||||
int
|
||||
RGA_set_mmu_info(
|
||||
msg_t *msg,
|
||||
u8 mmu_en,
|
||||
u8 src_flush,
|
||||
u8 dst_flush,
|
||||
u8 cmd_flush,
|
||||
u32 base_addr,
|
||||
u8 page_size);
|
||||
|
||||
msg_t * RGA_init_msg(void);
|
||||
int RGA_free_msg(msg_t *msg);
|
||||
void matrix_cal(msg_t *msg, TILE_INFO *tile);
|
||||
unsigned char * RGA_set_reg_info(msg_t *msg, u8 *base);
|
||||
void RGA_set_cmd_info(u8 cmd_mode, u32 cmd_addr);
|
||||
void RGA_start(void);
|
||||
void RGA_soft_reset(void);
|
||||
#endif
|
||||
|
||||
uint32_t RGA_gen_two_pro(struct rga_req *msg, struct rga_req *msg1);
|
||||
|
||||
|
||||
#endif
|
||||
483
drivers/video/rockchip/rga/rga.h
Normal file
483
drivers/video/rockchip/rga/rga.h
Normal file
@@ -0,0 +1,483 @@
|
||||
#ifndef _RGA_DRIVER_H_
|
||||
#define _RGA_DRIVER_H_
|
||||
|
||||
#include "rga_type.h"
|
||||
#include <linux/types.h>
|
||||
#include <linux/miscdevice.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
|
||||
#define RGA_BLIT_SYNC 0x5017
|
||||
#define RGA_BLIT_ASYNC 0x5018
|
||||
#define RGA_FLUSH 0x5019
|
||||
|
||||
|
||||
#define RGA_REG_CTRL_LEN 0x8 /* 8 */
|
||||
#define RGA_REG_CMD_LEN 0x1c /* 28 */
|
||||
#define RGA_CMD_BUF_SIZE 0x700 /* 16*28*4 */
|
||||
|
||||
|
||||
/* RGA process mode enum */
|
||||
enum
|
||||
{
|
||||
bitblt_mode = 0x0,
|
||||
color_palette_mode = 0x1,
|
||||
color_fill_mode = 0x2,
|
||||
line_point_drawing_mode = 0x3,
|
||||
blur_sharp_filter_mode = 0x4,
|
||||
pre_scaling_mode = 0x5,
|
||||
update_palette_table_mode = 0x6,
|
||||
update_patten_buff_mode = 0x7,
|
||||
};
|
||||
|
||||
|
||||
enum
|
||||
{
|
||||
rop_enable_mask = 0x2,
|
||||
dither_enable_mask = 0x8,
|
||||
fading_enable_mask = 0x10,
|
||||
PD_enbale_mask = 0x20,
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
yuv2rgb_mode0 = 0x0, /* BT.601 MPEG */
|
||||
yuv2rgb_mode1 = 0x1, /* BT.601 JPEG */
|
||||
yuv2rgb_mode2 = 0x2, /* BT.709 */
|
||||
};
|
||||
|
||||
|
||||
/* RGA rotate mode */
|
||||
enum
|
||||
{
|
||||
rotate_mode0 = 0x0, /* no rotate */
|
||||
rotate_mode1 = 0x1, /* rotate */
|
||||
rotate_mode2 = 0x2, /* x_mirror */
|
||||
rotate_mode3 = 0x3, /* y_mirror */
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
color_palette_mode0 = 0x0, /* 1K */
|
||||
color_palette_mode1 = 0x1, /* 2K */
|
||||
color_palette_mode2 = 0x2, /* 4K */
|
||||
color_palette_mode3 = 0x3, /* 8K */
|
||||
};
|
||||
|
||||
|
||||
|
||||
/*
|
||||
// Alpha Red Green Blue
|
||||
{ 4, 32, {{32,24, 8, 0, 16, 8, 24,16 }}, GGL_RGBA }, // RK_FORMAT_RGBA_8888
|
||||
{ 4, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGBX_8888
|
||||
{ 3, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGB_888
|
||||
{ 4, 32, {{32,24, 24,16, 16, 8, 8, 0 }}, GGL_BGRA }, // RK_FORMAT_BGRA_8888
|
||||
{ 2, 16, {{ 0, 0, 16,11, 11, 5, 5, 0 }}, GGL_RGB }, // RK_FORMAT_RGB_565
|
||||
{ 2, 16, {{ 1, 0, 16,11, 11, 6, 6, 1 }}, GGL_RGBA }, // RK_FORMAT_RGBA_5551
|
||||
{ 2, 16, {{ 4, 0, 16,12, 12, 8, 8, 4 }}, GGL_RGBA }, // RK_FORMAT_RGBA_4444
|
||||
{ 3, 24, {{ 0, 0, 24,16, 16, 8, 8, 0 }}, GGL_BGR }, // RK_FORMAT_BGB_888
|
||||
|
||||
*/
|
||||
enum
|
||||
{
|
||||
RK_FORMAT_RGBA_8888 = 0x0,
|
||||
RK_FORMAT_RGBX_8888 = 0x1,
|
||||
RK_FORMAT_RGB_888 = 0x2,
|
||||
RK_FORMAT_BGRA_8888 = 0x3,
|
||||
RK_FORMAT_RGB_565 = 0x4,
|
||||
RK_FORMAT_RGBA_5551 = 0x5,
|
||||
RK_FORMAT_RGBA_4444 = 0x6,
|
||||
RK_FORMAT_BGR_888 = 0x7,
|
||||
|
||||
RK_FORMAT_YCbCr_422_SP = 0x8,
|
||||
RK_FORMAT_YCbCr_422_P = 0x9,
|
||||
RK_FORMAT_YCbCr_420_SP = 0xa,
|
||||
RK_FORMAT_YCbCr_420_P = 0xb,
|
||||
|
||||
RK_FORMAT_YCrCb_422_SP = 0xc,
|
||||
RK_FORMAT_YCrCb_422_P = 0xd,
|
||||
RK_FORMAT_YCrCb_420_SP = 0xe,
|
||||
RK_FORMAT_YCrCb_420_P = 0xf,
|
||||
|
||||
RK_FORMAT_BPP1 = 0x10,
|
||||
RK_FORMAT_BPP2 = 0x11,
|
||||
RK_FORMAT_BPP4 = 0x12,
|
||||
RK_FORMAT_BPP8 = 0x13,
|
||||
};
|
||||
|
||||
|
||||
typedef struct rga_img_info_t
|
||||
{
|
||||
uint32 yrgb_addr; /* yrgb mem addr */
|
||||
uint32 uv_addr; /* cb/cr mem addr */
|
||||
uint32 v_addr; /* cr mem addr */
|
||||
uint32 format; //definition by RK_FORMAT
|
||||
|
||||
UWORD16 act_w;
|
||||
UWORD16 act_h;
|
||||
UWORD16 x_offset;
|
||||
UWORD16 y_offset;
|
||||
|
||||
UWORD16 vir_w;
|
||||
UWORD16 vir_h;
|
||||
|
||||
UWORD16 endian_mode; //for BPP
|
||||
UWORD16 alpha_swap;
|
||||
}
|
||||
rga_img_info_t;
|
||||
|
||||
|
||||
typedef struct mdp_img_act
|
||||
{
|
||||
UWORD16 w; // width
|
||||
UWORD16 h; // height
|
||||
WORD16 x_off; // x offset for the vir
|
||||
WORD16 y_off; // y offset for the vir
|
||||
}
|
||||
mdp_img_act;
|
||||
|
||||
|
||||
|
||||
typedef struct RANGE
|
||||
{
|
||||
UWORD16 min;
|
||||
UWORD16 max;
|
||||
}
|
||||
RANGE;
|
||||
|
||||
typedef struct POINT
|
||||
{
|
||||
UWORD16 x;
|
||||
UWORD16 y;
|
||||
}
|
||||
POINT;
|
||||
|
||||
typedef struct RECT
|
||||
{
|
||||
WORD16 xmin;
|
||||
WORD16 xmax; // width - 1
|
||||
WORD16 ymin;
|
||||
WORD16 ymax; // height - 1
|
||||
} RECT;
|
||||
|
||||
typedef struct RGB
|
||||
{
|
||||
unsigned char r;
|
||||
unsigned char g;
|
||||
unsigned char b;
|
||||
unsigned char res;
|
||||
}RGB;
|
||||
|
||||
|
||||
typedef struct MMU
|
||||
{
|
||||
unsigned char mmu_en;
|
||||
uint32 base_addr;
|
||||
uint32 mmu_flag; /* [0] mmu enable [1] src_flush [2] dst_flush [3] CMD_flush [4~5] page size*/
|
||||
} MMU;
|
||||
|
||||
|
||||
|
||||
|
||||
typedef struct COLOR_FILL
|
||||
{
|
||||
short gr_x_a;
|
||||
short gr_y_a;
|
||||
short gr_x_b;
|
||||
short gr_y_b;
|
||||
short gr_x_g;
|
||||
short gr_y_g;
|
||||
short gr_x_r;
|
||||
short gr_y_r;
|
||||
|
||||
//u8 cp_gr_saturation;
|
||||
}
|
||||
COLOR_FILL;
|
||||
|
||||
typedef struct FADING
|
||||
{
|
||||
UBYTE b;
|
||||
UBYTE g;
|
||||
UBYTE r;
|
||||
UBYTE res;
|
||||
}
|
||||
FADING;
|
||||
|
||||
|
||||
typedef struct line_draw_t
|
||||
{
|
||||
POINT start_point; /* LineDraw_start_point */
|
||||
POINT end_point; /* LineDraw_end_point */
|
||||
uint32 color; /* LineDraw_color */
|
||||
uint32 flag; /* (enum) LineDrawing mode sel */
|
||||
uint32 line_width; /* range 1~16 */
|
||||
}
|
||||
line_draw_t;
|
||||
|
||||
|
||||
|
||||
struct rga_req {
|
||||
UBYTE render_mode; /* (enum) process mode sel */
|
||||
|
||||
rga_img_info_t src; /* src image info */
|
||||
rga_img_info_t dst; /* dst image info */
|
||||
rga_img_info_t pat; /* patten image info */
|
||||
|
||||
uint32 rop_mask_addr; /* rop4 mask addr */
|
||||
uint32 LUT_addr; /* LUT addr */
|
||||
|
||||
RECT clip; /* dst clip window default value is dst_vir */
|
||||
/* value from [0, w-1] / [0, h-1]*/
|
||||
|
||||
int32_t sina; /* dst angle default value 0 16.16 scan from table */
|
||||
int32_t cosa; /* dst angle default value 0 16.16 scan from table */
|
||||
|
||||
uint16_t alpha_rop_flag; /* alpha rop process flag */
|
||||
/* ([0] = 1 alpha_rop_enable) */
|
||||
/* ([1] = 1 rop enable) */
|
||||
/* ([2] = 1 fading_enable) */
|
||||
/* ([3] = 1 PD_enable) */
|
||||
/* ([4] = 1 alpha cal_mode_sel) */
|
||||
/* ([5] = 1 dither_enable) */
|
||||
/* ([6] = 1 gradient fill mode sel) */
|
||||
/* ([7] = 1 AA_enable) */
|
||||
|
||||
uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */
|
||||
|
||||
uint32 color_key_max; /* color key max */
|
||||
uint32 color_key_min; /* color key min */
|
||||
|
||||
uint32 fg_color; /* foreground color */
|
||||
uint32 bg_color; /* background color */
|
||||
|
||||
COLOR_FILL gr_color; /* color fill use gradient */
|
||||
|
||||
line_draw_t line_draw_info;
|
||||
|
||||
FADING fading;
|
||||
|
||||
uint8_t PD_mode; /* porter duff alpha mode sel */
|
||||
|
||||
uint8_t alpha_global_value; /* global alpha value */
|
||||
|
||||
uint16_t rop_code; /* rop2/3/4 code scan from rop code table*/
|
||||
|
||||
uint8_t bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type*/
|
||||
|
||||
uint8_t palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/
|
||||
|
||||
uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */
|
||||
|
||||
uint8_t endian_mode; /* 0/big endian 1/little endian*/
|
||||
|
||||
uint8_t rotate_mode; /* (enum) rotate mode */
|
||||
/* 0x0, no rotate */
|
||||
/* 0x1, rotate */
|
||||
/* 0x2, x_mirror */
|
||||
/* 0x3, y_mirror */
|
||||
|
||||
uint8_t color_fill_mode; /* 0 solid color / 1 patten color */
|
||||
|
||||
MMU mmu_info; /* mmu information */
|
||||
|
||||
uint8_t alpha_rop_mode; /* ([0~1] alpha mode) */
|
||||
/* ([2~3] rop mode) */
|
||||
/* ([4] zero mode en) */
|
||||
/* ([5] dst alpha mode) */
|
||||
|
||||
uint8_t src_trans_mode;
|
||||
|
||||
uint8_t CMD_fin_int_enable;
|
||||
|
||||
/* completion is reported through a callback */
|
||||
void (*complete)(int retval);
|
||||
};
|
||||
|
||||
|
||||
typedef struct TILE_INFO
|
||||
{
|
||||
int64_t matrix[4];
|
||||
|
||||
uint16_t tile_x_num; /* x axis tile num / tile size is 8x8 pixel */
|
||||
uint16_t tile_y_num; /* y axis tile num */
|
||||
|
||||
int16_t dst_x_tmp; /* dst pos x = (xstart - xoff) default value 0 */
|
||||
int16_t dst_y_tmp; /* dst pos y = (ystart - yoff) default value 0 */
|
||||
|
||||
uint16_t tile_w;
|
||||
uint16_t tile_h;
|
||||
int16_t tile_start_x_coor;
|
||||
int16_t tile_start_y_coor;
|
||||
int32_t tile_xoff;
|
||||
int32_t tile_yoff;
|
||||
|
||||
int32_t tile_temp_xstart;
|
||||
int32_t tile_temp_ystart;
|
||||
|
||||
/* src tile incr */
|
||||
int32_t x_dx;
|
||||
int32_t x_dy;
|
||||
int32_t y_dx;
|
||||
int32_t y_dy;
|
||||
|
||||
mdp_img_act dst_ctrl;
|
||||
|
||||
}
|
||||
TILE_INFO;
|
||||
|
||||
|
||||
/**
|
||||
* struct for process session which connect to rga
|
||||
*
|
||||
* @author ZhangShengqin (2012-2-15)
|
||||
*/
|
||||
typedef struct rga_session {
|
||||
/* a linked list of data so we can access them for debugging */
|
||||
struct list_head list_session;
|
||||
/* a linked list of register data waiting for process */
|
||||
struct list_head waiting;
|
||||
/* a linked list of register data in processing */
|
||||
struct list_head running;
|
||||
/* all coommand this thread done */
|
||||
uint32_t done;
|
||||
wait_queue_head_t wait;
|
||||
pid_t pid;
|
||||
atomic_t task_running;
|
||||
} rga_session;
|
||||
|
||||
struct rga_reg {
|
||||
rga_session *session;
|
||||
struct list_head session_link; /* link to rga service session */
|
||||
struct list_head status_link; /* link to register set list */
|
||||
uint32_t sys_reg[RGA_REG_CTRL_LEN];
|
||||
uint32_t cmd_reg[RGA_REG_CMD_LEN];
|
||||
uint32_t *MMU_base;
|
||||
atomic_t int_enable;
|
||||
};
|
||||
|
||||
|
||||
|
||||
typedef struct rga_service_info {
|
||||
spinlock_t lock;
|
||||
struct timer_list timer; /* timer for power off */
|
||||
struct list_head waiting; /* link to link_reg in struct vpu_reg */
|
||||
struct list_head running; /* link to link_reg in struct vpu_reg */
|
||||
struct list_head done; /* link to link_reg in struct vpu_reg */
|
||||
struct list_head session; /* link to list_session in struct vpu_session */
|
||||
atomic_t total_running;
|
||||
bool enabled;
|
||||
struct rga_reg *reg;
|
||||
uint32_t cmd_buff[28*16];/* cmd_buff for rga */
|
||||
uint32_t *pre_scale_buf;
|
||||
atomic_t int_disable; /* 0 int enable 1 int disable */
|
||||
} rga_service_info;
|
||||
|
||||
|
||||
|
||||
|
||||
struct rga_drvdata {
|
||||
struct miscdevice miscdev;
|
||||
struct device dev;
|
||||
void *rga_base;
|
||||
int irq0;
|
||||
|
||||
struct clk *pd_display;
|
||||
struct clk *aclk_lcdc;
|
||||
struct clk *hclk_lcdc;
|
||||
struct clk *aclk_ddr_lcdc;
|
||||
struct clk *hclk_cpu_display;
|
||||
struct clk *aclk_disp_matrix;
|
||||
struct clk *hclk_disp_matrix;
|
||||
struct clk *axi_clk;
|
||||
struct clk *ahb_clk;
|
||||
|
||||
struct mutex mutex; // mutex
|
||||
|
||||
struct delayed_work power_off_work;
|
||||
bool enable; //clk enable or disable
|
||||
void (*rga_irq_callback)(int rga_retval); //callback function used by aync call
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define RGA_BASE 0x10114000
|
||||
|
||||
//General Registers
|
||||
#define RGA_SYS_CTRL 0x000
|
||||
#define RGA_CMD_CTRL 0x004
|
||||
#define RGA_CMD_ADDR 0x008
|
||||
#define RGA_STATUS 0x00c
|
||||
#define RGA_INT 0x010
|
||||
#define RGA_AXI_ID 0x014
|
||||
#define RGA_MMU_STA_CTRL 0x018
|
||||
#define RGA_MMU_STA 0x01c
|
||||
|
||||
//Command code start
|
||||
#define RGA_MODE_CTRL 0x100
|
||||
|
||||
//Source Image Registers
|
||||
#define RGA_SRC_Y_MST 0x104
|
||||
#define RGA_SRC_CB_MST 0x108
|
||||
#define RGA_MASK_READ_MST 0x108 //repeat
|
||||
#define RGA_SRC_CR_MST 0x10c
|
||||
#define RGA_SRC_VIR_INFO 0x110
|
||||
#define RGA_SRC_ACT_INFO 0x114
|
||||
#define RGA_SRC_X_PARA 0x118
|
||||
#define RGA_SRC_Y_PARA 0x11c
|
||||
#define RGA_SRC_TILE_XINFO 0x120
|
||||
#define RGA_SRC_TILE_YINFO 0x124
|
||||
#define RGA_SRC_TILE_H_INCR 0x128
|
||||
#define RGA_SRC_TILE_V_INCR 0x12c
|
||||
#define RGA_SRC_TILE_OFFSETX 0x130
|
||||
#define RGA_SRC_TILE_OFFSETY 0x134
|
||||
#define RGA_SRC_BG_COLOR 0x138
|
||||
#define RGA_SRC_FG_COLOR 0x13c
|
||||
#define RGA_LINE_DRAWING_COLOR 0x13c //repeat
|
||||
#define RGA_SRC_TR_COLOR0 0x140
|
||||
#define RGA_CP_GR_A 0x140 //repeat
|
||||
#define RGA_SRC_TR_COLOR1 0x144
|
||||
#define RGA_CP_GR_B 0x144 //repeat
|
||||
|
||||
#define RGA_LINE_DRAW 0x148
|
||||
#define RGA_PAT_START_POINT 0x148 //repeat
|
||||
|
||||
//Destination Image Registers
|
||||
#define RGA_DST_MST 0x14c
|
||||
#define RGA_LUT_MST 0x14c //repeat
|
||||
#define RGA_PAT_MST 0x14c //repeat
|
||||
#define RGA_LINE_DRAWING_MST 0x14c //repeat
|
||||
|
||||
#define RGA_DST_VIR_INFO 0x150
|
||||
|
||||
#define RGA_DST_CTR_INFO 0x154
|
||||
#define RGA_LINE_DRAW_XY_INFO 0x154 //repeat
|
||||
|
||||
//Alpha/ROP Registers
|
||||
#define RGA_ALPHA_CON 0x158
|
||||
|
||||
#define RGA_PAT_CON 0x15c
|
||||
#define RGA_DST_VIR_WIDTH_PIX 0x15c //repeat
|
||||
|
||||
#define RGA_ROP_CON0 0x160
|
||||
#define RGA_CP_GR_G 0x160 //repeat
|
||||
#define RGA_PRESCL_CB_MST 0x160 //repeat
|
||||
|
||||
#define RGA_ROP_CON1 0x164
|
||||
#define RGA_CP_GR_R 0x164 //repeat
|
||||
#define RGA_PRESCL_CR_MST 0x164 //repeat
|
||||
|
||||
//MMU Register
|
||||
#define RGA_FADING_CON 0x168
|
||||
#define RGA_MMU_CTRL 0x168 //repeat
|
||||
|
||||
#define RGA_MMU_TBL 0x16c //repeat
|
||||
|
||||
|
||||
#define RGA_BLIT_COMPLETE_EVENT 1
|
||||
|
||||
|
||||
|
||||
|
||||
#endif /*_RK29_IPP_DRIVER_H_*/
|
||||
989
drivers/video/rockchip/rga/rga_drv.c
Normal file
989
drivers/video/rockchip/rga/rga_drv.c
Normal file
@@ -0,0 +1,989 @@
|
||||
/*
|
||||
* Copyright (C) 2012 ROCKCHIP, Inc.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk.h>
|
||||
#include <asm/delay.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/delay.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <mach/io.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <linux/fs.h>
|
||||
#include <asm/uaccess.h>
|
||||
#include <linux/firmware.h>
|
||||
#include <linux/miscdevice.h>
|
||||
#include <linux/poll.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/wait.h>
|
||||
#include <linux/syscalls.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/time.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
|
||||
#include "rga.h"
|
||||
#include "rga_reg_info.h"
|
||||
#include "rga_mmu_info.h"
|
||||
#include "RGA_API.h"
|
||||
|
||||
|
||||
#define PRE_SCALE_BUF_SIZE 2048*1024*4
|
||||
|
||||
#define RGA_POWER_OFF_DELAY 4*HZ /* 4s */
|
||||
#define RGA_TIMEOUT_DELAY 2*HZ /* 2s */
|
||||
|
||||
|
||||
|
||||
|
||||
static struct rga_drvdata *drvdata = NULL;
|
||||
rga_service_info rga_service;
|
||||
|
||||
|
||||
static int rga_blit_async(rga_session *session, struct rga_req *req);
|
||||
|
||||
|
||||
#define RGA_MAJOR 232
|
||||
|
||||
#define RK30_RGA_PHYS 0x10114000
|
||||
#define RK30_RGA_SIZE SZ_8K
|
||||
#define RGA_RESET_TIMEOUT 1000
|
||||
|
||||
/* Driver information */
|
||||
#define DRIVER_DESC "RGA Device Driver"
|
||||
#define DRIVER_NAME "rga"
|
||||
|
||||
|
||||
/* Logging */
|
||||
#define RGA_DEBUG 0
|
||||
#if RGA_DEBUG
|
||||
#define DBG(format, args...) printk(KERN_DEBUG "%s: " format, DRIVER_NAME, ## args)
|
||||
#define ERR(format, args...) printk(KERN_DEBUG "%s: " format, DRIVER_NAME, ## args)
|
||||
#define WARNING(format, args...) printk(KERN_DEBUG "%s: " format, DRIVER_NAME, ## args)
|
||||
#define INFO(format, args...) printk(KERN_DEBUG "%s: " format, DRIVER_NAME, ## args)
|
||||
#else
|
||||
#define DBG(format, args...)
|
||||
#define ERR(format, args...)
|
||||
#define WARNING(format, args...)
|
||||
#define INFO(format, args...)
|
||||
#endif
|
||||
|
||||
|
||||
static inline void rga_write(u32 b, u32 r)
|
||||
{
|
||||
__raw_writel(b, drvdata->rga_base + r);
|
||||
}
|
||||
|
||||
static inline u32 rga_read(u32 r)
|
||||
{
|
||||
return __raw_readl(drvdata->rga_base + r);
|
||||
}
|
||||
|
||||
static void rga_soft_reset(void)
|
||||
{
|
||||
u32 i;
|
||||
u32 reg;
|
||||
|
||||
rga_write(1, RGA_SYS_CTRL); //RGA_SYS_CTRL
|
||||
|
||||
for(i = 0; i < RGA_RESET_TIMEOUT; i++) {
|
||||
reg = rga_read(RGA_SYS_CTRL) & 1; //RGA_SYS_CTRL
|
||||
|
||||
if(reg == 0)
|
||||
break;
|
||||
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
if(i == RGA_RESET_TIMEOUT)
|
||||
ERR("soft reset timeout.\n");
|
||||
}
|
||||
|
||||
static void rga_dump(void)
|
||||
{
|
||||
int running;
|
||||
struct rga_reg *reg, *reg_tmp;
|
||||
rga_session *session, *session_tmp;
|
||||
|
||||
running = atomic_read(&rga_service.total_running);
|
||||
printk("total_running %d\n", running);
|
||||
|
||||
list_for_each_entry_safe(session, session_tmp, &rga_service.session, list_session)
|
||||
{
|
||||
printk("session pid %d:\n", session->pid);
|
||||
running = atomic_read(&session->task_running);
|
||||
printk("task_running %d\n", running);
|
||||
list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link)
|
||||
{
|
||||
printk("waiting register set 0x%.8x\n", (unsigned int)reg);
|
||||
}
|
||||
list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link)
|
||||
{
|
||||
printk("running register set 0x%.8x\n", (unsigned int)reg);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void rga_power_on(void)
|
||||
{
|
||||
//printk("rga_power_on\n");
|
||||
cancel_delayed_work_sync(&drvdata->power_off_work);
|
||||
if (drvdata->enable)
|
||||
return;
|
||||
|
||||
clk_enable(drvdata->pd_display);
|
||||
clk_enable(drvdata->aclk_lcdc);
|
||||
clk_enable(drvdata->hclk_lcdc);
|
||||
clk_enable(drvdata->aclk_ddr_lcdc);
|
||||
clk_enable(drvdata->hclk_cpu_display);
|
||||
clk_enable(drvdata->aclk_disp_matrix);
|
||||
clk_enable(drvdata->hclk_disp_matrix);
|
||||
clk_enable(drvdata->axi_clk);
|
||||
clk_enable(drvdata->ahb_clk);
|
||||
|
||||
drvdata->enable = true;
|
||||
}
|
||||
|
||||
|
||||
static void rga_power_off(struct work_struct *work)
|
||||
{
|
||||
int total_running;
|
||||
|
||||
//printk("rga_power_off\n");
|
||||
if(!drvdata->enable)
|
||||
return;
|
||||
|
||||
total_running = atomic_read(&rga_service.total_running);
|
||||
if (total_running) {
|
||||
pr_alert("power off when %d task running!!\n", total_running);
|
||||
mdelay(50);
|
||||
pr_alert("delay 50 ms for running task\n");
|
||||
rga_dump();
|
||||
}
|
||||
|
||||
clk_disable(drvdata->pd_display);
|
||||
clk_disable(drvdata->aclk_lcdc);
|
||||
clk_disable(drvdata->hclk_lcdc);
|
||||
clk_disable(drvdata->aclk_ddr_lcdc);
|
||||
clk_disable(drvdata->hclk_cpu_display);
|
||||
clk_disable(drvdata->aclk_disp_matrix);
|
||||
clk_disable(drvdata->hclk_disp_matrix);
|
||||
clk_disable(drvdata->axi_clk);
|
||||
clk_disable(drvdata->ahb_clk);
|
||||
|
||||
drvdata->enable = false;
|
||||
}
|
||||
|
||||
|
||||
static int rga_flush(rga_session *session, unsigned long arg)
|
||||
{
|
||||
//printk("rga_get_result %d\n",drvdata->rga_result);
|
||||
|
||||
int ret;
|
||||
|
||||
ret = wait_event_interruptible_timeout(session->wait, session->done, RGA_TIMEOUT_DELAY);
|
||||
|
||||
if (unlikely(ret < 0)) {
|
||||
pr_err("pid %d wait task ret %d\n", session->pid, ret);
|
||||
} else if (0 == ret) {
|
||||
pr_err("pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
|
||||
ret = -ETIMEDOUT;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
static int rga_check_param(const struct rga_req *req)
|
||||
{
|
||||
#if 1
|
||||
/*RGA can support up to 8192*8192 resolution in RGB format,but we limit the image size to 8191*8191 here*/
|
||||
//check src width and height
|
||||
if (unlikely((req->src.act_w < 0) || (req->src.act_w > 8191) || (req->src.act_h < 0) || (req->src.act_h > 8191))) {
|
||||
ERR("invalid source resolution\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
//check dst width and height
|
||||
if (unlikely((req->dst.act_w < 0) || (req->dst.act_w > 2048) || (req->dst.act_h < 16) || (req->dst.act_h > 2048))) {
|
||||
ERR("invalid destination resolution\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
//check src_vir_w
|
||||
if(unlikely(req->src.vir_w < req->src.act_w)){
|
||||
ERR("invalid src_vir_w\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
//check dst_vir_w
|
||||
if(unlikely(req->dst.vir_w < req->dst.act_w)){
|
||||
ERR("invalid dst_vir_w\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
//check src address
|
||||
if (unlikely(req->src.yrgb_addr == 0))
|
||||
{
|
||||
ERR("could not retrieve src image from memory\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
//check src address
|
||||
if (unlikely(req->dst.yrgb_addr == 0))
|
||||
{
|
||||
ERR("could not retrieve dst image from memory\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rga_copy_reg(struct rga_reg *reg, uint32_t offset)
|
||||
{
|
||||
uint32_t i;
|
||||
uint32_t *cmd_buf;
|
||||
uint32_t *reg_p;
|
||||
|
||||
atomic_add(1, &rga_service.total_running);
|
||||
atomic_add(1, ®->session->task_running);
|
||||
|
||||
cmd_buf = (uint32_t *)rga_service.cmd_buff + offset*28;
|
||||
reg_p = (uint32_t *)reg->cmd_reg;
|
||||
|
||||
for(i=0; i<28; i++)
|
||||
{
|
||||
cmd_buf[i] = reg_p[i];
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static struct rga_reg * rga_reg_init(rga_session *session, struct rga_req *req)
|
||||
{
|
||||
unsigned long flag;
|
||||
struct rga_reg *reg = kmalloc(sizeof(struct rga_reg), GFP_KERNEL);
|
||||
if (NULL == reg) {
|
||||
pr_err("kmalloc fail in rga_reg_init\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
reg->session = session;
|
||||
INIT_LIST_HEAD(®->session_link);
|
||||
INIT_LIST_HEAD(®->status_link);
|
||||
|
||||
rga_set_mmu_info(reg, req);
|
||||
RGA_gen_reg_info(req, (uint8_t *)reg->cmd_reg);
|
||||
|
||||
spin_lock_irqsave(&rga_service.lock, flag);
|
||||
list_add_tail(®->status_link, &rga_service.waiting);
|
||||
list_add_tail(®->session_link, &session->waiting);
|
||||
spin_unlock_irqrestore(&rga_service.lock, flag);
|
||||
|
||||
return reg;
|
||||
}
|
||||
|
||||
static void rga_reg_deinit(struct rga_reg *reg)
|
||||
{
|
||||
list_del_init(®->session_link);
|
||||
list_del_init(®->status_link);
|
||||
kfree(reg);
|
||||
}
|
||||
|
||||
static void rga_reg_from_wait_to_run(struct rga_reg *reg)
|
||||
{
|
||||
list_del_init(®->status_link);
|
||||
list_add_tail(®->status_link, &rga_service.running);
|
||||
|
||||
list_del_init(®->session_link);
|
||||
list_add_tail(®->session_link, ®->session->running);
|
||||
}
|
||||
|
||||
#if 0
|
||||
static void rga_reg_from_run_to_done(struct rga_reg *reg)
|
||||
{
|
||||
spin_lock(&rga_service.lock);
|
||||
list_del_init(®->status_link);
|
||||
list_add_tail(®->status_link, &rga_service.done);
|
||||
|
||||
list_del_init(®->session_link);
|
||||
list_add_tail(®->session_link, ®->session->done);
|
||||
|
||||
atomic_sub(1, ®->session->task_running);
|
||||
atomic_sub(1, &rga_service.total_running);
|
||||
wake_up_interruptible_sync(®->session->wait);
|
||||
spin_unlock(&rga_service.lock);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
static void rga_service_session_clear(rga_session *session)
|
||||
{
|
||||
struct rga_reg *reg, *n;
|
||||
|
||||
list_for_each_entry_safe(reg, n, &session->waiting, session_link)
|
||||
{
|
||||
rga_reg_deinit(reg);
|
||||
}
|
||||
|
||||
list_for_each_entry_safe(reg, n, &session->running, session_link)
|
||||
{
|
||||
rga_reg_deinit(reg);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void rga_try_set_reg(void)
|
||||
{
|
||||
unsigned long flag;
|
||||
|
||||
// first get reg from reg list
|
||||
spin_lock_irqsave(&rga_service.lock, flag);
|
||||
if (!list_empty(&rga_service.waiting))
|
||||
{
|
||||
struct rga_reg *reg = list_entry(rga_service.waiting.next, struct rga_reg, status_link);
|
||||
|
||||
if(!(rga_read(RGA_STATUS) & 0x1))
|
||||
{
|
||||
/* RGA is busy */
|
||||
if((atomic_read(&rga_service.total_running) <= 0xf) && (atomic_read(&rga_service.int_disable) == 0))
|
||||
{
|
||||
rga_copy_reg(reg, atomic_read(&rga_service.total_running));
|
||||
rga_reg_from_wait_to_run(reg);
|
||||
rga_write(RGA_INT, 0x1<<10);
|
||||
reg->session->done = 0;
|
||||
rga_write(RGA_CMD_CTRL, (0x1<<3)|(0x1<<1));
|
||||
if(atomic_read(®->int_enable))
|
||||
atomic_set(&rga_service.int_disable, 1);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* RGA is idle */
|
||||
rga_copy_reg(reg, 0);
|
||||
rga_reg_from_wait_to_run(reg);
|
||||
|
||||
/* MMU */
|
||||
rga_write(RGA_CMD_ADDR, 0);
|
||||
|
||||
/* All CMD finish int */
|
||||
rga_write(RGA_INT, 0x1<<10);
|
||||
|
||||
/* Start proc */
|
||||
reg->session->done = 0;
|
||||
rga_write(RGA_CMD_CTRL, (0x1<<3)|0x1);
|
||||
}
|
||||
}
|
||||
spin_unlock_irqrestore(&rga_service.lock, flag);
|
||||
}
|
||||
|
||||
|
||||
|
||||
static int rga_blit_async(rga_session *session, struct rga_req *req)
|
||||
{
|
||||
int ret = -1;
|
||||
struct rga_reg *reg0, *reg1;
|
||||
struct rga_req *req2;
|
||||
|
||||
uint32_t saw, sah, daw, dah;
|
||||
|
||||
saw = req->src.act_w;
|
||||
sah = req->src.act_h;
|
||||
daw = req->dst.act_w;
|
||||
dah = req->dst.act_h;
|
||||
|
||||
if((req->render_mode == bitblt_mode) && (((saw>>1) >= daw) || ((sah>>1) >= dah)))
|
||||
{
|
||||
/* generate 2 cmd for pre scale */
|
||||
|
||||
req2 = kmalloc(sizeof(struct rga_req), GFP_KERNEL);
|
||||
if(NULL == req2) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
RGA_gen_two_pro(req, req2);
|
||||
|
||||
reg0 = rga_reg_init(session, req2);
|
||||
if(reg0 == NULL) {
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
reg1 = rga_reg_init(session, req);
|
||||
if(reg1 == NULL) {
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
rga_try_set_reg();
|
||||
rga_try_set_reg();
|
||||
|
||||
if(req2 != NULL)
|
||||
{
|
||||
kfree(req2);
|
||||
}
|
||||
|
||||
}
|
||||
else {
|
||||
/* check value if legal */
|
||||
ret = rga_check_param(req);
|
||||
if(ret == -EINVAL) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
reg0 = rga_reg_init(session, req);
|
||||
if(reg0 == NULL) {
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
rga_try_set_reg();
|
||||
}
|
||||
|
||||
//printk("rga_blit_async done******************\n");
|
||||
|
||||
#if 0
|
||||
error_status:
|
||||
error_scale:
|
||||
ret = -EINVAL;
|
||||
rga_soft_reset();
|
||||
rga_power_off();
|
||||
#endif
|
||||
return ret;
|
||||
|
||||
}
|
||||
|
||||
static int rga_blit_sync(rga_session *session, struct rga_req *req)
|
||||
{
|
||||
int ret = 0;
|
||||
struct rga_reg *reg0, *reg1;
|
||||
struct rga_req *req2;
|
||||
|
||||
uint32_t saw, sah, daw, dah;
|
||||
|
||||
saw = req->src.act_w;
|
||||
sah = req->src.act_h;
|
||||
daw = req->dst.act_w;
|
||||
dah = req->dst.act_h;
|
||||
|
||||
if((req->render_mode == bitblt_mode) && (((saw>>1) >= daw) || ((sah>>1) >= dah)))
|
||||
{
|
||||
/* generate 2 cmd for pre scale */
|
||||
|
||||
req2 = kmalloc(sizeof(struct rga_req), GFP_KERNEL);
|
||||
if(NULL == req2) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
RGA_gen_two_pro(req, req2);
|
||||
|
||||
reg0 = rga_reg_init(session, req2);
|
||||
if(reg0 == NULL) {
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
reg1 = rga_reg_init(session, req);
|
||||
if(reg1 == NULL) {
|
||||
return -EFAULT;
|
||||
}
|
||||
atomic_set(®1->int_enable, 1);
|
||||
|
||||
rga_try_set_reg();
|
||||
rga_try_set_reg();
|
||||
|
||||
}
|
||||
else {
|
||||
/* check value if legal */
|
||||
ret = rga_check_param(req);
|
||||
if(ret == -EINVAL) {
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
reg0 = rga_reg_init(session, req);
|
||||
if(reg0 == NULL) {
|
||||
return -EFAULT;
|
||||
}
|
||||
atomic_set(®0->int_enable, 1);
|
||||
|
||||
rga_try_set_reg();
|
||||
}
|
||||
|
||||
ret = wait_event_interruptible_timeout(session->wait, session->done, RGA_TIMEOUT_DELAY);
|
||||
|
||||
if (unlikely(ret < 0))
|
||||
{
|
||||
pr_err("pid %d wait task ret %d\n", session->pid, ret);
|
||||
}
|
||||
else if (0 == ret)
|
||||
{
|
||||
pr_err("pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
|
||||
ret = -ETIMEDOUT;
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
||||
//printk("rga_blit_sync done******************\n");
|
||||
}
|
||||
|
||||
static long rga_ioctl(struct file *file, uint32_t cmd, unsigned long arg)
|
||||
{
|
||||
struct rga_req *req;
|
||||
int ret = 0;
|
||||
rga_session *session = (rga_session *)file->private_data;
|
||||
if (NULL == session)
|
||||
{
|
||||
printk("%s [%d] rga thread session is null\n",__FUNCTION__,__LINE__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
req = (struct rga_req *)kmalloc(sizeof(struct rga_req), GFP_KERNEL);
|
||||
if(req == NULL)
|
||||
{
|
||||
printk("%s [%d] get rga_req mem failed\n",__FUNCTION__,__LINE__);
|
||||
ret = -EINVAL;
|
||||
}
|
||||
|
||||
if (unlikely(copy_from_user(&req, (struct rga_req*)arg, sizeof(struct rga_req))))
|
||||
{
|
||||
ERR("copy_from_user failed\n");
|
||||
ret = -EFAULT;
|
||||
}
|
||||
|
||||
switch (cmd)
|
||||
{
|
||||
case RGA_BLIT_SYNC:
|
||||
ret = rga_blit_sync(session, req);
|
||||
break;
|
||||
case RGA_BLIT_ASYNC:
|
||||
ret = rga_blit_async(session, req);
|
||||
break;
|
||||
case RGA_FLUSH:
|
||||
ret = rga_flush(session, arg);
|
||||
break;
|
||||
default:
|
||||
ERR("unknown ioctl cmd!\n");
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
if(req != NULL)
|
||||
{
|
||||
kfree(req);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rga_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
rga_session *session = (rga_session *)kmalloc(sizeof(rga_session), GFP_KERNEL);
|
||||
if (NULL == session) {
|
||||
pr_err("unable to allocate memory for rga_session.");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
session->pid = current->pid;
|
||||
INIT_LIST_HEAD(&session->waiting);
|
||||
INIT_LIST_HEAD(&session->running);
|
||||
INIT_LIST_HEAD(&session->list_session);
|
||||
init_waitqueue_head(&session->wait);
|
||||
/* no need to protect */
|
||||
list_add_tail(&session->list_session, &rga_service.session);
|
||||
atomic_set(&session->task_running, 0);
|
||||
file->private_data = (void *)session;
|
||||
|
||||
DBG("*** rga dev opened *** \n");
|
||||
return nonseekable_open(inode, file);
|
||||
|
||||
}
|
||||
|
||||
static int rga_release(struct inode *inode, struct file *file)
|
||||
{
|
||||
int task_running;
|
||||
unsigned long flag;
|
||||
rga_session *session = (rga_session *)file->private_data;
|
||||
if (NULL == session)
|
||||
return -EINVAL;
|
||||
|
||||
task_running = atomic_read(&session->task_running);
|
||||
if (task_running) {
|
||||
pr_err("rga_service session %d still has %d task running when closing\n", session->pid, task_running);
|
||||
msleep(50);
|
||||
}
|
||||
wake_up_interruptible_sync(&session->wait);
|
||||
spin_lock_irqsave(&rga_service.lock, flag);
|
||||
list_del(&session->list_session);
|
||||
rga_service_session_clear(session);
|
||||
kfree(session);
|
||||
spin_unlock_irqrestore(&rga_service.lock, flag);
|
||||
|
||||
pr_debug("dev closed\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static irqreturn_t rga_irq(int irq, void *dev_id)
|
||||
{
|
||||
struct rga_reg *reg;
|
||||
|
||||
DBG("rga_irq %d \n", irq);
|
||||
|
||||
/*clear INT */
|
||||
rga_write(rga_read(RGA_INT) | (0x1<<6), RGA_INT);
|
||||
if(((rga_read(RGA_STATUS) & 0x1) != 0))// idle
|
||||
{
|
||||
printk("RGA is not idle!\n");
|
||||
rga_soft_reset();
|
||||
}
|
||||
|
||||
spin_lock(&rga_service.lock);
|
||||
do
|
||||
{
|
||||
reg = list_entry(rga_service.running.next, struct rga_reg, status_link);
|
||||
if(reg->MMU_base != NULL)
|
||||
{
|
||||
kfree(reg->MMU_base);
|
||||
}
|
||||
|
||||
atomic_sub(1, ®->session->task_running);
|
||||
atomic_sub(1, &rga_service.total_running);
|
||||
|
||||
if(list_empty(®->session->waiting))
|
||||
{
|
||||
reg->session->done = 1;
|
||||
wake_up_interruptible_sync(®->session->wait);
|
||||
}
|
||||
rga_reg_deinit(reg);
|
||||
|
||||
}
|
||||
while(!list_empty(&rga_service.running));
|
||||
|
||||
|
||||
/* add cmd to cmd buf */
|
||||
while(((!list_empty(&rga_service.waiting)) && (atomic_read(&rga_service.int_disable) == 0)))
|
||||
{
|
||||
rga_try_set_reg();
|
||||
}
|
||||
|
||||
spin_lock(&rga_service.lock);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int rga_suspend(struct platform_device *pdev, pm_message_t state)
|
||||
{
|
||||
uint32_t enable;
|
||||
|
||||
enable = drvdata->enable;
|
||||
rga_power_off(NULL);
|
||||
drvdata->enable = enable;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rga_resume(struct platform_device *pdev)
|
||||
{
|
||||
rga_power_on();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rga_shutdown(struct platform_device *pdev)
|
||||
{
|
||||
pr_cont("shutdown...");
|
||||
rga_power_off(NULL);
|
||||
pr_cont("done\n");
|
||||
}
|
||||
|
||||
|
||||
|
||||
struct file_operations rga_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.open = rga_open,
|
||||
.release = rga_release,
|
||||
.unlocked_ioctl = rga_ioctl,
|
||||
};
|
||||
|
||||
static struct miscdevice rga_dev ={
|
||||
.minor = RGA_MAJOR,
|
||||
.name = "rga",
|
||||
.fops = &rga_fops,
|
||||
};
|
||||
|
||||
static int __devinit rga_drv_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct rga_drvdata *data;
|
||||
int ret = 0;
|
||||
|
||||
data = kmalloc(sizeof(struct rga_drvdata), GFP_KERNEL);
|
||||
|
||||
INIT_LIST_HEAD(&rga_service.waiting);
|
||||
INIT_LIST_HEAD(&rga_service.running);
|
||||
INIT_LIST_HEAD(&rga_service.done);
|
||||
INIT_LIST_HEAD(&rga_service.session);
|
||||
spin_lock_init(&rga_service.lock);
|
||||
atomic_set(&rga_service.total_running, 0);
|
||||
rga_service.enabled = false;
|
||||
|
||||
if(NULL == data)
|
||||
{
|
||||
ERR("failed to allocate driver data.\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/* get the clock */
|
||||
data->pd_display = clk_get(&pdev->dev, "pd_display");
|
||||
if (IS_ERR(data->pd_display))
|
||||
{
|
||||
ERR("failed to find rga pd_display source\n");
|
||||
ret = -ENOENT;
|
||||
goto err_clock;
|
||||
}
|
||||
|
||||
data->aclk_lcdc = clk_get(&pdev->dev, "aclk_lcdc");
|
||||
if (IS_ERR(data->aclk_lcdc))
|
||||
{
|
||||
ERR("failed to find rga aclk_lcdc source\n");
|
||||
ret = -ENOENT;
|
||||
goto err_clock;
|
||||
}
|
||||
|
||||
data->hclk_lcdc = clk_get(&pdev->dev, "hclk_lcdc");
|
||||
if (IS_ERR(data->hclk_lcdc))
|
||||
{
|
||||
ERR("failed to find rga hclk_lcdc source\n");
|
||||
ret = -ENOENT;
|
||||
goto err_clock;
|
||||
}
|
||||
|
||||
data->aclk_ddr_lcdc = clk_get(&pdev->dev, "aclk_ddr_lcdc");
|
||||
if (IS_ERR(data->aclk_ddr_lcdc))
|
||||
{
|
||||
ERR("failed to find rga aclk_ddr_lcdc source\n");
|
||||
ret = -ENOENT;
|
||||
goto err_clock;
|
||||
}
|
||||
|
||||
data->hclk_cpu_display = clk_get(&pdev->dev, "hclk_cpu_display");
|
||||
if (IS_ERR(data->hclk_cpu_display))
|
||||
{
|
||||
ERR("failed to find rga hclk_cpu_display source\n");
|
||||
ret = -ENOENT;
|
||||
goto err_clock;
|
||||
}
|
||||
|
||||
data->aclk_disp_matrix = clk_get(&pdev->dev, "aclk_disp_matrix");
|
||||
if (IS_ERR(data->aclk_disp_matrix))
|
||||
{
|
||||
ERR("failed to find rga aclk_disp_matrix source\n");
|
||||
ret = -ENOENT;
|
||||
goto err_clock;
|
||||
}
|
||||
|
||||
data->hclk_disp_matrix = clk_get(&pdev->dev, "hclk_disp_matrix");
|
||||
if (IS_ERR(data->hclk_disp_matrix))
|
||||
{
|
||||
ERR("failed to find rga hclk_disp_matrix source\n");
|
||||
ret = -ENOENT;
|
||||
goto err_clock;
|
||||
}
|
||||
|
||||
data->axi_clk = clk_get(&pdev->dev, "aclk_rga");
|
||||
if (IS_ERR(data->axi_clk))
|
||||
{
|
||||
ERR("failed to find rga axi clock source\n");
|
||||
ret = -ENOENT;
|
||||
goto err_clock;
|
||||
}
|
||||
|
||||
data->ahb_clk = clk_get(&pdev->dev, "hclk_rga");
|
||||
if (IS_ERR(data->ahb_clk))
|
||||
{
|
||||
ERR("failed to find rga ahb clock source\n");
|
||||
ret = -ENOENT;
|
||||
goto err_clock;
|
||||
}
|
||||
|
||||
/* map the memory */
|
||||
if (!request_mem_region(RK30_RGA_PHYS, RK30_RGA_SIZE, "rga_io"))
|
||||
{
|
||||
pr_info("failed to reserve rga HW regs\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
data->rga_base = (void*)ioremap_nocache(RK30_RGA_PHYS, RK30_RGA_SIZE);
|
||||
if (data->rga_base == NULL)
|
||||
{
|
||||
ERR("rga ioremap failed\n");
|
||||
ret = -ENOENT;
|
||||
goto err_ioremap;
|
||||
}
|
||||
|
||||
/* get the IRQ */
|
||||
data->irq0 = pdev->resource[1].start;
|
||||
printk("rga irq %d\n", data->irq0);
|
||||
if (data->irq0 <= 0)
|
||||
{
|
||||
ERR("failed to get rga irq resource (%d).\n", data->irq0);
|
||||
ret = data->irq0;
|
||||
goto err_irq;
|
||||
}
|
||||
|
||||
/* request the IRQ */
|
||||
ret = request_irq(data->irq0, rga_irq, 0/*IRQF_DISABLED*/, "rga", pdev);
|
||||
if (ret)
|
||||
{
|
||||
ERR("rga request_irq failed (%d).\n", ret);
|
||||
goto err_irq;
|
||||
}
|
||||
|
||||
mutex_init(&data->mutex);
|
||||
data->enable = false;
|
||||
INIT_DELAYED_WORK(&data->power_off_work, rga_power_off);
|
||||
data->rga_irq_callback = NULL;
|
||||
|
||||
platform_set_drvdata(pdev, data);
|
||||
drvdata = data;
|
||||
|
||||
ret = misc_register(&rga_dev);
|
||||
if(ret)
|
||||
{
|
||||
ERR("cannot register miscdev (%d)\n", ret);
|
||||
goto err_misc_register;
|
||||
}
|
||||
DBG("RGA Driver loaded succesfully\n");
|
||||
|
||||
return 0;
|
||||
|
||||
err_misc_register:
|
||||
free_irq(data->irq0, pdev);
|
||||
err_irq:
|
||||
iounmap(data->rga_base);
|
||||
err_ioremap:
|
||||
err_clock:
|
||||
kfree(data);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rga_drv_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct rga_drvdata *data = platform_get_drvdata(pdev);
|
||||
DBG("%s [%d]\n",__FUNCTION__,__LINE__);
|
||||
|
||||
misc_deregister(&(data->miscdev));
|
||||
free_irq(data->irq0, &data->miscdev);
|
||||
iounmap((void __iomem *)(data->rga_base));
|
||||
|
||||
if(data->axi_clk) {
|
||||
clk_put(data->axi_clk);
|
||||
}
|
||||
|
||||
if(data->ahb_clk) {
|
||||
clk_put(data->ahb_clk);
|
||||
}
|
||||
if(data->aclk_disp_matrix) {
|
||||
clk_put(data->aclk_disp_matrix);
|
||||
}
|
||||
|
||||
if(data->hclk_disp_matrix) {
|
||||
clk_put(data->hclk_disp_matrix);
|
||||
}
|
||||
|
||||
if(data->aclk_ddr_lcdc) {
|
||||
clk_put(data->aclk_ddr_lcdc);
|
||||
}
|
||||
|
||||
if(data->hclk_lcdc) {
|
||||
clk_put(data->hclk_lcdc);
|
||||
}
|
||||
|
||||
if(data->aclk_lcdc) {
|
||||
clk_put(data->aclk_lcdc);
|
||||
}
|
||||
|
||||
if(data->hclk_cpu_display) {
|
||||
clk_put(data->hclk_cpu_display);
|
||||
}
|
||||
|
||||
if(data->pd_display){
|
||||
clk_put(data->pd_display);
|
||||
}
|
||||
|
||||
kfree(data);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver rga_driver = {
|
||||
.probe = rga_drv_probe,
|
||||
.remove = __devexit_p(rga_drv_remove),
|
||||
.suspend = rga_suspend,
|
||||
.resume = rga_resume,
|
||||
.shutdown = rga_shutdown,
|
||||
.driver = {
|
||||
.owner = THIS_MODULE,
|
||||
.name = "rga",
|
||||
},
|
||||
};
|
||||
|
||||
static int __init rga_init(void)
|
||||
{
|
||||
int ret;
|
||||
uint8_t *buf;
|
||||
|
||||
/* malloc pre scale mid buf */
|
||||
buf = kmalloc(PRE_SCALE_BUF_SIZE, GFP_KERNEL);
|
||||
if(buf == NULL) {
|
||||
ERR("RGA get Pre Scale buff failed. \n");
|
||||
return -1;
|
||||
}
|
||||
rga_service.pre_scale_buf = (uint32_t *)buf;
|
||||
|
||||
if ((ret = platform_driver_register(&rga_driver)) != 0)
|
||||
{
|
||||
ERR("Platform device register failed (%d).\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
INFO("Module initialized.\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __exit rga_exit(void)
|
||||
{
|
||||
if(rga_service.pre_scale_buf != NULL) {
|
||||
kfree((uint8_t *)rga_service.pre_scale_buf);
|
||||
}
|
||||
platform_driver_unregister(&rga_driver);
|
||||
}
|
||||
|
||||
|
||||
|
||||
module_init(rga_init);
|
||||
module_exit(rga_exit);
|
||||
|
||||
|
||||
/* Module information */
|
||||
MODULE_AUTHOR("zsq@rock-chips.com");
|
||||
MODULE_DESCRIPTION("Driver for rga device");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
|
||||
950
drivers/video/rockchip/rga/rga_mmu_info.c
Normal file
950
drivers/video/rockchip/rga/rga_mmu_info.c
Normal file
@@ -0,0 +1,950 @@
|
||||
|
||||
|
||||
#include <linux/version.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/signal.h>
|
||||
#include <linux/pagemap.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/mman.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/slab.h>
|
||||
#include <asm/atomic.h>
|
||||
|
||||
|
||||
#include "rga_mmu_info.h"
|
||||
|
||||
|
||||
extern rga_service_info rga_service;
|
||||
|
||||
#define KERNEL_SPACE_VALID 0xc0000000
|
||||
|
||||
static int rga_mem_size_cal(uint32_t Mem, uint32_t MemSize, uint32_t *StartAddr)
|
||||
{
|
||||
uint32_t start, end;
|
||||
uint32_t pageCount;
|
||||
|
||||
end = (Mem + (MemSize + PAGE_SIZE - 1)) >> PAGE_SHIFT;
|
||||
start = Mem >> PAGE_SHIFT;
|
||||
pageCount = end - start;
|
||||
*StartAddr = start;
|
||||
return pageCount;
|
||||
}
|
||||
|
||||
static int rga_buf_size_cal(uint32_t yrgb_addr, uint32_t uv_addr, uint32_t v_addr,
|
||||
int format, uint32_t w, uint32_t h, uint32_t *StartAddr )
|
||||
{
|
||||
uint32_t size_yrgb = 0;
|
||||
uint32_t size_uv = 0;
|
||||
uint32_t size_v = 0;
|
||||
uint32_t stride = 0;
|
||||
uint32_t start, end;
|
||||
uint32_t pageCount;
|
||||
|
||||
switch(format)
|
||||
{
|
||||
case RK_FORMAT_RGBA_8888 :
|
||||
stride = (w * 4 + 3) & (~3);
|
||||
size_yrgb = stride*h;
|
||||
end = (yrgb_addr + (size_yrgb + PAGE_SIZE - 1)) >> PAGE_SHIFT;
|
||||
start = yrgb_addr >> PAGE_SHIFT;
|
||||
pageCount = end - start;
|
||||
break;
|
||||
case RK_FORMAT_RGBX_8888 :
|
||||
stride = (w * 4 + 3) & (~3);
|
||||
size_yrgb = stride*h;
|
||||
end = (yrgb_addr + (size_yrgb + PAGE_SIZE - 1)) >> PAGE_SHIFT;
|
||||
start = yrgb_addr >> PAGE_SHIFT;
|
||||
pageCount = end - start;
|
||||
break;
|
||||
case RK_FORMAT_RGB_888 :
|
||||
stride = (w * 3 + 3) & (~3);
|
||||
size_yrgb = stride*h;
|
||||
end = (yrgb_addr + (size_yrgb + PAGE_SIZE - 1)) >> PAGE_SHIFT;
|
||||
start = yrgb_addr >> PAGE_SHIFT;
|
||||
pageCount = end - start;
|
||||
break;
|
||||
case RK_FORMAT_BGRA_8888 :
|
||||
size_yrgb = w*h*4;
|
||||
end = (yrgb_addr + (size_yrgb + PAGE_SIZE - 1)) >> PAGE_SHIFT;
|
||||
start = yrgb_addr >> PAGE_SHIFT;
|
||||
pageCount = end - start;
|
||||
*StartAddr = start;
|
||||
break;
|
||||
case RK_FORMAT_RGB_565 :
|
||||
stride = (w*2 + 3) & (~3);
|
||||
size_yrgb = stride * h;
|
||||
end = (yrgb_addr + (size_yrgb + PAGE_SIZE - 1)) >> PAGE_SHIFT;
|
||||
start = yrgb_addr >> PAGE_SHIFT;
|
||||
pageCount = end - start;
|
||||
break;
|
||||
case RK_FORMAT_RGBA_5551 :
|
||||
stride = (w*2 + 3) & (~3);
|
||||
size_yrgb = stride * h;
|
||||
end = (yrgb_addr + (size_yrgb + PAGE_SIZE - 1)) >> PAGE_SHIFT;
|
||||
start = yrgb_addr >> PAGE_SHIFT;
|
||||
pageCount = end - start;
|
||||
break;
|
||||
case RK_FORMAT_RGBA_4444 :
|
||||
stride = (w*2 + 3) & (~3);
|
||||
size_yrgb = stride * h;
|
||||
end = (yrgb_addr + (size_yrgb + PAGE_SIZE - 1)) >> PAGE_SHIFT;
|
||||
start = yrgb_addr >> PAGE_SHIFT;
|
||||
pageCount = end - start;
|
||||
break;
|
||||
case RK_FORMAT_BGR_888 :
|
||||
stride = (w*3 + 3) & (~3);
|
||||
size_yrgb = stride * h;
|
||||
end = (yrgb_addr + (size_yrgb + PAGE_SIZE - 1)) >> PAGE_SHIFT;
|
||||
start = yrgb_addr >> PAGE_SHIFT;
|
||||
pageCount = end - start;
|
||||
break;
|
||||
|
||||
/* YUV FORMAT */
|
||||
case RK_FORMAT_YCbCr_422_SP :
|
||||
stride = (w + 3) & (~3);
|
||||
size_yrgb = stride * h;
|
||||
size_uv = stride * h;
|
||||
start = MIN(yrgb_addr, uv_addr);
|
||||
start >>= PAGE_SHIFT;
|
||||
end = MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv));
|
||||
end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
|
||||
pageCount = end - start;
|
||||
break;
|
||||
case RK_FORMAT_YCbCr_422_P :
|
||||
stride = (w + 3) & (~3);
|
||||
size_yrgb = stride * h;
|
||||
size_uv = ((stride >> 1) * h);
|
||||
size_v = ((stride >> 1) * h);
|
||||
start = MIN(MIN(yrgb_addr, uv_addr), v_addr);
|
||||
start = start >> PAGE_SHIFT;
|
||||
end = MAX(MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv)), (v_addr + size_v));
|
||||
end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
|
||||
pageCount = end - start;
|
||||
break;
|
||||
case RK_FORMAT_YCbCr_420_SP :
|
||||
stride = (w + 3) & (~3);
|
||||
size_yrgb = stride * h;
|
||||
size_uv = (stride * (h >> 1));
|
||||
start = MIN(yrgb_addr, uv_addr);
|
||||
start >>= PAGE_SHIFT;
|
||||
end = MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv));
|
||||
end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
|
||||
pageCount = end - start;
|
||||
break;
|
||||
case RK_FORMAT_YCbCr_420_P :
|
||||
stride = (w + 3) & (~3);
|
||||
size_yrgb = stride * h;
|
||||
size_uv = ((stride >> 1) * (h >> 1));
|
||||
size_v = ((stride >> 1) * (h >> 1));
|
||||
start = MIN(MIN(yrgb_addr, uv_addr), v_addr);
|
||||
start >>= PAGE_SHIFT;
|
||||
end = MAX(MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv)), (v_addr + size_v));
|
||||
end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
|
||||
pageCount = end - start;
|
||||
break;
|
||||
|
||||
case RK_FORMAT_YCrCb_422_SP :
|
||||
stride = (w + 3) & (~3);
|
||||
size_yrgb = stride * h;
|
||||
size_uv = stride * h;
|
||||
start = MIN(yrgb_addr, uv_addr);
|
||||
start >>= PAGE_SHIFT;
|
||||
end = MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv));
|
||||
end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
|
||||
pageCount = end - start;
|
||||
break;
|
||||
case RK_FORMAT_YCrCb_422_P :
|
||||
stride = (w + 3) & (~3);
|
||||
size_yrgb = stride * h;
|
||||
size_uv = ((stride >> 1) * h);
|
||||
size_v = ((stride >> 1) * h);
|
||||
start = MIN(MIN(yrgb_addr, uv_addr), v_addr);
|
||||
start >>= PAGE_SHIFT;
|
||||
end = MAX(MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv)), (v_addr + size_v));
|
||||
end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
|
||||
pageCount = end - start;
|
||||
break;
|
||||
|
||||
case RK_FORMAT_YCrCb_420_SP :
|
||||
stride = (w + 3) & (~3);
|
||||
size_yrgb = stride * h;
|
||||
size_uv = (stride * (h >> 1));
|
||||
start = MIN(yrgb_addr, uv_addr);
|
||||
start >>= PAGE_SHIFT;
|
||||
end = MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv));
|
||||
end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
|
||||
pageCount = end - start;
|
||||
break;
|
||||
case RK_FORMAT_YCrCb_420_P :
|
||||
stride = (w + 3) & (~3);
|
||||
size_yrgb = stride * h;
|
||||
size_uv = ((stride >> 1) * (h >> 1));
|
||||
size_v = ((stride >> 1) * (h >> 1));
|
||||
start = MIN(MIN(yrgb_addr, uv_addr), v_addr);
|
||||
start >>= PAGE_SHIFT;
|
||||
end = MAX(MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv)), (v_addr + size_v));
|
||||
end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
|
||||
pageCount = end - start;
|
||||
break;
|
||||
#if 0
|
||||
case RK_FORMAT_BPP1 :
|
||||
break;
|
||||
case RK_FORMAT_BPP2 :
|
||||
break;
|
||||
case RK_FORMAT_BPP4 :
|
||||
break;
|
||||
case RK_FORMAT_BPP8 :
|
||||
break;
|
||||
#endif
|
||||
default :
|
||||
pageCount = 0;
|
||||
start = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
*StartAddr = start;
|
||||
return pageCount;
|
||||
}
|
||||
|
||||
static int rga_MapUserMemory(struct page **pages,
|
||||
uint32_t *pageTable,
|
||||
uint32_t Memory,
|
||||
uint32_t pageCount)
|
||||
{
|
||||
int32_t result;
|
||||
uint32_t i;
|
||||
|
||||
down_read(¤t->mm->mmap_sem);
|
||||
result = get_user_pages(current,
|
||||
current->mm,
|
||||
Memory << PAGE_SHIFT,
|
||||
pageCount,
|
||||
1,
|
||||
0,
|
||||
pages,
|
||||
NULL
|
||||
);
|
||||
up_read(¤t->mm->mmap_sem);
|
||||
|
||||
if(result <= 0 || result < pageCount)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
for (i = 0; i < pageCount; i++)
|
||||
{
|
||||
/* Flush the data cache. */
|
||||
#ifdef ANDROID
|
||||
dma_sync_single_for_device(
|
||||
gcvNULL,
|
||||
page_to_phys(pages[i]),
|
||||
PAGE_SIZE,
|
||||
DMA_TO_DEVICE);
|
||||
#else
|
||||
flush_dcache_page(pages[i]);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Fill the page table. */
|
||||
for(i=0; i<pageCount; i++) {
|
||||
|
||||
/* Get the physical address from page struct. */
|
||||
pageTable[i * (PAGE_SIZE/4096)] = page_to_phys(pages[i]);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rga_mmu_info_BitBlt_mode(struct rga_reg *reg, struct rga_req *req)
|
||||
{
|
||||
int SrcMemSize, DstMemSize, CMDMemSize;
|
||||
uint32_t SrcStart, DstStart, CMDStart;
|
||||
uint32_t i;
|
||||
uint32_t AllSize;
|
||||
uint32_t *MMU_Base, *MMU_p;
|
||||
int ret;
|
||||
|
||||
struct page **pages = NULL;
|
||||
|
||||
/* cal src buf mmu info */
|
||||
SrcMemSize = rga_buf_size_cal(req->src.yrgb_addr, req->src.uv_addr, req->src.v_addr,
|
||||
req->src.format, req->src.vir_w, req->src.vir_h,
|
||||
&SrcStart);
|
||||
if(SrcMemSize == 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* cal dst buf mmu info */
|
||||
DstMemSize = rga_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr,
|
||||
req->dst.format, req->dst.vir_w, req->dst.vir_h,
|
||||
&DstStart);
|
||||
if(DstMemSize == 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* cal cmd buf mmu info */
|
||||
CMDMemSize = rga_mem_size_cal((uint32_t)rga_service.cmd_buff, RGA_CMD_BUF_SIZE, &CMDStart);
|
||||
if(CMDMemSize == 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
AllSize = SrcMemSize + DstMemSize + CMDMemSize;
|
||||
|
||||
pages = (struct page **)kmalloc(AllSize * sizeof(struct page *), GFP_KERNEL);
|
||||
if(pages == NULL) {
|
||||
pr_err("RGA MMU malloc pages mem failed");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
MMU_Base = (uint32_t *)kmalloc(AllSize * sizeof(uint32_t), GFP_KERNEL);
|
||||
if(pages == NULL) {
|
||||
pr_err("RGA MMU malloc MMU_Base point failed");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
for(i=0; i<CMDMemSize; i++) {
|
||||
MMU_Base[i] = (uint32_t)virt_to_phys((uint32_t *)((CMDStart + i)<< PAGE_SHIFT));
|
||||
}
|
||||
|
||||
if(req->src.yrgb_addr < KERNEL_SPACE_VALID)
|
||||
{
|
||||
ret = rga_MapUserMemory(&pages[CMDMemSize], &MMU_Base[CMDMemSize], SrcStart, SrcMemSize);
|
||||
if (ret < 0) {
|
||||
pr_err("rga map src memory failed");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
MMU_p = MMU_Base + CMDMemSize;
|
||||
|
||||
for(i=0; i<SrcMemSize; i++)
|
||||
{
|
||||
MMU_p[i] = (uint32_t)virt_to_phys((uint32_t *)((SrcStart + i) << PAGE_SHIFT));
|
||||
}
|
||||
}
|
||||
|
||||
if(req->dst.yrgb_addr < KERNEL_SPACE_VALID)
|
||||
{
|
||||
ret = rga_MapUserMemory(&pages[CMDMemSize + SrcMemSize], &MMU_Base[CMDMemSize + SrcMemSize], DstStart, DstMemSize);
|
||||
if (ret < 0) {
|
||||
pr_err("rga map dst memory failed");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
MMU_p = MMU_Base + CMDMemSize + SrcMemSize;
|
||||
|
||||
for(i=0; i<DstMemSize; i++)
|
||||
{
|
||||
MMU_p[i] = (uint32_t)virt_to_phys((uint32_t *)((DstStart + i) << PAGE_SHIFT));
|
||||
}
|
||||
}
|
||||
|
||||
/* zsq
|
||||
* change the buf address in req struct
|
||||
* for the reason of lie to MMU
|
||||
*/
|
||||
req->mmu_info.base_addr = virt_to_phys(MMU_Base);
|
||||
|
||||
req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);
|
||||
req->src.uv_addr = (req->src.uv_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);
|
||||
req->src.v_addr = (req->src.v_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);
|
||||
|
||||
req->dst.yrgb_addr = (req->dst.yrgb_addr & (~PAGE_MASK)) | ((CMDMemSize + SrcMemSize) << PAGE_SHIFT);
|
||||
|
||||
/*record the malloc buf for the cmd end to release*/
|
||||
reg->MMU_base = MMU_Base;
|
||||
|
||||
if (pages != NULL) {
|
||||
/* Free the page table */
|
||||
kfree(pages);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rga_mmu_info_color_palette_mode(struct rga_reg *reg, struct rga_req *req)
|
||||
{
|
||||
int SrcMemSize, DstMemSize, CMDMemSize;
|
||||
uint32_t SrcStart, DstStart, CMDStart;
|
||||
struct page **pages = NULL;
|
||||
uint32_t i;
|
||||
uint32_t AllSize;
|
||||
uint32_t *MMU_Base;
|
||||
int ret;
|
||||
uint32_t stride;
|
||||
|
||||
uint8_t shift;
|
||||
uint16_t sw, byte_num;
|
||||
|
||||
shift = 3 - (req->palette_mode & 3);
|
||||
sw = req->src.vir_w;
|
||||
byte_num = sw >> shift;
|
||||
stride = (byte_num + 3) & (~3);
|
||||
|
||||
SrcMemSize = rga_mem_size_cal(req->src.yrgb_addr, stride, &SrcStart);
|
||||
if(SrcMemSize == 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
DstMemSize = rga_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr,
|
||||
req->dst.format, req->dst.vir_w, req->dst.vir_h,
|
||||
&DstStart);
|
||||
if(DstMemSize == 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
CMDMemSize = rga_mem_size_cal((uint32_t)rga_service.cmd_buff, RGA_CMD_BUF_SIZE, &CMDStart);
|
||||
if(CMDMemSize == 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
AllSize = SrcMemSize + DstMemSize + CMDMemSize;
|
||||
|
||||
pages = (struct page **)kmalloc(AllSize * sizeof(struct page *), GFP_KERNEL);
|
||||
if(pages == NULL) {
|
||||
pr_err("RGA MMU malloc pages mem failed");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
MMU_Base = (uint32_t *)kmalloc(AllSize * sizeof(uint32_t), GFP_KERNEL);
|
||||
if(pages == NULL) {
|
||||
pr_err("RGA MMU malloc MMU_Base point failed");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
for(i=0; i<CMDMemSize; i++) {
|
||||
MMU_Base[i] = virt_to_phys((uint32_t *)((CMDStart + i)<<PAGE_SHIFT));
|
||||
}
|
||||
|
||||
ret = rga_MapUserMemory(&pages[CMDMemSize], &MMU_Base[CMDMemSize], SrcStart, SrcMemSize);
|
||||
if (ret < 0) {
|
||||
pr_err("rga map src memory failed");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = rga_MapUserMemory(&pages[CMDMemSize + SrcMemSize], &MMU_Base[CMDMemSize + SrcMemSize], DstStart, DstMemSize);
|
||||
if (ret < 0) {
|
||||
pr_err("rga map dst memory failed");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* zsq
|
||||
* change the buf address in req struct
|
||||
* for the reason of lie to MMU
|
||||
*/
|
||||
req->mmu_info.base_addr = virt_to_phys(MMU_Base);
|
||||
req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);
|
||||
req->dst.yrgb_addr = (req->dst.yrgb_addr & (~PAGE_MASK)) | ((CMDMemSize + SrcMemSize) << PAGE_SHIFT);
|
||||
|
||||
|
||||
/*record the malloc buf for the cmd end to release*/
|
||||
reg->MMU_base = MMU_Base;
|
||||
|
||||
if (pages != NULL) {
|
||||
/* Free the page table */
|
||||
kfree(pages);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rga_mmu_info_color_fill_mode(struct rga_reg *reg, struct rga_req *req)
|
||||
{
|
||||
int DstMemSize, CMDMemSize;
|
||||
uint32_t DstStart, CMDStart;
|
||||
struct page **pages = NULL;
|
||||
uint32_t i;
|
||||
uint32_t AllSize;
|
||||
uint32_t *MMU_Base;
|
||||
int ret;
|
||||
|
||||
DstMemSize = rga_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr,
|
||||
req->dst.format, req->dst.vir_w, req->dst.vir_h,
|
||||
&DstStart);
|
||||
if(DstMemSize == 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
CMDMemSize = rga_mem_size_cal((uint32_t)rga_service.cmd_buff, RGA_CMD_BUF_SIZE, &CMDStart);
|
||||
if(CMDMemSize == 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
AllSize = DstMemSize + CMDMemSize;
|
||||
|
||||
pages = (struct page **)kmalloc(AllSize * sizeof(struct page *), GFP_KERNEL);
|
||||
if(pages == NULL) {
|
||||
pr_err("RGA MMU malloc pages mem failed");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
MMU_Base = (uint32_t *)kmalloc(AllSize * sizeof(uint32_t), GFP_KERNEL);
|
||||
if(pages == NULL) {
|
||||
pr_err("RGA MMU malloc MMU_Base point failed");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
for(i=0; i<CMDMemSize; i++) {
|
||||
MMU_Base[i] = virt_to_phys((uint32_t *)((CMDStart+i)<<PAGE_SHIFT));
|
||||
}
|
||||
|
||||
ret = rga_MapUserMemory(&pages[CMDMemSize], &MMU_Base[CMDMemSize], DstStart, DstMemSize);
|
||||
if (ret < 0) {
|
||||
pr_err("rga map dst memory failed");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* zsq
|
||||
* change the buf address in req struct
|
||||
* for the reason of lie to MMU
|
||||
*/
|
||||
req->mmu_info.base_addr = virt_to_phys(MMU_Base);
|
||||
req->dst.yrgb_addr = (req->dst.yrgb_addr & (~PAGE_MASK)) | ((CMDMemSize) << PAGE_SHIFT);
|
||||
|
||||
|
||||
/*record the malloc buf for the cmd end to release*/
|
||||
reg->MMU_base = MMU_Base;
|
||||
|
||||
if (pages != NULL) {
|
||||
/* Free the page table */
|
||||
kfree(pages);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int rga_mmu_info_line_point_drawing_mode(struct rga_reg *reg, struct rga_req *req)
|
||||
{
|
||||
int DstMemSize, CMDMemSize;
|
||||
uint32_t DstStart, CMDStart;
|
||||
struct page **pages = NULL;
|
||||
uint32_t i;
|
||||
uint32_t AllSize;
|
||||
uint32_t *MMU_Base;
|
||||
int ret;
|
||||
|
||||
/* cal dst buf mmu info */
|
||||
DstMemSize = rga_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr,
|
||||
req->dst.format, req->dst.vir_w, req->dst.vir_h,
|
||||
&DstStart);
|
||||
if(DstMemSize == 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
CMDMemSize = rga_mem_size_cal((uint32_t)rga_service.cmd_buff, RGA_CMD_BUF_SIZE, &CMDStart);
|
||||
if(CMDMemSize == 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
AllSize = DstMemSize + CMDMemSize;
|
||||
|
||||
pages = (struct page **)kmalloc(AllSize * sizeof(struct page *), GFP_KERNEL);
|
||||
if(pages == NULL) {
|
||||
pr_err("RGA MMU malloc pages mem failed");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
MMU_Base = (uint32_t *)kmalloc(AllSize * sizeof(uint32_t), GFP_KERNEL);
|
||||
if(pages == NULL) {
|
||||
pr_err("RGA MMU malloc MMU_Base point failed");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
for(i=0; i<CMDMemSize; i++) {
|
||||
MMU_Base[i] = virt_to_phys((uint32_t *)((CMDStart+i)<<PAGE_SHIFT));
|
||||
}
|
||||
|
||||
ret = rga_MapUserMemory(&pages[CMDMemSize], &MMU_Base[CMDMemSize], DstStart, DstMemSize);
|
||||
if (ret < 0) {
|
||||
pr_err("rga map dst memory failed");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* zsq
|
||||
* change the buf address in req struct
|
||||
* for the reason of lie to MMU
|
||||
*/
|
||||
req->mmu_info.base_addr = virt_to_phys(MMU_Base);
|
||||
req->dst.yrgb_addr = (req->dst.yrgb_addr & (~PAGE_MASK)) | ((CMDMemSize) << PAGE_SHIFT);
|
||||
|
||||
|
||||
/*record the malloc buf for the cmd end to release*/
|
||||
reg->MMU_base = MMU_Base;
|
||||
|
||||
if (pages != NULL) {
|
||||
/* Free the page table */
|
||||
kfree(pages);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rga_mmu_info_blur_sharp_filter_mode(struct rga_reg *reg, struct rga_req *req)
|
||||
{
|
||||
int SrcMemSize, DstMemSize, CMDMemSize;
|
||||
uint32_t SrcStart, DstStart, CMDStart;
|
||||
struct page **pages = NULL;
|
||||
uint32_t i;
|
||||
uint32_t AllSize;
|
||||
uint32_t *MMU_Base;
|
||||
int ret;
|
||||
|
||||
/* cal src buf mmu info */
|
||||
SrcMemSize = rga_buf_size_cal(req->src.yrgb_addr, req->src.uv_addr, req->src.v_addr,
|
||||
req->src.format, req->src.vir_w, req->src.vir_h,
|
||||
&SrcStart);
|
||||
if(SrcMemSize == 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* cal dst buf mmu info */
|
||||
DstMemSize = rga_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr,
|
||||
req->dst.format, req->dst.vir_w, req->dst.vir_h,
|
||||
&DstStart);
|
||||
if(DstMemSize == 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* cal cmd buf mmu info */
|
||||
CMDMemSize = rga_mem_size_cal((uint32_t)rga_service.cmd_buff, RGA_CMD_BUF_SIZE, &CMDStart);
|
||||
if(CMDMemSize == 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
AllSize = SrcMemSize + DstMemSize + CMDMemSize;
|
||||
|
||||
pages = (struct page **)kmalloc(AllSize * sizeof(struct page *), GFP_KERNEL);
|
||||
if(pages == NULL) {
|
||||
pr_err("RGA MMU malloc pages mem failed");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
MMU_Base = (uint32_t *)kmalloc(AllSize * sizeof(uint32_t), GFP_KERNEL);
|
||||
if(pages == NULL) {
|
||||
pr_err("RGA MMU malloc MMU_Base point failed");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
for(i=0; i<CMDMemSize; i++) {
|
||||
MMU_Base[i] = virt_to_phys((uint32_t *)((CMDStart + i)<< PAGE_SHIFT));
|
||||
}
|
||||
|
||||
ret = rga_MapUserMemory(&pages[CMDMemSize], &MMU_Base[CMDMemSize], SrcStart, SrcMemSize);
|
||||
if (ret < 0) {
|
||||
pr_err("rga map src memory failed");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = rga_MapUserMemory(&pages[CMDMemSize + SrcMemSize], &MMU_Base[CMDMemSize + SrcMemSize], DstStart, DstMemSize);
|
||||
if (ret < 0) {
|
||||
pr_err("rga map dst memory failed");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* zsq
|
||||
* change the buf address in req struct
|
||||
* for the reason of lie to MMU
|
||||
*/
|
||||
req->mmu_info.base_addr = virt_to_phys(MMU_Base);
|
||||
|
||||
req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);
|
||||
req->src.uv_addr = (req->src.uv_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);
|
||||
req->src.v_addr = (req->src.v_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);
|
||||
|
||||
req->dst.yrgb_addr = (req->dst.yrgb_addr & (~PAGE_MASK)) | ((CMDMemSize + SrcMemSize) << PAGE_SHIFT);
|
||||
|
||||
/*record the malloc buf for the cmd end to release*/
|
||||
reg->MMU_base = MMU_Base;
|
||||
|
||||
if (pages != NULL) {
|
||||
/* Free the page table */
|
||||
kfree(pages);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
static int rga_mmu_info_pre_scale_mode(struct rga_reg *reg, struct rga_req *req)
|
||||
{
|
||||
int SrcMemSize, DstMemSize, CMDMemSize;
|
||||
uint32_t SrcStart, DstStart, CMDStart;
|
||||
struct page **pages = NULL;
|
||||
uint32_t i;
|
||||
uint32_t AllSize;
|
||||
uint32_t *MMU_Base, *MMU_p;
|
||||
int ret;
|
||||
|
||||
/* cal src buf mmu info */
|
||||
SrcMemSize = rga_buf_size_cal(req->src.yrgb_addr, req->src.uv_addr, req->src.v_addr,
|
||||
req->src.format, req->src.vir_w, req->src.vir_h,
|
||||
&SrcStart);
|
||||
if(SrcMemSize == 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* cal dst buf mmu info */
|
||||
DstMemSize = rga_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr,
|
||||
req->dst.format, req->dst.vir_w, req->dst.vir_h,
|
||||
&DstStart);
|
||||
if(DstMemSize == 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* cal cmd buf mmu info */
|
||||
CMDMemSize = rga_mem_size_cal((uint32_t)rga_service.cmd_buff, RGA_CMD_BUF_SIZE, &CMDStart);
|
||||
if(CMDMemSize == 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
AllSize = SrcMemSize + DstMemSize + CMDMemSize;
|
||||
|
||||
pages = (struct page **)kmalloc(AllSize * sizeof(struct page *), GFP_KERNEL);
|
||||
if(pages == NULL) {
|
||||
pr_err("RGA MMU malloc pages mem failed");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Allocate MMU Index mem
|
||||
* This mem release in run_to_done fun
|
||||
*/
|
||||
MMU_Base = (uint32_t *)kmalloc(AllSize * sizeof(uint32_t), GFP_KERNEL);
|
||||
if(pages == NULL) {
|
||||
pr_err("RGA MMU malloc MMU_Base point failed");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
for(i=0; i<CMDMemSize; i++) {
|
||||
MMU_Base[i] = virt_to_phys((uint32_t *)((CMDStart + i) << PAGE_SHIFT));
|
||||
}
|
||||
|
||||
|
||||
/* map src pages */
|
||||
ret = rga_MapUserMemory(&pages[CMDMemSize], &MMU_Base[CMDMemSize], SrcStart, SrcMemSize);
|
||||
if (ret < 0) {
|
||||
pr_err("rga map src memory failed");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
||||
if(req->dst.yrgb_addr >= 0xc0000000)
|
||||
{
|
||||
/* kernel space */
|
||||
MMU_p = MMU_Base + CMDMemSize + SrcMemSize;
|
||||
for(i=0; i<DstMemSize; i++)
|
||||
{
|
||||
MMU_p[i] = virt_to_phys((uint32_t *)((DstStart + i)<< PAGE_SHIFT));
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* user space */
|
||||
ret = rga_MapUserMemory(&pages[CMDMemSize + SrcMemSize], &MMU_Base[CMDMemSize + SrcMemSize], DstStart, DstMemSize);
|
||||
if (ret < 0)
|
||||
{
|
||||
pr_err("rga map dst memory failed");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
/* zsq
|
||||
* change the buf address in req struct
|
||||
* for the reason of lie to MMU
|
||||
*/
|
||||
req->mmu_info.base_addr = virt_to_phys(MMU_Base);
|
||||
|
||||
req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);
|
||||
req->src.uv_addr = (req->src.uv_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);
|
||||
req->src.v_addr = (req->src.v_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);
|
||||
|
||||
req->dst.yrgb_addr = (req->dst.yrgb_addr & (~PAGE_MASK)) | ((CMDMemSize + SrcMemSize) << PAGE_SHIFT);
|
||||
|
||||
/*record the malloc buf for the cmd end to release*/
|
||||
reg->MMU_base = MMU_Base;
|
||||
|
||||
if (pages != NULL) {
|
||||
/* Free the page table */
|
||||
kfree(pages);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int rga_mmu_info_update_palette_table_mode(struct rga_reg *reg, struct rga_req *req)
|
||||
{
|
||||
int SrcMemSize, DstMemSize, CMDMemSize;
|
||||
uint32_t SrcStart, CMDStart;
|
||||
struct page **pages = NULL;
|
||||
uint32_t i;
|
||||
uint32_t AllSize;
|
||||
uint32_t *MMU_Base;
|
||||
int ret;
|
||||
|
||||
/* cal src buf mmu info */
|
||||
SrcMemSize = rga_mem_size_cal(req->src.yrgb_addr, req->src.vir_w * req->src.vir_h, &SrcStart);
|
||||
if(SrcMemSize == 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* cal cmd buf mmu info */
|
||||
CMDMemSize = rga_mem_size_cal((uint32_t)rga_service.cmd_buff, RGA_CMD_BUF_SIZE, &CMDStart);
|
||||
if(CMDMemSize == 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
AllSize = SrcMemSize + DstMemSize + CMDMemSize;
|
||||
|
||||
pages = (struct page **)kmalloc(AllSize * sizeof(struct page *), GFP_KERNEL);
|
||||
if(pages == NULL) {
|
||||
pr_err("RGA MMU malloc pages mem failed");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
MMU_Base = (uint32_t *)kmalloc(AllSize * sizeof(uint32_t), GFP_KERNEL);
|
||||
if(pages == NULL) {
|
||||
pr_err("RGA MMU malloc MMU_Base point failed");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
for(i=0; i<CMDMemSize; i++) {
|
||||
MMU_Base[i] = virt_to_phys((uint32_t *)((CMDStart + i) << PAGE_SHIFT));
|
||||
}
|
||||
|
||||
ret = rga_MapUserMemory(&pages[CMDMemSize], &MMU_Base[CMDMemSize], SrcStart, SrcMemSize);
|
||||
if (ret < 0) {
|
||||
pr_err("rga map src memory failed");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* zsq
|
||||
* change the buf address in req struct
|
||||
* for the reason of lie to MMU
|
||||
*/
|
||||
req->mmu_info.base_addr = virt_to_phys(MMU_Base);
|
||||
|
||||
req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);
|
||||
|
||||
/*record the malloc buf for the cmd end to release*/
|
||||
reg->MMU_base = MMU_Base;
|
||||
|
||||
if (pages != NULL) {
|
||||
/* Free the page table */
|
||||
kfree(pages);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rga_mmu_info_update_patten_buff_mode(struct rga_reg *reg, struct rga_req *req)
|
||||
{
|
||||
int SrcMemSize, DstMemSize, CMDMemSize;
|
||||
uint32_t SrcStart, CMDStart;
|
||||
struct page **pages = NULL;
|
||||
uint32_t i;
|
||||
uint32_t AllSize;
|
||||
uint32_t *MMU_Base;
|
||||
int ret;
|
||||
|
||||
/* cal src buf mmu info */
|
||||
SrcMemSize = rga_mem_size_cal(req->pat.yrgb_addr, req->pat.vir_w * req->pat.vir_h * 4, &SrcStart);
|
||||
if(SrcMemSize == 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* cal cmd buf mmu info */
|
||||
CMDMemSize = rga_mem_size_cal((uint32_t)rga_service.cmd_buff, RGA_CMD_BUF_SIZE, &CMDStart);
|
||||
if(CMDMemSize == 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
AllSize = SrcMemSize + DstMemSize + CMDMemSize;
|
||||
|
||||
pages = (struct page **)kmalloc(AllSize * sizeof(struct page *), GFP_KERNEL);
|
||||
if(pages == NULL) {
|
||||
pr_err("RGA MMU malloc pages mem failed");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
MMU_Base = (uint32_t *)kmalloc(AllSize * sizeof(uint32_t), GFP_KERNEL);
|
||||
if(pages == NULL) {
|
||||
pr_err("RGA MMU malloc MMU_Base point failed");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
for(i=0; i<CMDMemSize; i++) {
|
||||
MMU_Base[i] = virt_to_phys((uint32_t *)((CMDStart + i) << PAGE_SHIFT));
|
||||
}
|
||||
|
||||
ret = rga_MapUserMemory(&pages[CMDMemSize], &MMU_Base[CMDMemSize], SrcStart, SrcMemSize);
|
||||
if (ret < 0) {
|
||||
pr_err("rga map src memory failed");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* zsq
|
||||
* change the buf address in req struct
|
||||
* for the reason of lie to MMU
|
||||
*/
|
||||
req->mmu_info.base_addr = virt_to_phys(MMU_Base);
|
||||
|
||||
req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);
|
||||
|
||||
/*record the malloc buf for the cmd end to release*/
|
||||
reg->MMU_base = MMU_Base;
|
||||
|
||||
if (pages != NULL) {
|
||||
/* Free the page table */
|
||||
kfree(pages);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rga_set_mmu_info(struct rga_reg *reg, struct rga_req *req)
|
||||
{
|
||||
int ret;
|
||||
|
||||
switch (req->render_mode) {
|
||||
case bitblt_mode :
|
||||
ret = rga_mmu_info_BitBlt_mode(reg, req);
|
||||
break;
|
||||
case color_palette_mode :
|
||||
ret = rga_mmu_info_color_palette_mode(reg, req);
|
||||
break;
|
||||
case color_fill_mode :
|
||||
ret = rga_mmu_info_color_fill_mode(reg, req);
|
||||
break;
|
||||
case line_point_drawing_mode :
|
||||
ret = rga_mmu_info_line_point_drawing_mode(reg, req);
|
||||
break;
|
||||
case blur_sharp_filter_mode :
|
||||
ret = rga_mmu_info_blur_sharp_filter_mode(reg, req);
|
||||
break;
|
||||
case pre_scaling_mode :
|
||||
ret = rga_mmu_info_pre_scale_mode(reg, req);
|
||||
break;
|
||||
case update_palette_table_mode :
|
||||
ret = rga_mmu_info_update_palette_table_mode(reg, req);
|
||||
break;
|
||||
case update_patten_buff_mode :
|
||||
ret = rga_mmu_info_update_patten_buff_mode(reg, req);
|
||||
break;
|
||||
default :
|
||||
ret = -1;
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
20
drivers/video/rockchip/rga/rga_mmu_info.h
Normal file
20
drivers/video/rockchip/rga/rga_mmu_info.h
Normal file
@@ -0,0 +1,20 @@
|
||||
#ifndef __RGA_MMU_INFO_H__
|
||||
#define __RGA_MMU_INFO_H__
|
||||
|
||||
#include "rga.h"
|
||||
|
||||
#ifndef MIN
|
||||
#define MIN(X, Y) ((X)<(Y)?(X):(Y))
|
||||
#endif
|
||||
|
||||
#ifndef MAX
|
||||
#define MAX(X, Y) ((X)>(Y)?(X):(Y))
|
||||
#endif
|
||||
|
||||
|
||||
int rga_set_mmu_info(struct rga_reg *reg, struct rga_req *req);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
1503
drivers/video/rockchip/rga/rga_reg_info.c
Normal file
1503
drivers/video/rockchip/rga/rga_reg_info.c
Normal file
File diff suppressed because it is too large
Load Diff
485
drivers/video/rockchip/rga/rga_reg_info.h
Normal file
485
drivers/video/rockchip/rga/rga_reg_info.h
Normal file
@@ -0,0 +1,485 @@
|
||||
#ifndef __REG_INFO_H__
|
||||
#define __REG_INFO_H__
|
||||
|
||||
|
||||
//#include "chip_register.h"
|
||||
|
||||
//#include "rga_struct.h"
|
||||
#include "rga.h"
|
||||
|
||||
#ifndef MIN
|
||||
#define MIN(X, Y) ((X)<(Y)?(X):(Y))
|
||||
#endif
|
||||
|
||||
#ifndef MAX
|
||||
#define MAX(X, Y) ((X)>(Y)?(X):(Y))
|
||||
#endif
|
||||
|
||||
#ifndef ABS
|
||||
#define ABS(X) (((X) < 0) ? (-(X)) : (X))
|
||||
#endif
|
||||
|
||||
#ifndef CLIP
|
||||
#define CLIP(x, a, b) ((x) < (a)) ? (a) : (((x) > (b)) ? (b) : (x))
|
||||
#endif
|
||||
|
||||
//RGA register map
|
||||
|
||||
//General Registers
|
||||
#define rRGA_SYS_CTRL (*(volatile uint32 *)(RGA_BASE + RGA_SYS_CTRL))
|
||||
#define rRGA_CMD_CTRL (*(volatile uint32 *)(RGA_BASE + RGA_CMD_CTRL))
|
||||
#define rRGA_CMD_ADDR (*(volatile uint32 *)(RGA_BASE + RGA_CMD_ADDR))
|
||||
#define rRGA_STATUS (*(volatile uint32 *)(RGA_BASE + RGA_STATUS))
|
||||
#define rRGA_INT (*(volatile uint32 *)(RGA_BASE + RGA_INT))
|
||||
#define rRGA_AXI_ID (*(volatile uint32 *)(RGA_BASE + RGA_AXI_ID))
|
||||
#define rRGA_MMU_STA_CTRL (*(volatile uint32 *)(RGA_BASE + RGA_MMU_STA_CTRL))
|
||||
#define rRGA_MMU_STA (*(volatile uint32 *)(RGA_BASE + RGA_MMU_STA))
|
||||
|
||||
//Command code start
|
||||
#define rRGA_MODE_CTRL (*(volatile uint32 *)(RGA_BASE + RGA_MODE_CTRL))
|
||||
|
||||
//Source Image Registers
|
||||
#define rRGA_SRC_Y_MST (*(volatile uint32 *)(RGA_BASE + RGA_SRC_Y_MST))
|
||||
#define rRGA_SRC_CB_MST (*(volatile uint32 *)(RGA_BASE + RGA_SRC_CB_MST))
|
||||
#define rRGA_MASK_READ_MST (*(volatile uint32 *)(RGA_BASE + RGA_MASK_READ_MST)) //repeat
|
||||
#define rRGA_SRC_CR_MST (*(volatile uint32 *)(RGA_BASE + RGA_SRC_CR_MST))
|
||||
#define rRGA_SRC_VIR_INFO (*(volatile uint32 *)(RGA_BASE + RGA_SRC_VIR_INFO))
|
||||
#define rRGA_SRC_ACT_INFO (*(volatile uint32 *)(RGA_BASE + RGA_SRC_ACT_INFO))
|
||||
#define rRGA_SRC_X_PARA (*(volatile uint32 *)(RGA_BASE + RGA_SRC_X_PARA))
|
||||
#define rRGA_SRC_Y_PARA (*(volatile uint32 *)(RGA_BASE + RGA_SRC_Y_PARA))
|
||||
#define rRGA_SRC_TILE_XINFO (*(volatile uint32 *)(RGA_BASE + RGA_SRC_TILE_XINFO))
|
||||
#define rRGA_SRC_TILE_YINFO (*(volatile uint32 *)(RGA_BASE + RGA_SRC_TILE_YINFO))
|
||||
#define rRGA_SRC_TILE_H_INCR (*(volatile uint32 *)(RGA_BASE + RGA_SRC_TILE_H_INCR))
|
||||
#define rRGA_SRC_TILE_V_INCR (*(volatile uint32 *)(RGA_BASE + RGA_SRC_TILE_V_INCR))
|
||||
#define rRGA_SRC_TILE_OFFSETX (*(volatile uint32 *)(RGA_BASE + RGA_SRC_TILE_OFFSETX))
|
||||
#define rRGA_SRC_TILE_OFFSETY (*(volatile uint32 *)(RGA_BASE + RGA_SRC_TILE_OFFSETY))
|
||||
#define rRGA_SRC_BG_COLOR (*(volatile uint32 *)(RGA_BASE + RGA_SRC_BG_COLOR))
|
||||
#define rRGA_SRC_FG_COLOR (*(volatile uint32 *)(RGA_BASE + RGA_SRC_FG_COLOR))
|
||||
#define rRGA_LINE_DRAWING_COLOR (*(volatile uint32 *)(RGA_BASE + RGA_LINE_DRAWING_COLOR)) //repeat
|
||||
#define rRGA_SRC_TR_COLOR0 (*(volatile uint32 *)(RGA_BASE + RGA_SRC_TR_COLOR0))
|
||||
#define rRGA_CP_GR_A (*(volatile uint32 *)(RGA_BASE + RGA_CP_GR_A)) //repeat
|
||||
#define rRGA_SRC_TR_COLOR1 (*(volatile uint32 *)(RGA_BASE + RGA_SRC_TR_COLOR1))
|
||||
#define rRGA_CP_GR_B (*(volatile uint32 *)(RGA_BASE + RGA_CP_GR_B)) //repeat
|
||||
|
||||
#define rRGA_LINE_DRAW (*(volatile uint32 *)(RGA_BASE + RGA_LINE_DRAW))
|
||||
#define rRGA_PAT_START_POINT (*(volatile uint32 *)(RGA_BASE + RGA_PAT_START_POINT)) //repeat
|
||||
|
||||
//Destination Image Registers
|
||||
#define rRGA_DST_MST (*(volatile uint32 *)(RGA_BASE + RGA_DST_MST))
|
||||
#define rRGA_LUT_MST (*(volatile uint32 *)(RGA_BASE + RGA_LUT_MST)) //repeat
|
||||
#define rRGA_PAT_MST (*(volatile uint32 *)(RGA_BASE + RGA_PAT_MST)) //repeat
|
||||
#define rRGA_LINE_DRAWING_MST (*(volatile uint32 *)(RGA_BASE + RGA_LINE_DRAWING_MST)) //repeat
|
||||
|
||||
#define rRGA_DST_VIR_INFO (*(volatile uint32 *)(RGA_BASE + RGA_DST_VIR_INFO))
|
||||
|
||||
#define rRGA_DST_CTR_INFO (*(volatile uint32 *)(RGA_BASE + RGA_DST_CTR_INFO))
|
||||
#define rRGA_LINE_DRAW_XY_INFO (*(volatile uint32 *)(RGA_BASE + RGA_LINE_DRAW_XY_INFO)) //repeat
|
||||
|
||||
//Alpha/ROP Registers
|
||||
#define rRGA_ALPHA_CON (*(volatile uint32 *)(RGA_BASE + RGA_ALPHA_CON))
|
||||
#define rRGA_FADING_CON (*(volatile uint32 *)(RGA_BASE + RGA_FADING_CON))
|
||||
|
||||
#define rRGA_PAT_CON (*(volatile uint32 *)(RGA_BASE + RGA_PAT_CON))
|
||||
#define rRGA_DST_VIR_WIDTH_PIX (*(volatile uint32 *)(RGA_BASE + RGA_DST_VIR_WIDTH_PIX)) //repeat
|
||||
|
||||
#define rRGA_ROP_CON0 (*(volatile uint32 *)(RGA_BASE + RGA_ROP_CON0))
|
||||
#define rRGA_CP_GR_G (*(volatile uint32 *)(RGA_BASE + RGA_CP_GR_G)) //repeat
|
||||
#define rRGA_PRESCL_CB_MST (*(volatile uint32 *)(RGA_BASE + RGA_PRESCL_CB_MST)) //repeat
|
||||
|
||||
#define rRGA_ROP_CON1 (*(volatile uint32 *)(RGA_BASE + RGA_ROP_CON1))
|
||||
#define rRGA_CP_GR_R (*(volatile uint32 *)(RGA_BASE + RGA_CP_GR_R)) //repeat
|
||||
#define rRGA_PRESCL_CR_MST (*(volatile uint32 *)(RGA_BASE + RGA_PRESCL_CR_MST)) //repeat
|
||||
|
||||
//MMU Register
|
||||
#define rRGA_MMU_CTRL (*(volatile uint32 *)(RGA_BASE + RGA_MMU_CTRL))
|
||||
|
||||
|
||||
|
||||
|
||||
//-----------------------------------------------------------------
|
||||
//reg detail definition
|
||||
//-----------------------------------------------------------------
|
||||
/*RGA_SYS_CTRL*/
|
||||
#define m_RGA_SYS_CTRL_CMD_MODE ( 1<<2 )
|
||||
#define m_RGA_SYS_CTRL_OP_ST_SLV ( 1<<1 )
|
||||
#define m_RGA_sys_CTRL_SOFT_RESET ( 1<<0 )
|
||||
|
||||
#define s_RGA_SYS_CTRL_CMD_MODE(x) ( (x&0x1)<<2 )
|
||||
#define s_RGA_SYS_CTRL_OP_ST_SLV(x) ( (x&0x1)<<1 )
|
||||
#define s_RGA_sys_CTRL_SOFT_RESET(x) ( (x&0x1)<<0 )
|
||||
|
||||
|
||||
/*RGA_CMD_CTRL*/
|
||||
#define m_RGA_CMD_CTRL_CMD_INCR_NUM ( 0x3ff<<3 )
|
||||
#define m_RGA_CMD_CTRL_CMD_STOP_MODE ( 1<<2 )
|
||||
#define m_RGA_CMD_CTRL_CMD_INCR_VALID ( 1<<1 )
|
||||
#define m_RGA_CMD_CTRL_CMD_LINE_FET_ST ( 1<<0 )
|
||||
|
||||
#define s_RGA_CMD_CTRL_CMD_INCR_NUM(x) ( (x&0x3ff)<<3 )
|
||||
#define s_RGA_CMD_CTRL_CMD_STOP_MODE(x) ( (x&0x1)<<2 )
|
||||
#define s_RGA_CMD_CTRL_CMD_INCR_VALID(x) ( (x&0x1)<<1 )
|
||||
#define s_RGA_CMD_CTRL_CMD_LINE_FET_ST(x) ( (x*0x1)<<0 )
|
||||
|
||||
|
||||
/*RGA_STATUS*/
|
||||
#define m_RGA_CMD_STATUS_CMD_TOTAL_NUM ( 0xfff<<20 )
|
||||
#define m_RGA_CMD_STATUS_NOW_CMD_NUM ( 0xfff<<8 )
|
||||
#define m_RGA_CMD_STATUS_ENGINE_STATUS ( 1<<0 )
|
||||
|
||||
|
||||
/*RGA_INT*/
|
||||
#define m_RGA_INT_ALL_CMD_DONE_INT_EN ( 1<<10 )
|
||||
#define m_RGA_INT_MMU_INT_EN ( 1<<9 )
|
||||
#define m_RGA_INT_ERROR_INT_EN ( 1<<8 )
|
||||
#define m_RGA_INT_NOW_CMD_DONE_INT_CLEAR ( 1<<7 )
|
||||
#define m_RGA_INT_ALL_CMD_DONE_INT_CLEAR ( 1<<6 )
|
||||
#define m_RGA_INT_MMU_INT_CLEAR ( 1<<5 )
|
||||
#define m_RGA_INT_ERROR_INT_CLEAR ( 1<<4 )
|
||||
#define m_RGA_INT_NOW_CMD_DONE_INT_FLAG ( 1<<3 )
|
||||
#define m_RGA_INT_ALL_CMD_DONE_INT_FLAG ( 1<<2 )
|
||||
#define m_RGA_INT_MMU_INT_FLAG ( 1<<1 )
|
||||
#define m_RGA_INT_ERROR_INT_FLAG ( 1<<0 )
|
||||
|
||||
#define s_RGA_INT_ALL_CMD_DONE_INT_EN(x) ( (x&0x1)<<10 )
|
||||
#define s_RGA_INT_MMU_INT_EN(x) ( (x&0x1)<<9 )
|
||||
#define s_RGA_INT_ERROR_INT_EN(x) ( (x&0x1)<<8 )
|
||||
#define s_RGA_INT_NOW_CMD_DONE_INT_CLEAR(x) ( (x&0x1)<<7 )
|
||||
#define s_RGA_INT_ALL_CMD_DONE_INT_CLEAR(x) ( (x&0x1)<<6 )
|
||||
#define s_RGA_INT_MMU_INT_CLEAR(x) ( (x&0x1)<<5 )
|
||||
#define s_RGA_INT_ERROR_INT_CLEAR(x) ( (x&0x1)<<4 )
|
||||
|
||||
|
||||
/*RGA_AXI_ID*/
|
||||
#define m_RGA_AXI_ID_MMU_READ ( 3<<30 )
|
||||
#define m_RGA_AXI_ID_MMU_WRITE ( 3<<28 )
|
||||
#define m_RGA_AXI_ID_MASK_READ ( 0xf<<24 )
|
||||
#define m_RGA_AXI_ID_CMD_FET ( 0xf<<20 )
|
||||
#define m_RGA_AXI_ID_DST_WRITE ( 0xf<<16 )
|
||||
#define m_RGA_AXI_ID_DST_READ ( 0xf<<12 )
|
||||
#define m_RGA_AXI_ID_SRC_CR_READ ( 0xf<<8 )
|
||||
#define m_RGA_AXI_ID_SRC_CB_READ ( 0xf<<4 )
|
||||
#define m_RGA_AXI_ID_SRC_Y_READ ( 0xf<<0 )
|
||||
|
||||
#define s_RGA_AXI_ID_MMU_READ(x) ( (x&0x3)<<30 )
|
||||
#define s_RGA_AXI_ID_MMU_WRITE(x) ( (x&0x3)<<28 )
|
||||
#define s_RGA_AXI_ID_MASK_READ(x) ( (x&0xf)<<24 )
|
||||
#define s_RGA_AXI_ID_CMD_FET(x) ( (x&0xf)<<20 )
|
||||
#define s_RGA_AXI_ID_DST_WRITE(x) ( (x&0xf)<<16 )
|
||||
#define s_RGA_AXI_ID_DST_READ(x) ( (x&0xf)<<12 )
|
||||
#define s_RGA_AXI_ID_SRC_CR_READ(x) ( (x&0xf)<<8 )
|
||||
#define s_RGA_AXI_ID_SRC_CB_READ(x) ( (x&0xf)<<4 )
|
||||
#define s_RGA_AXI_ID_SRC_Y_READ(x) ( (x&0xf)<<0 )
|
||||
|
||||
|
||||
/*RGA_MMU_STA_CTRL*/
|
||||
#define m_RGA_MMU_STA_CTRL_TLB_STA_CLEAR ( 1<<3 )
|
||||
#define m_RGA_MMU_STA_CTRL_TLB_STA_RESUME ( 1<<2 )
|
||||
#define m_RGA_MMU_STA_CTRL_TLB_STA_PAUSE ( 1<<1 )
|
||||
#define m_RGA_MMU_STA_CTRL_TLB_STA_EN ( 1<<0 )
|
||||
|
||||
#define s_RGA_MMU_STA_CTRL_TLB_STA_CLEAR(x) ( (x&0x1)<<3 )
|
||||
#define s_RGA_MMU_STA_CTRL_TLB_STA_RESUME(x) ( (x&0x1)<<2 )
|
||||
#define s_RGA_MMU_STA_CTRL_TLB_STA_PAUSE(x) ( (x&0x1)<<1 )
|
||||
#define s_RGA_MMU_STA_CTRL_TLB_STA_EN(x) ( (x&0x1)<<0 )
|
||||
|
||||
|
||||
|
||||
/* RGA_MODE_CTRL */
|
||||
#define m_RGA_MODE_CTRL_2D_RENDER_MODE ( 7<<0 )
|
||||
#define m_RGA_MODE_CTRL_SRC_RGB_PACK ( 1<<3 )
|
||||
#define m_RGA_MODE_CTRL_SRC_FORMAT ( 15<<4 )
|
||||
#define m_RGA_MODE_CTRL_SRC_RB_SWAP ( 1<<8 )
|
||||
#define m_RGA_MODE_CTRL_SRC_ALPHA_SWAP ( 1<<9 )
|
||||
#define m_RGA_MODE_CTRL_SRC_UV_SWAP_MODE ( 1<<10 )
|
||||
#define m_RGA_MODE_CTRL_YUV2RGB_CON_MODE ( 3<<11 )
|
||||
#define m_RGA_MODE_CTRL_SRC_TRANS_MODE (0x1f<<13 )
|
||||
#define m_RGA_MODE_CTRL_SRC_TR_MODE ( 1<<13 )
|
||||
#define m_RGA_MODE_CTRL_SRC_TR_R_EN ( 1<<14 )
|
||||
#define m_RGA_MODE_CTRL_SRC_TR_G_EN ( 1<<15 )
|
||||
#define m_RGA_MODE_CTRL_SRC_TR_B_EN ( 1<<16 )
|
||||
#define m_RGA_MODE_CTRL_SRC_TR_A_EN ( 1<<17 )
|
||||
#define m_RGA_MODE_CTRL_ROTATE_MODE ( 3<<18 )
|
||||
#define m_RGA_MODE_CTRL_SCALE_MODE ( 3<<20 )
|
||||
#define m_RGA_MODE_CTRL_PAT_SEL ( 1<<22 )
|
||||
#define m_RGA_MODE_CTRL_DST_FORMAT ( 3<<23 )
|
||||
#define m_RGA_MODE_CTRL_DST_RGB_PACK ( 1<<25 )
|
||||
#define m_RGA_MODE_CTRL_DST_RB_SWAP ( 1<<26 )
|
||||
#define m_RGA_MODE_CTRL_DST_ALPHA_SWAP ( 1<<27 )
|
||||
#define m_RGA_MODE_CTRL_LUT_ENDIAN_MODE ( 1<<28 )
|
||||
#define m_RGA_MODE_CTRL_CMD_INT_ENABLE ( 1<<29 )
|
||||
#define m_RGA_MODE_CTRL_ZERO_MODE_ENABLE ( 1<<30 )
|
||||
#define m_RGA_MODE_CTRL_DST_ALPHA_ENABLE ( 1<<30 )
|
||||
|
||||
|
||||
|
||||
#define s_RGA_MODE_CTRL_2D_RENDER_MODE(x) ( (x&0x7)<<0 )
|
||||
#define s_RGA_MODE_CTRL_SRC_RGB_PACK(x) ( (x&0x1)<<3 )
|
||||
#define s_RGA_MODE_CTRL_SRC_FORMAT(x) ( (x&0xf)<<4 )
|
||||
#define s_RGA_MODE_CTRL_SRC_RB_SWAP(x) ( (x&0x1)<<8 )
|
||||
#define s_RGA_MODE_CTRL_SRC_ALPHA_SWAP(x) ( (x&0x1)<<9 )
|
||||
#define s_RGA_MODE_CTRL_SRC_UV_SWAP_MODE(x) ( (x&0x1)<<10 )
|
||||
#define s_RGA_MODE_CTRL_YUV2RGB_CON_MODE(x) ( (x&0x3)<<11 )
|
||||
#define s_RGA_MODE_CTRL_SRC_TRANS_MODE(x) ( (x&0x1f)<<13 )
|
||||
#define s_RGA_MODE_CTRL_SRC_TR_MODE(x) ( (x&0x1)<<13 )
|
||||
#define s_RGA_MODE_CTRL_SRC_TR_R_EN(x) ( (x&0x1)<<14 )
|
||||
#define s_RGA_MODE_CTRL_SRC_TR_G_EN(x) ( (x&0x1)<<15 )
|
||||
#define s_RGA_MODE_CTRL_SRC_TR_B_EN(x) ( (x&0x1)<<16 )
|
||||
#define s_RGA_MODE_CTRL_SRC_TR_A_EN(x) ( (x&0x1)<<17 )
|
||||
#define s_RGA_MODE_CTRL_ROTATE_MODE(x) ( (x&0x3)<<18 )
|
||||
#define s_RGA_MODE_CTRL_SCALE_MODE(x) ( (x&0x3)<<20 )
|
||||
#define s_RGA_MODE_CTRL_PAT_SEL(x) ( (x&0x1)<<22 )
|
||||
#define s_RGA_MODE_CTRL_DST_FORMAT(x) ( (x&0x3)<<23 )
|
||||
#define s_RGA_MODE_CTRL_DST_RGB_PACK(x) ( (x&0x1)<<25 )
|
||||
#define s_RGA_MODE_CTRL_DST_RB_SWAP(x) ( (x&0x1)<<26 )
|
||||
#define s_RGA_MODE_CTRL_DST_ALPHA_SWAP(x) ( (x&0x1)<<27 )
|
||||
#define s_RGA_MODE_CTRL_LUT_ENDIAN_MODE(x) ( (x&0x1)<<28 )
|
||||
#define s_RGA_MODE_CTRL_CMD_INT_ENABLE(x) ( (x&0x1)<<29 )
|
||||
#define s_RGA_MODE_CTRL_ZERO_MODE_ENABLE(x) ( (x&0x1)<<30 )
|
||||
#define s_RGA_MODE_CTRL_DST_ALPHA_ENABLE(x) ( (x&0x1)<<31 )
|
||||
|
||||
|
||||
|
||||
/* RGA_LINE_DRAW */
|
||||
#define m_RGA_LINE_DRAW_MAJOR_WIDTH ( 0x7ff<<0 )
|
||||
#define m_RGA_LINE_DRAW_LINE_DIRECTION ( 0x1<<11)
|
||||
#define m_RGA_LINE_DRAW_LINE_WIDTH ( 0xf<<12)
|
||||
#define m_RGA_LINE_DRAW_INCR_VALUE ( 0xfff<<16)
|
||||
#define m_RGA_LINE_DRAW_DIR_MAJOR ( 0x1<<28)
|
||||
#define m_RGA_LINE_DRAW_DIR_SEMI_MAJOR ( 0x1<<29)
|
||||
#define m_RGA_LINE_DRAW_LAST_POINT ( 0x1<<30)
|
||||
#define m_RGA_LINE_DRAW_ANTI_ALISING ( 0x1<<31)
|
||||
|
||||
#define s_RGA_LINE_DRAW_MAJOR_WIDTH(x) (((x)&0x7ff)<<0 )
|
||||
#define s_RGA_LINE_DRAW_LINE_DIRECTION(x) ( ((x)&0x1)<<11)
|
||||
#define s_RGA_LINE_DRAW_LINE_WIDTH(x) ( ((x)&0xf)<<12)
|
||||
#define s_RGA_LINE_DRAW_INCR_VALUE(x) (((x)&0xfff)<<16)
|
||||
#define s_RGA_LINE_DRAW_DIR_MAJOR(x) ( ((x)&0x1)<<28)
|
||||
#define s_RGA_LINE_DRAW_DIR_SEMI_MAJOR(x) ( ((x)&0x1)<<29)
|
||||
#define s_RGA_LINE_DRAW_LAST_POINT(x) ( ((x)&0x1)<<30)
|
||||
#define s_RGA_LINE_DRAW_ANTI_ALISING(x) ( ((x)&0x1)<<31)
|
||||
|
||||
|
||||
/* RGA_ALPHA_CON */
|
||||
#define m_RGA_ALPHA_CON_ENABLE ( 0x1<<0 )
|
||||
#define m_RGA_ALPHA_CON_A_OR_R_SEL ( 0x1<<1 )
|
||||
#define m_RGA_ALPHA_CON_ALPHA_MODE ( 0x3<<2 )
|
||||
#define m_RGA_ALPHA_CON_PD_MODE ( 0xf<<4 )
|
||||
#define m_RGA_ALPHA_CON_SET_CONSTANT_VALUE (0xff<<8 )
|
||||
#define m_RGA_ALPHA_CON_PD_M_SEL ( 0x1<<16)
|
||||
#define m_RGA_ALPHA_CON_FADING_ENABLE ( 0x1<<17)
|
||||
#define m_RGA_ALPHA_CON_ROP_MODE_SEL ( 0x3<<18)
|
||||
#define m_RGA_ALPHA_CON_CAL_MODE_SEL ( 0x1<<28)
|
||||
#define m_RGA_ALPHA_CON_DITHER_ENABLE ( 0x1<<29)
|
||||
#define m_RGA_ALPHA_CON_GRADIENT_CAL_MODE ( 0x1<<30)
|
||||
#define m_RGA_ALPHA_CON_AA_SEL ( 0x1<<31)
|
||||
|
||||
#define s_RGA_ALPHA_CON_ENABLE(x) ( (x&0x1)<<0 )
|
||||
#define s_RGA_ALPHA_CON_A_OR_R_SEL(x) ( (x&0x1)<<1 )
|
||||
#define s_RGA_ALPHA_CON_ALPHA_MODE(x) ( (x&0x3)<<2 )
|
||||
#define s_RGA_ALPHA_CON_PD_MODE(x) ( (x&0xf)<<4 )
|
||||
#define s_RGA_ALPHA_CON_SET_CONSTANT_VALUE(x) ((x&0xff)<<8 )
|
||||
#define s_RGA_ALPHA_CON_PD_M_SEL(x) ( (x&0x1)<<16)
|
||||
#define s_RGA_ALPHA_CON_FADING_ENABLE(x) ( (x&0x1)<<17)
|
||||
#define s_RGA_ALPHA_CON_ROP_MODE_SEL(x) ( (x&0x3)<<18)
|
||||
#define s_RGA_ALPHA_CON_CAL_MODE_SEL(x) ( (x&0x1)<<28)
|
||||
#define s_RGA_ALPHA_CON_DITHER_ENABLE(x) ( (x&0x1)<<29)
|
||||
#define s_RGA_ALPHA_CON_GRADIENT_CAL_MODE(x) ( (x&0x1)<<30)
|
||||
#define s_RGA_ALPHA_CON_AA_SEL(x) ( (x&0x1)<<31)
|
||||
|
||||
|
||||
/* blur sharp mode */
|
||||
#define m_RGA_BLUR_SHARP_FILTER_MODE ( 0x1<<25 )
|
||||
#define m_RGA_BLUR_SHARP_FILTER_TYPE ( 0x3<<26 )
|
||||
|
||||
#define s_RGA_BLUR_SHARP_FILTER_MODE(x) ( (x&0x1)<<25 )
|
||||
#define s_RGA_BLUR_SHARP_FILTER_TYPE(x) ( (x&0x3)<<26 )
|
||||
|
||||
|
||||
/* pre scale mode */
|
||||
#define m_RGA_PRE_SCALE_HOR_RATIO ( 0x3 <<20 )
|
||||
#define m_RGA_PRE_SCALE_VER_RATIO ( 0x3 <<22 )
|
||||
#define m_RGA_PRE_SCALE_OUTPUT_FORMAT ( 0x1 <<24 )
|
||||
|
||||
#define s_RGA_PRE_SCALE_HOR_RATIO(x) ( (x&0x3) <<20 )
|
||||
#define s_RGA_PRE_SCALE_VER_RATIO(x) ( (x&0x3) <<22 )
|
||||
#define s_RGA_PRE_SCALE_OUTPUT_FORMAT(x) ( (x&0x1) <<24 )
|
||||
|
||||
|
||||
|
||||
/* RGA_MMU_CTRL*/
|
||||
#define m_RGA_MMU_CTRL_TLB_ADDR ( 0xffffffff<<0)
|
||||
#define m_RGA_MMU_CTRL_PAGE_TABLE_SIZE ( 0x3<<4 )
|
||||
#define m_RGA_MMU_CTRL_MMU_ENABLE ( 0x1<<0 )
|
||||
#define m_RGA_MMU_CTRL_SRC_FLUSH ( 0x1<<1 )
|
||||
#define m_RGA_MMU_CTRL_DST_FLUSH ( 0x1<<2 )
|
||||
#define m_RGA_MMU_CTRL_CMD_CHAN_FLUSH ( 0x1<<3 )
|
||||
|
||||
#define s_RGA_MMU_CTRL_TLB_ADDR(x) ((x&0xffffffff))
|
||||
#define s_RGA_MMU_CTRL_PAGE_TABLE_SIZE(x) ((x&0x3)<<4)
|
||||
#define s_RGA_MMU_CTRL_MMU_ENABLE(x) ((x&0x1)<<0)
|
||||
#define s_RGA_MMU_CTRL_SRC_FLUSH(x) ((x&0x1)<<1)
|
||||
#define s_RGA_MMU_CTRL_DST_FLUSH(x) ((x&0x1)<<2)
|
||||
#define s_RGA_MMU_CTRL_CMD_CHAN_FLUSH(x) ((x&0x1)<<3)
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
#define RGA_MODE_CTRL_OFFSET 0x0
|
||||
#define RGA_SRC_Y_MST_OFFSET 0x4
|
||||
#define RGA_SRC_CB_MST_OFFSET 0x8
|
||||
#define RGA_SRC_CR_MST_OFFSET 0xc
|
||||
#define RGA_SRC_VIR_INFO_OFFSET 0x10
|
||||
#define RGA_SRC_ACT_INFO_OFFSET 0x14
|
||||
#define RGA_SRC_X_PARA_OFFSET 0x18
|
||||
#define RGA_SRC_Y_PARA_OFFSET 0x1c
|
||||
#define RGA_SRC_TILE_XINFO_OFFSET 0x20
|
||||
#define RGA_SRC_TILE_YINFO_OFFSET 0x24
|
||||
#define RGA_SRC_TILE_H_INCR_OFFSET 0x28
|
||||
#define RGA_SRC_TILE_V_INCR_OFFSET 0x2c
|
||||
#define RGA_SRC_TILE_OFFSETX_OFFSET 0x30
|
||||
#define RGA_SRC_TILE_OFFSETY_OFFSET 0x34
|
||||
#define RGA_SRC_BG_COLOR_OFFSET 0x38
|
||||
|
||||
#define RGA_SRC_FG_COLOR_OFFSET 0x3c
|
||||
#define RGA_LINE_DRAWING_COLOR_OFFSET 0x3c
|
||||
|
||||
#define RGA_SRC_TR_COLOR0_OFFSET 0x40
|
||||
#define RGA_CP_GR_A_OFFSET 0x40 //repeat
|
||||
|
||||
#define RGA_SRC_TR_COLOR1_OFFSET 0x44
|
||||
#define RGA_CP_GR_B_OFFSET 0x44 //repeat
|
||||
|
||||
#define RGA_LINE_DRAW_OFFSET 0x48
|
||||
#define RGA_PAT_START_POINT_OFFSET 0x48 //repeat
|
||||
|
||||
#define RGA_DST_MST_OFFSET 0x4c
|
||||
#define RGA_LUT_MST_OFFSET 0x4c //repeat
|
||||
#define RGA_PAT_MST_OFFSET 0x4c //repeat
|
||||
#define RGA_LINE_DRAWING_MST_OFFSET 0x4c //repeat
|
||||
|
||||
#define RGA_DST_VIR_INFO_OFFSET 0x50
|
||||
|
||||
#define RGA_DST_CTR_INFO_OFFSET 0x54
|
||||
#define RGA_LINE_DRAW_XY_INFO_OFFSET 0x54 //repeat
|
||||
|
||||
#define RGA_ALPHA_CON_OFFSET 0x58
|
||||
#define RGA_FADING_CON_OFFSET 0x5c
|
||||
|
||||
#define RGA_PAT_CON_OFFSET 0x60
|
||||
#define RGA_LINE_DRAWING_WIDTH_OFFSET 0x60 //repeat
|
||||
|
||||
#define RGA_ROP_CON0_OFFSET 0x64
|
||||
#define RGA_CP_GR_G_OFFSET 0x64 //repeat
|
||||
#define RGA_PRESCL_CB_MST_OFFSET 0x64 //repeat
|
||||
|
||||
#define RGA_ROP_CON1_OFFSET 0x68
|
||||
#define RGA_CP_GR_R_OFFSET 0x68 //repeat
|
||||
#define RGA_PRESCL_CR_MST_OFFSET 0x68 //repeat
|
||||
|
||||
#define RGA_MMU_CTRL_OFFSET 0x6c
|
||||
|
||||
|
||||
#define RGA_SYS_CTRL_OFFSET 0x000
|
||||
#define RGA_CMD_CTRL_OFFSET 0x004
|
||||
#define RGA_CMD_ADDR_OFFSET 0x008
|
||||
#define RGA_STATUS_OFFSET 0x00c
|
||||
#define RGA_INT_OFFSET 0x010
|
||||
#define RGA_AXI_ID_OFFSET 0x014
|
||||
#define RGA_MMU_STA_CTRL_OFFSET 0x018
|
||||
#define RGA_MMU_STA_OFFSET 0x01c
|
||||
*/
|
||||
//hxx
|
||||
|
||||
#define RGA_SYS_CTRL_OFFSET (RGA_SYS_CTRL-0x100)
|
||||
#define RGA_CMD_CTRL_OFFSET (RGA_CMD_CTRL-0x100)
|
||||
#define RGA_CMD_ADDR_OFFSET (RGA_CMD_ADDR-0x100)
|
||||
#define RGA_STATUS_OFFSET (RGA_STATUS-0x100)
|
||||
#define RGA_INT_OFFSET (RGA_INT-0x100)
|
||||
#define RGA_AXI_ID_OFFSET (RGA_AXI_ID-0x100)
|
||||
#define RGA_MMU_STA_CTRL_OFFSET (RGA_MMU_STA_CTRL-0x100)
|
||||
#define RGA_MMU_STA_OFFSET (RGA_MMU_STA-0x100)
|
||||
|
||||
#define RGA_MODE_CTRL_OFFSET (RGA_MODE_CTRL-0x100)
|
||||
#define RGA_SRC_Y_MST_OFFSET (RGA_SRC_Y_MST-0x100)
|
||||
#define RGA_SRC_CB_MST_OFFSET (RGA_SRC_CB_MST-0x100)
|
||||
#define RGA_SRC_CR_MST_OFFSET (RGA_SRC_CR_MST-0x100)
|
||||
#define RGA_SRC_VIR_INFO_OFFSET (RGA_SRC_VIR_INFO-0x100)
|
||||
#define RGA_SRC_ACT_INFO_OFFSET (RGA_SRC_ACT_INFO-0x100)
|
||||
#define RGA_SRC_X_PARA_OFFSET (RGA_SRC_X_PARA-0x100)
|
||||
#define RGA_SRC_Y_PARA_OFFSET (RGA_SRC_Y_PARA-0x100)
|
||||
#define RGA_SRC_TILE_XINFO_OFFSET (RGA_SRC_TILE_XINFO-0x100)
|
||||
#define RGA_SRC_TILE_YINFO_OFFSET (RGA_SRC_TILE_YINFO-0x100)
|
||||
#define RGA_SRC_TILE_H_INCR_OFFSET (RGA_SRC_TILE_H_INCR-0x100)
|
||||
#define RGA_SRC_TILE_V_INCR_OFFSET (RGA_SRC_TILE_V_INCR-0x100)
|
||||
#define RGA_SRC_TILE_OFFSETX_OFFSET (RGA_SRC_TILE_OFFSETX-0x100)
|
||||
#define RGA_SRC_TILE_OFFSETY_OFFSET (RGA_SRC_TILE_OFFSETY-0x100)
|
||||
#define RGA_SRC_BG_COLOR_OFFSET (RGA_SRC_BG_COLOR-0x100)
|
||||
|
||||
#define RGA_SRC_FG_COLOR_OFFSET (RGA_SRC_FG_COLOR-0x100)
|
||||
#define RGA_LINE_DRAWING_COLOR_OFFSET (RGA_LINE_DRAWING_COLOR-0x100)
|
||||
|
||||
#define RGA_SRC_TR_COLOR0_OFFSET (RGA_SRC_TR_COLOR0-0x100)
|
||||
#define RGA_CP_GR_A_OFFSET (RGA_CP_GR_A-0x100) //repeat
|
||||
|
||||
#define RGA_SRC_TR_COLOR1_OFFSET (RGA_SRC_TR_COLOR1-0x100)
|
||||
#define RGA_CP_GR_B_OFFSET (RGA_CP_GR_B-0x100) //repeat
|
||||
|
||||
#define RGA_LINE_DRAW_OFFSET (RGA_LINE_DRAW-0x100)
|
||||
#define RGA_PAT_START_POINT_OFFSET (RGA_PAT_START_POINT-0x100) //repeat
|
||||
|
||||
#define RGA_DST_MST_OFFSET (RGA_DST_MST-0x100)
|
||||
#define RGA_LUT_MST_OFFSET (RGA_LUT_MST-0x100) //repeat
|
||||
#define RGA_PAT_MST_OFFSET (RGA_PAT_MST-0x100) //repeat
|
||||
#define RGA_LINE_DRAWING_MST_OFFSET (RGA_LINE_DRAWING_MST-0x100) //repeat
|
||||
|
||||
#define RGA_DST_VIR_INFO_OFFSET (RGA_DST_VIR_INFO-0x100)
|
||||
|
||||
#define RGA_DST_CTR_INFO_OFFSET (RGA_DST_CTR_INFO-0x100)
|
||||
#define RGA_LINE_DRAW_XY_INFO_OFFSET (RGA_LINE_DRAW_XY_INFO-0x100) //repeat
|
||||
|
||||
#define RGA_ALPHA_CON_OFFSET (RGA_ALPHA_CON-0x100)
|
||||
|
||||
#define RGA_PAT_CON_OFFSET (RGA_PAT_CON-0x100)
|
||||
#define RGA_LINE_DRAWING_WIDTH_OFFSET (RGA_DST_VIR_WIDTH_PIX-0x100) //repeat
|
||||
|
||||
#define RGA_ROP_CON0_OFFSET (RGA_ROP_CON0-0x100)
|
||||
#define RGA_CP_GR_G_OFFSET (RGA_CP_GR_G-0x100) //repeat
|
||||
#define RGA_PRESCL_CB_MST_OFFSET (RGA_PRESCL_CB_MST-0x100) //repeat
|
||||
|
||||
#define RGA_ROP_CON1_OFFSET (RGA_ROP_CON1-0x100)
|
||||
#define RGA_CP_GR_R_OFFSET (RGA_CP_GR_R-0x100) //repeat
|
||||
#define RGA_PRESCL_CR_MST_OFFSET (RGA_PRESCL_CR_MST-0x100) //repeat
|
||||
|
||||
#define RGA_FADING_CON_OFFSET (RGA_FADING_CON-0x100)
|
||||
#define RGA_MMU_TLB_OFFSET (RGA_MMU_CTRL-0x100)
|
||||
|
||||
|
||||
void matrix_cal(const struct rga_req *msg, TILE_INFO *tile);
|
||||
|
||||
|
||||
unsigned int RGA_gen_reg_info(const struct rga_req *msg, unsigned char *base);
|
||||
uint8_t RGA_pixel_width_init(uint32_t format);
|
||||
|
||||
|
||||
|
||||
/*
|
||||
u8 RGA_pixel_width_init(u32 format);
|
||||
void dst_ctrl_cal(msg_t *msg, TILE_INFO *tile);
|
||||
void src_tile_info_cal(msg_t *msg, TILE_INFO *tile);
|
||||
void RGA_set_mode_ctrl(u8 *base, msg_t *msg);
|
||||
void RGA_set_src(u8 *base, msg_t *msg, TILE_INFO *tile);
|
||||
s32 RGA_set_dst(u8 *base, msg_t *msg);
|
||||
void RGA_set_alpha_rop(u8 *base, msg_t *msg);
|
||||
void RGA_set_color(u8 *base, msg_t *msg);
|
||||
s32 RGA_set_fading(u8 *base, msg_t *msg);
|
||||
s32 RGA_set_pat(u8 *base, msg_t *msg);
|
||||
void RGA_set_bitblt_reg_info(u8 *base, msg_t * msg, TILE_INFO *tile);
|
||||
void RGA_set_color_palette_reg_info(u8 *base, msg_t *msg);
|
||||
void RGA_set_color_fill_reg_info(u8 *base, msg_t *msg);
|
||||
s32 RGA_set_line_drawing_reg_info(u8 *base, msg_t *msg);
|
||||
s32 RGA_set_filter_reg_info(u8 *base, msg_t *msg);
|
||||
s32 RGA_set_pre_scale_reg_info(u8 *base, msg_t *msg);
|
||||
s32 RGA_set_update_palette_table_reg_info(u8 *base, msg_t *msg);
|
||||
s32 RGA_set_update_patten_buff_reg_info(u8 *base, msg_t *msg);
|
||||
s32 RGA_set_mmu_ctrl_reg_info(u8 *base, msg_t *msg);
|
||||
*/
|
||||
57
drivers/video/rockchip/rga/rga_rop.h
Normal file
57
drivers/video/rockchip/rga/rga_rop.h
Normal file
@@ -0,0 +1,57 @@
|
||||
#ifndef __RGA_ROP_H__
|
||||
#define __RGA_ROP_H__
|
||||
|
||||
#include "rga_type.h"
|
||||
|
||||
UWORD32 ROP3_code[256] =
|
||||
{
|
||||
0x00000007, 0x00000451, 0x00006051, 0x00800051, 0x00007041, 0x00800041, 0x00804830, 0x000004f0,//0
|
||||
0x00800765, 0x000004b0, 0x00000065, 0x000004f4, 0x00000075, 0x000004e6, 0x00804850, 0x00800005,
|
||||
|
||||
0x00006850, 0x00800050, 0x00805028, 0x00000568, 0x00804031, 0x00000471, 0x002b6071, 0x018037aa,//1
|
||||
0x008007aa, 0x00036071, 0x00002c6a, 0x00803631, 0x00002d68, 0x00802721, 0x008002d0, 0x000006d0,
|
||||
|
||||
0x0080066e, 0x00000528, 0x00000066, 0x0000056c, 0x018007aa, 0x0002e06a, 0x00003471, 0x00834031,//2
|
||||
0x00800631, 0x0002b471, 0x00006071, 0x008037aa, 0x000036d0, 0x008002d4, 0x00002d28, 0x000006d4,
|
||||
|
||||
0x0000006e, 0x00000565, 0x00003451, 0x00800006, 0x000034f0, 0x00834830, 0x00800348, 0x00000748,//3
|
||||
0x00002f48, 0x0080034c, 0x000034b0, 0x0000074c, 0x00000031, 0x00834850, 0x000034e6, 0x00800071,
|
||||
|
||||
0x008006f4, 0x00000431, 0x018007a1, 0x00b6e870, 0x00000074, 0x0000046e, 0x00002561, 0x00802f28,//4
|
||||
0x00800728, 0x0002a561, 0x000026c2, 0x008002c6, 0x00007068, 0x018035aa, 0x00002c2a, 0x000006c6,
|
||||
|
||||
0x0000006c, 0x00000475, 0x000024e2, 0x008036b0, 0x00804051, 0x00800004, 0x00800251, 0x00000651,
|
||||
0x00002e4a, 0x0080024e, 0x00000028, 0x00824842, 0x000024a2, 0x0000064e, 0x000024f4, 0x00800068,//5
|
||||
|
||||
0x008006b0, 0x000234f0, 0x00002741, 0x00800345, 0x00003651, 0x00800255, 0x00000030, 0x00834051,
|
||||
0x00a34842, 0x000002b0, 0x00800271, 0x0002b651, 0x00800368, 0x0002a741, 0x0000364e, 0x00806830,//6
|
||||
|
||||
0x00006870, 0x008037a2, 0x00003431, 0x00000745, 0x00002521, 0x00000655, 0x0000346e, 0x00800062,
|
||||
0x008002f0, 0x000236d0, 0x000026d4, 0x00807028, 0x000036c6, 0x00806031, 0x008005aa, 0x00000671,//7
|
||||
|
||||
0x00800671, 0x000005aa, 0x00006031, 0x008036c6, 0x00007028, 0x00802e55, 0x008236d0, 0x000002f0,
|
||||
0x00000070, 0x0080346e, 0x00800655, 0x00802521, 0x00800745, 0x00803431, 0x000037a2, 0x00806870,//8
|
||||
|
||||
0x00006830, 0x0080364e, 0x00822f48, 0x00000361, 0x0082b651, 0x00000271, 0x00800231, 0x002b4051,
|
||||
0x00034051, 0x00800030, 0x0080026e, 0x00803651, 0x0080036c, 0x00802741, 0x008234f0, 0x000006b0,//9
|
||||
|
||||
0x00000068, 0x00802c75, 0x0080064e, 0x008024a2, 0x0002c04a, 0x00800021, 0x00800275, 0x00802e51,
|
||||
0x00800651, 0x00000251, 0x00800000, 0x00004051, 0x000036b0, 0x008024e2, 0x00800475, 0x00000045,//a
|
||||
|
||||
0x008006c6, 0x00802c2a, 0x000035aa, 0x00807068, 0x008002f4, 0x008026c2, 0x00822d68, 0x00000728,
|
||||
0x00002f28, 0x00802561, 0x0080046e, 0x00000046, 0x00836870, 0x000007a2, 0x00800431, 0x00004071,//b
|
||||
|
||||
0x00000071, 0x008034e6, 0x00034850, 0x00800031, 0x0080074c, 0x008034b0, 0x00800365, 0x00802f48,
|
||||
0x00800748, 0x00000341, 0x000026a2, 0x008034f0, 0x00800002, 0x00005048, 0x00800565, 0x00000055,//c
|
||||
|
||||
0x008006d4, 0x00802d28, 0x008002e6, 0x008036d0, 0x000037aa, 0x00806071, 0x0082b471, 0x00000631,
|
||||
0x00002e2a, 0x00803471, 0x00826862, 0x010007aa, 0x0080056c, 0x00000054, 0x00800528, 0x00005068,//d
|
||||
|
||||
0x008006d0, 0x000002d0, 0x00002721, 0x00802d68, 0x00003631, 0x00802c6a, 0x00836071, 0x000007aa,
|
||||
0x010037aa, 0x00a36870, 0x00800471, 0x00004031, 0x00800568, 0x00005028, 0x00000050, 0x00800545,//e
|
||||
|
||||
0x00800001, 0x00004850, 0x008004e6, 0x0000004e, 0x008004f4, 0x0000004c, 0x008004b0, 0x00004870,
|
||||
0x008004f0, 0x00004830, 0x00000048, 0x0080044e, 0x00000051, 0x008004d4, 0x00800451, 0x00800007,//f
|
||||
};
|
||||
|
||||
#endif
|
||||
48
drivers/video/rockchip/rga/rga_type.h
Normal file
48
drivers/video/rockchip/rga/rga_type.h
Normal file
@@ -0,0 +1,48 @@
|
||||
#ifndef __RGA_TYPE_H__
|
||||
#define __RGA_TYPE_H__
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __cplusplus */
|
||||
|
||||
typedef unsigned int UWORD32;
|
||||
typedef unsigned int uint32;
|
||||
typedef unsigned int RK_U32;
|
||||
|
||||
typedef unsigned short UWORD16;
|
||||
typedef unsigned short RK_U16;
|
||||
|
||||
typedef unsigned char UBYTE;
|
||||
typedef unsigned char RK_U8;
|
||||
|
||||
typedef int WORD32;
|
||||
typedef int RK_S32;
|
||||
|
||||
typedef short WORD16;
|
||||
typedef short RK_S16;
|
||||
|
||||
typedef char BYTE;
|
||||
typedef char RK_S8;
|
||||
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL 0L
|
||||
#endif
|
||||
|
||||
#ifndef TRUE
|
||||
#define TRUE 1L
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __cplusplus */
|
||||
|
||||
|
||||
#endif /* __RGA_TYPR_H__ */
|
||||
|
||||
Reference in New Issue
Block a user