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Merge commit '64ab42efa552b21f5d9cd259f7f13c8b5125842d'

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* commit '64ab42efa552b21f5d9cd259f7f13c8b5125842d':
  net: can: rockchip: use soft reset for bus off
  net: can: rockchip: fix rx stuck and timeout
  net: can: rockchip: support Listen-only mode
  net: can: rockchip: fix tx error in special application
  arm64: dts: rockchip: rk3588-vehicle-evb-v22: Switch to use standalone NCA9539 driver
  video: rockchip: mpp: fix rkvenc2 run crash issue
  arm64: dts: rockchip: rk3588: dmc add SYS_STATUS_DEEP_SUSPEND
  PM / devfreq: rockchip_dmc: add support SYS_STATUS_DEEP_SUSPEND
  media: rockchip: isp: support change work mode to online with quick stream
  arm64: dts: rockchip: rk3588-vehicle-s66\*maxim\*: Fix pins default pinctrls
  arm64: dts: rockchip: rk3588-vehicle\*maxim\*: Fix pins default pinctrls
  backlight: pwm_bl: fix the state check in power-off
  arm64: dts: rockchip: rk3528: Add low temperature config for opp table
  net: phy: rk630: Fixed for reboot && ping issue

Change-Id: I24998055c32c70cc92b97550bd54fd755ce0430e
This commit is contained in:
Tao Huang
2023-11-06 17:37:03 +08:00
parent 2e205b21b6 64ab42efa5
commit 91e80a06a1
20 changed files with 198 additions and 106 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm64/boot/dts/rockchip/rk3528.dtsi
View File

@@ -220,6 +220,9 @@
rockchip,pvtm-temp-prop = <0 0>;
rockchip,pvtm-thermal-zone = "soc-thermal";
rockchip,grf = <&grf>;
rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <10000>;
rockchip,low-temp-min-volt = <900000>;
opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
@@ -1073,6 +1076,9 @@
rockchip,pvtm-temp-prop = <0 0>;
rockchip,pvtm-thermal-zone = "soc-thermal";
rockchip,grf = <&grf>;
rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <10000>;
rockchip,low-temp-min-volt = <900000>;
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;

6
arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96712-dcphy0.dtsi
View File

@@ -720,15 +720,15 @@
&pinctrl {
max96712-dcphy0 {
max96712_dcphy0_pwdn: max96712-dcphy0-pwdn {
rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>;
};
max96712_dcphy0_errb: max96712-dcphy0-errb {
rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
max96712_dcphy0_lock: max96712-dcphy0-lock {
rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
};
};

6
arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96712-dcphy1.dtsi
View File

@@ -490,15 +490,15 @@
&pinctrl {
max96712-dcphy1 {
max96712_dcphy1_pwdn: max96712-dcphy1-pwdn {
rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_output_low>;
};
max96712_dcphy1_errb: max96712-dcphy1-errb {
rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
max96712_dcphy1_lock: max96712-dcphy1-lock {
rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
};
};

6
arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96712-dphy0.dtsi
View File

@@ -732,15 +732,15 @@
&pinctrl {
max96712-dphy0 {
max96712_dphy0_pwdn: max96712-dphy0-pwdn {
rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_output_low>;
};
max96712_dphy0_errb: max96712-dphy0-errb {
rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
max96712_dphy0_lock: max96712-dphy0-lock {
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
};
};

6
arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96712-dphy3.dtsi
View File

@@ -636,15 +636,15 @@
&pinctrl {
max96712-dphy3 {
max96712_dphy3_pwdn: max96712-dphy3-pwdn {
rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_output_low>;
};
max96712_dphy3_errb: max96712-dphy3-errb {
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
max96712_dphy3_lock: max96712-dphy3-lock {
rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
};
};

6
arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96712.dtsi
View File

@@ -148,15 +148,15 @@
&pinctrl {
max96712-dphy3 {
max96712_dphy3_power: max96712-dphy3-power {
rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_output_low>;
};
max96712_dphy3_errb: max96712-dphy3-errb {
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
max96712_dphy3_lock: max96712-dphy3-lock {
rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
};
};

6
arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96722-dphy0.dtsi
View File

@@ -732,15 +732,15 @@
&pinctrl {
max96722-dphy0 {
max96722_dphy0_pwdn: max96722-dphy0-pwdn {
rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_output_low>;
};
max96722_dphy0_errb: max96722-dphy0-errb {
rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
max96722_dphy0_lock: max96722-dphy0-lock {
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
};
};

6
arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96722-dphy3.dtsi
View File

@@ -502,15 +502,15 @@
&pinctrl {
max96722-dphy3 {
max96722_dphy3_pwdn: max96722-dphy3-pwdn {
rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_output_low>;
};
max96722_dphy3_errb: max96722-dphy3-errb {
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
max96722_dphy3_lock: max96722-dphy3-lock {
rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
};
};

6
arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96722.dtsi
View File

@@ -149,15 +149,15 @@
&pinctrl {
max96722-dphy0 {
max96722_dphy0_power: max96722-dphy0-power {
rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_output_low>;
};
max96722_dphy0_errb: max96722-dphy0-errb {
rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
max96722_dphy0_lock: max96722-dphy0-lock {
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
};
};

69
arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v22.dts
View File

@@ -7,6 +7,7 @@
/dts-v1/;
#include "rk3588-vehicle-evb-v21.dtsi"
#include "rk3588-vehicle-evb-v22-nca9539-io-expander.dtsi"
#include "rk3588-vehicle-evb-maxim-max96712-dphy3.dtsi"
#include "rk3588-vehicle-serdes-mfd-display-rohm.dtsi"
#include "rk3588-android.dtsi"
@@ -61,7 +62,7 @@
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&i2c5_nca9539_gpio 0 GPIO_ACTIVE_HIGH>;
gpio = <&nca9539_gpio 0 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
@@ -77,7 +78,7 @@
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&i2c5_nca9539_gpio 1 GPIO_ACTIVE_HIGH>;
gpio = <&nca9539_gpio 1 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
@@ -93,7 +94,7 @@
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&i2c5_nca9539_gpio 2 GPIO_ACTIVE_HIGH>;
gpio = <&nca9539_gpio 2 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
@@ -109,7 +110,7 @@
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&i2c5_nca9539_gpio 3 GPIO_ACTIVE_HIGH>;
gpio = <&nca9539_gpio 3 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
@@ -125,7 +126,7 @@
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&i2c5_nca9539_gpio 4 GPIO_ACTIVE_HIGH>;
gpio = <&nca9539_gpio 4 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
@@ -141,7 +142,7 @@
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&i2c5_nca9539_gpio 5 GPIO_ACTIVE_HIGH>;
gpio = <&nca9539_gpio 5 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
@@ -156,7 +157,7 @@
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&i2c5_nca9539_gpio 6 GPIO_ACTIVE_HIGH>;
gpio = <&nca9539_gpio 6 GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
off-on-delay-us = <16000>;
vin-supply = <&vcc12v_dcin>;
@@ -173,7 +174,7 @@
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&i2c5_nca9539_gpio 7 GPIO_ACTIVE_HIGH>;
gpio = <&nca9539_gpio 7 GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
off-on-delay-us = <16000>;
vin-supply = <&vcc12v_dcin>;
@@ -190,7 +191,7 @@
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&i2c5_nca9539_gpio 8 GPIO_ACTIVE_HIGH>;
gpio = <&nca9539_gpio 8 GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
off-on-delay-us = <16000>;
vin-supply = <&vcc12v_dcin>;
@@ -207,7 +208,7 @@
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&i2c5_nca9539_gpio 9 GPIO_ACTIVE_HIGH>;
gpio = <&nca9539_gpio 9 GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
off-on-delay-us = <16000>;
vin-supply = <&vcc12v_dcin>;
@@ -225,7 +226,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&i2c5_nca9539_gpio 10 GPIO_ACTIVE_HIGH>;
gpio = <&nca9539_gpio 10 GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
off-on-delay-us = <16000>;
vin-supply = <&vcc5v0_usb>;
@@ -239,7 +240,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&i2c5_nca9539_gpio 11 GPIO_ACTIVE_HIGH>;
gpio = <&nca9539_gpio 11 GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
off-on-delay-us = <16000>;
vin-supply = <&vcc5v0_usb>;
@@ -253,7 +254,7 @@
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&i2c5_nca9539_gpio 12 GPIO_ACTIVE_HIGH>;
gpio = <&nca9539_gpio 12 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
@@ -269,7 +270,7 @@
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&i2c5_nca9539_gpio 13 GPIO_ACTIVE_HIGH>;
gpio = <&nca9539_gpio 13 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_usb>;
regulator-state-mem {
regulator-off-in-suspend;
@@ -398,36 +399,6 @@
interrupt-parent = <&gpio1>;
interrupts = <RK_PA5 IRQ_TYPE_LEVEL_LOW>;
};
i2c5_nca9539: i2c5-nca9539@74 {
compatible = "novo,nca9539";
reg = <0x74>;
status = "okay";
/* P00-P07 P10-P17 output HIGH level default*/
serdes-init-sequence = [
0002 00ff
0003 00ff
0004 0000
0005 0000
0006 0000
0007 0000
];
i2c5_nca9539_pinctrl: i2c5-nca9539-pinctrl {
compatible = "novo,nca9539-pinctrl";
status = "okay";
i2c5_nca9539_gpio: i2c5-nca9539-gpio {
compatible = "novo,nca9539-gpio";
status = "okay";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&i2c5_nca9539_pinctrl 0 256 16>;
};
};
};
};
&i2c5_bu18tl82 {
@@ -456,6 +427,10 @@
};
&pinctrl {
pinctrl-names = "init";
pinctrl-0 = <&max96712_dphy3_pwdn
&max96712_dphy3_errb
&max96712_dphy3_lock>;
bl {
bl0_enable_pin: bl0-enable-pin {
@@ -489,15 +464,15 @@
max96712-dphy3 {
max96712_dphy3_pwdn: max96712-dphy3-pwdn {
rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_output_low>;
};
max96712_dphy3_errb: max96712-dphy3-errb {
rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
max96712_dphy3_lock: max96712-dphy3-lock {
rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
};

12
arch/arm64/boot/dts/rockchip/rk3588-vehicle-maxim-cameras-s66.dtsi
View File

@@ -1151,27 +1151,27 @@
&pinctrl {
maxim-cameras {
max96712_dphy0_pwdn: max96712-dphy0-pwdn {
rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_output_low>;
};
max96712_dphy0_errb: max96712-dphy0-errb {
rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
max96712_dphy0_lock: max96712-dphy0-lock {
rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
max96722_dphy3_pwdn: max96722-dphy3-pwdn {
rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_output_low>;
};
max96722_dphy3_errb: max96722-dphy3-errb {
rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
max96722_dphy3_lock: max96722-dphy3-lock {
rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
};
};

10
arch/arm64/boot/dts/rockchip/rk3588-vehicle-s66-v10.dts
View File

@@ -87,3 +87,13 @@
regulator-on-in-suspend;
};
};
&pinctrl {
pinctrl-names = "init";
pinctrl-0 = <&max96712_dphy0_pwdn
&max96712_dphy0_errb
&max96712_dphy0_lock
&max96722_dphy3_pwdn
&max96722_dphy3_errb
&max96722_dphy3_lock>;
};

1
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
View File

@@ -1744,6 +1744,7 @@
SYS_STATUS_PERFORMANCE DMC_FREQ_LEVEL_HIGH
SYS_STATUS_DUALVIEW DMC_FREQ_LEVEL_HIGH
SYS_STATUS_HDMIRX DMC_FREQ_LEVEL_HIGH
SYS_STATUS_DEEP_SUSPEND DMC_FREQ_LEVEL_HIGH
>;
auto-freq-en = <1>;
status = "disabled";

10
drivers/devfreq/rockchip_dmc.c
View File

@@ -139,6 +139,7 @@ struct rockchip_dmcfreq {
unsigned long hdmirx_rate;
unsigned long idle_rate;
unsigned long suspend_rate;
unsigned long deep_suspend_rate;
unsigned long reboot_rate;
unsigned long boost_rate;
unsigned long fixed_rate;
@@ -2266,6 +2267,9 @@ static int rockchip_get_system_status_rate(struct device_node *np,
case SYS_STATUS_SUSPEND:
dmcfreq->suspend_rate = freq * 1000;
break;
case SYS_STATUS_DEEP_SUSPEND:
dmcfreq->deep_suspend_rate = freq * 1000;
break;
case SYS_STATUS_VIDEO_1080P:
dmcfreq->video_1080p_rate = freq * 1000;
break;
@@ -2408,6 +2412,11 @@ static int rockchip_get_system_status_level(struct device_node *np,
dmcfreq->suspend_rate = rockchip_freq_level_2_rate(dmcfreq, level);
dev_info(dmcfreq->dev, "suspend_rate = %ld\n", dmcfreq->suspend_rate);
break;
case SYS_STATUS_DEEP_SUSPEND:
dmcfreq->deep_suspend_rate = rockchip_freq_level_2_rate(dmcfreq, level);
dev_info(dmcfreq->dev, "deep_suspend_rate = %ld\n",
dmcfreq->deep_suspend_rate);
break;
case SYS_STATUS_VIDEO_1080P:
dmcfreq->video_1080p_rate = rockchip_freq_level_2_rate(dmcfreq, level);
dev_info(dmcfreq->dev, "video_1080p_rate = %ld\n",
@@ -3051,6 +3060,7 @@ static int rockchip_dmcfreq_add_devfreq(struct rockchip_dmcfreq *dmcfreq)
devm_devfreq_register_opp_notifier(dev, devfreq);
devfreq->last_status.current_frequency = opp_rate;
devfreq->suspend_freq = dmcfreq->deep_suspend_rate;
reset_last_status(devfreq);

52
drivers/media/platform/rockchip/isp/rkisp.c
View File

@@ -3384,6 +3384,55 @@ static int rkisp_get_info(struct rkisp_device *dev, struct rkisp_isp_info *info)
return 0;
}
static int rkisp_set_work_mode_by_vicap(struct rkisp_device *isp_dev,
struct rkisp_vicap_mode *vicap_mode)
{
struct rkisp_hw_dev *hw = isp_dev->hw_dev;
int rd_mode = isp_dev->rd_mode;
if (vicap_mode->rdbk_mode == RKISP_VICAP_ONLINE) {
if (!hw->is_single)
return -EINVAL;
/* switch to online mode for single sensor */
switch (rd_mode) {
case HDR_RDBK_FRAME3:
isp_dev->rd_mode = HDR_LINEX3_DDR;
break;
case HDR_RDBK_FRAME2:
isp_dev->rd_mode = HDR_LINEX2_DDR;
break;
default:
isp_dev->rd_mode = HDR_NORMAL;
}
} else if (vicap_mode->rdbk_mode == RKISP_VICAP_RDBK_AUTO) {
/* switch to readback mode */
switch (rd_mode) {
case HDR_LINEX3_DDR:
isp_dev->rd_mode = HDR_RDBK_FRAME3;
break;
case HDR_LINEX2_DDR:
isp_dev->rd_mode = HDR_RDBK_FRAME2;
break;
default:
isp_dev->rd_mode = HDR_RDBK_FRAME1;
}
} else {
return -EINVAL;
}
isp_dev->hdr.op_mode = isp_dev->rd_mode;
if (rd_mode != isp_dev->rd_mode && hw->cur_dev_id == isp_dev->dev_id) {
rkisp_unite_write(isp_dev, CSI2RX_CTRL0,
SW_IBUF_OP_MODE(isp_dev->rd_mode), true);
if (IS_HDR_RDBK(isp_dev->rd_mode))
rkisp_unite_set_bits(isp_dev, CTRL_SWS_CFG, 0,
SW_MPIP_DROP_FRM_DIS, true);
else
rkisp_unite_clear_bits(isp_dev, CTRL_SWS_CFG,
SW_MPIP_DROP_FRM_DIS, true);
}
return 0;
}
static long rkisp_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
{
struct rkisp_device *isp_dev = sd_to_isp_dev(sd);
@@ -3515,6 +3564,9 @@ static long rkisp_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
isp_dev->hw_dev->monitor.state &= ~ISP_CIF_RESET;
}
break;
case RKISP_VICAP_CMD_MODE:
ret = rkisp_set_work_mode_by_vicap(isp_dev, arg);
break;
default:
ret = -ENOIOCTLCMD;
}

77
drivers/net/can/rockchip/rockchip_canfd.c
View File

@@ -214,6 +214,8 @@ enum {
#define CAN_RXFRD_OFFSET(n) (CAN_RXFRD + CAN_RF_SIZE * (n))
#define CAN_RX_FILTER_MASK 0x1fffffff
#define NOACK_ERR_FLAG 0xc200800
#define CAN_BUSOFF_FLAG 0x20
#define DRV_NAME "rockchip_canfd"
@@ -234,6 +236,7 @@ struct rockchip_canfd {
bool txtorx;
u32 tx_invalid[4];
struct delayed_work tx_err_work;
u32 delay_time_ms;
};
static inline u32 rockchip_canfd_read(const struct rockchip_canfd *priv,
@@ -357,6 +360,12 @@ static int rockchip_canfd_set_bittiming(struct net_device *ndev)
rockchip_canfd_write(rcan, CAN_DBTP, reg_btp);
}
if (bt->bitrate > 200000)
rcan->delay_time_ms = 1;
else if (bt->bitrate > 50000)
rcan->delay_time_ms = 5;
else
rcan->delay_time_ms = 20;
netdev_dbg(ndev, "%s NBTP=0x%08x, DBTP=0x%08x, TDCR=0x%08x\n", __func__,
rockchip_canfd_read(rcan, CAN_NBTP),
@@ -428,6 +437,10 @@ static int rockchip_canfd_start(struct net_device *ndev)
if (rcan->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
val |= MODE_SELF_TEST | MODE_LBACK;
/* Listen-only mode */
if (rcan->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
val |= MODE_SILENT;
rockchip_canfd_write(rcan, CAN_MODE, val);
rockchip_canfd_set_bittiming(ndev);
@@ -487,13 +500,27 @@ static void rockchip_canfd_tx_err_delay_work(struct work_struct *work)
{
struct rockchip_canfd *rcan =
container_of(work, struct rockchip_canfd, tx_err_work.work);
u32 mode;
u32 mode, err_code;
mode = rockchip_canfd_read(rcan, CAN_MODE);
rockchip_canfd_write(rcan, CAN_MODE, 0);
rockchip_canfd_write(rcan, CAN_MODE, mode);
rockchip_canfd_write(rcan, CAN_CMD, CAN_TX0_REQ);
schedule_delayed_work(&rcan->tx_err_work, 1);
err_code = rockchip_canfd_read(rcan, CAN_ERR_CODE);
if ((err_code & NOACK_ERR_FLAG) == NOACK_ERR_FLAG) {
rockchip_canfd_write(rcan, CAN_MODE,
rockchip_canfd_read(rcan, CAN_MODE) | MODE_SPACE_RX);
rockchip_canfd_write(rcan, CAN_CMD, CAN_TX0_REQ);
rockchip_canfd_write(rcan, CAN_MODE,
rockchip_canfd_read(rcan, CAN_MODE) & (~MODE_SPACE_RX));
schedule_delayed_work(&rcan->tx_err_work, msecs_to_jiffies(rcan->delay_time_ms));
} else {
rockchip_canfd_write(rcan, CAN_MODE, 0);
rockchip_canfd_write(rcan, CAN_MODE, mode);
rockchip_canfd_write(rcan, CAN_MODE,
rockchip_canfd_read(rcan, CAN_MODE) | MODE_SPACE_RX);
rockchip_canfd_write(rcan, CAN_CMD, CAN_TX0_REQ);
rockchip_canfd_write(rcan, CAN_MODE,
rockchip_canfd_read(rcan, CAN_MODE) & (~MODE_SPACE_RX));
schedule_delayed_work(&rcan->tx_err_work, msecs_to_jiffies(rcan->delay_time_ms));
}
}
/* transmit a CAN message
@@ -569,10 +596,9 @@ static int rockchip_canfd_start_xmit(struct sk_buff *skb,
for (i = 0; i < cf->len; i += 4)
rockchip_canfd_write(rcan, CAN_TXDAT0 + i,
*(u32 *)(cf->data + i));
can_put_echo_skb(skb, ndev, 0);
rockchip_canfd_write(rcan, CAN_CMD, CAN_TX1_REQ);
local_irq_restore(flags);
can_put_echo_skb(skb, ndev, 0);
return NETDEV_TX_OK;
}
@@ -583,12 +609,13 @@ static int rockchip_canfd_start_xmit(struct sk_buff *skb,
rockchip_canfd_write(rcan, CAN_TXDAT0 + i,
*(u32 *)(cf->data + i));
rockchip_canfd_write(rcan, CAN_CMD, cmd);
schedule_delayed_work(&rcan->tx_err_work, 1);
can_put_echo_skb(skb, ndev, 0);
rockchip_canfd_write(rcan, CAN_MODE,
rockchip_canfd_read(rcan, CAN_MODE) | MODE_SPACE_RX);
rockchip_canfd_write(rcan, CAN_CMD, cmd);
rockchip_canfd_write(rcan, CAN_MODE,
rockchip_canfd_read(rcan, CAN_MODE) & (~MODE_SPACE_RX));
schedule_delayed_work(&rcan->tx_err_work, msecs_to_jiffies(rcan->delay_time_ms));
return NETDEV_TX_OK;
}
@@ -740,9 +767,6 @@ static int rockchip_canfd_err(struct net_device *ndev, u32 isr)
cf->data[7] = rxerr;
}
if (isr & TX_LOSTARB_INT)
schedule_delayed_work(&rcan->tx_err_work, 1);
if (isr & BUS_OFF_INT) {
rcan->can.state = CAN_STATE_BUS_OFF;
rcan->can.can_stats.bus_off++;
@@ -772,8 +796,14 @@ static int rockchip_canfd_err(struct net_device *ndev, u32 isr)
}
if (rcan->can.state >= CAN_STATE_BUS_OFF ||
((sta_reg & 0x20) == 0x20))
can_bus_off(ndev);
((sta_reg & CAN_BUSOFF_FLAG) == CAN_BUSOFF_FLAG)) {
cancel_delayed_work(&rcan->tx_err_work);
netif_stop_queue(ndev);
rockchip_canfd_stop(ndev);
can_free_echo_skb(ndev, 0);
rockchip_canfd_start(ndev);
netif_start_queue(ndev);
}
stats->rx_packets++;
stats->rx_bytes += cf->can_dlc;
@@ -788,13 +818,14 @@ static irqreturn_t rockchip_canfd_interrupt(int irq, void *dev_id)
struct rockchip_canfd *rcan = netdev_priv(ndev);
struct net_device_stats *stats = &ndev->stats;
u32 err_int = ERR_WARN_INT | RX_BUF_OV_INT | PASSIVE_ERR_INT |
TX_LOSTARB_INT | BUS_ERR_INT | BUS_OFF_INT;
BUS_ERR_INT | BUS_OFF_INT;
u32 isr;
u32 dlc = 0;
u32 quota, work_done = 0;
isr = rockchip_canfd_read(rcan, CAN_INT);
if (isr & TX_FINISH_INT) {
cancel_delayed_work(&rcan->tx_err_work);
dlc = rockchip_canfd_read(rcan, CAN_TXFIC);
/* transmission complete interrupt */
if (dlc & FDF_MASK)
@@ -802,7 +833,6 @@ static irqreturn_t rockchip_canfd_interrupt(int irq, void *dev_id)
else
stats->tx_bytes += (dlc & DLC_MASK);
stats->tx_packets++;
cancel_delayed_work(&rcan->tx_err_work);
if (rcan->txtorx && rcan->mode <= ROCKCHIP_RK3568_CAN_MODE && dlc & FORMAT_MASK) {
rockchip_canfd_write(rcan, CAN_TX_CHECK_FIC, FORMAT_MASK);
quota = rockchip_canfd_get_rx_fifo_cnt(ndev);
@@ -814,6 +844,10 @@ static irqreturn_t rockchip_canfd_interrupt(int irq, void *dev_id)
rockchip_canfd_write(rcan, CAN_CMD, CAN_TX1_REQ);
rockchip_canfd_write(rcan, CAN_TX_CHECK_FIC, 0);
}
if (read_poll_timeout_atomic(rockchip_canfd_read, quota,
!(quota & 0x3),
0, 5000000, false, rcan, CAN_CMD))
netdev_err(ndev, "Warning: wait tx req timeout!\n");
rockchip_canfd_write(rcan, CAN_CMD, 0);
can_get_echo_skb(ndev, 0);
netif_wake_queue(ndev);
@@ -825,7 +859,10 @@ static irqreturn_t rockchip_canfd_interrupt(int irq, void *dev_id)
rockchip_canfd_write(rcan, CAN_INT_MASK, 0x1);
napi_schedule(&rcan->napi);
} else {
quota = rockchip_canfd_get_rx_fifo_cnt(ndev);
work_done = 0;
quota = (rockchip_canfd_read(rcan, CAN_RXFC) &
rcan->rx_fifo_mask) >>
rcan->rx_fifo_shift;
if (quota) {
while (work_done < quota)
work_done += rockchip_canfd_rx(ndev);

6
drivers/net/phy/rk630phy.c
View File

@@ -238,7 +238,7 @@ static void rk630_phy_t22_config_init(struct phy_device *phydev)
/* Switch to page 6 */
phy_write(phydev, REG_PAGE_SEL, 0x0600);
/* PHYAFE ADC optimization */
phy_write(phydev, REG_PAGE6_ADC_ANONTROL, 0x555e);
phy_write(phydev, REG_PAGE6_ADC_ANONTROL, 0x5540);
/* PHYAFE Gain optimization */
phy_write(phydev, REG_PAGE6_GAIN_ANONTROL, 0x0400);
/* PHYAFE EQ optimization */
@@ -291,8 +291,8 @@ static int rk630_phy_config_init(struct phy_device *phydev)
break;
case PHY_ADDR_T22:
rk630_phy_t22_config_init(phydev);
rk630_phy_set_aps(phydev, true);
rk630_phy_set_uaps(phydev, true);
rk630_phy_set_aps(phydev, false);
rk630_phy_set_uaps(phydev, false);
break;
default:
phydev_err(phydev, "Unsupported address for current phy: %d\n",

2
drivers/video/backlight/pwm_bl.c
View File

@@ -74,7 +74,7 @@ static void pwm_backlight_power_off(struct pwm_bl_data *pb)
struct pwm_state state;
pwm_get_state(pb->pwm, &state);
if (!pb->enabled)
if (!pb->enabled && !state.enabled)
return;
if (pb->enable_gpio)

10
drivers/video/rockchip/mpp/mpp_rkvenc2.c
View File

@@ -1245,11 +1245,6 @@ static int rkvenc_run(struct mpp_dev *mpp, struct mpp_task *mpp_task)
/* init current task */
mpp->cur_task = mpp_task;
mpp_task_run_begin(mpp_task, timing_en, MPP_WORK_TIMEOUT_DELAY);
/* Flush the register before the start the device */
wmb();
/*
* reconfig timeout threshold.
* bit0-bit23,x1024 core clk cycles
@@ -1257,6 +1252,11 @@ static int rkvenc_run(struct mpp_dev *mpp, struct mpp_task *mpp_task)
timeout_thd = mpp_read(mpp, RKVENC_WDG) & 0xff000000;
timeout_thd |= TIMEOUT_MS * clk_get_rate(enc->core_clk_info.clk) / 1024000;
mpp_write(mpp, RKVENC_WDG, timeout_thd);
mpp_task_run_begin(mpp_task, timing_en, MPP_WORK_TIMEOUT_DELAY);
/* Flush the register before the start the device */
wmb();
mpp_write(mpp, enc->hw_info->enc_start_base, start_val);
mpp_task_run_end(mpp_task, timing_en);

1
include/dt-bindings/soc/rockchip-system-status.h
View File

@@ -37,6 +37,7 @@
#define SYS_STATUS_HDMIRX (1 << 18)
#define SYS_STATUS_VIDEO_SVEP (1 << 19)
#define SYS_STATUS_VIDEO_4K_60P (1 << 20)
#define SYS_STATUS_DEEP_SUSPEND (1 << 21)
#define SYS_STATUS_VIDEO (SYS_STATUS_VIDEO_4K | \
SYS_STATUS_VIDEO_1080P | \