From 92c75d601da47dea864cee2220a23721cf50cd1f Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Mon, 27 Nov 2023 18:46:09 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3568: add pwm irq configs Change-Id: I45dd3c50cbae6100c099714dcec5d39ce20a710a Signed-off-by: Damon Ding --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 57e799b9cb22..1aacc3eab62e 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -951,6 +951,7 @@ pwm0: pwm@fdd70000 { compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xfdd70000 0x0 0x10>; + interrupts = ; clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm0m0_pins>; @@ -962,6 +963,7 @@ pwm1: pwm@fdd70010 { compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xfdd70010 0x0 0x10>; + interrupts = ; clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm1m0_pins>; @@ -973,6 +975,7 @@ pwm2: pwm@fdd70020 { compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xfdd70020 0x0 0x10>; + interrupts = ; clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm2m0_pins>; @@ -3053,6 +3056,7 @@ pwm4: pwm@fe6e0000 { compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xfe6e0000 0x0 0x10>; + interrupts = ; clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm4_pins>; @@ -3064,6 +3068,7 @@ pwm5: pwm@fe6e0010 { compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xfe6e0010 0x0 0x10>; + interrupts = ; clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm5_pins>; @@ -3075,6 +3080,7 @@ pwm6: pwm@fe6e0020 { compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xfe6e0020 0x0 0x10>; + interrupts = ; clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm6_pins>; @@ -3099,6 +3105,7 @@ pwm8: pwm@fe6f0000 { compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xfe6f0000 0x0 0x10>; + interrupts = ; clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm8m0_pins>; @@ -3121,6 +3128,7 @@ pwm10: pwm@fe6f0020 { compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xfe6f0020 0x0 0x10>; + interrupts = ; clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm10m0_pins>; @@ -3145,6 +3153,7 @@ pwm12: pwm@fe700000 { compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xfe700000 0x0 0x10>; + interrupts = ; clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm12m0_pins>; @@ -3156,6 +3165,7 @@ pwm13: pwm@fe700010 { compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xfe700010 0x0 0x10>; + interrupts = ; clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm13m0_pins>; @@ -3167,6 +3177,7 @@ pwm14: pwm@fe700020 { compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xfe700020 0x0 0x10>; + interrupts = ; clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm14m0_pins>;