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clk: rockchip: rk3399: To prevent the dclk_vopx below the FRAC clock

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In most case, we use the VPLL directly for HDMI or DP, and the
the frac dclk will bring the big jitter for dclk. So we don't need
to use the dclk_vopx_frac.

Change-Id: I0d27e5fcb8b4c9a28c0102074c1d6da9426386f4
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
This commit is contained in:
Xing Zheng
2016-05-09 09:29:32 +08:00
committed by Gerrit Code Review
parent bdba697e30
commit 92cfd751b4
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/rockchip/clk-rk3399.c
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@@ -159,9 +159,9 @@ PNAME(mux_pll_src_dmyvpll_cpll_gpll_24m_p) = { "dummy_vpll", "cpll", "gpll",
"xin24m" };
PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div",
"dclk_vop0_frac" };
"dummy_dclk_vop0_frac" };
PNAME(mux_dclk_vop1_p) = { "dclk_vop1_div",
"dclk_vop1_frac" };
"dummy_dclk_vop1_frac" };
PNAME(mux_clk_cif_p) = { "clk_cifout_src", "xin24m" };