From 9322b4700a733f4e9c2152a1dbd6352449ddb64e Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 14 May 2018 16:09:52 +0800 Subject: [PATCH] clk: rockchip: rk3288: export PCLK_PD_PMU and PCLK_PD_ALIVE clock id Change-Id: Ie0550d9528367fa070328562fad2e597a5d6d7f7 Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-rk3288.c | 4 ++-- include/dt-bindings/clock/rk3288-cru.h | 4 ++++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index b72d3d230747..d0e1d5191a4f 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -490,9 +490,9 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { COMPOSITE_NOGATE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0, RK3288_CLKSEL_CON(26), 15, 1, MFLAGS, 9, 5, DFLAGS), - DIV(0, "pclk_pd_alive", "gpll", 0, + DIV(PCLK_PD_ALIVE, "pclk_pd_alive", "gpll", 0, RK3288_CLKSEL_CON(33), 8, 5, DFLAGS), - COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", CLK_IGNORE_UNUSED, + COMPOSITE_NOMUX(PCLK_PD_PMU, "pclk_pd_pmu", "gpll", CLK_IGNORE_UNUSED, RK3288_CLKSEL_CON(33), 0, 5, DFLAGS, RK3288_CLKGATE_CON(5), 8, GFLAGS), diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h index 33819acbfc56..7c94bc10baae 100644 --- a/include/dt-bindings/clock/rk3288-cru.h +++ b/include/dt-bindings/clock/rk3288-cru.h @@ -161,6 +161,10 @@ #define PCLK_EFUSE256 369 #define PCLK_EFUSE1024 370 #define PCLK_ISP_IN 371 +#define PCLK_VIP 372 +#define PCLK_VIP_IN 373 +#define PCLK_PD_ALIVE 374 +#define PCLK_PD_PMU 375 /* hclk gates */ #define HCLK_GPS 448