From 932e81825b3516b3e2aa13d1da91c7cf3ae3a50d Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Fri, 9 Dec 2022 14:25:37 +0800 Subject: [PATCH] clk: rockchip: rk3588: Workaround for DTS-HD Bitstream on Denon BACKGROUND: DTS-HD Bitstream sounds noise occasionally on Denon-AVR-X2700H, and we found this happen sometime on PLL(frac mode), But it's gone on PLL(int mode). This patch Adds "CLK_SET_RATE_NO_REPARENT" for I2S5/6 which used for HDMI0/1 to make its parent fixed from GPLL(int mode) to fix DTS-HD Bitstream noise occasionally on Denon-AVR-X2700H. Signed-off-by: Sugar Zhang Change-Id: I5694c0a7839df817fd32b82ce69450f0eebdcf77 --- drivers/clk/rockchip/clk-rk3588.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c index 1331452fbd46..ea8c8df593d3 100644 --- a/drivers/clk/rockchip/clk-rk3588.c +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -1995,7 +1995,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { &rk3588_i2s9_8ch_rx_fracmux), GATE(MCLK_I2S9_8CH_RX, "mclk_i2s9_8ch_rx", "clk_i2s9_8ch_rx", 0, RK3588_CLKGATE_CON(65), 3, GFLAGS), - COMPOSITE(CLK_I2S5_8CH_TX_SRC, "clk_i2s5_8ch_tx_src", gpll_aupll_p, 0, + COMPOSITE(CLK_I2S5_8CH_TX_SRC, "clk_i2s5_8ch_tx_src", gpll_aupll_p, CLK_SET_RATE_NO_REPARENT, RK3588_CLKSEL_CON(140), 10, 1, MFLAGS, 5, 5, DFLAGS, RK3588_CLKGATE_CON(62), 6, GFLAGS), COMPOSITE_FRACMUX(CLK_I2S5_8CH_TX_FRAC, "clk_i2s5_8ch_tx_frac", "clk_i2s5_8ch_tx_src", CLK_SET_RATE_PARENT, @@ -2004,7 +2004,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { &rk3588_i2s5_8ch_tx_fracmux), GATE(MCLK_I2S5_8CH_TX, "mclk_i2s5_8ch_tx", "clk_i2s5_8ch_tx", 0, RK3588_CLKGATE_CON(62), 8, GFLAGS), - COMPOSITE(CLK_I2S6_8CH_TX_SRC, "clk_i2s6_8ch_tx_src", gpll_aupll_p, 0, + COMPOSITE(CLK_I2S6_8CH_TX_SRC, "clk_i2s6_8ch_tx_src", gpll_aupll_p, CLK_SET_RATE_NO_REPARENT, RK3588_CLKSEL_CON(144), 8, 1, MFLAGS, 3, 5, DFLAGS, RK3588_CLKGATE_CON(62), 13, GFLAGS), COMPOSITE_FRACMUX(CLK_I2S6_8CH_TX_FRAC, "clk_i2s6_8ch_tx_frac", "clk_i2s6_8ch_tx_src", CLK_SET_RATE_PARENT,