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mtd: spi-nor: spansion: Enable JFFS2 write buffer for Infineon s25hx SEMPER flash
[ Upstream commit4199c1719e] Infineon(Cypress) SEMPER NOR flash family has on-die ECC and its program granularity is 16-byte ECC data unit size. JFFS2 supports write buffer mode for ECC'd NOR flash. Provide a way to clear the MTD_BIT_WRITEABLE flag in order to enable JFFS2 write buffer mode support. Fixes:b6b23833fc("mtd: spi-nor: spansion: Add s25hl-t/s25hs-t IDs and fixups") Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/a1cc128e094db4ec141f85bd380127598dfef17e.1680760742.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
committed by
Greg Kroah-Hartman
parent
50f54a48f6
commit
93eb8dd4b4
@@ -260,13 +260,10 @@ static void s25hx_t_post_sfdp_fixup(struct spi_nor *nor)
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static void s25hx_t_late_init(struct spi_nor *nor)
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static void s25hx_t_late_init(struct spi_nor *nor)
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{
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{
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struct spi_nor_flash_parameter *params = nor->params;
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/* Fast Read 4B requires mode cycles */
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/* Fast Read 4B requires mode cycles */
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params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8;
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nor->params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8;
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/* The writesize should be ECC data unit size */
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cypress_nor_ecc_init(nor);
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params->writesize = 16;
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}
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}
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static struct spi_nor_fixups s25hx_t_fixups = {
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static struct spi_nor_fixups s25hx_t_fixups = {
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