From 94a5dd9f3253dfe29ae82543bc3b24aab69cbd2c Mon Sep 17 00:00:00 2001
From: Yandong Lin <yandong.lin@rock-chips.com>
Date: Tue, 14 Jun 2022 14:54:51 +0800
Subject: [PATCH] arm64: dts: rockchip: add vepu support and separate jpege for
 rk3588

Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: I530c8213039d52329a05ddc3092ec18f63c4063a
---
 arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi  |  4 +++
 arch/arm64/boot/dts/rockchip/rk3588s-evb.dtsi |  4 +++
 arch/arm64/boot/dts/rockchip/rk3588s.dtsi     | 34 ++++++++++++++++---
 3 files changed, 37 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi
index cf731aacfcd9..4882092c2ea5 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi
@@ -1180,6 +1180,10 @@
 	status = "okay";
 };
 
+&vepu {
+	status = "okay";
+};
+
 &vop {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-evb.dtsi
index 57f1d510e4c5..82488ea1330a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-evb.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-evb.dtsi
@@ -1118,6 +1118,10 @@
 	status = "okay";
 };
 
+&vepu {
+	status = "okay";
+};
+
 &vop {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index d7f5ecfadd53..9b1d7f9f581a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -1369,13 +1369,14 @@
 	};
 
 	jpege_ccu: jpege-ccu {
-		compatible = "rockchip,vpu-encoder-v2-ccu";
+		compatible = "rockchip,vpu-jpege-ccu";
 		status = "disabled";
 	};
 
 	mpp_srv: mpp-srv {
 		compatible = "rockchip,mpp-service";
 		rockchip,taskqueue-count = <12>;
+		rockchip,resetgroup-count = <1>;
 		status = "disabled";
 	};
 
@@ -2893,6 +2894,27 @@
 		status = "disabled";
 	};
 
+	vepu: vepu@fdb50000 {
+		compatible = "rockchip,vpu-encoder-v2";
+		reg = <0x0 0xfdb50000 0x0 0x400>;
+		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "irq_vepu";
+		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+		clock-names = "aclk_vcodec", "hclk_vcodec";
+		rockchip,normal-rates = <594000000>, <0>;
+		assigned-clocks = <&cru ACLK_VPU>;
+		assigned-clock-rates = <594000000>;
+		resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>;
+		reset-names = "shared_video_a", "shared_video_h";
+		rockchip,skip-pmu-idle-request;
+		iommus = <&vdpu_mmu>;
+		rockchip,srv = <&mpp_srv>;
+		rockchip,taskqueue-node = <0>;
+		rockchip,resetgroup-node = <0>;
+		power-domains = <&power RK3588_PD_VDPU>;
+		status = "disabled";
+	};
+
 	vdpu: vdpu@fdb50400 {
 		compatible = "rockchip,vpu-decoder-v2";
 		reg = <0x0 0xfdb50400 0x0 0x400>;
@@ -2909,6 +2931,7 @@
 		iommus = <&vdpu_mmu>;
 		rockchip,srv = <&mpp_srv>;
 		rockchip,taskqueue-node = <0>;
+		rockchip,resetgroup-node = <0>;
 		power-domains = <&power RK3588_PD_VDPU>;
 		status = "disabled";
 	};
@@ -2938,6 +2961,7 @@
 		power-domains = <&power RK3588_PD_VDPU>;
 		rockchip,srv = <&mpp_srv>;
 		rockchip,taskqueue-node = <0>;
+		rockchip,resetgroup-node = <0>;
 		status = "disabled";
 	};
 
@@ -3033,7 +3057,7 @@
 	};
 
 	jpege0: jpege-core@fdba0000 {
-		compatible = "rockchip,vpu-encoder-v2-core";
+		compatible = "rockchip,vpu-jpege-core";
 		reg = <0x0 0xfdba0000 0x0 0x400>;
 		interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "irq_jpege0";
@@ -3066,7 +3090,7 @@
 	};
 
 	jpege1: jpege-core@fdba4000 {
-		compatible = "rockchip,vpu-encoder-v2-core";
+		compatible = "rockchip,vpu-jpege-core";
 		reg = <0x0 0xfdba4000 0x0 0x400>;
 		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "irq_jpege1";
@@ -3099,7 +3123,7 @@
 	};
 
 	jpege2: jpege-core@fdba8000 {
-		compatible = "rockchip,vpu-encoder-v2-core";
+		compatible = "rockchip,vpu-jpege-core";
 		reg = <0x0 0xfdba8000 0x0 0x400>;
 		interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "irq_jpege2";
@@ -3132,7 +3156,7 @@
 	};
 
 	jpege3: jpege-core@fdbac000 {
-		compatible = "rockchip,vpu-encoder-v2-core";
+		compatible = "rockchip,vpu-jpege-core";
 		reg = <0x0 0xfdbac000 0x0 0x400>;
 		interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "irq_jpege3";