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Merge commit '8fcc8f437c57f09dfb5745a220651e7f7f0d04d6'

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* commit '8fcc8f437c57f09dfb5745a220651e7f7f0d04d6':
  arm64: dts: rockchip: rk3528-evb: support es7243 sound
  drm: bridge: dw-hdmi: Support ddc io pull down when hdmi disconnected
  arm64: dts: rockchip: rk3528: Add hdmi ddc io idle state
  drm/rockchip: vop3: acquire vop private blob property reference
  drm/rockchip: dsi2: let te_irq_handle be called as soon as possible
  drm/rockchip: vop2: Don't crash for invalid duplicate_state()
  UPSTREAM: drm/rockchip: vop: Don't crash for invalid duplicate_state()
  arm64: dts: rockchip: rk3562: modify driver strength for pwm pins
  arm64: dts: rockchip: rk3588 boards: Add supply for rkvenc
  arm64: dts: rockchip: rk3588: Add opp table for rkvenc
  video: rockchip: mpp: rkvenc2: Add devfreq support
  arm64: dts: rockchip: rk3528-linux.dtsi enable route-hdmi and route-tve
  arm64/config: rockchip_linux_defconfig add CONFIG_CPU_RK3528
  arm64: dts: rockchip: rk3528-linux.dtsi add cmdline root and optee
  arm64: dts: rockchip: rk3528-evb1-ddr4-v10-linux.dts: add sdmmc status
  media: rockchip: vicap: make rkcif_vb_done_oneframe() static
  drm/bridge: synopsys: dw_hdmi: Add support for HBR / NLPCM Bitstream
  media: rockchip: fix isp no work due to irq_ends_mask error
  media: rockchip: isp: fix warning of vb2 cancel or done

Change-Id: Ic308e6755a2e44fd7caca67cfb36a713a87951aa
This commit is contained in:
Tao Huang
2023-03-14 16:53:04 +08:00
parent 538ed29a66 8fcc8f437c
commit 959e79906c
35 changed files with 476 additions and 102 deletions
Download Patch File Download Diff File Expand all files Collapse all files

39
arch/arm64/boot/dts/rockchip/rk3528-evb.dtsi
View File

@@ -48,6 +48,21 @@
regulator-max-microvolt = <12000000>;
};
es7243_sound: es7243-sound {
status = "disabled";
compatible = "simple-audio-card";
simple-audio-card,name = "rockchip,es7243";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,cpu {
sound-dai = <&sai1>;
};
simple-audio-card,codec {
sound-dai = <&es7243e>;
};
};
hdmi_sound: hdmi-sound {
compatible = "rockchip,hdmi";
rockchip,mclk-fs = <128>;
@@ -280,6 +295,30 @@
status = "okay";
};
&i2c6 {
status = "disabled";
es7243e: es7243e@10 {
status = "okay";
#sound-dai-cells = <0>;
compatible = "ES7243E_MicArray_0";
reg = <0x10>;
};
es7243e_11: es7243e@11 {
status = "okay";
#sound-dai-cells = <0>;
compatible = "ES7243E_MicArray_1";
reg = <0x11>;
};
es7243e_12: es7243e@12 {
status = "okay";
#sound-dai-cells = <0>;
compatible = "ES7243E_MicArray_2";
reg = <0x12>;
};
};
&iep {
status = "okay";
};

4
arch/arm64/boot/dts/rockchip/rk3528-evb1-ddr4-v10-linux.dts
View File

@@ -6,3 +6,7 @@
#include "rk3528-evb1-ddr4-v10.dtsi"
#include "rk3528-linux.dtsi"
&sdmmc {
status = "okay";
};

12
arch/arm64/boot/dts/rockchip/rk3528-evb1-ddr4-v10.dtsi
View File

@@ -45,6 +45,14 @@
};
&es7243_sound {
status = "okay";
};
&i2c6 {
status = "okay";
};
&gmac1 {
/* Use rgmii-rxid mode to disable rx delay inside Soc */
phy-mode = "rgmii-rxid";
@@ -76,6 +84,10 @@
};
};
&sai1 {
status = "okay";
};
&sdio0 {
max-frequency = <200000000>;
no-sd;

13
arch/arm64/boot/dts/rockchip/rk3528-linux.dtsi
View File

@@ -6,7 +6,7 @@
/ {
chosen: chosen {
bootargs = "earlycon=uart8250,mmio32,0xff9f0000 console=ttyFIQ0";
bootargs = "earlycon=uart8250,mmio32,0xff9f0000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait";
};
fiq-debugger {
@@ -22,6 +22,13 @@
status = "okay";
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@@ -58,7 +65,7 @@
route {
route_hdmi: route-hdmi {
status = "disabled";
status = "okay";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
@@ -66,7 +73,7 @@
connect = <&vp0_out_hdmi>;
};
route_tve: route-tve {
status = "disabled";
status = "okay";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";

11
arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi
View File

@@ -190,6 +190,17 @@
/* hdmi_tx_sda */
<0 RK_PA5 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
hdmi_pins_idle: hdmi-pins-idle {
rockchip,pins =
/* hdmi_tx_cec */
<0 RK_PA3 1 &pcfg_pull_none>,
/* hdmi_tx_scl */
<0 RK_PA4 0 &pcfg_output_low_pull_down>,
/* hdmi_tx_sda */
<0 RK_PA5 0 &pcfg_output_low_pull_down>;
};
};
hsm {

3
arch/arm64/boot/dts/rockchip/rk3528.dtsi
View File

@@ -1339,8 +1339,9 @@
clock-names = "iahb", "isfr", "cec";
reg-io-width = <4>;
rockchip,grf = <&grf>;
pinctrl-names = "default";
pinctrl-names = "default", "idle";
pinctrl-0 = <&hdmi_pins>;
pinctrl-1 = <&hdmi_pins_idle>;
phys = <&hdmiphy>;
phy-names = "hdmi";
#sound-dai-cells = <0>;

64
arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi
View File

@@ -942,14 +942,14 @@
pwm0m0_pins: pwm0m0-pins {
rockchip,pins =
/* pwm0_m0 */
<0 RK_PC3 2 &pcfg_pull_none>;
<0 RK_PC3 2 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm0m1_pins: pwm0m1-pins {
rockchip,pins =
/* pwm0_m1 */
<1 RK_PC5 4 &pcfg_pull_none>;
<1 RK_PC5 4 &pcfg_pull_none_drv_level_1>;
};
};
@@ -958,14 +958,14 @@
pwm1m0_pins: pwm1m0-pins {
rockchip,pins =
/* pwm1_m0 */
<0 RK_PC4 2 &pcfg_pull_none>;
<0 RK_PC4 2 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm1m1_pins: pwm1m1-pins {
rockchip,pins =
/* pwm1_m1 */
<1 RK_PC6 4 &pcfg_pull_none>;
<1 RK_PC6 4 &pcfg_pull_none_drv_level_1>;
};
};
@@ -974,14 +974,14 @@
pwm2m0_pins: pwm2m0-pins {
rockchip,pins =
/* pwm2_m0 */
<0 RK_PC5 2 &pcfg_pull_none>;
<0 RK_PC5 2 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm2m1_pins: pwm2m1-pins {
rockchip,pins =
/* pwm2_m1 */
<1 RK_PC7 3 &pcfg_pull_none>;
<1 RK_PC7 3 &pcfg_pull_none_drv_level_1>;
};
};
@@ -990,14 +990,14 @@
pwm3m0_pins: pwm3m0-pins {
rockchip,pins =
/* pwm3_m0 */
<0 RK_PA7 1 &pcfg_pull_none>;
<0 RK_PA7 1 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm3m1_pins: pwm3m1-pins {
rockchip,pins =
/* pwm3_m1 */
<1 RK_PD0 3 &pcfg_pull_none>;
<1 RK_PD0 3 &pcfg_pull_none_drv_level_1>;
};
};
@@ -1006,14 +1006,14 @@
pwm4m0_pins: pwm4m0-pins {
rockchip,pins =
/* pwm4_m0 */
<0 RK_PB7 2 &pcfg_pull_none>;
<0 RK_PB7 2 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm4m1_pins: pwm4m1-pins {
rockchip,pins =
/* pwm4_m1 */
<1 RK_PD1 4 &pcfg_pull_none>;
<1 RK_PD1 4 &pcfg_pull_none_drv_level_1>;
};
};
@@ -1022,14 +1022,14 @@
pwm5m0_pins: pwm5m0-pins {
rockchip,pins =
/* pwm5_m0 */
<0 RK_PC2 2 &pcfg_pull_none>;
<0 RK_PC2 2 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm5m1_pins: pwm5m1-pins {
rockchip,pins =
/* pwm5_m1 */
<1 RK_PD2 4 &pcfg_pull_none>;
<1 RK_PD2 4 &pcfg_pull_none_drv_level_1>;
};
};
@@ -1038,14 +1038,14 @@
pwm6m0_pins: pwm6m0-pins {
rockchip,pins =
/* pwm6_m0 */
<0 RK_PC1 2 &pcfg_pull_none>;
<0 RK_PC1 2 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm6m1_pins: pwm6m1-pins {
rockchip,pins =
/* pwm6_m1 */
<1 RK_PD3 4 &pcfg_pull_none>;
<1 RK_PD3 4 &pcfg_pull_none_drv_level_1>;
};
};
@@ -1054,14 +1054,14 @@
pwm7m0_pins: pwm7m0-pins {
rockchip,pins =
/* pwm7_m0 */
<0 RK_PC0 2 &pcfg_pull_none>;
<0 RK_PC0 2 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm7m1_pins: pwm7m1-pins {
rockchip,pins =
/* pwm7_m1 */
<1 RK_PD4 4 &pcfg_pull_none>;
<1 RK_PD4 4 &pcfg_pull_none_drv_level_1>;
};
};
@@ -1070,14 +1070,14 @@
pwm8m0_pins: pwm8m0-pins {
rockchip,pins =
/* pwm8_m0 */
<3 RK_PA4 2 &pcfg_pull_none>;
<3 RK_PA4 2 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm8m1_pins: pwm8m1-pins {
rockchip,pins =
/* pwm8_m1 */
<1 RK_PC1 4 &pcfg_pull_none>;
<1 RK_PC1 4 &pcfg_pull_none_drv_level_1>;
};
};
@@ -1086,14 +1086,14 @@
pwm9m0_pins: pwm9m0-pins {
rockchip,pins =
/* pwm9_m0 */
<3 RK_PA5 2 &pcfg_pull_none>;
<3 RK_PA5 2 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm9m1_pins: pwm9m1-pins {
rockchip,pins =
/* pwm9_m1 */
<1 RK_PC2 4 &pcfg_pull_none>;
<1 RK_PC2 4 &pcfg_pull_none_drv_level_1>;
};
};
@@ -1102,14 +1102,14 @@
pwm10m0_pins: pwm10m0-pins {
rockchip,pins =
/* pwm10_m0 */
<1 RK_PB5 5 &pcfg_pull_none>;
<1 RK_PB5 5 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm10m1_pins: pwm10m1-pins {
rockchip,pins =
/* pwm10_m1 */
<1 RK_PC3 4 &pcfg_pull_none>;
<1 RK_PC3 4 &pcfg_pull_none_drv_level_1>;
};
};
@@ -1118,14 +1118,14 @@
pwm11m0_pins: pwm11m0-pins {
rockchip,pins =
/* pwm11_m0 */
<1 RK_PB6 5 &pcfg_pull_none>;
<1 RK_PB6 5 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm11m1_pins: pwm11m1-pins {
rockchip,pins =
/* pwm11_m1 */
<1 RK_PC4 4 &pcfg_pull_none>;
<1 RK_PC4 4 &pcfg_pull_none_drv_level_1>;
};
};
@@ -1134,14 +1134,14 @@
pwm12m0_pins: pwm12m0-pins {
rockchip,pins =
/* pwm12_m0 */
<4 RK_PA1 4 &pcfg_pull_none>;
<4 RK_PA1 4 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm12m1_pins: pwm12m1-pins {
rockchip,pins =
/* pwm12_m1 */
<3 RK_PB4 5 &pcfg_pull_none>;
<3 RK_PB4 5 &pcfg_pull_none_drv_level_1>;
};
};
@@ -1150,14 +1150,14 @@
pwm13m0_pins: pwm13m0-pins {
rockchip,pins =
/* pwm13_m0 */
<4 RK_PA4 3 &pcfg_pull_none>;
<4 RK_PA4 3 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm13m1_pins: pwm13m1-pins {
rockchip,pins =
/* pwm13_m1 */
<3 RK_PB5 5 &pcfg_pull_none>;
<3 RK_PB5 5 &pcfg_pull_none_drv_level_1>;
};
};
@@ -1166,14 +1166,14 @@
pwm14m0_pins: pwm14m0-pins {
rockchip,pins =
/* pwm14_m0 */
<3 RK_PC5 4 &pcfg_pull_none>;
<3 RK_PC5 4 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm14m1_pins: pwm14m1-pins {
rockchip,pins =
/* pwm14_m1 */
<1 RK_PD7 5 &pcfg_pull_none>;
<1 RK_PD7 5 &pcfg_pull_none_drv_level_1>;
};
};
@@ -1182,14 +1182,14 @@
pwm15m0_pins: pwm15m0-pins {
rockchip,pins =
/* pwm15_m0 */
<3 RK_PC6 4 &pcfg_pull_none>;
<3 RK_PC6 4 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm15m1_pins: pwm15m1-pins {
rockchip,pins =
/* pwm15_m1 */
<2 RK_PA0 5 &pcfg_pull_none>;
<2 RK_PA0 5 &pcfg_pull_none_drv_level_1>;
};
};

4
arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi
View File

@@ -1026,6 +1026,8 @@
};
&rkvenc0 {
venc-supply = <&vdd_vdenc_s0>;
mem-supply = <&vdd_vdenc_mem_s0>;
status = "okay";
};
@@ -1034,6 +1036,8 @@
};
&rkvenc1 {
venc-supply = <&vdd_vdenc_s0>;
mem-supply = <&vdd_vdenc_mem_s0>;
status = "okay";
};

12
arch/arm64/boot/dts/rockchip/rk3588-nvr-demo3-v10.dtsi
View File

@@ -36,6 +36,18 @@
/delete-node/ rk8602@42;
};
&rkvenc0 {
venc-supply = <&vdd_log_s0>;
mem-supply = <&vdd_log_s0>;
status = "okay";
};
&rkvenc1 {
venc-supply = <&vdd_log_s0>;
mem-supply = <&vdd_log_s0>;
status = "okay";
};
&spi2 {
rk806single@0 {
regulators {

4
arch/arm64/boot/dts/rockchip/rk3588-nvr.dtsi
View File

@@ -274,6 +274,8 @@
};
&rkvenc0 {
venc-supply = <&vdd_vdenc_s0>;
mem-supply = <&vdd_vdenc_mem_s0>;
status = "okay";
};
@@ -282,6 +284,8 @@
};
&rkvenc1 {
venc-supply = <&vdd_vdenc_s0>;
mem-supply = <&vdd_vdenc_mem_s0>;
status = "okay";
};

4
arch/arm64/boot/dts/rockchip/rk3588-pc.dtsi
View File

@@ -226,6 +226,8 @@
};
&rkvenc0 {
venc-supply = <&vdd_vdenc_s0>;
mem-supply = <&vdd_vdenc_mem_s0>;
status = "okay";
};
@@ -234,6 +236,8 @@
};
&rkvenc1 {
venc-supply = <&vdd_vdenc_s0>;
mem-supply = <&vdd_vdenc_mem_s0>;
status = "okay";
};

4
arch/arm64/boot/dts/rockchip/rk3588-toybrick.dtsi
View File

@@ -1049,6 +1049,8 @@
};
&rkvenc0 {
venc-supply = <&vdd_vdenc_s0>;
mem-supply = <&vdd_vdenc_mem_s0>;
status = "okay";
};
@@ -1057,6 +1059,8 @@
};
&rkvenc1 {
venc-supply = <&vdd_vdenc_s0>;
mem-supply = <&vdd_vdenc_mem_s0>;
status = "okay";
};

4
arch/arm64/boot/dts/rockchip/rk3588-vehicle.dtsi
View File

@@ -339,6 +339,8 @@
};
&rkvenc0 {
venc-supply = <&vdd_vdenc_s0>;
mem-supply = <&vdd_vdenc_mem_s0>;
status = "okay";
};
@@ -347,6 +349,8 @@
};
&rkvenc1 {
venc-supply = <&vdd_vdenc_s0>;
mem-supply = <&vdd_vdenc_mem_s0>;
status = "okay";
};

4
arch/arm64/boot/dts/rockchip/rk3588s-evb.dtsi
View File

@@ -988,6 +988,8 @@
};
&rkvenc0 {
venc-supply = <&vdd_vdenc_s0>;
mem-supply = <&vdd_vdenc_mem_s0>;
status = "okay";
};
@@ -996,6 +998,8 @@
};
&rkvenc1 {
venc-supply = <&vdd_vdenc_s0>;
mem-supply = <&vdd_vdenc_mem_s0>;
status = "okay";
};

2
arch/arm64/boot/dts/rockchip/rk3588s-tablet-rk806-single.dtsi
View File

@@ -1551,6 +1551,8 @@
};
&rkvenc0 {
venc-supply = <&vdd_vdenc_s0>;
mem-supply = <&vdd_vdenc_mem_s0>;
status = "okay";
};

4
arch/arm64/boot/dts/rockchip/rk3588s-tablet-single.dtsi
View File

@@ -1193,6 +1193,8 @@
};
&rkvenc0 {
venc-supply = <&vdd_vdenc_s0>;
mem-supply = <&vdd_vdenc_mem_s0>;
status = "okay";
};
@@ -1201,6 +1203,8 @@
};
&rkvenc1 {
venc-supply = <&vdd_vdenc_s0>;
mem-supply = <&vdd_vdenc_mem_s0>;
status = "okay";
};

4
arch/arm64/boot/dts/rockchip/rk3588s-tablet.dtsi
View File

@@ -1104,6 +1104,8 @@
};
&rkvenc0 {
venc-supply = <&vdd_vdenc_s0>;
mem-supply = <&vdd_vdenc_mem_s0>;
status = "okay";
};
@@ -1112,6 +1114,8 @@
};
&rkvenc1 {
venc-supply = <&vdd_vdenc_s0>;
mem-supply = <&vdd_vdenc_mem_s0>;
status = "okay";
};

34
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
View File

@@ -3371,6 +3371,7 @@
rockchip,taskqueue-node = <7>;
rockchip,task-capacity = <8>;
power-domains = <&power RK3588_PD_VENC0>;
operating-points-v2 = <&venc_opp_table>;
status = "disabled";
};
@@ -3409,6 +3410,7 @@
rockchip,taskqueue-node = <7>;
rockchip,task-capacity = <8>;
power-domains = <&power RK3588_PD_VENC1>;
operating-points-v2 = <&venc_opp_table>;
status = "disabled";
};
@@ -3428,6 +3430,38 @@
status = "disabled";
};
venc_opp_table: venc-opp-table {
compatible = "operating-points-v2";
nvmem-cells = <&codec_leakage>;
nvmem-cell-names = "leakage";
rockchip,leakage-voltage-sel = <
1 8 0
9 20 1
21 254 2
>;
rockchip,grf = <&sys_grf>;
volt-mem-read-margin = <
855000 1
765000 2
675000 3
495000 4
>;
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <750000 750000 850000>,
<750000 750000 850000>;
opp-microvolt-L0 = <800000 800000 850000>,
<800000 800000 850000>;
opp-microvolt-L1 = <775000 775000 850000>,
<775000 775000 850000>;
opp-microvolt-L2 = <750000 750000 850000>,
<750000 750000 850000>;
};
};
rkvdec_ccu: rkvdec-ccu@fdc30000 {
compatible = "rockchip,rkv-decoder-v2-ccu";
reg = <0x0 0xfdc30000 0x0 0x100>;

1
arch/arm64/configs/rockchip_linux_defconfig
View File

@@ -508,6 +508,7 @@ CONFIG_CPU_PX30=y
CONFIG_CPU_RK1808=y
CONFIG_CPU_RK3328=y
CONFIG_CPU_RK3399=y
CONFIG_CPU_RK3528=y
CONFIG_CPU_RK3562=y
CONFIG_CPU_RK3568=y
CONFIG_CPU_RK3588=y

19
drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
View File

@@ -42,6 +42,7 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data,
struct dw_hdmi *hdmi = audio->hdmi;
u8 conf0 = 0;
u8 conf1 = 0;
u8 conf2 = 0;
u8 inputclkfs = 0;
/* it cares I2S only */
@@ -101,6 +102,23 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data,
return -EINVAL;
}
switch (fmt->bit_fmt) {
case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
conf1 = HDMI_AUD_CONF1_WIDTH_21;
conf2 = (hparms->channels == 8) ? HDMI_AUD_CONF2_HBR : HDMI_AUD_CONF2_NLPCM;
break;
default:
/*
* dw-hdmi introduced insert_pcuv bit in version 2.10a.
* When set (1'b1), this bit enables the insertion of the PCUV
* (Parity, Channel Status, User bit and Validity) bits on the
* incoming audio stream (support limited to Linear PCM audio)
*/
if (hdmi_read(audio, HDMI_DESIGN_ID) >= 0x21)
conf2 = HDMI_AUD_CONF2_INSERT_PCUV;
break;
}
dw_hdmi_set_sample_rate(hdmi, hparms->sample_rate);
dw_hdmi_set_channel_status(hdmi, hparms->iec.status);
dw_hdmi_set_channel_count(hdmi, hparms->channels);
@@ -109,6 +127,7 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data,
hdmi_write(audio, inputclkfs, HDMI_AUD_INPUTCLKFS);
hdmi_write(audio, conf0, HDMI_AUD_CONF0);
hdmi_write(audio, conf1, HDMI_AUD_CONF1);
hdmi_write(audio, conf2, HDMI_AUD_CONF2);
return 0;
}

19
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
View File

@@ -420,13 +420,18 @@ static void repo_hpd_event(struct work_struct *p_work)
if (hdmi->bridge.dev) {
bool change;
void *data = hdmi->plat_data->phy_data;
change = drm_helper_hpd_irq_event(hdmi->bridge.dev);
if (change && hdmi->cec_adap &&
hdmi->cec_adap->devnode.registered)
cec_queue_pin_hpd_event(hdmi->cec_adap,
hdmi->hpd_state,
ktime_get());
if (change) {
if (hdmi->plat_data->set_ddc_io)
hdmi->plat_data->set_ddc_io(data, hdmi->hpd_state);
if (hdmi->cec_adap->devnode.registered)
cec_queue_pin_hpd_event(hdmi->cec_adap,
hdmi->hpd_state,
ktime_get());
}
drm_bridge_hpd_notify(&hdmi->bridge, status);
}
}
@@ -4794,8 +4799,12 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
hdmi->bridge_is_on = true;
hdmi->phy.enabled = true;
hdmi->initialized = true;
if (hdmi->plat_data->set_ddc_io)
hdmi->plat_data->set_ddc_io(hdmi->plat_data->phy_data, true);
} else if (ret & HDMI_PHY_TX_PHY_LOCK) {
hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
if (hdmi->plat_data->set_ddc_io)
hdmi->plat_data->set_ddc_io(hdmi->plat_data->phy_data, false);
}
init_hpd_work(hdmi);

6
drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
View File

@@ -967,8 +967,14 @@ enum {
HDMI_AUD_CONF1_MODE_BURST_1 = 0x60,
HDMI_AUD_CONF1_MODE_BURST_2 = 0x80,
HDMI_AUD_CONF1_WIDTH_16 = 0x10,
HDMI_AUD_CONF1_WIDTH_21 = 0x15,
HDMI_AUD_CONF1_WIDTH_24 = 0x18,
/* AUD_CONF2 filed values */
HDMI_AUD_CONF2_HBR = 0x1,
HDMI_AUD_CONF2_NLPCM = 0x2,
HDMI_AUD_CONF2_INSERT_PCUV = 0x04,
/* AUD_CTS3 field values */
HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,

4
drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c
View File

@@ -1611,8 +1611,8 @@ static int dw_mipi_dsi2_probe(struct platform_device *pdev)
if (dsi2->te_gpio) {
ret = devm_request_threaded_irq(dsi2->dev, gpiod_to_irq(dsi2->te_gpio),
NULL, dw_mipi_dsi2_te_irq_handler,
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
dw_mipi_dsi2_te_irq_handler, NULL,
IRQF_TRIGGER_RISING | IRQF_ONESHOT,
"PANEL-TE", dsi2);
if (ret) {
dev_err(dsi2->dev, "failed to request TE IRQ: %d\n", ret);

39
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
View File

@@ -241,6 +241,9 @@ struct rockchip_hdmi {
struct delayed_work work;
struct workqueue_struct *workqueue;
struct gpio_desc *hpd_gpiod;
struct pinctrl *p;
struct pinctrl_state *idle_state;
struct pinctrl_state *default_state;
};
#define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x)
@@ -1516,6 +1519,24 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
enable_irq_wake(hdmi->hpd_irq);
}
hdmi->p = devm_pinctrl_get(hdmi->dev);
if (IS_ERR(hdmi->p)) {
dev_err(hdmi->dev, "could not get pinctrl\n");
return PTR_ERR(hdmi->p);
}
hdmi->idle_state = pinctrl_lookup_state(hdmi->p, "idle");
if (IS_ERR(hdmi->idle_state)) {
dev_dbg(hdmi->dev, "idle state is not defined\n");
return 0;
}
hdmi->default_state = pinctrl_lookup_state(hdmi->p, "default");
if (IS_ERR(hdmi->default_state)) {
dev_err(hdmi->dev, "could not find default state\n");
return PTR_ERR(hdmi->default_state);
}
return 0;
}
@@ -2450,6 +2471,22 @@ static void dw_hdmi_rockchip_set_prev_bus_format(void *data, unsigned long bus_f
hdmi->prev_bus_format = bus_format;
}
static void dw_hdmi_rockchip_set_ddc_io(void *data, bool enable)
{
struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
if (!hdmi->p || !hdmi->idle_state || !hdmi->default_state)
return;
if (!enable) {
if (pinctrl_select_state(hdmi->p, hdmi->idle_state))
dev_err(hdmi->dev, "could not select idle state\n");
} else {
if (pinctrl_select_state(hdmi->p, hdmi->default_state))
dev_err(hdmi->dev, "could not select default state\n");
}
}
static const struct drm_prop_enum_list color_depth_enum_list[] = {
{ 0, "Automatic" }, /* Prefer highest color depth */
{ 8, "24bit" },
@@ -3364,6 +3401,8 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
dw_hdmi_rockchip_check_hdr_color_change;
plat_data->set_prev_bus_format =
dw_hdmi_rockchip_set_prev_bus_format;
plat_data->set_ddc_io =
dw_hdmi_rockchip_set_ddc_io;
plat_data->property_ops = &dw_hdmi_rockchip_property_ops;
secondary = rockchip_hdmi_find_by_id(dev->driver, !hdmi->id);

3
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
View File

@@ -4086,6 +4086,9 @@ static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
{
struct rockchip_crtc_state *rockchip_state, *old_state;
if (WARN_ON(!crtc->state))
return NULL;
old_state = to_rockchip_crtc_state(crtc->state);
rockchip_state = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
if (!rockchip_state)

13
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -9791,12 +9791,22 @@ static struct drm_crtc_state *vop2_crtc_duplicate_state(struct drm_crtc *crtc)
struct rockchip_crtc_state *vcstate, *old_vcstate;
struct vop2_video_port *vp = to_vop2_video_port(crtc);
if (WARN_ON(!crtc->state))
return NULL;
old_vcstate = to_rockchip_crtc_state(crtc->state);
vcstate = kmemdup(old_vcstate, sizeof(*old_vcstate), GFP_KERNEL);
if (!vcstate)
return NULL;
vcstate->vp_id = vp->id;
if (vcstate->hdr_ext_data)
drm_property_blob_get(vcstate->hdr_ext_data);
if (vcstate->acm_lut_data)
drm_property_blob_get(vcstate->acm_lut_data);
if (vcstate->post_csc_data)
drm_property_blob_get(vcstate->post_csc_data);
__drm_atomic_helper_crtc_duplicate_state(crtc, &vcstate->base);
return &vcstate->base;
}
@@ -9807,6 +9817,9 @@ static void vop2_crtc_destroy_state(struct drm_crtc *crtc,
struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(state);
__drm_atomic_helper_crtc_destroy_state(&vcstate->base);
drm_property_blob_put(vcstate->hdr_ext_data);
drm_property_blob_put(vcstate->acm_lut_data);
drm_property_blob_put(vcstate->post_csc_data);
kfree(vcstate);
}

2
drivers/media/platform/rockchip/cif/capture.c
View File

@@ -6494,7 +6494,7 @@ static const struct v4l2_ioctl_ops rkcif_v4l2_ioctl_ops = {
.vidioc_default = rkcif_ioctl_default,
};
void rkcif_vb_done_oneframe(struct rkcif_stream *stream,
static void rkcif_vb_done_oneframe(struct rkcif_stream *stream,
struct vb2_v4l2_buffer *vb_done)
{
const struct cif_output_fmt *fmt = stream->cif_fmt_out;

7
drivers/media/platform/rockchip/isp/capture.c
View File

@@ -1559,7 +1559,12 @@ static void rkisp_buf_done_task(unsigned long arg)
buf = list_first_entry(&local_list,
struct rkisp_buffer, queue);
list_del(&buf->queue);
vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
v4l2_dbg(2, rkisp_debug, &stream->ispdev->v4l2_dev,
"stream:%d seq:%d buf:0x%x done\n",
stream->id, buf->vb.sequence, buf->buff_addr[0]);
vb2_buffer_done(&buf->vb.vb2_buf,
stream->streaming ? VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR);
}
}

6
drivers/media/platform/rockchip/isp/capture_v20.c
View File

@@ -1739,6 +1739,12 @@ static void destroy_buf_queue(struct rkisp_stream *stream,
list_del(&buf->queue);
vb2_buffer_done(&buf->vb.vb2_buf, state);
}
while (!list_empty(&stream->buf_done_list)) {
buf = list_first_entry(&stream->buf_done_list,
struct rkisp_buffer, queue);
list_del(&buf->queue);
vb2_buffer_done(&buf->vb.vb2_buf, state);
}
spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
}

20
drivers/media/platform/rockchip/isp/capture_v21.c
View File

@@ -1388,15 +1388,8 @@ static void rkisp_stream_stop(struct rkisp_stream *stream)
static int rkisp_start(struct rkisp_stream *stream)
{
struct rkisp_device *dev = stream->ispdev;
bool is_update = false;
int ret;
if (stream->id == RKISP_STREAM_MP || stream->id == RKISP_STREAM_SP) {
is_update = (stream->id == RKISP_STREAM_MP) ?
!dev->cap_dev.stream[RKISP_STREAM_SP].streaming :
!dev->cap_dev.stream[RKISP_STREAM_MP].streaming;
}
if (stream->ops->set_data_path)
stream->ops->set_data_path(stream);
ret = stream->ops->config_mi(stream);
@@ -1406,9 +1399,6 @@ static int rkisp_start(struct rkisp_stream *stream)
stream->ops->enable_mi(stream);
if (stream->id == RKISP_STREAM_MP || stream->id == RKISP_STREAM_SP)
hdr_config_dmatx(dev);
if (is_update)
dev->irq_ends_mask |=
(stream->id == RKISP_STREAM_MP) ? ISP_FRAME_MP : ISP_FRAME_SP;
stream->streaming = true;
return 0;
@@ -1556,6 +1546,12 @@ static void destroy_buf_queue(struct rkisp_stream *stream,
list_del(&buf->queue);
vb2_buffer_done(&buf->vb.vb2_buf, state);
}
while (!list_empty(&stream->buf_done_list)) {
buf = list_first_entry(&stream->buf_done_list,
struct rkisp_buffer, queue);
list_del(&buf->queue);
vb2_buffer_done(&buf->vb.vb2_buf, state);
}
spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
}
@@ -1959,16 +1955,12 @@ void rkisp_mi_v21_isr(u32 mis_val, struct rkisp_device *dev)
stream = &dev->cap_dev.stream[RKISP_STREAM_MP];
if (!stream->streaming)
dev->irq_ends_mask &= ~ISP_FRAME_MP;
else
dev->irq_ends_mask |= ISP_FRAME_MP;
rkisp_check_idle(dev, ISP_FRAME_MP);
}
if (mis_val & CIF_MI_SP_FRAME) {
stream = &dev->cap_dev.stream[RKISP_STREAM_SP];
if (!stream->streaming)
dev->irq_ends_mask &= ~ISP_FRAME_SP;
else
dev->irq_ends_mask |= ISP_FRAME_SP;
rkisp_check_idle(dev, ISP_FRAME_SP);
}
}

22
drivers/media/platform/rockchip/isp/capture_v30.c
View File

@@ -1029,11 +1029,13 @@ static void rkisp_stream_stop(struct rkisp_stream *stream)
bool is_wait = dev->hw_dev->is_shutdown ? false : true;
stream->stopping = true;
stream->ops->disable_mi(stream);
if (dev->hw_dev->is_single)
stream->ops->disable_mi(stream);
if (IS_HDR_RDBK(dev->rd_mode)) {
spin_lock_irqsave(&dev->hw_dev->rdbk_lock, lock_flags);
if (dev->hw_dev->cur_dev_id != dev->dev_id || dev->hw_dev->is_idle) {
is_wait = false;
stream->ops->disable_mi(stream);
/* force update to close */
if (dev->hw_dev->is_single)
stream_self_update(stream);
@@ -1074,8 +1076,6 @@ static void rkisp_stream_stop(struct rkisp_stream *stream)
*/
static int rkisp_start(struct rkisp_stream *stream)
{
struct rkisp_device *dev = stream->ispdev;
bool is_update = atomic_read(&dev->cap_dev.refcnt) > 1 ? false : true;
int ret;
if (stream->ops->set_data_path)
@@ -1085,8 +1085,6 @@ static int rkisp_start(struct rkisp_stream *stream)
return ret;
stream->ops->enable_mi(stream);
if (is_update)
dev->irq_ends_mask |= get_stream_irq_mask(stream);
stream->streaming = true;
return 0;
@@ -1218,6 +1216,12 @@ static void destroy_buf_queue(struct rkisp_stream *stream,
list_del(&buf->queue);
vb2_buffer_done(&buf->vb.vb2_buf, state);
}
while (!list_empty(&stream->buf_done_list)) {
buf = list_first_entry(&stream->buf_done_list,
struct rkisp_buffer, queue);
list_del(&buf->queue);
vb2_buffer_done(&buf->vb.vb2_buf, state);
}
spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
}
@@ -1715,32 +1719,24 @@ void rkisp_mi_v30_isr(u32 mis_val, struct rkisp_device *dev)
stream = &dev->cap_dev.stream[RKISP_STREAM_MP];
if (!stream->streaming)
dev->irq_ends_mask &= ~ISP_FRAME_MP;
else
dev->irq_ends_mask |= ISP_FRAME_MP;
rkisp_check_idle(dev, ISP_FRAME_MP);
}
if (mis_val & ISP3X_MI_SP_FRAME) {
stream = &dev->cap_dev.stream[RKISP_STREAM_SP];
if (!stream->streaming)
dev->irq_ends_mask &= ~ISP_FRAME_SP;
else
dev->irq_ends_mask |= ISP_FRAME_SP;
rkisp_check_idle(dev, ISP_FRAME_SP);
}
if (mis_val & ISP3X_MI_MPFBC_FRAME) {
stream = &dev->cap_dev.stream[RKISP_STREAM_FBC];
if (!stream->streaming)
dev->irq_ends_mask &= ~ISP_FRAME_MPFBC;
else
dev->irq_ends_mask |= ISP_FRAME_MPFBC;
rkisp_check_idle(dev, ISP_FRAME_MPFBC);
}
if (mis_val & ISP3X_MI_BP_FRAME) {
stream = &dev->cap_dev.stream[RKISP_STREAM_BP];
if (!stream->streaming)
dev->irq_ends_mask &= ~ISP_FRAME_BP;
else
dev->irq_ends_mask |= ISP_FRAME_BP;
rkisp_check_idle(dev, ISP_FRAME_BP);
}
}

27
drivers/media/platform/rockchip/isp/capture_v32.c
View File

@@ -1438,12 +1438,14 @@ static void rkisp_stream_stop(struct rkisp_stream *stream)
stream->stopping = true;
stream->is_pause = false;
if (stream->ops->disable_mi)
if (stream->ops->disable_mi && dev->hw_dev->is_single)
stream->ops->disable_mi(stream);
if (IS_HDR_RDBK(dev->rd_mode)) {
spin_lock_irqsave(&dev->hw_dev->rdbk_lock, lock_flags);
if (dev->hw_dev->cur_dev_id != dev->dev_id || dev->hw_dev->is_idle) {
is_wait = false;
if (stream->ops->disable_mi)
stream->ops->disable_mi(stream);
/* force update to close */
if (dev->hw_dev->is_single)
stream_self_update(stream);
@@ -1489,7 +1491,6 @@ static void rkisp_stream_stop(struct rkisp_stream *stream)
static int rkisp_start(struct rkisp_stream *stream)
{
struct rkisp_device *dev = stream->ispdev;
bool is_update = atomic_read(&dev->cap_dev.refcnt) > 1 ? false : true;
int ret;
if (stream->ops->set_data_path)
@@ -1504,10 +1505,7 @@ static int rkisp_start(struct rkisp_stream *stream)
if (stream->ops->enable_mi && !stream->is_pause)
stream->ops->enable_mi(stream);
if (is_update)
dev->irq_ends_mask |= get_stream_irq_mask(stream);
stream->streaming = true;
return 0;
}
@@ -1672,6 +1670,13 @@ static void destroy_buf_queue(struct rkisp_stream *stream,
if (buf->vb.vb2_buf.memory)
vb2_buffer_done(&buf->vb.vb2_buf, state);
}
while (!list_empty(&stream->buf_done_list)) {
buf = list_first_entry(&stream->buf_done_list,
struct rkisp_buffer, queue);
list_del(&buf->queue);
if (buf->vb.vb2_buf.memory)
vb2_buffer_done(&buf->vb.vb2_buf, state);
}
rkisp_rockit_buf_free(stream);
spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
}
@@ -2268,26 +2273,20 @@ void rkisp_mi_v32_isr(u32 mis_val, struct rkisp_device *dev)
if (mis_val & ISP3X_MI_MP_FRAME) {
stream = &dev->cap_dev.stream[RKISP_STREAM_MP];
if (!stream->streaming || stream->is_pause)
if (!stream->streaming)
dev->irq_ends_mask &= ~ISP_FRAME_MP;
else
dev->irq_ends_mask |= ISP_FRAME_MP;
rkisp_check_idle(dev, ISP_FRAME_MP);
}
if (mis_val & ISP3X_MI_SP_FRAME) {
stream = &dev->cap_dev.stream[RKISP_STREAM_SP];
if (!stream->streaming || stream->is_pause)
if (!stream->streaming)
dev->irq_ends_mask &= ~ISP_FRAME_SP;
else
dev->irq_ends_mask |= ISP_FRAME_SP;
rkisp_check_idle(dev, ISP_FRAME_SP);
}
if (mis_val & ISP3X_MI_BP_FRAME) {
stream = &dev->cap_dev.stream[RKISP_STREAM_BP];
if (!stream->streaming || stream->is_pause)
if (!stream->streaming)
dev->irq_ends_mask &= ~ISP_FRAME_BP;
else
dev->irq_ends_mask |= ISP_FRAME_BP;
rkisp_check_idle(dev, ISP_FRAME_BP);
}
}

47
drivers/media/platform/rockchip/isp/rkisp.c
View File

@@ -703,22 +703,6 @@ void rkisp_trigger_read_back(struct rkisp_device *dev, u8 dma2frm, u32 mode, boo
dev->multi_mode, dev->multi_index, val);
}
is_upd = true;
/* if output stream enable, wait it end */
val = rkisp_read(dev, CIF_MI_CTRL_SHD, true);
if (val & CIF_MI_CTRL_SHD_MP_OUT_ENABLED &&
!(dev->irq_ends_mask & ISP_FRAME_MP))
dev->irq_ends_mask |= ISP_FRAME_MP;
if (val & CIF_MI_CTRL_SHD_SP_OUT_ENABLED &&
!(dev->irq_ends_mask & ISP_FRAME_SP))
dev->irq_ends_mask |= ISP_FRAME_SP;
if (dev->isp_ver == ISP_V30 &&
!(dev->irq_ends_mask & ISP_FRAME_MPFBC) &&
rkisp_read(dev, ISP3X_MPFBC_CTRL, true) & ISP3X_MPFBC_EN_SHD)
dev->irq_ends_mask |= ISP_FRAME_MPFBC;
if (dev->isp_ver == ISP_V32 &&
!(dev->irq_ends_mask & ISP_FRAME_BP) &&
rkisp_read(dev, ISP32_MI_WR_CTRL2_SHD, true) & ISP32_BP_EN_OUT_SHD)
dev->irq_ends_mask |= ISP_FRAME_BP;
}
if (dev->isp_ver > ISP_V20)
@@ -779,6 +763,31 @@ run_next:
if (is_3dlut_upd)
rkisp_unite_write(dev, ISP_3DLUT_UPDATE, 1, true, hw->is_unite);
/* if output stream enable, wait it end */
val = rkisp_read(dev, CIF_MI_CTRL_SHD, true);
if (val & CIF_MI_CTRL_SHD_MP_OUT_ENABLED)
dev->irq_ends_mask |= ISP_FRAME_MP;
else
dev->irq_ends_mask &= ~ISP_FRAME_MP;
if (val & CIF_MI_CTRL_SHD_SP_OUT_ENABLED)
dev->irq_ends_mask |= ISP_FRAME_SP;
else
dev->irq_ends_mask &= ~ISP_FRAME_SP;
if ((dev->isp_ver == ISP_V20 &&
rkisp_read(dev, ISP_MPFBC_CTRL, true) & SW_MPFBC_EN) ||
(dev->isp_ver == ISP_V30 &&
rkisp_read(dev, ISP3X_MPFBC_CTRL, true) & ISP3X_MPFBC_EN_SHD))
dev->irq_ends_mask |= ISP_FRAME_MPFBC;
else
dev->irq_ends_mask &= ~ISP_FRAME_MPFBC;
if ((dev->isp_ver == ISP_V30 &&
rkisp_read(dev, ISP3X_BP_ENABLE, true) & ISP3X_BP_ENABLE) ||
(dev->isp_ver == ISP_V32 &&
rkisp_read(dev, ISP32_MI_WR_CTRL2_SHD, true) & ISP32_BP_EN_OUT_SHD))
dev->irq_ends_mask |= ISP_FRAME_BP;
else
dev->irq_ends_mask &= ~ISP_FRAME_BP;
val = rkisp_read(dev, CSI2RX_CTRL0, true);
val &= ~SW_IBUF_OP_MODE(0xf);
tmp = SW_IBUF_OP_MODE(dev->rd_mode);
@@ -1019,6 +1028,8 @@ end:
schedule_work(&dev->rdbk_work);
else
rkisp_rdbk_trigger_event(dev, T_CMD_END, NULL);
if (dev->isp_state == ISP_STOP)
wake_up(&dev->sync_onoff);
}
static void rkisp_set_state(u32 *state, u32 val)
@@ -2826,6 +2837,10 @@ static int rkisp_isp_sd_s_stream(struct v4l2_subdev *sd, int on)
wake_up(&s->done);
}
}
wait_event_timeout(isp_dev->sync_onoff,
isp_dev->isp_state & ISP_STOP ||
!IS_HDR_RDBK(isp_dev->rd_mode),
msecs_to_jiffies(50));
rkisp_isp_stop(isp_dev);
atomic_dec(&hw_dev->refcnt);
rkisp_params_stream_stop(&isp_dev->params_vdev);

116
drivers/video/rockchip/mpp/mpp_rkvenc2.c
View File

@@ -282,6 +282,11 @@ struct rkvenc_dev {
dma_addr_t sram_iova;
u32 sram_enabled;
struct page *rcb_page;
#ifdef CONFIG_PM_DEVFREQ
struct rockchip_opp_info opp_info;
struct monitor_dev_info *mdev_info;
#endif
};
struct rkvenc_ccu {
@@ -1674,6 +1679,101 @@ static inline int rkvenc_procfs_ccu_init(struct mpp_dev *mpp)
}
#endif
#ifdef CONFIG_PM_DEVFREQ
static int rk3588_venc_set_read_margin(struct device *dev,
struct rockchip_opp_info *opp_info,
u32 rm)
{
if (!opp_info->grf || !opp_info->volt_rm_tbl)
return 0;
if (rm == opp_info->current_rm || rm == UINT_MAX)
return 0;
dev_dbg(dev, "set rm to %d\n", rm);
regmap_write(opp_info->grf, 0x214, 0x001c0000 | (rm << 2));
regmap_write(opp_info->grf, 0x218, 0x001c0000 | (rm << 2));
regmap_write(opp_info->grf, 0x220, 0x003c0000 | (rm << 2));
regmap_write(opp_info->grf, 0x224, 0x003c0000 | (rm << 2));
opp_info->current_rm = rm;
return 0;
}
static const struct rockchip_opp_data rk3588_venc_opp_data = {
.set_read_margin = rk3588_venc_set_read_margin,
};
static const struct of_device_id rockchip_rkvenc_of_match[] = {
{
.compatible = "rockchip,rk3588",
.data = (void *)&rk3588_venc_opp_data,
},
{},
};
static struct monitor_dev_profile venc_mdevp = {
.type = MONITOR_TPYE_DEV,
.update_volt = rockchip_monitor_check_rate_volt,
};
static int rkvenc_devfreq_init(struct mpp_dev *mpp)
{
struct rkvenc_dev *enc = to_rkvenc_dev(mpp);
struct clk *clk_core = enc->core_clk_info.clk;
struct device *dev = mpp->dev;
struct opp_table *reg_table = NULL;
struct opp_table *clk_table = NULL;
const char *const reg_names[] = { "venc", "mem" };
int ret = 0;
if (!clk_core)
return 0;
if (of_find_property(dev->of_node, "venc-supply", NULL) &&
of_find_property(dev->of_node, "mem-supply", NULL)) {
reg_table = dev_pm_opp_set_regulators(dev, reg_names, 2);
if (IS_ERR(reg_table))
return PTR_ERR(reg_table);
} else {
reg_table = dev_pm_opp_set_regulators(dev, reg_names, 1);
if (IS_ERR(reg_table))
return PTR_ERR(reg_table);
}
clk_table = dev_pm_opp_set_clkname(dev, "clk_core");
if (IS_ERR(clk_table))
return PTR_ERR(clk_table);
rockchip_get_opp_data(rockchip_rkvenc_of_match, &enc->opp_info);
ret = rockchip_init_opp_table(dev, &enc->opp_info, "leakage", "venc");
if (ret) {
dev_err(dev, "failed to init_opp_table\n");
return ret;
}
enc->mdev_info = rockchip_system_monitor_register(dev, &venc_mdevp);
if (IS_ERR(enc->mdev_info)) {
dev_dbg(dev, "without system monitor\n");
enc->mdev_info = NULL;
}
return ret;
}
static int rkvenc_devfreq_remove(struct mpp_dev *mpp)
{
struct rkvenc_dev *enc = to_rkvenc_dev(mpp);
if (enc->mdev_info)
rockchip_system_monitor_unregister(enc->mdev_info);
return 0;
}
#endif
static int rkvenc_init(struct mpp_dev *mpp)
{
struct rkvenc_dev *enc = to_rkvenc_dev(mpp);
@@ -1710,6 +1810,21 @@ static int rkvenc_init(struct mpp_dev *mpp)
if (!enc->rst_core)
mpp_err("No core reset resource define\n");
#ifdef CONFIG_PM_DEVFREQ
ret = rkvenc_devfreq_init(mpp);
if (ret)
mpp_err("failed to add venc devfreq\n");
#endif
return 0;
}
static int rkvenc_exit(struct mpp_dev *mpp)
{
#ifdef CONFIG_PM_DEVFREQ
rkvenc_devfreq_remove(mpp);
#endif
return 0;
}
@@ -1979,6 +2094,7 @@ task_done_ret:
static struct mpp_hw_ops rkvenc_hw_ops = {
.init = rkvenc_init,
.exit = rkvenc_exit,
.clk_on = rkvenc_clk_on,
.clk_off = rkvenc_clk_off,
.set_freq = rkvenc_set_freq,

1
include/drm/bridge/dw_hdmi.h
View File

@@ -256,6 +256,7 @@ struct dw_hdmi_plat_data {
bool (*check_hdr_color_change)(struct drm_connector_state *conn_state, void *data);
void (*set_prev_bus_format)(void *data, unsigned long bus_format);
int (*get_colorimetry)(void *data, struct edid *edid);
void (*set_ddc_io)(void *data, bool enable);
/* Vendor Property support */
const struct dw_hdmi_property_ops *property_ops;