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drm/rockchip: vop2: Add support for rk3588
RK3588 VOP: 4 Video Ports. 4 Cluster Windows. 4 Esmart Windows. Can drive HDMI/eDP/DP/MIPI/BT1120/BT656 interface. Support drive HDMI/DP 8k output in splice mode. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Change-Id: I37df329fcab729cd7fa1de47c4d5faf232bb265f
This commit is contained in:
Andy Yan
@@ -105,6 +105,10 @@ struct rockchip_crtc_state {
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int output_bpc;
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int output_flags;
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bool enable_afbc;
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/**
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* @splice_mode: enabled when display a hdisplay > 4096 on rk3588
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*/
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bool splice_mode;
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struct drm_tv_connector_state *tv_state;
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int left_margin;
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@@ -135,6 +139,8 @@ struct rockchip_crtc_state {
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u32 background;
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u32 line_flag;
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u8 mode_update;
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u8 dsc_enable;
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unsigned long dsc_clk;
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struct rockchip_hdr_state hdr;
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};
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@@ -18,6 +18,9 @@
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#define VOP_MAJOR(version) ((version) >> 8)
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#define VOP_MINOR(version) ((version) & 0xff)
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#define VOP_VERSION_RK3568 VOP_VERSION(0x40, 0x15)
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#define VOP_VERSION_RK3588 VOP_VERSION(0x40, 0x17)
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#define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0)
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#define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1)
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#define ROCKCHIP_OUTPUT_DATA_SWAP BIT(2)
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@@ -31,15 +34,20 @@
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#define VOP_FEATURE_ALPHA_SCALE BIT(2)
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#define VOP_FEATURE_ALPHA_HDR10 BIT(3)
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#define VOP_FEATURE_ALPHA_DOLBY_HDR BIT(4)
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/* a feature to splice two windows and two vps to support resolution > 4096 */
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#define VOP_FEATURE_SPLICE BIT(5)
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#define VOP_FEATURE_OUTPUT_10BIT VOP_FEATURE_OUTPUT_RGB10
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#define WIN_FEATURE_HDR2SDR BIT(0)
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#define WIN_FEATURE_SDR2HDR BIT(1)
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#define WIN_FEATURE_PRE_OVERLAY BIT(2)
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#define WIN_FEATURE_AFBDC BIT(3)
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#define WIN_FEATURE_CLUSTER_MAIN BIT(4)
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#define WIN_FEATURE_CLUSTER_SUB BIT(5)
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/* Left win in splice mode */
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#define WIN_FEATURE_SPLICE_LEFT BIT(6)
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/* a mirror win can only get fb address
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* from source win:
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* Cluster1---->Cluster0
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@@ -640,6 +648,18 @@ struct vop2_video_port_regs {
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struct vop_reg cubic_lut_en;
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struct vop_reg cubic_lut_update_en;
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struct vop_reg cubic_lut_mst;
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/* cru */
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struct vop_reg dclk_core_div;
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struct vop_reg dclk_out_div;
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struct vop_reg dclk_src_sel;
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struct vop_reg splice_en;
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};
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struct vop2_dsc_regs {
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struct vop_reg rst_deassert;
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struct vop_reg port_mux;
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};
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struct vop2_wb_regs {
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@@ -658,9 +678,26 @@ struct vop2_wb_regs {
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struct vop_reg axi_uv_id;
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};
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/*
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* connector interface(RGB/HDMI/eDP/DP/MIPI) data
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*/
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struct vop2_connector_if_data {
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u32 id;
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const char *clk_src_name;
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const char *clk_parent_name;
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const char *pixclk_name;
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const char *dclk_name;
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u32 post_proc_div_shift;
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u32 if_div_shift;
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u32 if_div_yuv420_shift;
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u32 bus_div_shift;
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u32 pixel_clk_div_shift;
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};
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struct vop2_win_data {
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const char *name;
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uint8_t phys_id;
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uint8_t splice_win_id;
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uint32_t base;
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enum drm_plane_type type;
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@@ -692,6 +729,11 @@ struct vop2_win_data {
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const uint8_t dly[VOP2_DLY_MODE_MAX];
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};
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struct vop2_dsc_data {
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char id;
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const struct vop2_dsc_regs *regs;
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};
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struct vop2_wb_data {
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uint32_t nformats;
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const uint32_t *formats;
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@@ -701,10 +743,12 @@ struct vop2_wb_data {
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struct vop2_video_port_data {
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char id;
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uint8_t splice_vp_id;
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uint32_t feature;
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uint64_t soc_id[VOP2_SOC_VARIANT];
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uint16_t gamma_lut_len;
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uint16_t cubic_lut_len;
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unsigned long dclk_max;
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struct vop_rect max_output;
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const u8 pre_scan_max_dly[4];
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const struct vop_intr *intr;
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@@ -812,8 +856,9 @@ struct vop2_ctrl {
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struct vop_reg dp_dclk_pol;
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struct vop_reg dp_pin_pol;
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struct vop_reg win_vp_id[8];
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struct vop_reg win_dly[8];
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/* This will be reference by win_phy_id */
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struct vop_reg win_vp_id[16];
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struct vop_reg win_dly[16];
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/* connector mux */
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struct vop_reg rgb_mux;
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@@ -832,6 +877,19 @@ struct vop2_ctrl {
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struct vop_reg lvds_dual_mode;
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struct vop_reg lvds_dual_channel_swap;
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struct vop_reg hdmi0_dclk_div;
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struct vop_reg hdmi0_pixclk_div;
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struct vop_reg edp0_dclk_div;
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struct vop_reg edp0_pixclk_div;
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struct vop_reg hdmi1_dclk_div;
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struct vop_reg hdmi1_pixclk_div;
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struct vop_reg edp1_dclk_div;
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struct vop_reg edp1_pixclk_div;
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struct vop_reg mipi0_pixclk_div;
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struct vop_reg mipi1_pixclk_div;
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struct vop_reg cluster0_src_color_ctrl;
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struct vop_reg cluster0_dst_color_ctrl;
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struct vop_reg cluster0_src_alpha_ctrl;
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@@ -859,15 +917,19 @@ struct vop2_ctrl {
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struct vop2_data {
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uint32_t version;
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uint32_t feature;
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uint8_t nr_dscs;
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uint8_t nr_vps;
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uint8_t nr_mixers;
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uint8_t nr_layers;
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uint8_t nr_axi_intr;
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uint8_t nr_gammas;
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uint8_t nr_conns;
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const struct vop_intr *axi_intr;
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const struct vop2_ctrl *ctrl;
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const struct vop2_dsc_data *dsc;
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const struct vop2_win_data *win;
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const struct vop2_video_port_data *vp;
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const struct vop2_connector_if_data *conn;
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const struct vop2_wb_data *wb;
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const struct vop2_layer_data *layer;
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const struct vop_csc_table *csc_table;
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File diff suppressed because it is too large
Load Diff
324
drivers/gpu/drm/rockchip/rockchip_vop2_clk.c
Normal file
324
drivers/gpu/drm/rockchip/rockchip_vop2_clk.c
Normal file
@@ -0,0 +1,324 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2021 Rockchip Electronics Co. Ltd.
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* Author: Elaine Zhang <zhangqing@rock-chips.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/log2.h>
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static int cru_debug;
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#define cru_dbg(format, ...) do { \
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if (cru_debug) \
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pr_info("%s: " format, __func__, ## __VA_ARGS__); \
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} while (0)
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#define PNAME(x) static const char *const x[]
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enum vop_clk_branch_type {
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branch_mux,
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branch_divider,
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branch_factor,
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branch_virtual,
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};
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#define VIR(cname) \
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{ \
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.branch_type = branch_virtual, \
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.name = cname, \
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}
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#define MUX(cname, pnames, f) \
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{ \
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.branch_type = branch_mux, \
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.name = cname, \
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.parent_names = pnames, \
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.num_parents = ARRAY_SIZE(pnames), \
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.flags = f, \
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}
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#define FACTOR(cname, pname, f) \
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{ \
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.branch_type = branch_factor, \
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.name = cname, \
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.parent_names = (const char *[]){ pname }, \
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.num_parents = 1, \
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.flags = f, \
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}
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#define DIV(cname, pname, f, w) \
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{ \
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.branch_type = branch_divider, \
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.name = cname, \
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.parent_names = (const char *[]){ pname }, \
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.num_parents = 1, \
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.flags = f, \
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.div_width = w, \
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}
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struct vop2_clk_branch {
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enum vop_clk_branch_type branch_type;
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const char *name;
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const char *const *parent_names;
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u8 num_parents;
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unsigned long flags;
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u8 div_shift;
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u8 div_width;
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u8 div_flags;
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};
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PNAME(mux_port0_dclk_src_p) = { "dclk0", "dclk1" };
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PNAME(mux_port2_dclk_src_p) = { "dclk2", "dclk1" };
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PNAME(mux_dp_pixclk_p) = { "dclk_out0", "dclk_out1", "dclk_out2" };
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PNAME(mux_hdmi_edp_clk_src_p) = { "dclk0", "dclk1", "dclk2" };
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PNAME(mux_mipi_clk_src_p) = { "dclk_out2", "dclk_out3" };
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PNAME(mux_dsc_8k_clk_src_p) = { "dclk0", "dclk1", "dclk2", "dclk3" };
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PNAME(mux_dsc_4k_clk_src_p) = { "dclk0", "dclk1", "dclk2", "dclk3" };
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/*
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* We only use this clk driver calculate the div
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* of dclk_core/dclk_out/if_pixclk/if_dclk and
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* the rate of the dclk from the soc.
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*
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* We don't touch the cru in the vop here, as
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* these registers has special read andy write
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* limits.
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*/
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static struct vop2_clk_branch rk3588_vop_clk_branches[] = {
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VIR("dclk0"),
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VIR("dclk1"),
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VIR("dclk2"),
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VIR("dclk3"),
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MUX("port0_dclk_src", mux_port0_dclk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
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DIV("dclk_core0", "port0_dclk_src", CLK_SET_RATE_PARENT, 2),
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DIV("dclk_out0", "port0_dclk_src", CLK_SET_RATE_PARENT, 2),
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FACTOR("port1_dclk_src", "dclk1", CLK_SET_RATE_PARENT),
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DIV("dclk_core1", "port1_dclk_src", CLK_SET_RATE_PARENT, 2),
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DIV("dclk_out1", "port1_dclk_src", CLK_SET_RATE_PARENT, 2),
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MUX("port2_dclk_src", mux_port2_dclk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
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DIV("dclk_core2", "port2_dclk_src", CLK_SET_RATE_PARENT, 2),
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DIV("dclk_out2", "port2_dclk_src", CLK_SET_RATE_PARENT, 2),
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FACTOR("port3_dclk_src", "dclk3", CLK_SET_RATE_PARENT),
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DIV("dclk_core3", "port3_dclk_src", CLK_SET_RATE_PARENT, 2),
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DIV("dclk_out3", "port3_dclk_src", CLK_SET_RATE_PARENT, 2),
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MUX("dp0_pixclk", mux_dp_pixclk_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
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MUX("dp1_pixclk", mux_dp_pixclk_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
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MUX("hdmi_edp0_clk_src", mux_hdmi_edp_clk_src_p,
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
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DIV("hdmi_edp0_dclk", "hdmi_edp0_clk_src", 0, 2),
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DIV("hdmi_edp0_pixclk", "hdmi_edp0_clk_src", CLK_SET_RATE_PARENT, 1),
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MUX("hdmi_edp1_clk_src", mux_hdmi_edp_clk_src_p,
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
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DIV("hdmi_edp1_dclk", "hdmi_edp1_clk_src", 0, 2),
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DIV("hdmi_edp1_pixclk", "hdmi_edp1_clk_src", CLK_SET_RATE_PARENT, 2),
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MUX("mipi0_clk_src", mux_mipi_clk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
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DIV("mipi0_pixclk", "mipi0_clk_src", CLK_SET_RATE_PARENT, 2),
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MUX("mipi1_clk_src", mux_mipi_clk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
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DIV("mipi1_pixclk", "mipi1_clk_src", CLK_SET_RATE_PARENT, 2),
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FACTOR("rgb_pixclk", "port3_dclk_src", CLK_SET_RATE_PARENT),
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MUX("dsc_8k_clk_src", mux_dsc_8k_clk_src_p, CLK_SET_RATE_NO_REPARENT),
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DIV("dsc_8k_pixclk", "dsc_8k_clk_src", 0, 2),
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DIV("dsc_8k_cds_clk", "dsc_8k_pixclk", 0, 2),
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DIV("dsc_8k_slice_clk", "dsc_8k_pixclk", 0, 2),
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MUX("dsc_4k_clk_src", mux_dsc_4k_clk_src_p, CLK_SET_RATE_NO_REPARENT),
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DIV("dsc_4k_pixclk", "dsc_4k_clk_src", 0, 2),
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DIV("dsc_4k_cds_clk", "dsc_4k_pixclk", 0, 2),
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DIV("dsc_4k_slice_clk", "dsc_4k_pixclk", 0, 2),
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};
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static unsigned long clk_virtual_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct vop2_clk *vop2_clk = to_vop2_clk(hw);
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return (unsigned long)vop2_clk->rate;
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}
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static long clk_virtual_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct vop2_clk *vop2_clk = to_vop2_clk(hw);
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vop2_clk->rate = rate;
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return rate;
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}
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static int clk_virtual_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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return 0;
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}
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const struct clk_ops clk_virtual_ops = {
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.round_rate = clk_virtual_round_rate,
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.set_rate = clk_virtual_set_rate,
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.recalc_rate = clk_virtual_recalc_rate,
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};
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static u8 vop2_mux_get_parent(struct clk_hw *hw)
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{
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struct vop2_clk *vop2_clk = to_vop2_clk(hw);
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cru_dbg("%s index: %d\n", clk_hw_get_name(hw), vop2_clk->parent_index);
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return vop2_clk->parent_index;
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}
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static int vop2_mux_set_parent(struct clk_hw *hw, u8 index)
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{
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struct vop2_clk *vop2_clk = to_vop2_clk(hw);
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vop2_clk->parent_index = index;
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cru_dbg("%s index: %d\n", clk_hw_get_name(hw), index);
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return 0;
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}
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static int vop2_clk_mux_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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cru_dbg("%s %ld(min: %ld max: %ld)\n",
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clk_hw_get_name(hw), req->rate, req->min_rate, req->max_rate);
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return __clk_mux_determine_rate(hw, req);
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}
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static const struct clk_ops vop2_mux_clk_ops = {
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.get_parent = vop2_mux_get_parent,
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.set_parent = vop2_mux_set_parent,
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.determine_rate = vop2_clk_mux_determine_rate,
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};
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#define div_mask(width) ((1 << (width)) - 1)
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static int vop2_div_get_val(unsigned long rate, unsigned long parent_rate)
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{
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unsigned int div, value;
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div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
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value = ilog2(div);
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return value;
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}
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static unsigned long vop2_clk_div_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct vop2_clk *vop2_clk = to_vop2_clk(hw);
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unsigned long rate;
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unsigned int div;
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div = 1 << vop2_clk->div_val;
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rate = parent_rate / div;
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cru_dbg("%s rate: %ld(prate: %ld)\n", clk_hw_get_name(hw), rate, parent_rate);
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return rate;
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}
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|
||||
static long vop2_clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
|
||||
if (*prate < rate)
|
||||
*prate = rate;
|
||||
}
|
||||
|
||||
cru_dbg("%s rate: %ld(prate: %ld)\n", clk_hw_get_name(hw), rate, *prate);
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
||||
static int vop2_clk_div_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate)
|
||||
{
|
||||
struct vop2_clk *vop2_clk = to_vop2_clk(hw);
|
||||
int div_val;
|
||||
|
||||
div_val = vop2_div_get_val(rate, parent_rate);
|
||||
vop2_clk->div_val = div_val;
|
||||
|
||||
cru_dbg("%s prate: %ld rate: %ld div_val: %d\n",
|
||||
clk_hw_get_name(hw), parent_rate, rate, div_val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clk_ops vop2_div_clk_ops = {
|
||||
.recalc_rate = vop2_clk_div_recalc_rate,
|
||||
.round_rate = vop2_clk_div_round_rate,
|
||||
.set_rate = vop2_clk_div_set_rate,
|
||||
};
|
||||
|
||||
static struct clk *vop2_clk_register(struct vop2 *vop2, struct vop2_clk_branch *branch)
|
||||
{
|
||||
struct clk_init_data init = {};
|
||||
struct vop2_clk *vop2_clk;
|
||||
struct clk *clk;
|
||||
|
||||
vop2_clk = devm_kzalloc(vop2->dev, sizeof(*vop2_clk), GFP_KERNEL);
|
||||
if (!vop2_clk)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
vop2_clk->vop2 = vop2;
|
||||
vop2_clk->hw.init = &init;
|
||||
vop2_clk->div.shift = branch->div_shift;
|
||||
vop2_clk->div.width = branch->div_width;
|
||||
|
||||
init.name = branch->name;
|
||||
init.flags = branch->flags;
|
||||
init.num_parents = branch->num_parents;
|
||||
init.parent_names = branch->parent_names;
|
||||
if (branch->branch_type == branch_divider) {
|
||||
init.ops = &vop2_div_clk_ops;
|
||||
} else if (branch->branch_type == branch_virtual) {
|
||||
init.ops = &clk_virtual_ops;
|
||||
init.num_parents = 0;
|
||||
init.parent_names = NULL;
|
||||
} else {
|
||||
init.ops = &vop2_mux_clk_ops;
|
||||
}
|
||||
|
||||
clk = devm_clk_register(vop2->dev, &vop2_clk->hw);
|
||||
if (!IS_ERR(clk))
|
||||
list_add_tail(&vop2_clk->list, &vop2->clk_list_head);
|
||||
else
|
||||
DRM_DEV_ERROR(vop2->dev, "Register %s failed\n", branch->name);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
int vop2_clk_init(struct vop2 *vop2)
|
||||
{
|
||||
struct vop2_clk_branch *branch = rk3588_vop_clk_branches;
|
||||
unsigned int nr_clk = ARRAY_SIZE(rk3588_vop_clk_branches);
|
||||
unsigned int idx;
|
||||
struct vop2_clk *clk, *n;
|
||||
|
||||
INIT_LIST_HEAD(&vop2->clk_list_head);
|
||||
|
||||
if (vop2->version < VOP_VERSION_RK3588)
|
||||
return 0;
|
||||
|
||||
list_for_each_entry_safe(clk, n, &vop2->clk_list_head, list) {
|
||||
list_del(&clk->list);
|
||||
}
|
||||
|
||||
for (idx = 0; idx < nr_clk; idx++, branch++)
|
||||
vop2_clk_register(vop2, branch);
|
||||
|
||||
return 0;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1050,6 +1050,7 @@
|
||||
#define RK3568_DSP_IF_EN 0x028
|
||||
#define RK3568_DSP_IF_CTRL 0x02c
|
||||
#define RK3568_DSP_IF_POL 0x030
|
||||
#define RK3568_SYS_PD_CTRL 0x034
|
||||
#define RK3568_WB_CTRL 0x40
|
||||
#define RK3568_WB_XSCAL_FACTOR 0x44
|
||||
#define RK3568_WB_YRGB_MST 0x48
|
||||
@@ -1060,6 +1061,7 @@
|
||||
#define RK3568_VP0_LINE_FLAG 0x70
|
||||
#define RK3568_VP1_LINE_FLAG 0x74
|
||||
#define RK3568_VP2_LINE_FLAG 0x78
|
||||
#define RK3588_VP3_LINE_FLAG 0x7C
|
||||
#define RK3568_SYS0_INT_EN 0x80
|
||||
#define RK3568_SYS0_INT_CLR 0x84
|
||||
#define RK3568_SYS0_INT_STATUS 0x88
|
||||
@@ -1078,11 +1080,32 @@
|
||||
#define RK3568_VP2_INT_CLR 0xC4
|
||||
#define RK3568_VP2_INT_STATUS 0xC8
|
||||
#define RK3568_VP2_INT_RAW_STATUS 0xCC
|
||||
#define RK3588_VP3_INT_EN 0xD0
|
||||
#define RK3588_VP3_INT_CLR 0xD4
|
||||
#define RK3588_VP3_INT_STATUS 0xD8
|
||||
|
||||
#define RK3588_DSC0_SYS_CTRL 0x200
|
||||
#define RK3588_DSC0_RST 0x204
|
||||
#define RK3588_DSC0_CFG_DONE 0x208
|
||||
#define RK3588_DSC0_INIT_DLY 0x20C
|
||||
#define RK3588_DSC0_HTOTAL_HS_END 0x210
|
||||
#define RK3588_DSC0_HACT_ST_END 0x214
|
||||
#define RK3588_DSC0_VTOTAL_VS_END 0x218
|
||||
#define RK3588_DSC0_VACT_ST_END 0x21C
|
||||
#define RK3588_DSC1_SYS_CTRL 0x230
|
||||
#define RK3588_DSC1_RST 0x234
|
||||
#define RK3588_DSC1_CFG_DONE 0x238
|
||||
#define RK3588_DSC1_INIT_DLY 0x23C
|
||||
#define RK3588_DSC1_HTOTAL_HS_END 0x240
|
||||
#define RK3588_DSC1_HACT_ST_END 0x244
|
||||
#define RK3588_DSC1_VTOTAL_VS_END 0x248
|
||||
#define RK3588_DSC1_VACT_ST_END 0x24C
|
||||
|
||||
/* Video Port registers definition */
|
||||
#define RK3568_VP0_DSP_CTRL 0xC00
|
||||
#define RK3568_VP0_MIPI_CTRL 0xC04
|
||||
#define RK3568_VP0_COLOR_BAR_CTRL 0xC08
|
||||
#define RK3568_VP0_CLK_CTRL 0xC0C
|
||||
#define RK3568_VP0_3D_LUT_CTRL 0xC10
|
||||
#define RK3568_VP0_3D_LUT_MST 0xC20
|
||||
#define RK3568_VP0_DSP_BG 0xC2C
|
||||
@@ -1106,6 +1129,7 @@
|
||||
#define RK3568_VP1_DSP_CTRL 0xD00
|
||||
#define RK3568_VP1_MIPI_CTRL 0xD04
|
||||
#define RK3568_VP1_COLOR_BAR_CTRL 0xD08
|
||||
#define RK3568_VP1_CLK_CTRL 0xD0C
|
||||
#define RK3568_VP1_DSP_BG 0xD2C
|
||||
#define RK3568_VP1_PRE_SCAN_HTIMING 0xD30
|
||||
#define RK3568_VP1_POST_DSP_HACT_INFO 0xD34
|
||||
@@ -1129,6 +1153,7 @@
|
||||
#define RK3568_VP2_DSP_CTRL 0xE00
|
||||
#define RK3568_VP2_MIPI_CTRL 0xE04
|
||||
#define RK3568_VP2_COLOR_BAR_CTRL 0xE08
|
||||
#define RK3568_VP2_CLK_CTRL 0xE0C
|
||||
#define RK3568_VP2_DSP_BG 0xE2C
|
||||
#define RK3568_VP2_PRE_SCAN_HTIMING 0xE30
|
||||
#define RK3568_VP2_POST_DSP_HACT_INFO 0xE34
|
||||
@@ -1149,6 +1174,30 @@
|
||||
#define RK3568_VP2_BCSH_H 0xE68
|
||||
#define RK3568_VP2_BCSH_COLOR_BAR 0xE6C
|
||||
|
||||
#define RK3588_VP3_DSP_CTRL 0xF00
|
||||
#define RK3588_VP3_MIPI_CTRL 0xF04
|
||||
#define RK3588_VP3_COLOR_BAR_CTRL 0xF08
|
||||
#define RK3568_VP3_CLK_CTRL 0xF0C
|
||||
#define RK3588_VP3_DSP_BG 0xF2C
|
||||
#define RK3588_VP3_PRE_SCAN_HTIMING 0xF30
|
||||
#define RK3588_VP3_POST_DSP_HACT_INFO 0xF34
|
||||
#define RK3588_VP3_POST_DSP_VACT_INFO 0xF38
|
||||
#define RK3588_VP3_POST_SCL_FACTOR_YRGB 0xF3C
|
||||
#define RK3588_VP3_POST_SCL_CTRL 0xF40
|
||||
#define RK3588_VP3_DSP_HACT_INFO 0xF34
|
||||
#define RK3588_VP3_DSP_VACT_INFO 0xF38
|
||||
#define RK3588_VP3_POST_DSP_VACT_INFO_F1 0xF44
|
||||
#define RK3588_VP3_DSP_HTOTAL_HS_END 0xF48
|
||||
#define RK3588_VP3_DSP_HACT_ST_END 0xF4C
|
||||
#define RK3588_VP3_DSP_VTOTAL_VS_END 0xF50
|
||||
#define RK3588_VP3_DSP_VACT_ST_END 0xF54
|
||||
#define RK3588_VP3_DSP_VS_ST_END_F1 0xF58
|
||||
#define RK3588_VP3_DSP_VACT_ST_END_F1 0xF5C
|
||||
#define RK3588_VP3_BCSH_CTRL 0xF60
|
||||
#define RK3588_VP3_BCSH_BCS 0xF64
|
||||
#define RK3588_VP3_BCSH_H 0xF68
|
||||
#define RK3588_VP3_BCSH_COLOR_BAR 0xF6C
|
||||
|
||||
/* Overlay registers definition */
|
||||
#define RK3568_OVL_CTRL 0x600
|
||||
#define RK3568_OVL_LAYER_SEL 0x604
|
||||
@@ -1165,10 +1214,16 @@
|
||||
#define RK3568_HDR0_DST_COLOR_CTRL 0x6C4
|
||||
#define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8
|
||||
#define RK3568_HDR0_DST_ALPHA_CTRL 0x6CC
|
||||
#define RK3568_HDR1_SRC_COLOR_CTRL 0x6D0
|
||||
#define RK3568_HDR1_DST_COLOR_CTRL 0x6D4
|
||||
#define RK3568_HDR1_SRC_ALPHA_CTRL 0x6D8
|
||||
#define RK3568_HDR1_DST_ALPHA_CTRL 0x6DC
|
||||
#define RK3568_VP0_BG_MIX_CTRL 0x6E0
|
||||
#define RK3568_VP1_BG_MIX_CTRL 0x6E4
|
||||
#define RK3568_VP2_BG_MIX_CTRL 0x6E8
|
||||
#define RK3588_VP3_BG_MIX_CTRL 0x6EC
|
||||
#define RK3568_CLUSTER_DLY_NUM 0x6F0
|
||||
#define RK3568_CLUSTER_DLY_NUM1 0x6F4
|
||||
#define RK3568_SMART_DLY_NUM 0x6F8
|
||||
|
||||
/* Cluster0 register definition */
|
||||
@@ -1250,6 +1305,84 @@
|
||||
|
||||
#define RK3568_CLUSTER1_CTRL 0x1300
|
||||
|
||||
#define RK3588_CLUSTER2_WIN0_CTRL0 0x1400
|
||||
#define RK3588_CLUSTER2_WIN0_CTRL1 0x1404
|
||||
#define RK3588_CLUSTER2_WIN0_YRGB_MST 0x1410
|
||||
#define RK3588_CLUSTER2_WIN0_CBR_MST 0x1414
|
||||
#define RK3588_CLUSTER2_WIN0_VIR 0x1418
|
||||
#define RK3588_CLUSTER2_WIN0_ACT_INFO 0x1420
|
||||
#define RK3588_CLUSTER2_WIN0_DSP_INFO 0x1424
|
||||
#define RK3588_CLUSTER2_WIN0_DSP_ST 0x1428
|
||||
#define RK3588_CLUSTER2_WIN0_SCL_FACTOR_YRGB 0x1430
|
||||
#define RK3588_CLUSTER2_WIN0_AFBCD_TRANSFORM_OFFSET 0x143C
|
||||
#define RK3588_CLUSTER2_WIN0_AFBCD_OUTPUT_CTRL 0x1450
|
||||
#define RK3588_CLUSTER2_WIN0_AFBCD_ROTATE_MODE 0x1454
|
||||
#define RK3588_CLUSTER2_WIN0_AFBCD_HDR_PTR 0x1458
|
||||
#define RK3588_CLUSTER2_WIN0_AFBCD_VIR_WIDTH 0x145C
|
||||
#define RK3588_CLUSTER2_WIN0_AFBCD_PIC_SIZE 0x1460
|
||||
#define RK3588_CLUSTER2_WIN0_AFBCD_PIC_OFFSET 0x1464
|
||||
#define RK3588_CLUSTER2_WIN0_AFBCD_DSP_OFFSET 0x1468
|
||||
#define RK3588_CLUSTER2_WIN0_AFBCD_CTRL 0x146C
|
||||
|
||||
#define RK3588_CLUSTER2_WIN1_CTRL0 0x1480
|
||||
#define RK3588_CLUSTER2_WIN1_CTRL1 0x1484
|
||||
#define RK3588_CLUSTER2_WIN1_YRGB_MST 0x1490
|
||||
#define RK3588_CLUSTER2_WIN1_CBR_MST 0x1494
|
||||
#define RK3588_CLUSTER2_WIN1_VIR 0x1498
|
||||
#define RK3588_CLUSTER2_WIN1_ACT_INFO 0x14A0
|
||||
#define RK3588_CLUSTER2_WIN1_DSP_INFO 0x14A4
|
||||
#define RK3588_CLUSTER2_WIN1_DSP_ST 0x14A8
|
||||
#define RK3588_CLUSTER2_WIN1_SCL_FACTOR_YRGB 0x14B0
|
||||
#define RK3588_CLUSTER2_WIN1_AFBCD_OUTPUT_CTRL 0x14D0
|
||||
#define RK3588_CLUSTER2_WIN1_AFBCD_ROTATE_MODE 0x14D4
|
||||
#define RK3588_CLUSTER2_WIN1_AFBCD_HDR_PTR 0x14D8
|
||||
#define RK3588_CLUSTER2_WIN1_AFBCD_VIR_WIDTH 0x14DC
|
||||
#define RK3588_CLUSTER2_WIN1_AFBCD_PIC_SIZE 0x14E0
|
||||
#define RK3588_CLUSTER2_WIN1_AFBCD_PIC_OFFSET 0x14E4
|
||||
#define RK3588_CLUSTER2_WIN1_AFBCD_DSP_OFFSET 0x14E8
|
||||
#define RK3588_CLUSTER2_WIN1_AFBCD_CTRL 0x14EC
|
||||
|
||||
#define RK3588_CLUSTER2_CTRL 0x1500
|
||||
|
||||
#define RK3588_CLUSTER3_WIN0_CTRL0 0x1600
|
||||
#define RK3588_CLUSTER3_WIN0_CTRL1 0x1604
|
||||
#define RK3588_CLUSTER3_WIN0_YRGB_MST 0x1610
|
||||
#define RK3588_CLUSTER3_WIN0_CBR_MST 0x1614
|
||||
#define RK3588_CLUSTER3_WIN0_VIR 0x1618
|
||||
#define RK3588_CLUSTER3_WIN0_ACT_INFO 0x1620
|
||||
#define RK3588_CLUSTER3_WIN0_DSP_INFO 0x1624
|
||||
#define RK3588_CLUSTER3_WIN0_DSP_ST 0x1628
|
||||
#define RK3588_CLUSTER3_WIN0_SCL_FACTOR_YRGB 0x1630
|
||||
#define RK3588_CLUSTER3_WIN0_AFBCD_TRANSFORM_OFFSET 0x163C
|
||||
#define RK3588_CLUSTER3_WIN0_AFBCD_OUTPUT_CTRL 0x1650
|
||||
#define RK3588_CLUSTER3_WIN0_AFBCD_ROTATE_MODE 0x1654
|
||||
#define RK3588_CLUSTER3_WIN0_AFBCD_HDR_PTR 0x1658
|
||||
#define RK3588_CLUSTER3_WIN0_AFBCD_VIR_WIDTH 0x165C
|
||||
#define RK3588_CLUSTER3_WIN0_AFBCD_PIC_SIZE 0x1660
|
||||
#define RK3588_CLUSTER3_WIN0_AFBCD_PIC_OFFSET 0x1664
|
||||
#define RK3588_CLUSTER3_WIN0_AFBCD_DSP_OFFSET 0x1668
|
||||
#define RK3588_CLUSTER3_WIN0_AFBCD_CTRL 0x166C
|
||||
|
||||
#define RK3588_CLUSTER3_WIN1_CTRL0 0x1680
|
||||
#define RK3588_CLUSTER3_WIN1_CTRL1 0x1684
|
||||
#define RK3588_CLUSTER3_WIN1_YRGB_MST 0x1690
|
||||
#define RK3588_CLUSTER3_WIN1_CBR_MST 0x1694
|
||||
#define RK3588_CLUSTER3_WIN1_VIR 0x1698
|
||||
#define RK3588_CLUSTER3_WIN1_ACT_INFO 0x16A0
|
||||
#define RK3588_CLUSTER3_WIN1_DSP_INFO 0x16A4
|
||||
#define RK3588_CLUSTER3_WIN1_DSP_ST 0x16A8
|
||||
#define RK3588_CLUSTER3_WIN1_SCL_FACTOR_YRGB 0x16B0
|
||||
#define RK3588_CLUSTER3_WIN1_AFBCD_OUTPUT_CTRL 0x16D0
|
||||
#define RK3588_CLUSTER3_WIN1_AFBCD_ROTATE_MODE 0x16D4
|
||||
#define RK3588_CLUSTER3_WIN1_AFBCD_HDR_PTR 0x16D8
|
||||
#define RK3588_CLUSTER3_WIN1_AFBCD_VIR_WIDTH 0x16DC
|
||||
#define RK3588_CLUSTER3_WIN1_AFBCD_PIC_SIZE 0x16E0
|
||||
#define RK3588_CLUSTER3_WIN1_AFBCD_PIC_OFFSET 0x16E4
|
||||
#define RK3588_CLUSTER3_WIN1_AFBCD_DSP_OFFSET 0x16E8
|
||||
#define RK3588_CLUSTER3_WIN1_AFBCD_CTRL 0x16EC
|
||||
|
||||
#define RK3588_CLUSTER3_CTRL 0x1700
|
||||
|
||||
/* Esmart register definition */
|
||||
#define RK3568_ESMART0_CTRL0 0x1800
|
||||
#define RK3568_ESMART0_CTRL1 0x1804
|
||||
@@ -1444,6 +1577,9 @@
|
||||
#define RK3568_HDR_LUT_CTRL 0x2000
|
||||
#define RK3568_HDR_LUT_MST 0x2004
|
||||
#define RK3568_SDR2HDR_CTRL 0x2010
|
||||
/* for HDR10 controller1 */
|
||||
#define RK3568_SDR2HDR_CTRL1 0x2018
|
||||
#define RK3568_HDR2SDR_CTRL1 0x201C
|
||||
#define RK3568_HDR2SDR_CTRL 0x2020
|
||||
#define RK3568_HDR2SDR_SRC_RANGE 0x2024
|
||||
#define RK3568_HDR2SDR_NORMFACEETF 0x2028
|
||||
@@ -1454,4 +1590,9 @@
|
||||
#define RK3568_HDR_EOTF_OETF_Y0 0x20F0
|
||||
#define RK3568_HDR_OETF_DX_POW1 0x2200
|
||||
#define RK3568_HDR_OETF_XN1 0x2300
|
||||
|
||||
/* DSC register definition */
|
||||
|
||||
#define RK3588_DSC_8K_PPS0_3 0x4000
|
||||
|
||||
#endif /* _ROCKCHIP_VOP_REG_H */
|
||||
|
||||
Reference in New Issue
Block a user