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audio: auge: add mixer for eARC RX/TX latency and capability [1/1]
PD#SWPL-6918 Problem: lack function to read/write eARC RX/TX latency and capability Solution: add mixer for eARC RX set/get latency and capability add mixer for eARC RX get latency and capability Verify: ab311 Change-Id: I0d8aa00af7d856493417dc881a1a8c40497b12a5 Signed-off-by: Xing Wang <xing.wang@amlogic.com>
This commit is contained in:
Xing Wang
@@ -13824,7 +13824,6 @@ F: sound/soc/codecs/Makefile
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F: sound/soc/codecs/amlogic/*
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F: drivers/amlogic/audiodsp/*
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AMLOGIC PPMGR DRIVER
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M: Guosong Zhou <guosong.zhou@amlogic.com>
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F: arch/arm64/boot/dts/amlogic/gxl_p212_1g.dts
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43
include/linux/amlogic/media/sound/mixer.h
Normal file
43
include/linux/amlogic/media/sound/mixer.h
Normal file
@@ -0,0 +1,43 @@
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/*
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* include/linux/amlogic/media/sound/mixer.h
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*
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* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#ifndef __MIXER_H__
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#define __MIXER_H__
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#include <sound/control.h>
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static int snd_int_info(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_info *uinfo)
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{
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uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
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uinfo->value.integer.min = 0;
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uinfo->value.integer.max = 0xffffffff;
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uinfo->count = 1;
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return 0;
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}
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#define SND_INT(xname, xhandler_get, xhandler_put) \
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{ \
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.iface = SNDRV_CTL_ELEM_IFACE_PCM, \
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.name = xname, \
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.info = snd_int_info, \
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.get = xhandler_get, \
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.put = xhandler_put, \
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}
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#endif
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@@ -37,6 +37,7 @@
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#include <sound/pcm_params.h>
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#include <linux/amlogic/media/sound/hdmi_earc.h>
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#include <linux/amlogic/media/sound/mixer.h>
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#include "ddr_mngr.h"
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#include "earc_hw.h"
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@@ -153,17 +154,24 @@ static irqreturn_t earc_rx_isr(int irq, void *data)
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if (status0)
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earcrx_cdmc_clr_irqs(p_earc->rx_top_map, status0);
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if (status0 & INT_EARCRX_CMDC_TIMEOUT) {
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earcrx_update_attend_event(p_earc,
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false, false);
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pr_debug("%s EARCRX_CMDC_TIMEOUT\n", __func__);
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}
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if (status0 & INT_EARCRX_CMDC_IDLE2) {
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earcrx_update_attend_event(p_earc,
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false, true);
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pr_debug("%s EARCRX_CMDC_IDLE2\n", __func__);
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pr_info("%s EARCRX_CMDC_IDLE2\n", __func__);
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}
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if (status0 & INT_EARCRX_CMDC_IDLE1) {
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earcrx_update_attend_event(p_earc,
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false, false);
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pr_debug("%s EARCRX_CMDC_IDLE1\n", __func__);
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pr_info("%s EARCRX_CMDC_IDLE1\n", __func__);
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}
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if (status0 & INT_EARCRX_CMDC_DISC2)
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pr_debug("%s EARCRX_CMDC_DISC2\n", __func__);
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@@ -181,12 +189,6 @@ static irqreturn_t earc_rx_isr(int irq, void *data)
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*/
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if (status0 & INT_EARCRX_CMDC_LOSTHB)
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pr_debug("%s EARCRX_CMDC_LOSTHB\n", __func__);
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if (status0 & INT_EARCRX_CMDC_TIMEOUT) {
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earcrx_update_attend_event(p_earc,
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false, false);
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pr_debug("%s EARCRX_CMDC_TIMEOUT\n", __func__);
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}
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if (p_earc->rx_dmac_clk_on) {
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unsigned int status1 = earcrx_dmac_get_irqs(p_earc->rx_top_map);
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@@ -936,21 +938,205 @@ int earctx_set_attend_type(struct snd_kcontrol *kcontrol,
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return 0;
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}
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static const struct snd_kcontrol_new earc_controls[] = {
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SOC_ENUM_EXT("eARC_RX attended type",
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attended_type_enum,
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earcrx_get_attend_type,
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earcrx_set_attend_type),
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int earcrx_get_latency(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
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struct earc *p_earc = dev_get_drvdata(component->dev);
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enum cmdc_st state;
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u8 val = 0;
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if (!p_earc || IS_ERR(p_earc->rx_top_map))
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return 0;
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state = earcrx_cmdc_get_state(p_earc->rx_cmdc_map);
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if (state != CMDC_ST_EARC)
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return 0;
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earcrx_cmdc_get_latency(p_earc->rx_cmdc_map, &val);
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ucontrol->value.integer.value[0] = val;
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return 0;
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}
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int earcrx_set_latency(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
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struct earc *p_earc = dev_get_drvdata(component->dev);
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u8 latency = ucontrol->value.integer.value[0];
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enum cmdc_st state;
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if (!p_earc || IS_ERR(p_earc->rx_top_map))
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return 0;
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state = earcrx_cmdc_get_state(p_earc->rx_cmdc_map);
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if (state != CMDC_ST_EARC)
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return 0;
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earcrx_cmdc_set_latency(p_earc->rx_cmdc_map, &latency);
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return 0;
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}
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int earcrx_get_cds(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
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struct earc *p_earc = dev_get_drvdata(component->dev);
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struct soc_bytes_ext *bytes_ext =
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(struct soc_bytes_ext *)kcontrol->private_value;
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u8 *value = (u8 *)ucontrol->value.bytes.data;
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enum cmdc_st state;
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int i;
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u8 data[256];
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if (!p_earc || IS_ERR(p_earc->rx_top_map))
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return 0;
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state = earcrx_cmdc_get_state(p_earc->rx_cmdc_map);
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if (state != CMDC_ST_EARC)
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return 0;
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earcrx_cmdc_get_cds(p_earc->rx_cmdc_map, data);
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for (i = 0; i < bytes_ext->max; i++)
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*value++ = data[i];
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return 0;
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}
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int earcrx_set_cds(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
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struct earc *p_earc = dev_get_drvdata(component->dev);
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struct soc_bytes_ext *params = (void *)kcontrol->private_value;
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u8 *data;
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enum cmdc_st state;
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if (!p_earc || IS_ERR(p_earc->rx_top_map))
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return 0;
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state = earcrx_cmdc_get_state(p_earc->rx_cmdc_map);
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if (state != CMDC_ST_EARC)
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return 0;
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data = kmemdup(ucontrol->value.bytes.data,
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params->max, GFP_KERNEL | GFP_DMA);
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if (!data)
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return -ENOMEM;
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earcrx_cmdc_set_cds(p_earc->rx_cmdc_map, data);
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kfree(data);
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return 0;
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}
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int earctx_get_latency(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
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struct earc *p_earc = dev_get_drvdata(component->dev);
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enum cmdc_st state;
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u8 val = 0;
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if (!p_earc || IS_ERR(p_earc->tx_top_map))
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return 0;
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state = earctx_cmdc_get_state(p_earc->tx_cmdc_map);
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if (state != CMDC_ST_EARC)
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return 0;
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earctx_cmdc_get_latency(p_earc->tx_cmdc_map, &val);
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ucontrol->value.integer.value[0] = val;
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return 0;
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}
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int earctx_set_latency(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
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struct earc *p_earc = dev_get_drvdata(component->dev);
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u8 latency = ucontrol->value.integer.value[0];
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enum cmdc_st state;
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if (!p_earc || IS_ERR(p_earc->tx_top_map))
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return 0;
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state = earctx_cmdc_get_state(p_earc->tx_cmdc_map);
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if (state != CMDC_ST_EARC)
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return 0;
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earctx_cmdc_set_latency(p_earc->tx_cmdc_map, &latency);
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return 0;
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}
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int earctx_get_cds(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
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struct earc *p_earc = dev_get_drvdata(component->dev);
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struct soc_bytes_ext *bytes_ext =
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(struct soc_bytes_ext *)kcontrol->private_value;
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u8 *value = (u8 *)ucontrol->value.bytes.data;
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enum cmdc_st state;
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u8 data[256];
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int i;
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if (!p_earc || IS_ERR(p_earc->tx_top_map))
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return 0;
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state = earctx_cmdc_get_state(p_earc->tx_cmdc_map);
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if (state != CMDC_ST_EARC)
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return 0;
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earctx_cmdc_get_cds(p_earc->tx_cmdc_map, data);
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for (i = 0; i < bytes_ext->max; i++)
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*value++ = data[i];
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return 0;
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}
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static const struct snd_kcontrol_new earc_controls[] = {
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SOC_SINGLE_BOOL_EXT("HDMI ARC Switch",
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0,
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earcrx_arc_get_enable,
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earcrx_arc_set_enable),
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SOC_ENUM_EXT("eARC_RX attended type",
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attended_type_enum,
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earcrx_get_attend_type,
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earcrx_set_attend_type),
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SOC_ENUM_EXT("eARC_TX attended type",
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attended_type_enum,
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earctx_get_attend_type,
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earctx_set_attend_type),
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SND_INT("eARC_RX Latency",
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earcrx_get_latency,
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earcrx_set_latency),
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SND_INT("eARC_TX Latency",
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earctx_get_latency,
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earctx_set_latency),
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SND_SOC_BYTES_EXT("eARC_RX CDS",
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CDS_MAX_BYTES,
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earcrx_get_cds,
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earcrx_set_cds),
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SND_SOC_BYTES_EXT("eARC_TX CDS",
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CDS_MAX_BYTES,
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earctx_get_cds,
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NULL),
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};
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static const struct snd_soc_component_driver earc_component = {
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@@ -612,3 +612,250 @@ void earctx_enable(struct regmap *top_map,
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enable << 30);
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}
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}
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static void earcrx_cmdc_get_reg(struct regmap *cmdc_map, int dev_id, int offset,
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u8 *data, int bytes)
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{
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int i;
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mmio_update_bits(cmdc_map, EARC_RX_CMDC_DEVICE_ID_CTRL,
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0x1 << 31 | /* apb_write */
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0x1 << 30 | /* apb_read */
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0x1 << 29 | /* apb_w_r_done */
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0xff << 8 | /* apb_rwid */
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0xff << 0, /* apbrw_start_addr */
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0x0 << 31 |
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0x1 << 30 |
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0x0 << 29 |
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dev_id << 8 |
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offset << 0);
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for (i = 0; i < bytes; i++) {
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data[i] = mmio_read(cmdc_map, EARC_RX_CMDC_DEVICE_RDATA);
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pr_info("%s, data[%d]:%#x\n", __func__, i, data[i]);
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}
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mmio_update_bits(cmdc_map, EARC_RX_CMDC_DEVICE_ID_CTRL,
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0x1 << 29, 0x1 << 29);
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mmio_update_bits(cmdc_map, EARC_RX_CMDC_DEVICE_ID_CTRL,
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0x1 << 29, 0x0 << 29);
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}
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static void earcrx_cmdc_set_reg(struct regmap *cmdc_map, int dev_id, int offset,
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u8 *data, int bytes)
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{
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int i;
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mmio_update_bits(cmdc_map, EARC_RX_CMDC_DEVICE_ID_CTRL,
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0x1 << 31 | /* apb_write */
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0x1 << 30 | /* apb_read */
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0x1 << 29 | /* apb_w_r_done */
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0xff << 8 | /* apb_rwid */
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0xff << 0, /* apbrw_start_addr */
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0x1 << 31 |
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0x0 << 30 |
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0x0 << 29 |
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dev_id << 8 |
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offset << 0);
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for (i = 0; i < bytes; i++) {
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pr_info("%s, data[%d]:%#x\n", __func__, i, data[i]);
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mmio_write(cmdc_map, EARC_RX_CMDC_DEVICE_WDATA, data[i]);
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}
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mmio_update_bits(cmdc_map, EARC_RX_CMDC_DEVICE_ID_CTRL,
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0x1 << 29, 0x1 << 29);
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mmio_update_bits(cmdc_map, EARC_RX_CMDC_DEVICE_ID_CTRL,
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0x1 << 29, 0x0 << 29);
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}
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/* Latency */
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void earcrx_cmdc_get_latency(struct regmap *cmdc_map, u8 *latency)
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{
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earcrx_cmdc_get_reg(cmdc_map,
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STAT_CTRL_DEV_ID,
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ERX_LATENCY_REG,
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latency,
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1);
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}
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void earcrx_cmdc_set_latency(struct regmap *cmdc_map, u8 *latency)
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{
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earcrx_cmdc_set_reg(cmdc_map,
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STAT_CTRL_DEV_ID,
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ERX_LATENCY_REG,
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latency,
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1);
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}
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void earcrx_cmdc_get_cds(struct regmap *cmdc_map, u8 *cds)
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{
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earcrx_cmdc_get_reg(cmdc_map,
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CAP_DEV_ID,
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0x0,
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cds,
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CDS_MAX_BYTES);
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}
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void earcrx_cmdc_set_cds(struct regmap *cmdc_map, u8 *cds)
|
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{
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earcrx_cmdc_set_reg(cmdc_map,
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CAP_DEV_ID,
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0x0,
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cds,
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CDS_MAX_BYTES);
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}
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||||
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static int earctx_cmdc_get_reg(struct regmap *cmdc_map, int dev_id, int offset,
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u8 *data, int bytes)
|
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{
|
||||
int val = 0, i;
|
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int ret = -1;
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||||
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mmio_update_bits(cmdc_map, EARC_TX_CMDC_MASTER_CTRL,
|
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0x1 << 31 | /* master_cmd_rw, read */
|
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0x1 << 30 | /* master_hb_ignore */
|
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0xf << 24 | /* hb_cmd_val_th */
|
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0xff << 16 | /* master_cmd_count */
|
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0xff << 8 | /* master_cmd_id */
|
||||
0xff << 0, /* master_cmd_address */
|
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0x0 << 31 |
|
||||
0x1 << 30 |
|
||||
0x4 << 24 |
|
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(bytes - 1) << 16 |
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||||
dev_id << 8 |
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offset << 0);
|
||||
|
||||
/* wait read from rx done */
|
||||
while (!(val & (1 << 29))) {
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usleep_range(500, 1500);
|
||||
val = mmio_read(cmdc_map, EARC_TX_CMDC_MASTER_CTRL);
|
||||
}
|
||||
|
||||
mmio_update_bits(cmdc_map, EARC_TX_CMDC_DEVICE_ID_CTRL,
|
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0x1 << 31 | /* apb_write */
|
||||
0x1 << 30 | /* apb_read */
|
||||
0x1 << 29 | /* apb_rw_done */
|
||||
0x1 << 16 | /* hpb_rst_enable */
|
||||
0xff << 8 | /* apb_rwid */
|
||||
0xff << 0, /* apbrw_start_addr */
|
||||
0x0 << 31 |
|
||||
0x1 << 30 |
|
||||
0x0 << 29 |
|
||||
0x1 << 16 |
|
||||
dev_id << 8 |
|
||||
offset << 0);
|
||||
|
||||
for (i = 0; i < bytes; i++) {
|
||||
data[i] = mmio_read(cmdc_map, EARC_TX_CMDC_DEVICE_RDATA);
|
||||
pr_info("%s, bytes:%d, data[%d]:%#x\n",
|
||||
__func__,
|
||||
bytes,
|
||||
i,
|
||||
data[i]);
|
||||
}
|
||||
|
||||
mmio_update_bits(cmdc_map, EARC_TX_CMDC_DEVICE_ID_CTRL,
|
||||
0x1 << 29, 0x1 << 29);
|
||||
mmio_update_bits(cmdc_map, EARC_TX_CMDC_DEVICE_ID_CTRL,
|
||||
0x1 << 29, 0x0 << 29);
|
||||
|
||||
if (val & (1 << 29))
|
||||
ret = 0;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int earctx_cmdc_set_reg(struct regmap *cmdc_map, int dev_id, int offset,
|
||||
u8 *data, int bytes)
|
||||
{
|
||||
int val = 0, i;
|
||||
int ret = -1;
|
||||
int cnt = 0;
|
||||
|
||||
mmio_update_bits(cmdc_map, EARC_TX_CMDC_DEVICE_ID_CTRL,
|
||||
0x1 << 31 | /* apb_write */
|
||||
0x1 << 30 | /* apb_read */
|
||||
0x1 << 29 | /* apb_rw_done */
|
||||
0x1 << 16 | /* hpb_rst_enable */
|
||||
0xff << 8 | /* apb_rwid */
|
||||
0xff << 0, /* apbrw_start_addr */
|
||||
0x1 << 31 |
|
||||
0x0 << 30 |
|
||||
0x0 << 29 |
|
||||
0x1 << 16 |
|
||||
dev_id << 8 |
|
||||
offset << 0);
|
||||
|
||||
for (i = 0; i < bytes; i++) {
|
||||
mmio_update_bits(cmdc_map, EARC_TX_CMDC_DEVICE_WDATA,
|
||||
0xff << 0,
|
||||
data[i] << 0);
|
||||
pr_info("%s, data[%d]:%#x, bytes:%d\n",
|
||||
__func__,
|
||||
i,
|
||||
data[i],
|
||||
bytes);
|
||||
}
|
||||
|
||||
mmio_update_bits(cmdc_map, EARC_TX_CMDC_MASTER_CTRL,
|
||||
0x1 << 31 | /* master_cmd_rw, write */
|
||||
0x1 << 30 | /* master_hb_ignore */
|
||||
0xf << 24 | /* hb_cmd_cal_th */
|
||||
0xff << 16 | /* master_cmd_count */
|
||||
0xff << 8 | /* master_cmd_id */
|
||||
0xff << 0, /* master_cmd_address */
|
||||
0x1 << 31 |
|
||||
0x1 << 30 |
|
||||
4 << 24 |
|
||||
(bytes - 1) << 16 |
|
||||
dev_id << 8 |
|
||||
offset << 0);
|
||||
|
||||
/* wait write done */
|
||||
while (!(val & (1 << 29))) {
|
||||
usleep_range(500, 1500);
|
||||
val = mmio_read(cmdc_map, EARC_TX_CMDC_MASTER_CTRL);
|
||||
cnt++;
|
||||
}
|
||||
pr_info("%s, cnt:%d\n", __func__, cnt);
|
||||
|
||||
mmio_update_bits(cmdc_map, EARC_TX_CMDC_DEVICE_ID_CTRL,
|
||||
0x1 << 29, 0x1 << 29);
|
||||
mmio_update_bits(cmdc_map, EARC_TX_CMDC_DEVICE_ID_CTRL,
|
||||
0x1 << 29, 0x0 << 29);
|
||||
|
||||
if (val & (1 << 29))
|
||||
ret = 0;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Latency */
|
||||
void earctx_cmdc_get_latency(struct regmap *cmdc_map, u8 *latency)
|
||||
{
|
||||
earctx_cmdc_get_reg(cmdc_map,
|
||||
STAT_CTRL_DEV_ID,
|
||||
ERX_LATENCY_REG,
|
||||
latency,
|
||||
1);
|
||||
}
|
||||
|
||||
void earctx_cmdc_set_latency(struct regmap *cmdc_map, u8 *latency)
|
||||
{
|
||||
earctx_cmdc_set_reg(cmdc_map,
|
||||
STAT_CTRL_DEV_ID,
|
||||
ERX_LATENCY_REQ_REG,
|
||||
latency,
|
||||
1);
|
||||
}
|
||||
|
||||
/* Capability Data Structure, fetch CDS from RX */
|
||||
void earctx_cmdc_get_cds(struct regmap *cmdc_map, u8 *cds)
|
||||
{
|
||||
earctx_cmdc_get_reg(cmdc_map,
|
||||
CAP_DEV_ID,
|
||||
0x0,
|
||||
cds,
|
||||
CDS_MAX_BYTES);
|
||||
}
|
||||
|
||||
@@ -107,6 +107,24 @@ enum tx_hd_hdp_mux {
|
||||
GPIOW_5
|
||||
};
|
||||
|
||||
enum device_id {
|
||||
/* Capabilities Data Structure */
|
||||
CAP_DEV_ID = 0xA0,
|
||||
/* eARC status and latency control registers */
|
||||
STAT_CTRL_DEV_ID = 0x74
|
||||
};
|
||||
|
||||
enum reg_offset {
|
||||
/* eARC Status Register Offset */
|
||||
EARCRX_STAT_REG = 0xD0,
|
||||
EARCTX_STAT_REG = 0xD1,
|
||||
/* eARC Latency Registers Offset */
|
||||
ERX_LATENCY_REG = 0xD2,
|
||||
ERX_LATENCY_REQ_REG = 0xD3
|
||||
};
|
||||
|
||||
#define CDS_MAX_BYTES 256
|
||||
|
||||
void earcrx_pll_refresh(struct regmap *top_map);
|
||||
void earcrx_cmdc_init(struct regmap *top_map);
|
||||
void earcrx_cmdc_arc_connect(struct regmap *cmdc_map, bool init);
|
||||
@@ -144,4 +162,13 @@ void earctx_enable(struct regmap *top_map,
|
||||
struct regmap *dmac_map,
|
||||
bool enable);
|
||||
|
||||
void earcrx_cmdc_get_latency(struct regmap *cmdc_map, u8 *latency);
|
||||
void earcrx_cmdc_set_latency(struct regmap *cmdc_map, u8 *latency);
|
||||
void earcrx_cmdc_get_cds(struct regmap *cmdc_map, u8 *cds);
|
||||
void earcrx_cmdc_set_cds(struct regmap *cmdc_map, u8 *cds);
|
||||
|
||||
void earctx_cmdc_get_latency(struct regmap *cmdc_map, u8 *latency);
|
||||
void earctx_cmdc_set_latency(struct regmap *cmdc_map, u8 *latency);
|
||||
void earctx_cmdc_get_cds(struct regmap *cmdc_map, u8 *cds);
|
||||
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user