From 961bd975978e5c02ff2885d0fb8ab427409cf397 Mon Sep 17 00:00:00 2001 From: Wyon Bi Date: Fri, 25 Feb 2022 10:13:08 +0800 Subject: [PATCH] clk: rockchip: link: Add pclk_vo1_grf clock Signed-off-by: Wyon Bi Change-Id: I3f0f46fd9580e935769335aa20f78c2ee74dbdaa --- drivers/clk/rockchip/clk-link.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/rockchip/clk-link.c b/drivers/clk/rockchip/clk-link.c index be59fa53da8a..8e86cc18411b 100644 --- a/drivers/clk/rockchip/clk-link.c +++ b/drivers/clk/rockchip/clk-link.c @@ -96,6 +96,7 @@ static const struct rockchip_link_info rk3588_clk_gate_link_info[] = { GATE_LINK("pclk_av1_pre", "pclk_av1_root", 4), GATE_LINK("hclk_sdio_pre", "hclk_sdio_root", 1), GATE_LINK("pclk_vo0_grf", "pclk_vo0_root", 10), + GATE_LINK("pclk_vo1_grf", "pclk_vo1_root", 12), }; static const struct rockchip_link rk3588_clk_gate_link = {