From 96560cb2ee1570b2f82275fe64fa11c58e567593 Mon Sep 17 00:00:00 2001 From: William Wu Date: Fri, 7 May 2021 20:42:52 +0800 Subject: [PATCH] phy: rockchip: naneng-combphy: adjust PLL parameters for USB When do USB 3.0 Receiver Jitter Tolerance Test, it fails at Sj Frequency 2.0/4.9/10.0 [MHz]. This patch adjusts the PLL parameters for USB to pass the Receiver Jitter Tolerance Test, and it's helpful to improve the USB 3.0 signal compatibility. Change-Id: I58eb687a4677fe22cf5bc324578b033526310859 Signed-off-by: William Wu Signed-off-by: Frank Wang --- .../rockchip/phy-rockchip-naneng-combphy.c | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index d28fe5728e7a..67c3663da80d 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -448,6 +448,27 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) val |= 0x01; writel(val, priv->mmio + (0x0e << 2)); + /* Set PLL KVCO fine tuning signals */ + val = readl(priv->mmio + (0x20 << 2)); + val &= ~(0x7 << 2); + val |= 0x2 << 2; + writel(val, priv->mmio + (0x20 << 2)); + + /* Set PLL LPF R1 to su_trim[10:7]=1001 */ + writel(0x4, priv->mmio + (0xb << 2)); + + /* Set PLL input clock divider 1/2 */ + val = readl(priv->mmio + (0x5 << 2)); + val &= ~(0x3 << 6); + val |= 0x1 << 6; + writel(val, priv->mmio + (0x5 << 2)); + + /* Set PLL loop divider */ + writel(0x32, priv->mmio + (0x11 << 2)); + + /* Set PLL KVCO to min and set PLL charge pump current to max */ + writel(0xf0, priv->mmio + (0xa << 2)); + param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);