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arm64: dts: rockchip: move resets to the subnode of dwc3 for rk3399

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The dwc3 reset operation has been moved to the dwc3/core.c, so we apply
this patch to make the reset operation effective.

Change-Id: I0eb8fb7b4cd1c167fa4c69b177b4a8b6dfe26ef8
Signed-off-by: Jianing Ren <jianing.ren@rock-chips.com>
This commit is contained in:
Jianing Ren
2019-11-18 15:42:25 +08:00
parent bb4c791a42
commit 966da4dbac
1 changed files with 4 additions and 4 deletions
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8
arch/arm64/boot/dts/rockchip/rk3399.dtsi
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@@ -446,8 +446,6 @@
<&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
clock-names = "ref_clk", "suspend_clk",
"bus_clk", "grf_clk";
resets = <&cru SRST_A_USB3_OTG0>;
reset-names = "usb3-otg";
status = "disabled";
usbdrd_dwc3_0: dwc3@fe800000 {
@@ -459,6 +457,8 @@
phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi_wide";
power-domains = <&power RK3399_PD_USB3>;
resets = <&cru SRST_A_USB3_OTG0>;
reset-names = "usb3-otg";
snps,dis_enblslpm_quirk;
snps,dis-u2-freeclk-exists-quirk;
snps,dis_u2_susphy_quirk;
@@ -480,8 +480,6 @@
<&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
clock-names = "ref_clk", "suspend_clk",
"bus_clk", "grf_clk";
resets = <&cru SRST_A_USB3_OTG1>;
reset-names = "usb3-otg";
status = "disabled";
usbdrd_dwc3_1: dwc3@fe900000 {
@@ -493,6 +491,8 @@
phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi_wide";
power-domains = <&power RK3399_PD_USB3>;
resets = <&cru SRST_A_USB3_OTG1>;
reset-names = "usb3-otg";
snps,dis_enblslpm_quirk;
snps,dis-u2-freeclk-exists-quirk;
snps,dis_u2_susphy_quirk;