From 970efca023925f11b5c5ce35814b6f506682e114 Mon Sep 17 00:00:00 2001 From: William Wu Date: Fri, 1 Jul 2022 17:39:38 +0800 Subject: [PATCH] phy: rockchip: inno_usb2: update phy tuning for rv1106 and rv1103 1. Set different pre_emphasize strength for rv1106 and rv1103. - Set pre_emphasize strength to 0x03 for cpu verison_0; - Set pre_emphasize strength to 0x01 for cpu verison_1; 2. Bypass Squelch detector calibration to improve receiving sensitivity. - Before: E-17 248.7mv, E-16 112.6mv - After: E-17 150mv, E-16 98.8mv Note: E-17 and E-16 is on page 3 of the "USB 2.0 Electrical Compliance Test Specification" https://usb.org/document-library/usb-20-electrical-compliance-test-specification-version-107 Signed-off-by: William Wu Change-Id: I0d668b3d126583ada03d9675e0175f02537d915f --- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index 2df94bf64363..cac7c4c0495e 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -2650,8 +2650,13 @@ static int rv1106_usb2phy_tuning(struct rockchip_usb2phy *rphy) /* Always enable pre-emphasis in SOF & EOP & chirp & non-chirp state */ phy_update_bits(rphy->phy_base + 0x30, GENMASK(2, 0), 0x07); - /* Set Tx HS pre_emphasize strength to 3'b010 */ - phy_update_bits(rphy->phy_base + 0x40, GENMASK(5, 3), (0x02 << 3)); + if (rockchip_get_cpu_version()) { + /* Set Tx HS pre_emphasize strength to 3'b001 */ + phy_update_bits(rphy->phy_base + 0x40, GENMASK(5, 3), (0x01 << 3)); + } else { + /* Set Tx HS pre_emphasize strength to 3'b011 */ + phy_update_bits(rphy->phy_base + 0x40, GENMASK(5, 3), (0x03 << 3)); + } /* Set RX Squelch trigger point configure to 4'b0000(112.5 mV) */ phy_update_bits(rphy->phy_base + 0x64, GENMASK(6, 3), (0x00 << 3)); @@ -2665,6 +2670,10 @@ static int rv1106_usb2phy_tuning(struct rockchip_usb2phy *rphy) /* Set Tx HS eye height tuning to 3'b011(462 mV)*/ phy_update_bits(rphy->phy_base + 0x124, GENMASK(4, 2), (0x03 << 2)); + /* Bypass Squelch detector calibration */ + phy_update_bits(rphy->phy_base + 0x1a4, GENMASK(7, 4), (0x01 << 4)); + phy_update_bits(rphy->phy_base + 0x1b4, GENMASK(7, 4), (0x01 << 4)); + return 0; }