mirror of
https://github.com/hardkernel/linux.git
synced 2026-06-09 12:17:12 +09:00
upload iep driver for linux kernel 3.10
This commit is contained in:
ljf
@@ -66,4 +66,5 @@ source "drivers/video/rockchip/hdmi/Kconfig"
|
||||
source "drivers/video/rockchip/tve/Kconfig"
|
||||
source "drivers/video/rockchip/rga/Kconfig"
|
||||
source "drivers/video/rockchip/rga2/Kconfig"
|
||||
source "drivers/video/rockchip/iep/Kconfig"
|
||||
|
||||
|
||||
@@ -3,3 +3,4 @@ obj-$(CONFIG_RK_TRSM) += transmitter/
|
||||
obj-$(CONFIG_ROCKCHIP_RGA) += rga/
|
||||
obj-$(CONFIG_ROCKCHIP_RGA2) += rga2/
|
||||
obj-$(CONFIG_RK_HDMI) += display-sys.o hdmi/
|
||||
obj-$(CONFIG_IEP) += iep/
|
||||
|
||||
17
drivers/video/rockchip/iep/Kconfig
Executable file
17
drivers/video/rockchip/iep/Kconfig
Executable file
@@ -0,0 +1,17 @@
|
||||
menu "IEP"
|
||||
depends on ARCH_ROCKCHIP
|
||||
|
||||
config IEP
|
||||
tristate "ROCKCHIP IEP driver"
|
||||
default y
|
||||
help
|
||||
rockchip iep module.
|
||||
|
||||
config IEP_MMU
|
||||
tristate "ROCKCHIP IEP MMU driver"
|
||||
depends on ARCH_ROCKCHIP
|
||||
default n
|
||||
help
|
||||
rockchip iep mmu
|
||||
|
||||
endmenu
|
||||
2
drivers/video/rockchip/iep/Makefile
Executable file
2
drivers/video/rockchip/iep/Makefile
Executable file
@@ -0,0 +1,2 @@
|
||||
obj-$(CONFIG_IEP) += hw_iep_reg.o iep_drv.o
|
||||
obj-$(CONFIG_IEP_MMU) += iep_mmu.o
|
||||
111
drivers/video/rockchip/iep/hw_iep_config_addr.h
Executable file
111
drivers/video/rockchip/iep/hw_iep_config_addr.h
Executable file
@@ -0,0 +1,111 @@
|
||||
#ifndef HW_IEP_CONFIG_ADDR_H_
|
||||
#define HW_IEP_CONFIG_ADDR_H_
|
||||
|
||||
#include <asm/io.h>
|
||||
|
||||
#define IEP_BASE 0x0 //ignore the IEP_BASE when program running in linux kernel //0x10108000
|
||||
|
||||
#define IEP_CONFIG0 0x0000
|
||||
#define IEP_CONFIG1 0x0004
|
||||
|
||||
#define IEP_STATUS 0x0008
|
||||
#define IEP_INT 0x000C
|
||||
#define IEP_FRM_START 0x0010
|
||||
#define IEP_SOFT_RST 0x0014
|
||||
#define IEP_CONF_DONE 0x0018
|
||||
|
||||
#define IEP_VIR_IMG_WIDTH 0x0020
|
||||
|
||||
#define IEP_IMG_SCL_FCT 0x0024
|
||||
|
||||
#define IEP_SRC_IMG_SIZE 0x0028
|
||||
#define IEP_DST_IMG_SIZE 0x002C
|
||||
|
||||
#define IEP_DST_IMG_WIDTH_TILE0 0x0030
|
||||
#define IEP_DST_IMG_WIDTH_TILE1 0x0034
|
||||
#define IEP_DST_IMG_WIDTH_TILE2 0x0038
|
||||
#define IEP_DST_IMG_WIDTH_TILE3 0x003C
|
||||
|
||||
#define IEP_ENH_YUV_CNFG_0 0x0040
|
||||
#define IEP_ENH_YUV_CNFG_1 0x0044
|
||||
#define IEP_ENH_YUV_CNFG_2 0x0048
|
||||
#define IEP_ENH_RGB_CNFG 0x004C
|
||||
#define IEP_ENH_C_COE 0x0050
|
||||
|
||||
#define IEP_SRC_ADDR_YRGB 0x0080
|
||||
#define IEP_SRC_ADDR_CBCR 0x0084
|
||||
#define IEP_SRC_ADDR_CR 0x0088
|
||||
#define IEP_SRC_ADDR_Y1 0x008C
|
||||
#define IEP_SRC_ADDR_CBCR1 0x0090
|
||||
#define IEP_SRC_ADDR_CR1 0x0094
|
||||
#define IEP_SRC_ADDR_Y_ITEMP 0x0098
|
||||
#define IEP_SRC_ADDR_CBCR_ITEMP 0x009C
|
||||
#define IEP_SRC_ADDR_CR_ITEMP 0x00A0
|
||||
#define IEP_SRC_ADDR_Y_FTEMP 0x00A4
|
||||
#define IEP_SRC_ADDR_CBCR_FTEMP 0x00A8
|
||||
#define IEP_SRC_ADDR_CR_FTEMP 0x00AC
|
||||
|
||||
#define IEP_DST_ADDR_YRGB 0x00B0
|
||||
#define IEP_DST_ADDR_CBCR 0x00B4
|
||||
#define IEP_DST_ADDR_CR 0x00B8
|
||||
#define IEP_DST_ADDR_Y1 0x00BC
|
||||
#define IEP_DST_ADDR_CBCR1 0x00C0
|
||||
#define IEP_DST_ADDR_CR1 0x00C4
|
||||
#define IEP_DST_ADDR_Y_ITEMP 0x00C8
|
||||
#define IEP_DST_ADDR_CBCR_ITEMP 0x00CC
|
||||
#define IEP_DST_ADDR_CR_ITEMP 0x00D0
|
||||
#define IEP_DST_ADDR_Y_FTEMP 0x00D4
|
||||
#define IEP_DST_ADDR_CBCR_FTEMP 0x00D8
|
||||
#define IEP_DST_ADDR_CR_FTEMP 0x00DC
|
||||
|
||||
#define IEP_DIL_MTN_TAB0 0x00E0
|
||||
#define IEP_DIL_MTN_TAB1 0x00E4
|
||||
#define IEP_DIL_MTN_TAB2 0x00E8
|
||||
#define IEP_DIL_MTN_TAB3 0x00EC
|
||||
#define IEP_DIL_MTN_TAB4 0x00F0
|
||||
#define IEP_DIL_MTN_TAB5 0x00F4
|
||||
#define IEP_DIL_MTN_TAB6 0x00F8
|
||||
#define IEP_DIL_MTN_TAB7 0x00FC
|
||||
|
||||
#define IEP_ENH_CG_TAB 0x0100
|
||||
|
||||
#define IEP_YUV_DNS_CRCT_TEMP 0x0400
|
||||
#define IEP_YUV_DNS_CRCT_SPAT 0x0800
|
||||
|
||||
#define IEP_ENH_DDE_COE0 0x0C00
|
||||
#define IEP_ENH_DDE_COE1 0x0E00
|
||||
|
||||
#define RAW_IEP_CONFIG0 0x0058
|
||||
#define RAW_IEP_CONFIG1 0x005C
|
||||
#define RAW_IEP_VIR_IMG_WIDTH 0x0060
|
||||
|
||||
#define RAW_IEP_IMG_SCL_FCT 0x0064
|
||||
|
||||
#define RAW_IEP_SRC_IMG_SIZE 0x0068
|
||||
#define RAW_IEP_DST_IMG_SIZE 0x006C
|
||||
|
||||
#define RAW_IEP_ENH_YUV_CNFG_0 0x0070
|
||||
#define RAW_IEP_ENH_YUV_CNFG_1 0x0074
|
||||
#define RAW_IEP_ENH_YUV_CNFG_2 0x0078
|
||||
#define RAW_IEP_ENH_RGB_CNFG 0x007C
|
||||
|
||||
#if defined(CONFIG_IEP_MMU)
|
||||
#define IEP_MMU_BASE 0x0800
|
||||
#define IEP_MMU_DTE_ADDR (IEP_MMU_BASE+0x00)
|
||||
#define IEP_MMU_STATUS (IEP_MMU_BASE+0x04)
|
||||
#define IEP_MMU_CMD (IEP_MMU_BASE+0x08)
|
||||
#define IEP_MMU_PAGE_FAULT_ADDR (IEP_MMU_BASE+0x0c)
|
||||
#define IEP_MMU_ZAP_ONE_LINE (IEP_MMU_BASE+0x10)
|
||||
#define IEP_MMU_INT_RAWSTAT (IEP_MMU_BASE+0x14)
|
||||
#define IEP_MMU_INT_CLEAR (IEP_MMU_BASE+0x18)
|
||||
#define IEP_MMU_INT_MASK (IEP_MMU_BASE+0x1c)
|
||||
#define IEP_MMU_INT_STATUS (IEP_MMU_BASE+0x20)
|
||||
#define IEP_MMU_AUTO_GATING (IEP_MMU_BASE+0x24)
|
||||
#endif
|
||||
|
||||
#define ReadReg32(base, raddr) (__raw_readl(base + raddr))
|
||||
#define WriteReg32(base, waddr, value) (__raw_writel(value, base + waddr))
|
||||
#define ConfRegBits32(base, raddr, waddr, position, value) WriteReg32(base, waddr, (ReadReg32(base, waddr)&~(position))|(value))
|
||||
#define MaskRegBits32(base, waddr, position, value) WriteReg32(base, waddr, (ReadReg32(base, waddr)&~(position))|(value))
|
||||
|
||||
#endif
|
||||
1186
drivers/video/rockchip/iep/hw_iep_reg.c
Executable file
1186
drivers/video/rockchip/iep/hw_iep_reg.c
Executable file
File diff suppressed because it is too large
Load Diff
677
drivers/video/rockchip/iep/hw_iep_reg.h
Executable file
677
drivers/video/rockchip/iep/hw_iep_reg.h
Executable file
@@ -0,0 +1,677 @@
|
||||
#ifndef IEP_REGS_H
|
||||
#define IEP_REGS_H
|
||||
#include "hw_iep_config_addr.h"
|
||||
#include "iep_api.h"
|
||||
#include "iep.h"
|
||||
#include "iep_drv.h"
|
||||
//#include "typedef.h"
|
||||
|
||||
struct iep_status {
|
||||
uint32_t reserved0 : 1;
|
||||
uint32_t scl_sts : 1;
|
||||
uint32_t dil_sts : 1;
|
||||
uint32_t reserved1 : 1;
|
||||
uint32_t wyuv_sts : 1;
|
||||
uint32_t ryuv_sts : 1;
|
||||
uint32_t wrgb_sts : 1;
|
||||
uint32_t rrgb_sts : 1;
|
||||
uint32_t voi_sts : 1;
|
||||
};
|
||||
|
||||
#if defined(CONFIG_IEP_MMU)
|
||||
struct iep_mmu_status {
|
||||
uint32_t paging_enabled : 1;
|
||||
uint32_t page_fault_active : 1;
|
||||
uint32_t stall_active : 1;
|
||||
uint32_t idle : 1;
|
||||
uint32_t replay_buffer_empty : 1;
|
||||
uint32_t page_fault_is_write : 1;
|
||||
uint32_t page_fault_bus_id : 5;
|
||||
};
|
||||
|
||||
struct iep_mmu_int_status {
|
||||
uint32_t page_fault : 1;
|
||||
uint32_t read_bus_error : 1;
|
||||
};
|
||||
|
||||
enum iep_mmu_cmd {
|
||||
MMU_ENABLE_PAGING,
|
||||
MMU_DISABLE_PAGING,
|
||||
MMU_ENABLE_STALL,
|
||||
MMU_DISABLE_STALL,
|
||||
MMU_ZAP_CACHE,
|
||||
MMU_PAGE_FAULT_DONE,
|
||||
MMU_FORCE_RESET
|
||||
};
|
||||
#endif
|
||||
|
||||
//<2F>м<EFBFBD><D0BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>õ<EFBFBD>ַ
|
||||
#define rIEP_CONFIG0 (IEP_BASE+IEP_CONFIG0)
|
||||
#define rIEP_CONFIG1 (IEP_BASE+IEP_CONFIG1)
|
||||
|
||||
#define rIEP_STATUS (IEP_BASE+IEP_STATUS)
|
||||
#define rIEP_INT (IEP_BASE+IEP_INT)
|
||||
#define rIEP_FRM_START (IEP_BASE+IEP_FRM_START)
|
||||
#define rIEP_SOFT_RST (IEP_BASE+IEP_SOFT_RST)
|
||||
#define rIEP_CONF_DONE (IEP_BASE+IEP_CONF_DONE)
|
||||
|
||||
#define rIEP_VIR_IMG_WIDTH (IEP_BASE+IEP_VIR_IMG_WIDTH)
|
||||
|
||||
#define rIEP_IMG_SCL_FCT (IEP_BASE+IEP_IMG_SCL_FCT)
|
||||
|
||||
#define rIEP_SRC_IMG_SIZE (IEP_BASE+IEP_SRC_IMG_SIZE)
|
||||
#define rIEP_DST_IMG_SIZE (IEP_BASE+IEP_DST_IMG_SIZE)
|
||||
|
||||
#define rIEP_DST_IMG_WIDTH_TILE0 (IEP_BASE+IEP_DST_IMG_WIDTH_TILE0)
|
||||
#define rIEP_DST_IMG_WIDTH_TILE1 (IEP_BASE+IEP_DST_IMG_WIDTH_TILE1)
|
||||
#define rIEP_DST_IMG_WIDTH_TILE2 (IEP_BASE+IEP_DST_IMG_WIDTH_TILE2)
|
||||
#define rIEP_DST_IMG_WIDTH_TILE3 (IEP_BASE+IEP_DST_IMG_WIDTH_TILE3)
|
||||
|
||||
#define rIEP_ENH_YUV_CNFG_0 (IEP_BASE+IEP_ENH_YUV_CNFG_0)
|
||||
#define rIEP_ENH_YUV_CNFG_1 (IEP_BASE+IEP_ENH_YUV_CNFG_1)
|
||||
#define rIEP_ENH_YUV_CNFG_2 (IEP_BASE+IEP_ENH_YUV_CNFG_2)
|
||||
#define rIEP_ENH_RGB_CNFG (IEP_BASE+IEP_ENH_RGB_CNFG)
|
||||
#define rIEP_ENH_C_COE (IEP_BASE+IEP_ENH_C_COE)
|
||||
|
||||
#define rIEP_SRC_ADDR_YRGB (IEP_BASE+IEP_SRC_ADDR_YRGB)
|
||||
#define rIEP_SRC_ADDR_CBCR (IEP_BASE+IEP_SRC_ADDR_CBCR)
|
||||
#define rIEP_SRC_ADDR_CR (IEP_BASE+IEP_SRC_ADDR_CR)
|
||||
#define rIEP_SRC_ADDR_Y1 (IEP_BASE+IEP_SRC_ADDR_Y1)
|
||||
#define rIEP_SRC_ADDR_CBCR1 (IEP_BASE+IEP_SRC_ADDR_CBCR1)
|
||||
#define rIEP_SRC_ADDR_CR1 (IEP_BASE+IEP_SRC_ADDR_CR1)
|
||||
#define rIEP_SRC_ADDR_Y_ITEMP (IEP_BASE+IEP_SRC_ADDR_Y_ITEMP)
|
||||
#define rIEP_SRC_ADDR_CBCR_ITEMP (IEP_BASE+IEP_SRC_ADDR_CBCR_ITEMP)
|
||||
#define rIEP_SRC_ADDR_CR_ITEMP (IEP_BASE+IEP_SRC_ADDR_CR_ITEMP)
|
||||
#define rIEP_SRC_ADDR_Y_FTEMP (IEP_BASE+IEP_SRC_ADDR_Y_FTEMP)
|
||||
#define rIEP_SRC_ADDR_CBCR_FTEMP (IEP_BASE+IEP_SRC_ADDR_CBCR_FTEMP)
|
||||
#define rIEP_SRC_ADDR_CR_FTEMP (IEP_BASE+IEP_SRC_ADDR_CR_FTEMP)
|
||||
|
||||
#define rIEP_DST_ADDR_YRGB (IEP_BASE+IEP_DST_ADDR_YRGB)
|
||||
#define rIEP_DST_ADDR_CBCR (IEP_BASE+IEP_DST_ADDR_CBCR)
|
||||
#define rIEP_DST_ADDR_CR (IEP_BASE+IEP_DST_ADDR_CR)
|
||||
#define rIEP_DST_ADDR_Y1 (IEP_BASE+IEP_DST_ADDR_Y1)
|
||||
#define rIEP_DST_ADDR_CBCR1 (IEP_BASE+IEP_DST_ADDR_CBCR1)
|
||||
#define rIEP_DST_ADDR_CR1 (IEP_BASE+IEP_DST_ADDR_CR1)
|
||||
#define rIEP_DST_ADDR_Y_ITEMP (IEP_BASE+IEP_DST_ADDR_Y_ITEMP)
|
||||
#define rIEP_DST_ADDR_CBCR_ITEMP (IEP_BASE+IEP_DST_ADDR_CBCR_ITEMP)
|
||||
#define rIEP_DST_ADDR_CR_ITEMP (IEP_BASE+IEP_DST_ADDR_CR_ITEMP)
|
||||
#define rIEP_DST_ADDR_Y_FTEMP (IEP_BASE+IEP_DST_ADDR_Y_FTEMP)
|
||||
#define rIEP_DST_ADDR_CBCR_FTEMP (IEP_BASE+IEP_DST_ADDR_CBCR_FTEMP)
|
||||
#define rIEP_DST_ADDR_CR_FTEMP (IEP_BASE+IEP_DST_ADDR_CR_FTEMP)
|
||||
|
||||
#define rIEP_DIL_MTN_TAB0 (IEP_BASE+IEP_DIL_MTN_TAB0)
|
||||
#define rIEP_DIL_MTN_TAB1 (IEP_BASE+IEP_DIL_MTN_TAB1)
|
||||
#define rIEP_DIL_MTN_TAB2 (IEP_BASE+IEP_DIL_MTN_TAB2)
|
||||
#define rIEP_DIL_MTN_TAB3 (IEP_BASE+IEP_DIL_MTN_TAB3)
|
||||
#define rIEP_DIL_MTN_TAB4 (IEP_BASE+IEP_DIL_MTN_TAB4)
|
||||
#define rIEP_DIL_MTN_TAB5 (IEP_BASE+IEP_DIL_MTN_TAB5)
|
||||
#define rIEP_DIL_MTN_TAB6 (IEP_BASE+IEP_DIL_MTN_TAB6)
|
||||
#define rIEP_DIL_MTN_TAB7 (IEP_BASE+IEP_DIL_MTN_TAB7)
|
||||
|
||||
#define rIEP_ENH_CG_TAB (IEP_BASE+IEP_ENH_CG_TAB)
|
||||
|
||||
#define rIEP_YUV_DNS_CRCT_TEMP (IEP_BASE+IEP_YUV_DNS_CRCT_TEMP)
|
||||
#define rIEP_YUV_DNS_CRCT_SPAT (IEP_BASE+IEP_YUV_DNS_CRCT_SPAT)
|
||||
|
||||
#define rIEP_ENH_DDE_COE0 (IEP_BASE+IEP_ENH_DDE_COE0)
|
||||
#define rIEP_ENH_DDE_COE1 (IEP_BASE+IEP_ENH_DDE_COE1)
|
||||
|
||||
#define RAW_rIEP_CONFIG0 (IEP_BASE+RAW_IEP_CONFIG0)
|
||||
#define RAW_rIEP_CONFIG1 (IEP_BASE+RAW_IEP_CONFIG1)
|
||||
#define RAW_rIEP_VIR_IMG_WIDTH (IEP_BASE+RAW_IEP_VIR_IMG_WIDTH)
|
||||
|
||||
#define RAW_rIEP_IMG_SCL_FCT (IEP_BASE+RAW_IEP_IMG_SCL_FCT)
|
||||
|
||||
#define RAW_rIEP_SRC_IMG_SIZE (IEP_BASE+RAW_IEP_SRC_IMG_SIZE)
|
||||
#define RAW_rIEP_DST_IMG_SIZE (IEP_BASE+RAW_IEP_DST_IMG_SIZE)
|
||||
|
||||
#define RAW_rIEP_ENH_YUV_CNFG_0 (IEP_BASE+RAW_IEP_ENH_YUV_CNFG_0)
|
||||
#define RAW_rIEP_ENH_YUV_CNFG_1 (IEP_BASE+RAW_IEP_ENH_YUV_CNFG_1)
|
||||
#define RAW_rIEP_ENH_YUV_CNFG_2 (IEP_BASE+RAW_IEP_ENH_YUV_CNFG_2)
|
||||
#define RAW_rIEP_ENH_RGB_CNFG (IEP_BASE+RAW_IEP_ENH_RGB_CNFG)
|
||||
|
||||
#define rIEP_CG_TAB_ADDR (IEP_BASE+0x0100)
|
||||
|
||||
#if defined(CONFIG_IEP_MMU)
|
||||
#define rIEP_MMU_BASE 0x0800
|
||||
#define rIEP_MMU_DTE_ADDR (IEP_MMU_BASE+0x00)
|
||||
#define rIEP_MMU_STATUS (IEP_MMU_BASE+0x04)
|
||||
#define rIEP_MMU_CMD (IEP_MMU_BASE+0x08)
|
||||
#define rIEP_MMU_PAGE_FAULT_ADDR (IEP_MMU_BASE+0x0c)
|
||||
#define rIEP_MMU_ZAP_ONE_LINE (IEP_MMU_BASE+0x10)
|
||||
#define rIEP_MMU_INT_RAWSTAT (IEP_MMU_BASE+0x14)
|
||||
#define rIEP_MMU_INT_CLEAR (IEP_MMU_BASE+0x18)
|
||||
#define rIEP_MMU_INT_MASK (IEP_MMU_BASE+0x1c)
|
||||
#define rIEP_MMU_INT_STATUS (IEP_MMU_BASE+0x20)
|
||||
#define rIEP_MMU_AUTO_GATING (IEP_MMU_BASE+0x24)
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------
|
||||
//reg bit operation definition
|
||||
-----------------------------------------------------------------*/
|
||||
/*-----------------------------------------------------------------
|
||||
//MaskRegBits32(addr, y, z),get z<><7A><EFBFBD>м<EFBFBD><D0BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
-----------------------------------------------------------------*/
|
||||
//iep_config0
|
||||
#define IEP_REGB_V_REVERSE_DISP_Z(x) (((x)&0x1 ) << 31 )
|
||||
#define IEP_REGB_H_REVERSE_DISP_Z(x) (((x)&0x1 ) << 30 )
|
||||
#define IEP_REGB_SCL_EN_Z(x) (((x)&0x1 ) << 28 )
|
||||
#define IEP_REGB_SCL_SEL_Z(x) (((x)&0x3 ) << 26 )
|
||||
#define IEP_REGB_SCL_UP_COE_SEL_Z(x) (((x)&0x3 ) << 24 )
|
||||
#define IEP_REGB_DIL_EI_SEL_Z(x) (((x)&0x1 ) << 23 )
|
||||
#define IEP_REGB_DIL_EI_RADIUS_Z(x) (((x)&0x3 ) << 21 )
|
||||
#define IEP_REGB_CON_GAM_ORDER_Z(x) (((x)&0x1 ) << 20 )
|
||||
#define IEP_REGB_RGB_ENH_SEL_Z(x) (((x)&0x3 ) << 18 )
|
||||
#define IEP_REGB_RGB_CON_GAM_EN_Z(x) (((x)&0x1 ) << 17 )
|
||||
#define IEP_REGB_RGB_COLOR_ENH_EN_Z(x) (((x)&0x1 ) << 16 )
|
||||
#define IEP_REGB_DIL_EI_SMOOTH_Z(x) (((x)&0x1 ) << 15 )
|
||||
#define IEP_REGB_YUV_ENH_EN_Z(x) (((x)&0x1 ) << 14 )
|
||||
#define IEP_REGB_YUV_DNS_EN_Z(x) (((x)&0x1 ) << 13 )
|
||||
#define IEP_REGB_DIL_EI_MODE_Z(x) (((x)&0x1 ) << 12 )
|
||||
#define IEP_REGB_DIL_HF_EN_Z(x) (((x)&0x1 ) << 11 )
|
||||
#define IEP_REGB_DIL_MODE_Z(x) (((x)&0x7 ) << 8 )
|
||||
#define IEP_REGB_DIL_HF_FCT_Z(x) (((x)&0x7F) << 1 )
|
||||
#define IEP_REGB_LCDC_PATH_EN_Z(x) (((x)&0x1 ) << 0 )
|
||||
|
||||
//iep_conig1
|
||||
#define IEP_REGB_GLB_ALPHA_Z(x) (((x)&0xff) << 24 )
|
||||
#define IEP_REGB_RGB2YUV_INPUT_CLIP_Z(x) (((x)&0x1 ) << 23 )
|
||||
#define IEP_REGB_YUV2RGB_INPUT_CLIP_Z(x) (((x)&0x1 ) << 22 )
|
||||
#define IEP_REGB_RGB_TO_YUV_EN_Z(x) (((x)&0x1 ) << 21 )
|
||||
#define IEP_REGB_YUV_TO_RGB_EN_Z(x) (((x)&0x1 ) << 20 )
|
||||
#define IEP_REGB_RGB2YUV_COE_SEL_Z(x) (((x)&0x3 ) << 18 )
|
||||
#define IEP_REGB_YUV2RGB_COE_SEL_Z(x) (((x)&0x3 ) << 16 )
|
||||
#define IEP_REGB_DITHER_DOWN_EN_Z(x) (((x)&0x1 ) << 15 )
|
||||
#define IEP_REGB_DITHER_UP_EN_Z(x) (((x)&0x1 ) << 14 )
|
||||
#define IEP_REGB_DST_YUV_SWAP_Z(x) (((x)&0x3 ) << 12 )
|
||||
#define IEP_REGB_DST_RGB_SWAP_Z(x) (((x)&0x3 ) << 10 )
|
||||
#define IEP_REGB_DST_FMT_Z(x) (((x)&0x3 ) << 8 )
|
||||
#define IEP_REGB_SRC_YUV_SWAP_Z(x) (((x)&0x3 ) << 4 )
|
||||
#define IEP_REGB_SRC_RGB_SWAP_Z(x) (((x)&0x3 ) << 2 )
|
||||
#define IEP_REGB_SRC_FMT_Z(x) (((x)&0x3 ) << 0 )
|
||||
|
||||
//iep_int
|
||||
#define IEP_REGB_FRAME_END_INT_CLR_Z(x) (((x)&0x1 ) << 16 )
|
||||
#define IEP_REGB_FRAME_END_INT_EN_Z(x) (((x)&0x1 ) << 8 )
|
||||
|
||||
//frm_start
|
||||
#define IEP_REGB_FRM_START_Z(x) (((x)&0x01 ) << 0 )
|
||||
|
||||
//soft_rst
|
||||
#define IEP_REGB_SOFT_RST_Z(x) (((x)&0x01 ) << 0 )
|
||||
|
||||
//iep_vir_img_width
|
||||
#define IEP_REGB_DST_VIR_LINE_WIDTH_Z(x) (((x)&0xffff) << 16 )
|
||||
#define IEP_REGB_SRC_VIR_LINE_WIDTH_Z(x) (((x)&0xffff) << 0 )
|
||||
|
||||
//iep_img_scl_fct
|
||||
#define IEP_REGB_SCL_VRT_FCT_Z(x) (((x)&0xffff) << 16 )
|
||||
#define IEP_REGB_SCL_HRZ_FCT_Z(x) (((x)&0xffff) << 0 )
|
||||
|
||||
//iep_src_img_size
|
||||
#define IEP_REGB_SRC_IMG_HEIGHT_Z(x) (((x)&0x1fff) << 16 )
|
||||
#define IEP_REGB_SRC_IMG_WIDTH_Z(x) (((x)&0x1fff) << 0 )
|
||||
//iep_dst_img_size
|
||||
#define IEP_REGB_DST_IMG_HEIGHT_Z(x) (((x)&0x1fff) << 16 )
|
||||
#define IEP_REGB_DST_IMG_WIDTH_Z(x) (((x)&0x1fff) << 0 )
|
||||
|
||||
//dst_img_width_tile0/1/2/3
|
||||
#define IEP_REGB_DST_IMG_WIDTH_TILE0_Z(x) (((x)&0x3ff ) << 0 )
|
||||
#define IEP_REGB_DST_IMG_WIDTH_TILE1_Z(x) (((x)&0x3ff ) << 0 )
|
||||
#define IEP_REGB_DST_IMG_WIDTH_TILE2_Z(x) (((x)&0x3ff ) << 0 )
|
||||
#define IEP_REGB_DST_IMG_WIDTH_TILE3_Z(x) (((x)&0x3ff ) << 0 )
|
||||
|
||||
//iep_enh_yuv_cnfg0
|
||||
#define IEP_REGB_SAT_CON_Z(x) (((x)&0x1ff ) << 16 )
|
||||
#define IEP_REGB_CONTRAST_Z(x) (((x)&0xff ) << 8 )
|
||||
#define IEP_REGB_BRIGHTNESS_Z(x) (((x)&0x3f ) << 0 )
|
||||
//iep_enh_yuv_cnfg1
|
||||
#define IEP_REGB_COS_HUE_Z(x) (((x)&0xff ) << 8 )
|
||||
#define IEP_REGB_SIN_HUE_Z(x) (((x)&0xff ) << 0 )
|
||||
//iep_enh_yuv_cnfg2
|
||||
#define IEP_REGB_VIDEO_MODE_Z(x) (((x)&0x3 ) << 24 )
|
||||
#define IEP_REGB_COLOR_BAR_V_Z(x) (((x)&0xff ) << 16 )
|
||||
#define IEP_REGB_COLOR_BAR_U_Z(x) (((x)&0xff ) << 8 )
|
||||
#define IEP_REGB_COLOR_BAR_Y_Z(x) (((x)&0xff ) << 0 )
|
||||
//iep_enh_rgb_cnfg
|
||||
#define IEP_REGB_ENH_THRESHOLD_Z(x) (((x)&0xff ) << 16 )
|
||||
#define IEP_REGB_ENH_ALPHA_Z(x) (((x)&0x3f ) << 8 )
|
||||
#define IEP_REGB_ENH_RADIUS_Z(x) (((x)&0x3 ) << 0 )
|
||||
//iep_enh_c_coe
|
||||
#define IEP_REGB_ENH_C_COE_Z(x) (((x)&0x7f ) << 0 )
|
||||
//dil_mtn_tab
|
||||
#define IEP_REGB_DIL_MTN_TAB0_0_Z(x) (((x)&0x7f ) << 0 )
|
||||
#define IEP_REGB_DIL_MTN_TAB0_1_Z(x) (((x)&0x7f ) << 8 )
|
||||
#define IEP_REGB_DIL_MTN_TAB0_2_Z(x) (((x)&0x7f ) << 16 )
|
||||
#define IEP_REGB_DIL_MTN_TAB0_3_Z(x) (((x)&0x7f ) << 24 )
|
||||
|
||||
#define IEP_REGB_DIL_MTN_TAB1_0_Z(x) (((x)&0x7f ) << 0 )
|
||||
#define IEP_REGB_DIL_MTN_TAB1_1_Z(x) (((x)&0x7f ) << 8 )
|
||||
#define IEP_REGB_DIL_MTN_TAB1_2_Z(x) (((x)&0x7f ) << 16 )
|
||||
#define IEP_REGB_DIL_MTN_TAB1_3_Z(x) (((x)&0x7f ) << 24 )
|
||||
|
||||
#define IEP_REGB_DIL_MTN_TAB2_0_Z(x) (((x)&0x7f ) << 0 )
|
||||
#define IEP_REGB_DIL_MTN_TAB2_1_Z(x) (((x)&0x7f ) << 8 )
|
||||
#define IEP_REGB_DIL_MTN_TAB2_2_Z(x) (((x)&0x7f ) << 16 )
|
||||
#define IEP_REGB_DIL_MTN_TAB2_3_Z(x) (((x)&0x7f ) << 24 )
|
||||
|
||||
#define IEP_REGB_DIL_MTN_TAB3_0_Z(x) (((x)&0x7f ) << 0 )
|
||||
#define IEP_REGB_DIL_MTN_TAB3_1_Z(x) (((x)&0x7f ) << 8 )
|
||||
#define IEP_REGB_DIL_MTN_TAB3_2_Z(x) (((x)&0x7f ) << 16 )
|
||||
#define IEP_REGB_DIL_MTN_TAB3_3_Z(x) (((x)&0x7f ) << 24 )
|
||||
|
||||
#define IEP_REGB_DIL_MTN_TAB4_0_Z(x) (((x)&0x7f ) << 0 )
|
||||
#define IEP_REGB_DIL_MTN_TAB4_1_Z(x) (((x)&0x7f ) << 8 )
|
||||
#define IEP_REGB_DIL_MTN_TAB4_2_Z(x) (((x)&0x7f ) << 16 )
|
||||
#define IEP_REGB_DIL_MTN_TAB4_3_Z(x) (((x)&0x7f ) << 24 )
|
||||
|
||||
#define IEP_REGB_DIL_MTN_TAB5_0_Z(x) (((x)&0x7f ) << 0 )
|
||||
#define IEP_REGB_DIL_MTN_TAB5_1_Z(x) (((x)&0x7f ) << 8 )
|
||||
#define IEP_REGB_DIL_MTN_TAB5_2_Z(x) (((x)&0x7f ) << 16 )
|
||||
#define IEP_REGB_DIL_MTN_TAB5_3_Z(x) (((x)&0x7f ) << 24 )
|
||||
|
||||
#define IEP_REGB_DIL_MTN_TAB6_0_Z(x) (((x)&0x7f ) << 0 )
|
||||
#define IEP_REGB_DIL_MTN_TAB6_1_Z(x) (((x)&0x7f ) << 8 )
|
||||
#define IEP_REGB_DIL_MTN_TAB6_2_Z(x) (((x)&0x7f ) << 16 )
|
||||
#define IEP_REGB_DIL_MTN_TAB6_3_Z(x) (((x)&0x7f ) << 24 )
|
||||
|
||||
#define IEP_REGB_DIL_MTN_TAB7_0_Z(x) (((x)&0x7f ) << 0 )
|
||||
#define IEP_REGB_DIL_MTN_TAB7_1_Z(x) (((x)&0x7f ) << 8 )
|
||||
#define IEP_REGB_DIL_MTN_TAB7_2_Z(x) (((x)&0x7f ) << 16 )
|
||||
#define IEP_REGB_DIL_MTN_TAB7_3_Z(x) (((x)&0x7f ) << 24 )
|
||||
|
||||
#if defined(CONFIG_IEP_MMU)
|
||||
// mmu
|
||||
#define IEP_REGB_MMU_STATUS_PAGING_ENABLE_Z(x) (((x)&0x01) << 0)
|
||||
#define IEP_REGB_MMU_STATUS_PAGE_FAULT_ACTIVE_Z(x) (((x)&0x01) << 1)
|
||||
#define IEP_REGB_MMU_STATUS_STALL_ACTIVE_Z(x) (((x)&0x01) << 2)
|
||||
#define IEP_REGB_MMU_STATUS_IDLE_Z(x) (((x)&0x01) << 3)
|
||||
#define IEP_REGB_MMU_STATUS_REPLAY_BUFFER_EMPTY_Z(x) (((x)&0x01) << 4)
|
||||
#define IEP_REGB_MMU_STATUS_PAGE_FAULT_IS_WRITE_Z(x) (((x)&0x01) << 5)
|
||||
#define IEP_REGB_MMU_STATUS_PAGE_FAULT_BUS_ID_Z(x) (((x)&0x1F) << 6)
|
||||
|
||||
#define IEP_REGB_MMU_CMD_Z(x) (((x)&0x07) << 0)
|
||||
|
||||
#define IEP_REGB_MMU_ZAP_ONE_LINE_Z(x) (((x)&0x01) << 0)
|
||||
|
||||
#define IEP_REGB_MMU_INT_RAWSTAT_PAGE_FAULT_Z(x) (((x)&0x01) << 0)
|
||||
#define IEP_REGB_MMU_INT_RAWSTAT_READ_BUS_ERROR_Z(x) (((x)&0x01) << 1)
|
||||
|
||||
#define IEP_REGB_MMU_INT_CLEAR_PAGE_FAULT_CLEAR_Z(x) (((x)&0x01) << 0)
|
||||
#define IEP_REGB_MMU_INT_CLEAR_READ_BUS_ERROR_CLEAR_Z(x) (((x)&0x01) << 1)
|
||||
|
||||
#define IEP_REGB_MMU_INT_MASK_PAGE_FAULT_INT_EN_Z(x) (((x)&0x01) << 0)
|
||||
#define IEP_REGB_MMU_INT_MASK_READ_BUS_ERROR_INT_EN_Z(x) (((x)&0x01) << 1)
|
||||
|
||||
#define IEP_REGB_MMU_INT_STATUS_PAGE_FAULT_Z(x) (((x)&0x01) << 0)
|
||||
#define IEP_REGB_MMU_INT_STATUS_READ_BUS_ERROR_Z(x) (((x)&0x01) << 1)
|
||||
|
||||
#define IEP_REGB_MMU_AUTO_GATING_Z(x) (((x)&0x01) << 0)
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------
|
||||
//MaskRegBits32(addr, y, z),get y<><79><EFBFBD>м<EFBFBD><D0BC><EFBFBD><EFBFBD><EFBFBD>
|
||||
-----------------------------------------------------------------*/
|
||||
//iep_config0
|
||||
#define IEP_REGB_V_REVERSE_DISP_Y (0x1 << 31 )
|
||||
#define IEP_REGB_H_REVERSE_DISP_Y (0x1 << 30 )
|
||||
#define IEP_REGB_SCL_EN_Y (0x1 << 28 )
|
||||
#define IEP_REGB_SCL_SEL_Y (0x3 << 26 )
|
||||
#define IEP_REGB_SCL_UP_COE_SEL_Y (0x3 << 24 )
|
||||
#define IEP_REGB_DIL_EI_SEL_Y (0x1 << 23 )
|
||||
#define IEP_REGB_DIL_EI_RADIUS_Y (0x3 << 21 )
|
||||
#define IEP_REGB_CON_GAM_ORDER_Y (0x1 << 20 )
|
||||
#define IEP_REGB_RGB_ENH_SEL_Y (0x3 << 18 )
|
||||
#define IEP_REGB_RGB_CON_GAM_EN_Y (0x1 << 17 )
|
||||
#define IEP_REGB_RGB_COLOR_ENH_EN_Y (0x1 << 16 )
|
||||
#define IEP_REGB_DIL_EI_SMOOTH_Y (0x1 << 15 )
|
||||
#define IEP_REGB_YUV_ENH_EN_Y (0x1 << 14 )
|
||||
#define IEP_REGB_YUV_DNS_EN_Y (0x1 << 13 )
|
||||
#define IEP_REGB_DIL_EI_MODE_Y (0x1 << 12 )
|
||||
#define IEP_REGB_DIL_HF_EN_Y (0x1 << 11 )
|
||||
#define IEP_REGB_DIL_MODE_Y (0x7 << 8 )
|
||||
#define IEP_REGB_DIL_HF_FCT_Y (0x7F << 1 )
|
||||
#define IEP_REGB_LCDC_PATH_EN_Y (0x1 << 0 )
|
||||
|
||||
//iep_conig1
|
||||
#define IEP_REGB_GLB_ALPHA_Y (0xff << 24 )
|
||||
#define IEP_REGB_RGB2YUV_INPUT_CLIP_Y (0x1 << 23 )
|
||||
#define IEP_REGB_YUV2RGB_INPUT_CLIP_Y (0x1 << 22 )
|
||||
#define IEP_REGB_RGB_TO_YUV_EN_Y (0x1 << 21 )
|
||||
#define IEP_REGB_YUV_TO_RGB_EN_Y (0x1 << 20 )
|
||||
#define IEP_REGB_RGB2YUV_COE_SEL_Y (0x3 << 18 )
|
||||
#define IEP_REGB_YUV2RGB_COE_SEL_Y (0x3 << 16 )
|
||||
#define IEP_REGB_DITHER_DOWN_EN_Y (0x1 << 15 )
|
||||
#define IEP_REGB_DITHER_UP_EN_Y (0x1 << 14 )
|
||||
#define IEP_REGB_DST_YUV_SWAP_Y (0x3 << 12 )
|
||||
#define IEP_REGB_DST_RGB_SWAP_Y (0x3 << 10 )
|
||||
#define IEP_REGB_DST_FMT_Y (0x3 << 8 )
|
||||
#define IEP_REGB_SRC_YUV_SWAP_Y (0x3 << 4 )
|
||||
#define IEP_REGB_SRC_RGB_SWAP_Y (0x3 << 2 )
|
||||
#define IEP_REGB_SRC_FMT_Y (0x3 << 0 )
|
||||
|
||||
//iep_int
|
||||
#define IEP_REGB_FRAME_END_INT_CLR_Y (0x1 << 16 )
|
||||
#define IEP_REGB_FRAME_END_INT_EN_Y (0x1 << 8 )
|
||||
|
||||
//frm_start
|
||||
#define IEP_REGB_FRM_START_Y (0x1 << 0 )
|
||||
|
||||
//soft_rst
|
||||
#define IEP_REGB_SOFT_RST_Y (0x1 << 0 )
|
||||
|
||||
//iep_vir_img_width
|
||||
#define IEP_REGB_DST_VIR_LINE_WIDTH_Y (0xffff << 16 )
|
||||
#define IEP_REGB_SRC_VIR_LINE_WIDTH_Y (0xffff << 0 )
|
||||
|
||||
//iep_img_scl_fct
|
||||
#define IEP_REGB_SCL_VRT_FCT_Y (0xffff << 16 )
|
||||
#define IEP_REGB_SCL_HRZ_FCT_Y (0xffff << 0 )
|
||||
|
||||
//iep_src_img_size
|
||||
#define IEP_REGB_SRC_IMG_HEIGHT_Y (0x1fff << 16 )
|
||||
#define IEP_REGB_SRC_IMG_WIDTH_Y (0x1fff << 0 )
|
||||
//iep_dst_img_size
|
||||
#define IEP_REGB_DST_IMG_HEIGHT_Y (0x1fff << 16 )
|
||||
#define IEP_REGB_DST_IMG_WIDTH_Y (0x1fff << 0 )
|
||||
|
||||
//dst_img_width_tile0/1/2/3
|
||||
#define IEP_REGB_DST_IMG_WIDTH_TILE0_Y (0x3ff << 0 )
|
||||
#define IEP_REGB_DST_IMG_WIDTH_TILE1_Y (0x3ff << 0 )
|
||||
#define IEP_REGB_DST_IMG_WIDTH_TILE2_Y (0x3ff << 0 )
|
||||
#define IEP_REGB_DST_IMG_WIDTH_TILE3_Y (0x3ff << 0 )
|
||||
|
||||
//iep_enh_yuv_cnfg0
|
||||
#define IEP_REGB_SAT_CON_Y (0x1ff << 16)
|
||||
#define IEP_REGB_CONTRAST_Y (0xff << 8 )
|
||||
#define IEP_REGB_BRIGHTNESS_Y (0x3f << 0 )
|
||||
//iep_enh_yuv_cnfg1
|
||||
#define IEP_REGB_COS_HUE_Y (0xff << 8 )
|
||||
#define IEP_REGB_SIN_HUE_Y (0xff << 0 )
|
||||
//iep_enh_yuv_cnfg2
|
||||
#define IEP_REGB_VIDEO_MODE_Y (0x3 << 24)
|
||||
#define IEP_REGB_COLOR_BAR_V_Y (0xff << 16)
|
||||
#define IEP_REGB_COLOR_BAR_U_Y (0xff << 8 )
|
||||
#define IEP_REGB_COLOR_BAR_Y_Y (0xff << 0 )
|
||||
//iep_enh_rgb_cnfg
|
||||
#define IEP_REGB_ENH_THRESHOLD_Y (0xff << 16)
|
||||
#define IEP_REGB_ENH_ALPHA_Y (0x3f << 8 )
|
||||
#define IEP_REGB_ENH_RADIUS_Y (0x3 << 0 )
|
||||
//iep_enh_c_coe
|
||||
#define IEP_REGB_ENH_C_COE_Y (0x7f << 0 )
|
||||
//dil_mtn_tab
|
||||
#define IEP_REGB_DIL_MTN_TAB0_0_Y (0x7f << 0 )
|
||||
#define IEP_REGB_DIL_MTN_TAB0_1_Y (0x7f << 8 )
|
||||
#define IEP_REGB_DIL_MTN_TAB0_2_Y (0x7f << 16 )
|
||||
#define IEP_REGB_DIL_MTN_TAB0_3_Y (0x7f << 24 )
|
||||
|
||||
#define IEP_REGB_DIL_MTN_TAB1_0_Y (0x7f << 0 )
|
||||
#define IEP_REGB_DIL_MTN_TAB1_1_Y (0x7f << 8 )
|
||||
#define IEP_REGB_DIL_MTN_TAB1_2_Y (0x7f << 16 )
|
||||
#define IEP_REGB_DIL_MTN_TAB1_3_Y (0x7f << 24 )
|
||||
|
||||
#define IEP_REGB_DIL_MTN_TAB2_0_Y (0x7f << 0 )
|
||||
#define IEP_REGB_DIL_MTN_TAB2_1_Y (0x7f << 8 )
|
||||
#define IEP_REGB_DIL_MTN_TAB2_2_Y (0x7f << 16 )
|
||||
#define IEP_REGB_DIL_MTN_TAB2_3_Y (0x7f << 24 )
|
||||
|
||||
#define IEP_REGB_DIL_MTN_TAB3_0_Y (0x7f << 0 )
|
||||
#define IEP_REGB_DIL_MTN_TAB3_1_Y (0x7f << 8 )
|
||||
#define IEP_REGB_DIL_MTN_TAB3_2_Y (0x7f << 16 )
|
||||
#define IEP_REGB_DIL_MTN_TAB3_3_Y (0x7f << 24 )
|
||||
|
||||
#define IEP_REGB_DIL_MTN_TAB4_0_Y (0x7f << 0 )
|
||||
#define IEP_REGB_DIL_MTN_TAB4_1_Y (0x7f << 8 )
|
||||
#define IEP_REGB_DIL_MTN_TAB4_2_Y (0x7f << 16 )
|
||||
#define IEP_REGB_DIL_MTN_TAB4_3_Y (0x7f << 24 )
|
||||
|
||||
#define IEP_REGB_DIL_MTN_TAB5_0_Y (0x7f << 0 )
|
||||
#define IEP_REGB_DIL_MTN_TAB5_1_Y (0x7f << 8 )
|
||||
#define IEP_REGB_DIL_MTN_TAB5_2_Y (0x7f << 16 )
|
||||
#define IEP_REGB_DIL_MTN_TAB5_3_Y (0x7f << 24 )
|
||||
|
||||
#define IEP_REGB_DIL_MTN_TAB6_0_Y (0x7f << 0 )
|
||||
#define IEP_REGB_DIL_MTN_TAB6_1_Y (0x7f << 8 )
|
||||
#define IEP_REGB_DIL_MTN_TAB6_2_Y (0x7f << 16 )
|
||||
#define IEP_REGB_DIL_MTN_TAB6_3_Y (0x7f << 24 )
|
||||
|
||||
#define IEP_REGB_DIL_MTN_TAB7_0_Y (0x7f << 0 )
|
||||
#define IEP_REGB_DIL_MTN_TAB7_1_Y (0x7f << 8 )
|
||||
#define IEP_REGB_DIL_MTN_TAB7_2_Y (0x7f << 16 )
|
||||
#define IEP_REGB_DIL_MTN_TAB7_3_Y (0x7f << 24 )
|
||||
|
||||
#if defined(CONFIG_IEP_MMU)
|
||||
// mmu
|
||||
#define IEP_REGB_MMU_STATUS_PAGING_ENABLE_Y (0x01 << 0)
|
||||
#define IEP_REGB_MMU_STATUS_PAGE_FAULT_ACTIVE_Y (0x01 << 1)
|
||||
#define IEP_REGB_MMU_STATUS_STALL_ACTIVE_Y (0x01 << 2)
|
||||
#define IEP_REGB_MMU_STATUS_IDLE_Y (0x01 << 3)
|
||||
#define IEP_REGB_MMU_STATUS_REPLAY_BUFFER_EMPTY_Y (0x01 << 4)
|
||||
#define IEP_REGB_MMU_STATUS_PAGE_FAULT_IS_WRITE_Y (0x01 << 5)
|
||||
#define IEP_REGB_MMU_STATUS_PAGE_FAULT_BUS_ID_Y (0x1F << 6)
|
||||
|
||||
#define IEP_REGB_MMU_CMD_Y (0x07 << 0)
|
||||
|
||||
#define IEP_REGB_MMU_ZAP_ONE_LINE_Y (0x01 << 0)
|
||||
|
||||
#define IEP_REGB_MMU_INT_RAWSTAT_PAGE_FAULT_Y (0x01 << 0)
|
||||
#define IEP_REGB_MMU_INT_RAWSTAT_READ_BUS_ERROR_Y (0x01 << 1)
|
||||
|
||||
#define IEP_REGB_MMU_INT_CLEAR_PAGE_FAULT_CLEAR_Y (0x01 << 0)
|
||||
#define IEP_REGB_MMU_INT_CLEAR_READ_BUS_ERROR_CLEAR_Y (0x01 << 1)
|
||||
|
||||
#define IEP_REGB_MMU_INT_MASK_PAGE_FAULT_INT_EN_Y (0x01 << 0)
|
||||
#define IEP_REGB_MMU_INT_MASK_READ_BUS_ERROR_INT_EN_Y (0x01 << 1)
|
||||
|
||||
#define IEP_REGB_MMU_INT_STATUS_PAGE_FAULT_Y (0x01 << 0)
|
||||
#define IEP_REGB_MMU_INT_STATUS_READ_BUS_ERROR_Y (0x01 << 1)
|
||||
|
||||
#define IEP_REGB_MMU_AUTO_GATING_Y (0x01 << 0)
|
||||
|
||||
// offset
|
||||
#define IEP_REGB_MMU_STATUS_PAGING_ENABLE_F (0)
|
||||
#define IEP_REGB_MMU_STATUS_PAGE_FAULT_ACTIVE_F (1)
|
||||
#define IEP_REGB_MMU_STATUS_STALL_ACTIVE_F (2)
|
||||
#define IEP_REGB_MMU_STATUS_IDLE_F (3)
|
||||
#define IEP_REGB_MMU_STATUS_REPLAY_BUFFER_EMPTY_F (4)
|
||||
#define IEP_REGB_MMU_STATUS_PAGE_FAULT_IS_WRITE_F (5)
|
||||
#define IEP_REGB_MMU_STATUS_PAGE_FAULT_BUS_ID_F (6)
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------
|
||||
//MaskRegBits32(addr, y, z),<2C>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
-----------------------------------------------------------------*/
|
||||
//iep_config0
|
||||
#define IEP_REGB_V_REVERSE_DISP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_V_REVERSE_DISP_Y,IEP_REGB_V_REVERSE_DISP_Z(x))
|
||||
#define IEP_REGB_H_REVERSE_DISP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_H_REVERSE_DISP_Y,IEP_REGB_H_REVERSE_DISP_Z(x))
|
||||
#define IEP_REGB_SCL_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_SCL_EN_Y,IEP_REGB_SCL_EN_Z(x))
|
||||
#define IEP_REGB_SCL_SEL(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_SCL_SEL_Y,IEP_REGB_SCL_SEL_Z(x))
|
||||
#define IEP_REGB_SCL_UP_COE_SEL(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_SCL_UP_COE_SEL_Y,IEP_REGB_SCL_UP_COE_SEL_Z(x))
|
||||
#define IEP_REGB_DIL_EI_SEL(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_DIL_EI_SEL_Y,IEP_REGB_DIL_EI_SEL_Z(x))
|
||||
#define IEP_REGB_DIL_EI_RADIUS(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_DIL_EI_RADIUS_Y,IEP_REGB_DIL_EI_RADIUS_Z(x))
|
||||
#define IEP_REGB_CON_GAM_ORDER(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_CON_GAM_ORDER_Y,IEP_REGB_CON_GAM_ORDER_Z(x))
|
||||
#define IEP_REGB_RGB_ENH_SEL(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_RGB_ENH_SEL_Y,IEP_REGB_RGB_ENH_SEL_Z(x))
|
||||
#define IEP_REGB_RGB_CON_GAM_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_RGB_CON_GAM_EN_Y,IEP_REGB_RGB_CON_GAM_EN_Z(x))
|
||||
#define IEP_REGB_RGB_COLOR_ENH_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_RGB_COLOR_ENH_EN_Y,IEP_REGB_RGB_COLOR_ENH_EN_Z(x))
|
||||
#define IEP_REGB_DIL_EI_SMOOTH(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_DIL_EI_SMOOTH_Y,IEP_REGB_DIL_EI_SMOOTH_Z(x))
|
||||
#define IEP_REGB_YUV_ENH_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_YUV_ENH_EN_Y,IEP_REGB_YUV_ENH_EN_Z(x))
|
||||
#define IEP_REGB_YUV_DNS_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_YUV_DNS_EN_Y,IEP_REGB_YUV_DNS_EN_Z(x))
|
||||
#define IEP_REGB_DIL_EI_MODE(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_DIL_EI_MODE_Y,IEP_REGB_DIL_EI_MODE_Z(x))
|
||||
#define IEP_REGB_DIL_HF_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_DIL_HF_EN_Y,IEP_REGB_DIL_HF_EN_Z(x))
|
||||
#define IEP_REGB_DIL_MODE(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_DIL_MODE_Y,IEP_REGB_DIL_MODE_Z(x))
|
||||
#define IEP_REGB_DIL_HF_FCT(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_DIL_HF_FCT_Y,IEP_REGB_DIL_HF_FCT_Z(x))
|
||||
#define IEP_REGB_LCDC_PATH_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_LCDC_PATH_EN_Y,IEP_REGB_LCDC_PATH_EN_Z(x))
|
||||
|
||||
//iep_conig1
|
||||
#define IEP_REGB_GLB_ALPHA(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_GLB_ALPHA_Y,IEP_REGB_GLB_ALPHA_Z(x))
|
||||
#define IEP_REGB_RGB2YUV_INPUT_CLIP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_RGB2YUV_INPUT_CLIP_Y,IEP_REGB_RGB2YUV_INPUT_CLIP_Z(x))
|
||||
#define IEP_REGB_YUV2RGB_INPUT_CLIP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_YUV2RGB_INPUT_CLIP_Y,IEP_REGB_YUV2RGB_INPUT_CLIP_Z(x))
|
||||
#define IEP_REGB_RGB_TO_YUV_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_RGB_TO_YUV_EN_Y,IEP_REGB_RGB_TO_YUV_EN_Z(x))
|
||||
#define IEP_REGB_YUV_TO_RGB_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_YUV_TO_RGB_EN_Y,IEP_REGB_YUV_TO_RGB_EN_Z(x))
|
||||
#define IEP_REGB_RGB2YUV_COE_SEL(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_RGB2YUV_COE_SEL_Y,IEP_REGB_RGB2YUV_COE_SEL_Z(x))
|
||||
#define IEP_REGB_YUV2RGB_COE_SEL(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_YUV2RGB_COE_SEL_Y,IEP_REGB_YUV2RGB_COE_SEL_Z(x))
|
||||
#define IEP_REGB_DITHER_DOWN_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_DITHER_DOWN_EN_Y,IEP_REGB_DITHER_DOWN_EN_Z(x))
|
||||
#define IEP_REGB_DITHER_UP_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_DITHER_UP_EN_Y,IEP_REGB_DITHER_UP_EN_Z(x))
|
||||
#define IEP_REGB_DST_YUV_SWAP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_DST_YUV_SWAP_Y,IEP_REGB_DST_YUV_SWAP_Z(x))
|
||||
#define IEP_REGB_DST_RGB_SWAP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_DST_RGB_SWAP_Y,IEP_REGB_DST_RGB_SWAP_Z(x))
|
||||
#define IEP_REGB_DST_FMT(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_DST_FMT_Y,IEP_REGB_DST_FMT_Z(x))
|
||||
#define IEP_REGB_SRC_YUV_SWAP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_SRC_YUV_SWAP_Y,IEP_REGB_SRC_YUV_SWAP_Z(x))
|
||||
#define IEP_REGB_SRC_RGB_SWAP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_SRC_RGB_SWAP_Y,IEP_REGB_SRC_RGB_SWAP_Z(x))
|
||||
#define IEP_REGB_SRC_FMT(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_SRC_FMT_Y,IEP_REGB_SRC_FMT_Z(x))
|
||||
|
||||
//iep_int
|
||||
#define IEP_REGB_FRAME_END_INT_CLR(base, x) MaskRegBits32(base, rIEP_INT,IEP_REGB_FRAME_END_INT_CLR_Y,IEP_REGB_FRAME_END_INT_CLR_Z(x))
|
||||
#define IEP_REGB_FRAME_END_INT_EN(base, x) MaskRegBits32(base, rIEP_INT,IEP_REGB_FRAME_END_INT_EN_Y,IEP_REGB_FRAME_END_INT_EN_Z(x))
|
||||
|
||||
//frm_start
|
||||
#define IEP_REGB_FRM_START(base, x) WriteReg32(base, rIEP_FRM_START,x)
|
||||
|
||||
//soft_rst
|
||||
#define IEP_REGB_SOFT_RST(base, x) WriteReg32(base, rIEP_SOFT_RST,x)
|
||||
|
||||
//iep_vir_img_width
|
||||
#define IEP_REGB_DST_VIR_LINE_WIDTH(base, x) ConfRegBits32(base, RAW_rIEP_VIR_IMG_WIDTH,rIEP_VIR_IMG_WIDTH,IEP_REGB_DST_VIR_LINE_WIDTH_Y,IEP_REGB_DST_VIR_LINE_WIDTH_Z(x))
|
||||
#define IEP_REGB_SRC_VIR_LINE_WIDTH(base, x) ConfRegBits32(base, RAW_rIEP_VIR_IMG_WIDTH,rIEP_VIR_IMG_WIDTH,IEP_REGB_SRC_VIR_LINE_WIDTH_Y,IEP_REGB_SRC_VIR_LINE_WIDTH_Z(x))
|
||||
|
||||
//iep_img_scl_fct
|
||||
#define IEP_REGB_SCL_VRT_FCT(base, x) ConfRegBits32(base, RAW_rIEP_IMG_SCL_FCT,rIEP_IMG_SCL_FCT,IEP_REGB_SCL_VRT_FCT_Y,IEP_REGB_SCL_VRT_FCT_Z(x))
|
||||
#define IEP_REGB_SCL_HRZ_FCT(base, x) ConfRegBits32(base, RAW_rIEP_IMG_SCL_FCT,rIEP_IMG_SCL_FCT,IEP_REGB_SCL_HRZ_FCT_Y,IEP_REGB_SCL_HRZ_FCT_Z(x))
|
||||
|
||||
//iep_src_img_size
|
||||
#define IEP_REGB_SRC_IMG_HEIGHT(base, x) ConfRegBits32(base, RAW_rIEP_SRC_IMG_SIZE,rIEP_SRC_IMG_SIZE,IEP_REGB_SRC_IMG_HEIGHT_Y,IEP_REGB_SRC_IMG_HEIGHT_Z(x))
|
||||
#define IEP_REGB_SRC_IMG_WIDTH(base, x) ConfRegBits32(base, RAW_rIEP_SRC_IMG_SIZE,rIEP_SRC_IMG_SIZE,IEP_REGB_SRC_IMG_WIDTH_Y,IEP_REGB_SRC_IMG_WIDTH_Z(x))
|
||||
//iep_dst_img_size
|
||||
#define IEP_REGB_DST_IMG_HEIGHT(base, x) ConfRegBits32(base, RAW_rIEP_DST_IMG_SIZE,rIEP_DST_IMG_SIZE,IEP_REGB_DST_IMG_HEIGHT_Y,IEP_REGB_DST_IMG_HEIGHT_Z(x))
|
||||
#define IEP_REGB_DST_IMG_WIDTH(base, x) ConfRegBits32(base, RAW_rIEP_DST_IMG_SIZE,rIEP_DST_IMG_SIZE,IEP_REGB_DST_IMG_WIDTH_Y,IEP_REGB_DST_IMG_WIDTH_Z(x))
|
||||
|
||||
//dst_img_width_tile0/1/2/3
|
||||
#define IEP_REGB_DST_IMG_WIDTH_TILE0(base, x) WriteReg32(base, rIEP_DST_IMG_WIDTH_TILE0,x)
|
||||
#define IEP_REGB_DST_IMG_WIDTH_TILE1(base, x) WriteReg32(base, rIEP_DST_IMG_WIDTH_TILE1,x)
|
||||
#define IEP_REGB_DST_IMG_WIDTH_TILE2(base, x) WriteReg32(base, rIEP_DST_IMG_WIDTH_TILE2,x)
|
||||
#define IEP_REGB_DST_IMG_WIDTH_TILE3(base, x) WriteReg32(base, rIEP_DST_IMG_WIDTH_TILE3,x)
|
||||
|
||||
//iep_enh_yuv_cnfg0
|
||||
#define IEP_REGB_SAT_CON(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_0,rIEP_ENH_YUV_CNFG_0,IEP_REGB_SAT_CON_Y,IEP_REGB_SAT_CON_Z(x))
|
||||
#define IEP_REGB_CONTRAST(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_0,rIEP_ENH_YUV_CNFG_0,IEP_REGB_CONTRAST_Y,IEP_REGB_CONTRAST_Z(x))
|
||||
#define IEP_REGB_BRIGHTNESS(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_0,rIEP_ENH_YUV_CNFG_0,IEP_REGB_BRIGHTNESS_Y,IEP_REGB_BRIGHTNESS_Z(x))
|
||||
//iep_enh_yuv_cnfg1
|
||||
#define IEP_REGB_COS_HUE(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_1,rIEP_ENH_YUV_CNFG_1,IEP_REGB_COS_HUE_Y,IEP_REGB_COS_HUE_Z(x))
|
||||
#define IEP_REGB_SIN_HUE(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_1,rIEP_ENH_YUV_CNFG_1,IEP_REGB_SIN_HUE_Y,IEP_REGB_SIN_HUE_Z(x))
|
||||
//iep_enh_yuv_cnfg2
|
||||
#define IEP_REGB_VIDEO_MODE(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_2,rIEP_ENH_YUV_CNFG_2,IEP_REGB_VIDEO_MODE_Y,IEP_REGB_VIDEO_MODE_Z(x))
|
||||
#define IEP_REGB_COLOR_BAR_V(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_2,rIEP_ENH_YUV_CNFG_2,IEP_REGB_COLOR_BAR_V_Y,IEP_REGB_COLOR_BAR_V_Z(x))
|
||||
#define IEP_REGB_COLOR_BAR_U(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_2,rIEP_ENH_YUV_CNFG_2,IEP_REGB_COLOR_BAR_U_Y,IEP_REGB_COLOR_BAR_U_Z(x))
|
||||
#define IEP_REGB_COLOR_BAR_Y(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_2,rIEP_ENH_YUV_CNFG_2,IEP_REGB_COLOR_BAR_Y_Y,IEP_REGB_COLOR_BAR_Y_Z(x))
|
||||
//iep_enh_rgb_cnfg
|
||||
#define IEP_REGB_ENH_THRESHOLD(base, x) ConfRegBits32(base, RAW_rIEP_ENH_RGB_CNFG,rIEP_ENH_RGB_CNFG,IEP_REGB_ENH_THRESHOLD_Y,IEP_REGB_ENH_THRESHOLD_Z(x))
|
||||
#define IEP_REGB_ENH_ALPHA(base, x) ConfRegBits32(base, RAW_rIEP_ENH_RGB_CNFG,rIEP_ENH_RGB_CNFG,IEP_REGB_ENH_ALPHA_Y,IEP_REGB_ENH_ALPHA_Z(x))
|
||||
#define IEP_REGB_ENH_RADIUS(base, x) ConfRegBits32(base, RAW_rIEP_ENH_RGB_CNFG,rIEP_ENH_RGB_CNFG,IEP_REGB_ENH_RADIUS_Y,IEP_REGB_ENH_RADIUS_Z(x))
|
||||
//iep_enh_c_coe
|
||||
#define IEP_REGB_ENH_C_COE(base, x) WriteReg32(base, rIEP_ENH_C_COE,x)
|
||||
//src_addr
|
||||
#define IEP_REGB_SRC_ADDR_YRGB(base, x) WriteReg32(base, rIEP_SRC_ADDR_YRGB, x)
|
||||
#define IEP_REGB_SRC_ADDR_CBCR(base, x) WriteReg32(base, rIEP_SRC_ADDR_CBCR, x)
|
||||
#define IEP_REGB_SRC_ADDR_CR(base, x) WriteReg32(base, rIEP_SRC_ADDR_CR, x)
|
||||
#define IEP_REGB_SRC_ADDR_Y1(base, x) WriteReg32(base, rIEP_SRC_ADDR_Y1, x)
|
||||
#define IEP_REGB_SRC_ADDR_CBCR1(base, x) WriteReg32(base, rIEP_SRC_ADDR_CBCR1, x)
|
||||
#define IEP_REGB_SRC_ADDR_CR1(base, x) WriteReg32(base, rIEP_SRC_ADDR_CR1, x)
|
||||
#define IEP_REGB_SRC_ADDR_Y_ITEMP(base, x) WriteReg32(base, rIEP_SRC_ADDR_Y_ITEMP, x)
|
||||
#define IEP_REGB_SRC_ADDR_CBCR_ITEMP(base, x) WriteReg32(base, rIEP_SRC_ADDR_CBCR_ITEMP, x)
|
||||
#define IEP_REGB_SRC_ADDR_CR_ITEMP(base, x) WriteReg32(base, rIEP_SRC_ADDR_CR_ITEMP, x)
|
||||
#define IEP_REGB_SRC_ADDR_Y_FTEMP(base, x) WriteReg32(base, rIEP_SRC_ADDR_Y_FTEMP, x)
|
||||
#define IEP_REGB_SRC_ADDR_CBCR_FTEMP(base, x) WriteReg32(base, rIEP_SRC_ADDR_CBCR_FTEMP, x)
|
||||
#define IEP_REGB_SRC_ADDR_CR_FTEMP(base, x) WriteReg32(base, rIEP_SRC_ADDR_CR_FTEMP, x)
|
||||
//dst_addr
|
||||
#define IEP_REGB_DST_ADDR_YRGB(base, x) WriteReg32(base, rIEP_DST_ADDR_YRGB,x)
|
||||
#define IEP_REGB_DST_ADDR_CBCR(base, x) WriteReg32(base, rIEP_DST_ADDR_CBCR, x)
|
||||
#define IEP_REGB_DST_ADDR_CR(base, x) WriteReg32(base, rIEP_DST_ADDR_CR, x)
|
||||
#define IEP_REGB_DST_ADDR_Y1(base, x) WriteReg32(base, rIEP_DST_ADDR_Y1, x)
|
||||
#define IEP_REGB_DST_ADDR_CBCR1(base, x) WriteReg32(base, rIEP_DST_ADDR_CBCR1, x)
|
||||
#define IEP_REGB_DST_ADDR_CR1(base, x) WriteReg32(base, rIEP_DST_ADDR_CR1, x)
|
||||
#define IEP_REGB_DST_ADDR_Y_ITEMP(base, x) WriteReg32(base, rIEP_DST_ADDR_Y_ITEMP, x)
|
||||
#define IEP_REGB_DST_ADDR_CBCR_ITEMP(base, x) WriteReg32(base, rIEP_DST_ADDR_CBCR_ITEMP, x)
|
||||
#define IEP_REGB_DST_ADDR_CR_ITEMP(base, x) WriteReg32(base, rIEP_DST_ADDR_CR_ITEMP, x)
|
||||
#define IEP_REGB_DST_ADDR_Y_FTEMP(base, x) WriteReg32(base, rIEP_DST_ADDR_Y_FTEMP, x)
|
||||
#define IEP_REGB_DST_ADDR_CBCR_FTEMP(base, x) WriteReg32(base, rIEP_DST_ADDR_CBCR_FTEMP, x)
|
||||
#define IEP_REGB_DST_ADDR_CR_FTEMP(base, x) WriteReg32(base, rIEP_DST_ADDR_CR_FTEMP, x)
|
||||
|
||||
//dil_mtn_tab
|
||||
#define IEP_REGB_DIL_MTN_TAB0(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB0,x)
|
||||
#define IEP_REGB_DIL_MTN_TAB1(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB1,x)
|
||||
#define IEP_REGB_DIL_MTN_TAB2(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB2,x)
|
||||
#define IEP_REGB_DIL_MTN_TAB3(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB3,x)
|
||||
#define IEP_REGB_DIL_MTN_TAB4(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB4,x)
|
||||
#define IEP_REGB_DIL_MTN_TAB5(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB5,x)
|
||||
#define IEP_REGB_DIL_MTN_TAB6(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB6,x)
|
||||
#define IEP_REGB_DIL_MTN_TAB7(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB7,x)
|
||||
|
||||
#define IEP_REGB_STATUS(base) ReadReg32(base, rIEP_STATUS)
|
||||
|
||||
#if defined(CONFIG_IEP_MMU)
|
||||
// mmu
|
||||
#define IEP_REGB_MMU_DTE_ADDR(base, x) WriteReg32(base, rIEP_MMU_DTE_ADDR, x)
|
||||
#define IEP_REGB_MMU_STATUS(base) ReadReg32(base, rIEP_MMU_STATUS)
|
||||
|
||||
#define IEP_REGB_MMU_CMD(base, x) MaskRegBits32(base, rIEP_MMU_CMD, IEP_REGB_MMU_CMD_Y, IEP_REGB_MMU_CMD_Z(x))
|
||||
|
||||
#define IEP_REGB_MMU_PAGE_FAULT_ADDR(base) ReadReg32(base, rIEP_MMU_PAGE_FAULT_ADDR)
|
||||
|
||||
#define IEP_REGB_MMU_ZAP_ONE_LINE(base, x) MaskRegBits32(base, rIEP_MMU_ZAP_ONE_LINE, \
|
||||
IEP_REGB_MMU_ZAP_ONE_LINE_Y, \
|
||||
IEP_REGB_MMU_ZAP_ONE_LINE_Z(x))
|
||||
|
||||
#define IEP_REGB_MMU_INT_RAWSTAT(base) ReadReg32(base, rIEP_MMU_INT_RAWSTAT)
|
||||
|
||||
#define IEP_REGB_MMU_INT_CLEAR_PAGE_FAULT_CLEAR(base, x) MaskRegBits32(base, rIEP_MMU_INT_CLEAR, \
|
||||
IEP_REGB_MMU_INT_CLEAR_PAGE_FAULT_CLEAR_Y, \
|
||||
IEP_REGB_MMU_INT_CLEAR_PAGE_FAULT_CLEAR_Z(x))
|
||||
#define IEP_REGB_MMU_INT_CLEAR_READ_BUS_ERROR_CLEAR(base, x) MaskRegBits32(base, rIEP_MMU_INT_CLEAR, \
|
||||
IEP_REGB_MMU_INT_CLEAR_READ_BUS_ERROR_CLEAR_Y, \
|
||||
IEP_REGB_MMU_INT_CLEAR_READ_BUS_ERROR_CLEAR_Z(x))
|
||||
|
||||
#define IEP_REGB_MMU_INT_MASK_PAGE_FAULT_INT_EN(base, x) MaskRegBits32(base, rIEP_MMU_INT_MASK, \
|
||||
IEP_REGB_MMU_INT_MASK_PAGE_FAULT_INT_EN_Y, \
|
||||
IEP_REGB_MMU_INT_MASK_PAGE_FAULT_INT_EN_Z(x))
|
||||
#define IEP_REGB_MMU_INT_MASK_READ_BUS_ERROR_INT_EN(base, x) MaskRegBits32(base, rIEP_MMU_INT_MASK, \
|
||||
IEP_REGB_MMU_INT_MASK_READ_BUS_ERROR_INT_EN_Y, \
|
||||
IEP_REGB_MMU_INT_MASK_PAGE_FAULT_INT_EN_Z(x))
|
||||
|
||||
#define IEP_REGB_MMU_INT_STATUS(base) ReadReg32(base, rIEP_MMU_INT_STATUS)
|
||||
|
||||
#define IEP_REGB_MMU_AUTO_GATING(base, x) MaskRegBits32(base, rIEP_MMU_AUTO_GATING, \
|
||||
IEP_REGB_MMU_AUTO_GATING_Y, \
|
||||
IEP_REGB_MMU_AUTO_GATING_Z(x))
|
||||
#endif
|
||||
|
||||
///function define
|
||||
void iep_config_lcdc_path(IEP_MSG *iep_msg);
|
||||
|
||||
/// system control, directly operating the device registers.
|
||||
/// parameter @base need to be set to device base address.
|
||||
void iep_soft_rst(void *base);
|
||||
void iep_config_done(void *base);
|
||||
void iep_config_frm_start(void *base);
|
||||
int iep_probe_int(void *base);
|
||||
void iep_config_frame_end_int_clr(void *base);
|
||||
void iep_config_frame_end_int_en(void *base);
|
||||
struct iep_status iep_get_status(void *base);
|
||||
#if defined(CONFIG_IEP_MMU)
|
||||
struct iep_mmu_int_status iep_probe_mmu_int_status(void *base);
|
||||
void iep_config_mmu_page_fault_int_en(void *base, bool en);
|
||||
void iep_config_mmu_page_fault_int_clr(void *base);
|
||||
void iep_config_mmu_read_bus_error_int_clr(void *base);
|
||||
uint32_t iep_probe_mmu_page_fault_addr(void *base);
|
||||
void iep_config_mmu_cmd(void *base, enum iep_mmu_cmd cmd);
|
||||
void iep_config_mmu_dte_addr(void *base, uint32_t addr);
|
||||
#endif
|
||||
int iep_get_deinterlace_mode(void *base);
|
||||
void iep_set_deinterlace_mode(int mode, void *base);
|
||||
void iep_switch_input_address(void *base);
|
||||
|
||||
/// generating a series of iep registers copy to the session private buffer
|
||||
void iep_config(iep_session *session, IEP_MSG *iep_msg);
|
||||
|
||||
//#define IEP_PRINT_INFO
|
||||
#endif
|
||||
|
||||
|
||||
234
drivers/video/rockchip/iep/iep.h
Executable file
234
drivers/video/rockchip/iep/iep.h
Executable file
@@ -0,0 +1,234 @@
|
||||
#ifndef _IEP_H_
|
||||
#define _IEP_H_
|
||||
|
||||
#define IEP_IOC_MAGIC 'i'
|
||||
|
||||
#define IEP_SET_PARAMETER_REQ _IOW(IEP_IOC_MAGIC, 1, unsigned long)
|
||||
#define IEP_SET_PARAMETER_DEINTERLACE _IOW(IEP_IOC_MAGIC, 2, unsigned long)
|
||||
#define IEP_SET_PARAMETER_ENHANCE _IOW(IEP_IOC_MAGIC, 3, unsigned long)
|
||||
#define IEP_SET_PARAMETER_CONVERT _IOW(IEP_IOC_MAGIC, 4, unsigned long)
|
||||
#define IEP_SET_PARAMETER_SCALE _IOW(IEP_IOC_MAGIC, 5, unsigned long)
|
||||
#define IEP_GET_RESULT_SYNC _IOW(IEP_IOC_MAGIC, 6, unsigned long)
|
||||
#define IEP_GET_RESULT_ASYNC _IOW(IEP_IOC_MAGIC, 7, unsigned long)
|
||||
#define IEP_SET_PARAMETER _IOW(IEP_IOC_MAGIC, 8, unsigned long)
|
||||
#define IEP_RELEASE_CURRENT_TASK _IOW(IEP_IOC_MAGIC, 9, unsigned long)
|
||||
|
||||
/* Driver information */
|
||||
#define DRIVER_DESC "IEP Device Driver"
|
||||
#define DRIVER_NAME "iep"
|
||||
|
||||
/* Logging */
|
||||
#define IEP_DEBUG 0
|
||||
#if IEP_DEBUG
|
||||
#define IEP_DBG(format, args...) printk("%s: " format, DRIVER_NAME, ## args)
|
||||
#else
|
||||
#define IEP_DBG(format, args...)
|
||||
#endif
|
||||
|
||||
#define IEP_INFORMATION 1
|
||||
#if IEP_INFORMATION
|
||||
#define IEP_INFO(format, args...) printk(format, ## args)
|
||||
#else
|
||||
#define IEP_INFO(format, args...)
|
||||
#endif
|
||||
|
||||
#define IEP_ERR(format, args...) printk(KERN_ERR "%s: " format, DRIVER_NAME, ## args)
|
||||
#define IEP_WARNING(format, args...) printk(KERN_WARNING "%s: " format, DRIVER_NAME, ## args)
|
||||
|
||||
enum
|
||||
{
|
||||
yuv2rgb_BT_601_l = 0x0, /* BT.601_1 */
|
||||
yuv2rgb_BT_601_f = 0x1, /* BT.601_f */
|
||||
yuv2rgb_BT_709_l = 0x2, /* BT.709_1 */
|
||||
yuv2rgb_BT_709_f = 0x3, /* BT.709_f */
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
rgb2yuv_BT_601_l = 0x0, /* BT.601_1 */
|
||||
rgb2yuv_BT_601_f = 0x1, /* BT.601_f */
|
||||
rgb2yuv_BT_709_l = 0x2, /* BT.709_1 */
|
||||
rgb2yuv_BT_709_f = 0x3, /* BT.709_f */
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
dein_mode_bypass_dis = 0x0,
|
||||
dein_mode_I4O2 = 0x1,
|
||||
dein_mode_I4O1B = 0x2,
|
||||
dein_mode_I4O1T = 0x3,
|
||||
dein_mode_I2O1B = 0x4,
|
||||
dein_mode_I2O1T = 0x5,
|
||||
dein_mode_bypass = 0x6,
|
||||
};
|
||||
|
||||
typedef enum IEP_FIELD_ORDER
|
||||
{
|
||||
FIELD_ORDER_TOP_FIRST,
|
||||
FIELD_ORDER_BOTTOM_FIRST
|
||||
} IEP_FIELD_ORDER_t;
|
||||
|
||||
typedef enum IEP_YUV_DEINTERLACE_MODE {
|
||||
IEP_DEINTERLACE_MODE_DISABLE,
|
||||
IEP_DEINTERLACE_MODE_I2O1,
|
||||
IEP_DEINTERLACE_MODE_I4O1,
|
||||
IEP_DEINTERLACE_MODE_I4O2,
|
||||
IEP_DEINTERLACE_MODE_BYPASS
|
||||
} IEP_YUV_DEINTERLACE_MODE_t;
|
||||
|
||||
enum
|
||||
{
|
||||
rgb_enhance_bypass = 0x0,
|
||||
rgb_enhance_denoise = 0x1,
|
||||
rgb_enhance_detail = 0x2,
|
||||
rgb_enhance_edge = 0x3,
|
||||
};//for rgb_enhance_mode
|
||||
|
||||
enum
|
||||
{
|
||||
rgb_contrast_CC_P_DDE = 0x0, //cg prior to dde
|
||||
rgb_contrast_DDE_P_CC = 0x1, //dde prior to cg
|
||||
}; //for rgb_contrast_enhance_mode
|
||||
|
||||
enum
|
||||
{
|
||||
black_screen = 0x0,
|
||||
blue_screen = 0x1,
|
||||
color_bar = 0x2,
|
||||
normal_mode = 0x3,
|
||||
}; //for video mode
|
||||
|
||||
/*
|
||||
// Alpha Red Green Blue
|
||||
{ 4, 32, {{32,24, 24,16, 16, 8, 8, 0 }}, GGL_RGBA }, // IEP_FORMAT_ARGB_8888
|
||||
{ 4, 32, {{32,24, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // IEP_FORMAT_ABGR_8888
|
||||
{ 4, 32, {{ 8, 0, 32,24, 24,16, 16, 8 }}, GGL_RGB }, // IEP_FORMAT_RGBA_8888
|
||||
{ 4, 32, {{ 8, 0, 16, 8, 24,16, 32,24 }}, GGL_BGRA }, // IEP_FORMAT_BGRA_8888
|
||||
{ 2, 16, {{ 0, 0, 16,11, 11, 5, 5, 0 }}, GGL_RGB }, // IEP_FORMAT_RGB_565
|
||||
{ 2, 16, {{ 0, 0, 5, 0, 11, 5, 16,11 }}, GGL_RGB }, // IEP_FORMAT_RGB_565
|
||||
*/
|
||||
enum
|
||||
{
|
||||
IEP_FORMAT_ARGB_8888 = 0x0,
|
||||
IEP_FORMAT_ABGR_8888 = 0x1,
|
||||
IEP_FORMAT_RGBA_8888 = 0x2,
|
||||
IEP_FORMAT_BGRA_8888 = 0x3,
|
||||
IEP_FORMAT_RGB_565 = 0x4,
|
||||
IEP_FORMAT_BGR_565 = 0x5,
|
||||
|
||||
IEP_FORMAT_YCbCr_422_SP = 0x10,
|
||||
IEP_FORMAT_YCbCr_422_P = 0x11,
|
||||
IEP_FORMAT_YCbCr_420_SP = 0x12,
|
||||
IEP_FORMAT_YCbCr_420_P = 0x13,
|
||||
IEP_FORMAT_YCrCb_422_SP = 0x14,
|
||||
IEP_FORMAT_YCrCb_422_P = 0x15,//same as IEP_FORMAT_YCbCr_422_P
|
||||
IEP_FORMAT_YCrCb_420_SP = 0x16,
|
||||
IEP_FORMAT_YCrCb_420_P = 0x17,//same as IEP_FORMAT_YCbCr_420_P
|
||||
|
||||
}; //for format
|
||||
|
||||
typedef struct iep_img
|
||||
{
|
||||
unsigned short act_w; // act_width
|
||||
unsigned short act_h; // act_height
|
||||
signed short x_off; // x offset for the vir,word unit
|
||||
signed short y_off; // y offset for the vir,word unit
|
||||
|
||||
unsigned short vir_w; //unit :pix
|
||||
unsigned short vir_h; //unit :pix
|
||||
unsigned int format;
|
||||
unsigned int *mem_addr;
|
||||
unsigned int *uv_addr;
|
||||
unsigned int *v_addr;
|
||||
|
||||
unsigned char rb_swap;//not be used
|
||||
unsigned char uv_swap;//not be used
|
||||
|
||||
unsigned char alpha_swap;//not be used
|
||||
}
|
||||
iep_img;
|
||||
|
||||
|
||||
typedef struct IEP_MSG
|
||||
{
|
||||
iep_img src; // src active window
|
||||
iep_img dst; // src virtual window
|
||||
|
||||
iep_img src1;
|
||||
iep_img dst1;
|
||||
|
||||
iep_img src_itemp;
|
||||
iep_img src_ftemp;
|
||||
|
||||
iep_img dst_itemp;
|
||||
iep_img dst_ftemp;
|
||||
|
||||
unsigned char dither_up_en;
|
||||
unsigned char dither_down_en;//not to be used
|
||||
|
||||
unsigned char yuv2rgb_mode;
|
||||
unsigned char rgb2yuv_mode;
|
||||
|
||||
unsigned char global_alpha_value;
|
||||
|
||||
unsigned char rgb2yuv_clip_en;
|
||||
unsigned char yuv2rgb_clip_en;
|
||||
|
||||
unsigned char lcdc_path_en;
|
||||
int off_x;
|
||||
int off_y;
|
||||
int width;
|
||||
int height;
|
||||
int layer;
|
||||
|
||||
unsigned char yuv_3D_denoise_en;
|
||||
|
||||
/// yuv color enhance
|
||||
unsigned char yuv_enhance_en;
|
||||
int sat_con_int;
|
||||
int contrast_int;
|
||||
int cos_hue_int;
|
||||
int sin_hue_int;
|
||||
signed char yuv_enh_brightness;//-32<brightness<31
|
||||
unsigned char video_mode;//0-3
|
||||
unsigned char color_bar_y;//0-127
|
||||
unsigned char color_bar_u;//0-127
|
||||
unsigned char color_bar_v;//0-127
|
||||
|
||||
|
||||
unsigned char rgb_enhance_en;//i don't konw what is used
|
||||
|
||||
unsigned char rgb_color_enhance_en;//sw_rgb_color_enh_en
|
||||
unsigned int rgb_enh_coe;
|
||||
|
||||
unsigned char rgb_enhance_mode;//sw_rgb_enh_sel,dde sel
|
||||
|
||||
unsigned char rgb_cg_en;//sw_rgb_con_gam_en
|
||||
unsigned int cg_tab[192];
|
||||
|
||||
unsigned char rgb_contrast_enhance_mode;//sw_con_gam_order;0 cg prior to dde,1 dde prior to cg
|
||||
|
||||
int enh_threshold;
|
||||
int enh_alpha;
|
||||
int enh_radius;
|
||||
|
||||
unsigned char scale_up_mode;
|
||||
|
||||
unsigned char field_order;
|
||||
unsigned char dein_mode;
|
||||
//DIL HF
|
||||
unsigned char dein_high_fre_en;
|
||||
unsigned char dein_high_fre_fct;
|
||||
//DIL EI
|
||||
unsigned char dein_ei_mode;
|
||||
unsigned char dein_ei_smooth;
|
||||
unsigned char dein_ei_sel;
|
||||
unsigned char dein_ei_radius;//when dein_ei_sel=0 will be used
|
||||
|
||||
bool vir_addr_enable;
|
||||
|
||||
void *base;
|
||||
}
|
||||
IEP_MSG;
|
||||
|
||||
#endif
|
||||
143
drivers/video/rockchip/iep/iep_api.c
Executable file
143
drivers/video/rockchip/iep/iep_api.c
Executable file
@@ -0,0 +1,143 @@
|
||||
#include "iep_api.h"
|
||||
|
||||
|
||||
|
||||
void
|
||||
iep_set_act_info(iep_img *img, unsigned int w, unsigned int h, unsigned int x_off, unsigned int y_off)
|
||||
{
|
||||
|
||||
img->act_w = w;
|
||||
img->act_h = h;
|
||||
img->x_off = x_off;
|
||||
img->y_off = y_off;
|
||||
}
|
||||
|
||||
void
|
||||
iep_set_vir_info(iep_img *img, unsigned int w, unsigned int h, unsigned int *yrgb, unsigned int *uv, unsigned int *v, unsigned int format )
|
||||
{
|
||||
|
||||
img->vir_w = w;
|
||||
img->vir_h = h;
|
||||
img->mem_addr = yrgb;
|
||||
img->uv_addr = uv;
|
||||
img->v_addr = v;
|
||||
img->format = format;
|
||||
}
|
||||
|
||||
void
|
||||
iep_set_scl_up_mode(IEP_MSG *msg, unsigned char mode)
|
||||
{
|
||||
msg->scale_up_mode = mode;
|
||||
}
|
||||
|
||||
void
|
||||
iep_set_color_enhance(IEP_MSG *msg, unsigned char color_enh_en,float color_enh_coe)
|
||||
{
|
||||
msg->rgb_color_enhance_en = color_enh_en;
|
||||
msg->rgb_enh_coe = color_enh_coe;
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
iep_rgb_cg(IEP_MSG *msg,unsigned char cg_en,double cg_rr,double cg_rg,double cg_rb)
|
||||
{
|
||||
msg->rgb_cg_en=cg_en;
|
||||
msg->cg_rr=cg_rr;
|
||||
msg->cg_rg=cg_rg;
|
||||
msg->cg_rb=cg_rb;
|
||||
}
|
||||
|
||||
void
|
||||
iep_set_deinterlace(IEP_MSG *msg, unsigned char mode, unsigned char dein_high_fre_en, unsigned char dein_edge_interp_en)
|
||||
{
|
||||
msg->dein_mode = mode;
|
||||
msg->dein_high_fre_en = dein_high_fre_en;
|
||||
msg->dein_ei_mode = dein_edge_interp_en;
|
||||
}
|
||||
void
|
||||
iep_set_dil_ei_smooth(IEP_MSG *msg,unsigned int en)
|
||||
{
|
||||
msg->dein_ei_smooth = en;
|
||||
}
|
||||
void
|
||||
iep_set_dil_ei(IEP_MSG *msg,unsigned char ei_sel,unsigned char ei_radius,unsigned char ei_smooth_en,unsigned char ei_mode)
|
||||
{
|
||||
msg->dein_ei_sel=ei_sel;
|
||||
msg->dein_ei_radius=ei_radius;
|
||||
msg->dein_ei_smooth=ei_smooth_en;
|
||||
msg->dein_ei_mode=ei_mode;
|
||||
}
|
||||
void
|
||||
iep_set_dil_hf(IEP_MSG *msg,unsigned char dil_hf_en,unsigned char dil_hf_fct)
|
||||
{
|
||||
msg->dein_high_fre_en=dil_hf_en;
|
||||
msg->dein_high_fre_fct=dil_hf_fct;
|
||||
}
|
||||
|
||||
void
|
||||
iep_set_rgb2yuv(IEP_MSG *msg, unsigned char rgb2yuv_mode, unsigned char rgb2yuv_clip_en)
|
||||
{
|
||||
msg->rgb2yuv_mode = rgb2yuv_mode;
|
||||
msg->rgb2yuv_clip_en = rgb2yuv_clip_en;
|
||||
}
|
||||
|
||||
void
|
||||
iep_set_yuv2rgb(IEP_MSG *msg, unsigned char yuv2rgb_mode, unsigned char yuv2rgb_clip_en)
|
||||
{
|
||||
msg->yuv2rgb_mode = yuv2rgb_mode;
|
||||
msg->yuv2rgb_clip_en = yuv2rgb_clip_en;
|
||||
}
|
||||
|
||||
void
|
||||
iep_set_dither_up(IEP_MSG *msg,unsigned int en)
|
||||
{
|
||||
msg->dither_up_en = en;
|
||||
}
|
||||
|
||||
void
|
||||
iep_set_lcdc_path(IEP_MSG *msg)
|
||||
{
|
||||
msg->lcdc_path_en = 1;
|
||||
}
|
||||
|
||||
void
|
||||
iep_set_3D_denoise(IEP_MSG *msg)
|
||||
{
|
||||
msg->yuv_3D_denoise_en = 1;
|
||||
}
|
||||
|
||||
void
|
||||
iep_set_yuv_normal_mode_enh(IEP_MSG *msg,float saturation,float contrast,signed char brightness,signed char angle)
|
||||
{
|
||||
msg->yuv_enhance_en = 1;
|
||||
msg->video_mode = normal_mode;
|
||||
msg->yuv_enh_saturation = saturation;
|
||||
msg->yuv_enh_contrast = contrast;
|
||||
msg->yuv_enh_brightness = brightness;
|
||||
msg->yuv_enh_hue_angle = angle;
|
||||
}
|
||||
|
||||
void
|
||||
iep_set_yuv_black_screen(IEP_MSG *msg)
|
||||
{
|
||||
msg->yuv_enhance_en = 1;
|
||||
msg->video_mode = black_screen;
|
||||
}
|
||||
|
||||
void
|
||||
iep_set_yuv_blue_screen(IEP_MSG *msg)
|
||||
{
|
||||
msg->yuv_enhance_en = 1;
|
||||
msg->video_mode = blue_screen;
|
||||
}
|
||||
|
||||
void
|
||||
iep_set_yuv_color_bar(IEP_MSG *msg,unsigned char color_bar_y,unsigned char color_bar_u,unsigned char color_bar_v)
|
||||
{
|
||||
msg->yuv_enhance_en = 1;
|
||||
msg->video_mode = color_bar;
|
||||
msg->color_bar_y = color_bar_y;
|
||||
msg->color_bar_u = color_bar_u;
|
||||
msg->color_bar_v = color_bar_v;
|
||||
}
|
||||
|
||||
56
drivers/video/rockchip/iep/iep_api.h
Executable file
56
drivers/video/rockchip/iep/iep_api.h
Executable file
@@ -0,0 +1,56 @@
|
||||
#ifndef __IEP_API_H__
|
||||
#define __IEP_API_H__
|
||||
|
||||
|
||||
#include "iep.h"
|
||||
//#include "../lcdc/hwapi_lcdc.h"
|
||||
|
||||
void
|
||||
iep_set_act_info(iep_img *img, unsigned int w, unsigned int h, unsigned int x_off, unsigned int y_off);
|
||||
|
||||
void
|
||||
iep_set_vir_info(iep_img *img, unsigned int w, unsigned int h, unsigned int *yrgb, unsigned int *uv, unsigned int *v, unsigned int format );
|
||||
|
||||
void
|
||||
iep_set_scl_up_mode(IEP_MSG *msg, unsigned char mode);
|
||||
|
||||
void
|
||||
iep_set_color_enhance(IEP_MSG *msg, unsigned char color_enh_en,float color_enh_coe);
|
||||
|
||||
void
|
||||
iep_rgb_cg(IEP_MSG *msg,unsigned char cg_en,double cg_rr,double cg_rg,double cg_rb);
|
||||
|
||||
void
|
||||
iep_set_deinterlace(IEP_MSG *msg, unsigned char mode, unsigned char dein_high_fre_en, unsigned char dein_edge_interp_en);
|
||||
|
||||
void
|
||||
iep_set_dil_ei_smooth(IEP_MSG *msg,unsigned int en);
|
||||
|
||||
void
|
||||
iep_set_rgb2yuv(IEP_MSG *msg, unsigned char rgb2yuv_mode, unsigned char rgb2yuv_clip_en);
|
||||
|
||||
void
|
||||
iep_set_yuv2rgb(IEP_MSG *msg, unsigned char yuv2rgb_mode, unsigned char yuv2rgb_clip_en);
|
||||
|
||||
void
|
||||
iep_set_dither_up(IEP_MSG *msg,unsigned int en);
|
||||
|
||||
void
|
||||
iep_set_lcdc_path(IEP_MSG *msg);
|
||||
|
||||
void
|
||||
iep_set_3D_denoise(IEP_MSG *msg);
|
||||
|
||||
void
|
||||
iep_set_yuv_normal_mode_enh(IEP_MSG *msg,float saturation,float contrast,signed char brightness,signed char angle);
|
||||
|
||||
void
|
||||
iep_set_yuv_black_screen(IEP_MSG *msg);
|
||||
|
||||
void
|
||||
iep_set_yuv_blue_screen(IEP_MSG *msg);
|
||||
|
||||
void
|
||||
iep_set_yuv_color_bar(IEP_MSG *msg,unsigned char color_bar_y,unsigned char color_bar_u,unsigned char color_bar_v);
|
||||
|
||||
#endif
|
||||
1139
drivers/video/rockchip/iep/iep_drv.c
Executable file
1139
drivers/video/rockchip/iep/iep_drv.c
Executable file
File diff suppressed because it is too large
Load Diff
153
drivers/video/rockchip/iep/iep_drv.h
Executable file
153
drivers/video/rockchip/iep/iep_drv.h
Executable file
@@ -0,0 +1,153 @@
|
||||
#ifndef IEP_DRV_H_
|
||||
#define IEP_DRV_H_
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/miscdevice.h>
|
||||
#include <linux/mutex.h>
|
||||
#include "iep.h"
|
||||
|
||||
#define IEP_REG_LEN 0x100
|
||||
#define IEP_CMD_REG_LEN 0xE
|
||||
#define IEP_ADD_REG_LEN 0xE0
|
||||
#define IEP_RAW_REG_LEN 0xA
|
||||
#define IEP_SYS_REG_LEN 0x6
|
||||
#define IEP_CNF_REG_LEN 0x2
|
||||
|
||||
#define IEP_CNF_REG_BASE 0x0
|
||||
#define IEP_SYS_REG_BASE 0x2
|
||||
#define IEP_CMD_REG_BASE 0x8
|
||||
#define IEP_ADD_REG_BASE 0x20
|
||||
#define IEP_RAW_REG_BASE 0x16
|
||||
|
||||
#if defined(CONFIG_IEP_MMU)
|
||||
#define IEP_MMU_REG_BASE 0x200
|
||||
#define IEP_MMU_REG_LEN 0xA
|
||||
#endif
|
||||
|
||||
struct iep_parameter_req {
|
||||
iep_img src;
|
||||
iep_img dst;
|
||||
};
|
||||
|
||||
struct iep_parameter_deinterlace {
|
||||
iep_img src1;
|
||||
iep_img dst1;
|
||||
|
||||
iep_img src_itemp;
|
||||
iep_img src_ftemp;
|
||||
|
||||
iep_img dst_itemp;
|
||||
iep_img dst_ftemp;
|
||||
|
||||
u8 dein_mode;
|
||||
|
||||
// deinterlace high frequency
|
||||
u8 dein_high_fre_en;
|
||||
u8 dein_high_fre_fct;
|
||||
|
||||
// deinterlace edge interpolation
|
||||
u8 dein_ei_mode;
|
||||
u8 dein_ei_smooth;
|
||||
u8 dein_ei_sel;
|
||||
u8 dein_ei_radius;
|
||||
};
|
||||
|
||||
struct iep_parameter_enhance {
|
||||
u8 yuv_3D_denoise_en;
|
||||
|
||||
u8 yuv_enhance_en;
|
||||
float yuv_enh_saturation; //0-1.992
|
||||
float yuv_enh_contrast; //0-1.992
|
||||
s8 yuv_enh_brightness; //-32<brightness<31
|
||||
s8 yuv_enh_hue_angle; //0-30<33>㣬value is 0 - 30
|
||||
|
||||
u8 video_mode; //0-3
|
||||
u8 color_bar_y; //0-127
|
||||
u8 color_bar_u; //0-127
|
||||
u8 color_bar_v; //0-127
|
||||
|
||||
u8 rgb_enhance_en;
|
||||
|
||||
u8 rgb_cg_en; //sw_rgb_con_gam_en
|
||||
double cg_rr;
|
||||
double cg_rg;
|
||||
double cg_rb;
|
||||
u8 rgb_color_enhance_en; //sw_rgb_color_enh_en
|
||||
float rgb_enh_coe; //0-3.96875
|
||||
};
|
||||
|
||||
struct iep_parameter_scale {
|
||||
u8 scale_up_mode;
|
||||
};
|
||||
|
||||
struct iep_parameter_convert {
|
||||
u8 dither_up_en;
|
||||
u8 dither_down_en; //not to be used
|
||||
|
||||
u8 yuv2rgb_mode;
|
||||
u8 rgb2yuv_mode;
|
||||
|
||||
u8 global_alpha_value;
|
||||
|
||||
u8 rgb2yuv_clip_en;
|
||||
u8 yuv2rgb_clip_en;
|
||||
};
|
||||
|
||||
typedef struct iep_session {
|
||||
/* a linked list of data so we can access them for debugging */
|
||||
struct list_head list_session;
|
||||
/* a linked list of register data waiting for process */
|
||||
struct list_head waiting;
|
||||
/* a linked list of register data in ready */
|
||||
struct list_head ready;
|
||||
/* a linked list of register data in processing */
|
||||
struct list_head running;
|
||||
/* all coommand this thread done */
|
||||
atomic_t done;
|
||||
wait_queue_head_t wait;
|
||||
pid_t pid;
|
||||
atomic_t task_running;
|
||||
atomic_t num_done;
|
||||
|
||||
#if defined(CONFIG_IEP_MMU)
|
||||
uint32_t* dte_table;
|
||||
struct list_head pte_list;
|
||||
struct task_struct *tsk;
|
||||
#endif
|
||||
} iep_session;
|
||||
|
||||
typedef struct iep_service_info {
|
||||
struct mutex lock;
|
||||
struct timer_list timer; /* timer for power off */
|
||||
struct list_head waiting; /* link to link_reg in struct iep_reg */
|
||||
atomic_t waitcnt;
|
||||
struct list_head ready; /* link to link_reg in struct iep_reg */
|
||||
struct list_head running; /* link to link_reg in struct iep_reg */
|
||||
struct list_head done; /* link to link_reg in struct iep_reg */
|
||||
struct list_head session; /* link to list_session in struct vpu_session */
|
||||
atomic_t total_running;
|
||||
|
||||
struct iep_reg *reg;
|
||||
bool enable;
|
||||
|
||||
struct mutex mutex; // mutex
|
||||
} iep_service_info;
|
||||
|
||||
struct iep_reg {
|
||||
iep_session *session;
|
||||
struct list_head session_link; /* link to rga service session */
|
||||
struct list_head status_link; /* link to register set list */
|
||||
uint32_t reg[0x300];
|
||||
bool dpi_en;
|
||||
int off_x;
|
||||
int off_y;
|
||||
int act_width;
|
||||
int act_height;
|
||||
int vir_width;
|
||||
int vir_height;
|
||||
int layer;
|
||||
unsigned int format;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
233
drivers/video/rockchip/iep/iep_mmu.c
Executable file
233
drivers/video/rockchip/iep/iep_mmu.c
Executable file
@@ -0,0 +1,233 @@
|
||||
/*
|
||||
* Copyright (C) 2013 ROCKCHIP, Inc.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/slab.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/sched.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include "iep_mmu.h"
|
||||
|
||||
#define RK_MMU_DTE_SHIFT 22
|
||||
#define RK_MMU_DTE_MASK (~0xFFFL)
|
||||
#define RK_MMU_PTE_SHIFT 12
|
||||
#define RK_MMU_PTE_MASK (~0xFFFL)
|
||||
#define RK_MMU_DTE_ENTRY_CNT ((1) << (32-RK_MMU_DTE_SHIFT))
|
||||
#define RK_MMU_PTE_ENTRY_CNT ((1) << (RK_MMU_DTE_SHIFT - RK_MMU_PTE_SHIFT))
|
||||
|
||||
#define RK_MMU_PAGE_PRESENT (1<<0)
|
||||
#define RK_MMU_READ_PERMISSION (1<<1)
|
||||
#define RK_MMU_WRITE_PERMISSION (1<<2)
|
||||
#define RK_MMU_OVERRIDE_CACHE_ATTRIBUTES (0<<3)
|
||||
#define RK_MMU_WRITE_CACHE_ABLE (0<<4)
|
||||
#define RK_MMU_WRITE_ALLOCABLE (0<<5)
|
||||
#define RK_MMU_WRITE_BUFFERABLE (0<<6)
|
||||
#define RK_MMU_READ_CACHE_ABLE (0<<7)
|
||||
#define RK_MMU_READ_ALLOCABLE (0<<8)
|
||||
|
||||
#define RK_MMU_PTE_CTRL (RK_MMU_PAGE_PRESENT | RK_MMU_READ_PERMISSION | \
|
||||
RK_MMU_WRITE_PERMISSION | RK_MMU_OVERRIDE_CACHE_ATTRIBUTES | \
|
||||
RK_MMU_WRITE_CACHE_ABLE | RK_MMU_WRITE_ALLOCABLE | \
|
||||
RK_MMU_WRITE_BUFFERABLE | RK_MMU_READ_CACHE_ABLE | \
|
||||
RK_MMU_READ_ALLOCABLE)
|
||||
|
||||
#define RK_MMU_DTE_CTRL RK_MMU_PAGE_PRESENT
|
||||
|
||||
//#define RK_MMU_DEBUG
|
||||
|
||||
static int map_user_space_addr(struct task_struct *tsk,
|
||||
uint32_t *pte_table,
|
||||
uint32_t page_index,
|
||||
uint32_t page_count)
|
||||
{
|
||||
int result;
|
||||
int i;
|
||||
int status = 0;
|
||||
uint32_t phy_addr = 0;
|
||||
struct page **pages;
|
||||
|
||||
pages = kzalloc((page_count + 1) * sizeof(struct page*), GFP_KERNEL);
|
||||
|
||||
down_read(&tsk->mm->mmap_sem);
|
||||
result = get_user_pages(tsk,
|
||||
tsk->mm,
|
||||
page_index << PAGE_SHIFT,
|
||||
page_count,
|
||||
1, 0, pages, NULL
|
||||
);
|
||||
up_read(&tsk->mm->mmap_sem);
|
||||
|
||||
if (result <= 0 || result < page_count) {
|
||||
struct vm_area_struct *vma;
|
||||
|
||||
for(i=0; i<page_count; i++) {
|
||||
vma = find_vma(tsk->mm, (page_index + i) << PAGE_SHIFT);
|
||||
|
||||
if (vma) {
|
||||
pte_t *pte;
|
||||
spinlock_t *ptl;
|
||||
unsigned long pfn;
|
||||
pgd_t *pgd;
|
||||
pud_t *pud;
|
||||
pmd_t *pmd;
|
||||
|
||||
pgd = pgd_offset(tsk->mm, (page_index + i) << PAGE_SHIFT);
|
||||
|
||||
if (pgd_none(*pgd) || pgd_bad(*pgd)) {
|
||||
IEP_ERR("iep, invalid pgd\n");
|
||||
status = -EIO;
|
||||
break;
|
||||
}
|
||||
|
||||
pud = pud_offset(pgd, (page_index + i) << PAGE_SHIFT);
|
||||
if (pud_none(*pud) || pud_bad(*pud)) {
|
||||
IEP_ERR("iep, invalid pud\n");
|
||||
status = -EIO;
|
||||
break;
|
||||
}
|
||||
|
||||
pmd = pmd_offset(pud, (page_index + i) << PAGE_SHIFT);
|
||||
if (pmd_none(*pmd) || pmd_bad(*pmd)) {
|
||||
status = -EIO;
|
||||
continue;
|
||||
}
|
||||
|
||||
pte = pte_offset_map_lock(tsk->mm, pmd, (page_index + i) << PAGE_SHIFT, &ptl);
|
||||
if (pte_none(*pte)) {
|
||||
pte_unmap_unlock(pte, ptl);
|
||||
status = -EIO;
|
||||
continue;
|
||||
}
|
||||
|
||||
pfn = pte_pfn(*pte);
|
||||
phy_addr = ((pfn << PAGE_SHIFT) | (((unsigned long)((page_index + i) << PAGE_SHIFT)) & ~PAGE_MASK));
|
||||
pte_unmap_unlock(pte, ptl);
|
||||
|
||||
pte_table[i] = (phy_addr & RK_MMU_PTE_MASK) | RK_MMU_PTE_CTRL;
|
||||
} else {
|
||||
status = -EIO;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
} else {
|
||||
/* fill the page table. */
|
||||
for(i=0; i<page_count; i++) {
|
||||
/* get the physical address from page struct. */
|
||||
pte_table[i] = (page_to_phys(pages[i]) & RK_MMU_PTE_MASK) | RK_MMU_PTE_CTRL;
|
||||
}
|
||||
}
|
||||
|
||||
kfree(pages);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
int rk_mmu_generate_pte_from_va(iep_session *session, uint32_t va)
|
||||
{
|
||||
int i;
|
||||
int dte_index = va >> RK_MMU_DTE_SHIFT;
|
||||
struct rk_mmu_pte *pte_node = NULL, *n;
|
||||
|
||||
|
||||
if (session->dte_table[dte_index] != 0) {
|
||||
list_for_each_entry_safe(pte_node, n, &session->pte_list, session_link) {
|
||||
if (pte_node->index == dte_index) {
|
||||
// a incomplete pte.
|
||||
#ifdef RK_MMU_DEBUG
|
||||
uint32_t phy_addr;
|
||||
uint32_t dte_addr;
|
||||
uint32_t *pte_table;
|
||||
uint32_t pte_addr;
|
||||
|
||||
int pte_index = (va >> PAGE_SHIFT) & 0x3FF;
|
||||
int page_index = va & 0xFFF;
|
||||
|
||||
dte_addr = session->dte_table[dte_index];
|
||||
IEP_DBG("dte_addr = %08x\n", dte_addr);
|
||||
|
||||
pte_table = phys_to_virt(dte_addr & RK_MMU_DTE_MASK);
|
||||
|
||||
pte_addr = pte_table[pte_index];
|
||||
|
||||
IEP_DBG("pte_addr = %08x\n", pte_addr);
|
||||
|
||||
phy_addr = (pte_addr & RK_MMU_PTE_MASK) | page_index;
|
||||
|
||||
IEP_DBG("phy %08x\n", phy_addr);
|
||||
#endif
|
||||
IEP_DBG("Incomplete pte\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (pte_node == NULL || pte_node->index != dte_index) {
|
||||
// pte node is absence
|
||||
pte_node = (struct rk_mmu_pte*)kzalloc(sizeof(struct rk_mmu_pte), GFP_KERNEL);
|
||||
pte_node->pte = (uint32_t*)kzalloc(sizeof(uint32_t) * RK_MMU_PTE_ENTRY_CNT, GFP_KERNEL);
|
||||
pte_node->index = dte_index;
|
||||
}
|
||||
|
||||
IEP_DBG("va = %08x\n", va);
|
||||
|
||||
if (va < PAGE_OFFSET) {
|
||||
map_user_space_addr(session->tsk, pte_node->pte, (va >> PAGE_SHIFT) & (~0x3FFL), RK_MMU_PTE_ENTRY_CNT);
|
||||
} else {
|
||||
for (i=0; i<RK_MMU_PTE_ENTRY_CNT; i++) {
|
||||
pte_node->pte[i] = (uint32_t)(virt_to_phys((uint32_t*)((va + i) << PAGE_SHIFT)) & RK_MMU_PTE_MASK) | RK_MMU_PTE_CTRL;
|
||||
}
|
||||
}
|
||||
|
||||
IEP_DBG("pa = %08x\n", (uint32_t)((pte_node->pte[(va>>PAGE_SHIFT) & 0x3FFL] & RK_MMU_PTE_MASK) | (va & 0xFFFL)));
|
||||
|
||||
INIT_LIST_HEAD(&pte_node->session_link);
|
||||
list_add_tail(&pte_node->session_link, &session->pte_list);
|
||||
|
||||
dmac_flush_range(&pte_node->pte[0], &pte_node->pte[RK_MMU_PTE_ENTRY_CNT-1]);
|
||||
outer_flush_range(virt_to_phys(&pte_node->pte[0]),virt_to_phys(&pte_node->pte[RK_MMU_PTE_ENTRY_CNT-1]));
|
||||
|
||||
session->dte_table[pte_node->index] = (uint32_t)(virt_to_phys((uint32_t*)pte_node->pte) & RK_MMU_DTE_MASK) | RK_MMU_DTE_CTRL;
|
||||
|
||||
dmac_flush_range(&session->dte_table[pte_node->index], &session->dte_table[pte_node->index+1]);
|
||||
outer_flush_range(virt_to_phys(&session->dte_table[pte_node->index]),virt_to_phys(&session->dte_table[pte_node->index+1]));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void rk_mmu_reclaim_pte_list(iep_session *session)
|
||||
{
|
||||
struct rk_mmu_pte *pte_node, *n;
|
||||
|
||||
list_for_each_entry_safe(pte_node, n, &session->pte_list, session_link) {
|
||||
list_del_init(&pte_node->session_link);
|
||||
kfree(pte_node->pte);
|
||||
kfree(pte_node);
|
||||
}
|
||||
}
|
||||
|
||||
/// don't call this function in interupt service.
|
||||
int rk_mmu_init_dte_table(iep_session *session)
|
||||
{
|
||||
session->tsk = current;
|
||||
session->dte_table = (uint32_t*)kzalloc(sizeof(uint32_t) * RK_MMU_DTE_ENTRY_CNT, GFP_KERNEL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void rk_mmu_deinit_dte_table(iep_session *session)
|
||||
{
|
||||
rk_mmu_reclaim_pte_list(session);
|
||||
kfree(session->dte_table);
|
||||
}
|
||||
|
||||
18
drivers/video/rockchip/iep/iep_mmu.h
Executable file
18
drivers/video/rockchip/iep/iep_mmu.h
Executable file
@@ -0,0 +1,18 @@
|
||||
#ifndef _IEP_MMU_H_
|
||||
#define _IEP_MMU_H_
|
||||
|
||||
#include <linux/types.h>
|
||||
#include "iep_drv.h"
|
||||
|
||||
struct rk_mmu_pte {
|
||||
int index; // dte entry index [0, 1023]
|
||||
uint32_t *pte; // point to pte table
|
||||
struct list_head session_link; // link to session
|
||||
};
|
||||
|
||||
int rk_mmu_generate_pte_from_va(iep_session *session, uint32_t va);
|
||||
void rk_mmu_reclaim_pte_list(iep_session *session);
|
||||
int rk_mmu_init_dte_table(iep_session *session);
|
||||
void rk_mmu_deinit_dte_table(iep_session *session);
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user