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media: i2c: gc2093 fastboot support hdr

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Signed-off-by: Sisyphean Zhou <sisyphean.zhou@rock-chips.com>
Change-Id: I42233a5c897534ad89f3318186404836aafcc92c
This commit is contained in:
Sisyphean Zhou
2023-07-27 15:17:12 +08:00
committed by Tao Huang
parent da9d34f7cf
commit 97aa45b328
1 changed files with 363 additions and 26 deletions
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389
drivers/media/i2c/gc2093.c
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@@ -82,6 +82,8 @@
#define GC2093_LANES 2
#define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
static const char * const gc2093_supply_names[] = {
"dovdd", /* Digital I/O power */
"avdd", /* Analog power */
@@ -142,7 +144,6 @@ struct gc2093 {
struct mutex lock;
bool streaming;
bool power_on;
unsigned int cfg_num;
const struct gc2093_mode *cur_mode;
u32 module_index;
@@ -421,6 +422,138 @@ static const struct reg_sequence gc2093_1080p_hdr_settings[] = {
{0x024d, 0x01},
};
/*
* window size=1920*1080 mipi@2lane
* mclk=27M mipi_clk=792Mbps
* pixel_line_total=2640 line_frame_total=1500
* row_time=20us frame_rate=50fps
*/
static const struct reg_sequence gc2093_1080p_25fps_hdr_settings[] = {
/* System */
{0x03fe, 0x80},
{0x03fe, 0x80},
{0x03fe, 0x80},
{0x03fe, 0x00},
{0x03f2, 0x00},
{0x03f3, 0x00},
{0x03f4, 0x36},
{0x03f5, 0xc0},
{0x03f6, 0x0B},
{0x03f7, 0x01},
{0x03f8, 0x58},
{0x03f9, 0x40},
{0x03fc, 0x8e},
/* Cisctl & Analog */
{0x0087, 0x18},
{0x00ee, 0x30},
{0x00d0, 0xbf},
{0x01a0, 0x00},
{0x01a4, 0x40},
{0x01a5, 0x40},
{0x01a6, 0x40},
{0x01af, 0x09},
{0x0001, 0x00},
{0x0002, 0x02},
{0x0003, 0x04},
{0x0004, 0x02},
{0x0005, 0x02},
{0x0006, 0x94},
{0x0007, 0x00},
{0x0008, 0x11},
{0x0009, 0x00},
{0x000a, 0x02},
{0x000b, 0x00},
{0x000c, 0x04},
{0x000d, 0x04},
{0x000e, 0x40},
{0x000f, 0x07},
{0x0010, 0x8c},
{0x0013, 0x15},
{0x0019, 0x0c},
{0x0041, 0x05},
{0x0042, 0xdc},
{0x0053, 0x60},
{0x008d, 0x92},
{0x0090, 0x00},
{0x00c7, 0xe1},
{0x001b, 0x73},
{0x0028, 0x0d},
{0x0029, 0x24},
{0x002b, 0x04},
{0x002e, 0x23},
{0x0037, 0x03},
{0x0043, 0x04},
{0x0044, 0x20},
{0x004a, 0x01},
{0x004b, 0x20},
{0x0055, 0x30},
{0x006b, 0x44},
{0x0077, 0x00},
{0x0078, 0x20},
{0x007c, 0xa1},
{0x00d3, 0xd4},
{0x00e6, 0x50},
/* Gain */
{0x00b6, 0xc0},
{0x00b0, 0x60},
/* Isp */
{0x0102, 0x89},
{0x0104, 0x01},
{0x010e, 0x01},
{0x0158, 0x00},
{0x0183, 0x01},
{0x0187, 0x50},
/* Dark sun*/
{0x0123, 0x08},
{0x0123, 0x00},
{0x0120, 0x01},
{0x0121, 0x00},
{0x0122, 0x10},
{0x0124, 0x03},
{0x0125, 0xff},
{0x0126, 0x3c},
{0x001a, 0x8c},
{0x00c6, 0xe0},
/* Blk */
{0x0026, 0x30},
{0x0142, 0x00},
{0x0149, 0x1e},
{0x014a, 0x0f},
{0x014b, 0x00},
{0x0155, 0x00},
{0x0414, 0x78},
{0x0415, 0x78},
{0x0416, 0x78},
{0x0417, 0x78},
{0x0454, 0x78},
{0x0455, 0x78},
{0x0456, 0x78},
{0x0457, 0x78},
{0x04e0, 0x18},
/* Window */
{0x0192, 0x02},
{0x0194, 0x03},
{0x0195, 0x04},
{0x0196, 0x38},
{0x0197, 0x07},
{0x0198, 0x80},
/* MIPI */
{0x019a, 0x06},
{0x007b, 0x2a},
{0x0023, 0x2d},
{0x0201, 0x27},
{0x0202, 0x56},
{0x0203, 0xb6},
{0x0212, 0x80},
{0x0213, 0x07},
{0x0215, 0x12},
{0x003e, 0x91},
/* HDR En */
{0x0027, 0x71},
{0x0215, 0x92},
{0x024d, 0x01},
};
static const struct gc2093_mode supported_modes[] = {
{
.width = 1920,
@@ -457,6 +590,25 @@ static const struct gc2093_mode supported_modes[] = {
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
},
{
.width = 1920,
.height = 1080,
.max_fps = {
.numerator = 10000,
.denominator = 250000,
},
.exp_def = 0x460,
.hts_def = 0xa50,
.vts_def = 0x5dc,
.link_freq_index = LINK_FREQ_396M_INDEX,
.reg_list = gc2093_1080p_25fps_hdr_settings,
.reg_num = ARRAY_SIZE(gc2093_1080p_25fps_hdr_settings),
.hdr_mode = HDR_X2,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
},
};
/* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
@@ -585,6 +737,7 @@ static int gc2093_set_ctrl(struct v4l2_ctrl *ctrl)
switch (ctrl->id) {
case V4L2_CID_EXPOSURE:
dev_dbg(gc2093->dev, "set exposure value 0x%x\n", ctrl->val);
if (gc2093->cur_mode->hdr_mode != NO_HDR)
goto ctrl_end;
dev_dbg(gc2093->dev, "set exposure value 0x%x\n", ctrl->val);
@@ -594,28 +747,36 @@ static int gc2093_set_ctrl(struct v4l2_ctrl *ctrl)
ctrl->val & 0xff);
break;
case V4L2_CID_ANALOGUE_GAIN:
dev_dbg(gc2093->dev, "set gain value 0x%x, mode: %d\n",
ctrl->val, gc2093->cur_mode->hdr_mode);
if (gc2093->cur_mode->hdr_mode != NO_HDR)
goto ctrl_end;
dev_dbg(gc2093->dev, "set gain value 0x%x\n", ctrl->val);
gc2093_set_gain(gc2093, ctrl->val);
break;
case V4L2_CID_VBLANK:
dev_dbg(gc2093->dev, "set blank value 0x%x\n", ctrl->val);
vts = gc2093->cur_mode->height + ctrl->val;
gc2093->cur_vts = vts;
ret = gc2093_write_reg(gc2093, GC2093_REG_VTS_H,
(vts >> 8) & 0x3f);
ret |= gc2093_write_reg(gc2093, GC2093_REG_VTS_L,
vts & 0xff);
gc2093_modify_fps_info(gc2093);
if (!ret)
gc2093->cur_vts = ctrl->val + gc2093->cur_mode->height;
if (gc2093->cur_vts != gc2093->cur_mode->vts_def)
gc2093_modify_fps_info(gc2093);
dev_dbg(gc2093->dev, " set blank value 0x%x\n", ctrl->val);
break;
case V4L2_CID_HFLIP:
regmap_update_bits(gc2093->regmap, GC2093_MIRROR_FLIP_REG,
MIRROR_MASK, ctrl->val ? MIRROR_MASK : 0);
dev_dbg(gc2093->dev, "set hflip 0x%x\n", ctrl->val);
regmap_update_bits(gc2093->regmap, GC2093_MIRROR_FLIP_REG,
MIRROR_MASK, ctrl->val ? MIRROR_MASK : 0);
break;
case V4L2_CID_VFLIP:
regmap_update_bits(gc2093->regmap, GC2093_MIRROR_FLIP_REG,
FLIP_MASK, ctrl->val ? FLIP_MASK : 0);
dev_dbg(gc2093->dev, "set vflip 0x%x\n", ctrl->val);
regmap_update_bits(gc2093->regmap, GC2093_MIRROR_FLIP_REG,
FLIP_MASK, ctrl->val ? FLIP_MASK : 0);
break;
default:
dev_warn(gc2093->dev, "%s Unhandled id:0x%x, val:0x%x\n",
@@ -672,7 +833,7 @@ static int gc2093_initialize_controls(struct gc2093 *gc2093)
h_blank, h_blank, 1, h_blank);
if (gc2093->hblank)
gc2093->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
gc2093->cur_fps = mode->max_fps;
vblank_def = mode->vts_def - mode->height;
gc2093->cur_vts = mode->vts_def;
gc2093->vblank = v4l2_ctrl_new_std(handler, &gc2093_ctrl_ops,
@@ -819,11 +980,24 @@ static void gc2093_get_module_inf(struct gc2093 *gc2093,
strlcpy(inf->base.module, gc2093->module_name, sizeof(inf->base.module));
}
static int gc2093_get_channel_info(struct gc2093 *gc2093,
struct rkmodule_channel_info *ch_info)
{
if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
return -EINVAL;
ch_info->vc = gc2093->cur_mode->vc[ch_info->index];
ch_info->width = gc2093->cur_mode->width;
ch_info->height = gc2093->cur_mode->height;
ch_info->bus_fmt = GC2093_MEDIA_BUS_FMT;
return 0;
}
static long gc2093_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
{
struct gc2093 *gc2093 = to_gc2093(sd);
struct preisp_hdrae_exp_s *hdrae_exp = arg;
struct rkmodule_hdr_cfg *hdr_cfg;
struct rkmodule_channel_info *ch_info;
long ret = 0;
u32 i, h, w;
u32 stream = 0;
@@ -913,15 +1087,18 @@ static long gc2093_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
w = gc2093->cur_mode->width;
h = gc2093->cur_mode->height;
for (i = 0; i < gc2093->cfg_num; i++) {
for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
if (w == supported_modes[i].width &&
h == supported_modes[i].height &&
supported_modes[i].hdr_mode == hdr_cfg->hdr_mode) {
gc2093->cur_mode = &supported_modes[i];
break;
}
dev_err(gc2093->dev, "i:%d,w:%d, h:%d, hdr:%d\n",
i, supported_modes[i].width, supported_modes[i].height,
supported_modes[i].hdr_mode);
}
if (i == gc2093->cfg_num) {
if (i == ARRAY_SIZE(supported_modes)) {
dev_err(gc2093->dev, "not find hdr mode:%d %dx%d config\n",
hdr_cfg->hdr_mode, w, h);
ret = -EINVAL;
@@ -957,6 +1134,10 @@ static long gc2093_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
usleep_range(delay_us, delay_us + 2000);
}
break;
case RKMODULE_GET_CHANNEL_INFO:
ch_info = (struct rkmodule_channel_info *)arg;
ret = gc2093_get_channel_info(gc2093, ch_info);
break;
default:
ret = -ENOIOCTLCMD;
break;
@@ -989,8 +1170,16 @@ static int __gc2093_start_stream(struct gc2093 *gc2093)
}
}
}
dev_info(gc2093->dev,
"%dx%d@%d, mode %d, vts 0x%x\n",
gc2093->cur_mode->width,
gc2093->cur_mode->height,
gc2093->cur_fps.denominator / gc2093->cur_fps.numerator,
gc2093->cur_mode->hdr_mode,
gc2093->cur_vts);
dev_info(gc2093->dev, "is_tb:%d\n", gc2093->is_thunderboot);
return gc2093_write_reg(gc2093, GC2093_REG_CTRL_MODE,
GC2093_MODE_STREAMING);
GC2093_MODE_STREAMING);
}
static int __gc2093_stop_stream(struct gc2093 *gc2093)
@@ -1012,6 +1201,7 @@ static long gc2093_compat_ioctl32(struct v4l2_subdev *sd,
struct rkmodule_inf *inf;
struct rkmodule_hdr_cfg *hdr;
struct preisp_hdrae_exp_s *hdrae;
struct rkmodule_channel_info *ch_info;
long ret = 0;
u32 stream = 0;
@@ -1081,6 +1271,21 @@ static long gc2093_compat_ioctl32(struct v4l2_subdev *sd,
else
ret = -EFAULT;
break;
case RKMODULE_GET_CHANNEL_INFO:
ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
if (!ch_info) {
ret = -ENOMEM;
return ret;
}
ret = gc2093_ioctl(sd, cmd, ch_info);
if (!ret) {
ret = copy_to_user(up, ch_info, sizeof(*ch_info));
if (ret)
ret = -EFAULT;
}
kfree(ch_info);
break;
default:
ret = -ENOIOCTLCMD;
break;
@@ -1099,11 +1304,17 @@ static int gc2093_s_stream(struct v4l2_subdev *sd, int on)
fps = DIV_ROUND_CLOSEST(gc2093->cur_mode->max_fps.denominator,
gc2093->cur_mode->max_fps.numerator);
dev_info(gc2093->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
gc2093->cur_mode->width,
gc2093->cur_mode->height,
fps);
dev_info(gc2093->dev,
"%dx%d@%d, mode %d, vts 0x%x\n",
gc2093->cur_mode->width,
gc2093->cur_mode->height,
gc2093->cur_fps.denominator / gc2093->cur_fps.numerator,
gc2093->cur_mode->hdr_mode,
gc2093->cur_vts);
dev_info(gc2093->dev,
"stream:%d\n, on:%d",
gc2093->streaming, on);
mutex_lock(&gc2093->lock);
on = !!on;
if (on == gc2093->streaming)
@@ -1150,7 +1361,10 @@ static int gc2093_g_frame_interval(struct v4l2_subdev *sd,
struct gc2093 *gc2093 = to_gc2093(sd);
const struct gc2093_mode *mode = gc2093->cur_mode;
fi->interval = mode->max_fps;
if (gc2093->streaming)
fi->interval = gc2093->cur_fps;
else
fi->interval = mode->max_fps;
return 0;
}
@@ -1183,9 +1397,7 @@ static int gc2093_enum_frame_sizes(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_frame_size_enum *fse)
{
struct gc2093 *gc2093 = to_gc2093(sd);
if (fse->index >= gc2093->cfg_num)
if (fse->index >= ARRAY_SIZE(supported_modes))
return -EINVAL;
if (fse->code != GC2093_MEDIA_BUS_FMT)
@@ -1202,9 +1414,7 @@ static int gc2093_enum_frame_interval(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_frame_interval_enum *fie)
{
struct gc2093 *gc2093 = to_gc2093(sd);
if (fie->index >= gc2093->cfg_num)
if (fie->index >= ARRAY_SIZE(supported_modes))
return -EINVAL;
fie->code = GC2093_MEDIA_BUS_FMT;
@@ -1400,6 +1610,136 @@ static const struct dev_pm_ops gc2093_pm_ops = {
gc2093_runtime_resume, NULL)
};
#ifdef CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP
static u32 rk_cam_hdr;
static u32 rk_cam_w;
static u32 rk_cam_h;
static u32 rk_cam_fps;
static int __init __maybe_unused rk_cam_hdr_setup(char *str)
{
int ret = 0;
unsigned long val = 0;
ret = kstrtoul(str, 0, &val);
if (!ret)
rk_cam_hdr = (u32)val;
else
pr_err("get rk_cam_hdr fail\n");
return 1;
}
static int __init __maybe_unused rk_cam_w_setup(char *str)
{
int ret = 0;
unsigned long val = 0;
ret = kstrtoul(str, 0, &val);
if (!ret)
rk_cam_w = (u32)val;
else
pr_err("get rk_cam_w fail\n");
return 1;
}
static int __init __maybe_unused rk_cam_h_setup(char *str)
{
int ret = 0;
unsigned long val = 0;
ret = kstrtoul(str, 0, &val);
if (!ret)
rk_cam_h = (u32)val;
else
pr_err("get rk_cam_h fail\n");
return 1;
}
static int __init __maybe_unused rk_cam_fps_setup(char *str)
{
int ret = 0;
unsigned long val = 0;
ret = kstrtoul(str, 0, &val);
if (!ret)
rk_cam_fps = (u32)val;
else
pr_err("get rk_cam_fps fail\n");
return 1;
}
__setup("rk_cam_hdr=", rk_cam_hdr_setup);
__setup("rk_cam_w=", rk_cam_w_setup);
__setup("rk_cam_h=", rk_cam_h_setup);
__setup("rk_cam_fps=", rk_cam_fps_setup);
static void find_terminal_resolution(struct gc2093 *gc2093)
{
int i = 0;
const struct gc2093_mode *mode = NULL;
const struct gc2093_mode *fit_mode = NULL;
u32 cur_fps = 0;
u32 dst_fps = 0;
u32 tmp_fps = 0;
if (rk_cam_w == 0 || rk_cam_h == 0 ||
rk_cam_fps == 0)
goto err_find_res;
dev_info(gc2093->dev, "find resolution width: %d, height: %d, hdr: %d, fps: %d\n",
rk_cam_w, rk_cam_h, rk_cam_hdr, rk_cam_fps);
dst_fps = rk_cam_fps;
for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
mode = &supported_modes[i];
cur_fps = mode->max_fps.denominator / mode->max_fps.numerator;
if (mode->width == rk_cam_w && mode->height == rk_cam_h &&
mode->hdr_mode == rk_cam_hdr) {
if (cur_fps == dst_fps) {
gc2093->cur_mode = mode;
return;
}
if (cur_fps >= dst_fps) {
if (fit_mode) {
tmp_fps = fit_mode->max_fps.denominator /
fit_mode->max_fps.numerator;
if (tmp_fps - dst_fps > cur_fps - dst_fps)
fit_mode = mode;
} else {
fit_mode = mode;
}
}
}
}
if (fit_mode) {
gc2093->cur_mode = fit_mode;
return;
}
err_find_res:
dev_err(gc2093->dev, "not match %dx%d@%dfps mode %d\n!",
rk_cam_w, rk_cam_h, dst_fps, rk_cam_hdr);
gc2093->cur_mode = &supported_modes[0];
}
#else
static void find_terminal_resolution(struct gc2093 *gc2093)
{
u32 hdr_mode = 0;
struct device_node *node = gc2093->dev->of_node;
int i = 0;
of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
if (hdr_mode == supported_modes[i].hdr_mode) {
gc2093->cur_mode = &supported_modes[i];
break;
}
}
if (i == ARRAY_SIZE(supported_modes))
gc2093->cur_mode = &supported_modes[0];
}
#endif
static int gc2093_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
@@ -1447,6 +1787,8 @@ static int gc2093_probe(struct i2c_client *client,
return -EINVAL;
}
find_terminal_resolution(gc2093);
gc2093->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
if (IS_ERR(gc2093->reset_gpio))
dev_warn(dev, "Failed to get reset-gpios\n");
@@ -1463,11 +1805,6 @@ static int gc2093_probe(struct i2c_client *client,
mutex_init(&gc2093->lock);
/* set default mode */
gc2093->cur_mode = &supported_modes[0];
gc2093->cfg_num = ARRAY_SIZE(supported_modes);
gc2093->cur_vts = gc2093->cur_mode->vts_def;
sd = &gc2093->subdev;
v4l2_i2c_subdev_init(sd, client, &gc2093_subdev_ops);
ret = gc2093_initialize_controls(gc2093);