diff --git a/drivers/video/rockchip/rga3/include/rga2_reg_info.h b/drivers/video/rockchip/rga3/include/rga2_reg_info.h
index 37afb7640f8a..66c467d4df46 100644
--- a/drivers/video/rockchip/rga3/include/rga2_reg_info.h
+++ b/drivers/video/rockchip/rga3/include/rga2_reg_info.h
@@ -41,19 +41,6 @@
 #define RGA2_OSD_CUR_FLAGS0			0x090
 #define RGA2_OSD_CUR_FLAGS1			0x09c
 
-/* iommu reg */
-#define RGA2_MMU_DTE_ADDR			0xf00
-#define RGA2_MMU_STATUS				0xf04
-#define RGA2_MMU_COMMAND			0xf08
-#define RGA2_MMU_PAGE_FAULT_ADDR		0xf0c
-#define RGA2_MMU_ZAP_ONE_LINE			0xf10
-#define RGA2_MMU_INT_RAWSTAT			0xf14
-#define RGA2_MMU_INT_CLEAR			0xf18
-#define RGA2_MMU_INT_MASK			0xf1c
-#define RGA2_MMU_INT_STATUS			0xf20
-#define RGA2_MMU_AUTO_GATING			0xf24
-#define RGA2_MMU_REG_LOAD_EN			0xf28
-
 /* mode ctrl */
 #define RGA2_MODE_CTRL_OFFSET			0x000
 #define RGA2_SRC_INFO_OFFSET			0x004
diff --git a/drivers/video/rockchip/rga3/include/rga3_reg_info.h b/drivers/video/rockchip/rga3/include/rga3_reg_info.h
index 78baf74460e8..88d05a5beccb 100644
--- a/drivers/video/rockchip/rga3/include/rga3_reg_info.h
+++ b/drivers/video/rockchip/rga3/include/rga3_reg_info.h
@@ -21,19 +21,6 @@
 #define RGA3_SCAN_CNT				0x038
 #define RGA3_CMD_STATE				0x040
 
-/* iommu reg */
-#define RGA3_MMU_DTE_ADDR			0xf00
-#define RGA3_MMU_STATUS				0xf04
-#define RGA3_MMU_COMMAND			0xf08
-#define RGA3_MMU_PAGE_FAULT_ADDR		0xf0c
-#define RGA3_MMU_ZAP_ONE_LINE			0xf10
-#define RGA3_MMU_INT_RAWSTAT			0xf14
-#define RGA3_MMU_INT_CLEAR			0xf18
-#define RGA3_MMU_INT_MASK			0xf1c
-#define RGA3_MMU_INT_STATUS			0xf20
-#define RGA3_MMU_AUTO_GATING			0xf24
-#define RGA3_MMU_REG_LOAD_EN			0xf28
-
 /* cmd reg */
 #define RGA3_WIN0_RD_CTRL_OFFSET		0x000
 #define RGA3_WIN0_Y_BASE_OFFSET			0x010
@@ -152,6 +139,9 @@
 #define m_RGA3_CMD_CTRL_CMD_INCR_VALID_P			(0x1 << 1)
 #define m_RGA3_CMD_CTRL_CMD_LINE_ST_P				(0x1 << 0)
 
+/* RGA3_RO_SRST */
+#define m_RGA3_RO_SRST_RO_RST_DONE				(0x3f << 0)
+
 /* RGA3_CMD_STATE */
 #define m_RGA3_CMD_STATE_CMD_CNT_CUR				(0xfff << 16)
 #define m_RGA3_CMD_STATE_CMD_WORKING				(0x1 << 0)
diff --git a/drivers/video/rockchip/rga3/include/rga_iommu.h b/drivers/video/rockchip/rga3/include/rga_iommu.h
index 5654cfd4b59c..b80a1f48bb25 100644
--- a/drivers/video/rockchip/rga3/include/rga_iommu.h
+++ b/drivers/video/rockchip/rga3/include/rga_iommu.h
@@ -4,10 +4,41 @@
 
 #include "rga_drv.h"
 
+/* RGA_IOMMU register offsets */
+#define RGA_IOMMU_BASE				0xf00
+#define RGA_IOMMU_DTE_ADDR			(RGA_IOMMU_BASE + 0x00) /* Directory table address */
+#define RGA_IOMMU_STATUS			(RGA_IOMMU_BASE + 0x04)
+#define RGA_IOMMU_COMMAND			(RGA_IOMMU_BASE + 0x08)
+#define RGA_IOMMU_PAGE_FAULT_ADDR		(RGA_IOMMU_BASE + 0x0C) /* IOVA of last page fault */
+#define RGA_IOMMU_ZAP_ONE_LINE			(RGA_IOMMU_BASE + 0x10) /* Shootdown one IOTLB entry */
+#define RGA_IOMMU_INT_RAWSTAT			(RGA_IOMMU_BASE + 0x14) /* IRQ status ignoring mask */
+#define RGA_IOMMU_INT_CLEAR			(RGA_IOMMU_BASE + 0x18) /* Acknowledge and re-arm irq */
+#define RGA_IOMMU_INT_MASK			(RGA_IOMMU_BASE + 0x1C) /* IRQ enable */
+#define RGA_IOMMU_INT_STATUS			(RGA_IOMMU_BASE + 0x20) /* IRQ status after masking */
+#define RGA_IOMMU_AUTO_GATING			(RGA_IOMMU_BASE + 0x24)
+
+/* RGA_IOMMU_STATUS fields */
+#define RGA_IOMMU_STATUS_PAGING_ENABLED		BIT(0)
+#define RGA_IOMMU_STATUS_PAGE_FAULT_ACTIVE	BIT(1)
+#define RGA_IOMMU_STATUS_STALL_ACTIVE		BIT(2)
+#define RGA_IOMMU_STATUS_IDLE			BIT(3)
+#define RGA_IOMMU_STATUS_REPLAY_BUFFER_EMPTY	BIT(4)
+#define RGA_IOMMU_STATUS_PAGE_FAULT_IS_WRITE	BIT(5)
+#define RGA_IOMMU_STATUS_STALL_NOT_ACTIVE	BIT(31)
+
+/* RGA_IOMMU_COMMAND command values */
+#define RGA_IOMMU_CMD_ENABLE_PAGING		0 /* Enable memory translation */
+#define RGA_IOMMU_CMD_DISABLE_PAGING		1 /* Disable memory translation */
+#define RGA_IOMMU_CMD_ENABLE_STALL		2 /* Stall paging to allow other cmds */
+#define RGA_IOMMU_CMD_DISABLE_STALL		3 /* Stop stall re-enables paging */
+#define RGA_IOMMU_CMD_ZAP_CACHE			4 /* Shoot down entire IOTLB */
+#define RGA_IOMMU_CMD_PAGE_FAULT_DONE		5 /* Clear page fault */
+#define RGA_IOMMU_CMD_FORCE_RESET		6 /* Reset all registers */
+
 /* RGA_IOMMU_INT_* register fields */
-#define RGA_IOMMU_IRQ_PAGE_FAULT    0x01  /* page fault */
-#define RGA_IOMMU_IRQ_BUS_ERROR     0x02  /* bus read error */
-#define RGA_IOMMU_IRQ_MASK          (RGA_IOMMU_IRQ_PAGE_FAULT | RGA_IOMMU_IRQ_BUS_ERROR)
+#define RGA_IOMMU_IRQ_PAGE_FAULT		0x01 /* page fault */
+#define RGA_IOMMU_IRQ_BUS_ERROR			0x02 /* bus read error */
+#define RGA_IOMMU_IRQ_MASK			(RGA_IOMMU_IRQ_PAGE_FAULT | RGA_IOMMU_IRQ_BUS_ERROR)
 
 /*
  * The maximum input is 8192*8192, the maximum output is 4096*4096
diff --git a/drivers/video/rockchip/rga3/rga2_reg_info.c b/drivers/video/rockchip/rga3/rga2_reg_info.c
index 2465b86466bd..c95ea04be224 100644
--- a/drivers/video/rockchip/rga3/rga2_reg_info.c
+++ b/drivers/video/rockchip/rga3/rga2_reg_info.c
@@ -2062,7 +2062,7 @@ static void rga2_soft_reset(struct rga_scheduler_t *scheduler)
 	u32 iommu_dte_addr;
 
 	if (scheduler->data->mmu == RGA_IOMMU)
-		iommu_dte_addr = rga_read(0xf00, scheduler);
+		iommu_dte_addr = rga_read(RGA_IOMMU_DTE_ADDR, scheduler);
 
 	rga_write(m_RGA2_SYS_CTRL_ACLK_SRESET_P | m_RGA2_SYS_CTRL_CCLK_SRESET_P |
 		  m_RGA2_SYS_CTRL_RST_PROTECT_P,
@@ -2079,13 +2079,16 @@ static void rga2_soft_reset(struct rga_scheduler_t *scheduler)
 	}
 
 	if (scheduler->data->mmu == RGA_IOMMU) {
-		rga_write(iommu_dte_addr, RGA2_MMU_DTE_ADDR, scheduler);
+		rga_write(iommu_dte_addr, RGA_IOMMU_DTE_ADDR, scheduler);
 		/* enable iommu */
-		rga_write(0, RGA2_MMU_COMMAND, scheduler);
+		rga_write(RGA_IOMMU_CMD_ENABLE_PAGING, RGA_IOMMU_COMMAND, scheduler);
 	}
 
 	if (i == RGA_RESET_TIMEOUT)
-		pr_err("soft reset timeout.\n");
+		pr_err("RAG2 soft reset timeout.\n");
+	else
+		pr_info("RGA2 soft reset complete.\n");
+
 }
 
 static int rga2_check_param(const struct rga_hw_data *data, const struct rga2_req *req)
diff --git a/drivers/video/rockchip/rga3/rga3_reg_info.c b/drivers/video/rockchip/rga3/rga3_reg_info.c
index 1b3d7e2f7ad6..bc9fa49baa45 100644
--- a/drivers/video/rockchip/rga3/rga3_reg_info.c
+++ b/drivers/video/rockchip/rga3/rga3_reg_info.c
@@ -9,6 +9,7 @@
 
 #include "rga3_reg_info.h"
 #include "rga_dma_buf.h"
+#include "rga_iommu.h"
 #include "rga_common.h"
 #include "rga_debugger.h"
 #include "rga_hw_config.h"
@@ -1593,54 +1594,35 @@ static void rga_cmd_to_rga3_cmd(struct rga_req *req_rga, struct rga3_req *req)
 static void rga3_soft_reset(struct rga_scheduler_t *scheduler)
 {
 	u32 i;
-	u32 reg;
-	u32 mmu_addr;
+	u32 iommu_dte_addr;
 
-	mmu_addr = rga_read(0xf00, scheduler);
+	if (scheduler->data->mmu == RGA_IOMMU)
+		iommu_dte_addr = rga_read(RGA_IOMMU_DTE_ADDR, scheduler);
 
 	rga_write(s_RGA3_SYS_CTRL_CCLK_SRESET(1) | s_RGA3_SYS_CTRL_ACLK_SRESET(1),
 		  RGA3_SYS_CTRL, scheduler);
 
-	pr_err("soft reset sys_ctrl = %x, ro_rest = %x",
-		rga_read(RGA3_SYS_CTRL, scheduler),
-		rga_read(RGA3_RO_SRST, scheduler));
-
-	mdelay(20);
-
-	pr_err("soft reset sys_ctrl = %x, ro_rest = %x",
-		rga_read(RGA3_SYS_CTRL, scheduler),
-		rga_read(RGA3_RO_SRST, scheduler));
-
-	rga_write(s_RGA3_SYS_CTRL_CCLK_SRESET(0) | s_RGA3_SYS_CTRL_ACLK_SRESET(0),
-		  RGA3_SYS_CTRL, scheduler);
-
-	pr_err("soft after reset sys_ctrl = %x, ro_rest = %x",
-		rga_read(RGA3_SYS_CTRL, scheduler),
-		rga_read(RGA3_RO_SRST, scheduler));
-
-	rga_write(m_RGA3_INT_FRM_DONE | m_RGA3_INT_CMD_LINE_FINISH | m_RGA3_INT_ERROR_MASK,
-		  RGA3_INT_CLR, scheduler);
-
-	rga_write(mmu_addr, RGA3_MMU_DTE_ADDR, scheduler);
-	rga_write(0, RGA3_MMU_COMMAND, scheduler);
-
-	if (DEBUGGER_EN(INT_FLAG))
-		pr_info("soft reset, INTR[0x%x], HW_STATUS[0x%x], CMD_STATUS[0x%x]\n",
-			rga_read(RGA3_INT_RAW, scheduler),
-			rga_read(RGA3_STATUS0, scheduler),
-			rga_read(RGA3_CMD_STATE, scheduler));
-
 	for (i = 0; i < RGA_RESET_TIMEOUT; i++) {
-		reg = rga_read(RGA3_SYS_CTRL, scheduler) & 1;
-
-		if (reg == 0)
+		if (rga_read(RGA3_RO_SRST, scheduler) & m_RGA3_RO_SRST_RO_RST_DONE)
 			break;
 
 		udelay(1);
 	}
 
+	rga_write(s_RGA3_SYS_CTRL_CCLK_SRESET(0) | s_RGA3_SYS_CTRL_ACLK_SRESET(0),
+		  RGA3_SYS_CTRL, scheduler);
+
+	if (scheduler->data->mmu == RGA_IOMMU) {
+		rga_write(iommu_dte_addr, RGA_IOMMU_DTE_ADDR, scheduler);
+		/* enable iommu */
+		rga_write(RGA_IOMMU_CMD_ENABLE_PAGING, RGA_IOMMU_COMMAND, scheduler);
+	}
+
 	if (i == RGA_RESET_TIMEOUT)
-		pr_err("soft reset timeout.\n");
+		pr_err("RGA3 soft reset timeout. SYS_CTRL[0x%x], RO_SRST[0x%x]\n",
+		       rga_read(RGA3_SYS_CTRL, scheduler), rga_read(RGA3_RO_SRST, scheduler));
+	else
+		pr_info("RGA3 soft reset complete.\n");
 }
 
 static int rga3_scale_check(const struct rga3_req *req)